PGMAllBth.h@ 96962

Last change on this file since 96962 was 96958, checked in by vboxsync, 2 years ago
VMM/PGM: Made the APIC access page related optimizations for nested VMs configurable via PGM_WITH_NESTED_APIC_ACCESS_PAGE define in PGMInternal.h, leaving it disabled for now till things are working. bugref:10092
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1	/* $Id: PGMAllBth.h 96958 2022-09-30 21:15:44Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
15	*
16	* This file is part of VirtualBox base platform packages, as
17	* available from https://www.virtualbox.org.
18	*
19	* This program is free software; you can redistribute it and/or
20	* modify it under the terms of the GNU General Public License
21	* as published by the Free Software Foundation, in version 3 of the
22	* License.
23	*
24	* This program is distributed in the hope that it will be useful, but
25	* WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27	* General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, see <https://www.gnu.org/licenses>.
31	*
32	* SPDX-License-Identifier: GPL-3.0-only
33	*/
34
35	#ifdef _MSC_VER
36	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
37	* real/prot-guest+RC mode. */
38	# pragma warning(disable: 4505)
39	#endif
40
41
42	/*********************************************************************************************************************************
43	* Internal Functions *
44	*********************************************************************************************************************************/
45	RT_C_DECLS_BEGIN
46	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
47	#ifndef IN_RING3
48	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
49	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNestedFault,
50	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken);
51	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
52	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
53	unsigned iPte, PPGMPTWALKGST pGstWalkAll);
54	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
55	uint32_t uErr, PPGMPTWALKGST pGstWalkAll);
56	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll);
57	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
58	#endif
59	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
60	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
61	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
62	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
63	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
64	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
65	#else
66	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
67	#endif
68	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
69	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
70	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
71	#ifdef VBOX_STRICT
72	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
73	#endif
74	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
75	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
76
77	#ifdef IN_RING3
78	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
79	#endif
80	RT_C_DECLS_END
81
82
83
84
85	/*
86	* Filter out some illegal combinations of guest and shadow paging, so we can
87	* remove redundant checks inside functions.
88	*/
89	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
90	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
91	# error "Invalid combination; PAE guest implies PAE shadow"
92	#endif
93
94	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
95	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
96	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
97	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
98	#endif
99
100	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
101	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
102	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
103	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
104	#endif
105
106	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
107	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
108	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
109	#endif
110
111
112	/**
113	* Enters the shadow+guest mode.
114	*
115	* @returns VBox status code.
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param GCPhysCR3 The physical address from the CR3 register.
118	*/
119	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
120	{
121	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
122	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
123	*/
124	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
125	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
126	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
127	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
128	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
129
130	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
131
132	Assert(!pVM->pgm.s.fNestedPaging);
133
134	PGM_LOCK_VOID(pVM);
135	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
136	* but any calls to GC need a proper shadow page setup as well.
137	*/
138	/* Free the previous root mapping if still active. */
139	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
140	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
141	if (pOldShwPageCR3)
142	{
143	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
144
145	/* Mark the page as unlocked; allow flushing again. */
146	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
147
148	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
149	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
150	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
151	}
152
153	/* construct a fake address. */
154	GCPhysCR3 = RT_BIT_64(63);
155	PPGMPOOLPAGE pNewShwPageCR3;
156	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
157	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
158	&pNewShwPageCR3);
159	AssertRCReturn(rc, rc);
160
161	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
162	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
163
164	/* Mark the page as locked; disallow flushing. */
165	pgmPoolLockPage(pPool, pNewShwPageCR3);
166
167	/* Set the current hypervisor CR3. */
168	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
169
170	PGM_UNLOCK(pVM);
171	return rc;
172	#else
173	NOREF(pVCpu); NOREF(GCPhysCR3);
174	return VINF_SUCCESS;
175	#endif
176	}
177
178
179	#ifndef IN_RING3
180
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	/**
183	* Deal with a guest page fault.
184	*
185	* @returns Strict VBox status code.
186	* @retval VINF_EM_RAW_GUEST_TRAP
187	* @retval VINF_EM_RAW_EMULATE_INSTR
188	*
189	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
190	* @param pWalk The guest page table walk result.
191	* @param uErr The error code.
192	*/
193	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, RTGCUINT uErr)
194	{
195	/*
196	* Calc the error code for the guest trap.
197	*/
198	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
199	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
200	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
201	if ( pWalk->fRsvdError
202	\|\| pWalk->fBadPhysAddr)
203	{
204	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
205	Assert(!pWalk->fNotPresent);
206	}
207	else if (!pWalk->fNotPresent)
208	uNewErr \|= X86_TRAP_PF_P;
209	TRPMSetErrorCode(pVCpu, uNewErr);
210
211	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pWalk->GCPtr, uErr, pWalk->uLevel));
212	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
213	return VINF_EM_RAW_GUEST_TRAP;
214	}
215	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
216
217
218	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
219	/**
220	* Deal with a guest page fault.
221	*
222	* The caller has taken the PGM lock.
223	*
224	* @returns Strict VBox status code.
225	*
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param uErr The error code.
228	* @param pRegFrame The register frame.
229	* @param pvFault The fault address.
230	* @param pPage The guest page at @a pvFault.
231	* @param pWalk The guest page table walk result.
232	* @param pGstWalk The guest paging-mode specific walk information.
233	* @param pfLockTaken PGM lock taken here or not (out). This is true
234	* when we're called.
235	*/
236	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
237	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
238	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
239	, PPGMPTWALK pWalk
240	, PGSTPTWALK pGstWalk
241	# endif
242	)
243	{
244	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
245	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
246	# endif
247	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
248	VBOXSTRICTRC rcStrict;
249
250	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
251	{
252	/*
253	* Physical page access handler.
254	*/
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	const RTGCPHYS GCPhysFault = pWalk->GCPhys;
257	# else
258	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
259	# endif
260	PPGMPHYSHANDLER pCur;
261	rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysFault, &pCur);
262	if (RT_SUCCESS(rcStrict))
263	{
264	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
265
266	# ifdef PGM_SYNC_N_PAGES
267	/*
268	* If the region is write protected and we got a page not present fault, then sync
269	* the pages. If the fault was caused by a read, then restart the instruction.
270	* In case of write access continue to the GC write handler.
271	*
272	* ASSUMES that there is only one handler per page or that they have similar write properties.
273	*/
274	if ( !(uErr & X86_TRAP_PF_P)
275	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
276	{
277	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
278	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
279	# else
280	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
281	# endif
282	if ( RT_FAILURE(rcStrict)
283	\|\| !(uErr & X86_TRAP_PF_RW)
284	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
285	{
286	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
288	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
289	return rcStrict;
290	}
291	}
292	# endif
293	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
294	/*
295	* If the access was not thru a #PF(RSVD\|...) resync the page.
296	*/
297	if ( !(uErr & X86_TRAP_PF_RSVD)
298	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
299	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
300	&& (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
301	== PGM_PTATTRS_W_MASK /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
302	# endif
303	)
304	{
305	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
306	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
307	# else
308	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
309	# endif
310	if ( RT_FAILURE(rcStrict)
311	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
312	{
313	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
314	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
315	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
316	return rcStrict;
317	}
318	}
319	# endif
320
321	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
322	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
323	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
324	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
325	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
326	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
327	else
328	{
329	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
330	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
331	}
332
333	if (pCurType->pfnPfHandler)
334	{
335	STAM_PROFILE_START(&pCur->Stat, h);
336
337	if (pCurType->fKeepPgmLock)
338	{
339	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault,
340	!pCurType->fRing0DevInsIdx ? pCur->uUser
341	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser));
342
343	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
344	}
345	else
346	{
347	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
348	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
349	PGM_UNLOCK(pVM);
350	*pfLockTaken = false;
351
352	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, uUser);
353
354	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
355	}
356	}
357	else
358	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
359
360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
361	return rcStrict;
362	}
363	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
364	}
365
366	/*
367	* There is a handled area of the page, but this fault doesn't belong to it.
368	* We must emulate the instruction.
369	*
370	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
371	* we first check if this was a page-not-present fault for a page with only
372	* write access handlers. Restart the instruction if it wasn't a write access.
373	*/
374	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersUnhandled);
375
376	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
377	&& !(uErr & X86_TRAP_PF_P))
378	{
379	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
380	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
381	# else
382	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
383	# endif
384	if ( RT_FAILURE(rcStrict)
385	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
386	\|\| !(uErr & X86_TRAP_PF_RW))
387	{
388	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
389	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
390	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
391	return rcStrict;
392	}
393	}
394
395	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
396	* It's writing to an unhandled part of the LDT page several million times.
397	*/
398	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
399	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
400	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
401	return rcStrict;
402	} /* if any kind of handler */
403	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
404
405
406	/**
407	* \#PF Handler for raw-mode guest execution.
408	*
409	* @returns VBox status code (appropriate for trap handling and GC return).
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param uErr The trap error code.
413	* @param pRegFrame Trap register frame.
414	* @param pvFault The fault address.
415	* @param pfLockTaken PGM lock taken here or not (out)
416	*/
417	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
418	{
419	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
420
421	*pfLockTaken = false;
422
423	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
424	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
425	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
426	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
427	&& PGM_SHW_TYPE != PGM_TYPE_NONE
428	int rc;
429
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	/*
432	* Walk the guest page translation tables and check if it's a guest fault.
433	*/
434	PGMPTWALK Walk;
435	GSTPTWALK GstWalk;
436	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &Walk, &GstWalk);
437	if (RT_FAILURE_NP(rc))
438	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
439
440	/* assert some GstWalk sanity. */
441	# if PGM_GST_TYPE == PGM_TYPE_AMD64
442	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
443	# endif
444	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
445	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
446	# endif
447	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
448	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
449	Assert(Walk.fSucceeded);
450	Assert(Walk.fEffective & PGM_PTATTRS_R_MASK);
451
452	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
453	{
454	if ( ( (uErr & X86_TRAP_PF_RW)
455	&& !(Walk.fEffective & PGM_PTATTRS_W_MASK)
456	&& ( (uErr & X86_TRAP_PF_US)
457	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
458	\|\| ((uErr & X86_TRAP_PF_US) && !(Walk.fEffective & PGM_PTATTRS_US_MASK))
459	\|\| ((uErr & X86_TRAP_PF_ID) && (Walk.fEffective & PGM_PTATTRS_NX_MASK))
460	)
461	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
462	}
463
464	/* Take the big lock now before we update flags. */
465	*pfLockTaken = true;
466	PGM_LOCK_VOID(pVM);
467
468	/*
469	* Set the accessed and dirty flags.
470	*/
471	/** @todo Should probably use cmpxchg logic here as we're potentially racing
472	* other CPUs in SMP configs. (the lock isn't enough, since we take it
473	* after walking and the page tables could be stale already) */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	if (!(GstWalk.Pml4e.u & X86_PML4E_A))
476	{
477	GstWalk.Pml4e.u \|= X86_PML4E_A;
478	GST_ATOMIC_OR(&GstWalk.pPml4e->u, X86_PML4E_A);
479	}
480	if (!(GstWalk.Pdpe.u & X86_PDPE_A))
481	{
482	GstWalk.Pdpe.u \|= X86_PDPE_A;
483	GST_ATOMIC_OR(&GstWalk.pPdpe->u, X86_PDPE_A);
484	}
485	# endif
486	if (Walk.fBigPage)
487	{
488	Assert(GstWalk.Pde.u & X86_PDE_PS);
489	if (uErr & X86_TRAP_PF_RW)
490	{
491	if ((GstWalk.Pde.u & (X86_PDE4M_A \| X86_PDE4M_D)) != (X86_PDE4M_A \| X86_PDE4M_D))
492	{
493	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
494	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A \| X86_PDE4M_D);
495	}
496	}
497	else
498	{
499	if (!(GstWalk.Pde.u & X86_PDE4M_A))
500	{
501	GstWalk.Pde.u \|= X86_PDE4M_A;
502	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A);
503	}
504	}
505	}
506	else
507	{
508	Assert(!(GstWalk.Pde.u & X86_PDE_PS));
509	if (!(GstWalk.Pde.u & X86_PDE_A))
510	{
511	GstWalk.Pde.u \|= X86_PDE_A;
512	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE_A);
513	}
514
515	if (uErr & X86_TRAP_PF_RW)
516	{
517	# ifdef VBOX_WITH_STATISTICS
518	if (GstWalk.Pte.u & X86_PTE_D)
519	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageAlreadyDirty));
520	else
521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtiedPage));
522	# endif
523	if ((GstWalk.Pte.u & (X86_PTE_A \| X86_PTE_D)) != (X86_PTE_A \| X86_PTE_D))
524	{
525	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
526	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A \| X86_PTE_D);
527	}
528	}
529	else
530	{
531	if (!(GstWalk.Pte.u & X86_PTE_A))
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A);
535	}
536	}
537	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538	}
539	#if 0
540	/* Disabling this since it's not reliable for SMP, see @bugref{10092#c22}. */
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	#endif
544
545	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	PGM_LOCK_VOID(pVM);
551	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
554	/*
555	* If it is a reserved bit fault we know that it is an MMIO (access
556	* handler) related fault and can skip some 200 lines of code.
557	*/
558	if (uErr & X86_TRAP_PF_RSVD)
559	{
560	Assert(uErr & X86_TRAP_PF_P);
561	PPGMPAGE pPage;
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
566	pfLockTaken, &Walk, &GstWalk));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
568	# else
569	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
570	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
571	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
572	pfLockTaken));
573	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
574	# endif
575	AssertRC(rc);
576	PGM_INVL_PG(pVCpu, pvFault);
577	return rc; /* Restart with the corrected entry. */
578	}
579	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
580
581	/*
582	* Fetch the guest PDE, PDPE and PML4E.
583	*/
584	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
585	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
586	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
587
588	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
589	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
590	PX86PDPAE pPDDst;
591	# if PGM_GST_TYPE == PGM_TYPE_PAE
592	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
593	# else
594	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
595	# endif
596	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
597
598	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
599	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
600	PX86PDPAE pPDDst;
601	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
602	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
603	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
604	# else
605	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
606	# endif
607	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
608
609	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
610	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
611	PEPTPD pPDDst;
612	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
613	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
614	# endif
615	Assert(pPDDst);
616
617	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
618	/*
619	* Dirty page handling.
620	*
621	* If we successfully correct the write protection fault due to dirty bit
622	* tracking, then return immediately.
623	*/
624	if (uErr & X86_TRAP_PF_RW) /* write fault? */
625	{
626	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
627	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
628	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
629	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
630	{
631	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0
632	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
633	? &pVCpu->pgm.s.Stats.StatRZTrap0eTime2DirtyAndAccessed
634	: &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
635	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
636	return VINF_SUCCESS;
637	}
638	#ifdef DEBUG_bird
639	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
640	AssertMsg(Walk.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
641	#endif
642	}
643
644	# if 0 /* rarely useful; leave for debugging. */
645	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
646	# endif
647	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
648
649	/*
650	* A common case is the not-present error caused by lazy page table syncing.
651	*
652	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
653	* here so we can safely assume that the shadow PT is present when calling
654	* SyncPage later.
655	*
656	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
657	* of mapping conflict and defer to SyncCR3 in R3.
658	* (Again, we do NOT support access handlers for non-present guest pages.)
659	*
660	*/
661	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
662	Assert(GstWalk.Pde.u & X86_PDE_P);
663	# endif
664	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
665	&& !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
666	{
667	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
668	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
669	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
670	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
671	# else
672	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
673	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
674	# endif
675	if (RT_SUCCESS(rc))
676	return rc;
677	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
678	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
679	return VINF_PGM_SYNC_CR3;
680	}
681
682	/*
683	* Check if this fault address is flagged for special treatment,
684	* which means we'll have to figure out the physical address and
685	* check flags associated with it.
686	*
687	* ASSUME that we can limit any special access handling to pages
688	* in page tables which the guest believes to be present.
689	*/
690	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
691	RTGCPHYS GCPhys = Walk.GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
692	# else
693	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK);
694	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
695	PPGMPAGE pPage;
696	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
697	if (RT_FAILURE(rc))
698	{
699	/*
700	* When the guest accesses invalid physical memory (e.g. probing
701	* of RAM or accessing a remapped MMIO range), then we'll fall
702	* back to the recompiler to emulate the instruction.
703	*/
704	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
705	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
706	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
707	return VINF_EM_RAW_EMULATE_INSTR;
708	}
709
710	/*
711	* Any handlers for this page?
712	*/
713	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
714	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
715	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
716	&Walk, &GstWalk));
717	# else
718	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
719	# endif
720
721	/*
722	* We are here only if page is present in Guest page tables and
723	* trap is not handled by our handlers.
724	*
725	* Check it for page out-of-sync situation.
726	*/
727	if (!(uErr & X86_TRAP_PF_P))
728	{
729	/*
730	* Page is not present in our page tables. Try to sync it!
731	*/
732	if (uErr & X86_TRAP_PF_US)
733	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
734	else /* supervisor */
735	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
736
737	if (PGM_PAGE_IS_BALLOONED(pPage))
738	{
739	/* Emulate reads from ballooned pages as they are not present in
740	our shadow page tables. (Required for e.g. Solaris guests; soft
741	ecc, random nr generator.) */
742	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
743	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
744	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
745	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Ballooned; });
746	return rc;
747	}
748
749	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
750	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
751	# else
752	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
753	# endif
754	if (RT_SUCCESS(rc))
755	{
756	/* The page was successfully synced, return to the guest. */
757	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
758	return VINF_SUCCESS;
759	}
760	}
761	else /* uErr & X86_TRAP_PF_P: */
762	{
763	/*
764	* Write protected pages are made writable when the guest makes the
765	* first write to it. This happens for pages that are shared, write
766	* monitored or not yet allocated.
767	*
768	* We may also end up here when CR0.WP=0 in the guest.
769	*
770	* Also, a side effect of not flushing global PDEs are out of sync
771	* pages due to physical monitored regions, that are no longer valid.
772	* Assume for now it only applies to the read/write flag.
773	*/
774	if (uErr & X86_TRAP_PF_RW)
775	{
776	/*
777	* Check if it is a read-only page.
778	*/
779	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
780	{
781	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
782	Assert(!PGM_PAGE_IS_ZERO(pPage));
783	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
784	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
785
786	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
787	if (rc != VINF_SUCCESS)
788	{
789	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
790	return rc;
791	}
792	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
793	return VINF_EM_NO_MEMORY;
794	}
795
796	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
797	/*
798	* Check to see if we need to emulate the instruction if CR0.WP=0.
799	*/
800	if ( !(Walk.fEffective & PGM_PTATTRS_W_MASK)
801	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
802	&& CPUMGetGuestCPL(pVCpu) < 3)
803	{
804	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
805
806	/*
807	* The Netware WP0+RO+US hack.
808	*
809	* Netware sometimes(/always?) runs with WP0. It has been observed doing
810	* excessive write accesses to pages which are mapped with US=1 and RW=0
811	* while WP=0. This causes a lot of exits and extremely slow execution.
812	* To avoid trapping and emulating every write here, we change the shadow
813	* page table entry to map it as US=0 and RW=1 until user mode tries to
814	* access it again (see further below). We count these shadow page table
815	* changes so we can avoid having to clear the page pool every time the WP
816	* bit changes to 1 (see PGMCr0WpEnabled()).
817	*/
818	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
819	if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
820	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
821	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
822	{
823	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, Walk.fBigPage));
824	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, Walk.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
825	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
826	{
827	PGM_INVL_PG(pVCpu, pvFault);
828	pVCpu->pgm.s.cNetwareWp0Hacks++;
829	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsHack; });
830	return rc;
831	}
832	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
833	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
834	}
835	# endif
836
837	/* Interpret the access. */
838	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
839	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
840	if (RT_SUCCESS(rc))
841	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulInRZ);
842	else
843	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulToR3);
844	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2WPEmulation; });
845	return rc;
846	}
847	# endif
848	/// @todo count the above case; else
849	if (uErr & X86_TRAP_PF_US)
850	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
851	else /* supervisor */
852	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
853
854	/*
855	* Sync the page.
856	*
857	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
858	* page is not present, which is not true in this case.
859	*/
860	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
861	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
862	# else
863	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
864	# endif
865	if (RT_SUCCESS(rc))
866	{
867	/*
868	* Page was successfully synced, return to guest but invalidate
869	* the TLB first as the page is very likely to be in it.
870	*/
871	# if PGM_SHW_TYPE == PGM_TYPE_EPT
872	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
873	# else
874	PGM_INVL_PG(pVCpu, pvFault);
875	# endif
876	# ifdef VBOX_STRICT
877	PGMPTWALK GstPageWalk;
878	GstPageWalk.GCPhys = RTGCPHYS_MAX;
879	if (!pVM->pgm.s.fNestedPaging)
880	{
881	rc = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
882	AssertMsg(RT_SUCCESS(rc) && ((GstPageWalk.fEffective & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, GstPageWalk.fEffective));
883	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GstPageWalk.GCPhys, GstPageWalk.fEffective));
884	}
885	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
886	uint64_t fPageShw = 0;
887	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
888	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
889	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GstPageWalk.GCPhys, fPageGst, pvFault));
890	# endif
891	# endif /* VBOX_STRICT */
892	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
893	return VINF_SUCCESS;
894	}
895	}
896	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
897	/*
898	* Check for Netware WP0+RO+US hack from above and undo it when user
899	* mode accesses the page again.
900	*/
901	else if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
902	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
903	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
904	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
905	&& CPUMGetGuestCPL(pVCpu) == 3
906	&& pVM->cCpus == 1
907	)
908	{
909	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
910	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
911	if (RT_SUCCESS(rc))
912	{
913	PGM_INVL_PG(pVCpu, pvFault);
914	pVCpu->pgm.s.cNetwareWp0Hacks--;
915	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsUnhack; });
916	return VINF_SUCCESS;
917	}
918	}
919	# endif /* PGM_WITH_PAGING */
920
921	/** @todo else: why are we here? */
922
923	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
924	/*
925	* Check for VMM page flags vs. Guest page flags consistency.
926	* Currently only for debug purposes.
927	*/
928	if (RT_SUCCESS(rc))
929	{
930	/* Get guest page flags. */
931	PGMPTWALK GstPageWalk;
932	int rc2 = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
933	if (RT_SUCCESS(rc2))
934	{
935	uint64_t fPageShw = 0;
936	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
937
938	#if 0
939	/*
940	* Compare page flags.
941	* Note: we have AVL, A, D bits desynced.
942	*/
943	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
944	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
945	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
946	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
947	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
948	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
949	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
950	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
951	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
952	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
953	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
954
955	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
956	01:01:15.625516 00:08:43.268051 Location :
957	e:\vbox\svn\trunk\srcPage flags mismatch!
958	pvFault=fffff801b0d7b000
959	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
960	GCPhys=0000000019b52000
961	fPageShw=0
962	fPageGst=77b0000000000121
963	rc=0
964	#endif
965
966	}
967	else
968	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
969	}
970	else
971	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
972	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
973	}
974
975
976	/*
977	* If we get here it is because something failed above, i.e. most like guru
978	* meditiation time.
979	*/
980	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
981	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
982	return rc;
983
984	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
985	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
986	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
987	return VERR_PGM_NOT_USED_IN_MODE;
988	# endif
989	}
990
991
992	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT)
993	/**
994	* Deals with a nested-guest \#PF fault for a guest-physical page with a handler.
995	*
996	* @returns Strict VBox status code.
997	* @param pVCpu The cross context virtual CPU structure.
998	* @param uErr The error code.
999	* @param pRegFrame The register frame.
1000	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1001	* @param pPage The guest page at @a GCPhysNestedFault.
1002	* @param GCPhysFault The guest-physical address of the fault.
1003	* @param pGstWalkAll The guest page walk result.
1004	* @param pfLockTaken Where to store whether the PGM is still held when
1005	* this function completes.
1006	*
1007	* @note The caller has taken the PGM lock.
1008	*/
1009	static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
1010	RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage,
1011	RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll,
1012	bool *pfLockTaken)
1013	{
1014	# if PGM_GST_TYPE == PGM_TYPE_PROT \
1015	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1016
1017	/** @todo Assert uErr isn't X86_TRAP_PF_RSVD and remove release checks. */
1018	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysFault);
1019	AssertMsgReturn(PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage), ("%RGp %RGp uErr=%u\n", GCPhysNestedFault, GCPhysFault, uErr),
1020	VERR_PGM_HANDLER_IPE_1);
1021
1022	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1023	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1024	RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1025
1026	/*
1027	* Physical page access handler.
1028	*/
1029	PPGMPHYSHANDLER pCur;
1030	VBOXSTRICTRC rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysPage, &pCur);
1031	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
1032
1033	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
1034	Assert(pCurType);
1035
1036	/*
1037	* If the region is write protected and we got a page not present fault, then sync
1038	* the pages. If the fault was caused by a read, then restart the instruction.
1039	* In case of write access continue to the GC write handler.
1040	*/
1041	if ( !(uErr & X86_TRAP_PF_P)
1042	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1043	{
1044	Log7Func(("Syncing Monitored: GCPhysNestedPage=%RGp GCPhysPage=%RGp uErr=%#x\n", GCPhysNestedPage, GCPhysPage, uErr));
1045	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1046	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1047	if ( RT_FAILURE(rcStrict)
1048	\|\| !(uErr & X86_TRAP_PF_RW))
1049	{
1050	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1051	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1052	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1053	return rcStrict;
1054	}
1055	}
1056	else if ( !(uErr & X86_TRAP_PF_RSVD)
1057	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE)
1058	{
1059	/*
1060	* If the access was NOT through an EPT misconfig (i.e. RSVD), sync the page.
1061	* This can happen for the VMX APIC-access page.
1062	*/
1063	Log7Func(("Syncing MMIO: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1064	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1065	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1066	if (RT_FAILURE(rcStrict))
1067	{
1068	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1069	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1070	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1071	return rcStrict;
1072	}
1073	}
1074
1075	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
1076	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
1077	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
1078	GCPhysNestedFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
1079	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1080	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
1081	else
1082	{
1083	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
1084	if (uErr & X86_TRAP_PF_RSVD)
1085	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
1086	}
1087
1088	if (pCurType->pfnPfHandler)
1089	{
1090	STAM_PROFILE_START(&pCur->Stat, h);
1091	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
1092	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
1093
1094	if (pCurType->fKeepPgmLock)
1095	{
1096	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, GCPhysNestedFault, GCPhysFault, uUser);
1097	STAM_PROFILE_STOP(&pCur->Stat, h);
1098	}
1099	else
1100	{
1101	PGM_UNLOCK(pVM);
1102	*pfLockTaken = false;
1103	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pRegFrame, GCPhysNestedFault, GCPhysFault, uUser);
1104	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
1105	}
1106	}
1107	else
1108	{
1109	AssertMsgFailed(("What's going on here!? Fault falls outside handler range!?\n"));
1110	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
1111	}
1112
1113	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
1114	return rcStrict;
1115
1116	# else
1117	RT_NOREF8(pVCpu, uErr, pRegFrame, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
1118	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1119	return VERR_PGM_NOT_USED_IN_MODE;
1120	# endif
1121	}
1122	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1123
1124
1125	/**
1126	* Nested \#PF handler for nested-guest hardware-assisted execution using nested
1127	* paging.
1128	*
1129	* @returns VBox status code (appropriate for trap handling and GC return).
1130	* @param pVCpu The cross context virtual CPU structure.
1131	* @param uErr The fault error (X86_TRAP_PF_*).
1132	* @param pRegFrame The register frame.
1133	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1134	* @param fIsLinearAddrValid Whether translation of a nested-guest linear address
1135	* caused this fault. If @c false, GCPtrNestedFault
1136	* must be 0.
1137	* @param GCPtrNestedFault The nested-guest linear address of this fault.
1138	* @param pWalk The guest page table walk result.
1139	* @param pfLockTaken Where to store whether the PGM lock is still held
1140	* when this function completes.
1141	*/
1142	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysNestedFault,
1143	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken)
1144	{
1145	*pfLockTaken = false;
1146	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) \
1147	&& PGM_GST_TYPE == PGM_TYPE_PROT \
1148	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1149
1150	Assert(CPUMIsGuestVmxEptPagingEnabled(pVCpu));
1151	Assert(PGM_A20_IS_ENABLED(pVCpu));
1152
1153	/* We don't support mode-based execute control for EPT yet. */
1154	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
1155	Assert(!(uErr & X86_TRAP_PF_US));
1156
1157	/* Take the big lock now. */
1158	*pfLockTaken = true;
1159	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1160	PGM_LOCK_VOID(pVM);
1161
1162	/*
1163	* Walk the guest EPT tables and check if it's an EPT violation or misconfiguration.
1164	*/
1165	Log7Func(("cs:rip=%04x:%#RX64 GCPhysNestedFault=%RGp\n", pRegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedFault));
1166	PGMPTWALKGST GstWalkAll;
1167	int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll);
1168	if (RT_FAILURE(rc))
1169	return rc;
1170
1171	Assert(GstWalkAll.enmType == PGMPTWALKGSTTYPE_EPT);
1172	Assert(pWalk->fSucceeded);
1173	Assert(pWalk->fEffective & (PGM_PTATTRS_EPT_R_MASK \| PGM_PTATTRS_EPT_W_MASK \| PGM_PTATTRS_EPT_X_SUPER_MASK));
1174	Assert(pWalk->fIsSlat);
1175
1176	/* Paranoia: Remove later. */
1177	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_R_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_R_MASK));
1178	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_W_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_W_MASK));
1179	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_NX_MASK) == !RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_X_SUPER_MASK));
1180
1181	/*
1182	* Check page-access permissions.
1183	*/
1184	if ( ((uErr & X86_TRAP_PF_RW) && !(pWalk->fEffective & PGM_PTATTRS_W_MASK))
1185	\|\| ((uErr & X86_TRAP_PF_ID) && (pWalk->fEffective & PGM_PTATTRS_NX_MASK)))
1186	{
1187	Log7Func(("Permission failed! GCPtrNested=%RGv GCPhysNested=%RGp uErr=%#x fEffective=%#RX64\n", GCPtrNestedFault,
1188	GCPhysNestedFault, uErr, pWalk->fEffective));
1189	pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
1190	return VERR_ACCESS_DENIED;
1191	}
1192
1193	PGM_A20_ASSERT_MASKED(pVCpu, pWalk->GCPhys);
1194	RTGCPHYS const GCPhysPage = pWalk->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1195	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1196
1197	/*
1198	* If we were called via an EPT misconfig, it should've already resulted in a nested-guest VM-exit.
1199	*/
1200	AssertMsgReturn(!(uErr & X86_TRAP_PF_RSVD),
1201	("Unexpected EPT misconfig VM-exit. GCPhysPage=%RGp GCPhysNestedPage=%RGp\n", GCPhysPage, GCPhysNestedPage),
1202	VERR_PGM_MAPPING_IPE);
1203
1204	/*
1205	* Fetch and sync the nested-guest EPT page directory pointer.
1206	*/
1207	PEPTPD pEptPd;
1208	rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL /ppPdpt/, &pEptPd, &GstWalkAll);
1209	AssertRCReturn(rc, rc);
1210	Assert(pEptPd);
1211
1212	/*
1213	* A common case is the not-present error caused by lazy page table syncing.
1214	*
1215	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
1216	* here so we can safely assume that the shadow PT is present when calling
1217	* NestedSyncPage later.
1218	*
1219	* NOTE: It's possible we will be syncing the VMX APIC-access page here.
1220	* In that case, we would sync the page but will NOT go ahead with emulating
1221	* the APIC-access VM-exit through IEM. However, once the page is mapped in
1222	* the shadow tables, subsequent APIC-access VM-exits for the nested-guest
1223	* will be triggered by hardware. Maybe calling the IEM #PF handler can be
1224	* considered as an optimization later.
1225	*/
1226	unsigned const iPde = (GCPhysNestedPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1227	if ( !(uErr & X86_TRAP_PF_P)
1228	&& !(pEptPd->a[iPde].u & EPT_PRESENT_MASK))
1229	{
1230	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
1231	Log7Func(("NestedSyncPT: Lazy. GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1232	rc = PGM_BTH_NAME(NestedSyncPT)(pVCpu, GCPhysNestedPage, GCPhysPage, &GstWalkAll);
1233	if (RT_SUCCESS(rc))
1234	return rc;
1235	AssertMsgFailedReturn(("NestedSyncPT: %RGv failed! rc=%Rrc\n", GCPhysNestedPage, rc), VERR_PGM_MAPPING_IPE);
1236	}
1237
1238	/*
1239	* Check if this fault address is flagged for special treatment.
1240	* This handles faults on an MMIO or write-monitored page.
1241	*
1242	* If this happens to be the VMX APIC-access page, we sync it in the shadow tables
1243	* and emulate the APIC-access VM-exit by calling IEM's VMX APIC-access #PF handler
1244	* registered for the page. Once the page is mapped in the shadow tables, subsequent
1245	* APIC-access VM-exits for the nested-guest will be triggered by hardware.
1246	*/
1247	PPGMPAGE pPage;
1248	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1249	AssertRCReturn(rc, rc);
1250	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1251	{
1252	Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage));
1253	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, GCPhysNestedFault,
1254	pPage, pWalk->GCPhys, &GstWalkAll,
1255	pfLockTaken));
1256	}
1257
1258	/*
1259	* We are here only if page is present in nested-guest page tables but the
1260	* trap is not handled by our handlers. Check for page out-of-sync situation.
1261	*/
1262	if (!(uErr & X86_TRAP_PF_P))
1263	{
1264	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
1265	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1266	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
1267
1268	Log7Func(("SyncPage: Not-Present: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedFault, GCPhysPage));
1269	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, PGM_SYNC_NR_PAGES, uErr, &GstWalkAll);
1270	if (RT_SUCCESS(rc))
1271	{
1272	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
1273	return VINF_SUCCESS;
1274	}
1275	}
1276	else if (uErr & X86_TRAP_PF_RW)
1277	{
1278	/*
1279	* Write protected pages are made writable when the guest makes the
1280	* first write to it. This happens for pages that are shared, write
1281	* monitored or not yet allocated.
1282	*
1283	* We may also end up here when CR0.WP=0 in the guest.
1284	*
1285	* Also, a side effect of not flushing global PDEs are out of sync
1286	* pages due to physical monitored regions, that are no longer valid.
1287	* Assume for now it only applies to the read/write flag.
1288	*/
1289	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1290	{
1291	/* This is a read-only page. */
1292	AssertMsgFailed(("Failed\n"));
1293
1294	Assert(!PGM_PAGE_IS_ZERO(pPage));
1295	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhysPage));
1296	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
1297
1298	Log7Func(("Calling pgmPhysPageMakeWritable for GCPhysPage=%RGp\n", GCPhysPage));
1299	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1300	if (rc != VINF_SUCCESS)
1301	{
1302	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1303	return rc;
1304	}
1305	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
1306	return VINF_EM_NO_MEMORY;
1307	}
1308
1309	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1310	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1311
1312	/*
1313	* Sync the write-protected page.
1314	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1315	* page is not present, which is not true in this case.
1316	*/
1317	Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n",
1318	pRegFrame->cs.Sel, pRegFrame->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
1319	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll);
1320	if (RT_SUCCESS(rc))
1321	{
1322	HMInvalidatePhysPage(pVM, GCPhysPage);
1323	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
1324	return VINF_SUCCESS;
1325	}
1326	}
1327
1328	/*
1329	* If we get here it is because something failed above => guru meditation time.
1330	*/
1331	LogRelFunc(("GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n", rc, GCPhysNestedFault, GCPhysPage,
1332	(uint32_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1333	return VERR_PGM_MAPPING_IPE;
1334
1335	# else
1336	RT_NOREF7(pVCpu, uErr, pRegFrame, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
1337	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1338	return VERR_PGM_NOT_USED_IN_MODE;
1339	# endif
1340	}
1341
1342	#endif /* !IN_RING3 */
1343
1344
1345	/**
1346	* Emulation of the invlpg instruction.
1347	*
1348	*
1349	* @returns VBox status code.
1350	*
1351	* @param pVCpu The cross context virtual CPU structure.
1352	* @param GCPtrPage Page to invalidate.
1353	*
1354	* @remark ASSUMES that the guest is updating before invalidating. This order
1355	* isn't required by the CPU, so this is speculative and could cause
1356	* trouble.
1357	* @remark No TLB shootdown is done on any other VCPU as we assume that
1358	* invlpg emulation is the only reason for calling this function.
1359	* (The guest has to shoot down TLB entries on other CPUs itself)
1360	* Currently true, but keep in mind!
1361	*
1362	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1363	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1364	*/
1365	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1366	{
1367	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1368	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1369	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1370	int rc;
1371	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1372	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1373
1374	PGM_LOCK_ASSERT_OWNER(pVM);
1375
1376	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1377
1378	/*
1379	* Get the shadow PD entry and skip out if this PD isn't present.
1380	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1381	*/
1382	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1383	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1384	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1385
1386	/* Fetch the pgm pool shadow descriptor. */
1387	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1388	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1389	if (!pShwPde)
1390	{
1391	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1392	return VINF_SUCCESS;
1393	}
1394	# else
1395	Assert(pShwPde);
1396	# endif
1397
1398	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1399	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1400	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1401
1402	/* If the shadow PDPE isn't present, then skip the invalidate. */
1403	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1404	if (!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1405	# else
1406	if (!(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1407	# endif
1408	{
1409	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1410	PGM_INVL_PG(pVCpu, GCPtrPage);
1411	return VINF_SUCCESS;
1412	}
1413
1414	/* Fetch the pgm pool shadow descriptor. */
1415	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1416	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1417
1418	PX86PDPAE pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1419	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1420	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1421
1422	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1423	/* PML4 */
1424	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1425	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1426	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1427	PX86PDPAE pPDDst;
1428	PX86PDPT pPdptDst;
1429	PX86PML4E pPml4eDst;
1430	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1431	if (rc != VINF_SUCCESS)
1432	{
1433	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1434	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1435	PGM_INVL_PG(pVCpu, GCPtrPage);
1436	return VINF_SUCCESS;
1437	}
1438	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1439	Assert(pPDDst);
1440	Assert(pPdptDst->a[iPdpt].u & X86_PDPE_P);
1441
1442	/* Fetch the pgm pool shadow descriptor. */
1443	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1444	Assert(pShwPde);
1445
1446	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1447
1448	const SHWPDE PdeDst = *pPdeDst;
1449	if (!(PdeDst.u & X86_PDE_P))
1450	{
1451	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1452	PGM_INVL_PG(pVCpu, GCPtrPage);
1453	return VINF_SUCCESS;
1454	}
1455
1456	/*
1457	* Get the guest PD entry and calc big page.
1458	*/
1459	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1460	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1461	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1462	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1463	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1464	unsigned iPDSrc = 0;
1465	# if PGM_GST_TYPE == PGM_TYPE_PAE
1466	X86PDPE PdpeSrcIgn;
1467	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1468	# else /* AMD64 */
1469	PX86PML4E pPml4eSrcIgn;
1470	X86PDPE PdpeSrcIgn;
1471	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1472	# endif
1473	GSTPDE PdeSrc;
1474
1475	if (pPDSrc)
1476	PdeSrc = pPDSrc->a[iPDSrc];
1477	else
1478	PdeSrc.u = 0;
1479	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1480	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1481	const bool fIsBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1482	if (fWasBigPage != fIsBigPage)
1483	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1484
1485	# ifdef IN_RING3
1486	/*
1487	* If a CR3 Sync is pending we may ignore the invalidate page operation
1488	* depending on the kind of sync and if it's a global page or not.
1489	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1490	*/
1491	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1492	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1493	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1494	&& fIsBigPage
1495	&& (PdeSrc.u & X86_PDE4M_G)
1496	)
1497	)
1498	# else
1499	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1500	# endif
1501	{
1502	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1503	return VINF_SUCCESS;
1504	}
1505	# endif /* IN_RING3 */
1506
1507	/*
1508	* Deal with the Guest PDE.
1509	*/
1510	rc = VINF_SUCCESS;
1511	if (PdeSrc.u & X86_PDE_P)
1512	{
1513	Assert( (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1514	&& ((PdeSrc.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW) \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1515	if (!fIsBigPage)
1516	{
1517	/*
1518	* 4KB - page.
1519	*/
1520	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1521	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1522
1523	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1524	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1525	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
1526	# endif
1527	if (pShwPage->GCPhys == GCPhys)
1528	{
1529	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1530	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1531
1532	PGSTPT pPTSrc;
1533	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1534	if (RT_SUCCESS(rc))
1535	{
1536	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1537	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1538	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1539	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1540	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1541	GCPtrPage, PteSrc.u & X86_PTE_P,
1542	(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1543	(PteSrc.u & PdeSrc.u & X86_PTE_US),
1544	(uint64_t)PteSrc.u,
1545	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1546	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1547	}
1548	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1549	PGM_INVL_PG(pVCpu, GCPtrPage);
1550	}
1551	else
1552	{
1553	/*
1554	* The page table address changed.
1555	*/
1556	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1557	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1558	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1559	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1560	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1561	PGM_INVL_VCPU_TLBS(pVCpu);
1562	}
1563	}
1564	else
1565	{
1566	/*
1567	* 2/4MB - page.
1568	*/
1569	/* Before freeing the page, check if anything really changed. */
1570	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1571	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1572	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1573	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1574	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1575	# endif
1576	if ( pShwPage->GCPhys == GCPhys
1577	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1578	{
1579	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1580	/** @todo This test is wrong as it cannot check the G bit!
1581	* FIXME */
1582	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1583	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1584	&& ( (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1585	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1586	{
1587	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1588	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1589	return VINF_SUCCESS;
1590	}
1591	}
1592
1593	/*
1594	* Ok, the page table is present and it's been changed in the guest.
1595	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1596	* We could do this for some flushes in GC too, but we need an algorithm for
1597	* deciding which 4MB pages containing code likely to be executed very soon.
1598	*/
1599	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1600	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1601	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1602	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1603	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1604	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1605	}
1606	}
1607	else
1608	{
1609	/*
1610	* Page directory is not present, mark shadow PDE not present.
1611	*/
1612	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1613	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1614	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1615	PGM_INVL_PG(pVCpu, GCPtrPage);
1616	}
1617	return rc;
1618
1619	#else /* guest real and protected mode, nested + ept, none. */
1620	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1621	NOREF(pVCpu); NOREF(GCPtrPage);
1622	return VINF_SUCCESS;
1623	#endif
1624	}
1625
1626	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1627
1628	/**
1629	* Update the tracking of shadowed pages.
1630	*
1631	* @param pVCpu The cross context virtual CPU structure.
1632	* @param pShwPage The shadow page.
1633	* @param HCPhys The physical page we is being dereferenced.
1634	* @param iPte Shadow PTE index
1635	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1636	*/
1637	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1638	RTGCPHYS GCPhysPage)
1639	{
1640	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1641
1642	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1643	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1644	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1645
1646	/* Use the hint we retrieved from the cached guest PT. */
1647	if (pShwPage->fDirty)
1648	{
1649	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1650
1651	Assert(pShwPage->cPresent);
1652	Assert(pPool->cPresent);
1653	pShwPage->cPresent--;
1654	pPool->cPresent--;
1655
1656	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1657	AssertRelease(pPhysPage);
1658	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1659	return;
1660	}
1661	# else
1662	NOREF(GCPhysPage);
1663	# endif
1664
1665	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatTrackDeref, a);
1666	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1667
1668	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1669	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1670	* 2. write protect all shadowed pages. I.e. implement caching.
1671	*/
1672	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1673
1674	/*
1675	* Find the guest address.
1676	*/
1677	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1678	pRam;
1679	pRam = pRam->CTX_SUFF(pNext))
1680	{
1681	unsigned iPage = pRam->cb >> GUEST_PAGE_SHIFT;
1682	while (iPage-- > 0)
1683	{
1684	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1685	{
1686	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1687
1688	Assert(pShwPage->cPresent);
1689	Assert(pPool->cPresent);
1690	pShwPage->cPresent--;
1691	pPool->cPresent--;
1692
1693	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1694	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatTrackDeref, a);
1695	return;
1696	}
1697	}
1698	}
1699
1700	for (;;)
1701	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1702	}
1703
1704
1705	/**
1706	* Update the tracking of shadowed pages.
1707	*
1708	* @param pVCpu The cross context virtual CPU structure.
1709	* @param pShwPage The shadow page.
1710	* @param u16 The top 16-bit of the pPage->HCPhys.
1711	* @param pPage Pointer to the guest page. this will be modified.
1712	* @param iPTDst The index into the shadow table.
1713	*/
1714	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16,
1715	PPGMPAGE pPage, const unsigned iPTDst)
1716	{
1717	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1718
1719	/*
1720	* Just deal with the simple first time here.
1721	*/
1722	if (!u16)
1723	{
1724	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatTrackVirgin);
1725	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1726	/* Save the page table index. */
1727	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1728	}
1729	else
1730	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1731
1732	/* write back */
1733	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1734	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1735
1736	/* update statistics. */
1737	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1738	pShwPage->cPresent++;
1739	if (pShwPage->iFirstPresent > iPTDst)
1740	pShwPage->iFirstPresent = iPTDst;
1741	}
1742
1743
1744	/**
1745	* Modifies a shadow PTE to account for access handlers.
1746	*
1747	* @param pVM The cross context VM structure.
1748	* @param pVCpu The cross context virtual CPU structure.
1749	* @param pPage The page in question.
1750	* @param GCPhysPage The guest-physical address of the page.
1751	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1752	* A (accessed) bit so it can be emulated correctly.
1753	* @param pPteDst The shadow PTE (output). This is temporary storage and
1754	* does not need to be set atomically.
1755	*/
1756	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PVMCPUCC pVCpu, PCPGMPAGE pPage, RTGCPHYS GCPhysPage, uint64_t fPteSrc,
1757	PSHWPTE pPteDst)
1758	{
1759	RT_NOREF_PV(pVM); RT_NOREF_PV(fPteSrc); RT_NOREF_PV(pVCpu); RT_NOREF_PV(GCPhysPage);
1760
1761	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1762	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1763	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1764	{
1765	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1766	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1767	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) \| EPT_E_READ \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1768	# else
1769	if (fPteSrc & X86_PTE_A)
1770	{
1771	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1772	SHW_PTE_SET_RO(*pPteDst);
1773	}
1774	else
1775	SHW_PTE_SET(*pPteDst, 0);
1776	# endif
1777	}
1778	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1779	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1780	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1781	&& ( BTH_IS_NP_ACTIVE(pVM)
1782	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1783	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1784	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1785	# endif
1786	)
1787	{
1788	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX) && PGM_SHW_TYPE == PGM_TYPE_EPT && defined(PGM_WITH_NESTED_APIC_ACCESS_PAGE)
1789	/*
1790	* If an "ALL" access handler has been registered for the VMX APIC-access page,
1791	* we want to ensure EPT violations are triggered rather than EPT misconfigs
1792	* as the former allows us to translate it to an APIC-access VM-exit. This is a
1793	* weird case because this is not an MMIO page (it's regular guest RAM) but we
1794	* want to treat it as an MMIO page wrt to trapping all accesses but we only
1795	* want EPT violations for the reasons state above.
1796	*
1797	* NOTE! This is required even when the nested-hypervisor is not using EPT!
1798	*/
1799	if (CPUMIsGuestVmxApicAccessPageAddr(pVCpu, GCPhysPage))
1800	{
1801	Log7Func(("SyncHandlerPte: VMX APIC-access page at %#RGp -> marking not present\n", GCPhysPage));
1802	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1803	return;
1804	}
1805	# endif
1806
1807	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1808	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1809	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1810	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
1811	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1812	\| EPT_E_WRITE
1813	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1814	\| EPT_E_MEMTYPE_INVALID_3;
1815	# else
1816	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1817	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1818	# endif
1819	}
1820	# endif
1821	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1822	else
1823	{
1824	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1825	SHW_PTE_SET(*pPteDst, 0);
1826	}
1827	/** @todo count these kinds of entries. */
1828	}
1829
1830
1831	/**
1832	* Creates a 4K shadow page for a guest page.
1833	*
1834	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1835	* physical address. The PdeSrc argument only the flags are used. No page
1836	* structured will be mapped in this function.
1837	*
1838	* @param pVCpu The cross context virtual CPU structure.
1839	* @param pPteDst Destination page table entry.
1840	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1841	* Can safely assume that only the flags are being used.
1842	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1843	* @param pShwPage Pointer to the shadow page.
1844	* @param iPTDst The index into the shadow table.
1845	*
1846	* @remark Not used for 2/4MB pages!
1847	*/
1848	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1849	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1850	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1851	# else
1852	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1853	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1854	# endif
1855	{
1856	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1857	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1858
1859	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1860	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1861	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1862
1863	if (pShwPage->fDirty)
1864	{
1865	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1866	PGSTPT pGstPT;
1867
1868	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1869	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1870	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1871	pGstPT->a[iPTDst].u = PteSrc.u;
1872	}
1873	# else
1874	Assert(!pShwPage->fDirty);
1875	# endif
1876
1877	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1878	if ( (PteSrc.u & X86_PTE_P)
1879	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1880	# endif
1881	{
1882	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1883	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1884	# endif
1885	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1886
1887	/*
1888	* Find the ram range.
1889	*/
1890	PPGMPAGE pPage;
1891	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1892	if (RT_SUCCESS(rc))
1893	{
1894	/* Ignore ballooned pages.
1895	Don't return errors or use a fatal assert here as part of a
1896	shadow sync range might included ballooned pages. */
1897	if (PGM_PAGE_IS_BALLOONED(pPage))
1898	{
1899	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1900	return;
1901	}
1902
1903	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1904	/* Make the page writable if necessary. */
1905	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1906	&& ( PGM_PAGE_IS_ZERO(pPage)
1907	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1908	\|\| ( (PteSrc.u & X86_PTE_RW)
1909	# else
1910	\|\| ( 1
1911	# endif
1912	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1913	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1914	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1915	# endif
1916	# ifdef VBOX_WITH_PAGE_SHARING
1917	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1918	# endif
1919	)
1920	)
1921	)
1922	{
1923	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1924	AssertRC(rc);
1925	}
1926	# endif
1927
1928	/*
1929	* Make page table entry.
1930	*/
1931	SHWPTE PteDst;
1932	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1933	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1934	# else
1935	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1936	# endif
1937	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1938	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhysPage, fGstShwPteFlags, &PteDst);
1939	else
1940	{
1941	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1942	/*
1943	* If the page or page directory entry is not marked accessed,
1944	* we mark the page not present.
1945	*/
1946	if (!(PteSrc.u & X86_PTE_A) \|\| !(PdeSrc.u & X86_PDE_A))
1947	{
1948	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1949	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,AccessedPage));
1950	SHW_PTE_SET(PteDst, 0);
1951	}
1952	/*
1953	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1954	* when the page is modified.
1955	*/
1956	else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
1957	{
1958	AssertCompile(X86_PTE_RW == X86_PDE_RW);
1959	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPage));
1960	SHW_PTE_SET(PteDst,
1961	fGstShwPteFlags
1962	\| PGM_PAGE_GET_HCPHYS(pPage)
1963	\| PGM_PTFLAGS_TRACK_DIRTY);
1964	SHW_PTE_SET_RO(PteDst);
1965	}
1966	else
1967	# endif
1968	{
1969	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageSkipped));
1970	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1971	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
1972	\| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1973	# else
1974	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1975	# endif
1976	}
1977
1978	/*
1979	* Make sure only allocated pages are mapped writable.
1980	*/
1981	if ( SHW_PTE_IS_P_RW(PteDst)
1982	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1983	{
1984	/* Still applies to shared pages. */
1985	Assert(!PGM_PAGE_IS_ZERO(pPage));
1986	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1987	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1988	}
1989	}
1990
1991	/*
1992	* Keep user track up to date.
1993	*/
1994	if (SHW_PTE_IS_P(PteDst))
1995	{
1996	if (!SHW_PTE_IS_P(*pPteDst))
1997	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1998	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1999	{
2000	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
2001	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2002	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2003	}
2004	}
2005	else if (SHW_PTE_IS_P(*pPteDst))
2006	{
2007	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2008	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2009	}
2010
2011	/*
2012	* Update statistics and commit the entry.
2013	*/
2014	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2015	if (!(PteSrc.u & X86_PTE_G))
2016	pShwPage->fSeenNonGlobal = true;
2017	# endif
2018	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2019	return;
2020	}
2021
2022	/** @todo count these three different kinds. */
2023	Log2(("SyncPageWorker: invalid address in Pte\n"));
2024	}
2025	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2026	else if (!(PteSrc.u & X86_PTE_P))
2027	Log2(("SyncPageWorker: page not present in Pte\n"));
2028	else
2029	Log2(("SyncPageWorker: invalid Pte\n"));
2030	# endif
2031
2032	/*
2033	* The page is not present or the PTE is bad. Replace the shadow PTE by
2034	* an empty entry, making sure to keep the user tracking up to date.
2035	*/
2036	if (SHW_PTE_IS_P(*pPteDst))
2037	{
2038	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2039	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2040	}
2041	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
2042	}
2043
2044
2045	/**
2046	* Syncs a guest OS page.
2047	*
2048	* There are no conflicts at this point, neither is there any need for
2049	* page table allocations.
2050	*
2051	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
2052	* When called in AMD64 guest mode, the guest PML4E shall be valid.
2053	*
2054	* @returns VBox status code.
2055	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
2056	* @param pVCpu The cross context virtual CPU structure.
2057	* @param PdeSrc Page directory entry of the guest.
2058	* @param GCPtrPage Guest context page address.
2059	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2060	* @param uErr Fault error (X86_TRAP_PF_*).
2061	*/
2062	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
2063	{
2064	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2065	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2066	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
2067	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
2068
2069	PGM_LOCK_ASSERT_OWNER(pVM);
2070
2071	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2072	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2073	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2074	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
2075
2076	/*
2077	* Assert preconditions.
2078	*/
2079	Assert(PdeSrc.u & X86_PDE_P);
2080	Assert(cPages);
2081	# if 0 /* rarely useful; leave for debugging. */
2082	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
2083	# endif
2084
2085	/*
2086	* Get the shadow PDE, find the shadow page table in the pool.
2087	*/
2088	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2089	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2090	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2091
2092	/* Fetch the pgm pool shadow descriptor. */
2093	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2094	Assert(pShwPde);
2095
2096	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2097	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2098	PPGMPOOLPAGE pShwPde = NULL;
2099	PX86PDPAE pPDDst;
2100
2101	/* Fetch the pgm pool shadow descriptor. */
2102	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2103	AssertRCSuccessReturn(rc2, rc2);
2104	Assert(pShwPde);
2105
2106	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2107	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2108
2109	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2110	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2111	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2112	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2113	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2114
2115	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2116	AssertRCSuccessReturn(rc2, rc2);
2117	Assert(pPDDst && pPdptDst);
2118	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2119	# endif
2120	SHWPDE PdeDst = *pPdeDst;
2121
2122	/*
2123	* - In the guest SMP case we could have blocked while another VCPU reused
2124	* this page table.
2125	* - With W7-64 we may also take this path when the A bit is cleared on
2126	* higher level tables (PDPE/PML4E). The guest does not invalidate the
2127	* relevant TLB entries. If we're write monitoring any page mapped by
2128	* the modified entry, we may end up here with a "stale" TLB entry.
2129	*/
2130	if (!(PdeDst.u & X86_PDE_P))
2131	{
2132	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2133	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
2134	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2135	if (uErr & X86_TRAP_PF_P)
2136	PGM_INVL_PG(pVCpu, GCPtrPage);
2137	return VINF_SUCCESS; /* force the instruction to be executed again. */
2138	}
2139
2140	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2141	Assert(pShwPage);
2142
2143	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2144	/* Fetch the pgm pool shadow descriptor. */
2145	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2146	Assert(pShwPde);
2147	# endif
2148
2149	/*
2150	* Check that the page is present and that the shadow PDE isn't out of sync.
2151	*/
2152	const bool fBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
2153	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2154	RTGCPHYS GCPhys;
2155	if (!fBigPage)
2156	{
2157	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2158	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2159	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2160	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
2161	# endif
2162	}
2163	else
2164	{
2165	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2166	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2167	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2168	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2169	# endif
2170	}
2171	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2172	if ( fPdeValid
2173	&& pShwPage->GCPhys == GCPhys
2174	&& (PdeSrc.u & X86_PDE_P)
2175	&& (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
2176	&& ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW))
2177	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2178	&& ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) \|\| !GST_IS_NX_ACTIVE(pVCpu))
2179	# endif
2180	)
2181	{
2182	/*
2183	* Check that the PDE is marked accessed already.
2184	* Since we set the accessed bit before getting here on a #PF, this
2185	* check is only meant for dealing with non-#PF'ing paths.
2186	*/
2187	if (PdeSrc.u & X86_PDE_A)
2188	{
2189	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2190	if (!fBigPage)
2191	{
2192	/*
2193	* 4KB Page - Map the guest page table.
2194	*/
2195	PGSTPT pPTSrc;
2196	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2197	if (RT_SUCCESS(rc))
2198	{
2199	# ifdef PGM_SYNC_N_PAGES
2200	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2201	if ( cPages > 1
2202	&& !(uErr & X86_TRAP_PF_P)
2203	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2204	{
2205	/*
2206	* This code path is currently only taken when the caller is PGMTrap0eHandler
2207	* for non-present pages!
2208	*
2209	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2210	* deal with locality.
2211	*/
2212	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2213	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2214	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2215	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2216	# else
2217	const unsigned offPTSrc = 0;
2218	# endif
2219	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2220	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2221	iPTDst = 0;
2222	else
2223	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2224
2225	for (; iPTDst < iPTDstEnd; iPTDst++)
2226	{
2227	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2228
2229	if ( (pPteSrc->u & X86_PTE_P)
2230	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2231	{
2232	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT))
2233	\| ((offPTSrc + iPTDst) << GUEST_PAGE_SHIFT);
2234	NOREF(GCPtrCurPage);
2235	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2236	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2237	GCPtrCurPage, pPteSrc->u & X86_PTE_P,
2238	!!(pPteSrc->u & PdeSrc.u & X86_PTE_RW),
2239	!!(pPteSrc->u & PdeSrc.u & X86_PTE_US),
2240	(uint64_t)pPteSrc->u,
2241	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2242	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2243	}
2244	}
2245	}
2246	else
2247	# endif /* PGM_SYNC_N_PAGES */
2248	{
2249	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2250	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2251	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2252	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2253	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2254	GCPtrPage, PteSrc.u & X86_PTE_P,
2255	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
2256	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
2257	(uint64_t)PteSrc.u,
2258	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2259	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2260	}
2261	}
2262	else /* MMIO or invalid page: emulated in #PF handler. */
2263	{
2264	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2265	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2266	}
2267	}
2268	else
2269	{
2270	/*
2271	* 4/2MB page - lazy syncing shadow 4K pages.
2272	* (There are many causes of getting here, it's no longer only CSAM.)
2273	*/
2274	/* Calculate the GC physical address of this 4KB shadow page. */
2275	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2276	/* Find ram range. */
2277	PPGMPAGE pPage;
2278	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2279	if (RT_SUCCESS(rc))
2280	{
2281	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2282
2283	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2284	/* Try to make the page writable if necessary. */
2285	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2286	&& ( PGM_PAGE_IS_ZERO(pPage)
2287	\|\| ( (PdeSrc.u & X86_PDE_RW)
2288	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2289	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2290	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2291	# endif
2292	# ifdef VBOX_WITH_PAGE_SHARING
2293	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2294	# endif
2295	)
2296	)
2297	)
2298	{
2299	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2300	AssertRC(rc);
2301	}
2302	# endif
2303
2304	/*
2305	* Make shadow PTE entry.
2306	*/
2307	SHWPTE PteDst;
2308	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2309	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2310	else
2311	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2312
2313	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2314	if ( SHW_PTE_IS_P(PteDst)
2315	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2316	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2317
2318	/* Make sure only allocated pages are mapped writable. */
2319	if ( SHW_PTE_IS_P_RW(PteDst)
2320	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2321	{
2322	/* Still applies to shared pages. */
2323	Assert(!PGM_PAGE_IS_ZERO(pPage));
2324	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2325	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2326	}
2327
2328	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2329
2330	/*
2331	* If the page is not flagged as dirty and is writable, then make it read-only
2332	* at PD level, so we can set the dirty bit when the page is modified.
2333	*
2334	* ASSUMES that page access handlers are implemented on page table entry level.
2335	* Thus we will first catch the dirty access and set PDE.D and restart. If
2336	* there is an access handler, we'll trap again and let it work on the problem.
2337	*/
2338	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2339	* As for invlpg, it simply frees the whole shadow PT.
2340	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2341	if ((PdeSrc.u & (X86_PDE4M_D \| X86_PDE_RW)) == X86_PDE_RW)
2342	{
2343	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2344	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2345	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2346	}
2347	else
2348	{
2349	PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY \| X86_PDE_RW);
2350	PdeDst.u \|= PdeSrc.u & X86_PDE_RW;
2351	}
2352	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2353	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2354	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US),
2355	(uint64_t)PdeSrc.u, GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2356	}
2357	else
2358	{
2359	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2360	/** @todo must wipe the shadow page table entry in this
2361	* case. */
2362	}
2363	}
2364	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2365	return VINF_SUCCESS;
2366	}
2367
2368	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDNAs));
2369	}
2370	else if (fPdeValid)
2371	{
2372	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2373	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2374	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2375	}
2376	else
2377	{
2378	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2379	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2380	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2381	}
2382
2383	/*
2384	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2385	* Yea, I'm lazy.
2386	*/
2387	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2388	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
2389
2390	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2391	PGM_INVL_VCPU_TLBS(pVCpu);
2392	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2393
2394
2395	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2396	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2397	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2398	NOREF(PdeSrc);
2399
2400	# ifdef PGM_SYNC_N_PAGES
2401	/*
2402	* Get the shadow PDE, find the shadow page table in the pool.
2403	*/
2404	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2405	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2406
2407	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2408	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2409
2410	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2411	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2412	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2413	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2414	X86PDEPAE PdeDst;
2415	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2416
2417	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2418	AssertRCSuccessReturn(rc, rc);
2419	Assert(pPDDst && pPdptDst);
2420	PdeDst = pPDDst->a[iPDDst];
2421
2422	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2423	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2424	PEPTPD pPDDst;
2425	EPTPDE PdeDst;
2426
2427	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2428	if (rc != VINF_SUCCESS)
2429	{
2430	AssertRC(rc);
2431	return rc;
2432	}
2433	Assert(pPDDst);
2434	PdeDst = pPDDst->a[iPDDst];
2435	# endif
2436	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2437	if (!SHW_PDE_IS_P(PdeDst))
2438	{
2439	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2440	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2441	return VINF_SUCCESS; /* force the instruction to be executed again. */
2442	}
2443
2444	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2445	if (SHW_PDE_IS_BIG(PdeDst))
2446	{
2447	Assert(pVM->pgm.s.fNestedPaging);
2448	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2449	return VINF_SUCCESS;
2450	}
2451
2452	/* Mask away the page offset. */
2453	GCPtrPage &= ~((RTGCPTR)0xfff);
2454
2455	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2456	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2457
2458	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2459	if ( cPages > 1
2460	&& !(uErr & X86_TRAP_PF_P)
2461	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2462	{
2463	/*
2464	* This code path is currently only taken when the caller is PGMTrap0eHandler
2465	* for non-present pages!
2466	*
2467	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2468	* deal with locality.
2469	*/
2470	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2471	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2472	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2473	iPTDst = 0;
2474	else
2475	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2476	for (; iPTDst < iPTDstEnd; iPTDst++)
2477	{
2478	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2479	{
2480	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2481	\| (iPTDst << GUEST_PAGE_SHIFT));
2482
2483	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2484	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2485	GCPtrCurPage,
2486	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2487	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2488
2489	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2490	break;
2491	}
2492	else
2493	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n",
2494	(GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << GUEST_PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2495	}
2496	}
2497	else
2498	# endif /* PGM_SYNC_N_PAGES */
2499	{
2500	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2501	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2502	\| (iPTDst << GUEST_PAGE_SHIFT));
2503
2504	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2505
2506	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2507	GCPtrPage,
2508	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2509	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2510	}
2511	return VINF_SUCCESS;
2512
2513	# else
2514	NOREF(PdeSrc);
2515	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2516	return VERR_PGM_NOT_USED_IN_MODE;
2517	# endif
2518	}
2519
2520	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2521
2522
2523	#if !defined(IN_RING3) && defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
2524	/**
2525	* Sync a shadow page for a nested-guest page.
2526	*
2527	* @param pVCpu The cross context virtual CPU structure.
2528	* @param pPte The shadow page table entry.
2529	* @param GCPhysPage The guest-physical address of the page.
2530	* @param pShwPage The shadow page of the page table.
2531	* @param iPte The index of the page table entry.
2532	* @param pGstWalkAll The guest page table walk result.
2533	*
2534	* @note Not to be used for 2/4MB pages!
2535	*/
2536	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
2537	unsigned iPte, PPGMPTWALKGST pGstWalkAll)
2538	{
2539	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2540	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2541	Assert(!pShwPage->fDirty);
2542	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
2543
2544	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2545	AssertMsg(GCPhysPage == (pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK),
2546	("GCPhys=%RGp Ept=%RX64\n", GCPhysPage, pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK));
2547
2548	/*
2549	* Find the ram range.
2550	*/
2551	PPGMPAGE pPage;
2552	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
2553	AssertRCReturnVoid(rc);
2554
2555	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
2556
2557	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2558	/* Make the page writable if necessary. */
2559	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2560	&& PGM_PAGE_IS_ZERO(pPage)
2561	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2562	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2563	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2564	# endif
2565	# ifdef VBOX_WITH_PAGE_SHARING
2566	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2567	# endif
2568	)
2569	{
2570	AssertMsgFailed(("GCPhysPage=%RGp\n", GCPhysPage)); /** @todo Shouldn't happen but if it does deal with it later. */
2571	}
2572	# endif
2573
2574	/*
2575	* Make page table entry.
2576	*/
2577	SHWPTE Pte;
2578	uint64_t const fGstShwPteFlags = pGstWalkAll->u.Ept.Pte.u & pVCpu->pgm.s.fGstEptShadowedPteMask;
2579	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2580	{
2581	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2582	Log7Func(("regular page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2583	}
2584	else if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2585	{
2586	/** @todo access bit. */
2587	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| (fGstShwPteFlags & ~EPT_E_WRITE);
2588	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2589	}
2590	else
2591	{
2592	# if defined(PGM_WITH_NESTED_APIC_ACCESS_PAGE)
2593	if (CPUMIsGuestVmxApicAccessPageAddr(pVCpu, GCPhysPage))
2594	{
2595	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2596	Log7Func(("APIC-access page at %RGp -> shadowing nested-hypervisor %RX64 (%RGp)\n", GCPhysPage, fGstShwPteFlags, pShwPage->GCPhys));
2597	}
2598	# if 0 /** @todo r=bird: What on earth is the rational for this? */
2599	else if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2600	{
2601	if (fGstShwPteFlags & EPT_E_WRITE)
2602	{
2603	PGMHandlerPhysicalPageTempOff(pVCpu->CTX_SUFF(pVM), GCPhysPage, GCPhysPage);
2604	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> read-write, monitoring disabled\n", pPage, GCPhysPage));
2605	}
2606	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2607	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> shadowing nested-hypervisor %RX64\n", pPage, GCPhysPage, fGstShwPteFlags));
2608	}
2609	# endif
2610	else
2611	# endif
2612	{
2613	# if defined(PGM_WITH_NESTED_APIC_ACCESS_PAGE)
2614	/** @todo Track using fVirtVmxApicAccess bit in PGMPHYSHANDLER and maybe in PGMPAGE
2615	* too? */
2616	/** @todo r=bird: this is wrong for device passthru among other scenarios. */
2617	PGMHandlerPhysicalDeregister(pVCpu->CTX_SUFF(pVM), GCPhysPage);
2618	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2619	Log7Func(("MMIO at %RGp potentially former VMX APIC-access page -> unregistered\n", GCPhysPage));
2620	# else
2621	/** @todo Do MMIO optimizations here too? */
2622	Log7Func(("mmio page (%R[pgmpage]) at %RGp -> 0\n", pPage, GCPhysPage));
2623	Pte.u = 0;
2624	# endif
2625	}
2626	}
2627
2628	/* Make sure only allocated pages are mapped writable. */
2629	Assert(!SHW_PTE_IS_P_RW(Pte) \|\| PGM_PAGE_IS_ALLOCATED(pPage));
2630
2631	/*
2632	* Keep user track up to date.
2633	*/
2634	if (SHW_PTE_IS_P(Pte))
2635	{
2636	if (!SHW_PTE_IS_P(*pPte))
2637	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2638	else if (SHW_PTE_GET_HCPHYS(*pPte) != SHW_PTE_GET_HCPHYS(Pte))
2639	{
2640	Log2(("SyncPageWorker: deref! pPte=%RX64 Pte=%RX64\n", SHW_PTE_LOG64(pPte), SHW_PTE_LOG64(Pte)));
2641	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2642	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2643	}
2644	}
2645	else if (SHW_PTE_IS_P(*pPte))
2646	{
2647	Log2(("SyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2648	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2649	}
2650
2651	/*
2652	* Commit the entry.
2653	*/
2654	SHW_PTE_ATOMIC_SET2(*pPte, Pte);
2655	return;
2656	}
2657
2658
2659	/**
2660	* Syncs a nested-guest page.
2661	*
2662	* There are no conflicts at this point, neither is there any need for
2663	* page table allocations.
2664	*
2665	* @returns VBox status code.
2666	* @param pVCpu The cross context virtual CPU structure.
2667	* @param GCPhysNestedPage The nested-guest physical address of the page being
2668	* synced.
2669	* @param GCPhysPage The guest-physical address of the page being synced.
2670	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2671	* @param uErr The page fault error (X86_TRAP_PF_XXX).
2672	* @param pGstWalkAll The guest page table walk result.
2673	*/
2674	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
2675	uint32_t uErr, PPGMPTWALKGST pGstWalkAll)
2676	{
2677	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2678	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2679	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2680
2681	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2682	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2683	Log7Func(("GCPhysNestedPage=%RGv GCPhysPage=%RGp cPages=%u uErr=%#x\n", GCPhysNestedPage, GCPhysPage, cPages, uErr));
2684	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages);
2685
2686	PGM_LOCK_ASSERT_OWNER(pVM);
2687
2688	/*
2689	* Get the shadow PDE, find the shadow page table in the pool.
2690	*/
2691	unsigned const iPde = ((GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK);
2692	PEPTPD pPd;
2693	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL, &pPd, pGstWalkAll);
2694	if (RT_SUCCESS(rc))
2695	{ /* likely */ }
2696	else
2697	{
2698	Log(("Failed to fetch EPT PD for %RGp (%RGp) rc=%Rrc\n", GCPhysNestedPage, GCPhysPage, rc));
2699	return rc;
2700	}
2701	Assert(pPd);
2702	EPTPDE Pde = pPd->a[iPde];
2703
2704	# if 0 /* Enable this later? */
2705	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2706	if (!SHW_PDE_IS_P(Pde))
2707	{
2708	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)Pde.u));
2709	Log7Func(("CPU%d: SyncPage: Pde at %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2710	return VINF_SUCCESS; /* force the instruction to be executed again. */
2711	}
2712
2713	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2714	if (SHW_PDE_IS_BIG(Pde))
2715	{
2716	Assert(pVM->pgm.s.fNestedPaging);
2717	Log7Func(("CPU%d: SyncPage: %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2718	return VINF_SUCCESS;
2719	}
2720	# else
2721	AssertMsg(SHW_PDE_IS_P(Pde), ("Pde=%RX64 iPde=%u\n", Pde.u, iPde));
2722	Assert(!SHW_PDE_IS_BIG(Pde));
2723	# endif
2724
2725	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, Pde.u & EPT_PDE_PG_MASK);
2726	PEPTPT pPt = (PEPTPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2727
2728	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2729	# ifdef PGM_SYNC_N_PAGES
2730	if ( cPages > 1
2731	&& !(uErr & X86_TRAP_PF_P)
2732	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2733	{
2734	/*
2735	* This code path is currently only taken for non-present pages!
2736	*
2737	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2738	* deal with locality.
2739	*/
2740	unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2741	unsigned const iPteEnd = RT_MIN(iPte + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPt->a));
2742	if (iPte < PGM_SYNC_NR_PAGES / 2)
2743	iPte = 0;
2744	else
2745	iPte -= PGM_SYNC_NR_PAGES / 2;
2746	for (; iPte < iPteEnd; iPte++)
2747	{
2748	if (!SHW_PTE_IS_P(pPt->a[iPte]))
2749	{
2750	PGMPTWALKGST GstWalkPt;
2751	PGMPTWALK WalkPt;
2752	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2753	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2754	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt,
2755	&GstWalkPt);
2756	if (RT_SUCCESS(rc))
2757	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], WalkPt.GCPhys, pShwPage, iPte, &GstWalkPt);
2758	else
2759	{
2760	/*
2761	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
2762	* Ensure the shadow tables entry is not-present.
2763	*/
2764	/** @todo Potential room for optimization (explained in NestedSyncPT). */
2765	AssertMsg(!pPt->a[iPte].u, ("%RX64\n", pPt->a[iPte].u));
2766	}
2767	Log7Func(("Many: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2768	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2769	break;
2770	}
2771	else
2772	{
2773	# ifdef VBOX_STRICT
2774	/* Paranoia - Verify address of the page is what it should be. */
2775	PGMPTWALKGST GstWalkPt;
2776	PGMPTWALK WalkPt;
2777	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2778	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2779	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt, &GstWalkPt);
2780	AssertRC(rc);
2781	PPGMPAGE pPage;
2782	rc = pgmPhysGetPageEx(pVM, WalkPt.GCPhys, &pPage);
2783	AssertRC(rc);
2784	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]),
2785	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp HCPhys=%RHp Shw=%RHp\n",
2786	GCPhysNestedPage, WalkPt.GCPhys, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2787	# endif
2788	Log7Func(("Many3: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2789	}
2790	}
2791	}
2792	else
2793	# endif /* PGM_SYNC_N_PAGES */
2794	{
2795	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2796	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
2797	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2798	}
2799
2800	return VINF_SUCCESS;
2801	}
2802
2803
2804	/**
2805	* Sync a shadow page table for a nested-guest page table.
2806	*
2807	* The shadow page table is not present in the shadow PDE.
2808	*
2809	* Handles mapping conflicts.
2810	*
2811	* A precondition for this method is that the shadow PDE is not present. The
2812	* caller must take the PGM lock before checking this and continue to hold it
2813	* when calling this method.
2814	*
2815	* @returns VBox status code.
2816	* @param pVCpu The cross context virtual CPU structure.
2817	* @param GCPhysNestedPage The nested-guest physical page address of the page
2818	* being synced.
2819	* @param GCPhysPage The guest-physical address of the page being synced.
2820	* @param pGstWalkAll The guest page table walk result.
2821	*/
2822	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll)
2823	{
2824	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2825	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2826	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2827
2828	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2829	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2830
2831	Log7Func(("GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
2832
2833	PGM_LOCK_ASSERT_OWNER(pVM);
2834	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2835
2836	PEPTPD pPd;
2837	PEPTPDPT pPdpt;
2838	unsigned const iPde = (GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK;
2839	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, &pPdpt, &pPd, pGstWalkAll);
2840	if (rc != VINF_SUCCESS)
2841	{
2842	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2843	AssertRC(rc);
2844	return rc;
2845	}
2846	Assert(pPd);
2847	PSHWPDE pPde = &pPd->a[iPde];
2848
2849	unsigned const iPdpt = (GCPhysNestedPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2850	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdpt->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2851	Assert(pShwPde->enmKind == PGMPOOLKIND_EPT_PD_FOR_EPT_PD);
2852
2853	SHWPDE Pde = *pPde;
2854	Assert(!SHW_PDE_IS_P(Pde)); /* We're only supposed to call SyncPT on PDE!P and conflicts. */
2855
2856	# ifdef PGM_WITH_LARGE_PAGES
2857	if (BTH_IS_NP_ACTIVE(pVM))
2858	{
2859	/* Check if we allocated a big page before for this 2 MB range and disable it. */
2860	PPGMPAGE pPage;
2861	rc = pgmPhysGetPageEx(pVM, GCPhysPage & X86_PDE2M_PAE_PG_MASK, &pPage);
2862	if ( RT_SUCCESS(rc)
2863	&& PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2864	{
2865	Log7Func(("Disabling large page %RGp\n", GCPhysPage));
2866	Assert(PGM_A20_IS_ENABLED(pVCpu)); /* Should never be in A20M mode in VMX operation. */
2867	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
2868	pVM->pgm.s.cLargePagesDisabled++;
2869	}
2870	}
2871	# endif /* PGM_WITH_LARGE_PAGES */
2872
2873	/*
2874	* Allocate & map the page table.
2875	*/
2876	PSHWPT pPt;
2877	PPGMPOOLPAGE pShwPage;
2878
2879	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE_PG_MASK;
2880	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_PT, PGMPOOLACCESS_DONTCARE,
2881	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
2882	if ( rc == VINF_SUCCESS
2883	\|\| rc == VINF_PGM_CACHED_PAGE)
2884	{ /* likely */ }
2885	else
2886	{
2887	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2888	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2889	}
2890
2891	pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2892	Assert(pPt);
2893	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2894
2895	if (rc == VINF_SUCCESS)
2896	{
2897	/* Sync the page we've already translated through SLAT. */
2898	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2899	Assert((pGstWalkAll->u.Ept.Pte.u & EPT_PTE_PG_MASK) == GCPhysPage);
2900	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll);
2901	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
2902
2903	/* Sync the rest of page table (expensive but might be cheaper than nested-guest VM-exits in hardware). */
2904	for (unsigned iPteCur = 0; iPteCur < RT_ELEMENTS(pPt->a); iPteCur++)
2905	{
2906	if (iPteCur != iPte)
2907	{
2908	PGMPTWALKGST GstWalkPt;
2909	PGMPTWALK WalkPt;
2910	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2911	GCPhysNestedPage \|= (iPteCur << GUEST_PAGE_SHIFT);
2912	int const rc2 = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/,
2913	&WalkPt, &GstWalkPt);
2914	if (RT_SUCCESS(rc2))
2915	{
2916	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPteCur], WalkPt.GCPhys, pShwPage, iPteCur, &GstWalkPt);
2917	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", GstWalkPt.u.Ept.Pte.u, pPt->a[iPteCur].u, iPteCur));
2918	}
2919	else
2920	{
2921	/*
2922	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
2923	* Ensure the shadow tables entry is not-present.
2924	*/
2925	/** @todo We currently don't sync. them to cause EPT misconfigs and trap all of them
2926	* using EPT violation and walk the guest EPT tables to determine EPT
2927	* misconfigs VM-exits for the nested-guest. In the future we could optimize
2928	* this by using a specific combination of reserved bits which we can
2929	* immediately identify as EPT misconfigs for the nested-guest without having
2930	* to walk its EPT tables. Tracking non-present entries might be tricky...
2931	*/
2932	AssertMsg(!pPt->a[iPteCur].u, ("%RX64\n", pPt->a[iPteCur].u));
2933	}
2934	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2935	break;
2936	}
2937	}
2938	}
2939	else
2940	{
2941	Assert(rc == VINF_PGM_CACHED_PAGE);
2942	# ifdef VBOX_STRICT
2943	/* Paranoia - Verify address of the page is what it should be. */
2944	PPGMPAGE pPage;
2945	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
2946	AssertRC(rc);
2947	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2948	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]),
2949	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp Page=%RHp Shw=%RHp\n",
2950	GCPhysNestedPage, GCPhysPage, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2951	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [cache]\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
2952	# endif
2953	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
2954	}
2955
2956	/* Save the new PDE. */
2957	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
2958	AssertReturn(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF), VERR_NOT_SUPPORTED); /* Implement this later. */
2959	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
2960	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
2961	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
2962
2963	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2964	return rc;
2965	}
2966	#endif /* !IN_RING3 && VBOX_WITH_NESTED_HWVIRT_VMX_EPT && PGM_SHW_TYPE == PGM_TYPE_EPT*/
2967
2968
2969	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
2970
2971	/**
2972	* Handle dirty bit tracking faults.
2973	*
2974	* @returns VBox status code.
2975	* @param pVCpu The cross context virtual CPU structure.
2976	* @param uErr Page fault error code.
2977	* @param pPdeSrc Guest page directory entry.
2978	* @param pPdeDst Shadow page directory entry.
2979	* @param GCPtrPage Guest context page address.
2980	*/
2981	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2982	RTGCPTR GCPtrPage)
2983	{
2984	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2985	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2986	NOREF(uErr);
2987
2988	PGM_LOCK_ASSERT_OWNER(pVM);
2989
2990	/*
2991	* Handle big page.
2992	*/
2993	if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
2994	{
2995	if ((pPdeDst->u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2996	{
2997	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
2998	Assert(pPdeSrc->u & X86_PDE_RW);
2999
3000	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
3001	* fault again and take this path to only invalidate the entry (see below). */
3002	SHWPDE PdeDst = *pPdeDst;
3003	PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
3004	PdeDst.u \|= X86_PDE_RW \| X86_PDE_A;
3005	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3006	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
3007	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3008	}
3009
3010	# ifdef IN_RING0
3011	/* Check for stale TLB entry; only applies to the SMP guest case. */
3012	if ( pVM->cCpus > 1
3013	&& (pPdeDst->u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A))
3014	{
3015	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3016	if (pShwPage)
3017	{
3018	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3019	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3020	if (SHW_PTE_IS_P_RW(*pPteDst))
3021	{
3022	/* Stale TLB entry. */
3023	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3024	PGM_INVL_PG(pVCpu, GCPtrPage);
3025	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3026	}
3027	}
3028	}
3029	# endif /* IN_RING0 */
3030	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3031	}
3032
3033	/*
3034	* Map the guest page table.
3035	*/
3036	PGSTPT pPTSrc;
3037	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
3038	AssertRCReturn(rc, rc);
3039
3040	if (SHW_PDE_IS_P(*pPdeDst))
3041	{
3042	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
3043	const GSTPTE PteSrc = *pPteSrc;
3044
3045	/*
3046	* Map shadow page table.
3047	*/
3048	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3049	if (pShwPage)
3050	{
3051	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3052	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3053	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
3054	{
3055	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
3056	{
3057	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
3058	SHWPTE PteDst = *pPteDst;
3059
3060	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
3061	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3062
3063	Assert(PteSrc.u & X86_PTE_RW);
3064
3065	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
3066	* entry will not harm; write access will simply fault again and
3067	* take this path to only invalidate the entry.
3068	*/
3069	if (RT_LIKELY(pPage))
3070	{
3071	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3072	{
3073	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
3074	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
3075	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
3076	SHW_PTE_SET_RO(PteDst);
3077	}
3078	else
3079	{
3080	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
3081	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
3082	{
3083	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
3084	AssertRC(rc);
3085	}
3086	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
3087	SHW_PTE_SET_RW(PteDst);
3088	else
3089	{
3090	/* Still applies to shared pages. */
3091	Assert(!PGM_PAGE_IS_ZERO(pPage));
3092	SHW_PTE_SET_RO(PteDst);
3093	}
3094	}
3095	}
3096	else
3097	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
3098
3099	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
3100	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
3101	PGM_INVL_PG(pVCpu, GCPtrPage);
3102	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3103	}
3104
3105	# ifdef IN_RING0
3106	/* Check for stale TLB entry; only applies to the SMP guest case. */
3107	if ( pVM->cCpus > 1
3108	&& SHW_PTE_IS_RW(*pPteDst)
3109	&& SHW_PTE_IS_A(*pPteDst))
3110	{
3111	/* Stale TLB entry. */
3112	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3113	PGM_INVL_PG(pVCpu, GCPtrPage);
3114	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3115	}
3116	# endif
3117	}
3118	}
3119	else
3120	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
3121	}
3122
3123	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3124	}
3125
3126	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
3127
3128	/**
3129	* Sync a shadow page table.
3130	*
3131	* The shadow page table is not present in the shadow PDE.
3132	*
3133	* Handles mapping conflicts.
3134	*
3135	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
3136	* conflict), and Trap0eHandler.
3137	*
3138	* A precondition for this method is that the shadow PDE is not present. The
3139	* caller must take the PGM lock before checking this and continue to hold it
3140	* when calling this method.
3141	*
3142	* @returns VBox status code.
3143	* @param pVCpu The cross context virtual CPU structure.
3144	* @param iPDSrc Page directory index.
3145	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
3146	* Assume this is a temporary mapping.
3147	* @param GCPtrPage GC Pointer of the page that caused the fault
3148	*/
3149	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
3150	{
3151	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3152	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3153
3154	#if 0 /* rarely useful; leave for debugging. */
3155	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
3156	#endif
3157	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
3158
3159	PGM_LOCK_ASSERT_OWNER(pVM);
3160
3161	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3162	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3163	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3164	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3165	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3166	int rc = VINF_SUCCESS;
3167
3168	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3169
3170	/*
3171	* Some input validation first.
3172	*/
3173	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
3174
3175	/*
3176	* Get the relevant shadow PDE entry.
3177	*/
3178	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3179	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
3180	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3181
3182	/* Fetch the pgm pool shadow descriptor. */
3183	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3184	Assert(pShwPde);
3185
3186	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3187	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3188	PPGMPOOLPAGE pShwPde = NULL;
3189	PX86PDPAE pPDDst;
3190	PSHWPDE pPdeDst;
3191
3192	/* Fetch the pgm pool shadow descriptor. */
3193	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3194	AssertRCSuccessReturn(rc, rc);
3195	Assert(pShwPde);
3196
3197	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3198	pPdeDst = &pPDDst->a[iPDDst];
3199
3200	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3201	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3202	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3203	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3204	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
3205	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3206	AssertRCSuccessReturn(rc, rc);
3207	Assert(pPDDst);
3208	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3209
3210	# endif
3211	SHWPDE PdeDst = *pPdeDst;
3212
3213	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3214	/* Fetch the pgm pool shadow descriptor. */
3215	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3216	Assert(pShwPde);
3217	# endif
3218
3219	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P.*/
3220
3221	/*
3222	* Sync the page directory entry.
3223	*/
3224	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3225	const bool fPageTable = !(PdeSrc.u & X86_PDE_PS) \|\| !GST_IS_PSE_ACTIVE(pVCpu);
3226	if ( (PdeSrc.u & X86_PDE_P)
3227	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
3228	{
3229	/*
3230	* Allocate & map the page table.
3231	*/
3232	PSHWPT pPTDst;
3233	PPGMPOOLPAGE pShwPage;
3234	RTGCPHYS GCPhys;
3235	if (fPageTable)
3236	{
3237	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
3238	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3239	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3240	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
3241	# endif
3242	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
3243	pShwPde->idx, iPDDst, false /fLockPage/,
3244	&pShwPage);
3245	}
3246	else
3247	{
3248	PGMPOOLACCESS enmAccess;
3249	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
3250	const bool fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
3251	# else
3252	const bool fNoExecute = false;
3253	# endif
3254
3255	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3256	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3257	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3258	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
3259	# endif
3260	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3261	if (PdeSrc.u & X86_PDE_US)
3262	{
3263	if (PdeSrc.u & X86_PDE_RW)
3264	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
3265	else
3266	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
3267	}
3268	else
3269	{
3270	if (PdeSrc.u & X86_PDE_RW)
3271	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3272	else
3273	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3274	}
3275	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3276	pShwPde->idx, iPDDst, false /fLockPage/,
3277	&pShwPage);
3278	}
3279	if (rc == VINF_SUCCESS)
3280	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3281	else if (rc == VINF_PGM_CACHED_PAGE)
3282	{
3283	/*
3284	* The PT was cached, just hook it up.
3285	*/
3286	if (fPageTable)
3287	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3288	else
3289	{
3290	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3291	/* (see explanation and assumptions further down.) */
3292	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3293	{
3294	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3295	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3296	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3297	}
3298	}
3299	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3300	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3301	return VINF_SUCCESS;
3302	}
3303	else
3304	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3305	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
3306	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
3307	* irrelevant at this point. */
3308	PdeDst.u &= X86_PDE_AVL_MASK;
3309	PdeDst.u \|= pShwPage->Core.Key;
3310
3311	/*
3312	* Page directory has been accessed (this is a fault situation, remember).
3313	*/
3314	/** @todo
3315	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
3316	* fault situation. What's more, the Trap0eHandler has already set the
3317	* accessed bit. So, it's actually just VerifyAccessSyncPage which
3318	* might need setting the accessed flag.
3319	*
3320	* The best idea is to leave this change to the caller and add an
3321	* assertion that it's set already. */
3322	pPDSrc->a[iPDSrc].u \|= X86_PDE_A;
3323	if (fPageTable)
3324	{
3325	/*
3326	* Page table - 4KB.
3327	*
3328	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
3329	*/
3330	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
3331	GCPtrPage, PdeSrc.u & X86_PTE_P, !!(PdeSrc.u & X86_PTE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u));
3332	PGSTPT pPTSrc;
3333	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
3334	if (RT_SUCCESS(rc))
3335	{
3336	/*
3337	* Start by syncing the page directory entry so CSAM's TLB trick works.
3338	*/
3339	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
3340	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3341	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3342	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3343
3344	/*
3345	* Directory/page user or supervisor privilege: (same goes for read/write)
3346	*
3347	* Directory Page Combined
3348	* U/S U/S U/S
3349	* 0 0 0
3350	* 0 1 0
3351	* 1 0 0
3352	* 1 1 1
3353	*
3354	* Simple AND operation. Table listed for completeness.
3355	*
3356	*/
3357	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4K));
3358	# ifdef PGM_SYNC_N_PAGES
3359	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3360	unsigned iPTDst = iPTBase;
3361	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
3362	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
3363	iPTDst = 0;
3364	else
3365	iPTDst -= PGM_SYNC_NR_PAGES / 2;
3366	# else /* !PGM_SYNC_N_PAGES */
3367	unsigned iPTDst = 0;
3368	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
3369	# endif /* !PGM_SYNC_N_PAGES */
3370	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
3371	\| ((RTGCPTR)iPTDst << GUEST_PAGE_SHIFT);
3372	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3373	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3374	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
3375	# else
3376	const unsigned offPTSrc = 0;
3377	# endif
3378	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += GUEST_PAGE_SIZE)
3379	{
3380	const unsigned iPTSrc = iPTDst + offPTSrc;
3381	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
3382	if (PteSrc.u & X86_PTE_P)
3383	{
3384	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
3385	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
3386	GCPtrCur,
3387	PteSrc.u & X86_PTE_P,
3388	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
3389	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
3390	(uint64_t)PteSrc.u,
3391	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
3392	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
3393	}
3394	/* else: the page table was cleared by the pool */
3395	} /* for PTEs */
3396	}
3397	}
3398	else
3399	{
3400	/*
3401	* Big page - 2/4MB.
3402	*
3403	* We'll walk the ram range list in parallel and optimize lookups.
3404	* We will only sync one shadow page table at a time.
3405	*/
3406	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4M));
3407
3408	/**
3409	* @todo It might be more efficient to sync only a part of the 4MB
3410	* page (similar to what we do for 4KB PDs).
3411	*/
3412
3413	/*
3414	* Start by syncing the page directory entry.
3415	*/
3416	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
3417	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3418
3419	/*
3420	* If the page is not flagged as dirty and is writable, then make it read-only
3421	* at PD level, so we can set the dirty bit when the page is modified.
3422	*
3423	* ASSUMES that page access handlers are implemented on page table entry level.
3424	* Thus we will first catch the dirty access and set PDE.D and restart. If
3425	* there is an access handler, we'll trap again and let it work on the problem.
3426	*/
3427	/** @todo move the above stuff to a section in the PGM documentation. */
3428	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3429	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3430	{
3431	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3432	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3433	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3434	}
3435	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3436	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3437
3438	/*
3439	* Fill the shadow page table.
3440	*/
3441	/* Get address and flags from the source PDE. */
3442	SHWPTE PteDstBase;
3443	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3444
3445	/* Loop thru the entries in the shadow PT. */
3446	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3447	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3448	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u, GCPtr,
3449	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3450	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3451	unsigned iPTDst = 0;
3452	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3453	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3454	{
3455	if (pRam && GCPhys >= pRam->GCPhys)
3456	{
3457	# ifndef PGM_WITH_A20
3458	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT;
3459	# endif
3460	do
3461	{
3462	/* Make shadow PTE. */
3463	# ifdef PGM_WITH_A20
3464	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT];
3465	# else
3466	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3467	# endif
3468	SHWPTE PteDst;
3469
3470	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3471	/* Try to make the page writable if necessary. */
3472	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3473	&& ( PGM_PAGE_IS_ZERO(pPage)
3474	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3475	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3476	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3477	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3478	# endif
3479	# ifdef VBOX_WITH_PAGE_SHARING
3480	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3481	# endif
3482	&& !PGM_PAGE_IS_BALLOONED(pPage))
3483	)
3484	)
3485	{
3486	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3487	AssertRCReturn(rc, rc);
3488	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3489	break;
3490	}
3491	# endif
3492
3493	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3494	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, SHW_PTE_GET_U(PteDstBase), &PteDst);
3495	else if (PGM_PAGE_IS_BALLOONED(pPage))
3496	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3497	else
3498	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3499
3500	/* Only map writable pages writable. */
3501	if ( SHW_PTE_IS_P_RW(PteDst)
3502	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3503	{
3504	/* Still applies to shared pages. */
3505	Assert(!PGM_PAGE_IS_ZERO(pPage));
3506	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3507	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3508	}
3509
3510	if (SHW_PTE_IS_P(PteDst))
3511	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3512
3513	/* commit it (not atomic, new table) */
3514	pPTDst->a[iPTDst] = PteDst;
3515	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3516	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3517	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3518
3519	/* advance */
3520	GCPhys += GUEST_PAGE_SIZE;
3521	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3522	# ifndef PGM_WITH_A20
3523	iHCPage++;
3524	# endif
3525	iPTDst++;
3526	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3527	&& GCPhys <= pRam->GCPhysLast);
3528
3529	/* Advance ram range list. */
3530	while (pRam && GCPhys > pRam->GCPhysLast)
3531	pRam = pRam->CTX_SUFF(pNext);
3532	}
3533	else if (pRam)
3534	{
3535	Log(("Invalid pages at %RGp\n", GCPhys));
3536	do
3537	{
3538	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3539	GCPhys += GUEST_PAGE_SIZE;
3540	iPTDst++;
3541	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3542	&& GCPhys < pRam->GCPhys);
3543	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3544	}
3545	else
3546	{
3547	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3548	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3549	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3550	}
3551	} /* while more PTEs */
3552	} /* 4KB / 4MB */
3553	}
3554	else
3555	AssertRelease(!SHW_PDE_IS_P(PdeDst));
3556
3557	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3558	if (RT_FAILURE(rc))
3559	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3560	return rc;
3561
3562	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3563	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
3564	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3565	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3566	NOREF(iPDSrc); NOREF(pPDSrc);
3567
3568	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3569
3570	/*
3571	* Validate input a little bit.
3572	*/
3573	int rc = VINF_SUCCESS;
3574	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3575	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3576	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3577
3578	/* Fetch the pgm pool shadow descriptor. */
3579	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3580	Assert(pShwPde);
3581
3582	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3583	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3584	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3585	PX86PDPAE pPDDst;
3586	PSHWPDE pPdeDst;
3587
3588	/* Fetch the pgm pool shadow descriptor. */
3589	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3590	AssertRCSuccessReturn(rc, rc);
3591	Assert(pShwPde);
3592
3593	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3594	pPdeDst = &pPDDst->a[iPDDst];
3595
3596	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3597	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3598	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3599	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3600	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3601	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3602	AssertRCSuccessReturn(rc, rc);
3603	Assert(pPDDst);
3604	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3605
3606	/* Fetch the pgm pool shadow descriptor. */
3607	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3608	Assert(pShwPde);
3609
3610	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3611	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3612	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3613	PEPTPD pPDDst;
3614	PEPTPDPT pPdptDst;
3615
3616	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3617	if (rc != VINF_SUCCESS)
3618	{
3619	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3620	AssertRC(rc);
3621	return rc;
3622	}
3623	Assert(pPDDst);
3624	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3625
3626	/* Fetch the pgm pool shadow descriptor. */
3627	/** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
3628	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3629	Assert(pShwPde);
3630	# endif
3631	SHWPDE PdeDst = *pPdeDst;
3632
3633	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3634
3635	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3636	if (BTH_IS_NP_ACTIVE(pVM))
3637	{
3638	Assert(!VM_IS_NEM_ENABLED(pVM));
3639
3640	/* Check if we allocated a big page before for this 2 MB range. */
3641	PPGMPAGE pPage;
3642	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3643	if (RT_SUCCESS(rc))
3644	{
3645	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3646	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3647	{
3648	if (PGM_A20_IS_ENABLED(pVCpu))
3649	{
3650	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3651	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3652	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3653	}
3654	else
3655	{
3656	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3657	pVM->pgm.s.cLargePagesDisabled++;
3658	}
3659	}
3660	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3661	&& PGM_A20_IS_ENABLED(pVCpu))
3662	{
3663	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3664	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3665	if (RT_SUCCESS(rc))
3666	{
3667	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3668	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3669	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3670	}
3671	}
3672	else if ( PGMIsUsingLargePages(pVM)
3673	&& PGM_A20_IS_ENABLED(pVCpu))
3674	{
3675	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3676	if (RT_SUCCESS(rc))
3677	{
3678	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3679	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3680	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3681	}
3682	else
3683	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3684	}
3685
3686	if (HCPhys != NIL_RTHCPHYS)
3687	{
3688	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3689	PdeDst.u = HCPhys \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_LEAF \| EPT_E_IGNORE_PAT \| EPT_E_MEMTYPE_WB
3690	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
3691	# else
3692	PdeDst.u = HCPhys \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PS
3693	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
3694	# endif
3695	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3696
3697	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3698	/* Add a reference to the first page only. */
3699	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3700
3701	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3702	return VINF_SUCCESS;
3703	}
3704	}
3705	}
3706	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
3707
3708	/*
3709	* Allocate & map the page table.
3710	*/
3711	PSHWPT pPTDst;
3712	PPGMPOOLPAGE pShwPage;
3713	RTGCPHYS GCPhys;
3714
3715	/* Virtual address = physical address */
3716	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3717	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3718	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3719	&pShwPage);
3720	if ( rc == VINF_SUCCESS
3721	\|\| rc == VINF_PGM_CACHED_PAGE)
3722	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3723	else
3724	{
3725	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3726	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3727	}
3728
3729	if (rc == VINF_SUCCESS)
3730	{
3731	/* New page table; fully set it up. */
3732	Assert(pPTDst);
3733
3734	/* Mask away the page offset. */
3735	GCPtrPage &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
3736
3737	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3738	{
3739	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3740	\| (iPTDst << GUEST_PAGE_SHIFT));
3741
3742	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3743	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3744	GCPtrCurPage,
3745	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3746	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3747
3748	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3749	break;
3750	}
3751	}
3752	else
3753	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3754
3755	/* Save the new PDE. */
3756	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3757	PdeDst.u = pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE
3758	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
3759	# else
3760	PdeDst.u = pShwPage->Core.Key \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A
3761	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
3762	# endif
3763	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3764
3765	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3766	if (RT_FAILURE(rc))
3767	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3768	return rc;
3769
3770	#else
3771	NOREF(iPDSrc); NOREF(pPDSrc);
3772	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3773	return VERR_PGM_NOT_USED_IN_MODE;
3774	#endif
3775	}
3776
3777
3778
3779	/**
3780	* Prefetch a page/set of pages.
3781	*
3782	* Typically used to sync commonly used pages before entering raw mode
3783	* after a CR3 reload.
3784	*
3785	* @returns VBox status code.
3786	* @param pVCpu The cross context virtual CPU structure.
3787	* @param GCPtrPage Page to invalidate.
3788	*/
3789	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
3790	{
3791	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3792	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3793	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3794	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3795	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3796	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3797	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3798	/*
3799	* Check that all Guest levels thru the PDE are present, getting the
3800	* PD and PDE in the processes.
3801	*/
3802	int rc = VINF_SUCCESS;
3803	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3804	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3805	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3806	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3807	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3808	unsigned iPDSrc;
3809	X86PDPE PdpeSrc;
3810	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3811	if (!pPDSrc)
3812	return VINF_SUCCESS; /* not present */
3813	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3814	unsigned iPDSrc;
3815	PX86PML4E pPml4eSrc;
3816	X86PDPE PdpeSrc;
3817	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3818	if (!pPDSrc)
3819	return VINF_SUCCESS; /* not present */
3820	# endif
3821	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3822	# else
3823	PGSTPD pPDSrc = NULL;
3824	const unsigned iPDSrc = 0;
3825	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
3826	# endif
3827
3828	if ((PdeSrc.u & (X86_PDE_P \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_A))
3829	{
3830	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3831	PGM_LOCK_VOID(pVM);
3832
3833	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3834	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3835	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3836	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3837	PX86PDPAE pPDDst;
3838	X86PDEPAE PdeDst;
3839	# if PGM_GST_TYPE != PGM_TYPE_PAE
3840	X86PDPE PdpeSrc;
3841
3842	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3843	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3844	# endif
3845	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3846	if (rc != VINF_SUCCESS)
3847	{
3848	PGM_UNLOCK(pVM);
3849	AssertRC(rc);
3850	return rc;
3851	}
3852	Assert(pPDDst);
3853	PdeDst = pPDDst->a[iPDDst];
3854
3855	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3856	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3857	PX86PDPAE pPDDst;
3858	X86PDEPAE PdeDst;
3859
3860	# if PGM_GST_TYPE == PGM_TYPE_PROT
3861	/* AMD-V nested paging */
3862	X86PML4E Pml4eSrc;
3863	X86PDPE PdpeSrc;
3864	PX86PML4E pPml4eSrc = &Pml4eSrc;
3865
3866	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3867	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3868	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3869	# endif
3870
3871	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3872	if (rc != VINF_SUCCESS)
3873	{
3874	PGM_UNLOCK(pVM);
3875	AssertRC(rc);
3876	return rc;
3877	}
3878	Assert(pPDDst);
3879	PdeDst = pPDDst->a[iPDDst];
3880	# endif
3881	if (!(PdeDst.u & X86_PDE_P))
3882	{
3883	/** @todo r=bird: This guy will set the A bit on the PDE,
3884	* probably harmless. */
3885	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3886	}
3887	else
3888	{
3889	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3890	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3891	* makes no sense to prefetch more than one page.
3892	*/
3893	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3894	if (RT_SUCCESS(rc))
3895	rc = VINF_SUCCESS;
3896	}
3897	PGM_UNLOCK(pVM);
3898	}
3899	return rc;
3900
3901	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
3902	NOREF(pVCpu); NOREF(GCPtrPage);
3903	return VINF_SUCCESS; /* ignore */
3904	#else
3905	AssertCompile(0);
3906	#endif
3907	}
3908
3909
3910
3911
3912	/**
3913	* Syncs a page during a PGMVerifyAccess() call.
3914	*
3915	* @returns VBox status code (informational included).
3916	* @param pVCpu The cross context virtual CPU structure.
3917	* @param GCPtrPage The address of the page to sync.
3918	* @param fPage The effective guest page flags.
3919	* @param uErr The trap error code.
3920	* @remarks This will normally never be called on invalid guest page
3921	* translation entries.
3922	*/
3923	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3924	{
3925	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3926
3927	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3928	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3929
3930	Assert(!pVM->pgm.s.fNestedPaging);
3931	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3932	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3933	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3934	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3935	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3936	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3937	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3938
3939	/*
3940	* Get guest PD and index.
3941	*/
3942	/** @todo Performance: We've done all this a jiffy ago in the
3943	* PGMGstGetPage call. */
3944	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3945	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3946	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
3947	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3948
3949	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3950	unsigned iPDSrc = 0;
3951	X86PDPE PdpeSrc;
3952	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3953	if (RT_UNLIKELY(!pPDSrc))
3954	{
3955	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3956	return VINF_EM_RAW_GUEST_TRAP;
3957	}
3958
3959	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3960	unsigned iPDSrc = 0; /* shut up gcc */
3961	PX86PML4E pPml4eSrc = NULL; /* ditto */
3962	X86PDPE PdpeSrc;
3963	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3964	if (RT_UNLIKELY(!pPDSrc))
3965	{
3966	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3967	return VINF_EM_RAW_GUEST_TRAP;
3968	}
3969	# endif
3970
3971	# else /* !PGM_WITH_PAGING */
3972	PGSTPD pPDSrc = NULL;
3973	const unsigned iPDSrc = 0;
3974	# endif /* !PGM_WITH_PAGING */
3975	int rc = VINF_SUCCESS;
3976
3977	PGM_LOCK_VOID(pVM);
3978
3979	/*
3980	* First check if the shadow pd is present.
3981	*/
3982	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3983	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3984
3985	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3986	PX86PDEPAE pPdeDst;
3987	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3988	PX86PDPAE pPDDst;
3989	# if PGM_GST_TYPE != PGM_TYPE_PAE
3990	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3991	X86PDPE PdpeSrc;
3992	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3993	# endif
3994	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3995	if (rc != VINF_SUCCESS)
3996	{
3997	PGM_UNLOCK(pVM);
3998	AssertRC(rc);
3999	return rc;
4000	}
4001	Assert(pPDDst);
4002	pPdeDst = &pPDDst->a[iPDDst];
4003
4004	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4005	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4006	PX86PDPAE pPDDst;
4007	PX86PDEPAE pPdeDst;
4008
4009	# if PGM_GST_TYPE == PGM_TYPE_PROT
4010	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4011	X86PML4E Pml4eSrc;
4012	X86PDPE PdpeSrc;
4013	PX86PML4E pPml4eSrc = &Pml4eSrc;
4014	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4015	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4016	# endif
4017
4018	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4019	if (rc != VINF_SUCCESS)
4020	{
4021	PGM_UNLOCK(pVM);
4022	AssertRC(rc);
4023	return rc;
4024	}
4025	Assert(pPDDst);
4026	pPdeDst = &pPDDst->a[iPDDst];
4027	# endif
4028
4029	if (!(pPdeDst->u & X86_PDE_P))
4030	{
4031	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4032	if (rc != VINF_SUCCESS)
4033	{
4034	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4035	PGM_UNLOCK(pVM);
4036	AssertRC(rc);
4037	return rc;
4038	}
4039	}
4040
4041	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4042	/* Check for dirty bit fault */
4043	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
4044	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
4045	Log(("PGMVerifyAccess: success (dirty)\n"));
4046	else
4047	# endif
4048	{
4049	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4050	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4051	# else
4052	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4053	# endif
4054
4055	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
4056	if (uErr & X86_TRAP_PF_US)
4057	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
4058	else /* supervisor */
4059	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
4060
4061	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4062	if (RT_SUCCESS(rc))
4063	{
4064	/* Page was successfully synced */
4065	Log2(("PGMVerifyAccess: success (sync)\n"));
4066	rc = VINF_SUCCESS;
4067	}
4068	else
4069	{
4070	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
4071	rc = VINF_EM_RAW_GUEST_TRAP;
4072	}
4073	}
4074	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4075	PGM_UNLOCK(pVM);
4076	return rc;
4077
4078	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4079
4080	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
4081	return VERR_PGM_NOT_USED_IN_MODE;
4082	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4083	}
4084
4085
4086	/**
4087	* Syncs the paging hierarchy starting at CR3.
4088	*
4089	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
4090	* informational status codes.
4091	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
4092	* the VMM into guest context.
4093	* @param pVCpu The cross context virtual CPU structure.
4094	* @param cr0 Guest context CR0 register.
4095	* @param cr3 Guest context CR3 register. Not subjected to the A20
4096	* mask.
4097	* @param cr4 Guest context CR4 register.
4098	* @param fGlobal Including global page directories or not
4099	*/
4100	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
4101	{
4102	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4103	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
4104
4105	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
4106
4107	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
4108	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4109	PGM_LOCK_VOID(pVM);
4110	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4111	if (pPool->cDirtyPages)
4112	pgmPoolResetDirtyPages(pVM);
4113	PGM_UNLOCK(pVM);
4114	# endif
4115	#endif /* !NESTED && !EPT */
4116
4117	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4118	/*
4119	* Nested / EPT / None - No work.
4120	*/
4121	return VINF_SUCCESS;
4122
4123	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4124	/*
4125	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
4126	* out the shadow parts when the guest modifies its tables.
4127	*/
4128	return VINF_SUCCESS;
4129
4130	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4131
4132	return VINF_SUCCESS;
4133	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4134	}
4135
4136
4137
4138
4139	#ifdef VBOX_STRICT
4140
4141	/**
4142	* Checks that the shadow page table is in sync with the guest one.
4143	*
4144	* @returns The number of errors.
4145	* @param pVCpu The cross context virtual CPU structure.
4146	* @param cr3 Guest context CR3 register.
4147	* @param cr4 Guest context CR4 register.
4148	* @param GCPtr Where to start. Defaults to 0.
4149	* @param cb How much to check. Defaults to everything.
4150	*/
4151	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
4152	{
4153	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
4154	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4155	return 0;
4156	#else
4157	unsigned cErrors = 0;
4158	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4159	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
4160
4161	# if PGM_GST_TYPE == PGM_TYPE_PAE
4162	/** @todo currently broken; crashes below somewhere */
4163	AssertFailed();
4164	# endif
4165
4166	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
4167	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4168	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4169
4170	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
4171	PPGMCPU pPGM = &pVCpu->pgm.s;
4172	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
4173	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
4174	# ifndef IN_RING0
4175	RTHCPHYS HCPhys; /* general usage. */
4176	# endif
4177	int rc;
4178
4179	/*
4180	* Check that the Guest CR3 and all its mappings are correct.
4181	*/
4182	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
4183	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
4184	false);
4185	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
4186	# if 0
4187	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4188	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
4189	# else
4190	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
4191	# endif
4192	AssertRCReturn(rc, 1);
4193	HCPhys = NIL_RTHCPHYS;
4194	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
4195	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
4196	# endif
4197	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
4198	pgmGstGet32bitPDPtr(pVCpu);
4199	RTGCPHYS GCPhys;
4200	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
4201	AssertRCReturn(rc, 1);
4202	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
4203	# endif
4204	# endif /* !IN_RING0 */
4205
4206	/*
4207	* Get and check the Shadow CR3.
4208	*/
4209	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4210	unsigned cPDEs = X86_PG_ENTRIES;
4211	unsigned cIncrement = X86_PG_ENTRIES * GUEST_PAGE_SIZE;
4212	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4213	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4214	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
4215	# else
4216	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4217	# endif
4218	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4219	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4220	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4221	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4222	# endif
4223	if (cb != ~(RTGCPTR)0)
4224	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
4225
4226	/** @todo call the other two PGMAssert() functions. /
4227
4228	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4229	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4230
4231	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
4232	{
4233	PPGMPOOLPAGE pShwPdpt = NULL;
4234	PX86PML4E pPml4eSrc;
4235	PX86PML4E pPml4eDst;
4236	RTGCPHYS GCPhysPdptSrc;
4237
4238	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
4239	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
4240
4241	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
4242	if (!(pPml4eDst->u & X86_PML4E_P))
4243	{
4244	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4245	continue;
4246	}
4247
4248	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
4249	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
4250
4251	if ((pPml4eSrc->u & X86_PML4E_P) != (pPml4eDst->u & X86_PML4E_P))
4252	{
4253	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4254	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4255	cErrors++;
4256	continue;
4257	}
4258
4259	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
4260	{
4261	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
4262	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4263	cErrors++;
4264	continue;
4265	}
4266
4267	if ( (pPml4eDst->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX))
4268	!= (pPml4eSrc->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX)))
4269	{
4270	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4271	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4272	cErrors++;
4273	continue;
4274	}
4275	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4276	{
4277	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4278
4279	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
4280	/*
4281	* Check the PDPTEs too.
4282	*/
4283	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
4284
4285	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
4286	{
4287	unsigned iPDSrc = 0; /* initialized to shut up gcc */
4288	PPGMPOOLPAGE pShwPde = NULL;
4289	PX86PDPE pPdpeDst;
4290	RTGCPHYS GCPhysPdeSrc;
4291	X86PDPE PdpeSrc;
4292	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
4293	# if PGM_GST_TYPE == PGM_TYPE_PAE
4294	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
4295	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
4296	# else
4297	PX86PML4E pPml4eSrcIgn;
4298	PX86PDPT pPdptDst;
4299	PX86PDPAE pPDDst;
4300	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
4301
4302	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
4303	if (rc != VINF_SUCCESS)
4304	{
4305	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
4306	GCPtr += 512 * _2M;
4307	continue; /* next PDPTE */
4308	}
4309	Assert(pPDDst);
4310	# endif
4311	Assert(iPDSrc == 0);
4312
4313	pPdpeDst = &pPdptDst->a[iPdpt];
4314
4315	if (!(pPdpeDst->u & X86_PDPE_P))
4316	{
4317	GCPtr += 512 * _2M;
4318	continue; /* next PDPTE */
4319	}
4320
4321	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
4322	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
4323
4324	if ((pPdpeDst->u & X86_PDPE_P) != (PdpeSrc.u & X86_PDPE_P))
4325	{
4326	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4327	GCPtr += 512 * _2M;
4328	cErrors++;
4329	continue;
4330	}
4331
4332	if (GCPhysPdeSrc != pShwPde->GCPhys)
4333	{
4334	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4335	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4336	# else
4337	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4338	# endif
4339	GCPtr += 512 * _2M;
4340	cErrors++;
4341	continue;
4342	}
4343
4344	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4345	if ( (pPdpeDst->u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX))
4346	!= (PdpeSrc.u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX)))
4347	{
4348	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4349	GCPtr += 512 * _2M;
4350	cErrors++;
4351	continue;
4352	}
4353	# endif
4354
4355	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4356	{
4357	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4358	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4359	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4360	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4361	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4362	# endif
4363	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4364	/*
4365	* Iterate the shadow page directory.
4366	*/
4367	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4368	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4369
4370	for (;
4371	iPDDst < cPDEs;
4372	iPDDst++, GCPtr += cIncrement)
4373	{
4374	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4375	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4376	# else
4377	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4378	# endif
4379	if ( (PdeDst.u & X86_PDE_P)
4380	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) )
4381	{
4382	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4383	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4384	if (!pPoolPage)
4385	{
4386	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4387	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4388	cErrors++;
4389	continue;
4390	}
4391	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4392
4393	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4394	{
4395	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4396	GCPtr, (uint64_t)PdeDst.u));
4397	cErrors++;
4398	}
4399
4400	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4401	{
4402	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4403	GCPtr, (uint64_t)PdeDst.u));
4404	cErrors++;
4405	}
4406
4407	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4408	if (!(PdeSrc.u & X86_PDE_P))
4409	{
4410	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4411	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4412	cErrors++;
4413	continue;
4414	}
4415
4416	if ( !(PdeSrc.u & X86_PDE_PS)
4417	\|\| !fBigPagesSupported)
4418	{
4419	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4420	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4421	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
4422	# endif
4423	}
4424	else
4425	{
4426	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4427	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4428	{
4429	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4430	GCPtr, (uint64_t)PdeSrc.u));
4431	cErrors++;
4432	continue;
4433	}
4434	# endif
4435	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4436	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4437	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4438	# endif
4439	}
4440
4441	if ( pPoolPage->enmKind
4442	!= (!(PdeSrc.u & X86_PDE_PS) \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4443	{
4444	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4445	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4446	cErrors++;
4447	}
4448
4449	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4450	if (!pPhysPage)
4451	{
4452	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4453	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4454	cErrors++;
4455	continue;
4456	}
4457
4458	if (GCPhysGst != pPoolPage->GCPhys)
4459	{
4460	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4461	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4462	cErrors++;
4463	continue;
4464	}
4465
4466	if ( !(PdeSrc.u & X86_PDE_PS)
4467	\|\| !fBigPagesSupported)
4468	{
4469	/*
4470	* Page Table.
4471	*/
4472	const GSTPT *pPTSrc;
4473	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(GUEST_PAGE_SIZE - 1)),
4474	&pPTSrc);
4475	if (RT_FAILURE(rc))
4476	{
4477	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4478	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4479	cErrors++;
4480	continue;
4481	}
4482	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4483	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4484	{
4485	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4486	// (This problem will go away when/if we shadow multiple CR3s.)
4487	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4488	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4489	cErrors++;
4490	continue;
4491	}
4492	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4493	{
4494	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4495	GCPtr, (uint64_t)PdeDst.u));
4496	cErrors++;
4497	continue;
4498	}
4499
4500	/* iterate the page table. */
4501	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4502	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4503	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4504	# else
4505	const unsigned offPTSrc = 0;
4506	# endif
4507	for (unsigned iPT = 0, off = 0;
4508	iPT < RT_ELEMENTS(pPTDst->a);
4509	iPT++, off += GUEST_PAGE_SIZE)
4510	{
4511	const SHWPTE PteDst = pPTDst->a[iPT];
4512
4513	/* skip not-present and dirty tracked entries. */
4514	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4515	continue;
4516	Assert(SHW_PTE_IS_P(PteDst));
4517
4518	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4519	if (!(PteSrc.u & X86_PTE_P))
4520	{
4521	# ifdef IN_RING3
4522	PGMAssertHandlerAndFlagsInSync(pVM);
4523	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4524	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4525	0, 0, UINT64_MAX, 99, NULL);
4526	# endif
4527	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4528	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4529	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4530	cErrors++;
4531	continue;
4532	}
4533
4534	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4535	# if 1 /** @todo sync accessed bit properly... */
4536	fIgnoreFlags \|= X86_PTE_A;
4537	# endif
4538
4539	/* match the physical addresses */
4540	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4541	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4542
4543	# ifdef IN_RING3
4544	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4545	if (RT_FAILURE(rc))
4546	{
4547	# if 0
4548	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4549	{
4550	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4551	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4552	cErrors++;
4553	continue;
4554	}
4555	# endif
4556	}
4557	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4558	{
4559	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4560	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4561	cErrors++;
4562	continue;
4563	}
4564	# endif
4565
4566	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4567	if (!pPhysPage)
4568	{
4569	# if 0
4570	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4571	{
4572	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4573	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4574	cErrors++;
4575	continue;
4576	}
4577	# endif
4578	if (SHW_PTE_IS_RW(PteDst))
4579	{
4580	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4581	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4582	cErrors++;
4583	}
4584	fIgnoreFlags \|= X86_PTE_RW;
4585	}
4586	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4587	{
4588	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4589	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4590	cErrors++;
4591	continue;
4592	}
4593
4594	/* flags */
4595	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4596	{
4597	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4598	{
4599	if (SHW_PTE_IS_RW(PteDst))
4600	{
4601	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4602	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4603	cErrors++;
4604	continue;
4605	}
4606	fIgnoreFlags \|= X86_PTE_RW;
4607	}
4608	else
4609	{
4610	if ( SHW_PTE_IS_P(PteDst)
4611	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4612	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4613	# endif
4614	)
4615	{
4616	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4617	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4618	cErrors++;
4619	continue;
4620	}
4621	fIgnoreFlags \|= X86_PTE_P;
4622	}
4623	}
4624	else
4625	{
4626	if ((PteSrc.u & (X86_PTE_RW \| X86_PTE_D)) == X86_PTE_RW)
4627	{
4628	if (SHW_PTE_IS_RW(PteDst))
4629	{
4630	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4631	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4632	cErrors++;
4633	continue;
4634	}
4635	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4636	{
4637	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4638	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4639	cErrors++;
4640	continue;
4641	}
4642	if (SHW_PTE_IS_D(PteDst))
4643	{
4644	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4645	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4646	cErrors++;
4647	}
4648	# if 0 /** @todo sync access bit properly... */
4649	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4650	{
4651	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4652	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4653	cErrors++;
4654	}
4655	fIgnoreFlags \|= X86_PTE_RW;
4656	# else
4657	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4658	# endif
4659	}
4660	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4661	{
4662	/* access bit emulation (not implemented). */
4663	if ((PteSrc.u & X86_PTE_A) \|\| SHW_PTE_IS_P(PteDst))
4664	{
4665	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4666	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4667	cErrors++;
4668	continue;
4669	}
4670	if (!SHW_PTE_IS_A(PteDst))
4671	{
4672	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4673	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4674	cErrors++;
4675	}
4676	fIgnoreFlags \|= X86_PTE_P;
4677	}
4678	# ifdef DEBUG_sandervl
4679	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4680	# endif
4681	}
4682
4683	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4684	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4685	)
4686	{
4687	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4688	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4689	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4690	cErrors++;
4691	continue;
4692	}
4693	} /* foreach PTE */
4694	}
4695	else
4696	{
4697	/*
4698	* Big Page.
4699	*/
4700	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4701	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
4702	{
4703	if (PdeDst.u & X86_PDE_RW)
4704	{
4705	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4706	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4707	cErrors++;
4708	continue;
4709	}
4710	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4711	{
4712	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4713	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4714	cErrors++;
4715	continue;
4716	}
4717	# if 0 /** @todo sync access bit properly... */
4718	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4719	{
4720	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4721	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4722	cErrors++;
4723	}
4724	fIgnoreFlags \|= X86_PTE_RW;
4725	# else
4726	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4727	# endif
4728	}
4729	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4730	{
4731	/* access bit emulation (not implemented). */
4732	if ((PdeSrc.u & X86_PDE_A) \|\| SHW_PDE_IS_P(PdeDst))
4733	{
4734	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4735	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4736	cErrors++;
4737	continue;
4738	}
4739	if (!SHW_PDE_IS_A(PdeDst))
4740	{
4741	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4742	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4743	cErrors++;
4744	}
4745	fIgnoreFlags \|= X86_PTE_P;
4746	}
4747
4748	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4749	{
4750	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4751	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4752	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4753	cErrors++;
4754	}
4755
4756	/* iterate the page table. */
4757	for (unsigned iPT = 0, off = 0;
4758	iPT < RT_ELEMENTS(pPTDst->a);
4759	iPT++, off += GUEST_PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + GUEST_PAGE_SIZE))
4760	{
4761	const SHWPTE PteDst = pPTDst->a[iPT];
4762
4763	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4764	{
4765	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4766	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4767	cErrors++;
4768	}
4769
4770	/* skip not-present entries. */
4771	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4772	continue;
4773
4774	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4775
4776	/* match the physical addresses */
4777	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4778
4779	# ifdef IN_RING3
4780	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4781	if (RT_FAILURE(rc))
4782	{
4783	# if 0
4784	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4785	{
4786	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4787	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4788	cErrors++;
4789	}
4790	# endif
4791	}
4792	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4793	{
4794	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4795	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4796	cErrors++;
4797	continue;
4798	}
4799	# endif
4800	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4801	if (!pPhysPage)
4802	{
4803	# if 0 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4804	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4805	{
4806	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4807	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4808	cErrors++;
4809	continue;
4810	}
4811	# endif
4812	if (SHW_PTE_IS_RW(PteDst))
4813	{
4814	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4815	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4816	cErrors++;
4817	}
4818	fIgnoreFlags \|= X86_PTE_RW;
4819	}
4820	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4821	{
4822	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4823	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4824	cErrors++;
4825	continue;
4826	}
4827
4828	/* flags */
4829	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4830	{
4831	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4832	{
4833	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4834	{
4835	if (SHW_PTE_IS_RW(PteDst))
4836	{
4837	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4838	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4839	cErrors++;
4840	continue;
4841	}
4842	fIgnoreFlags \|= X86_PTE_RW;
4843	}
4844	}
4845	else
4846	{
4847	if ( SHW_PTE_IS_P(PteDst)
4848	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4849	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4850	# endif
4851	)
4852	{
4853	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4854	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4855	cErrors++;
4856	continue;
4857	}
4858	fIgnoreFlags \|= X86_PTE_P;
4859	}
4860	}
4861
4862	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4863	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4864	)
4865	{
4866	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4867	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4868	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4869	cErrors++;
4870	continue;
4871	}
4872	} /* for each PTE */
4873	}
4874	}
4875	/* not present */
4876
4877	} /* for each PDE */
4878
4879	} /* for each PDPTE */
4880
4881	} /* for each PML4E */
4882
4883	# ifdef DEBUG
4884	if (cErrors)
4885	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4886	# endif
4887	# endif /* GST is in {32BIT, PAE, AMD64} */
4888	return cErrors;
4889	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
4890	}
4891	#endif /* VBOX_STRICT */
4892
4893
4894	/**
4895	* Sets up the CR3 for shadow paging
4896	*
4897	* @returns Strict VBox status code.
4898	* @retval VINF_SUCCESS.
4899	*
4900	* @param pVCpu The cross context virtual CPU structure.
4901	* @param GCPhysCR3 The physical address in the CR3 register. (A20 mask
4902	* already applied.)
4903	*/
4904	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
4905	{
4906	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4907	int rc = VINF_SUCCESS;
4908
4909	/* Update guest paging info. */
4910	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4911	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4912	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4913
4914	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4915	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4916
4917	# if PGM_GST_TYPE == PGM_TYPE_PAE
4918	if ( !pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped)
4919	\|\| pVCpu->pgm.s.GCPhysPaeCR3 != GCPhysCR3)
4920	# endif
4921	{
4922	/*
4923	* Map the page CR3 points at.
4924	*/
4925	RTHCPTR HCPtrGuestCR3;
4926	rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCR3);
4927	if (RT_SUCCESS(rc))
4928	{
4929	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4930	# ifdef IN_RING3
4931	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
4932	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
4933	# else
4934	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
4935	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
4936	# endif
4937
4938	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4939	# ifdef IN_RING3
4940	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
4941	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
4942	# else
4943	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
4944	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
4945	# endif
4946
4947	/*
4948	* Update CPUM and map the 4 PDs too.
4949	*/
4950	X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
4951	memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
4952	PGMGstMapPaePdpes(pVCpu, &aGstPaePdpes[0]);
4953
4954	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
4955	# ifdef IN_RING3
4956	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
4957	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
4958	# else
4959	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
4960	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
4961	# endif
4962
4963	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4964	# ifdef IN_RING3
4965	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
4966	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
4967	# else
4968	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
4969	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
4970	# endif
4971	# endif
4972	}
4973	else
4974	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4975	}
4976	#endif
4977
4978	/*
4979	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
4980	*/
4981	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4982	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4983	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4984	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4985	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4986
4987	Assert(!pVM->pgm.s.fNestedPaging);
4988	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4989
4990	/*
4991	* Update the shadow root page as well since that's not fixed.
4992	*/
4993	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4994	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4995	PPGMPOOLPAGE pNewShwPageCR3;
4996
4997	PGM_LOCK_VOID(pVM);
4998
4999	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5000	if (pPool->cDirtyPages)
5001	pgmPoolResetDirtyPages(pVM);
5002	# endif
5003
5004	Assert(!(GCPhysCR3 >> (GUEST_PAGE_SHIFT + 32))); /** @todo what is this for? */
5005	int const rc2 = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE,
5006	PGM_A20_IS_ENABLED(pVCpu), NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/, &pNewShwPageCR3);
5007	AssertFatalRC(rc2);
5008
5009	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
5010	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
5011
5012	/* Set the current hypervisor CR3. */
5013	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
5014
5015	/* Clean up the old CR3 root. */
5016	if ( pOldShwPageCR3
5017	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
5018	{
5019	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
5020
5021	/* Mark the page as unlocked; allow flushing again. */
5022	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
5023
5024	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
5025	}
5026	PGM_UNLOCK(pVM);
5027	# else
5028	NOREF(GCPhysCR3);
5029	# endif
5030
5031	return rc;
5032	}
5033
5034	/**
5035	* Unmaps the shadow CR3.
5036	*
5037	* @returns VBox status, no specials.
5038	* @param pVCpu The cross context virtual CPU structure.
5039	*/
5040	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
5041	{
5042	LogFlow(("UnmapCR3\n"));
5043
5044	int rc = VINF_SUCCESS;
5045	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5046
5047	/*
5048	* Update guest paging info.
5049	*/
5050	#if PGM_GST_TYPE == PGM_TYPE_32BIT
5051	pVCpu->pgm.s.pGst32BitPdR3 = 0;
5052	pVCpu->pgm.s.pGst32BitPdR0 = 0;
5053
5054	#elif PGM_GST_TYPE == PGM_TYPE_PAE
5055	pVCpu->pgm.s.pGstPaePdptR3 = 0;
5056	pVCpu->pgm.s.pGstPaePdptR0 = 0;
5057	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
5058	{
5059	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
5060	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
5061	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
5062	}
5063
5064	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
5065	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
5066	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
5067
5068	#else /* prot/real mode stub */
5069	/* nothing to do */
5070	#endif
5071
5072	/** @todo This should probably be moved inside \#if PGM_GST_TYPE == PGM_TYPE_PAE? */
5073	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5074	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5075	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
5076
5077	/*
5078	* Update shadow paging info.
5079	*/
5080	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5081	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5082	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
5083	# if PGM_GST_TYPE != PGM_TYPE_REAL
5084	Assert(!pVM->pgm.s.fNestedPaging);
5085	# endif
5086	PGM_LOCK_VOID(pVM);
5087
5088	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
5089	{
5090	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5091
5092	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5093	if (pPool->cDirtyPages)
5094	pgmPoolResetDirtyPages(pVM);
5095	# endif
5096
5097	/* Mark the page as unlocked; allow flushing again. */
5098	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
5099
5100	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
5101	pVCpu->pgm.s.pShwPageCR3R3 = 0;
5102	pVCpu->pgm.s.pShwPageCR3R0 = 0;
5103	}
5104
5105	PGM_UNLOCK(pVM);
5106	#endif
5107
5108	return rc;
5109	}
5110

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 96962

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