PGMAllBth.h@ 10013

Last change on this file since 10013 was 10013, checked in by vboxsync, 17 years ago
AMD64 shadow & real or protected mode without paging combo. Flush TLB when the EFER msr changes certain bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 188.0 KB

Line
1	/* $Id: PGMAllBth.h 10013 2008-06-30 11:39:41Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69	/**
70	* #PF Handler for raw-mode guest execution.
71	*
72	* @returns VBox status code (appropriate for trap handling and GC return).
73	* @param pVM VM Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	*/
78	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
79	{
80	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
81	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
82
83	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
84	/*
85	* Hide the instruction fetch trap indicator for now.
86	*/
87	/** @todo NXE will change this and we must fix NXE in the switcher too! */
88	if (uErr & X86_TRAP_PF_ID)
89	{
90	uErr &= ~X86_TRAP_PF_ID;
91	TRPMSetErrorCode(pVM, uErr);
92	}
93	# endif
94
95	/*
96	* Get PDs.
97	*/
98	int rc;
99	# if PGM_WITH_PAGING(PGM_GST_TYPE)
100	# if PGM_GST_TYPE == PGM_TYPE_32BIT
101	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
102	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
103
104	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
105
106	# if PGM_GST_TYPE == PGM_TYPE_PAE
107	unsigned iPDSrc;
108	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
109
110	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
111	unsigned iPDSrc;
112	PX86PML4E pPml4eSrc;
113	X86PDPE PdpeSrc;
114	PGSTPD pPDSrc;
115
116	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
117	Assert(pPml4eSrc);
118	# endif
119	/* Quick check for a valid guest trap. */
120	if (!pPDSrc)
121	{
122	LogFlow(("Trap0eHandler: guest PDPTR not present CR3=%VGp\n", (CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK)));
123	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
124	TRPMSetErrorCode(pVM, uErr);
125	return VINF_EM_RAW_GUEST_TRAP;
126	}
127	# endif
128	# else
129	PGSTPD pPDSrc = NULL;
130	const unsigned iPDSrc = 0;
131	# endif
132
133	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
134	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
135	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
136	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
137	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
138	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
139
140	# if PGM_GST_TYPE == PGM_TYPE_PAE
141	/* Did we mark the PDPT as not present in SyncCR3? */
142	unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
143	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
144	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
145
146	# endif
147
148	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
149	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
150	PX86PDPAE pPDDst;
151	# if PGM_GST_TYPE == PGM_TYPE_PROT
152	/* AMD-V nested paging */
153	X86PML4E Pml4eSrc;
154	X86PDPE PdpeSrc;
155	PX86PML4E pPml4eSrc = &Pml4eSrc;
156
157	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
158	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
159	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
160	# endif
161
162	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
163	if (rc != VINF_SUCCESS)
164	{
165	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
166	return rc;
167	}
168	Assert(pPDDst);
169	# endif
170
171	# if PGM_WITH_PAGING(PGM_GST_TYPE)
172	/*
173	* If we successfully correct the write protection fault due to dirty bit
174	* tracking, or this page fault is a genuine one, then return immediately.
175	*/
176	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
177	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
178	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
179	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
180	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
181	{
182	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
183	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
184	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
185	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
186	}
187
188	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
189	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
190
191	/*
192	* A common case is the not-present error caused by lazy page table syncing.
193	*
194	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
195	* so we can safely assume that the shadow PT is present when calling SyncPage later.
196	*
197	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
198	* of mapping conflict and defer to SyncCR3 in R3.
199	* (Again, we do NOT support access handlers for non-present guest pages.)
200	*
201	*/
202	# if PGM_WITH_PAGING(PGM_GST_TYPE)
203	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
204	# else
205	GSTPDE PdeSrc;
206	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
207	PdeSrc.n.u1Present = 1;
208	PdeSrc.n.u1Write = 1;
209	PdeSrc.n.u1Accessed = 1;
210	PdeSrc.n.u1User = 1;
211	# endif
212	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
213	&& !pPDDst->a[iPDDst].n.u1Present
214	&& PdeSrc.n.u1Present
215	)
216
217	{
218	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
219	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
220	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
221	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
222	if (VBOX_SUCCESS(rc))
223	{
224	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
225	return rc;
226	}
227	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
228	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
229	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
230	return VINF_PGM_SYNC_CR3;
231	}
232
233	# if PGM_WITH_PAGING(PGM_GST_TYPE)
234	/*
235	* Check if this address is within any of our mappings.
236	*
237	* This is very fast and it's gonna save us a bit of effort below and prevent
238	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
239	* (BTW, it's impossible to have physical access handlers in a mapping.)
240	*/
241	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
242	{
243	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
244	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
245	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
246	{
247	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
248	break;
249	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
250	{
251	/*
252	* The first thing we check is if we've got an undetected conflict.
253	*/
254	if (!pVM->pgm.s.fMappingsFixed)
255	{
256	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
257	while (iPT-- > 0)
258	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
259	{
260	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
261	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
262	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
263	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
264	return VINF_PGM_SYNC_CR3;
265	}
266	}
267
268	/*
269	* Check if the fault address is in a virtual page access handler range.
270	*/
271	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
272	if ( pCur
273	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
274	&& uErr & X86_TRAP_PF_RW)
275	{
276	# ifdef IN_GC
277	STAM_PROFILE_START(&pCur->Stat, h);
278	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
279	STAM_PROFILE_STOP(&pCur->Stat, h);
280	# else
281	AssertFailed();
282	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
283	# endif
284	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
286	return rc;
287	}
288
289	/*
290	* Pretend we're not here and let the guest handle the trap.
291	*/
292	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
293	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
294	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
295	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
296	return VINF_EM_RAW_GUEST_TRAP;
297	}
298	}
299	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
300	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
301	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
302
303	/*
304	* Check if this fault address is flagged for special treatment,
305	* which means we'll have to figure out the physical address and
306	* check flags associated with it.
307	*
308	* ASSUME that we can limit any special access handling to pages
309	* in page tables which the guest believes to be present.
310	*/
311	if (PdeSrc.n.u1Present)
312	{
313	RTGCPHYS GCPhys = NIL_RTGCPHYS;
314
315	# if PGM_WITH_PAGING(PGM_GST_TYPE)
316	# if PGM_GST_TYPE == PGM_TYPE_AMD64
317	bool fBigPagesSupported = true;
318	# else
319	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
320	# endif
321	if ( PdeSrc.b.u1Size
322	&& fBigPagesSupported)
323	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
324	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
325	else
326	{
327	PGSTPT pPTSrc;
328	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
329	if (VBOX_SUCCESS(rc))
330	{
331	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
332	if (pPTSrc->a[iPTESrc].n.u1Present)
333	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
334	}
335	}
336	# else
337	/* No paging so the fault address is the physical address */
338	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
339	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
340
341	/*
342	* If we have a GC address we'll check if it has any flags set.
343	*/
344	if (GCPhys != NIL_RTGCPHYS)
345	{
346	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
347
348	PPGMPAGE pPage;
349	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
350	if (VBOX_SUCCESS(rc))
351	{
352	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
353	{
354	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
355	{
356	/*
357	* Physical page access handler.
358	*/
359	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
360	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
361	if (pCur)
362	{
363	# ifdef PGM_SYNC_N_PAGES
364	/*
365	* If the region is write protected and we got a page not present fault, then sync
366	* the pages. If the fault was caused by a read, then restart the instruction.
367	* In case of write access continue to the GC write handler.
368	*
369	* ASSUMES that there is only one handler per page or that they have similar write properties.
370	*/
371	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
372	&& !(uErr & X86_TRAP_PF_P))
373	{
374	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
375	if ( VBOX_FAILURE(rc)
376	\|\| !(uErr & X86_TRAP_PF_RW)
377	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
378	{
379	AssertRC(rc);
380	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
381	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
382	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
383	return rc;
384	}
385	}
386	# endif
387
388	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
389	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
390	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
391
392	#if defined(IN_GC) \|\| defined(IN_RING0)
393	if (CTXALLSUFF(pCur->pfnHandler))
394	{
395	STAM_PROFILE_START(&pCur->Stat, h);
396	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
397	STAM_PROFILE_STOP(&pCur->Stat, h);
398	}
399	else
400	#endif
401	rc = VINF_EM_RAW_EMULATE_INSTR;
402	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
403	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
404	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
405	return rc;
406	}
407	}
408	# if PGM_WITH_PAGING(PGM_GST_TYPE)
409	else
410	{
411	# ifdef PGM_SYNC_N_PAGES
412	/*
413	* If the region is write protected and we got a page not present fault, then sync
414	* the pages. If the fault was caused by a read, then restart the instruction.
415	* In case of write access continue to the GC write handler.
416	*/
417	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
418	&& !(uErr & X86_TRAP_PF_P))
419	{
420	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
421	if ( VBOX_FAILURE(rc)
422	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
423	\|\| !(uErr & X86_TRAP_PF_RW))
424	{
425	AssertRC(rc);
426	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
427	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
428	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
429	return rc;
430	}
431	}
432	# endif
433	/*
434	* Ok, it's an virtual page access handler.
435	*
436	* Since it's faster to search by address, we'll do that first
437	* and then retry by GCPhys if that fails.
438	*/
439	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
440	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
441	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
442	*/
443	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
444	if (pCur)
445	{
446	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
447	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
448	\|\| !(uErr & X86_TRAP_PF_P)
449	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
450	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
451
452	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
453	&& ( uErr & X86_TRAP_PF_RW
454	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
455	{
456	# ifdef IN_GC
457	STAM_PROFILE_START(&pCur->Stat, h);
458	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
459	STAM_PROFILE_STOP(&pCur->Stat, h);
460	# else
461	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
462	# endif
463	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
464	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
465	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
466	return rc;
467	}
468	/* Unhandled part of a monitored page */
469	}
470	else
471	{
472	/* Check by physical address. */
473	PPGMVIRTHANDLER pCur;
474	unsigned iPage;
475	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
476	&pCur, &iPage);
477	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
478	if ( pCur
479	&& ( uErr & X86_TRAP_PF_RW
480	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
481	{
482	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
483	# ifdef IN_GC
484	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
485	Assert(off < pCur->cb);
486	STAM_PROFILE_START(&pCur->Stat, h);
487	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
488	STAM_PROFILE_STOP(&pCur->Stat, h);
489	# else
490	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
491	# endif
492	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
493	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
494	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
495	return rc;
496	}
497	}
498	}
499	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
500
501	/*
502	* There is a handled area of the page, but this fault doesn't belong to it.
503	* We must emulate the instruction.
504	*
505	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
506	* we first check if this was a page-not-present fault for a page with only
507	* write access handlers. Restart the instruction if it wasn't a write access.
508	*/
509	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
510
511	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
512	&& !(uErr & X86_TRAP_PF_P))
513	{
514	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
515	if ( VBOX_FAILURE(rc)
516	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
517	\|\| !(uErr & X86_TRAP_PF_RW))
518	{
519	AssertRC(rc);
520	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
521	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
522	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
523	return rc;
524	}
525	}
526
527	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
528	* It's writing to an unhandled part of the LDT page several million times.
529	*/
530	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
531	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
532	rc, pPage->HCPhys,
533	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
534	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
535	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
536	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
537	return rc;
538	} /* if any kind of handler */
539
540	# if PGM_WITH_PAGING(PGM_GST_TYPE)
541	if (uErr & X86_TRAP_PF_P)
542	{
543	/*
544	* The page isn't marked, but it might still be monitored by a virtual page access handler.
545	* (ASSUMES no temporary disabling of virtual handlers.)
546	*/
547	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
548	* we should correct both the shadow page table and physical memory flags, and not only check for
549	* accesses within the handler region but for access to pages with virtual handlers. */
550	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
551	if (pCur)
552	{
553	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
554	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
555	\|\| !(uErr & X86_TRAP_PF_P)
556	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
557	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
558
559	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
560	&& ( uErr & X86_TRAP_PF_RW
561	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
562	{
563	# ifdef IN_GC
564	STAM_PROFILE_START(&pCur->Stat, h);
565	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
566	STAM_PROFILE_STOP(&pCur->Stat, h);
567	# else
568	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
569	# endif
570	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
571	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
572	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
573	return rc;
574	}
575	}
576	}
577	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
578	}
579	else
580	{
581	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
582	* back to the recompiler to emulate the instruction.
583	*/
584	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
585	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersInvalid);
586	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
587	return VINF_EM_RAW_EMULATE_INSTR;
588	}
589
590	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
591
592	# ifdef PGM_OUT_OF_SYNC_IN_GC
593	/*
594	* We are here only if page is present in Guest page tables and trap is not handled
595	* by our handlers.
596	* Check it for page out-of-sync situation.
597	*/
598	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
599
600	if (!(uErr & X86_TRAP_PF_P))
601	{
602	/*
603	* Page is not present in our page tables.
604	* Try to sync it!
605	* BTW, fPageShw is invalid in this branch!
606	*/
607	if (uErr & X86_TRAP_PF_US)
608	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
609	else /* supervisor */
610	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
611
612	# if defined(LOG_ENABLED) && !defined(IN_RING0)
613	RTGCPHYS GCPhys;
614	uint64_t fPageGst;
615	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
616	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
617	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
618	# endif /* LOG_ENABLED */
619
620	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
621	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
622	{
623	uint64_t fPageGst;
624	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
625	if ( VBOX_SUCCESS(rc)
626	&& !(fPageGst & X86_PTE_US))
627	{
628	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
629	if ( pvFault == (RTGCPTR)pRegFrame->eip
630	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
631	# ifdef CSAM_DETECT_NEW_CODE_PAGES
632	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
633	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
634	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
635	)
636	{
637	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
638	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
639	if (rc != VINF_SUCCESS)
640	{
641	/*
642	* CSAM needs to perform a job in ring 3.
643	*
644	* Sync the page before going to the host context; otherwise we'll end up in a loop if
645	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
646	*/
647	LogFlow(("CSAM ring 3 job\n"));
648	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
649	AssertRC(rc2);
650
651	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
652	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
653	return rc;
654	}
655	}
656	# ifdef CSAM_DETECT_NEW_CODE_PAGES
657	else
658	if ( uErr == X86_TRAP_PF_RW
659	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
660	&& pRegFrame->ecx < 0x10000
661	)
662	{
663	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
664	* to detect loading of new code pages.
665	*/
666
667	/*
668	* Decode the instruction.
669	*/
670	RTGCPTR PC;
671	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
672	if (rc == VINF_SUCCESS)
673	{
674	DISCPUSTATE Cpu;
675	uint32_t cbOp;
676	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
677
678	/* For now we'll restrict this to rep movsw/d instructions */
679	if ( rc == VINF_SUCCESS
680	&& Cpu.pCurInstr->opcode == OP_MOVSWD
681	&& (Cpu.prefix & PREFIX_REP))
682	{
683	CSAMMarkPossibleCodePage(pVM, pvFault);
684	}
685	}
686	}
687	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
688
689	/*
690	* Mark this page as safe.
691	*/
692	/** @todo not correct for pages that contain both code and data!! */
693	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
694	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
695	}
696	}
697	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
698	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
699	if (VBOX_SUCCESS(rc))
700	{
701	/* The page was successfully synced, return to the guest. */
702	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
703	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
704	return VINF_SUCCESS;
705	}
706	}
707	else
708	{
709	/*
710	* A side effect of not flushing global PDEs are out of sync pages due
711	* to physical monitored regions, that are no longer valid.
712	* Assume for now it only applies to the read/write flag
713	*/
714	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
715	{
716	if (uErr & X86_TRAP_PF_US)
717	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
718	else /* supervisor */
719	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
720
721
722	/*
723	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
724	*/
725	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
726	if (VBOX_SUCCESS(rc))
727	{
728	/*
729	* Page was successfully synced, return to guest.
730	*/
731	# ifdef VBOX_STRICT
732	RTGCPHYS GCPhys;
733	uint64_t fPageGst;
734	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
735	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
736	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
737
738	uint64_t fPageShw;
739	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
740	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
741	# endif /* VBOX_STRICT */
742	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
743	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
744	return VINF_SUCCESS;
745	}
746
747	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
748	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
749	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
750	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
751	{
752	uint64_t fPageGst;
753	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
754	if ( VBOX_SUCCESS(rc)
755	&& !(fPageGst & X86_PTE_RW))
756	{
757	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
758	if (VBOX_SUCCESS(rc))
759	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
760	else
761	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
762	return rc;
763	}
764	else
765	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
766	}
767
768	}
769
770	# if PGM_WITH_PAGING(PGM_GST_TYPE)
771	# ifdef VBOX_STRICT
772	/*
773	* Check for VMM page flags vs. Guest page flags consistency.
774	* Currently only for debug purposes.
775	*/
776	if (VBOX_SUCCESS(rc))
777	{
778	/* Get guest page flags. */
779	uint64_t fPageGst;
780	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
781	if (VBOX_SUCCESS(rc))
782	{
783	uint64_t fPageShw;
784	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
785
786	/*
787	* Compare page flags.
788	* Note: we have AVL, A, D bits desynched.
789	*/
790	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
791	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
792	}
793	else
794	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
795	}
796	else
797	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
798	# endif /* VBOX_STRICT */
799	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
800	}
801	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
802	# endif /* PGM_OUT_OF_SYNC_IN_GC */
803	}
804	else
805	{
806	/*
807	* Page not present in Guest OS or invalid page table address.
808	* This is potential virtual page access handler food.
809	*
810	* For the present we'll say that our access handlers don't
811	* work for this case - we've already discarded the page table
812	* not present case which is identical to this.
813	*
814	* When we perchance find we need this, we will probably have AVL
815	* trees (offset based) to operate on and we can measure their speed
816	* agains mapping a page table and probably rearrange this handling
817	* a bit. (Like, searching virtual ranges before checking the
818	* physical address.)
819	*/
820	}
821	}
822
823
824	# if PGM_WITH_PAGING(PGM_GST_TYPE)
825	/*
826	* Conclusion, this is a guest trap.
827	*/
828	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
829	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
830	return VINF_EM_RAW_GUEST_TRAP;
831	# else
832	/* present, but not a monitored page; perhaps the guest is probing physical memory */
833	return VINF_EM_RAW_EMULATE_INSTR;
834	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
835
836
837	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
838
839	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
840	return VERR_INTERNAL_ERROR;
841	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
842	}
843
844
845	/**
846	* Emulation of the invlpg instruction.
847	*
848	*
849	* @returns VBox status code.
850	*
851	* @param pVM VM handle.
852	* @param GCPtrPage Page to invalidate.
853	*
854	* @remark ASSUMES that the guest is updating before invalidating. This order
855	* isn't required by the CPU, so this is speculative and could cause
856	* trouble.
857	*
858	* @todo Flush page or page directory only if necessary!
859	* @todo Add a #define for simply invalidating the page.
860	*/
861	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
862	{
863	#if PGM_WITH_PAGING(PGM_GST_TYPE) \
864	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
865	int rc;
866
867	LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
868	/*
869	* Get the shadow PD entry and skip out if this PD isn't present.
870	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
871	*/
872	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
873	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
874	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
875	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
876	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
877	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT);
878	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
879	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
880	# else /* AMD64 */
881	/* PML4 */
882	AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
883
884	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
885	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
886	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
887	PX86PDPAE pPDDst;
888	PX86PDPT pPdptDst;
889	PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
890	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
891	if (rc != VINF_SUCCESS)
892	{
893	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
894	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
895	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
896	PGM_INVL_GUEST_TLBS();
897	return VINF_SUCCESS;
898	}
899	Assert(pPDDst);
900
901	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
902	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
903
904	if (!pPdpeDst->n.u1Present)
905	{
906	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
907	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
908	PGM_INVL_GUEST_TLBS();
909	return VINF_SUCCESS;
910	}
911
912	# endif
913
914	const SHWPDE PdeDst = *pPdeDst;
915	if (!PdeDst.n.u1Present)
916	{
917	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
918	return VINF_SUCCESS;
919	}
920
921	/*
922	* Get the guest PD entry and calc big page.
923	*/
924	# if PGM_GST_TYPE == PGM_TYPE_32BIT
925	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
926	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
927	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
928	# else
929	unsigned iPDSrc;
930	# if PGM_GST_TYPE == PGM_TYPE_PAE
931	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
932	# else /* AMD64 */
933	PX86PML4E pPml4eSrc;
934	X86PDPE PdpeSrc;
935	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
936	# endif
937	GSTPDE PdeSrc;
938
939	if (pPDSrc)
940	PdeSrc = pPDSrc->a[iPDSrc];
941	else
942	PdeSrc.u = 0;
943	# endif
944
945	# if PGM_GST_TYPE == PGM_TYPE_AMD64
946	const bool fIsBigPage = PdeSrc.b.u1Size;
947	# else
948	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
949	# endif
950
951	# ifdef IN_RING3
952	/*
953	* If a CR3 Sync is pending we may ignore the invalidate page operation
954	* depending on the kind of sync and if it's a global page or not.
955	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
956	*/
957	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
958	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
959	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
960	&& fIsBigPage
961	&& PdeSrc.b.u1Global
962	)
963	)
964	# else
965	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
966	# endif
967	{
968	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
969	return VINF_SUCCESS;
970	}
971	# endif /* IN_RING3 */
972
973	# if PGM_GST_TYPE == PGM_TYPE_AMD64
974	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
975
976	/* Fetch the pgm pool shadow descriptor. */
977	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
978	Assert(pShwPdpt);
979
980	/* Fetch the pgm pool shadow descriptor. */
981	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
982	Assert(pShwPde);
983
984	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
985	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
986
987	if ( !pPml4eSrc->n.u1Present
988	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
989	{
990	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
991	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
992	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
993	pPml4eDst->u = 0;
994	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
995	PGM_INVL_GUEST_TLBS();
996	return VINF_SUCCESS;
997	}
998	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
999	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1000	{
1001	/*
1002	* Mark not present so we can resync the PML4E when it's used.
1003	*/
1004	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1005	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1006	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1007	pPml4eDst->u = 0;
1008	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1009	PGM_INVL_GUEST_TLBS();
1010	}
1011	else if (!pPml4eSrc->n.u1Accessed)
1012	{
1013	/*
1014	* Mark not present so we can set the accessed bit.
1015	*/
1016	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1017	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1018	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1019	pPml4eDst->u = 0;
1020	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1021	PGM_INVL_GUEST_TLBS();
1022	}
1023
1024	/* Check if the PDPT entry has changed. */
1025	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1026	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1027	if ( !PdpeSrc.n.u1Present
1028	\|\| pShwPde->GCPhys != GCPhysPd)
1029	{
1030	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1031	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1032	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1033	pPdpeDst->u = 0;
1034	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1035	PGM_INVL_GUEST_TLBS();
1036	return VINF_SUCCESS;
1037	}
1038	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1039	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1040	{
1041	/*
1042	* Mark not present so we can resync the PDPTE when it's used.
1043	*/
1044	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1045	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1046	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1047	pPdpeDst->u = 0;
1048	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1049	PGM_INVL_GUEST_TLBS();
1050	}
1051	else if (!PdpeSrc.lm.u1Accessed)
1052	{
1053	/*
1054	* Mark not present so we can set the accessed bit.
1055	*/
1056	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1057	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1058	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1059	pPdpeDst->u = 0;
1060	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1061	PGM_INVL_GUEST_TLBS();
1062	}
1063	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
1064
1065	# if PGM_GST_TYPE == PGM_TYPE_PAE
1066
1067	# endif
1068
1069
1070	/*
1071	* Deal with the Guest PDE.
1072	*/
1073	rc = VINF_SUCCESS;
1074	if (PdeSrc.n.u1Present)
1075	{
1076	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1077	{
1078	/*
1079	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1080	*/
1081	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1082	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1083	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1084	}
1085	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1086	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1087	{
1088	/*
1089	* Mark not present so we can resync the PDE when it's used.
1090	*/
1091	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1092	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1093	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1094	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1095	# else
1096	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1097	# endif
1098	pPdeDst->u = 0;
1099	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1100	PGM_INVL_GUEST_TLBS();
1101	}
1102	else if (!PdeSrc.n.u1Accessed)
1103	{
1104	/*
1105	* Mark not present so we can set the accessed bit.
1106	*/
1107	LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1108	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1109	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1110	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1111	# else
1112	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1113	# endif
1114	pPdeDst->u = 0;
1115	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1116	PGM_INVL_GUEST_TLBS();
1117	}
1118	else if (!fIsBigPage)
1119	{
1120	/*
1121	* 4KB - page.
1122	*/
1123	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1124	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1125	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1126	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1127	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1128	# endif
1129	if (pShwPage->GCPhys == GCPhys)
1130	{
1131	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1132	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1133	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1134	if (pPT->a[iPTEDst].n.u1Present)
1135	{
1136	# ifdef PGMPOOL_WITH_USER_TRACKING
1137	/* This is very unlikely with caching/monitoring enabled. */
1138	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1139	# endif
1140	pPT->a[iPTEDst].u = 0;
1141	}
1142	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1143	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1144	if (VBOX_SUCCESS(rc))
1145	rc = VINF_SUCCESS;
1146	# endif
1147	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
1148	PGM_INVL_PG(GCPtrPage);
1149	}
1150	else
1151	{
1152	/*
1153	* The page table address changed.
1154	*/
1155	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1156	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1157	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1158	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1159	# else
1160	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1161	# endif
1162	pPdeDst->u = 0;
1163	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1164	PGM_INVL_GUEST_TLBS();
1165	}
1166	}
1167	else
1168	{
1169	/*
1170	* 2/4MB - page.
1171	*/
1172	/* Before freeing the page, check if anything really changed. */
1173	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1174	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1175	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1176	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1177	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1178	# endif
1179	if ( pShwPage->GCPhys == GCPhys
1180	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1181	{
1182	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1183	/** @todo PAT */
1184	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1185	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1186	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1187	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1188	{
1189	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1190	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
1191	return VINF_SUCCESS;
1192	}
1193	}
1194
1195	/*
1196	* Ok, the page table is present and it's been changed in the guest.
1197	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1198	* We could do this for some flushes in GC too, but we need an algorithm for
1199	* deciding which 4MB pages containing code likely to be executed very soon.
1200	*/
1201	LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1202	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1203	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1204	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1205	# else
1206	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1207	# endif
1208	pPdeDst->u = 0;
1209	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1210	PGM_INVL_BIG_PG(GCPtrPage);
1211	}
1212	}
1213	else
1214	{
1215	/*
1216	* Page directory is not present, mark shadow PDE not present.
1217	*/
1218	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1219	{
1220	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1221	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1222	# else
1223	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1224	# endif
1225	pPdeDst->u = 0;
1226	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1227	PGM_INVL_PG(GCPtrPage);
1228	}
1229	else
1230	{
1231	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1232	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1233	}
1234	}
1235
1236	return rc;
1237
1238	#else /* guest real and protected mode */
1239	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1240	return VINF_SUCCESS;
1241	#endif
1242	}
1243
1244
1245	#ifdef PGMPOOL_WITH_USER_TRACKING
1246	/**
1247	* Update the tracking of shadowed pages.
1248	*
1249	* @param pVM The VM handle.
1250	* @param pShwPage The shadow page.
1251	* @param HCPhys The physical page we is being dereferenced.
1252	*/
1253	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1254	{
1255	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1256	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1257	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1258
1259	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1260	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1261	* 2. write protect all shadowed pages. I.e. implement caching.
1262	*/
1263	/*
1264	* Find the guest address.
1265	*/
1266	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1267	pRam;
1268	pRam = CTXALLSUFF(pRam->pNext))
1269	{
1270	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1271	while (iPage-- > 0)
1272	{
1273	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1274	{
1275	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1276	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1277	pShwPage->cPresent--;
1278	pPool->cPresent--;
1279	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1280	return;
1281	}
1282	}
1283	}
1284
1285	for (;;)
1286	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1287	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1288	pShwPage->cPresent--;
1289	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1290	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1291	}
1292
1293
1294	/**
1295	* Update the tracking of shadowed pages.
1296	*
1297	* @param pVM The VM handle.
1298	* @param pShwPage The shadow page.
1299	* @param u16 The top 16-bit of the pPage->HCPhys.
1300	* @param pPage Pointer to the guest page. this will be modified.
1301	* @param iPTDst The index into the shadow table.
1302	*/
1303	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1304	{
1305	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1306	/*
1307	* We're making certain assumptions about the placement of cRef and idx.
1308	*/
1309	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1310	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1311
1312	/*
1313	* Just deal with the simple first time here.
1314	*/
1315	if (!u16)
1316	{
1317	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1318	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1319	}
1320	else
1321	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1322
1323	/* write back, trying to be clever... */
1324	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1325	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1326	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1327	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1328
1329	/* update statistics. */
1330	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1331	pShwPage->cPresent++;
1332	if (pShwPage->iFirstPresent > iPTDst)
1333	pShwPage->iFirstPresent = iPTDst;
1334	}
1335	#endif /* PGMPOOL_WITH_USER_TRACKING */
1336
1337
1338	/**
1339	* Creates a 4K shadow page for a guest page.
1340	*
1341	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1342	* physical address. The PdeSrc argument only the flags are used. No page structured
1343	* will be mapped in this function.
1344	*
1345	* @param pVM VM handle.
1346	* @param pPteDst Destination page table entry.
1347	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1348	* Can safely assume that only the flags are being used.
1349	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1350	* @param pShwPage Pointer to the shadow page.
1351	* @param iPTDst The index into the shadow table.
1352	*
1353	* @remark Not used for 2/4MB pages!
1354	*/
1355	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1356	{
1357	if (PteSrc.n.u1Present)
1358	{
1359	/*
1360	* Find the ram range.
1361	*/
1362	PPGMPAGE pPage;
1363	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1364	if (VBOX_SUCCESS(rc))
1365	{
1366	/** @todo investiage PWT, PCD and PAT. */
1367	/*
1368	* Make page table entry.
1369	*/
1370	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1371	SHWPTE PteDst;
1372	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1373	{
1374	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1375	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1376	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1377	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1378	else
1379	{
1380	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1381	PteDst.u = 0;
1382	}
1383	/** @todo count these two kinds. */
1384	}
1385	else
1386	{
1387	/*
1388	* If the page or page directory entry is not marked accessed,
1389	* we mark the page not present.
1390	*/
1391	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1392	{
1393	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1394	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1395	PteDst.u = 0;
1396	}
1397	else
1398	/*
1399	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1400	* when the page is modified.
1401	*/
1402	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1403	{
1404	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1405	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1406	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1407	\| PGM_PTFLAGS_TRACK_DIRTY;
1408	}
1409	else
1410	{
1411	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1412	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1413	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1414	}
1415	}
1416
1417	#ifdef PGMPOOL_WITH_USER_TRACKING
1418	/*
1419	* Keep user track up to date.
1420	*/
1421	if (PteDst.n.u1Present)
1422	{
1423	if (!pPteDst->n.u1Present)
1424	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1425	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1426	{
1427	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1428	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1429	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1430	}
1431	}
1432	else if (pPteDst->n.u1Present)
1433	{
1434	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1435	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1436	}
1437	#endif /* PGMPOOL_WITH_USER_TRACKING */
1438
1439	/*
1440	* Update statistics and commit the entry.
1441	*/
1442	if (!PteSrc.n.u1Global)
1443	pShwPage->fSeenNonGlobal = true;
1444	*pPteDst = PteDst;
1445	}
1446	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1447	/** @todo count these. */
1448	}
1449	else
1450	{
1451	/*
1452	* Page not-present.
1453	*/
1454	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1455	#ifdef PGMPOOL_WITH_USER_TRACKING
1456	/* Keep user track up to date. */
1457	if (pPteDst->n.u1Present)
1458	{
1459	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1460	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1461	}
1462	#endif /* PGMPOOL_WITH_USER_TRACKING */
1463	pPteDst->u = 0;
1464	/** @todo count these. */
1465	}
1466	}
1467
1468
1469	/**
1470	* Syncs a guest OS page.
1471	*
1472	* There are no conflicts at this point, neither is there any need for
1473	* page table allocations.
1474	*
1475	* @returns VBox status code.
1476	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1477	* @param pVM VM handle.
1478	* @param PdeSrc Page directory entry of the guest.
1479	* @param GCPtrPage Guest context page address.
1480	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1481	* @param uErr Fault error (X86_TRAP_PF_*).
1482	*/
1483	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1484	{
1485	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1486
1487	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1488	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1489	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1490	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1491
1492	# if PGM_WITH_NX(PGM_GST_TYPE)
1493	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1494	# endif
1495
1496	/*
1497	* Assert preconditions.
1498	*/
1499	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1500	Assert(PdeSrc.n.u1Present);
1501	Assert(cPages);
1502
1503	/*
1504	* Get the shadow PDE, find the shadow page table in the pool.
1505	*/
1506	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1507	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1508	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1509	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1510	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1511	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); /* no mask; flat index into the 2048 entry array. */
1512	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
1513	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1514	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1515	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1516	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1517	PX86PDPAE pPDDst;
1518	X86PDEPAE PdeDst;
1519	PX86PDPT pPdptDst;
1520
1521	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1522	AssertRCReturn(rc, rc);
1523	Assert(pPDDst && pPdptDst);
1524	PdeDst = pPDDst->a[iPDDst];
1525	# endif
1526	Assert(PdeDst.n.u1Present);
1527	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1528
1529	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1530	/* Fetch the pgm pool shadow descriptor. */
1531	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1532	Assert(pShwPde);
1533	# endif
1534
1535	/*
1536	* Check that the page is present and that the shadow PDE isn't out of sync.
1537	*/
1538	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1539	const bool fBigPage = PdeSrc.b.u1Size;
1540	# else
1541	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1542	# endif
1543	RTGCPHYS GCPhys;
1544	if (!fBigPage)
1545	{
1546	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1547	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1548	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1549	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1550	# endif
1551	}
1552	else
1553	{
1554	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1555	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1556	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1557	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1558	# endif
1559	}
1560	if ( pShwPage->GCPhys == GCPhys
1561	&& PdeSrc.n.u1Present
1562	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1563	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1564	# if PGM_WITH_NX(PGM_GST_TYPE)
1565	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1566	# endif
1567	)
1568	{
1569	/*
1570	* Check that the PDE is marked accessed already.
1571	* Since we set the accessed bit before getting here on a #PF, this
1572	* check is only meant for dealing with non-#PF'ing paths.
1573	*/
1574	if (PdeSrc.n.u1Accessed)
1575	{
1576	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1577	if (!fBigPage)
1578	{
1579	/*
1580	* 4KB Page - Map the guest page table.
1581	*/
1582	PGSTPT pPTSrc;
1583	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1584	if (VBOX_SUCCESS(rc))
1585	{
1586	# ifdef PGM_SYNC_N_PAGES
1587	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1588	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1589	{
1590	/*
1591	* This code path is currently only taken when the caller is PGMTrap0eHandler
1592	* for non-present pages!
1593	*
1594	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1595	* deal with locality.
1596	*/
1597	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1598	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1599	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1600	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1601	# else
1602	const unsigned offPTSrc = 0;
1603	# endif
1604	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1605	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1606	iPTDst = 0;
1607	else
1608	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1609	for (; iPTDst < iPTDstEnd; iPTDst++)
1610	{
1611	if (!pPTDst->a[iPTDst].n.u1Present)
1612	{
1613	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1614	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1615	NOREF(GCPtrCurPage);
1616	#ifndef IN_RING0
1617	/*
1618	* Assuming kernel code will be marked as supervisor - and not as user level
1619	* and executed using a conforming code selector - And marked as readonly.
1620	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1621	*/
1622	PPGMPAGE pPage;
1623	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1624	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1625	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1626	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1627	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1628	)
1629	#endif /* else: CSAM not active */
1630	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1631	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1632	GCPtrCurPage, PteSrc.n.u1Present,
1633	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1634	PteSrc.n.u1User & PdeSrc.n.u1User,
1635	(uint64_t)PteSrc.u,
1636	(uint64_t)pPTDst->a[iPTDst].u,
1637	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1638	}
1639	}
1640	}
1641	else
1642	# endif /* PGM_SYNC_N_PAGES */
1643	{
1644	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1645	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1646	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1647	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1648	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1649	GCPtrPage, PteSrc.n.u1Present,
1650	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1651	PteSrc.n.u1User & PdeSrc.n.u1User,
1652	(uint64_t)PteSrc.u,
1653	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1654	}
1655	}
1656	else /* MMIO or invalid page: emulated in #PF handler. */
1657	{
1658	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1659	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1660	}
1661	}
1662	else
1663	{
1664	/*
1665	* 4/2MB page - lazy syncing shadow 4K pages.
1666	* (There are many causes of getting here, it's no longer only CSAM.)
1667	*/
1668	/* Calculate the GC physical address of this 4KB shadow page. */
1669	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1670	/* Find ram range. */
1671	PPGMPAGE pPage;
1672	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1673	if (VBOX_SUCCESS(rc))
1674	{
1675	/*
1676	* Make shadow PTE entry.
1677	*/
1678	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1679	SHWPTE PteDst;
1680	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1681	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1682	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1683	{
1684	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1685	PteDst.n.u1Write = 0;
1686	else
1687	PteDst.u = 0;
1688	}
1689	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1690	# ifdef PGMPOOL_WITH_USER_TRACKING
1691	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1692	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1693	# endif
1694	pPTDst->a[iPTDst] = PteDst;
1695
1696
1697	/*
1698	* If the page is not flagged as dirty and is writable, then make it read-only
1699	* at PD level, so we can set the dirty bit when the page is modified.
1700	*
1701	* ASSUMES that page access handlers are implemented on page table entry level.
1702	* Thus we will first catch the dirty access and set PDE.D and restart. If
1703	* there is an access handler, we'll trap again and let it work on the problem.
1704	*/
1705	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1706	* As for invlpg, it simply frees the whole shadow PT.
1707	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1708	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1709	{
1710	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1711	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1712	PdeDst.n.u1Write = 0;
1713	}
1714	else
1715	{
1716	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1717	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1718	}
1719	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1720	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1721	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1722	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1723	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1724	pPDDst->a[iPDDst] = PdeDst;
1725	# endif
1726	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1727	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1728	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1729	}
1730	else
1731	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1732	}
1733	return VINF_SUCCESS;
1734	}
1735	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1736	}
1737	else
1738	{
1739	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1740	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1741	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1742	}
1743
1744	/*
1745	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1746	* Yea, I'm lazy.
1747	*/
1748	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1749	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1750	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1751	# else
1752	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1753	# endif
1754
1755	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1756	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1757	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1758	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1759	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1760	pPDDst->a[iPDDst].u = 0;
1761	# endif
1762	PGM_INVL_GUEST_TLBS();
1763	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1764
1765	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1766	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1767
1768	# ifdef PGM_SYNC_N_PAGES
1769	/*
1770	* Get the shadow PDE, find the shadow page table in the pool.
1771	*/
1772	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1773	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1774	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1775	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1776	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
1777	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1778	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1779	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1780	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1781	PX86PDPAE pPDDst;
1782	X86PDEPAE PdeDst;
1783	PX86PDPT pPdptDst;
1784
1785	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1786	AssertRCReturn(rc, rc);
1787	Assert(pPDDst && pPdptDst);
1788	PdeDst = pPDDst->a[iPDDst];
1789	# endif
1790	Assert(PdeDst.n.u1Present);
1791	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1792	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1793
1794	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1795	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1796	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1797	# else
1798	const unsigned offPTSrc = 0;
1799	# endif
1800
1801	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1802	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1803	{
1804	/*
1805	* This code path is currently only taken when the caller is PGMTrap0eHandler
1806	* for non-present pages!
1807	*
1808	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1809	* deal with locality.
1810	*/
1811	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1812	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1813	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1814	iPTDst = 0;
1815	else
1816	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1817	for (; iPTDst < iPTDstEnd; iPTDst++)
1818	{
1819	if (!pPTDst->a[iPTDst].n.u1Present)
1820	{
1821	GSTPTE PteSrc;
1822
1823	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1824
1825	/* Fake the page table entry */
1826	PteSrc.u = GCPtrCurPage;
1827	PteSrc.n.u1Present = 1;
1828	PteSrc.n.u1Dirty = 1;
1829	PteSrc.n.u1Accessed = 1;
1830	PteSrc.n.u1Write = 1;
1831	PteSrc.n.u1User = 1;
1832
1833	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1834
1835	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1836	GCPtrCurPage, PteSrc.n.u1Present,
1837	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1838	PteSrc.n.u1User & PdeSrc.n.u1User,
1839	(uint64_t)PteSrc.u,
1840	(uint64_t)pPTDst->a[iPTDst].u,
1841	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1842	}
1843	else
1844	Log4(("%VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1845	}
1846	}
1847	else
1848	# endif /* PGM_SYNC_N_PAGES */
1849	{
1850	GSTPTE PteSrc;
1851	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1852	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1853
1854	/* Fake the page table entry */
1855	PteSrc.u = GCPtrCurPage;
1856	PteSrc.n.u1Present = 1;
1857	PteSrc.n.u1Dirty = 1;
1858	PteSrc.n.u1Accessed = 1;
1859	PteSrc.n.u1Write = 1;
1860	PteSrc.n.u1User = 1;
1861	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1862
1863	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1864	GCPtrPage, PteSrc.n.u1Present,
1865	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1866	PteSrc.n.u1User & PdeSrc.n.u1User,
1867	(uint64_t)PteSrc.u,
1868	(uint64_t)pPTDst->a[iPTDst].u,
1869	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1870	}
1871	return VINF_SUCCESS;
1872
1873	#else
1874	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1875	return VERR_INTERNAL_ERROR;
1876	#endif
1877	}
1878
1879
1880
1881	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1882
1883	/**
1884	* Investigate page fault and handle write protection page faults caused by
1885	* dirty bit tracking.
1886	*
1887	* @returns VBox status code.
1888	* @param pVM VM handle.
1889	* @param uErr Page fault error code.
1890	* @param pPdeDst Shadow page directory entry.
1891	* @param pPdeSrc Guest page directory entry.
1892	* @param GCPtrPage Guest context page address.
1893	*/
1894	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1895	{
1896	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1897	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1898	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1899	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1900	bool fBigPagesSupported = true;
1901	# else
1902	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1903	# endif
1904	# if PGM_WITH_NX(PGM_GST_TYPE)
1905	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1906	# endif
1907	unsigned uPageFaultLevel;
1908	int rc;
1909
1910	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1911	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1912
1913	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1914	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1915
1916	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1917	PX86PML4E pPml4eSrc;
1918	PX86PDPE pPdpeSrc;
1919
1920	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
1921	Assert(pPml4eSrc);
1922
1923	/*
1924	* Real page fault? (PML4E level)
1925	*/
1926	if ( (uErr & X86_TRAP_PF_RSVD)
1927	\|\| !pPml4eSrc->n.u1Present
1928	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
1929	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1930	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
1931	)
1932	{
1933	uPageFaultLevel = 0;
1934	goto UpperLevelPageFault;
1935	}
1936	Assert(pPdpeSrc);
1937
1938	# else /* PAE */
1939	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1940	# endif
1941
1942	/*
1943	* Real page fault? (PDPE level)
1944	*/
1945	if ( (uErr & X86_TRAP_PF_RSVD)
1946	\|\| !pPdpeSrc->n.u1Present
1947	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1948	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
1949	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
1950	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
1951	# endif
1952	)
1953	{
1954	uPageFaultLevel = 1;
1955	goto UpperLevelPageFault;
1956	}
1957	# endif
1958
1959	/*
1960	* Real page fault? (PDE level)
1961	*/
1962	if ( (uErr & X86_TRAP_PF_RSVD)
1963	\|\| !pPdeSrc->n.u1Present
1964	# if PGM_WITH_NX(PGM_GST_TYPE)
1965	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1966	# endif
1967	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1968	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1969	{
1970	uPageFaultLevel = 2;
1971	goto UpperLevelPageFault;
1972	}
1973
1974	/*
1975	* First check the easy case where the page directory has been marked read-only to track
1976	* the dirty bit of an emulated BIG page
1977	*/
1978	if (pPdeSrc->b.u1Size && fBigPagesSupported)
1979	{
1980	/* Mark guest page directory as accessed */
1981	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1982	pPml4eSrc->n.u1Accessed = 1;
1983	pPdpeSrc->lm.u1Accessed = 1;
1984	# endif
1985	pPdeSrc->b.u1Accessed = 1;
1986
1987	/*
1988	* Only write protection page faults are relevant here.
1989	*/
1990	if (fWriteFault)
1991	{
1992	/* Mark guest page directory as dirty (BIG page only). */
1993	pPdeSrc->b.u1Dirty = 1;
1994
1995	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1996	{
1997	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1998
1999	Assert(pPdeSrc->b.u1Write);
2000
2001	pPdeDst->n.u1Write = 1;
2002	pPdeDst->n.u1Accessed = 1;
2003	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2004	PGM_INVL_BIG_PG(GCPtrPage);
2005	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2006	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2007	}
2008	}
2009	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2010	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2011	}
2012	/* else: 4KB page table */
2013
2014	/*
2015	* Map the guest page table.
2016	*/
2017	PGSTPT pPTSrc;
2018	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2019	if (VBOX_SUCCESS(rc))
2020	{
2021	/*
2022	* Real page fault?
2023	*/
2024	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2025	const GSTPTE PteSrc = *pPteSrc;
2026	if ( !PteSrc.n.u1Present
2027	# if PGM_WITH_NX(PGM_GST_TYPE)
2028	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2029	# endif
2030	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2031	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2032	)
2033	{
2034	# ifdef IN_GC
2035	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2036	# endif
2037	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2038	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2039
2040	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2041	* See the 2nd case above as well.
2042	*/
2043	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2044	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2045
2046	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2047	return VINF_EM_RAW_GUEST_TRAP;
2048	}
2049	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2050
2051	/*
2052	* Set the accessed bits in the page directory and the page table.
2053	*/
2054	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2055	pPml4eSrc->n.u1Accessed = 1;
2056	pPdpeSrc->lm.u1Accessed = 1;
2057	# endif
2058	pPdeSrc->n.u1Accessed = 1;
2059	pPteSrc->n.u1Accessed = 1;
2060
2061	/*
2062	* Only write protection page faults are relevant here.
2063	*/
2064	if (fWriteFault)
2065	{
2066	/* Write access, so mark guest entry as dirty. */
2067	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
2068	if (!pPteSrc->n.u1Dirty)
2069	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
2070	else
2071	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
2072	# endif
2073
2074	pPteSrc->n.u1Dirty = 1;
2075
2076	if (pPdeDst->n.u1Present)
2077	{
2078	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2079	* Our individual shadow handlers will provide more information and force a fatal exit.
2080	*/
2081	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2082	{
2083	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2084	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2085	return VINF_SUCCESS;
2086	}
2087
2088	/*
2089	* Map shadow page table.
2090	*/
2091	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2092	if (pShwPage)
2093	{
2094	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2095	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2096	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2097	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2098	{
2099	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2100	# ifdef VBOX_STRICT
2101	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2102	if (pPage)
2103	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2104	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2105	# endif
2106	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
2107
2108	Assert(pPteSrc->n.u1Write);
2109
2110	pPteDst->n.u1Write = 1;
2111	pPteDst->n.u1Dirty = 1;
2112	pPteDst->n.u1Accessed = 1;
2113	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2114	PGM_INVL_PG(GCPtrPage);
2115
2116	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2117	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2118	}
2119	}
2120	else
2121	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2122	}
2123	}
2124	/** @todo Optimize accessed bit emulation? */
2125	# ifdef VBOX_STRICT
2126	/*
2127	* Sanity check.
2128	*/
2129	else if ( !pPteSrc->n.u1Dirty
2130	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2131	&& pPdeDst->n.u1Present)
2132	{
2133	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2134	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2135	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2136	if ( pPteDst->n.u1Present
2137	&& pPteDst->n.u1Write)
2138	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2139	}
2140	# endif /* VBOX_STRICT */
2141	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2142	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2143	}
2144	AssertRC(rc);
2145	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2146	return rc;
2147
2148
2149	UpperLevelPageFault:
2150	/* Pagefault detected while checking the PML4E, PDPE or PDE.
2151	* Single exit handler to get rid of duplicate code paths.
2152	*/
2153	# ifdef IN_GC
2154	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2155	# endif
2156	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
2157	LogFlow(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2158
2159	if (
2160	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2161	pPml4eSrc->n.u1Present &&
2162	# endif
2163	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2164	pPdpeSrc->n.u1Present &&
2165	# endif
2166	pPdeSrc->n.u1Present)
2167	{
2168	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2169	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2170	{
2171	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2172	}
2173	else
2174	{
2175	/*
2176	* Map the guest page table.
2177	*/
2178	PGSTPT pPTSrc;
2179	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2180	if (VBOX_SUCCESS(rc))
2181	{
2182	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2183	const GSTPTE PteSrc = *pPteSrc;
2184	if (pPteSrc->n.u1Present)
2185	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2186	}
2187	AssertRC(rc);
2188	}
2189	}
2190	return VINF_EM_RAW_GUEST_TRAP;
2191	}
2192
2193	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2194
2195
2196	/**
2197	* Sync a shadow page table.
2198	*
2199	* The shadow page table is not present. This includes the case where
2200	* there is a conflict with a mapping.
2201	*
2202	* @returns VBox status code.
2203	* @param pVM VM handle.
2204	* @param iPD Page directory index.
2205	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2206	* Assume this is a temporary mapping.
2207	* @param GCPtrPage GC Pointer of the page that caused the fault
2208	*/
2209	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2210	{
2211	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2212	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
2213	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2214
2215	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2216	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2217	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2218	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2219
2220	int rc = VINF_SUCCESS;
2221
2222	/*
2223	* Validate input a little bit.
2224	*/
2225	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2226	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2227	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2228	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2229	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2230	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2231	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT);
2232	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
2233	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2234	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2235	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2236	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2237	PX86PDPAE pPDDst;
2238	PX86PDPT pPdptDst;
2239	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2240	if (rc != VINF_SUCCESS)
2241	{
2242	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2243	return rc;
2244	}
2245	Assert(pPDDst);
2246	# endif
2247
2248	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2249	SHWPDE PdeDst = *pPdeDst;
2250
2251	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2252	/* Fetch the pgm pool shadow descriptor. */
2253	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2254	Assert(pShwPde);
2255	# endif
2256
2257	# ifndef PGM_WITHOUT_MAPPINGS
2258	/*
2259	* Check for conflicts.
2260	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2261	* HC: Simply resolve the conflict.
2262	*/
2263	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2264	{
2265	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2266	# ifndef IN_RING3
2267	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2268	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2269	return VERR_ADDRESS_CONFLICT;
2270	# else
2271	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2272	Assert(pMapping);
2273	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2274	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2275	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2276	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2277	# else
2278	AssertFailed(); /* can't happen for amd64 */
2279	# endif
2280	if (VBOX_FAILURE(rc))
2281	{
2282	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2283	return rc;
2284	}
2285	PdeDst = *pPdeDst;
2286	# endif
2287	}
2288	# else /* PGM_WITHOUT_MAPPINGS */
2289	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2290	# endif /* PGM_WITHOUT_MAPPINGS */
2291	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2292
2293	/*
2294	* Sync page directory entry.
2295	*/
2296	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2297	if (PdeSrc.n.u1Present)
2298	{
2299	/*
2300	* Allocate & map the page table.
2301	*/
2302	PSHWPT pPTDst;
2303	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2304	const bool fPageTable = !PdeSrc.b.u1Size;
2305	# else
2306	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2307	# endif
2308	PPGMPOOLPAGE pShwPage;
2309	RTGCPHYS GCPhys;
2310	if (fPageTable)
2311	{
2312	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2313	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2314	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2315	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2316	# endif
2317	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2318	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2319	# else
2320	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2321	# endif
2322	}
2323	else
2324	{
2325	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2326	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2327	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2328	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2329	# endif
2330	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2331	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2332	# else
2333	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2334	# endif
2335	}
2336	if (rc == VINF_SUCCESS)
2337	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2338	else if (rc == VINF_PGM_CACHED_PAGE)
2339	{
2340	/*
2341	* The PT was cached, just hook it up.
2342	*/
2343	if (fPageTable)
2344	PdeDst.u = pShwPage->Core.Key
2345	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2346	else
2347	{
2348	PdeDst.u = pShwPage->Core.Key
2349	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2350	/* (see explanation and assumptions further down.) */
2351	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2352	{
2353	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2354	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2355	PdeDst.b.u1Write = 0;
2356	}
2357	}
2358	*pPdeDst = PdeDst;
2359	return VINF_SUCCESS;
2360	}
2361	else if (rc == VERR_PGM_POOL_FLUSHED)
2362	return VINF_PGM_SYNC_CR3;
2363	else
2364	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2365	PdeDst.u &= X86_PDE_AVL_MASK;
2366	PdeDst.u \|= pShwPage->Core.Key;
2367
2368	/*
2369	* Page directory has been accessed (this is a fault situation, remember).
2370	*/
2371	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2372	if (fPageTable)
2373	{
2374	/*
2375	* Page table - 4KB.
2376	*
2377	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2378	*/
2379	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2380	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2381	PGSTPT pPTSrc;
2382	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2383	if (VBOX_SUCCESS(rc))
2384	{
2385	/*
2386	* Start by syncing the page directory entry so CSAM's TLB trick works.
2387	*/
2388	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2389	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2390	*pPdeDst = PdeDst;
2391
2392	/*
2393	* Directory/page user or supervisor privilege: (same goes for read/write)
2394	*
2395	* Directory Page Combined
2396	* U/S U/S U/S
2397	* 0 0 0
2398	* 0 1 0
2399	* 1 0 0
2400	* 1 1 1
2401	*
2402	* Simple AND operation. Table listed for completeness.
2403	*
2404	*/
2405	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2406	# ifdef PGM_SYNC_N_PAGES
2407	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2408	unsigned iPTDst = iPTBase;
2409	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2410	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2411	iPTDst = 0;
2412	else
2413	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2414	# else /* !PGM_SYNC_N_PAGES */
2415	unsigned iPTDst = 0;
2416	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2417	# endif /* !PGM_SYNC_N_PAGES */
2418	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2419	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2420	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2421	# else
2422	const unsigned offPTSrc = 0;
2423	# endif
2424	for (; iPTDst < iPTDstEnd; iPTDst++)
2425	{
2426	const unsigned iPTSrc = iPTDst + offPTSrc;
2427	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2428
2429	if (PteSrc.n.u1Present) /* we've already cleared it above */
2430	{
2431	# ifndef IN_RING0
2432	/*
2433	* Assuming kernel code will be marked as supervisor - and not as user level
2434	* and executed using a conforming code selector - And marked as readonly.
2435	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2436	*/
2437	PPGMPAGE pPage;
2438	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2439	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2440	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2441	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2442	)
2443	# endif
2444	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2445	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2446	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2447	PteSrc.n.u1Present,
2448	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2449	PteSrc.n.u1User & PdeSrc.n.u1User,
2450	(uint64_t)PteSrc.u,
2451	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2452	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2453	}
2454	} /* for PTEs */
2455	}
2456	}
2457	else
2458	{
2459	/*
2460	* Big page - 2/4MB.
2461	*
2462	* We'll walk the ram range list in parallel and optimize lookups.
2463	* We will only sync on shadow page table at a time.
2464	*/
2465	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2466
2467	/**
2468	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2469	*/
2470
2471	/*
2472	* Start by syncing the page directory entry.
2473	*/
2474	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2475	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2476
2477	/*
2478	* If the page is not flagged as dirty and is writable, then make it read-only
2479	* at PD level, so we can set the dirty bit when the page is modified.
2480	*
2481	* ASSUMES that page access handlers are implemented on page table entry level.
2482	* Thus we will first catch the dirty access and set PDE.D and restart. If
2483	* there is an access handler, we'll trap again and let it work on the problem.
2484	*/
2485	/** @todo move the above stuff to a section in the PGM documentation. */
2486	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2487	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2488	{
2489	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2490	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2491	PdeDst.b.u1Write = 0;
2492	}
2493	*pPdeDst = PdeDst;
2494
2495	/*
2496	* Fill the shadow page table.
2497	*/
2498	/* Get address and flags from the source PDE. */
2499	SHWPTE PteDstBase;
2500	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2501
2502	/* Loop thru the entries in the shadow PT. */
2503	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2504	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2505	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2506	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2507	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2508	unsigned iPTDst = 0;
2509	while (iPTDst < ELEMENTS(pPTDst->a))
2510	{
2511	/* Advance ram range list. */
2512	while (pRam && GCPhys > pRam->GCPhysLast)
2513	pRam = CTXALLSUFF(pRam->pNext);
2514	if (pRam && GCPhys >= pRam->GCPhys)
2515	{
2516	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2517	do
2518	{
2519	/* Make shadow PTE. */
2520	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2521	SHWPTE PteDst;
2522
2523	/* Make sure the RAM has already been allocated. */
2524	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2525	{
2526	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2527	{
2528	# ifdef IN_RING3
2529	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2530	# else
2531	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2532	# endif
2533	if (rc != VINF_SUCCESS)
2534	return rc;
2535	}
2536	}
2537
2538	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2539	{
2540	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2541	{
2542	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2543	PteDst.n.u1Write = 0;
2544	}
2545	else
2546	PteDst.u = 0;
2547	}
2548	# ifndef IN_RING0
2549	/*
2550	* Assuming kernel code will be marked as supervisor and not as user level and executed
2551	* using a conforming code selector. Don't check for readonly, as that implies the whole
2552	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2553	*/
2554	else if ( !PdeSrc.n.u1User
2555	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2556	PteDst.u = 0;
2557	# endif
2558	else
2559	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2560	# ifdef PGMPOOL_WITH_USER_TRACKING
2561	if (PteDst.n.u1Present)
2562	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2563	# endif
2564	/* commit it */
2565	pPTDst->a[iPTDst] = PteDst;
2566	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2567	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2568	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2569
2570	/* advance */
2571	GCPhys += PAGE_SIZE;
2572	iHCPage++;
2573	iPTDst++;
2574	} while ( iPTDst < ELEMENTS(pPTDst->a)
2575	&& GCPhys <= pRam->GCPhysLast);
2576	}
2577	else if (pRam)
2578	{
2579	Log(("Invalid pages at %VGp\n", GCPhys));
2580	do
2581	{
2582	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2583	GCPhys += PAGE_SIZE;
2584	iPTDst++;
2585	} while ( iPTDst < ELEMENTS(pPTDst->a)
2586	&& GCPhys < pRam->GCPhys);
2587	}
2588	else
2589	{
2590	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2591	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2592	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2593	}
2594	} /* while more PTEs */
2595	} /* 4KB / 4MB */
2596	}
2597	else
2598	AssertRelease(!PdeDst.n.u1Present);
2599
2600	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2601	# ifdef IN_GC
2602	if (VBOX_FAILURE(rc))
2603	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2604	# endif
2605	return rc;
2606
2607	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2608	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2609
2610	int rc = VINF_SUCCESS;
2611
2612	/*
2613	* Validate input a little bit.
2614	*/
2615	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2616	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2617	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2618	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2619	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2620	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2621	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2622	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2623	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2624	PX86PDPAE pPDDst;
2625	PX86PDPT pPdptDst;
2626	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2627	if (rc != VINF_SUCCESS)
2628	{
2629	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2630	return rc;
2631	}
2632	Assert(pPDDst);
2633
2634	/* Fetch the pgm pool shadow descriptor. */
2635	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2636	Assert(pShwPde);
2637	# endif
2638	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2639	SHWPDE PdeDst = *pPdeDst;
2640
2641	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2642	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2643
2644	GSTPDE PdeSrc;
2645	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2646	PdeSrc.n.u1Present = 1;
2647	PdeSrc.n.u1Write = 1;
2648	PdeSrc.n.u1Accessed = 1;
2649	PdeSrc.n.u1User = 1;
2650
2651	/*
2652	* Allocate & map the page table.
2653	*/
2654	PSHWPT pPTDst;
2655	PPGMPOOLPAGE pShwPage;
2656	RTGCPHYS GCPhys;
2657
2658	/* Virtual address = physical address */
2659	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2660	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2661	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2662	# else
2663	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2664	# endif
2665
2666	if ( rc == VINF_SUCCESS
2667	\|\| rc == VINF_PGM_CACHED_PAGE)
2668	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2669	else
2670	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2671
2672	PdeDst.u &= X86_PDE_AVL_MASK;
2673	PdeDst.u \|= pShwPage->Core.Key;
2674	PdeDst.n.u1Present = 1;
2675	PdeDst.n.u1Write = 1;
2676	PdeDst.n.u1User = 1;
2677	*pPdeDst = PdeDst;
2678
2679	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2680	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2681	return rc;
2682
2683	#else
2684	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2685	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2686	return VERR_INTERNAL_ERROR;
2687	#endif
2688	}
2689
2690
2691
2692	/**
2693	* Prefetch a page/set of pages.
2694	*
2695	* Typically used to sync commonly used pages before entering raw mode
2696	* after a CR3 reload.
2697	*
2698	* @returns VBox status code.
2699	* @param pVM VM handle.
2700	* @param GCPtrPage Page to invalidate.
2701	*/
2702	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2703	{
2704	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2705	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2706	/*
2707	* Check that all Guest levels thru the PDE are present, getting the
2708	* PD and PDE in the processes.
2709	*/
2710	int rc = VINF_SUCCESS;
2711	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2712	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2713	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2714	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2715	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2716	unsigned iPDSrc;
2717	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2718	if (!pPDSrc)
2719	return VINF_SUCCESS; /* not present */
2720	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2721	unsigned iPDSrc;
2722	PX86PML4E pPml4eSrc;
2723	X86PDPE PdpeSrc;
2724	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2725	if (!pPDSrc)
2726	return VINF_SUCCESS; /* not present */
2727	# endif
2728	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2729	# else
2730	PGSTPD pPDSrc = NULL;
2731	const unsigned iPDSrc = 0;
2732	GSTPDE PdeSrc;
2733
2734	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2735	PdeSrc.n.u1Present = 1;
2736	PdeSrc.n.u1Write = 1;
2737	PdeSrc.n.u1Accessed = 1;
2738	PdeSrc.n.u1User = 1;
2739	# endif
2740
2741	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2742	{
2743	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2744	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2745	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2746	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2747	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2748	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2749	PX86PDPAE pPDDst;
2750	X86PDEPAE PdeDst;
2751
2752	# if PGM_GST_TYPE == PGM_TYPE_PROT
2753	/* AMD-V nested paging */
2754	X86PML4E Pml4eSrc;
2755	X86PDPE PdpeSrc;
2756	PX86PML4E pPml4eSrc = &Pml4eSrc;
2757
2758	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2759	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2760	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2761	# endif
2762
2763	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2764	if (rc != VINF_SUCCESS)
2765	{
2766	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2767	return rc;
2768	}
2769	Assert(pPDDst);
2770	PdeDst = pPDDst->a[iPDDst];
2771	# endif
2772	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2773	{
2774	if (!PdeDst.n.u1Present)
2775	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2776	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2777	else
2778	{
2779	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2780	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2781	* makes no sense to prefetch more than one page.
2782	*/
2783	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2784	if (VBOX_SUCCESS(rc))
2785	rc = VINF_SUCCESS;
2786	}
2787	}
2788	}
2789	return rc;
2790	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED
2791	return VINF_SUCCESS; /* ignore */
2792	#endif
2793	}
2794
2795
2796
2797
2798	/**
2799	* Syncs a page during a PGMVerifyAccess() call.
2800	*
2801	* @returns VBox status code (informational included).
2802	* @param GCPtrPage The address of the page to sync.
2803	* @param fPage The effective guest page flags.
2804	* @param uErr The trap error code.
2805	*/
2806	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2807	{
2808	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2809
2810	Assert(!HWACCMIsNestedPagingActive(pVM));
2811	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2812	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2813
2814	# ifndef IN_RING0
2815	if (!(fPage & X86_PTE_US))
2816	{
2817	/*
2818	* Mark this page as safe.
2819	*/
2820	/** @todo not correct for pages that contain both code and data!! */
2821	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2822	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2823	}
2824	# endif
2825	/*
2826	* Get guest PD and index.
2827	*/
2828
2829	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2830	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2831	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2832	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2833	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2834	unsigned iPDSrc;
2835	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2836
2837	if (pPDSrc)
2838	{
2839	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2840	return VINF_EM_RAW_GUEST_TRAP;
2841	}
2842	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2843	unsigned iPDSrc;
2844	PX86PML4E pPml4eSrc;
2845	X86PDPE PdpeSrc;
2846	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2847	if (!pPDSrc)
2848	{
2849	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2850	return VINF_EM_RAW_GUEST_TRAP;
2851	}
2852	# endif
2853	# else
2854	PGSTPD pPDSrc = NULL;
2855	const unsigned iPDSrc = 0;
2856	# endif
2857	int rc = VINF_SUCCESS;
2858
2859	/*
2860	* First check if the shadow pd is present.
2861	*/
2862	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2863	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2864	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2865	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2866	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2867	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2868	PX86PDPAE pPDDst;
2869	PX86PDEPAE pPdeDst;
2870
2871	# if PGM_GST_TYPE == PGM_TYPE_PROT
2872	/* AMD-V nested paging */
2873	X86PML4E Pml4eSrc;
2874	X86PDPE PdpeSrc;
2875	PX86PML4E pPml4eSrc = &Pml4eSrc;
2876
2877	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2878	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2879	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2880	# endif
2881
2882	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2883	if (rc != VINF_SUCCESS)
2884	{
2885	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
2886	return rc;
2887	}
2888	Assert(pPDDst);
2889	pPdeDst = &pPDDst->a[iPDDst];
2890	# endif
2891	if (!pPdeDst->n.u1Present)
2892	{
2893	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2894	AssertRC(rc);
2895	if (rc != VINF_SUCCESS)
2896	return rc;
2897	}
2898
2899	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2900	/* Check for dirty bit fault */
2901	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2902	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2903	Log(("PGMVerifyAccess: success (dirty)\n"));
2904	else
2905	{
2906	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2907	#else
2908	{
2909	GSTPDE PdeSrc;
2910	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2911	PdeSrc.n.u1Present = 1;
2912	PdeSrc.n.u1Write = 1;
2913	PdeSrc.n.u1Accessed = 1;
2914	PdeSrc.n.u1User = 1;
2915
2916	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2917	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2918	if (uErr & X86_TRAP_PF_US)
2919	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2920	else /* supervisor */
2921	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2922
2923	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2924	if (VBOX_SUCCESS(rc))
2925	{
2926	/* Page was successfully synced */
2927	Log2(("PGMVerifyAccess: success (sync)\n"));
2928	rc = VINF_SUCCESS;
2929	}
2930	else
2931	{
2932	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2933	return VINF_EM_RAW_GUEST_TRAP;
2934	}
2935	}
2936	return rc;
2937
2938	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2939
2940	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2941	return VERR_INTERNAL_ERROR;
2942	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2943	}
2944
2945
2946	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2947	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
2948	/**
2949	* Figures out which kind of shadow page this guest PDE warrants.
2950	*
2951	* @returns Shadow page kind.
2952	* @param pPdeSrc The guest PDE in question.
2953	* @param cr4 The current guest cr4 value.
2954	*/
2955	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2956	{
2957	# if PMG_GST_TYPE == PGM_TYPE_AMD64
2958	if (!pPdeSrc->n.u1Size)
2959	# else
2960	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2961	# endif
2962	return BTH_PGMPOOLKIND_PT_FOR_PT;
2963	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2964	//{
2965	// case 0:
2966	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2967	// case X86_PDE4M_RW:
2968	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2969	// case X86_PDE4M_US:
2970	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2971	// case X86_PDE4M_RW \| X86_PDE4M_US:
2972	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2973	# if 0
2974	// case X86_PDE4M_PAE_NX:
2975	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2976	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2977	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2978	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2979	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2980	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2981	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2982	# endif
2983	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2984	//}
2985	}
2986	# endif
2987	#endif
2988
2989	#undef MY_STAM_COUNTER_INC
2990	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2991
2992
2993	/**
2994	* Syncs the paging hierarchy starting at CR3.
2995	*
2996	* @returns VBox status code, no specials.
2997	* @param pVM The virtual machine.
2998	* @param cr0 Guest context CR0 register
2999	* @param cr3 Guest context CR3 register
3000	* @param cr4 Guest context CR4 register
3001	* @param fGlobal Including global page directories or not
3002	*/
3003	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3004	{
3005	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
3006	/** @todo check if this is really necessary */
3007	HWACCMFlushTLB(pVM);
3008	return VINF_SUCCESS;
3009
3010	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
3011	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3012	fGlobal = true; /* Change this CR3 reload to be a global one. */
3013
3014	/*
3015	* Update page access handlers.
3016	* The virtual are always flushed, while the physical are only on demand.
3017	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3018	* have to look into that later because it will have a bad influence on the performance.
3019	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3020	* bird: Yes, but that won't work for aliases.
3021	*/
3022	/** @todo this MUST go away. See #1557. */
3023	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
3024	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3025	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
3026
3027	# ifdef PGMPOOL_WITH_MONITORING
3028	/*
3029	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
3030	* Occationally we will have to clear all the shadow page tables because we wanted
3031	* to monitor a page which was mapped by too many shadowed page tables. This operation
3032	* sometimes refered to as a 'lightweight flush'.
3033	*/
3034	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
3035	pgmPoolMonitorModifiedClearAll(pVM);
3036	else
3037	{
3038	# ifdef IN_RING3
3039	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
3040	pgmPoolClearAll(pVM);
3041	# else
3042	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
3043	return VINF_PGM_SYNC_CR3;
3044	# endif
3045	}
3046	# endif
3047
3048	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3049	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
3050
3051	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3052	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3053	bool fBigPagesSupported = true;
3054	# else
3055	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3056	# endif
3057
3058	/*
3059	* Get page directory addresses.
3060	*/
3061	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3062	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3063	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3064	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3065	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3066	# endif
3067	# endif
3068
3069	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3070	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
3071	Assert(pPDSrc);
3072	# ifndef IN_GC
3073	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3074	# endif
3075	# endif
3076
3077	/*
3078	* Iterate the page directory.
3079	*/
3080	PPGMMAPPING pMapping;
3081	unsigned iPdNoMapping;
3082	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3083	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
3084
3085	/* Only check mappings if they are supposed to be put into the shadow page table. */
3086	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3087	{
3088	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3089	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3090	}
3091	else
3092	{
3093	pMapping = 0;
3094	iPdNoMapping = ~0U;
3095	}
3096	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3097	for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3098	{
3099	PPGMPOOLPAGE pShwPdpt = NULL;
3100	PX86PML4E pPml4eSrc, pPml4eDst;
3101	RTGCPHYS GCPhysPdptSrc;
3102
3103	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3104	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3105
3106	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3107	if (!pPml4eDst->n.u1Present)
3108	continue;
3109	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3110
3111	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3112
3113	/* Anything significant changed? */
3114	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3115	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3116	{
3117	/* Free it. */
3118	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3119	(uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3120	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
3121	pPml4eDst->u = 0;
3122	continue;
3123	}
3124	/* Force an attribute sync. */
3125	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3126	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3127	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3128
3129	# else
3130	{
3131	# endif
3132	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3133	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3134	{
3135	unsigned iPDSrc;
3136	# if PGM_GST_TYPE == PGM_TYPE_PAE
3137	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3138	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3139	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
3140	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3141	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3142
3143	if (pPDSrc == NULL)
3144	{
3145	/* PDPE not present */
3146	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
3147	{
3148	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3149	/* for each page directory entry */
3150	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
3151	{
3152	if ( pPDEDst[iPD].n.u1Present
3153	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3154	{
3155	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3156	pPDEDst[iPD].u = 0;
3157	}
3158	}
3159	}
3160	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3161	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
3162	continue;
3163	}
3164	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3165	PPGMPOOLPAGE pShwPde = NULL;
3166	RTGCPHYS GCPhysPdeSrc;
3167	PX86PDPE pPdpeDst;
3168	PX86PML4E pPml4eSrc;
3169	X86PDPE PdpeSrc;
3170	PX86PDPT pPdptDst;
3171	PX86PDPAE pPDDst;
3172	PX86PDEPAE pPDEDst;
3173	RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3174	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3175
3176	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3177	if (rc != VINF_SUCCESS)
3178	{
3179	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3180	break; /* next PML4E */
3181
3182	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3183	continue; /* next PDPTE */
3184	}
3185	Assert(pPDDst);
3186	pPDEDst = &pPDDst->a[0];
3187	Assert(iPDSrc == 0);
3188
3189	pPdpeDst = &pPdptDst->a[iPdpte];
3190
3191	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3192	if (!pPdpeDst->n.u1Present)
3193	continue; /* next PDPTE */
3194
3195	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3196	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3197
3198	/* Anything significant changed? */
3199	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3200	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3201	{
3202	/* Free it. */
3203	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3204	((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3205
3206	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3207	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3208	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3209	pPdpeDst->u = 0;
3210	continue; /* next guest PDPTE */
3211	}
3212	/* Force an attribute sync. */
3213	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3214	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3215	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3216	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3217
3218	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3219	{
3220	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3221	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
3222	{
3223	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3224	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3225	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3226	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3227	# endif
3228	register GSTPDE PdeSrc = pPDSrc->a[iPD];
3229	if ( PdeSrc.n.u1Present
3230	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3231	{
3232	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3233	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3234	&& !defined(PGM_WITHOUT_MAPPINGS)
3235
3236	/*
3237	* Check for conflicts with GC mappings.
3238	*/
3239	# if PGM_GST_TYPE == PGM_TYPE_PAE
3240	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3241	# else
3242	if (iPD == iPdNoMapping)
3243	# endif
3244	{
3245	if (pVM->pgm.s.fMappingsFixed)
3246	{
3247	/* It's fixed, just skip the mapping. */
3248	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3249	iPD += cPTs - 1;
3250	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3251	pMapping = pMapping->CTXALLSUFF(pNext);
3252	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3253	continue;
3254	}
3255	# ifdef IN_RING3
3256	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3257	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3258	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3259	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3260	# endif
3261	if (VBOX_FAILURE(rc))
3262	return rc;
3263
3264	/*
3265	* Update iPdNoMapping and pMapping.
3266	*/
3267	pMapping = pVM->pgm.s.pMappingsR3;
3268	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3269	pMapping = pMapping->pNextR3;
3270	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3271	# else
3272	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3273	return VINF_PGM_SYNC_CR3;
3274	# endif
3275	}
3276	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3277	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3278	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3279	/*
3280	* Sync page directory entry.
3281	*
3282	* The current approach is to allocated the page table but to set
3283	* the entry to not-present and postpone the page table synching till
3284	* it's actually used.
3285	*/
3286	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3287	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3288	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3289	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3290	# else
3291	const unsigned iPdShw = iPD; NOREF(iPdShw);
3292	# endif
3293	{
3294	SHWPDE PdeDst = *pPDEDst;
3295	if (PdeDst.n.u1Present)
3296	{
3297	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3298	RTGCPHYS GCPhys;
3299	if ( !PdeSrc.b.u1Size
3300	\|\| !fBigPagesSupported)
3301	{
3302	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3303	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3304	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3305	GCPhys \|= i * (PAGE_SIZE / 2);
3306	# endif
3307	}
3308	else
3309	{
3310	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3311	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3312	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3313	GCPhys \|= i * X86_PAGE_2M_SIZE;
3314	# endif
3315	}
3316
3317	if ( pShwPage->GCPhys == GCPhys
3318	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3319	&& ( pShwPage->fCached
3320	\|\| ( !fGlobal
3321	&& ( false
3322	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3323	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3324	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3325	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3326	# else
3327	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3328	# endif
3329	\|\| ( !pShwPage->fSeenNonGlobal
3330	&& (cr4 & X86_CR4_PGE))
3331	# endif
3332	)
3333	)
3334	)
3335	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3336	\|\| ( fBigPagesSupported
3337	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3338	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3339	)
3340	)
3341	{
3342	# ifdef VBOX_WITH_STATISTICS
3343	if ( !fGlobal
3344	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3345	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3346	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3347	# else
3348	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3349	# endif
3350	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
3351	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3352	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
3353	else
3354	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
3355	# endif /* VBOX_WITH_STATISTICS */
3356	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3357	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3358	//# ifdef PGMPOOL_WITH_CACHE
3359	// pgmPoolCacheUsed(pPool, pShwPage);
3360	//# endif
3361	}
3362	else
3363	{
3364	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3365	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3366	# else
3367	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3368	# endif
3369	pPDEDst->u = 0;
3370	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
3371	}
3372	}
3373	else
3374	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
3375	pPDEDst++;
3376	}
3377	}
3378	# if PGM_GST_TYPE == PGM_TYPE_PAE
3379	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3380	# else
3381	else if (iPD != iPdNoMapping)
3382	# endif
3383	{
3384	/*
3385	* Check if there is any page directory to mark not present here.
3386	*/
3387	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3388	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3389	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3390	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3391	# else
3392	const unsigned iPdShw = iPD; NOREF(iPdShw);
3393	# endif
3394	{
3395	if (pPDEDst->n.u1Present)
3396	{
3397	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3398	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3399	# else
3400	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3401	# endif
3402	pPDEDst->u = 0;
3403	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
3404	}
3405	pPDEDst++;
3406	}
3407	}
3408	else
3409	{
3410	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3411	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3412	&& !defined(PGM_WITHOUT_MAPPINGS)
3413
3414	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3415
3416	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3417	if (pVM->pgm.s.fMappingsFixed)
3418	{
3419	/* It's fixed, just skip the mapping. */
3420	pMapping = pMapping->CTXALLSUFF(pNext);
3421	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3422	}
3423	else
3424	{
3425	/*
3426	* Check for conflicts for subsequent pagetables
3427	* and advance to the next mapping.
3428	*/
3429	iPdNoMapping = ~0U;
3430	unsigned iPT = cPTs;
3431	while (iPT-- > 1)
3432	{
3433	if ( pPDSrc->a[iPD + iPT].n.u1Present
3434	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3435	{
3436	# ifdef IN_RING3
3437	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3438	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3439	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3440	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3441	# endif
3442	if (VBOX_FAILURE(rc))
3443	return rc;
3444
3445	/*
3446	* Update iPdNoMapping and pMapping.
3447	*/
3448	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3449	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3450	pMapping = pMapping->CTXALLSUFF(pNext);
3451	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3452	break;
3453	# else
3454	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3455	return VINF_PGM_SYNC_CR3;
3456	# endif
3457	}
3458	}
3459	if (iPdNoMapping == ~0U && pMapping)
3460	{
3461	pMapping = pMapping->CTXALLSUFF(pNext);
3462	if (pMapping)
3463	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3464	}
3465	}
3466
3467	/* advance. */
3468	iPD += cPTs - 1;
3469	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3470	# if PGM_GST_TYPE != PGM_SHW_TYPE
3471	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3472	# endif
3473	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3474	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3475	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3476	}
3477
3478	} /* for iPD */
3479	} /* for each PDPTE (PAE) */
3480	} /* for each page map level 4 entry (amd64) */
3481	return VINF_SUCCESS;
3482
3483	# else /* guest real and protected mode */
3484	return VINF_SUCCESS;
3485	# endif
3486	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
3487	}
3488
3489
3490
3491
3492	#ifdef VBOX_STRICT
3493	#ifdef IN_GC
3494	# undef AssertMsgFailed
3495	# define AssertMsgFailed Log
3496	#endif
3497	#ifdef IN_RING3
3498	# include <VBox/dbgf.h>
3499
3500	/**
3501	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3502	*
3503	* @returns VBox status code (VINF_SUCCESS).
3504	* @param pVM The VM handle.
3505	* @param cr3 The root of the hierarchy.
3506	* @param crr The cr4, only PAE and PSE is currently used.
3507	* @param fLongMode Set if long mode, false if not long mode.
3508	* @param cMaxDepth Number of levels to dump.
3509	* @param pHlp Pointer to the output functions.
3510	*/
3511	__BEGIN_DECLS
3512	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3513	__END_DECLS
3514
3515	#endif
3516
3517	/**
3518	* Checks that the shadow page table is in sync with the guest one.
3519	*
3520	* @returns The number of errors.
3521	* @param pVM The virtual machine.
3522	* @param cr3 Guest context CR3 register
3523	* @param cr4 Guest context CR4 register
3524	* @param GCPtr Where to start. Defaults to 0.
3525	* @param cb How much to check. Defaults to everything.
3526	*/
3527	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3528	{
3529	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
3530	return 0;
3531	#else
3532	unsigned cErrors = 0;
3533
3534	#if PGM_GST_TYPE == PGM_TYPE_PAE
3535	/* @todo currently broken; crashes below somewhere */
3536	AssertFailed();
3537	#endif
3538
3539	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3540	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3541	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3542
3543	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3544	bool fBigPagesSupported = true;
3545	# else
3546	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3547	# endif
3548	PPGM pPGM = &pVM->pgm.s;
3549	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3550	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3551	# ifndef IN_RING0
3552	RTHCPHYS HCPhys; /* general usage. */
3553	# endif
3554	int rc;
3555
3556	/*
3557	* Check that the Guest CR3 and all its mappings are correct.
3558	*/
3559	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3560	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3561	false);
3562	# ifndef IN_RING0
3563	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3564	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3565	# else
3566	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3567	# endif
3568	AssertRCReturn(rc, 1);
3569	HCPhys = NIL_RTHCPHYS;
3570	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3571	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3572	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3573	RTGCPHYS GCPhys;
3574	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3575	AssertRCReturn(rc, 1);
3576	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3577	# endif
3578	#endif /* !IN_RING0 */
3579
3580	/*
3581	* Get and check the Shadow CR3.
3582	*/
3583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3584	unsigned cPDEs = X86_PG_ENTRIES;
3585	unsigned ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3586	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3587	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3588	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3589	# else
3590	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3591	# endif
3592	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3593	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3594	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3595	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3596	# endif
3597	if (cb != ~(RTGCUINTPTR)0)
3598	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3599
3600	/** @todo call the other two PGMAssert() functions. /
3601
3602	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3603	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
3604	# endif
3605
3606	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3607	unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3608
3609	for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3610	{
3611	PPGMPOOLPAGE pShwPdpt = NULL;
3612	PX86PML4E pPml4eSrc, pPml4eDst;
3613	RTGCPHYS GCPhysPdptSrc;
3614
3615	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3616	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3617
3618	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3619	if (!pPml4eDst->n.u1Present)
3620	{
3621	GCPtr += UINT64_C(_2M * 512 * 512);
3622	continue;
3623	}
3624
3625	# if PGM_GST_TYPE == PGM_TYPE_PAE
3626	/* not correct to call pgmPoolGetPage */
3627	# endif
3628	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3629	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3630
3631	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3632	{
3633	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3634	GCPtr += UINT64_C(_2M * 512 * 512);
3635	cErrors++;
3636	continue;
3637	}
3638
3639	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3640	{
3641	AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3642	GCPtr += UINT64_C(_2M * 512 * 512);
3643	cErrors++;
3644	continue;
3645	}
3646
3647	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3648	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3649	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3650	{
3651	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3652	GCPtr += UINT64_C(_2M * 512 * 512);
3653	cErrors++;
3654	continue;
3655	}
3656	# else
3657	{
3658	# endif
3659
3660	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3661	/*
3662	* Check the PDPTEs too.
3663	*/
3664	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3665
3666	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3667	{
3668	unsigned iPDSrc;
3669	PPGMPOOLPAGE pShwPde = NULL;
3670	PX86PDPE pPdpeDst;
3671	RTGCPHYS GCPhysPdeSrc;
3672	# if PGM_GST_TYPE == PGM_TYPE_PAE
3673	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3674	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
3675	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3676	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3677	# else
3678	PX86PML4E pPml4eSrc;
3679	X86PDPE PdpeSrc;
3680	PX86PDPT pPdptDst;
3681	PX86PDPAE pPDDst;
3682	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3683
3684	rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3685	if (rc != VINF_SUCCESS)
3686	{
3687	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3688	GCPtr += 512 * _2M;
3689	continue; /* next PDPTE */
3690	}
3691	Assert(pPDDst);
3692	# endif
3693	Assert(iPDSrc == 0);
3694
3695	pPdpeDst = &pPdptDst->a[iPdpte];
3696
3697	if (!pPdpeDst->n.u1Present)
3698	{
3699	GCPtr += 512 * _2M;
3700	continue; /* next PDPTE */
3701	}
3702
3703	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3704	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3705
3706	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3707	{
3708	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3709	GCPtr += 512 * _2M;
3710	cErrors++;
3711	continue;
3712	}
3713
3714	if (GCPhysPdeSrc != pShwPde->GCPhys)
3715	{
3716	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3717	AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3718	# else
3719	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3720	# endif
3721	GCPtr += 512 * _2M;
3722	cErrors++;
3723	continue;
3724	}
3725
3726	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3727	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3728	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3729	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3730	{
3731	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3732	GCPtr += 512 * _2M;
3733	cErrors++;
3734	continue;
3735	}
3736	# endif
3737
3738	# else
3739	{
3740	# endif
3741	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3742	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3743	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3744	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3745	# else
3746	const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3747	# endif
3748	# endif
3749	/*
3750	* Iterate the shadow page directory.
3751	*/
3752	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3753	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3754
3755	for (;
3756	iPDDst < cPDEs;
3757	iPDDst++, GCPtr += ulIncrement)
3758	{
3759	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3760	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3761	{
3762	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3763	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3764	{
3765	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3766	cErrors++;
3767	continue;
3768	}
3769	}
3770	else if ( (PdeDst.u & X86_PDE_P)
3771	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3772	)
3773	{
3774	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3775	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3776	if (!pPoolPage)
3777	{
3778	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3779	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3780	cErrors++;
3781	continue;
3782	}
3783	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3784
3785	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3786	{
3787	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3788	GCPtr, (uint64_t)PdeDst.u));
3789	cErrors++;
3790	}
3791
3792	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3793	{
3794	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3795	GCPtr, (uint64_t)PdeDst.u));
3796	cErrors++;
3797	}
3798
3799	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3800	if (!PdeSrc.n.u1Present)
3801	{
3802	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3803	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3804	cErrors++;
3805	continue;
3806	}
3807
3808	if ( !PdeSrc.b.u1Size
3809	\|\| !fBigPagesSupported)
3810	{
3811	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3812	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3813	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3814	# endif
3815	}
3816	else
3817	{
3818	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3819	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3820	{
3821	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3822	GCPtr, (uint64_t)PdeSrc.u));
3823	cErrors++;
3824	continue;
3825	}
3826	# endif
3827	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3828	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3829	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3830	# endif
3831	}
3832
3833	if ( pPoolPage->enmKind
3834	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3835	{
3836	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3837	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3838	cErrors++;
3839	}
3840
3841	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3842	if (!pPhysPage)
3843	{
3844	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3845	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3846	cErrors++;
3847	continue;
3848	}
3849
3850	if (GCPhysGst != pPoolPage->GCPhys)
3851	{
3852	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3853	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3854	cErrors++;
3855	continue;
3856	}
3857
3858	if ( !PdeSrc.b.u1Size
3859	\|\| !fBigPagesSupported)
3860	{
3861	/*
3862	* Page Table.
3863	*/
3864	const GSTPT *pPTSrc;
3865	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3866	if (VBOX_FAILURE(rc))
3867	{
3868	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3869	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3870	cErrors++;
3871	continue;
3872	}
3873	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3874	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3875	{
3876	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3877	// (This problem will go away when/if we shadow multiple CR3s.)
3878	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3879	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3880	cErrors++;
3881	continue;
3882	}
3883	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3884	{
3885	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3886	GCPtr, (uint64_t)PdeDst.u));
3887	cErrors++;
3888	continue;
3889	}
3890
3891	/* iterate the page table. */
3892	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3893	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3894	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3895	# else
3896	const unsigned offPTSrc = 0;
3897	# endif
3898	for (unsigned iPT = 0, off = 0;
3899	iPT < ELEMENTS(pPTDst->a);
3900	iPT++, off += PAGE_SIZE)
3901	{
3902	const SHWPTE PteDst = pPTDst->a[iPT];
3903
3904	/* skip not-present entries. */
3905	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3906	continue;
3907	Assert(PteDst.n.u1Present);
3908
3909	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3910	if (!PteSrc.n.u1Present)
3911	{
3912	# ifdef IN_RING3
3913	PGMAssertHandlerAndFlagsInSync(pVM);
3914	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3915	# endif
3916	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3917	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3918	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3919	cErrors++;
3920	continue;
3921	}
3922
3923	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3924	# if 1 /** @todo sync accessed bit properly... */
3925	fIgnoreFlags \|= X86_PTE_A;
3926	# endif
3927
3928	/* match the physical addresses */
3929	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3930	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3931
3932	# ifdef IN_RING3
3933	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3934	if (VBOX_FAILURE(rc))
3935	{
3936	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3937	{
3938	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3939	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3940	cErrors++;
3941	continue;
3942	}
3943	}
3944	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3945	{
3946	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3947	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3948	cErrors++;
3949	continue;
3950	}
3951	# endif
3952
3953	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3954	if (!pPhysPage)
3955	{
3956	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3957	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3958	{
3959	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3960	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3961	cErrors++;
3962	continue;
3963	}
3964	# endif
3965	if (PteDst.n.u1Write)
3966	{
3967	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3968	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3969	cErrors++;
3970	}
3971	fIgnoreFlags \|= X86_PTE_RW;
3972	}
3973	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3974	{
3975	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3976	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3977	cErrors++;
3978	continue;
3979	}
3980
3981	/* flags */
3982	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3983	{
3984	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3985	{
3986	if (PteDst.n.u1Write)
3987	{
3988	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3989	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3990	cErrors++;
3991	continue;
3992	}
3993	fIgnoreFlags \|= X86_PTE_RW;
3994	}
3995	else
3996	{
3997	if (PteDst.n.u1Present)
3998	{
3999	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
4000	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4001	cErrors++;
4002	continue;
4003	}
4004	fIgnoreFlags \|= X86_PTE_P;
4005	}
4006	}
4007	else
4008	{
4009	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4010	{
4011	if (PteDst.n.u1Write)
4012	{
4013	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4014	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4015	cErrors++;
4016	continue;
4017	}
4018	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4019	{
4020	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4021	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4022	cErrors++;
4023	continue;
4024	}
4025	if (PteDst.n.u1Dirty)
4026	{
4027	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4029	cErrors++;
4030	}
4031	# if 0 /** @todo sync access bit properly... */
4032	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4033	{
4034	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4035	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4036	cErrors++;
4037	}
4038	fIgnoreFlags \|= X86_PTE_RW;
4039	# else
4040	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4041	# endif
4042	}
4043	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4044	{
4045	/* access bit emulation (not implemented). */
4046	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4047	{
4048	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4050	cErrors++;
4051	continue;
4052	}
4053	if (!PteDst.n.u1Accessed)
4054	{
4055	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4056	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4057	cErrors++;
4058	}
4059	fIgnoreFlags \|= X86_PTE_P;
4060	}
4061	# ifdef DEBUG_sandervl
4062	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4063	# endif
4064	}
4065
4066	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4067	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4068	)
4069	{
4070	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4071	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4072	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4073	cErrors++;
4074	continue;
4075	}
4076	} /* foreach PTE */
4077	}
4078	else
4079	{
4080	/*
4081	* Big Page.
4082	*/
4083	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4084	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4085	{
4086	if (PdeDst.n.u1Write)
4087	{
4088	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4089	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4090	cErrors++;
4091	continue;
4092	}
4093	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4094	{
4095	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4096	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4097	cErrors++;
4098	continue;
4099	}
4100	# if 0 /** @todo sync access bit properly... */
4101	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4102	{
4103	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4104	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4105	cErrors++;
4106	}
4107	fIgnoreFlags \|= X86_PTE_RW;
4108	# else
4109	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4110	# endif
4111	}
4112	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4113	{
4114	/* access bit emulation (not implemented). */
4115	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4116	{
4117	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4118	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4119	cErrors++;
4120	continue;
4121	}
4122	if (!PdeDst.n.u1Accessed)
4123	{
4124	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4125	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4126	cErrors++;
4127	}
4128	fIgnoreFlags \|= X86_PTE_P;
4129	}
4130
4131	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4132	{
4133	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4134	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4135	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4136	cErrors++;
4137	}
4138
4139	/* iterate the page table. */
4140	for (unsigned iPT = 0, off = 0;
4141	iPT < ELEMENTS(pPTDst->a);
4142	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4143	{
4144	const SHWPTE PteDst = pPTDst->a[iPT];
4145
4146	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4147	{
4148	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4149	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4150	cErrors++;
4151	}
4152
4153	/* skip not-present entries. */
4154	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4155	continue;
4156
4157	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4158
4159	/* match the physical addresses */
4160	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4161
4162	# ifdef IN_RING3
4163	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4164	if (VBOX_FAILURE(rc))
4165	{
4166	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4167	{
4168	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4169	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4170	cErrors++;
4171	}
4172	}
4173	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4174	{
4175	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4176	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4177	cErrors++;
4178	continue;
4179	}
4180	# endif
4181	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4182	if (!pPhysPage)
4183	{
4184	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4185	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4186	{
4187	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4188	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4189	cErrors++;
4190	continue;
4191	}
4192	# endif
4193	if (PteDst.n.u1Write)
4194	{
4195	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4196	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4197	cErrors++;
4198	}
4199	fIgnoreFlags \|= X86_PTE_RW;
4200	}
4201	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4202	{
4203	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4204	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4205	cErrors++;
4206	continue;
4207	}
4208
4209	/* flags */
4210	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4211	{
4212	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4213	{
4214	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4215	{
4216	if (PteDst.n.u1Write)
4217	{
4218	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4219	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4220	cErrors++;
4221	continue;
4222	}
4223	fIgnoreFlags \|= X86_PTE_RW;
4224	}
4225	}
4226	else
4227	{
4228	if (PteDst.n.u1Present)
4229	{
4230	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4232	cErrors++;
4233	continue;
4234	}
4235	fIgnoreFlags \|= X86_PTE_P;
4236	}
4237	}
4238
4239	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4240	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4241	)
4242	{
4243	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4244	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4245	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4246	cErrors++;
4247	continue;
4248	}
4249	} /* for each PTE */
4250	}
4251	}
4252	/* not present */
4253
4254	} /* for each PDE */
4255
4256	} /* for each PDPTE */
4257
4258	} /* for each PML4E */
4259
4260	# ifdef DEBUG
4261	if (cErrors)
4262	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4263	# endif
4264
4265	#endif
4266	return cErrors;
4267
4268	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
4269	}
4270	#endif /* VBOX_STRICT */
4271

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 10013

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