PGMAllBth.h@ 101504

Last change on this file since 101504 was 101058, checked in by vboxsync, 15 months ago
VMM: Nested VMX: bugref:10318 Pass only the final (leaf) SLAT PTE entry to (NestedSyncPageWorker) rather than the whole page-walk result.
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File size: 235.6 KB

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1	/* $Id: PGMAllBth.h 101058 2023-09-08 04:02:27Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
15	*
16	* This file is part of VirtualBox base platform packages, as
17	* available from https://www.virtualbox.org.
18	*
19	* This program is free software; you can redistribute it and/or
20	* modify it under the terms of the GNU General Public License
21	* as published by the Free Software Foundation, in version 3 of the
22	* License.
23	*
24	* This program is distributed in the hope that it will be useful, but
25	* WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27	* General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, see <https://www.gnu.org/licenses>.
31	*
32	* SPDX-License-Identifier: GPL-3.0-only
33	*/
34
35	#ifdef _MSC_VER
36	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
37	* real/prot-guest+RC mode. */
38	# pragma warning(disable: 4505)
39	#endif
40
41
42	/*********************************************************************************************************************************
43	* Internal Functions *
44	*********************************************************************************************************************************/
45	RT_C_DECLS_BEGIN
46	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
47	#ifndef IN_RING3
48	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken);
49	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
50	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken);
51	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
52	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
53	unsigned iPte, SLATPTE GstSlatPte);
54	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
55	uint32_t uErr, PPGMPTWALKGST pGstWalkAll);
56	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll);
57	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
58	#endif
59	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
60	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
61	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
62	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
63	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
64	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
65	#else
66	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
67	#endif
68	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
69	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
70	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
71	#ifdef VBOX_STRICT
72	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
73	#endif
74	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
75	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
76
77	#ifdef IN_RING3
78	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
79	#endif
80	RT_C_DECLS_END
81
82
83
84
85	/*
86	* Filter out some illegal combinations of guest and shadow paging, so we can
87	* remove redundant checks inside functions.
88	*/
89	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
90	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
91	# error "Invalid combination; PAE guest implies PAE shadow"
92	#endif
93
94	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
95	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
96	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
97	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
98	#endif
99
100	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
101	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
102	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
103	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
104	#endif
105
106	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
107	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
108	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
109	#endif
110
111
112	/**
113	* Enters the shadow+guest mode.
114	*
115	* @returns VBox status code.
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param GCPhysCR3 The physical address from the CR3 register.
118	*/
119	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
120	{
121	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
122	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
123	*/
124	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
125	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
126	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
127	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
128	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
129
130	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
131
132	Assert(!pVM->pgm.s.fNestedPaging);
133
134	PGM_LOCK_VOID(pVM);
135	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
136	* but any calls to GC need a proper shadow page setup as well.
137	*/
138	/* Free the previous root mapping if still active. */
139	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
140	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
141	if (pOldShwPageCR3)
142	{
143	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
144
145	/* Mark the page as unlocked; allow flushing again. */
146	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
147
148	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
149	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
150	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
151	}
152
153	/* construct a fake address. */
154	GCPhysCR3 = RT_BIT_64(63);
155	PPGMPOOLPAGE pNewShwPageCR3;
156	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
157	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
158	&pNewShwPageCR3);
159	AssertRCReturn(rc, rc);
160
161	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
162	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
163
164	/* Mark the page as locked; disallow flushing. */
165	pgmPoolLockPage(pPool, pNewShwPageCR3);
166
167	/* Set the current hypervisor CR3. */
168	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
169
170	PGM_UNLOCK(pVM);
171	return rc;
172	#else
173	NOREF(pVCpu); NOREF(GCPhysCR3);
174	return VINF_SUCCESS;
175	#endif
176	}
177
178
179	#ifndef IN_RING3
180
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	/**
183	* Deal with a guest page fault.
184	*
185	* @returns Strict VBox status code.
186	* @retval VINF_EM_RAW_GUEST_TRAP
187	* @retval VINF_EM_RAW_EMULATE_INSTR
188	*
189	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
190	* @param pWalk The guest page table walk result.
191	* @param uErr The error code.
192	*/
193	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, RTGCUINT uErr)
194	{
195	/*
196	* Calc the error code for the guest trap.
197	*/
198	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
199	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
200	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
201	if ( pWalk->fRsvdError
202	\|\| pWalk->fBadPhysAddr)
203	{
204	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
205	Assert(!pWalk->fNotPresent);
206	}
207	else if (!pWalk->fNotPresent)
208	uNewErr \|= X86_TRAP_PF_P;
209	TRPMSetErrorCode(pVCpu, uNewErr);
210
211	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pWalk->GCPtr, uErr, pWalk->uLevel));
212	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
213	return VINF_EM_RAW_GUEST_TRAP;
214	}
215	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
216
217
218	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
219	/**
220	* Deal with a guest page fault.
221	*
222	* The caller has taken the PGM lock.
223	*
224	* @returns Strict VBox status code.
225	*
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param uErr The error code.
228	* @param pCtx Pointer to the register context for the CPU.
229	* @param pvFault The fault address.
230	* @param pPage The guest page at @a pvFault.
231	* @param pWalk The guest page table walk result.
232	* @param pGstWalk The guest paging-mode specific walk information.
233	* @param pfLockTaken PGM lock taken here or not (out). This is true
234	* when we're called.
235	*/
236	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
237	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
238	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
239	, PPGMPTWALK pWalk
240	, PGSTPTWALK pGstWalk
241	# endif
242	)
243	{
244	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
245	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
246	# endif
247	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
248	VBOXSTRICTRC rcStrict;
249
250	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
251	{
252	/*
253	* Physical page access handler.
254	*/
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	const RTGCPHYS GCPhysFault = pWalk->GCPhys;
257	# else
258	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
259	# endif
260	PPGMPHYSHANDLER pCur;
261	rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysFault, &pCur);
262	if (RT_SUCCESS(rcStrict))
263	{
264	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
265
266	# ifdef PGM_SYNC_N_PAGES
267	/*
268	* If the region is write protected and we got a page not present fault, then sync
269	* the pages. If the fault was caused by a read, then restart the instruction.
270	* In case of write access continue to the GC write handler.
271	*
272	* ASSUMES that there is only one handler per page or that they have similar write properties.
273	*/
274	if ( !(uErr & X86_TRAP_PF_P)
275	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
276	{
277	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
278	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
279	# else
280	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
281	# endif
282	if ( RT_FAILURE(rcStrict)
283	\|\| !(uErr & X86_TRAP_PF_RW)
284	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
285	{
286	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
288	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
289	return rcStrict;
290	}
291	}
292	# endif
293	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
294	/*
295	* If the access was not thru a #PF(RSVD\|...) resync the page.
296	*/
297	if ( !(uErr & X86_TRAP_PF_RSVD)
298	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
299	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
300	&& (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
301	== PGM_PTATTRS_W_MASK /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
302	# endif
303	)
304	{
305	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
306	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
307	# else
308	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
309	# endif
310	if ( RT_FAILURE(rcStrict)
311	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
312	{
313	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
314	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
315	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
316	return rcStrict;
317	}
318	}
319	# endif
320
321	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
322	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
323	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
324	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
325	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
326	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
327	else
328	{
329	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
330	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
331	}
332
333	if (pCurType->pfnPfHandler)
334	{
335	STAM_PROFILE_START(&pCur->Stat, h);
336
337	if (pCurType->fKeepPgmLock)
338	{
339	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault,
340	!pCurType->fRing0DevInsIdx ? pCur->uUser
341	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser));
342
343	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
344	}
345	else
346	{
347	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
348	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
349	PGM_UNLOCK(pVM);
350	*pfLockTaken = false;
351
352	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, uUser);
353
354	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
355	}
356	}
357	else
358	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
359
360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
361	return rcStrict;
362	}
363	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
364	}
365
366	/*
367	* There is a handled area of the page, but this fault doesn't belong to it.
368	* We must emulate the instruction.
369	*
370	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
371	* we first check if this was a page-not-present fault for a page with only
372	* write access handlers. Restart the instruction if it wasn't a write access.
373	*/
374	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersUnhandled);
375
376	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
377	&& !(uErr & X86_TRAP_PF_P))
378	{
379	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
380	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
381	# else
382	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
383	# endif
384	if ( RT_FAILURE(rcStrict)
385	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
386	\|\| !(uErr & X86_TRAP_PF_RW))
387	{
388	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
389	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
390	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
391	return rcStrict;
392	}
393	}
394
395	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
396	* It's writing to an unhandled part of the LDT page several million times.
397	*/
398	rcStrict = PGMInterpretInstruction(pVCpu, pvFault);
399	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
400	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
401	return rcStrict;
402	} /* if any kind of handler */
403	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
404
405
406	/**
407	* \#PF Handler for raw-mode guest execution.
408	*
409	* @returns VBox status code (appropriate for trap handling and GC return).
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param uErr The trap error code.
413	* @param pCtx Pointer to the register context for the CPU.
414	* @param pvFault The fault address.
415	* @param pfLockTaken PGM lock taken here or not (out)
416	*/
417	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken)
418	{
419	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
420
421	*pfLockTaken = false;
422
423	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
424	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
425	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
426	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
427	&& PGM_SHW_TYPE != PGM_TYPE_NONE
428	int rc;
429
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	/*
432	* Walk the guest page translation tables and check if it's a guest fault.
433	*/
434	PGMPTWALK Walk;
435	GSTPTWALK GstWalk;
436	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &Walk, &GstWalk);
437	if (RT_FAILURE_NP(rc))
438	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
439
440	/* assert some GstWalk sanity. */
441	# if PGM_GST_TYPE == PGM_TYPE_AMD64
442	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
443	# endif
444	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
445	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
446	# endif
447	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
448	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
449	Assert(Walk.fSucceeded);
450	Assert(Walk.fEffective & PGM_PTATTRS_R_MASK);
451
452	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
453	{
454	if ( ( (uErr & X86_TRAP_PF_RW)
455	&& !(Walk.fEffective & PGM_PTATTRS_W_MASK)
456	&& ( (uErr & X86_TRAP_PF_US)
457	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
458	\|\| ((uErr & X86_TRAP_PF_US) && !(Walk.fEffective & PGM_PTATTRS_US_MASK))
459	\|\| ((uErr & X86_TRAP_PF_ID) && (Walk.fEffective & PGM_PTATTRS_NX_MASK))
460	)
461	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
462	}
463
464	/* Take the big lock now before we update flags. */
465	*pfLockTaken = true;
466	PGM_LOCK_VOID(pVM);
467
468	/*
469	* Set the accessed and dirty flags.
470	*/
471	/** @todo Should probably use cmpxchg logic here as we're potentially racing
472	* other CPUs in SMP configs. (the lock isn't enough, since we take it
473	* after walking and the page tables could be stale already) */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	if (!(GstWalk.Pml4e.u & X86_PML4E_A))
476	{
477	GstWalk.Pml4e.u \|= X86_PML4E_A;
478	GST_ATOMIC_OR(&GstWalk.pPml4e->u, X86_PML4E_A);
479	}
480	if (!(GstWalk.Pdpe.u & X86_PDPE_A))
481	{
482	GstWalk.Pdpe.u \|= X86_PDPE_A;
483	GST_ATOMIC_OR(&GstWalk.pPdpe->u, X86_PDPE_A);
484	}
485	# endif
486	if (Walk.fBigPage)
487	{
488	Assert(GstWalk.Pde.u & X86_PDE_PS);
489	if (uErr & X86_TRAP_PF_RW)
490	{
491	if ((GstWalk.Pde.u & (X86_PDE4M_A \| X86_PDE4M_D)) != (X86_PDE4M_A \| X86_PDE4M_D))
492	{
493	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
494	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A \| X86_PDE4M_D);
495	}
496	}
497	else
498	{
499	if (!(GstWalk.Pde.u & X86_PDE4M_A))
500	{
501	GstWalk.Pde.u \|= X86_PDE4M_A;
502	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A);
503	}
504	}
505	}
506	else
507	{
508	Assert(!(GstWalk.Pde.u & X86_PDE_PS));
509	if (!(GstWalk.Pde.u & X86_PDE_A))
510	{
511	GstWalk.Pde.u \|= X86_PDE_A;
512	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE_A);
513	}
514
515	if (uErr & X86_TRAP_PF_RW)
516	{
517	# ifdef VBOX_WITH_STATISTICS
518	if (GstWalk.Pte.u & X86_PTE_D)
519	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageAlreadyDirty));
520	else
521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtiedPage));
522	# endif
523	if ((GstWalk.Pte.u & (X86_PTE_A \| X86_PTE_D)) != (X86_PTE_A \| X86_PTE_D))
524	{
525	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
526	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A \| X86_PTE_D);
527	}
528	}
529	else
530	{
531	if (!(GstWalk.Pte.u & X86_PTE_A))
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A);
535	}
536	}
537	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538	}
539	#if 0
540	/* Disabling this since it's not reliable for SMP, see @bugref{10092#c22}. */
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	#endif
544
545	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	PGM_LOCK_VOID(pVM);
551	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
554	/*
555	* If it is a reserved bit fault we know that it is an MMIO (access
556	* handler) related fault and can skip some 200 lines of code.
557	*/
558	if (uErr & X86_TRAP_PF_RSVD)
559	{
560	Assert(uErr & X86_TRAP_PF_P);
561	PPGMPAGE pPage;
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage,
566	pfLockTaken, &Walk, &GstWalk));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
568	# else
569	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
570	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
571	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
572	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
573	# endif
574	AssertRC(rc);
575	PGM_INVL_PG(pVCpu, pvFault);
576	return rc; /* Restart with the corrected entry. */
577	}
578	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
579
580	/*
581	* Fetch the guest PDE, PDPE and PML4E.
582	*/
583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
584	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
585	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
588	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PAE
591	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
592	# else
593	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PX86PDPAE pPDDst;
600	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
602	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
603	# else
604	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
605	# endif
606	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
607
608	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
609	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
610	PEPTPD pPDDst;
611	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
612	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
613	# endif
614	Assert(pPDDst);
615
616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
617	/*
618	* Dirty page handling.
619	*
620	* If we successfully correct the write protection fault due to dirty bit
621	* tracking, then return immediately.
622	*/
623	if (uErr & X86_TRAP_PF_RW) /* write fault? */
624	{
625	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
626	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
628	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
629	{
630	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0
631	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
632	? &pVCpu->pgm.s.Stats.StatRZTrap0eTime2DirtyAndAccessed
633	: &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
634	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
635	return VINF_SUCCESS;
636	}
637	#ifdef DEBUG_bird
638	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
639	AssertMsg(Walk.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
640	#endif
641	}
642
643	# if 0 /* rarely useful; leave for debugging. */
644	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
645	# endif
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647
648	/*
649	* A common case is the not-present error caused by lazy page table syncing.
650	*
651	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
652	* here so we can safely assume that the shadow PT is present when calling
653	* SyncPage later.
654	*
655	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
656	* of mapping conflict and defer to SyncCR3 in R3.
657	* (Again, we do NOT support access handlers for non-present guest pages.)
658	*
659	*/
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	Assert(GstWalk.Pde.u & X86_PDE_P);
662	# endif
663	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
664	&& !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
665	{
666	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
668	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
670	# else
671	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
672	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
673	# endif
674	if (RT_SUCCESS(rc))
675	return rc;
676	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
677	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
678	return VINF_PGM_SYNC_CR3;
679	}
680
681	/*
682	* Check if this fault address is flagged for special treatment,
683	* which means we'll have to figure out the physical address and
684	* check flags associated with it.
685	*
686	* ASSUME that we can limit any special access handling to pages
687	* in page tables which the guest believes to be present.
688	*/
689	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
690	RTGCPHYS GCPhys = Walk.GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
691	# else
692	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK);
693	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
694	PPGMPAGE pPage;
695	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
696	if (RT_FAILURE(rc))
697	{
698	/*
699	* When the guest accesses invalid physical memory (e.g. probing
700	* of RAM or accessing a remapped MMIO range), then we'll fall
701	* back to the recompiler to emulate the instruction.
702	*/
703	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
704	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
705	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
706	return VINF_EM_RAW_EMULATE_INSTR;
707	}
708
709	/*
710	* Any handlers for this page?
711	*/
712	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
713	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
714	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken,
715	&Walk, &GstWalk));
716	# else
717	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
718	# endif
719
720	/*
721	* We are here only if page is present in Guest page tables and
722	* trap is not handled by our handlers.
723	*
724	* Check it for page out-of-sync situation.
725	*/
726	if (!(uErr & X86_TRAP_PF_P))
727	{
728	/*
729	* Page is not present in our page tables. Try to sync it!
730	*/
731	if (uErr & X86_TRAP_PF_US)
732	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
733	else /* supervisor */
734	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
735
736	if (PGM_PAGE_IS_BALLOONED(pPage))
737	{
738	/* Emulate reads from ballooned pages as they are not present in
739	our shadow page tables. (Required for e.g. Solaris guests; soft
740	ecc, random nr generator.) */
741	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
742	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
743	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
744	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Ballooned; });
745	return rc;
746	}
747
748	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
749	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
750	# else
751	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
752	# endif
753	if (RT_SUCCESS(rc))
754	{
755	/* The page was successfully synced, return to the guest. */
756	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
757	return VINF_SUCCESS;
758	}
759	}
760	else /* uErr & X86_TRAP_PF_P: */
761	{
762	/*
763	* Write protected pages are made writable when the guest makes the
764	* first write to it. This happens for pages that are shared, write
765	* monitored or not yet allocated.
766	*
767	* We may also end up here when CR0.WP=0 in the guest.
768	*
769	* Also, a side effect of not flushing global PDEs are out of sync
770	* pages due to physical monitored regions, that are no longer valid.
771	* Assume for now it only applies to the read/write flag.
772	*/
773	if (uErr & X86_TRAP_PF_RW)
774	{
775	/*
776	* Check if it is a read-only page.
777	*/
778	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
779	{
780	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
781	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
782	Assert(!PGM_PAGE_IS_ZERO(pPage));
783	# endif
784	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
785	# ifdef PGM_WITH_PAGE_ZEROING_DETECTION
786	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO
787	&& (pvFault & X86_PAGE_OFFSET_MASK) == 0
788	&& pgmHandlePageZeroingCode(pVCpu, pCtx))
789	{
790	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2PageZeroing; });
791	return VINF_SUCCESS;
792	}
793	# endif
794	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
795
796	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
797	if (rc != VINF_SUCCESS)
798	{
799	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
800	return rc;
801	}
802	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
803	return VINF_EM_NO_MEMORY;
804	}
805
806	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
807	/*
808	* Check to see if we need to emulate the instruction if CR0.WP=0.
809	*/
810	if ( !(Walk.fEffective & PGM_PTATTRS_W_MASK)
811	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
812	&& CPUMGetGuestCPL(pVCpu) < 3)
813	{
814	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
815
816	/*
817	* The Netware WP0+RO+US hack.
818	*
819	* Netware sometimes(/always?) runs with WP0. It has been observed doing
820	* excessive write accesses to pages which are mapped with US=1 and RW=0
821	* while WP=0. This causes a lot of exits and extremely slow execution.
822	* To avoid trapping and emulating every write here, we change the shadow
823	* page table entry to map it as US=0 and RW=1 until user mode tries to
824	* access it again (see further below). We count these shadow page table
825	* changes so we can avoid having to clear the page pool every time the WP
826	* bit changes to 1 (see PGMCr0WpEnabled()).
827	*/
828	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
829	if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
830	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
831	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
832	{
833	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, Walk.fBigPage));
834	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, Walk.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
835	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
836	{
837	PGM_INVL_PG(pVCpu, pvFault);
838	pVCpu->pgm.s.cNetwareWp0Hacks++;
839	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsHack; });
840	return rc;
841	}
842	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
843	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
844	}
845	# endif
846
847	/* Interpret the access. */
848	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
849	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
850	if (RT_SUCCESS(rc))
851	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulInRZ);
852	else
853	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulToR3);
854	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2WPEmulation; });
855	return rc;
856	}
857	# endif
858	/// @todo count the above case; else
859	if (uErr & X86_TRAP_PF_US)
860	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
861	else /* supervisor */
862	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
863
864	/*
865	* Sync the page.
866	*
867	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
868	* page is not present, which is not true in this case.
869	*/
870	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
871	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
872	# else
873	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
874	# endif
875	if (RT_SUCCESS(rc))
876	{
877	/*
878	* Page was successfully synced, return to guest but invalidate
879	* the TLB first as the page is very likely to be in it.
880	*/
881	# if PGM_SHW_TYPE == PGM_TYPE_EPT
882	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
883	# else
884	PGM_INVL_PG(pVCpu, pvFault);
885	# endif
886	# ifdef VBOX_STRICT
887	PGMPTWALK GstPageWalk;
888	GstPageWalk.GCPhys = RTGCPHYS_MAX;
889	if (!pVM->pgm.s.fNestedPaging)
890	{
891	rc = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
892	AssertMsg(RT_SUCCESS(rc) && ((GstPageWalk.fEffective & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, GstPageWalk.fEffective));
893	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GstPageWalk.GCPhys, GstPageWalk.fEffective));
894	}
895	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
896	uint64_t fPageShw = 0;
897	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
898	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
899	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GstPageWalk.GCPhys, fPageGst, pvFault));
900	# endif
901	# endif /* VBOX_STRICT */
902	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
903	return VINF_SUCCESS;
904	}
905	}
906	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
907	/*
908	* Check for Netware WP0+RO+US hack from above and undo it when user
909	* mode accesses the page again.
910	*/
911	else if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
912	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
913	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
914	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
915	&& CPUMGetGuestCPL(pVCpu) == 3
916	&& pVM->cCpus == 1
917	)
918	{
919	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
920	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
921	if (RT_SUCCESS(rc))
922	{
923	PGM_INVL_PG(pVCpu, pvFault);
924	pVCpu->pgm.s.cNetwareWp0Hacks--;
925	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsUnhack; });
926	return VINF_SUCCESS;
927	}
928	}
929	# endif /* PGM_WITH_PAGING */
930
931	/** @todo else: why are we here? */
932
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
934	/*
935	* Check for VMM page flags vs. Guest page flags consistency.
936	* Currently only for debug purposes.
937	*/
938	if (RT_SUCCESS(rc))
939	{
940	/* Get guest page flags. */
941	PGMPTWALK GstPageWalk;
942	int rc2 = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
943	if (RT_SUCCESS(rc2))
944	{
945	uint64_t fPageShw = 0;
946	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
947
948	#if 0
949	/*
950	* Compare page flags.
951	* Note: we have AVL, A, D bits desynced.
952	*/
953	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
954	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
955	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
956	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
957	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
958	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
959	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
960	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
961	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
962	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
963	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
964
965	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
966	01:01:15.625516 00:08:43.268051 Location :
967	e:\vbox\svn\trunk\srcPage flags mismatch!
968	pvFault=fffff801b0d7b000
969	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
970	GCPhys=0000000019b52000
971	fPageShw=0
972	fPageGst=77b0000000000121
973	rc=0
974	#endif
975
976	}
977	else
978	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
979	}
980	else
981	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
982	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
983	}
984
985
986	/*
987	* If we get here it is because something failed above, i.e. most like guru
988	* meditiation time.
989	*/
990	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
991	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pCtx->cs.Sel, pCtx->rip));
992	return rc;
993
994	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
995	NOREF(uErr); NOREF(pCtx); NOREF(pvFault);
996	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
997	return VERR_PGM_NOT_USED_IN_MODE;
998	# endif
999	}
1000
1001
1002	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT)
1003	/**
1004	* Deals with a nested-guest \#PF fault for a guest-physical page with a handler.
1005	*
1006	* @returns Strict VBox status code.
1007	* @param pVCpu The cross context virtual CPU structure.
1008	* @param uErr The error code.
1009	* @param pCtx Pointer to the register context for the CPU.
1010	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1011	* @param pPage The guest page at @a GCPhysNestedFault.
1012	* @param GCPhysFault The guest-physical address of the fault.
1013	* @param pGstWalkAll The guest page walk result.
1014	* @param pfLockTaken Where to store whether the PGM is still held when
1015	* this function completes.
1016	*
1017	* @note The caller has taken the PGM lock.
1018	*/
1019	static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
1020	RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage,
1021	RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll,
1022	bool *pfLockTaken)
1023	{
1024	# if PGM_GST_TYPE == PGM_TYPE_PROT \
1025	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1026
1027	/** @todo Assert uErr isn't X86_TRAP_PF_RSVD and remove release checks. */
1028	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysFault);
1029	AssertMsgReturn(PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage), ("%RGp %RGp uErr=%u\n", GCPhysNestedFault, GCPhysFault, uErr),
1030	VERR_PGM_HANDLER_IPE_1);
1031
1032	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1033	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1034	RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1035
1036	/*
1037	* Physical page access handler.
1038	*/
1039	PPGMPHYSHANDLER pCur;
1040	VBOXSTRICTRC rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysPage, &pCur);
1041	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
1042
1043	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
1044	Assert(pCurType);
1045
1046	/*
1047	* If the region is write protected and we got a page not present fault, then sync
1048	* the pages. If the fault was caused by a read, then restart the instruction.
1049	* In case of write access continue to the GC write handler.
1050	*/
1051	if ( !(uErr & X86_TRAP_PF_P)
1052	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1053	{
1054	Log7Func(("Syncing Monitored: GCPhysNestedPage=%RGp GCPhysPage=%RGp uErr=%#x\n", GCPhysNestedPage, GCPhysPage, uErr));
1055	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1056	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1057	if ( RT_FAILURE(rcStrict)
1058	\|\| !(uErr & X86_TRAP_PF_RW))
1059	{
1060	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1061	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1062	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1063	return rcStrict;
1064	}
1065	}
1066	else if ( !(uErr & X86_TRAP_PF_RSVD)
1067	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE)
1068	{
1069	/*
1070	* If the access was NOT through an EPT misconfig (i.e. RSVD), sync the page.
1071	* This can happen for the VMX APIC-access page.
1072	*/
1073	Log7Func(("Syncing MMIO: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1074	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1075	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1076	if (RT_FAILURE(rcStrict))
1077	{
1078	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1079	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1080	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1081	return rcStrict;
1082	}
1083	}
1084
1085	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
1086	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
1087	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
1088	GCPhysNestedFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
1089	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1090	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
1091	else
1092	{
1093	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
1094	if (uErr & X86_TRAP_PF_RSVD)
1095	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
1096	}
1097
1098	if (pCurType->pfnPfHandler)
1099	{
1100	STAM_PROFILE_START(&pCur->Stat, h);
1101	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
1102	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
1103
1104	if (pCurType->fKeepPgmLock)
1105	{
1106	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1107	STAM_PROFILE_STOP(&pCur->Stat, h);
1108	}
1109	else
1110	{
1111	PGM_UNLOCK(pVM);
1112	*pfLockTaken = false;
1113	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1114	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
1115	}
1116	}
1117	else
1118	{
1119	AssertMsgFailed(("What's going on here!? Fault falls outside handler range!?\n"));
1120	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
1121	}
1122
1123	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
1124	return rcStrict;
1125
1126	# else
1127	RT_NOREF8(pVCpu, uErr, pCtx, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
1128	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1129	return VERR_PGM_NOT_USED_IN_MODE;
1130	# endif
1131	}
1132	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1133
1134
1135	/**
1136	* Nested \#PF handler for nested-guest hardware-assisted execution using nested
1137	* paging.
1138	*
1139	* @returns VBox status code (appropriate for trap handling and GC return).
1140	* @param pVCpu The cross context virtual CPU structure.
1141	* @param uErr The fault error (X86_TRAP_PF_*).
1142	* @param pCtx Pointer to the register context for the CPU.
1143	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1144	* @param fIsLinearAddrValid Whether translation of a nested-guest linear address
1145	* caused this fault. If @c false, GCPtrNestedFault
1146	* must be 0.
1147	* @param GCPtrNestedFault The nested-guest linear address of this fault.
1148	* @param pWalk The guest page table walk result.
1149	* @param pfLockTaken Where to store whether the PGM lock is still held
1150	* when this function completes.
1151	*/
1152	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1153	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken)
1154	{
1155	*pfLockTaken = false;
1156	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) \
1157	&& PGM_GST_TYPE == PGM_TYPE_PROT \
1158	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1159
1160	Assert(CPUMIsGuestVmxEptPagingEnabled(pVCpu));
1161	Assert(PGM_A20_IS_ENABLED(pVCpu));
1162
1163	/* We don't support mode-based execute control for EPT yet. */
1164	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
1165	Assert(!(uErr & X86_TRAP_PF_US));
1166
1167	/* Take the big lock now. */
1168	*pfLockTaken = true;
1169	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1170	PGM_LOCK_VOID(pVM);
1171
1172	/*
1173	* Walk the guest EPT tables and check if it's an EPT violation or misconfiguration.
1174	*/
1175	if (fIsLinearAddrValid)
1176	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x GCPtrNestedFault=%RGv\n",
1177	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));
1178	else
1179	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x\n",
1180	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr));
1181	PGMPTWALKGST GstWalkAll;
1182	int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll);
1183	if (RT_FAILURE(rc))
1184	return rc;
1185
1186	Assert(GstWalkAll.enmType == PGMPTWALKGSTTYPE_EPT);
1187	Assert(pWalk->fSucceeded);
1188	Assert(pWalk->fEffective & (PGM_PTATTRS_EPT_R_MASK \| PGM_PTATTRS_EPT_W_MASK \| PGM_PTATTRS_EPT_X_SUPER_MASK));
1189	Assert(pWalk->fIsSlat);
1190
1191	# ifdef DEBUG_ramshankar
1192	/* Paranoia. */
1193	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_R_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_R_MASK));
1194	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_W_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_W_MASK));
1195	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_NX_MASK) == !RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_X_SUPER_MASK));
1196	# endif
1197
1198	Log7Func(("SLAT: GCPhysNestedFault=%RGp -> GCPhys=%#RGp\n", GCPhysNestedFault, pWalk->GCPhys));
1199
1200	/*
1201	* Check page-access permissions.
1202	*/
1203	if ( ((uErr & X86_TRAP_PF_RW) && !(pWalk->fEffective & PGM_PTATTRS_W_MASK))
1204	\|\| ((uErr & X86_TRAP_PF_ID) && (pWalk->fEffective & PGM_PTATTRS_NX_MASK)))
1205	{
1206	Log7Func(("Permission failed! GCPtrNested=%RGv GCPhysNested=%RGp uErr=%#x fEffective=%#RX64\n", GCPtrNestedFault,
1207	GCPhysNestedFault, uErr, pWalk->fEffective));
1208	pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
1209	return VERR_ACCESS_DENIED;
1210	}
1211
1212	PGM_A20_ASSERT_MASKED(pVCpu, pWalk->GCPhys);
1213	RTGCPHYS const GCPhysPage = pWalk->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1214	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1215
1216	/*
1217	* If we were called via an EPT misconfig, it should've already resulted in a nested-guest VM-exit.
1218	*/
1219	AssertMsgReturn(!(uErr & X86_TRAP_PF_RSVD),
1220	("Unexpected EPT misconfig VM-exit. GCPhysPage=%RGp GCPhysNestedPage=%RGp\n", GCPhysPage, GCPhysNestedPage),
1221	VERR_PGM_MAPPING_IPE);
1222
1223	/*
1224	* Fetch and sync the nested-guest EPT page directory pointer.
1225	*/
1226	PEPTPD pEptPd;
1227	rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL /ppPdpt/, &pEptPd, &GstWalkAll);
1228	AssertRCReturn(rc, rc);
1229	Assert(pEptPd);
1230
1231	/*
1232	* A common case is the not-present error caused by lazy page table syncing.
1233	*
1234	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
1235	* here so we can safely assume that the shadow PT is present when calling
1236	* NestedSyncPage later.
1237	*
1238	* NOTE: It's possible we will be syncing the VMX APIC-access page here.
1239	* In that case, we would sync the page but will NOT go ahead with emulating
1240	* the APIC-access VM-exit through IEM. However, once the page is mapped in
1241	* the shadow tables, subsequent APIC-access VM-exits for the nested-guest
1242	* will be triggered by hardware. Maybe calling the IEM #PF handler can be
1243	* considered as an optimization later.
1244	*/
1245	unsigned const iPde = (GCPhysNestedPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1246	if ( !(uErr & X86_TRAP_PF_P)
1247	&& !(pEptPd->a[iPde].u & EPT_PRESENT_MASK))
1248	{
1249	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
1250	Log7Func(("NestedSyncPT: Lazy. GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1251	rc = PGM_BTH_NAME(NestedSyncPT)(pVCpu, GCPhysNestedPage, GCPhysPage, &GstWalkAll);
1252	if (RT_SUCCESS(rc))
1253	return rc;
1254	AssertMsgFailedReturn(("NestedSyncPT: %RGv failed! rc=%Rrc\n", GCPhysNestedPage, rc), VERR_PGM_MAPPING_IPE);
1255	}
1256
1257	/*
1258	* Check if this fault address is flagged for special treatment.
1259	* This handles faults on an MMIO or write-monitored page.
1260	*
1261	* If this happens to be the VMX APIC-access page, we don't treat is as MMIO
1262	* but rather sync it further below (as a regular guest page) which lets
1263	* hardware-assisted execution trigger the APIC-access VM-exits of the
1264	* nested-guest directly.
1265	*/
1266	PPGMPAGE pPage;
1267	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1268	if (RT_FAILURE(rc))
1269	{
1270	/*
1271	* We failed to get the physical page which means it's a reserved/invalid
1272	* page address (not MMIO even). This can typically be observed with
1273	* Microsoft Hyper-V enabled Windows guests. We must fall back to emulating
1274	* the instruction, see @bugref{10318#c7}.
1275	*/
1276	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
1277	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
1278	return VINF_EM_RAW_EMULATE_INSTR;
1279	}
1280	/* Check if this is an MMIO page and NOT the VMX APIC-access page. */
1281	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1282	{
1283	Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage));
1284	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, GCPhysNestedFault,
1285	pPage, pWalk->GCPhys, &GstWalkAll,
1286	pfLockTaken));
1287	}
1288
1289	/*
1290	* We are here only if page is present in nested-guest page tables but the
1291	* trap is not handled by our handlers. Check for page out-of-sync situation.
1292	*/
1293	if (!(uErr & X86_TRAP_PF_P))
1294	{
1295	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
1296	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1297	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
1298
1299	Log7Func(("SyncPage: Not-Present: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedFault, GCPhysPage));
1300	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, PGM_SYNC_NR_PAGES, uErr, &GstWalkAll);
1301	if (RT_SUCCESS(rc))
1302	{
1303	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
1304	return VINF_SUCCESS;
1305	}
1306	}
1307	else if (uErr & X86_TRAP_PF_RW)
1308	{
1309	/*
1310	* Write protected pages are made writable when the guest makes the
1311	* first write to it. This happens for pages that are shared, write
1312	* monitored or not yet allocated.
1313	*
1314	* We may also end up here when CR0.WP=0 in the guest.
1315	*
1316	* Also, a side effect of not flushing global PDEs are out of sync
1317	* pages due to physical monitored regions, that are no longer valid.
1318	* Assume for now it only applies to the read/write flag.
1319	*/
1320	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1321	{
1322	/* This is a read-only page. */
1323	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhysPage));
1324	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
1325	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO
1326	&& (GCPhysNestedFault & X86_PAGE_OFFSET_MASK) == 0
1327	&& pgmHandlePageZeroingCode(pVCpu, pCtx))
1328	{
1329	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2PageZeroing; });
1330	return VINF_SUCCESS;
1331	}
1332	#endif
1333	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
1334
1335	Log7Func(("Calling pgmPhysPageMakeWritable for GCPhysPage=%RGp\n", GCPhysPage));
1336	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1337	if (rc != VINF_SUCCESS)
1338	{
1339	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1340	return rc;
1341	}
1342	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
1343	return VINF_EM_NO_MEMORY;
1344	}
1345
1346	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1347	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1348
1349	/*
1350	* Sync the write-protected page.
1351	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1352	* page is not present, which is not true in this case.
1353	*/
1354	Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n",
1355	pCtx->cs.Sel, pCtx->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
1356	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll);
1357	if (RT_SUCCESS(rc))
1358	{
1359	HMInvalidatePhysPage(pVM, GCPhysPage);
1360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
1361	return VINF_SUCCESS;
1362	}
1363	}
1364
1365	/*
1366	* If we get here it is because something failed above => guru meditation time?
1367	*/
1368	LogRelMaxFunc(32, ("rc=%Rrc GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n",
1369	rc, GCPhysNestedFault, GCPhysPage, (uint32_t)uErr, pCtx->cs.Sel, pCtx->rip));
1370	return VERR_PGM_MAPPING_IPE;
1371
1372	# else /* !VBOX_WITH_NESTED_HWVIRT_VMX_EPT \|\| PGM_GST_TYPE != PGM_TYPE_PROT \|\| PGM_SHW_TYPE != PGM_TYPE_EPT */
1373	RT_NOREF7(pVCpu, uErr, pCtx, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
1374	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1375	return VERR_PGM_NOT_USED_IN_MODE;
1376	# endif
1377	}
1378
1379	#endif /* !IN_RING3 */
1380
1381
1382	/**
1383	* Emulation of the invlpg instruction.
1384	*
1385	*
1386	* @returns VBox status code.
1387	*
1388	* @param pVCpu The cross context virtual CPU structure.
1389	* @param GCPtrPage Page to invalidate.
1390	*
1391	* @remark ASSUMES that the guest is updating before invalidating. This order
1392	* isn't required by the CPU, so this is speculative and could cause
1393	* trouble.
1394	* @remark No TLB shootdown is done on any other VCPU as we assume that
1395	* invlpg emulation is the only reason for calling this function.
1396	* (The guest has to shoot down TLB entries on other CPUs itself)
1397	* Currently true, but keep in mind!
1398	*
1399	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1400	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1401	*/
1402	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1403	{
1404	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1405	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1406	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1407	int rc;
1408	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1409	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1410
1411	PGM_LOCK_ASSERT_OWNER(pVM);
1412
1413	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1414
1415	/*
1416	* Get the shadow PD entry and skip out if this PD isn't present.
1417	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1418	*/
1419	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1420	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1421	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1422
1423	/* Fetch the pgm pool shadow descriptor. */
1424	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1425	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1426	if (!pShwPde)
1427	{
1428	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1429	return VINF_SUCCESS;
1430	}
1431	# else
1432	Assert(pShwPde);
1433	# endif
1434
1435	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1436	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1437	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1438
1439	/* If the shadow PDPE isn't present, then skip the invalidate. */
1440	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1441	if (!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1442	# else
1443	if (!(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1444	# endif
1445	{
1446	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1447	PGM_INVL_PG(pVCpu, GCPtrPage);
1448	return VINF_SUCCESS;
1449	}
1450
1451	/* Fetch the pgm pool shadow descriptor. */
1452	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1453	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1454
1455	PX86PDPAE pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1456	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1457	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1458
1459	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1460	/* PML4 */
1461	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1462	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1463	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1464	PX86PDPAE pPDDst;
1465	PX86PDPT pPdptDst;
1466	PX86PML4E pPml4eDst;
1467	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1468	if (rc != VINF_SUCCESS)
1469	{
1470	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1471	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1472	PGM_INVL_PG(pVCpu, GCPtrPage);
1473	return VINF_SUCCESS;
1474	}
1475	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1476	Assert(pPDDst);
1477	Assert(pPdptDst->a[iPdpt].u & X86_PDPE_P);
1478
1479	/* Fetch the pgm pool shadow descriptor. */
1480	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1481	Assert(pShwPde);
1482
1483	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1484
1485	const SHWPDE PdeDst = *pPdeDst;
1486	if (!(PdeDst.u & X86_PDE_P))
1487	{
1488	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1489	PGM_INVL_PG(pVCpu, GCPtrPage);
1490	return VINF_SUCCESS;
1491	}
1492
1493	/*
1494	* Get the guest PD entry and calc big page.
1495	*/
1496	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1497	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1498	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1499	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1500	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1501	unsigned iPDSrc = 0;
1502	# if PGM_GST_TYPE == PGM_TYPE_PAE
1503	X86PDPE PdpeSrcIgn;
1504	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1505	# else /* AMD64 */
1506	PX86PML4E pPml4eSrcIgn;
1507	X86PDPE PdpeSrcIgn;
1508	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1509	# endif
1510	GSTPDE PdeSrc;
1511
1512	if (pPDSrc)
1513	PdeSrc = pPDSrc->a[iPDSrc];
1514	else
1515	PdeSrc.u = 0;
1516	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1517	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1518	const bool fIsBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1519	if (fWasBigPage != fIsBigPage)
1520	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1521
1522	# ifdef IN_RING3
1523	/*
1524	* If a CR3 Sync is pending we may ignore the invalidate page operation
1525	* depending on the kind of sync and if it's a global page or not.
1526	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1527	*/
1528	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1529	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1530	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1531	&& fIsBigPage
1532	&& (PdeSrc.u & X86_PDE4M_G)
1533	)
1534	)
1535	# else
1536	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1537	# endif
1538	{
1539	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1540	return VINF_SUCCESS;
1541	}
1542	# endif /* IN_RING3 */
1543
1544	/*
1545	* Deal with the Guest PDE.
1546	*/
1547	rc = VINF_SUCCESS;
1548	if (PdeSrc.u & X86_PDE_P)
1549	{
1550	Assert( (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1551	&& ((PdeSrc.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW) \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1552	if (!fIsBigPage)
1553	{
1554	/*
1555	* 4KB - page.
1556	*/
1557	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1558	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1559
1560	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1561	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1562	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
1563	# endif
1564	if (pShwPage->GCPhys == GCPhys)
1565	{
1566	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1567	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1568
1569	PGSTPT pPTSrc;
1570	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1571	if (RT_SUCCESS(rc))
1572	{
1573	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1574	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1575	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1576	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1577	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1578	GCPtrPage, PteSrc.u & X86_PTE_P,
1579	(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1580	(PteSrc.u & PdeSrc.u & X86_PTE_US),
1581	(uint64_t)PteSrc.u,
1582	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1583	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1584	}
1585	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1586	PGM_INVL_PG(pVCpu, GCPtrPage);
1587	}
1588	else
1589	{
1590	/*
1591	* The page table address changed.
1592	*/
1593	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1594	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1595	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1596	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1597	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1598	PGM_INVL_VCPU_TLBS(pVCpu);
1599	}
1600	}
1601	else
1602	{
1603	/*
1604	* 2/4MB - page.
1605	*/
1606	/* Before freeing the page, check if anything really changed. */
1607	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1608	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1609	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1610	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1611	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1612	# endif
1613	if ( pShwPage->GCPhys == GCPhys
1614	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1615	{
1616	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1617	/** @todo This test is wrong as it cannot check the G bit!
1618	* FIXME */
1619	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1620	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1621	&& ( (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1622	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1623	{
1624	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1625	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1626	return VINF_SUCCESS;
1627	}
1628	}
1629
1630	/*
1631	* Ok, the page table is present and it's been changed in the guest.
1632	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1633	* We could do this for some flushes in GC too, but we need an algorithm for
1634	* deciding which 4MB pages containing code likely to be executed very soon.
1635	*/
1636	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1637	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1638	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1639	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1640	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1641	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1642	}
1643	}
1644	else
1645	{
1646	/*
1647	* Page directory is not present, mark shadow PDE not present.
1648	*/
1649	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1650	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1651	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1652	PGM_INVL_PG(pVCpu, GCPtrPage);
1653	}
1654	return rc;
1655
1656	#else /* guest real and protected mode, nested + ept, none. */
1657	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1658	NOREF(pVCpu); NOREF(GCPtrPage);
1659	return VINF_SUCCESS;
1660	#endif
1661	}
1662
1663	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1664
1665	/**
1666	* Update the tracking of shadowed pages.
1667	*
1668	* @param pVCpu The cross context virtual CPU structure.
1669	* @param pShwPage The shadow page.
1670	* @param HCPhys The physical page we is being dereferenced.
1671	* @param iPte Shadow PTE index
1672	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1673	*/
1674	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1675	RTGCPHYS GCPhysPage)
1676	{
1677	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1678
1679	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1680	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1681	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1682
1683	/* Use the hint we retrieved from the cached guest PT. */
1684	if (pShwPage->fDirty)
1685	{
1686	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1687
1688	Assert(pShwPage->cPresent);
1689	Assert(pPool->cPresent);
1690	pShwPage->cPresent--;
1691	pPool->cPresent--;
1692
1693	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1694	AssertRelease(pPhysPage);
1695	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1696	return;
1697	}
1698	# else
1699	NOREF(GCPhysPage);
1700	# endif
1701
1702	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1703	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1704	* 2. write protect all shadowed pages. I.e. implement caching.
1705	*
1706	* 2023-08-24 bird: If we allow the ZeroPg to enter the shadow page tables,
1707	* this becomes a common occurence and we screw up. A better to the above would
1708	* be to have a parallel table that records the guest physical addresses of the
1709	* pages mapped by the shadow page table... For nested page tables,
1710	* we can easily correleate a table entry to a page entry, so it won't be
1711	* needed for those.
1712	*/
1713	# if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1714	/*
1715	* For non-paged guest tables, EPT and nested tables we can figure out the
1716	* physical page corresponding to the entry and dereference it.
1717	* (This ASSUMES that shadow PTs won't be used ever be used out of place.)
1718	*/
1719	if ( pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_PHYS
1720	\|\| pShwPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PHYS
1721	\|\| pShwPage->enmKind == PGMPOOLKIND_32BIT_PT_FOR_PHYS)
1722	{
1723	RTGCPHYS GCPhysNestedEntry = pShwPage->GCPhys + ((uint32_t)iPte << X86_PAGE_SHIFT);
1724	if (!pShwPage->fA20Enabled)
1725	GCPhysNestedEntry &= ~(uint64_t)RT_BIT_64(20);
1726	PPGMPAGE const pPhysPage = pgmPhysGetPage(pVM, GCPhysNestedEntry);
1727	AssertRelease(pPhysPage);
1728	pgmTrackDerefGCPhys(pVM->pgm.s.CTX_SUFF(pPool), pShwPage, pPhysPage, iPte);
1729	}
1730	else
1731	AssertMsgFailed(("enmKind=%d GCPhys=%RGp\n", pShwPage->enmKind, pShwPage->GCPhys));
1732	# endif
1733
1734	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1735
1736	/*
1737	* Find the guest address.
1738	*/
1739	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatTrackDeref, a);
1740	LogFlow(("SyncPageWorkerTrackDeref(%d,%d): Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n",
1741	PGM_SHW_TYPE, PGM_GST_TYPE, HCPhys, pShwPage->idx));
1742	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1743	pRam;
1744	pRam = pRam->CTX_SUFF(pNext))
1745	{
1746	unsigned iPage = pRam->cb >> GUEST_PAGE_SHIFT;
1747	while (iPage-- > 0)
1748	{
1749	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1750	{
1751	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1752
1753	Assert(pShwPage->cPresent);
1754	Assert(pPool->cPresent);
1755	pShwPage->cPresent--;
1756	pPool->cPresent--;
1757
1758	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1759	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatTrackDeref, a);
1760	return;
1761	}
1762	}
1763	}
1764
1765	for (;;)
1766	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1767	}
1768
1769
1770	/**
1771	* Update the tracking of shadowed pages.
1772	*
1773	* @param pVCpu The cross context virtual CPU structure.
1774	* @param pShwPage The shadow page.
1775	* @param u16 The top 16-bit of the pPage->HCPhys.
1776	* @param pPage Pointer to the guest page. this will be modified.
1777	* @param iPTDst The index into the shadow table.
1778	*/
1779	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16,
1780	PPGMPAGE pPage, const unsigned iPTDst)
1781	{
1782	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1783
1784	/*
1785	* Just deal with the simple first time here.
1786	*/
1787	if (!u16)
1788	{
1789	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatTrackVirgin);
1790	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1791	/* Save the page table index. */
1792	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1793	}
1794	else
1795	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1796
1797	/* write back */
1798	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x pPage=%p\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst, pPage));
1799	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1800
1801	/* update statistics. */
1802	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1803	pShwPage->cPresent++;
1804	if (pShwPage->iFirstPresent > iPTDst)
1805	pShwPage->iFirstPresent = iPTDst;
1806	}
1807
1808
1809	/**
1810	* Modifies a shadow PTE to account for access handlers.
1811	*
1812	* @param pVM The cross context VM structure.
1813	* @param pVCpu The cross context virtual CPU structure.
1814	* @param pPage The page in question.
1815	* @param GCPhysPage The guest-physical address of the page.
1816	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1817	* A (accessed) bit so it can be emulated correctly.
1818	* @param pPteDst The shadow PTE (output). This is temporary storage and
1819	* does not need to be set atomically.
1820	*/
1821	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PVMCPUCC pVCpu, PCPGMPAGE pPage, RTGCPHYS GCPhysPage, uint64_t fPteSrc,
1822	PSHWPTE pPteDst)
1823	{
1824	RT_NOREF_PV(pVM); RT_NOREF_PV(fPteSrc); RT_NOREF_PV(pVCpu); RT_NOREF_PV(GCPhysPage);
1825
1826	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1827	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1828	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1829	{
1830	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1831	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1832	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) \| EPT_E_READ \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1833	# else
1834	if (fPteSrc & X86_PTE_A)
1835	{
1836	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1837	SHW_PTE_SET_RO(*pPteDst);
1838	}
1839	else
1840	SHW_PTE_SET(*pPteDst, 0);
1841	# endif
1842	}
1843	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1844	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1845	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1846	&& ( BTH_IS_NP_ACTIVE(pVM)
1847	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1848	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1849	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1850	# endif
1851	)
1852	{
1853	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1854	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1855	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1856	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
1857	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1858	\| EPT_E_WRITE
1859	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1860	\| EPT_E_MEMTYPE_INVALID_3;
1861	# else
1862	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1863	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1864	# endif
1865	}
1866	# endif
1867	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1868	else
1869	{
1870	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1871	SHW_PTE_SET(*pPteDst, 0);
1872	}
1873	/** @todo count these kinds of entries. */
1874	}
1875
1876
1877	/**
1878	* Creates a 4K shadow page for a guest page.
1879	*
1880	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1881	* physical address. The PdeSrc argument only the flags are used. No page
1882	* structured will be mapped in this function.
1883	*
1884	* @param pVCpu The cross context virtual CPU structure.
1885	* @param pPteDst Destination page table entry.
1886	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1887	* Can safely assume that only the flags are being used.
1888	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1889	* @param pShwPage Pointer to the shadow page.
1890	* @param iPTDst The index into the shadow table.
1891	*
1892	* @remark Not used for 2/4MB pages!
1893	*/
1894	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1895	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1896	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1897	# else
1898	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1899	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1900	# endif
1901	{
1902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1903	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1904
1905	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1906	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1907	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1908
1909	if (pShwPage->fDirty)
1910	{
1911	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1912	PGSTPT pGstPT;
1913
1914	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1915	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1916	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1917	pGstPT->a[iPTDst].u = PteSrc.u;
1918	}
1919	# else
1920	Assert(!pShwPage->fDirty);
1921	# endif
1922
1923	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1924	if ( (PteSrc.u & X86_PTE_P)
1925	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1926	# endif
1927	{
1928	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1929	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1930	# endif
1931	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1932
1933	/*
1934	* Find the ram range.
1935	*/
1936	PPGMPAGE pPage;
1937	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1938	if (RT_SUCCESS(rc))
1939	{
1940	/* Ignore ballooned pages.
1941	Don't return errors or use a fatal assert here as part of a
1942	shadow sync range might included ballooned pages. */
1943	if (PGM_PAGE_IS_BALLOONED(pPage))
1944	{
1945	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1946	return;
1947	}
1948
1949	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1950	/* Make the page writable if necessary. */
1951	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1952	&& ( PGM_PAGE_IS_ZERO(pPage)
1953	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1954	\|\| ( (PteSrc.u & X86_PTE_RW)
1955	# else
1956	\|\| ( 1
1957	# endif
1958	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1959	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1960	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1961	# endif
1962	# ifdef VBOX_WITH_PAGE_SHARING
1963	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1964	# endif
1965	)
1966	)
1967	)
1968	{
1969	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1970	AssertRC(rc);
1971	}
1972	# endif
1973
1974	/*
1975	* Make page table entry.
1976	*/
1977	SHWPTE PteDst;
1978	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1979	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1980	# else
1981	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1982	# endif
1983	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1984	{
1985	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1986	/*
1987	* If the page or page directory entry is not marked accessed,
1988	* we mark the page not present.
1989	*/
1990	if (!(PteSrc.u & X86_PTE_A) \|\| !(PdeSrc.u & X86_PDE_A))
1991	{
1992	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1993	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,AccessedPage));
1994	SHW_PTE_SET(PteDst, 0);
1995	}
1996	/*
1997	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1998	* when the page is modified.
1999	*/
2000	else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
2001	{
2002	AssertCompile(X86_PTE_RW == X86_PDE_RW);
2003	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPage));
2004	SHW_PTE_SET(PteDst,
2005	fGstShwPteFlags
2006	\| PGM_PAGE_GET_HCPHYS(pPage)
2007	\| PGM_PTFLAGS_TRACK_DIRTY);
2008	SHW_PTE_SET_RO(PteDst);
2009	}
2010	else
2011	# endif
2012	{
2013	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageSkipped));
2014	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2015	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
2016	\| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2017	# else
2018	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
2019	# endif
2020	}
2021
2022	/*
2023	* Make sure only allocated pages are mapped writable.
2024	*/
2025	if ( SHW_PTE_IS_P_RW(PteDst)
2026	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2027	{
2028	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2029	/* Still applies to shared pages. */
2030	Assert(!PGM_PAGE_IS_ZERO(pPage));
2031	# endif
2032	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
2033	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
2034	}
2035	}
2036	else
2037	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhysPage, fGstShwPteFlags, &PteDst);
2038
2039	/*
2040	* Keep user track up to date.
2041	*/
2042	if (SHW_PTE_IS_P(PteDst))
2043	{
2044	if (!SHW_PTE_IS_P(*pPteDst))
2045	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2046	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
2047	{
2048	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
2049	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2050	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2051	}
2052	}
2053	else if (SHW_PTE_IS_P(*pPteDst))
2054	{
2055	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2056	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2057	}
2058
2059	/*
2060	* Update statistics and commit the entry.
2061	*/
2062	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2063	if (!(PteSrc.u & X86_PTE_G))
2064	pShwPage->fSeenNonGlobal = true;
2065	# endif
2066	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2067	return;
2068	}
2069
2070	/** @todo count these three different kinds. */
2071	Log2(("SyncPageWorker: invalid address in Pte\n"));
2072	}
2073	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2074	else if (!(PteSrc.u & X86_PTE_P))
2075	Log2(("SyncPageWorker: page not present in Pte\n"));
2076	else
2077	Log2(("SyncPageWorker: invalid Pte\n"));
2078	# endif
2079
2080	/*
2081	* The page is not present or the PTE is bad. Replace the shadow PTE by
2082	* an empty entry, making sure to keep the user tracking up to date.
2083	*/
2084	if (SHW_PTE_IS_P(*pPteDst))
2085	{
2086	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2087	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2088	}
2089	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
2090	}
2091
2092
2093	/**
2094	* Syncs a guest OS page.
2095	*
2096	* There are no conflicts at this point, neither is there any need for
2097	* page table allocations.
2098	*
2099	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
2100	* When called in AMD64 guest mode, the guest PML4E shall be valid.
2101	*
2102	* @returns VBox status code.
2103	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
2104	* @param pVCpu The cross context virtual CPU structure.
2105	* @param PdeSrc Page directory entry of the guest.
2106	* @param GCPtrPage Guest context page address.
2107	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2108	* @param uErr Fault error (X86_TRAP_PF_*).
2109	*/
2110	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
2111	{
2112	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2113	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2114	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
2115	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
2116
2117	PGM_LOCK_ASSERT_OWNER(pVM);
2118
2119	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2120	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2121	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2122	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
2123
2124	/*
2125	* Assert preconditions.
2126	*/
2127	Assert(PdeSrc.u & X86_PDE_P);
2128	Assert(cPages);
2129	# if 0 /* rarely useful; leave for debugging. */
2130	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
2131	# endif
2132
2133	/*
2134	* Get the shadow PDE, find the shadow page table in the pool.
2135	*/
2136	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2137	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2138	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2139
2140	/* Fetch the pgm pool shadow descriptor. */
2141	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2142	Assert(pShwPde);
2143
2144	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2145	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2146	PPGMPOOLPAGE pShwPde = NULL;
2147	PX86PDPAE pPDDst;
2148
2149	/* Fetch the pgm pool shadow descriptor. */
2150	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2151	AssertRCSuccessReturn(rc2, rc2);
2152	Assert(pShwPde);
2153
2154	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2155	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2156
2157	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2158	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2159	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2160	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2161	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2162
2163	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2164	AssertRCSuccessReturn(rc2, rc2);
2165	Assert(pPDDst && pPdptDst);
2166	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2167	# endif
2168	SHWPDE PdeDst = *pPdeDst;
2169
2170	/*
2171	* - In the guest SMP case we could have blocked while another VCPU reused
2172	* this page table.
2173	* - With W7-64 we may also take this path when the A bit is cleared on
2174	* higher level tables (PDPE/PML4E). The guest does not invalidate the
2175	* relevant TLB entries. If we're write monitoring any page mapped by
2176	* the modified entry, we may end up here with a "stale" TLB entry.
2177	*/
2178	if (!(PdeDst.u & X86_PDE_P))
2179	{
2180	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2181	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
2182	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2183	if (uErr & X86_TRAP_PF_P)
2184	PGM_INVL_PG(pVCpu, GCPtrPage);
2185	return VINF_SUCCESS; /* force the instruction to be executed again. */
2186	}
2187
2188	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2189	Assert(pShwPage);
2190
2191	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2192	/* Fetch the pgm pool shadow descriptor. */
2193	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2194	Assert(pShwPde);
2195	# endif
2196
2197	/*
2198	* Check that the page is present and that the shadow PDE isn't out of sync.
2199	*/
2200	const bool fBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
2201	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2202	RTGCPHYS GCPhys;
2203	if (!fBigPage)
2204	{
2205	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2206	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2207	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2208	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
2209	# endif
2210	}
2211	else
2212	{
2213	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2214	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2215	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2216	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2217	# endif
2218	}
2219	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2220	if ( fPdeValid
2221	&& pShwPage->GCPhys == GCPhys
2222	&& (PdeSrc.u & X86_PDE_P)
2223	&& (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
2224	&& ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW))
2225	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2226	&& ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) \|\| !GST_IS_NX_ACTIVE(pVCpu))
2227	# endif
2228	)
2229	{
2230	/*
2231	* Check that the PDE is marked accessed already.
2232	* Since we set the accessed bit before getting here on a #PF, this
2233	* check is only meant for dealing with non-#PF'ing paths.
2234	*/
2235	if (PdeSrc.u & X86_PDE_A)
2236	{
2237	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2238	if (!fBigPage)
2239	{
2240	/*
2241	* 4KB Page - Map the guest page table.
2242	*/
2243	PGSTPT pPTSrc;
2244	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2245	if (RT_SUCCESS(rc))
2246	{
2247	# ifdef PGM_SYNC_N_PAGES
2248	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2249	if ( cPages > 1
2250	&& !(uErr & X86_TRAP_PF_P)
2251	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2252	{
2253	/*
2254	* This code path is currently only taken when the caller is PGMTrap0eHandler
2255	* for non-present pages!
2256	*
2257	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2258	* deal with locality.
2259	*/
2260	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2261	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2262	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2263	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2264	# else
2265	const unsigned offPTSrc = 0;
2266	# endif
2267	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2268	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2269	iPTDst = 0;
2270	else
2271	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2272
2273	for (; iPTDst < iPTDstEnd; iPTDst++)
2274	{
2275	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2276
2277	if ( (pPteSrc->u & X86_PTE_P)
2278	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2279	{
2280	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT))
2281	\| ((offPTSrc + iPTDst) << GUEST_PAGE_SHIFT);
2282	NOREF(GCPtrCurPage);
2283	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2284	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2285	GCPtrCurPage, pPteSrc->u & X86_PTE_P,
2286	!!(pPteSrc->u & PdeSrc.u & X86_PTE_RW),
2287	!!(pPteSrc->u & PdeSrc.u & X86_PTE_US),
2288	(uint64_t)pPteSrc->u,
2289	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2290	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2291	}
2292	}
2293	}
2294	else
2295	# endif /* PGM_SYNC_N_PAGES */
2296	{
2297	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2298	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2299	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2300	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2301	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2302	GCPtrPage, PteSrc.u & X86_PTE_P,
2303	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
2304	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
2305	(uint64_t)PteSrc.u,
2306	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2307	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2308	}
2309	}
2310	else /* MMIO or invalid page: emulated in #PF handler. */
2311	{
2312	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2313	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2314	}
2315	}
2316	else
2317	{
2318	/*
2319	* 4/2MB page - lazy syncing shadow 4K pages.
2320	* (There are many causes of getting here, it's no longer only CSAM.)
2321	*/
2322	/* Calculate the GC physical address of this 4KB shadow page. */
2323	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2324	/* Find ram range. */
2325	PPGMPAGE pPage;
2326	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2327	if (RT_SUCCESS(rc))
2328	{
2329	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2330
2331	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2332	/* Try to make the page writable if necessary. */
2333	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2334	&& ( PGM_PAGE_IS_ZERO(pPage)
2335	\|\| ( (PdeSrc.u & X86_PDE_RW)
2336	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2337	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2338	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2339	# endif
2340	# ifdef VBOX_WITH_PAGE_SHARING
2341	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2342	# endif
2343	)
2344	)
2345	)
2346	{
2347	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2348	AssertRC(rc);
2349	}
2350	# endif
2351
2352	/*
2353	* Make shadow PTE entry.
2354	*/
2355	SHWPTE PteDst;
2356	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2357	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2358	else
2359	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2360
2361	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2362	if ( SHW_PTE_IS_P(PteDst)
2363	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2364	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2365
2366	/* Make sure only allocated pages are mapped writable. */
2367	if ( SHW_PTE_IS_P_RW(PteDst)
2368	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2369	{
2370	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2371	/* Still applies to shared pages. */
2372	Assert(!PGM_PAGE_IS_ZERO(pPage));
2373	# endif
2374	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2375	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2376	}
2377
2378	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2379
2380	/*
2381	* If the page is not flagged as dirty and is writable, then make it read-only
2382	* at PD level, so we can set the dirty bit when the page is modified.
2383	*
2384	* ASSUMES that page access handlers are implemented on page table entry level.
2385	* Thus we will first catch the dirty access and set PDE.D and restart. If
2386	* there is an access handler, we'll trap again and let it work on the problem.
2387	*/
2388	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2389	* As for invlpg, it simply frees the whole shadow PT.
2390	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2391	if ((PdeSrc.u & (X86_PDE4M_D \| X86_PDE_RW)) == X86_PDE_RW)
2392	{
2393	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2394	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2395	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2396	}
2397	else
2398	{
2399	PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY \| X86_PDE_RW);
2400	PdeDst.u \|= PdeSrc.u & X86_PDE_RW;
2401	}
2402	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2403	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2404	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US),
2405	(uint64_t)PdeSrc.u, GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2406	}
2407	else
2408	{
2409	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2410	/** @todo must wipe the shadow page table entry in this
2411	* case. */
2412	}
2413	}
2414	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2415	return VINF_SUCCESS;
2416	}
2417
2418	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDNAs));
2419	}
2420	else if (fPdeValid)
2421	{
2422	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2423	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2424	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2425	}
2426	else
2427	{
2428	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2429	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2430	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2431	}
2432
2433	/*
2434	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2435	* Yea, I'm lazy.
2436	*/
2437	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2438	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
2439
2440	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2441	PGM_INVL_VCPU_TLBS(pVCpu);
2442	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2443
2444
2445	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2446	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2447	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2448	NOREF(PdeSrc);
2449
2450	# ifdef PGM_SYNC_N_PAGES
2451	/*
2452	* Get the shadow PDE, find the shadow page table in the pool.
2453	*/
2454	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2455	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2456
2457	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2458	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2459
2460	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2461	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2462	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2463	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2464	X86PDEPAE PdeDst;
2465	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2466
2467	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2468	AssertRCSuccessReturn(rc, rc);
2469	Assert(pPDDst && pPdptDst);
2470	PdeDst = pPDDst->a[iPDDst];
2471
2472	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2473	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2474	PEPTPD pPDDst;
2475	EPTPDE PdeDst;
2476
2477	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2478	if (rc != VINF_SUCCESS)
2479	{
2480	AssertRC(rc);
2481	return rc;
2482	}
2483	Assert(pPDDst);
2484	PdeDst = pPDDst->a[iPDDst];
2485	# endif
2486	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2487	if (!SHW_PDE_IS_P(PdeDst))
2488	{
2489	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2490	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2491	return VINF_SUCCESS; /* force the instruction to be executed again. */
2492	}
2493
2494	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2495	if (SHW_PDE_IS_BIG(PdeDst))
2496	{
2497	Assert(pVM->pgm.s.fNestedPaging);
2498	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2499	return VINF_SUCCESS;
2500	}
2501
2502	/* Mask away the page offset. */
2503	GCPtrPage &= ~((RTGCPTR)0xfff);
2504
2505	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2506	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2507
2508	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2509	if ( cPages > 1
2510	&& !(uErr & X86_TRAP_PF_P)
2511	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2512	{
2513	/*
2514	* This code path is currently only taken when the caller is PGMTrap0eHandler
2515	* for non-present pages!
2516	*
2517	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2518	* deal with locality.
2519	*/
2520	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2521	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2522	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2523	iPTDst = 0;
2524	else
2525	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2526	for (; iPTDst < iPTDstEnd; iPTDst++)
2527	{
2528	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2529	{
2530	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2531	\| (iPTDst << GUEST_PAGE_SHIFT));
2532
2533	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2534	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2535	GCPtrCurPage,
2536	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2537	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2538
2539	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2540	break;
2541	}
2542	else
2543	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n",
2544	(GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << GUEST_PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2545	}
2546	}
2547	else
2548	# endif /* PGM_SYNC_N_PAGES */
2549	{
2550	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2551	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2552	\| (iPTDst << GUEST_PAGE_SHIFT));
2553
2554	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2555
2556	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2557	GCPtrPage,
2558	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2559	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2560	}
2561	return VINF_SUCCESS;
2562
2563	# else
2564	NOREF(PdeSrc);
2565	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2566	return VERR_PGM_NOT_USED_IN_MODE;
2567	# endif
2568	}
2569
2570	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2571
2572	#if !defined(IN_RING3) && defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
2573
2574	/**
2575	* Sync a shadow page for a nested-guest page.
2576	*
2577	* @param pVCpu The cross context virtual CPU structure.
2578	* @param pPte The shadow page table entry.
2579	* @param GCPhysPage The guest-physical address of the page.
2580	* @param pShwPage The shadow page of the page table.
2581	* @param iPte The index of the page table entry.
2582	* @param pGstSlatPte The guest SLAT page table entry.
2583	*
2584	* @note Not to be used for 2/4MB pages!
2585	*/
2586	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
2587	unsigned iPte, SLATPTE GstSlatPte)
2588	{
2589	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2590	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2591	Assert(!pShwPage->fDirty);
2592	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
2593	AssertMsg(!(GstSlatPte.u & EPT_E_LEAF), ("Large page unexpected: %RX64\n", GstSlatPte.u));
2594	AssertMsg((GstSlatPte.u & EPT_PTE_PG_MASK) == GCPhysPage,
2595	("PTE address mismatch. GCPhysPage=%RGp Pte=%RX64\n", GCPhysPage, GstSlatPte.u & EPT_PTE_PG_MASK));
2596
2597	/*
2598	* Find the ram range.
2599	*/
2600	PPGMPAGE pPage;
2601	int rc = pgmPhysGetPageEx(pVCpu->CTX_SUFF(pVM), GCPhysPage, &pPage);
2602	if (RT_SUCCESS(rc))
2603	{ /* likely */ }
2604	else
2605	{
2606	/*
2607	* This is a RAM hole/invalid/reserved address (not MMIO).
2608	* Nested Microsoft Hyper-V maps addresses like 0xf0220000 as RW WB memory.
2609	* Shadow a not-present page similar to MMIO, see @bugref{10318#c7}.
2610	*/
2611	Assert(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
2612	if (SHW_PTE_IS_P(*pPte))
2613	{
2614	Log2(("NestedSyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2615	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2616	}
2617	Log7Func(("RAM hole/reserved %RGp -> ShwPte=0\n", GCPhysPage));
2618	SHW_PTE_ATOMIC_SET(*pPte, 0);
2619	return;
2620	}
2621
2622	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
2623
2624	/*
2625	* Make page table entry.
2626	*/
2627	SHWPTE Pte;
2628	uint64_t const fGstShwPteFlags = (GstSlatPte.u & pVCpu->pgm.s.fGstEptShadowedPteMask)
2629	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2630	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2631	{
2632	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2633	/* If it's the zero page or write to an unallocated page, allocate it to make it writable. */
2634	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2635	&& ( PGM_PAGE_IS_ZERO(pPage)
2636	\|\| ( (GstSlatPte.u & EPT_E_WRITE)
2637	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2638	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2639	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2640	# endif
2641	# ifdef VBOX_WITH_PAGE_SHARING
2642	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2643	# endif
2644	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_BALLOONED
2645	)
2646	)
2647	)
2648	{
2649	rc = pgmPhysPageMakeWritable(pVCpu->CTX_SUFF(pVM), pPage, GCPhysPage);
2650	AssertRC(rc);
2651	Log7Func(("made writable (%R[pgmpage]) at %RGp\n", pPage, GCPhysPage));
2652	}
2653	# endif
2654	/** @todo access bit. */
2655	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2656	Log7Func(("regular page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2657
2658	/* Make sure only allocated pages are mapped writable. */
2659	if ( (fGstShwPteFlags & EPT_E_WRITE)
2660	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2661	{
2662	Pte.u &= ~EPT_E_WRITE;
2663	Log7Func(("write-protecting page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2664	}
2665	}
2666	else if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2667	{
2668	/** @todo access bit. */
2669	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| (fGstShwPteFlags & ~EPT_E_WRITE);
2670	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2671	}
2672	else
2673	{
2674	/** @todo Do MMIO optimizations here too? */
2675	Log7Func(("mmio/all page (%R[pgmpage]) at %RGp -> 0\n", pPage, GCPhysPage));
2676	Pte.u = 0;
2677	}
2678
2679	/* Make sure only allocated pages are mapped writable. */
2680	Assert(!SHW_PTE_IS_P_RW(Pte) \|\| PGM_PAGE_IS_ALLOCATED(pPage));
2681
2682	/*
2683	* Keep user track up to date.
2684	*/
2685	if (SHW_PTE_IS_P(Pte))
2686	{
2687	if (!SHW_PTE_IS_P(*pPte))
2688	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2689	else if (SHW_PTE_GET_HCPHYS(*pPte) != SHW_PTE_GET_HCPHYS(Pte))
2690	{
2691	Log2(("NestedSyncPageWorker: deref! pPte=%RX64 Pte=%RX64\n", SHW_PTE_LOG64(pPte), SHW_PTE_LOG64(Pte)));
2692	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2693	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2694	}
2695	}
2696	else if (SHW_PTE_IS_P(*pPte))
2697	{
2698	Log2(("NestedSyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2699	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2700	}
2701
2702	/*
2703	* Commit the entry.
2704	*/
2705	SHW_PTE_ATOMIC_SET2(*pPte, Pte);
2706	return;
2707	}
2708
2709
2710	/**
2711	* Syncs a nested-guest page.
2712	*
2713	* There are no conflicts at this point, neither is there any need for
2714	* page table allocations.
2715	*
2716	* @returns VBox status code.
2717	* @param pVCpu The cross context virtual CPU structure.
2718	* @param GCPhysNestedPage The nested-guest physical address of the page being
2719	* synced.
2720	* @param GCPhysPage The guest-physical address of the page being synced.
2721	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2722	* @param uErr The page fault error (X86_TRAP_PF_XXX).
2723	* @param pGstWalkAll The guest page table walk result.
2724	*/
2725	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
2726	uint32_t uErr, PPGMPTWALKGST pGstWalkAll)
2727	{
2728	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2729	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2730	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2731
2732	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2733	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2734	Log7Func(("GCPhysNestedPage=%RGv GCPhysPage=%RGp cPages=%u uErr=%#x\n", GCPhysNestedPage, GCPhysPage, cPages, uErr));
2735	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages);
2736
2737	PGM_LOCK_ASSERT_OWNER(pVM);
2738
2739	/*
2740	* Get the shadow PDE, find the shadow page table in the pool.
2741	*/
2742	unsigned const iPde = ((GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK);
2743	PEPTPD pPd;
2744	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL, &pPd, pGstWalkAll);
2745	if (RT_SUCCESS(rc))
2746	{ /* likely */ }
2747	else
2748	{
2749	Log(("Failed to fetch EPT PD for %RGp (%RGp) rc=%Rrc\n", GCPhysNestedPage, GCPhysPage, rc));
2750	return rc;
2751	}
2752	Assert(pPd);
2753	EPTPDE Pde = pPd->a[iPde];
2754
2755	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2756	if (!SHW_PDE_IS_P(Pde))
2757	{
2758	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)Pde.u));
2759	Log7Func(("CPU%d: SyncPage: Pde at %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2760	return VINF_SUCCESS; /* force the instruction to be executed again. */
2761	}
2762
2763	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2764	if (SHW_PDE_IS_BIG(Pde))
2765	{
2766	Log7Func(("CPU%d: SyncPage: %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2767	return VINF_SUCCESS;
2768	}
2769
2770	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, Pde.u & EPT_PDE_PG_MASK);
2771	PEPTPT pPt = (PEPTPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2772
2773	/*
2774	* If we've shadowed a guest EPT PDE that maps a 2M page using a 4K table,
2775	* then sync the 4K sub-page in the 2M range.
2776	*/
2777	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2778	{
2779	Assert(!SHW_PDE_IS_BIG(Pde));
2780
2781	Assert(pGstWalkAll->u.Ept.Pte.u == 0);
2782	Assert((Pde.u & EPT_PRESENT_MASK) == (pGstWalkAll->u.Ept.Pde.u & EPT_PRESENT_MASK));
2783	Assert(pShwPage->GCPhys == (pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK));
2784
2785	#if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
2786	PPGMPAGE pPage;
2787	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage); AssertRC(rc);
2788	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
2789	Assert(pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB);
2790	#endif
2791	uint64_t const fGstShwPteFlags = (pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask & ~EPT_E_LEAF)
2792	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2793	SLATPTE GstSlatPte;
2794	GstSlatPte.u = GCPhysPage \| fGstShwPteFlags;
2795
2796	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2797	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, GstSlatPte);
2798	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2799	return VINF_SUCCESS;
2800	}
2801
2802	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2803	# ifdef PGM_SYNC_N_PAGES
2804	if ( cPages > 1
2805	&& !(uErr & X86_TRAP_PF_P)
2806	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2807	{
2808	/*
2809	* This code path is currently only taken for non-present pages!
2810	*
2811	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2812	* deal with locality.
2813	*/
2814	unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2815	unsigned const iPteEnd = RT_MIN(iPte + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPt->a));
2816	if (iPte < PGM_SYNC_NR_PAGES / 2)
2817	iPte = 0;
2818	else
2819	iPte -= PGM_SYNC_NR_PAGES / 2;
2820	for (; iPte < iPteEnd; iPte++)
2821	{
2822	if (!SHW_PTE_IS_P(pPt->a[iPte]))
2823	{
2824	PGMPTWALKGST GstWalkPt;
2825	PGMPTWALK WalkPt;
2826	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2827	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2828	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt,
2829	&GstWalkPt);
2830	if (RT_SUCCESS(rc))
2831	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], WalkPt.GCPhys, pShwPage, iPte, GstWalkPt.u.Ept.Pte);
2832	else
2833	{
2834	/*
2835	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
2836	* Ensure the shadow tables entry is not-present.
2837	*/
2838	/** @todo Potential room for optimization (explained in NestedSyncPT). */
2839	AssertMsg(!pPt->a[iPte].u, ("%RX64\n", pPt->a[iPte].u));
2840	}
2841	Log7Func(("Many: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2842	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2843	break;
2844	}
2845	else
2846	{
2847	# ifdef VBOX_STRICT
2848	/* Paranoia - Verify address of the page is what it should be. */
2849	PGMPTWALKGST GstWalkPt;
2850	PGMPTWALK WalkPt;
2851	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2852	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2853	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt, &GstWalkPt);
2854	AssertRC(rc);
2855	PPGMPAGE pPage;
2856	rc = pgmPhysGetPageEx(pVM, WalkPt.GCPhys, &pPage);
2857	AssertRC(rc);
2858	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]),
2859	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp HCPhys=%RHp Shw=%RHp\n",
2860	GCPhysNestedPage, WalkPt.GCPhys, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2861	# endif
2862	Log7Func(("Many3: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2863	}
2864	}
2865	}
2866	else
2867	# endif /* PGM_SYNC_N_PAGES */
2868	{
2869	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2870	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll->u.Ept.Pte);
2871	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2872	}
2873
2874	return VINF_SUCCESS;
2875	}
2876
2877
2878	/**
2879	* Sync a shadow page table for a nested-guest page table.
2880	*
2881	* The shadow page table is not present in the shadow PDE.
2882	*
2883	* Handles mapping conflicts.
2884	*
2885	* A precondition for this method is that the shadow PDE is not present. The
2886	* caller must take the PGM lock before checking this and continue to hold it
2887	* when calling this method.
2888	*
2889	* @returns VBox status code.
2890	* @param pVCpu The cross context virtual CPU structure.
2891	* @param GCPhysNestedPage The nested-guest physical page address of the page
2892	* being synced.
2893	* @param GCPhysPage The guest-physical address of the page being synced.
2894	* @param pGstWalkAll The guest page table walk result.
2895	*/
2896	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll)
2897	{
2898	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2899	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2900	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2901
2902	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2903	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2904
2905	Log7Func(("GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
2906
2907	PGM_LOCK_ASSERT_OWNER(pVM);
2908	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2909
2910	PEPTPD pPd;
2911	PEPTPDPT pPdpt;
2912	unsigned const iPde = (GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK;
2913	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, &pPdpt, &pPd, pGstWalkAll);
2914	if (RT_SUCCESS(rc))
2915	{ /* likely */ }
2916	else
2917	{
2918	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2919	AssertRC(rc);
2920	return rc;
2921	}
2922	Assert(pPd);
2923	PSHWPDE pPde = &pPd->a[iPde];
2924
2925	unsigned const iPdpt = (GCPhysNestedPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2926	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdpt->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2927	Assert(pShwPde->enmKind == PGMPOOLKIND_EPT_PD_FOR_EPT_PD);
2928
2929	SHWPDE Pde = *pPde;
2930	Assert(!SHW_PDE_IS_P(Pde)); /* We're only supposed to call SyncPT on PDE!P and conflicts. */
2931
2932	# ifdef PGM_WITH_LARGE_PAGES
2933	Assert(BTH_IS_NP_ACTIVE(pVM));
2934
2935	/*
2936	* Check if the guest is mapping a 2M page.
2937	*/
2938	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2939	{
2940	PPGMPAGE pPage;
2941	rc = pgmPhysGetPageEx(pVM, GCPhysPage & X86_PDE2M_PAE_PG_MASK, &pPage);
2942	AssertRCReturn(rc, rc);
2943
2944	/* A20 is always enabled in VMX root and non-root operation. */
2945	Assert(PGM_A20_IS_ENABLED(pVCpu));
2946
2947	/*
2948	* Check if we have or can get a 2M backing page here.
2949	*/
2950	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2951	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2952	{
2953	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
2954	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2955	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2956	}
2957	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2958	{
2959	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
2960	rc = pgmPhysRecheckLargePage(pVM, GCPhysPage, pPage);
2961	if (RT_SUCCESS(rc))
2962	{
2963	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2964	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2965	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2966	}
2967	}
2968	else if (PGMIsUsingLargePages(pVM))
2969	{
2970	rc = pgmPhysAllocLargePage(pVM, GCPhysPage);
2971	if (RT_SUCCESS(rc))
2972	{
2973	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2974	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2975	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2976	}
2977	}
2978
2979	/*
2980	* If we have a 2M backing page, we can map the guest's 2M page right away.
2981	*/
2982	uint64_t const fGstShwBigPdeFlags = (pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask)
2983	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2984	if (HCPhys != NIL_RTHCPHYS)
2985	{
2986	Pde.u = HCPhys \| fGstShwBigPdeFlags;
2987	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzBigPdeMask));
2988	Assert(Pde.u & EPT_E_LEAF);
2989	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
2990
2991	/* Add a reference to the first page only. */
2992	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPde);
2993
2994	Assert(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED);
2995
2996	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2997	Log7Func(("GstPde=%RGp ShwPde=%RX64 [2M]\n", pGstWalkAll->u.Ept.Pde.u, Pde.u));
2998	return VINF_SUCCESS;
2999	}
3000
3001	/*
3002	* We didn't get a perfect 2M fit. Split the 2M page into 4K pages.
3003	* The page ought not to be marked as a big (2M) page at this point.
3004	*/
3005	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
3006
3007	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3008	PGMPOOLACCESS enmAccess;
3009	{
3010	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_USER_EXECUTE)); /* Mode-based execute control for EPT not supported. */
3011	bool const fNoExecute = !(pGstWalkAll->u.Ept.Pde.u & EPT_E_EXECUTE);
3012	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_WRITE)
3013	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3014	else
3015	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3016	}
3017
3018	/*
3019	* Allocate & map a 4K shadow table to cover the 2M guest page.
3020	*/
3021	PPGMPOOLPAGE pShwPage;
3022	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK;
3023	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_2MB, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3024	pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3025	if ( rc == VINF_SUCCESS
3026	\|\| rc == VINF_PGM_CACHED_PAGE)
3027	{ /* likely */ }
3028	else
3029	{
3030	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3031	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3032	}
3033
3034	PSHWPT pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3035	Assert(pPt);
3036	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3037	if (rc == VINF_SUCCESS)
3038	{
3039	/* The 4K PTEs shall inherit the flags of the 2M PDE page sans the leaf bit. */
3040	uint64_t const fGstShwPteFlags = fGstShwBigPdeFlags & ~EPT_E_LEAF;
3041
3042	/* Sync each 4K pages in the 2M range. */
3043	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++)
3044	{
3045	RTGCPHYS const GCPhysSubPage = GCPhysPt \| (iPte << GUEST_PAGE_SHIFT);
3046	SLATPTE GstSlatPte;
3047	GstSlatPte.u = GCPhysSubPage \| fGstShwPteFlags;
3048	Assert(!(GstSlatPte.u & pVCpu->pgm.s.fGstEptMbzPteMask));
3049	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysSubPage, pShwPage, iPte, GstSlatPte);
3050	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [2M->4K]\n", pGstWalkAll->u.Ept.Pte, pPt->a[iPte].u, iPte));
3051	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3052	break;
3053	}
3054	}
3055	else
3056	{
3057	Assert(rc == VINF_PGM_CACHED_PAGE);
3058	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3059	/* Paranoia - Verify address of each of the subpages are what they should be. */
3060	RTGCPHYS GCPhysSubPage = GCPhysPt;
3061	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++, GCPhysSubPage += GUEST_PAGE_SIZE)
3062	{
3063	PPGMPAGE pSubPage;
3064	rc = pgmPhysGetPageEx(pVM, GCPhysSubPage, &pSubPage);
3065	AssertRC(rc);
3066	AssertMsg( PGM_PAGE_GET_HCPHYS(pSubPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte])
3067	\|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3068	("PGM 2M page and shadow PTE conflict. GCPhysSubPage=%RGp Page=%RHp Shw=%RHp\n",
3069	GCPhysSubPage, PGM_PAGE_GET_HCPHYS(pSubPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3070	}
3071	# endif
3072	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3073	}
3074
3075	/* Save the new PDE. */
3076	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3077	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3078	Assert(!(Pde.u & EPT_E_LEAF));
3079	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3080	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3081	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3082	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3083	return rc;
3084	}
3085	# endif /* PGM_WITH_LARGE_PAGES */
3086
3087	/*
3088	* Allocate & map the shadow page table.
3089	*/
3090	PSHWPT pPt;
3091	PPGMPOOLPAGE pShwPage;
3092
3093	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE_PG_MASK;
3094	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_PT, PGMPOOLACCESS_DONTCARE,
3095	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3096	if ( rc == VINF_SUCCESS
3097	\|\| rc == VINF_PGM_CACHED_PAGE)
3098	{ /* likely */ }
3099	else
3100	{
3101	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3102	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3103	}
3104
3105	pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3106	Assert(pPt);
3107	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3108
3109	if (rc == VINF_SUCCESS)
3110	{
3111	/* Sync the page we've already translated through SLAT. */
3112	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3113	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll->u.Ept.Pte);
3114	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3115
3116	/* Sync the rest of page table (expensive but might be cheaper than nested-guest VM-exits in hardware). */
3117	for (unsigned iPteCur = 0; iPteCur < RT_ELEMENTS(pPt->a); iPteCur++)
3118	{
3119	if (iPteCur != iPte)
3120	{
3121	PGMPTWALKGST GstWalkPt;
3122	PGMPTWALK WalkPt;
3123	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
3124	GCPhysNestedPage \|= (iPteCur << GUEST_PAGE_SHIFT);
3125	int const rc2 = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/,
3126	&WalkPt, &GstWalkPt);
3127	if (RT_SUCCESS(rc2))
3128	{
3129	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPteCur], WalkPt.GCPhys, pShwPage, iPteCur,
3130	GstWalkPt.u.Ept.Pte);
3131	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", GstWalkPt.u.Ept.Pte.u, pPt->a[iPteCur].u, iPteCur));
3132	}
3133	else
3134	{
3135	/*
3136	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
3137	* Ensure the shadow tables entry is not-present.
3138	*/
3139	/** @todo We currently don't configure these to cause EPT misconfigs but rather trap
3140	* them using EPT violations and walk the guest EPT tables to determine
3141	* whether they are EPT misconfigs VM-exits for the nested-hypervisor. We
3142	* could optimize this by using a specific combination of reserved bits
3143	* which we could immediately identify as EPT misconfigs of the
3144	* nested-hypervisor without having to walk its EPT tables. However, tracking
3145	* non-present entries might be tricky...
3146	*/
3147	AssertMsg(!pPt->a[iPteCur].u, ("%RX64\n", pPt->a[iPteCur].u));
3148	}
3149	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3150	break;
3151	}
3152	}
3153	}
3154	else
3155	{
3156	Assert(rc == VINF_PGM_CACHED_PAGE);
3157	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3158	/* Paranoia - Verify address of the page is what it should be. */
3159	PPGMPAGE pPage;
3160	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
3161	AssertRC(rc);
3162	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3163	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]) \|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3164	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp Page=%RHp Shw=%RHp\n",
3165	GCPhysNestedPage, GCPhysPage, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3166	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [cache]\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3167	# endif
3168	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3169	}
3170
3171	/* Save the new PDE. */
3172	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3173	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF));
3174	Assert(!(pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3175	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3176	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3177	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3178
3179	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3180	return rc;
3181	}
3182
3183	#endif /* !IN_RING3 && VBOX_WITH_NESTED_HWVIRT_VMX_EPT && PGM_SHW_TYPE == PGM_TYPE_EPT*/
3184	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
3185
3186	/**
3187	* Handle dirty bit tracking faults.
3188	*
3189	* @returns VBox status code.
3190	* @param pVCpu The cross context virtual CPU structure.
3191	* @param uErr Page fault error code.
3192	* @param pPdeSrc Guest page directory entry.
3193	* @param pPdeDst Shadow page directory entry.
3194	* @param GCPtrPage Guest context page address.
3195	*/
3196	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
3197	RTGCPTR GCPtrPage)
3198	{
3199	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3200	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3201	NOREF(uErr);
3202
3203	PGM_LOCK_ASSERT_OWNER(pVM);
3204
3205	/*
3206	* Handle big page.
3207	*/
3208	if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
3209	{
3210	if ((pPdeDst->u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3211	{
3212	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3213	Assert(pPdeSrc->u & X86_PDE_RW);
3214
3215	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
3216	* fault again and take this path to only invalidate the entry (see below). */
3217	SHWPDE PdeDst = *pPdeDst;
3218	PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
3219	PdeDst.u \|= X86_PDE_RW \| X86_PDE_A;
3220	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3221	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
3222	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3223	}
3224
3225	# ifdef IN_RING0
3226	/* Check for stale TLB entry; only applies to the SMP guest case. */
3227	if ( pVM->cCpus > 1
3228	&& (pPdeDst->u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A))
3229	{
3230	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3231	if (pShwPage)
3232	{
3233	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3234	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3235	if (SHW_PTE_IS_P_RW(*pPteDst))
3236	{
3237	/* Stale TLB entry. */
3238	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3239	PGM_INVL_PG(pVCpu, GCPtrPage);
3240	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3241	}
3242	}
3243	}
3244	# endif /* IN_RING0 */
3245	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3246	}
3247
3248	/*
3249	* Map the guest page table.
3250	*/
3251	PGSTPT pPTSrc;
3252	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
3253	AssertRCReturn(rc, rc);
3254
3255	if (SHW_PDE_IS_P(*pPdeDst))
3256	{
3257	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
3258	const GSTPTE PteSrc = *pPteSrc;
3259
3260	/*
3261	* Map shadow page table.
3262	*/
3263	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3264	if (pShwPage)
3265	{
3266	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3267	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3268	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
3269	{
3270	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
3271	{
3272	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
3273	SHWPTE PteDst = *pPteDst;
3274
3275	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
3276	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3277
3278	Assert(PteSrc.u & X86_PTE_RW);
3279
3280	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
3281	* entry will not harm; write access will simply fault again and
3282	* take this path to only invalidate the entry.
3283	*/
3284	if (RT_LIKELY(pPage))
3285	{
3286	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3287	{
3288	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
3289	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
3290	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
3291	SHW_PTE_SET_RO(PteDst);
3292	}
3293	else
3294	{
3295	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
3296	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
3297	{
3298	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
3299	AssertRC(rc);
3300	}
3301	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
3302	SHW_PTE_SET_RW(PteDst);
3303	else
3304	{
3305	/* Still applies to shared pages. */
3306	Assert(!PGM_PAGE_IS_ZERO(pPage));
3307	SHW_PTE_SET_RO(PteDst);
3308	}
3309	}
3310	}
3311	else
3312	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
3313
3314	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
3315	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
3316	PGM_INVL_PG(pVCpu, GCPtrPage);
3317	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3318	}
3319
3320	# ifdef IN_RING0
3321	/* Check for stale TLB entry; only applies to the SMP guest case. */
3322	if ( pVM->cCpus > 1
3323	&& SHW_PTE_IS_RW(*pPteDst)
3324	&& SHW_PTE_IS_A(*pPteDst))
3325	{
3326	/* Stale TLB entry. */
3327	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3328	PGM_INVL_PG(pVCpu, GCPtrPage);
3329	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3330	}
3331	# endif
3332	}
3333	}
3334	else
3335	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
3336	}
3337
3338	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3339	}
3340
3341	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
3342
3343	/**
3344	* Sync a shadow page table.
3345	*
3346	* The shadow page table is not present in the shadow PDE.
3347	*
3348	* Handles mapping conflicts.
3349	*
3350	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
3351	* conflict), and Trap0eHandler.
3352	*
3353	* A precondition for this method is that the shadow PDE is not present. The
3354	* caller must take the PGM lock before checking this and continue to hold it
3355	* when calling this method.
3356	*
3357	* @returns VBox status code.
3358	* @param pVCpu The cross context virtual CPU structure.
3359	* @param iPDSrc Page directory index.
3360	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
3361	* Assume this is a temporary mapping.
3362	* @param GCPtrPage GC Pointer of the page that caused the fault
3363	*/
3364	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
3365	{
3366	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3367	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3368
3369	#if 0 /* rarely useful; leave for debugging. */
3370	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
3371	#endif
3372	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
3373
3374	PGM_LOCK_ASSERT_OWNER(pVM);
3375
3376	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3377	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3378	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3379	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3380	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3381	int rc = VINF_SUCCESS;
3382
3383	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3384
3385	/*
3386	* Some input validation first.
3387	*/
3388	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
3389
3390	/*
3391	* Get the relevant shadow PDE entry.
3392	*/
3393	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3394	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
3395	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3396
3397	/* Fetch the pgm pool shadow descriptor. */
3398	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3399	Assert(pShwPde);
3400
3401	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3402	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3403	PPGMPOOLPAGE pShwPde = NULL;
3404	PX86PDPAE pPDDst;
3405	PSHWPDE pPdeDst;
3406
3407	/* Fetch the pgm pool shadow descriptor. */
3408	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3409	AssertRCSuccessReturn(rc, rc);
3410	Assert(pShwPde);
3411
3412	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3413	pPdeDst = &pPDDst->a[iPDDst];
3414
3415	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3416	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3417	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3418	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3419	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
3420	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3421	AssertRCSuccessReturn(rc, rc);
3422	Assert(pPDDst);
3423	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3424
3425	# endif
3426	SHWPDE PdeDst = *pPdeDst;
3427
3428	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3429	/* Fetch the pgm pool shadow descriptor. */
3430	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3431	Assert(pShwPde);
3432	# endif
3433
3434	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P.*/
3435
3436	/*
3437	* Sync the page directory entry.
3438	*/
3439	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3440	const bool fPageTable = !(PdeSrc.u & X86_PDE_PS) \|\| !GST_IS_PSE_ACTIVE(pVCpu);
3441	if ( (PdeSrc.u & X86_PDE_P)
3442	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
3443	{
3444	/*
3445	* Allocate & map the page table.
3446	*/
3447	PSHWPT pPTDst;
3448	PPGMPOOLPAGE pShwPage;
3449	RTGCPHYS GCPhys;
3450	if (fPageTable)
3451	{
3452	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
3453	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3454	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3455	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
3456	# endif
3457	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
3458	pShwPde->idx, iPDDst, false /fLockPage/,
3459	&pShwPage);
3460	}
3461	else
3462	{
3463	PGMPOOLACCESS enmAccess;
3464	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
3465	const bool fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
3466	# else
3467	const bool fNoExecute = false;
3468	# endif
3469
3470	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3471	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3472	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3473	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
3474	# endif
3475	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3476	if (PdeSrc.u & X86_PDE_US)
3477	{
3478	if (PdeSrc.u & X86_PDE_RW)
3479	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
3480	else
3481	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
3482	}
3483	else
3484	{
3485	if (PdeSrc.u & X86_PDE_RW)
3486	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3487	else
3488	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3489	}
3490	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3491	pShwPde->idx, iPDDst, false /fLockPage/,
3492	&pShwPage);
3493	}
3494	if (rc == VINF_SUCCESS)
3495	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3496	else if (rc == VINF_PGM_CACHED_PAGE)
3497	{
3498	/*
3499	* The PT was cached, just hook it up.
3500	*/
3501	if (fPageTable)
3502	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3503	else
3504	{
3505	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3506	/* (see explanation and assumptions further down.) */
3507	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3508	{
3509	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3510	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3511	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3512	}
3513	}
3514	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3515	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3516	return VINF_SUCCESS;
3517	}
3518	else
3519	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3520	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
3521	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
3522	* irrelevant at this point. */
3523	PdeDst.u &= X86_PDE_AVL_MASK;
3524	PdeDst.u \|= pShwPage->Core.Key;
3525
3526	/*
3527	* Page directory has been accessed (this is a fault situation, remember).
3528	*/
3529	/** @todo
3530	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
3531	* fault situation. What's more, the Trap0eHandler has already set the
3532	* accessed bit. So, it's actually just VerifyAccessSyncPage which
3533	* might need setting the accessed flag.
3534	*
3535	* The best idea is to leave this change to the caller and add an
3536	* assertion that it's set already. */
3537	pPDSrc->a[iPDSrc].u \|= X86_PDE_A;
3538	if (fPageTable)
3539	{
3540	/*
3541	* Page table - 4KB.
3542	*
3543	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
3544	*/
3545	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
3546	GCPtrPage, PdeSrc.u & X86_PTE_P, !!(PdeSrc.u & X86_PTE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u));
3547	PGSTPT pPTSrc;
3548	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
3549	if (RT_SUCCESS(rc))
3550	{
3551	/*
3552	* Start by syncing the page directory entry so CSAM's TLB trick works.
3553	*/
3554	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
3555	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3556	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3557	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3558
3559	/*
3560	* Directory/page user or supervisor privilege: (same goes for read/write)
3561	*
3562	* Directory Page Combined
3563	* U/S U/S U/S
3564	* 0 0 0
3565	* 0 1 0
3566	* 1 0 0
3567	* 1 1 1
3568	*
3569	* Simple AND operation. Table listed for completeness.
3570	*
3571	*/
3572	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4K));
3573	# ifdef PGM_SYNC_N_PAGES
3574	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3575	unsigned iPTDst = iPTBase;
3576	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
3577	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
3578	iPTDst = 0;
3579	else
3580	iPTDst -= PGM_SYNC_NR_PAGES / 2;
3581	# else /* !PGM_SYNC_N_PAGES */
3582	unsigned iPTDst = 0;
3583	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
3584	# endif /* !PGM_SYNC_N_PAGES */
3585	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
3586	\| ((RTGCPTR)iPTDst << GUEST_PAGE_SHIFT);
3587	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3588	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3589	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
3590	# else
3591	const unsigned offPTSrc = 0;
3592	# endif
3593	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += GUEST_PAGE_SIZE)
3594	{
3595	const unsigned iPTSrc = iPTDst + offPTSrc;
3596	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
3597	if (PteSrc.u & X86_PTE_P)
3598	{
3599	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
3600	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
3601	GCPtrCur,
3602	PteSrc.u & X86_PTE_P,
3603	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
3604	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
3605	(uint64_t)PteSrc.u,
3606	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
3607	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
3608	}
3609	/* else: the page table was cleared by the pool */
3610	} /* for PTEs */
3611	}
3612	}
3613	else
3614	{
3615	/*
3616	* Big page - 2/4MB.
3617	*
3618	* We'll walk the ram range list in parallel and optimize lookups.
3619	* We will only sync one shadow page table at a time.
3620	*/
3621	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4M));
3622
3623	/**
3624	* @todo It might be more efficient to sync only a part of the 4MB
3625	* page (similar to what we do for 4KB PDs).
3626	*/
3627
3628	/*
3629	* Start by syncing the page directory entry.
3630	*/
3631	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
3632	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3633
3634	/*
3635	* If the page is not flagged as dirty and is writable, then make it read-only
3636	* at PD level, so we can set the dirty bit when the page is modified.
3637	*
3638	* ASSUMES that page access handlers are implemented on page table entry level.
3639	* Thus we will first catch the dirty access and set PDE.D and restart. If
3640	* there is an access handler, we'll trap again and let it work on the problem.
3641	*/
3642	/** @todo move the above stuff to a section in the PGM documentation. */
3643	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3644	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3645	{
3646	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3647	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3648	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3649	}
3650	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3651	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3652
3653	/*
3654	* Fill the shadow page table.
3655	*/
3656	/* Get address and flags from the source PDE. */
3657	SHWPTE PteDstBase;
3658	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3659
3660	/* Loop thru the entries in the shadow PT. */
3661	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3662	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3663	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u, GCPtr,
3664	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3665	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3666	unsigned iPTDst = 0;
3667	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3668	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3669	{
3670	if (pRam && GCPhys >= pRam->GCPhys)
3671	{
3672	# ifndef PGM_WITH_A20
3673	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT;
3674	# endif
3675	do
3676	{
3677	/* Make shadow PTE. */
3678	# ifdef PGM_WITH_A20
3679	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT];
3680	# else
3681	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3682	# endif
3683	SHWPTE PteDst;
3684
3685	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3686	/* Try to make the page writable if necessary. */
3687	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3688	&& ( PGM_PAGE_IS_ZERO(pPage)
3689	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3690	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3691	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3692	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3693	# endif
3694	# ifdef VBOX_WITH_PAGE_SHARING
3695	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3696	# endif
3697	&& !PGM_PAGE_IS_BALLOONED(pPage))
3698	)
3699	)
3700	{
3701	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3702	AssertRCReturn(rc, rc);
3703	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3704	break;
3705	}
3706	# endif
3707
3708	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3709	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, SHW_PTE_GET_U(PteDstBase), &PteDst);
3710	else if (PGM_PAGE_IS_BALLOONED(pPage))
3711	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3712	else
3713	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3714
3715	/* Only map writable pages writable. */
3716	if ( SHW_PTE_IS_P_RW(PteDst)
3717	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3718	{
3719	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3720	/* Still applies to shared pages. */
3721	Assert(!PGM_PAGE_IS_ZERO(pPage));
3722	# endif
3723	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3724	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3725	}
3726
3727	if (SHW_PTE_IS_P(PteDst))
3728	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3729
3730	/* commit it (not atomic, new table) */
3731	pPTDst->a[iPTDst] = PteDst;
3732	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3733	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3734	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3735
3736	/* advance */
3737	GCPhys += GUEST_PAGE_SIZE;
3738	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3739	# ifndef PGM_WITH_A20
3740	iHCPage++;
3741	# endif
3742	iPTDst++;
3743	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3744	&& GCPhys <= pRam->GCPhysLast);
3745
3746	/* Advance ram range list. */
3747	while (pRam && GCPhys > pRam->GCPhysLast)
3748	pRam = pRam->CTX_SUFF(pNext);
3749	}
3750	else if (pRam)
3751	{
3752	Log(("Invalid pages at %RGp\n", GCPhys));
3753	do
3754	{
3755	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3756	GCPhys += GUEST_PAGE_SIZE;
3757	iPTDst++;
3758	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3759	&& GCPhys < pRam->GCPhys);
3760	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3761	}
3762	else
3763	{
3764	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3765	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3766	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3767	}
3768	} /* while more PTEs */
3769	} /* 4KB / 4MB */
3770	}
3771	else
3772	AssertRelease(!SHW_PDE_IS_P(PdeDst));
3773
3774	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3775	if (RT_FAILURE(rc))
3776	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3777	return rc;
3778
3779	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3780	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
3781	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3782	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3783	NOREF(iPDSrc); NOREF(pPDSrc);
3784
3785	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3786
3787	/*
3788	* Validate input a little bit.
3789	*/
3790	int rc = VINF_SUCCESS;
3791	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3792	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3793	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3794
3795	/* Fetch the pgm pool shadow descriptor. */
3796	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3797	Assert(pShwPde);
3798
3799	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3800	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3801	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3802	PX86PDPAE pPDDst;
3803	PSHWPDE pPdeDst;
3804
3805	/* Fetch the pgm pool shadow descriptor. */
3806	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3807	AssertRCSuccessReturn(rc, rc);
3808	Assert(pShwPde);
3809
3810	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3811	pPdeDst = &pPDDst->a[iPDDst];
3812
3813	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3814	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3815	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3816	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3817	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3818	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3819	AssertRCSuccessReturn(rc, rc);
3820	Assert(pPDDst);
3821	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3822
3823	/* Fetch the pgm pool shadow descriptor. */
3824	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3825	Assert(pShwPde);
3826
3827	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3828	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3829	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3830	PEPTPD pPDDst;
3831	PEPTPDPT pPdptDst;
3832
3833	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3834	if (rc != VINF_SUCCESS)
3835	{
3836	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3837	AssertRC(rc);
3838	return rc;
3839	}
3840	Assert(pPDDst);
3841	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3842
3843	/* Fetch the pgm pool shadow descriptor. */
3844	/** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
3845	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3846	Assert(pShwPde);
3847	# endif
3848	SHWPDE PdeDst = *pPdeDst;
3849
3850	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3851
3852	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3853	if (BTH_IS_NP_ACTIVE(pVM))
3854	{
3855	Assert(!VM_IS_NEM_ENABLED(pVM));
3856
3857	/* Check if we allocated a big page before for this 2 MB range. */
3858	PPGMPAGE pPage;
3859	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3860	if (RT_SUCCESS(rc))
3861	{
3862	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3863	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3864	{
3865	if (PGM_A20_IS_ENABLED(pVCpu))
3866	{
3867	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3868	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3869	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3870	}
3871	else
3872	{
3873	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3874	pVM->pgm.s.cLargePagesDisabled++;
3875	}
3876	}
3877	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3878	&& PGM_A20_IS_ENABLED(pVCpu))
3879	{
3880	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3881	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3882	if (RT_SUCCESS(rc))
3883	{
3884	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3885	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3886	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3887	}
3888	}
3889	# if !defined(VBOX_WITH_NEW_LAZY_PAGE_ALLOC) && !defined(PGM_WITH_PAGE_ZEROING_DETECTION) /* This code is too aggresive! */
3890	else if ( PGMIsUsingLargePages(pVM)
3891	&& PGM_A20_IS_ENABLED(pVCpu))
3892	{
3893	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3894	if (RT_SUCCESS(rc))
3895	{
3896	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3897	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3898	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3899	}
3900	else
3901	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3902	}
3903	# endif
3904
3905	if (HCPhys != NIL_RTHCPHYS)
3906	{
3907	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3908	PdeDst.u = HCPhys \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_LEAF \| EPT_E_IGNORE_PAT \| EPT_E_MEMTYPE_WB
3909	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
3910	# else
3911	PdeDst.u = HCPhys \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PS
3912	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
3913	# endif
3914	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3915
3916	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3917	/* Add a reference to the first page only. */
3918	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3919
3920	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3921	return VINF_SUCCESS;
3922	}
3923	}
3924	}
3925	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
3926
3927	/*
3928	* Allocate & map the page table.
3929	*/
3930	PSHWPT pPTDst;
3931	PPGMPOOLPAGE pShwPage;
3932	RTGCPHYS GCPhys;
3933
3934	/* Virtual address = physical address */
3935	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3936	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3937	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3938	&pShwPage);
3939	if ( rc == VINF_SUCCESS
3940	\|\| rc == VINF_PGM_CACHED_PAGE)
3941	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3942	else
3943	{
3944	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3945	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3946	}
3947
3948	if (rc == VINF_SUCCESS)
3949	{
3950	/* New page table; fully set it up. */
3951	Assert(pPTDst);
3952
3953	/* Mask away the page offset. */
3954	GCPtrPage &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
3955
3956	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3957	{
3958	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3959	\| (iPTDst << GUEST_PAGE_SHIFT));
3960
3961	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3962	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3963	GCPtrCurPage,
3964	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3965	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3966
3967	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3968	break;
3969	}
3970	}
3971	else
3972	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3973
3974	/* Save the new PDE. */
3975	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3976	PdeDst.u = pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE
3977	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
3978	# else
3979	PdeDst.u = pShwPage->Core.Key \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A
3980	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
3981	# endif
3982	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3983
3984	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3985	if (RT_FAILURE(rc))
3986	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3987	return rc;
3988
3989	#else
3990	NOREF(iPDSrc); NOREF(pPDSrc);
3991	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3992	return VERR_PGM_NOT_USED_IN_MODE;
3993	#endif
3994	}
3995
3996
3997
3998	/**
3999	* Prefetch a page/set of pages.
4000	*
4001	* Typically used to sync commonly used pages before entering raw mode
4002	* after a CR3 reload.
4003	*
4004	* @returns VBox status code.
4005	* @param pVCpu The cross context virtual CPU structure.
4006	* @param GCPtrPage Page to invalidate.
4007	*/
4008	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
4009	{
4010	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4011	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4012	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4013	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4014	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4015	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4016	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4017	/*
4018	* Check that all Guest levels thru the PDE are present, getting the
4019	* PD and PDE in the processes.
4020	*/
4021	int rc = VINF_SUCCESS;
4022	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4023	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4024	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4025	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4026	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4027	unsigned iPDSrc;
4028	X86PDPE PdpeSrc;
4029	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4030	if (!pPDSrc)
4031	return VINF_SUCCESS; /* not present */
4032	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4033	unsigned iPDSrc;
4034	PX86PML4E pPml4eSrc;
4035	X86PDPE PdpeSrc;
4036	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4037	if (!pPDSrc)
4038	return VINF_SUCCESS; /* not present */
4039	# endif
4040	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4041	# else
4042	PGSTPD pPDSrc = NULL;
4043	const unsigned iPDSrc = 0;
4044	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4045	# endif
4046
4047	if ((PdeSrc.u & (X86_PDE_P \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_A))
4048	{
4049	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4050	PGM_LOCK_VOID(pVM);
4051
4052	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4053	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
4054	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4055	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4056	PX86PDPAE pPDDst;
4057	X86PDEPAE PdeDst;
4058	# if PGM_GST_TYPE != PGM_TYPE_PAE
4059	X86PDPE PdpeSrc;
4060
4061	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4062	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4063	# endif
4064	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4065	if (rc != VINF_SUCCESS)
4066	{
4067	PGM_UNLOCK(pVM);
4068	AssertRC(rc);
4069	return rc;
4070	}
4071	Assert(pPDDst);
4072	PdeDst = pPDDst->a[iPDDst];
4073
4074	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4075	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4076	PX86PDPAE pPDDst;
4077	X86PDEPAE PdeDst;
4078
4079	# if PGM_GST_TYPE == PGM_TYPE_PROT
4080	/* AMD-V nested paging */
4081	X86PML4E Pml4eSrc;
4082	X86PDPE PdpeSrc;
4083	PX86PML4E pPml4eSrc = &Pml4eSrc;
4084
4085	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4086	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4087	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4088	# endif
4089
4090	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4091	if (rc != VINF_SUCCESS)
4092	{
4093	PGM_UNLOCK(pVM);
4094	AssertRC(rc);
4095	return rc;
4096	}
4097	Assert(pPDDst);
4098	PdeDst = pPDDst->a[iPDDst];
4099	# endif
4100	if (!(PdeDst.u & X86_PDE_P))
4101	{
4102	/** @todo r=bird: This guy will set the A bit on the PDE,
4103	* probably harmless. */
4104	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4105	}
4106	else
4107	{
4108	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
4109	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
4110	* makes no sense to prefetch more than one page.
4111	*/
4112	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4113	if (RT_SUCCESS(rc))
4114	rc = VINF_SUCCESS;
4115	}
4116	PGM_UNLOCK(pVM);
4117	}
4118	return rc;
4119
4120	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4121	NOREF(pVCpu); NOREF(GCPtrPage);
4122	return VINF_SUCCESS; /* ignore */
4123	#else
4124	AssertCompile(0);
4125	#endif
4126	}
4127
4128
4129
4130
4131	/**
4132	* Syncs a page during a PGMVerifyAccess() call.
4133	*
4134	* @returns VBox status code (informational included).
4135	* @param pVCpu The cross context virtual CPU structure.
4136	* @param GCPtrPage The address of the page to sync.
4137	* @param fPage The effective guest page flags.
4138	* @param uErr The trap error code.
4139	* @remarks This will normally never be called on invalid guest page
4140	* translation entries.
4141	*/
4142	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
4143	{
4144	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4145
4146	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
4147	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
4148
4149	Assert(!pVM->pgm.s.fNestedPaging);
4150	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4151	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4152	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4153	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4154	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4155	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4156	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4157
4158	/*
4159	* Get guest PD and index.
4160	*/
4161	/** @todo Performance: We've done all this a jiffy ago in the
4162	* PGMGstGetPage call. */
4163	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4164	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4165	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4166	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4167
4168	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4169	unsigned iPDSrc = 0;
4170	X86PDPE PdpeSrc;
4171	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4172	if (RT_UNLIKELY(!pPDSrc))
4173	{
4174	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4175	return VINF_EM_RAW_GUEST_TRAP;
4176	}
4177
4178	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4179	unsigned iPDSrc = 0; /* shut up gcc */
4180	PX86PML4E pPml4eSrc = NULL; /* ditto */
4181	X86PDPE PdpeSrc;
4182	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4183	if (RT_UNLIKELY(!pPDSrc))
4184	{
4185	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4186	return VINF_EM_RAW_GUEST_TRAP;
4187	}
4188	# endif
4189
4190	# else /* !PGM_WITH_PAGING */
4191	PGSTPD pPDSrc = NULL;
4192	const unsigned iPDSrc = 0;
4193	# endif /* !PGM_WITH_PAGING */
4194	int rc = VINF_SUCCESS;
4195
4196	PGM_LOCK_VOID(pVM);
4197
4198	/*
4199	* First check if the shadow pd is present.
4200	*/
4201	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4202	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
4203
4204	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4205	PX86PDEPAE pPdeDst;
4206	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4207	PX86PDPAE pPDDst;
4208	# if PGM_GST_TYPE != PGM_TYPE_PAE
4209	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4210	X86PDPE PdpeSrc;
4211	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4212	# endif
4213	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4214	if (rc != VINF_SUCCESS)
4215	{
4216	PGM_UNLOCK(pVM);
4217	AssertRC(rc);
4218	return rc;
4219	}
4220	Assert(pPDDst);
4221	pPdeDst = &pPDDst->a[iPDDst];
4222
4223	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4224	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4225	PX86PDPAE pPDDst;
4226	PX86PDEPAE pPdeDst;
4227
4228	# if PGM_GST_TYPE == PGM_TYPE_PROT
4229	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4230	X86PML4E Pml4eSrc;
4231	X86PDPE PdpeSrc;
4232	PX86PML4E pPml4eSrc = &Pml4eSrc;
4233	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4234	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4235	# endif
4236
4237	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4238	if (rc != VINF_SUCCESS)
4239	{
4240	PGM_UNLOCK(pVM);
4241	AssertRC(rc);
4242	return rc;
4243	}
4244	Assert(pPDDst);
4245	pPdeDst = &pPDDst->a[iPDDst];
4246	# endif
4247
4248	if (!(pPdeDst->u & X86_PDE_P))
4249	{
4250	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4251	if (rc != VINF_SUCCESS)
4252	{
4253	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4254	PGM_UNLOCK(pVM);
4255	AssertRC(rc);
4256	return rc;
4257	}
4258	}
4259
4260	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4261	/* Check for dirty bit fault */
4262	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
4263	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
4264	Log(("PGMVerifyAccess: success (dirty)\n"));
4265	else
4266	# endif
4267	{
4268	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4269	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4270	# else
4271	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4272	# endif
4273
4274	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
4275	if (uErr & X86_TRAP_PF_US)
4276	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
4277	else /* supervisor */
4278	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
4279
4280	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4281	if (RT_SUCCESS(rc))
4282	{
4283	/* Page was successfully synced */
4284	Log2(("PGMVerifyAccess: success (sync)\n"));
4285	rc = VINF_SUCCESS;
4286	}
4287	else
4288	{
4289	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
4290	rc = VINF_EM_RAW_GUEST_TRAP;
4291	}
4292	}
4293	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4294	PGM_UNLOCK(pVM);
4295	return rc;
4296
4297	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4298
4299	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
4300	return VERR_PGM_NOT_USED_IN_MODE;
4301	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4302	}
4303
4304
4305	/**
4306	* Syncs the paging hierarchy starting at CR3.
4307	*
4308	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
4309	* informational status codes.
4310	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
4311	* the VMM into guest context.
4312	* @param pVCpu The cross context virtual CPU structure.
4313	* @param cr0 Guest context CR0 register.
4314	* @param cr3 Guest context CR3 register. Not subjected to the A20
4315	* mask.
4316	* @param cr4 Guest context CR4 register.
4317	* @param fGlobal Including global page directories or not
4318	*/
4319	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
4320	{
4321	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4322	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
4323
4324	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
4325
4326	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
4327	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4328	PGM_LOCK_VOID(pVM);
4329	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4330	if (pPool->cDirtyPages)
4331	pgmPoolResetDirtyPages(pVM);
4332	PGM_UNLOCK(pVM);
4333	# endif
4334	#endif /* !NESTED && !EPT */
4335
4336	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4337	/*
4338	* Nested / EPT / None - No work.
4339	*/
4340	return VINF_SUCCESS;
4341
4342	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4343	/*
4344	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
4345	* out the shadow parts when the guest modifies its tables.
4346	*/
4347	return VINF_SUCCESS;
4348
4349	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4350
4351	return VINF_SUCCESS;
4352	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4353	}
4354
4355
4356
4357
4358	#ifdef VBOX_STRICT
4359
4360	/**
4361	* Checks that the shadow page table is in sync with the guest one.
4362	*
4363	* @returns The number of errors.
4364	* @param pVCpu The cross context virtual CPU structure.
4365	* @param cr3 Guest context CR3 register.
4366	* @param cr4 Guest context CR4 register.
4367	* @param GCPtr Where to start. Defaults to 0.
4368	* @param cb How much to check. Defaults to everything.
4369	*/
4370	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
4371	{
4372	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
4373	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4374	return 0;
4375	#else
4376	unsigned cErrors = 0;
4377	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4378	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
4379
4380	# if PGM_GST_TYPE == PGM_TYPE_PAE
4381	/** @todo currently broken; crashes below somewhere */
4382	AssertFailed();
4383	# endif
4384
4385	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
4386	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4387	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4388
4389	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
4390	PPGMCPU pPGM = &pVCpu->pgm.s;
4391	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
4392	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
4393	# ifndef IN_RING0
4394	RTHCPHYS HCPhys; /* general usage. */
4395	# endif
4396	int rc;
4397
4398	/*
4399	* Check that the Guest CR3 and all its mappings are correct.
4400	*/
4401	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
4402	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
4403	false);
4404	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
4405	# if 0
4406	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4407	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
4408	# else
4409	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
4410	# endif
4411	AssertRCReturn(rc, 1);
4412	HCPhys = NIL_RTHCPHYS;
4413	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
4414	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
4415	# endif
4416	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
4417	pgmGstGet32bitPDPtr(pVCpu);
4418	RTGCPHYS GCPhys;
4419	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
4420	AssertRCReturn(rc, 1);
4421	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
4422	# endif
4423	# endif /* !IN_RING0 */
4424
4425	/*
4426	* Get and check the Shadow CR3.
4427	*/
4428	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4429	unsigned cPDEs = X86_PG_ENTRIES;
4430	unsigned cIncrement = X86_PG_ENTRIES * GUEST_PAGE_SIZE;
4431	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4432	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4433	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
4434	# else
4435	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4436	# endif
4437	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4438	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4439	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4440	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4441	# endif
4442	if (cb != ~(RTGCPTR)0)
4443	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
4444
4445	/** @todo call the other two PGMAssert() functions. /
4446
4447	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4448	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4449
4450	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
4451	{
4452	PPGMPOOLPAGE pShwPdpt = NULL;
4453	PX86PML4E pPml4eSrc;
4454	PX86PML4E pPml4eDst;
4455	RTGCPHYS GCPhysPdptSrc;
4456
4457	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
4458	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
4459
4460	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
4461	if (!(pPml4eDst->u & X86_PML4E_P))
4462	{
4463	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4464	continue;
4465	}
4466
4467	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
4468	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
4469
4470	if ((pPml4eSrc->u & X86_PML4E_P) != (pPml4eDst->u & X86_PML4E_P))
4471	{
4472	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4473	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4474	cErrors++;
4475	continue;
4476	}
4477
4478	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
4479	{
4480	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
4481	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4482	cErrors++;
4483	continue;
4484	}
4485
4486	if ( (pPml4eDst->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX))
4487	!= (pPml4eSrc->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX)))
4488	{
4489	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4490	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4491	cErrors++;
4492	continue;
4493	}
4494	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4495	{
4496	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4497
4498	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
4499	/*
4500	* Check the PDPTEs too.
4501	*/
4502	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
4503
4504	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
4505	{
4506	unsigned iPDSrc = 0; /* initialized to shut up gcc */
4507	PPGMPOOLPAGE pShwPde = NULL;
4508	PX86PDPE pPdpeDst;
4509	RTGCPHYS GCPhysPdeSrc;
4510	X86PDPE PdpeSrc;
4511	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
4512	# if PGM_GST_TYPE == PGM_TYPE_PAE
4513	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
4514	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
4515	# else
4516	PX86PML4E pPml4eSrcIgn;
4517	PX86PDPT pPdptDst;
4518	PX86PDPAE pPDDst;
4519	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
4520
4521	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
4522	if (rc != VINF_SUCCESS)
4523	{
4524	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
4525	GCPtr += 512 * _2M;
4526	continue; /* next PDPTE */
4527	}
4528	Assert(pPDDst);
4529	# endif
4530	Assert(iPDSrc == 0);
4531
4532	pPdpeDst = &pPdptDst->a[iPdpt];
4533
4534	if (!(pPdpeDst->u & X86_PDPE_P))
4535	{
4536	GCPtr += 512 * _2M;
4537	continue; /* next PDPTE */
4538	}
4539
4540	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
4541	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
4542
4543	if ((pPdpeDst->u & X86_PDPE_P) != (PdpeSrc.u & X86_PDPE_P))
4544	{
4545	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4546	GCPtr += 512 * _2M;
4547	cErrors++;
4548	continue;
4549	}
4550
4551	if (GCPhysPdeSrc != pShwPde->GCPhys)
4552	{
4553	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4554	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4555	# else
4556	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4557	# endif
4558	GCPtr += 512 * _2M;
4559	cErrors++;
4560	continue;
4561	}
4562
4563	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4564	if ( (pPdpeDst->u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX))
4565	!= (PdpeSrc.u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX)))
4566	{
4567	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4568	GCPtr += 512 * _2M;
4569	cErrors++;
4570	continue;
4571	}
4572	# endif
4573
4574	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4575	{
4576	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4577	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4578	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4579	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4580	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4581	# endif
4582	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4583	/*
4584	* Iterate the shadow page directory.
4585	*/
4586	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4587	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4588
4589	for (;
4590	iPDDst < cPDEs;
4591	iPDDst++, GCPtr += cIncrement)
4592	{
4593	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4594	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4595	# else
4596	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4597	# endif
4598	if ( (PdeDst.u & X86_PDE_P)
4599	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) )
4600	{
4601	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4602	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4603	if (!pPoolPage)
4604	{
4605	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4606	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4607	cErrors++;
4608	continue;
4609	}
4610	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4611
4612	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4613	{
4614	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4615	GCPtr, (uint64_t)PdeDst.u));
4616	cErrors++;
4617	}
4618
4619	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4620	{
4621	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4622	GCPtr, (uint64_t)PdeDst.u));
4623	cErrors++;
4624	}
4625
4626	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4627	if (!(PdeSrc.u & X86_PDE_P))
4628	{
4629	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4630	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4631	cErrors++;
4632	continue;
4633	}
4634
4635	if ( !(PdeSrc.u & X86_PDE_PS)
4636	\|\| !fBigPagesSupported)
4637	{
4638	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4639	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4640	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
4641	# endif
4642	}
4643	else
4644	{
4645	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4646	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4647	{
4648	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4649	GCPtr, (uint64_t)PdeSrc.u));
4650	cErrors++;
4651	continue;
4652	}
4653	# endif
4654	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4655	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4656	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4657	# endif
4658	}
4659
4660	if ( pPoolPage->enmKind
4661	!= (!(PdeSrc.u & X86_PDE_PS) \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4662	{
4663	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4664	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4665	cErrors++;
4666	}
4667
4668	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4669	if (!pPhysPage)
4670	{
4671	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4672	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4673	cErrors++;
4674	continue;
4675	}
4676
4677	if (GCPhysGst != pPoolPage->GCPhys)
4678	{
4679	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4680	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4681	cErrors++;
4682	continue;
4683	}
4684
4685	if ( !(PdeSrc.u & X86_PDE_PS)
4686	\|\| !fBigPagesSupported)
4687	{
4688	/*
4689	* Page Table.
4690	*/
4691	const GSTPT *pPTSrc;
4692	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(GUEST_PAGE_SIZE - 1)),
4693	&pPTSrc);
4694	if (RT_FAILURE(rc))
4695	{
4696	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4697	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4698	cErrors++;
4699	continue;
4700	}
4701	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4702	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4703	{
4704	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4705	// (This problem will go away when/if we shadow multiple CR3s.)
4706	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4707	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4708	cErrors++;
4709	continue;
4710	}
4711	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4712	{
4713	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4714	GCPtr, (uint64_t)PdeDst.u));
4715	cErrors++;
4716	continue;
4717	}
4718
4719	/* iterate the page table. */
4720	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4721	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4722	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4723	# else
4724	const unsigned offPTSrc = 0;
4725	# endif
4726	for (unsigned iPT = 0, off = 0;
4727	iPT < RT_ELEMENTS(pPTDst->a);
4728	iPT++, off += GUEST_PAGE_SIZE)
4729	{
4730	const SHWPTE PteDst = pPTDst->a[iPT];
4731
4732	/* skip not-present and dirty tracked entries. */
4733	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4734	continue;
4735	Assert(SHW_PTE_IS_P(PteDst));
4736
4737	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4738	if (!(PteSrc.u & X86_PTE_P))
4739	{
4740	# ifdef IN_RING3
4741	PGMAssertHandlerAndFlagsInSync(pVM);
4742	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4743	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4744	0, 0, UINT64_MAX, 99, NULL);
4745	# endif
4746	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4747	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4748	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4749	cErrors++;
4750	continue;
4751	}
4752
4753	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4754	# if 1 /** @todo sync accessed bit properly... */
4755	fIgnoreFlags \|= X86_PTE_A;
4756	# endif
4757
4758	/* match the physical addresses */
4759	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4760	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4761
4762	# ifdef IN_RING3
4763	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4764	if (RT_FAILURE(rc))
4765	{
4766	# if 0
4767	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4768	{
4769	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4770	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4771	cErrors++;
4772	continue;
4773	}
4774	# endif
4775	}
4776	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4777	{
4778	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4779	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4780	cErrors++;
4781	continue;
4782	}
4783	# endif
4784
4785	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4786	if (!pPhysPage)
4787	{
4788	# if 0
4789	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4790	{
4791	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4792	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4793	cErrors++;
4794	continue;
4795	}
4796	# endif
4797	if (SHW_PTE_IS_RW(PteDst))
4798	{
4799	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4800	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4801	cErrors++;
4802	}
4803	fIgnoreFlags \|= X86_PTE_RW;
4804	}
4805	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4806	{
4807	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4808	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4809	cErrors++;
4810	continue;
4811	}
4812
4813	/* flags */
4814	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
4815	{
4816	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4817	{
4818	if (SHW_PTE_IS_RW(PteDst))
4819	{
4820	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4821	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4822	cErrors++;
4823	continue;
4824	}
4825	fIgnoreFlags \|= X86_PTE_RW;
4826	}
4827	else
4828	{
4829	if ( SHW_PTE_IS_P(PteDst)
4830	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4831	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4832	# endif
4833	)
4834	{
4835	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4836	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4837	cErrors++;
4838	continue;
4839	}
4840	fIgnoreFlags \|= X86_PTE_P;
4841	}
4842	}
4843	else
4844	{
4845	if ((PteSrc.u & (X86_PTE_RW \| X86_PTE_D)) == X86_PTE_RW)
4846	{
4847	if (SHW_PTE_IS_RW(PteDst))
4848	{
4849	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4850	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4851	cErrors++;
4852	continue;
4853	}
4854	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4855	{
4856	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4857	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4858	cErrors++;
4859	continue;
4860	}
4861	if (SHW_PTE_IS_D(PteDst))
4862	{
4863	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4864	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4865	cErrors++;
4866	}
4867	# if 0 /** @todo sync access bit properly... */
4868	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4869	{
4870	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4871	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4872	cErrors++;
4873	}
4874	fIgnoreFlags \|= X86_PTE_RW;
4875	# else
4876	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4877	# endif
4878	}
4879	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4880	{
4881	/* access bit emulation (not implemented). */
4882	if ((PteSrc.u & X86_PTE_A) \|\| SHW_PTE_IS_P(PteDst))
4883	{
4884	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4885	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4886	cErrors++;
4887	continue;
4888	}
4889	if (!SHW_PTE_IS_A(PteDst))
4890	{
4891	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4892	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4893	cErrors++;
4894	}
4895	fIgnoreFlags \|= X86_PTE_P;
4896	}
4897	# ifdef DEBUG_sandervl
4898	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4899	# endif
4900	}
4901
4902	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4903	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4904	)
4905	{
4906	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4907	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4908	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4909	cErrors++;
4910	continue;
4911	}
4912	} /* foreach PTE */
4913	}
4914	else
4915	{
4916	/*
4917	* Big Page.
4918	*/
4919	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4920	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
4921	{
4922	if (PdeDst.u & X86_PDE_RW)
4923	{
4924	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4925	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4926	cErrors++;
4927	continue;
4928	}
4929	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4930	{
4931	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4932	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4933	cErrors++;
4934	continue;
4935	}
4936	# if 0 /** @todo sync access bit properly... */
4937	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4938	{
4939	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4940	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4941	cErrors++;
4942	}
4943	fIgnoreFlags \|= X86_PTE_RW;
4944	# else
4945	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4946	# endif
4947	}
4948	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4949	{
4950	/* access bit emulation (not implemented). */
4951	if ((PdeSrc.u & X86_PDE_A) \|\| SHW_PDE_IS_P(PdeDst))
4952	{
4953	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4954	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4955	cErrors++;
4956	continue;
4957	}
4958	if (!SHW_PDE_IS_A(PdeDst))
4959	{
4960	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4961	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4962	cErrors++;
4963	}
4964	fIgnoreFlags \|= X86_PTE_P;
4965	}
4966
4967	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4968	{
4969	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4970	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4971	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4972	cErrors++;
4973	}
4974
4975	/* iterate the page table. */
4976	for (unsigned iPT = 0, off = 0;
4977	iPT < RT_ELEMENTS(pPTDst->a);
4978	iPT++, off += GUEST_PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + GUEST_PAGE_SIZE))
4979	{
4980	const SHWPTE PteDst = pPTDst->a[iPT];
4981
4982	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4983	{
4984	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4985	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4986	cErrors++;
4987	}
4988
4989	/* skip not-present entries. */
4990	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4991	continue;
4992
4993	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4994
4995	/* match the physical addresses */
4996	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4997
4998	# ifdef IN_RING3
4999	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
5000	if (RT_FAILURE(rc))
5001	{
5002	# if 0
5003	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
5004	{
5005	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
5006	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5007	cErrors++;
5008	}
5009	# endif
5010	}
5011	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
5012	{
5013	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5014	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5015	cErrors++;
5016	continue;
5017	}
5018	# endif
5019	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
5020	if (!pPhysPage)
5021	{
5022	# if 0 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
5023	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
5024	{
5025	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
5026	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5027	cErrors++;
5028	continue;
5029	}
5030	# endif
5031	if (SHW_PTE_IS_RW(PteDst))
5032	{
5033	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5034	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5035	cErrors++;
5036	}
5037	fIgnoreFlags \|= X86_PTE_RW;
5038	}
5039	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
5040	{
5041	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5042	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5043	cErrors++;
5044	continue;
5045	}
5046
5047	/* flags */
5048	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
5049	{
5050	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
5051	{
5052	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
5053	{
5054	if ( SHW_PTE_IS_RW(PteDst)
5055	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
5056	{
5057	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
5058	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5059	cErrors++;
5060	continue;
5061	}
5062	fIgnoreFlags \|= X86_PTE_RW;
5063	}
5064	}
5065	else
5066	{
5067	if ( SHW_PTE_IS_P(PteDst)
5068	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage)
5069	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
5070	&& !PGM_PAGE_IS_MMIO(pPhysPage)
5071	# endif
5072	)
5073	{
5074	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
5075	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5076	cErrors++;
5077	continue;
5078	}
5079	fIgnoreFlags \|= X86_PTE_P;
5080	}
5081	}
5082
5083	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
5084	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
5085	)
5086	{
5087	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
5088	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
5089	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5090	cErrors++;
5091	continue;
5092	}
5093	} /* for each PTE */
5094	}
5095	}
5096	/* not present */
5097
5098	} /* for each PDE */
5099
5100	} /* for each PDPTE */
5101
5102	} /* for each PML4E */
5103
5104	# ifdef DEBUG
5105	if (cErrors)
5106	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
5107	# endif
5108	# endif /* GST is in {32BIT, PAE, AMD64} */
5109	return cErrors;
5110	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
5111	}
5112	#endif /* VBOX_STRICT */
5113
5114
5115	/**
5116	* Sets up the CR3 for shadow paging
5117	*
5118	* @returns Strict VBox status code.
5119	* @retval VINF_SUCCESS.
5120	*
5121	* @param pVCpu The cross context virtual CPU structure.
5122	* @param GCPhysCR3 The physical address in the CR3 register. (A20 mask
5123	* already applied.)
5124	*/
5125	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
5126	{
5127	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5128	int rc = VINF_SUCCESS;
5129
5130	/* Update guest paging info. */
5131	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5132	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
5133	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
5134
5135	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
5136	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5137
5138	# if PGM_GST_TYPE == PGM_TYPE_PAE
5139	if ( !pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped)
5140	\|\| pVCpu->pgm.s.GCPhysPaeCR3 != GCPhysCR3)
5141	# endif
5142	{
5143	/*
5144	* Map the page CR3 points at.
5145	*/
5146	RTHCPTR HCPtrGuestCR3;
5147	rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCR3);
5148	if (RT_SUCCESS(rc))
5149	{
5150	# if PGM_GST_TYPE == PGM_TYPE_32BIT
5151	# ifdef IN_RING3
5152	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
5153	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
5154	# else
5155	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
5156	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
5157	# endif
5158
5159	# elif PGM_GST_TYPE == PGM_TYPE_PAE
5160	# ifdef IN_RING3
5161	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
5162	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
5163	# else
5164	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
5165	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
5166	# endif
5167
5168	X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
5169	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5170	/*
5171	* When EPT is enabled by the nested-hypervisor and the nested-guest is in PAE mode,
5172	* the guest-CPU context would've already been updated with the 4 PAE PDPEs specified
5173	* in the virtual VMCS. The PDPEs can differ from those in guest memory referenced by
5174	* the translated nested-guest CR3. We -MUST- use the PDPEs provided in the virtual VMCS
5175	* rather than those in guest memory.
5176	*
5177	* See Intel spec. 26.3.2.4 "Loading Page-Directory-Pointer-Table Entries".
5178	*/
5179	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
5180	CPUMGetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5181	else
5182	#endif
5183	{
5184	/* Update CPUM with the PAE PDPEs referenced by CR3. */
5185	memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
5186	CPUMSetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5187	}
5188
5189	/*
5190	* Map the 4 PAE PDPEs.
5191	*/
5192	rc = PGMGstMapPaePdpes(pVCpu, &aGstPaePdpes[0]);
5193	if (RT_SUCCESS(rc))
5194	{
5195	# ifdef IN_RING3
5196	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
5197	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5198	# else
5199	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5200	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
5201	# endif
5202	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
5203	}
5204
5205	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
5206	# ifdef IN_RING3
5207	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
5208	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
5209	# else
5210	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
5211	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
5212	# endif
5213	# endif
5214	}
5215	else
5216	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
5217	}
5218	#endif
5219
5220	/*
5221	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
5222	*/
5223	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5224	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5225	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
5226	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
5227	&& PGM_GST_TYPE != PGM_TYPE_PROT))
5228
5229	Assert(!pVM->pgm.s.fNestedPaging);
5230	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5231
5232	/*
5233	* Update the shadow root page as well since that's not fixed.
5234	*/
5235	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5236	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
5237	PPGMPOOLPAGE pNewShwPageCR3;
5238
5239	PGM_LOCK_VOID(pVM);
5240
5241	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5242	if (pPool->cDirtyPages)
5243	pgmPoolResetDirtyPages(pVM);
5244	# endif
5245
5246	Assert(!(GCPhysCR3 >> (GUEST_PAGE_SHIFT + 32))); /** @todo what is this for? */
5247	int const rc2 = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE,
5248	PGM_A20_IS_ENABLED(pVCpu), NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/, &pNewShwPageCR3);
5249	AssertFatalRC(rc2);
5250
5251	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
5252	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
5253
5254	/* Set the current hypervisor CR3. */
5255	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
5256
5257	/* Clean up the old CR3 root. */
5258	if ( pOldShwPageCR3
5259	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
5260	{
5261	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
5262
5263	/* Mark the page as unlocked; allow flushing again. */
5264	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
5265
5266	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
5267	}
5268	PGM_UNLOCK(pVM);
5269	# else
5270	NOREF(GCPhysCR3);
5271	# endif
5272
5273	return rc;
5274	}
5275
5276	/**
5277	* Unmaps the shadow CR3.
5278	*
5279	* @returns VBox status, no specials.
5280	* @param pVCpu The cross context virtual CPU structure.
5281	*/
5282	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
5283	{
5284	LogFlow(("UnmapCR3\n"));
5285
5286	int rc = VINF_SUCCESS;
5287	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5288
5289	/*
5290	* Update guest paging info.
5291	*/
5292	#if PGM_GST_TYPE == PGM_TYPE_32BIT
5293	pVCpu->pgm.s.pGst32BitPdR3 = 0;
5294	pVCpu->pgm.s.pGst32BitPdR0 = 0;
5295
5296	#elif PGM_GST_TYPE == PGM_TYPE_PAE
5297	pVCpu->pgm.s.pGstPaePdptR3 = 0;
5298	pVCpu->pgm.s.pGstPaePdptR0 = 0;
5299	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
5300	{
5301	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
5302	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
5303	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
5304	}
5305
5306	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
5307	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
5308	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
5309
5310	#else /* prot/real mode stub */
5311	/* nothing to do */
5312	#endif
5313
5314	/*
5315	* PAE PDPEs (and CR3) might have been mapped via PGMGstMapPaePdpesAtCr3()
5316	* prior to switching to PAE in pfnMapCr3(), so we need to clear them here.
5317	*/
5318	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5319	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5320	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
5321
5322	/*
5323	* Update shadow paging info.
5324	*/
5325	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5326	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5327	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
5328	# if PGM_GST_TYPE != PGM_TYPE_REAL
5329	Assert(!pVM->pgm.s.fNestedPaging);
5330	# endif
5331	PGM_LOCK_VOID(pVM);
5332
5333	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
5334	{
5335	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5336
5337	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5338	if (pPool->cDirtyPages)
5339	pgmPoolResetDirtyPages(pVM);
5340	# endif
5341
5342	/* Mark the page as unlocked; allow flushing again. */
5343	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
5344
5345	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
5346	pVCpu->pgm.s.pShwPageCR3R3 = 0;
5347	pVCpu->pgm.s.pShwPageCR3R0 = 0;
5348	}
5349
5350	PGM_UNLOCK(pVM);
5351	#endif
5352
5353	return rc;
5354	}
5355

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 101504

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