PGMAllBth.h@ 103917

Last change on this file since 103917 was 103374, checked in by vboxsync, 10 months ago
VMM/PGM,DBGF,GIC: Parfait pointed out some potential NULL pointer use here and there. bugref:3409
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1	/* $Id: PGMAllBth.h 103374 2024-02-14 22:10:00Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
6	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
7	* bird: WTF does this mean these days? Looking at PGMAll.cpp it's
8	*
9	* @remarks This file is one big \#ifdef-orgy!
10	*
11	*/
12
13	/*
14	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
15	*
16	* This file is part of VirtualBox base platform packages, as
17	* available from https://www.virtualbox.org.
18	*
19	* This program is free software; you can redistribute it and/or
20	* modify it under the terms of the GNU General Public License
21	* as published by the Free Software Foundation, in version 3 of the
22	* License.
23	*
24	* This program is distributed in the hope that it will be useful, but
25	* WITHOUT ANY WARRANTY; without even the implied warranty of
26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27	* General Public License for more details.
28	*
29	* You should have received a copy of the GNU General Public License
30	* along with this program; if not, see <https://www.gnu.org/licenses>.
31	*
32	* SPDX-License-Identifier: GPL-3.0-only
33	*/
34
35	#ifdef _MSC_VER
36	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
37	* real/prot-guest+RC mode. */
38	# pragma warning(disable: 4505)
39	#endif
40
41
42	/*********************************************************************************************************************************
43	* Internal Functions *
44	*********************************************************************************************************************************/
45	RT_C_DECLS_BEGIN
46	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
47	#ifndef IN_RING3
48	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken);
49	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
50	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken);
51	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
52	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
53	unsigned iPte, SLATPTE GstSlatPte);
54	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
55	uint32_t uErr, PPGMPTWALKGST pGstWalkAll);
56	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll);
57	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
58	#endif
59	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
60	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
61	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
62	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
63	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
64	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
65	#else
66	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
67	#endif
68	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
69	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage);
70	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
71	#ifdef VBOX_STRICT
72	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
73	#endif
74	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3);
75	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu);
76
77	#ifdef IN_RING3
78	PGM_BTH_DECL(int, Relocate)(PVMCPUCC pVCpu, RTGCPTR offDelta);
79	#endif
80	RT_C_DECLS_END
81
82
83
84
85	/*
86	* Filter out some illegal combinations of guest and shadow paging, so we can
87	* remove redundant checks inside functions.
88	*/
89	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
90	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
91	# error "Invalid combination; PAE guest implies PAE shadow"
92	#endif
93
94	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
95	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \
96	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
97	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
98	#endif
99
100	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
101	&& !( PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
102	\|\| PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE)
103	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
104	#endif
105
106	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
107	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
108	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
109	#endif
110
111
112	/**
113	* Enters the shadow+guest mode.
114	*
115	* @returns VBox status code.
116	* @param pVCpu The cross context virtual CPU structure.
117	* @param GCPhysCR3 The physical address from the CR3 register.
118	*/
119	PGM_BTH_DECL(int, Enter)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
120	{
121	/* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
122	* Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
123	*/
124	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
125	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
126	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
127	&& ( PGM_GST_TYPE == PGM_TYPE_REAL \
128	\|\| PGM_GST_TYPE == PGM_TYPE_PROT))
129
130	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
131
132	Assert(!pVM->pgm.s.fNestedPaging);
133
134	PGM_LOCK_VOID(pVM);
135	/* Note: we only really need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes),
136	* but any calls to GC need a proper shadow page setup as well.
137	*/
138	/* Free the previous root mapping if still active. */
139	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
140	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
141	if (pOldShwPageCR3)
142	{
143	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
144
145	/* Mark the page as unlocked; allow flushing again. */
146	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
147
148	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
149	pVCpu->pgm.s.pShwPageCR3R3 = NIL_RTR3PTR;
150	pVCpu->pgm.s.pShwPageCR3R0 = NIL_RTR0PTR;
151	}
152
153	/* construct a fake address. */
154	GCPhysCR3 = RT_BIT_64(63);
155	PPGMPOOLPAGE pNewShwPageCR3;
156	int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
157	NIL_PGMPOOL_IDX, UINT32_MAX, false /fLockPage/,
158	&pNewShwPageCR3);
159	AssertRCReturn(rc, rc);
160
161	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
162	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
163
164	/* Mark the page as locked; disallow flushing. */
165	pgmPoolLockPage(pPool, pNewShwPageCR3);
166
167	/* Set the current hypervisor CR3. */
168	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
169
170	PGM_UNLOCK(pVM);
171	return rc;
172	#else
173	NOREF(pVCpu); NOREF(GCPhysCR3);
174	return VINF_SUCCESS;
175	#endif
176	}
177
178
179	#ifndef IN_RING3
180
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	/**
183	* Deal with a guest page fault.
184	*
185	* @returns Strict VBox status code.
186	* @retval VINF_EM_RAW_GUEST_TRAP
187	* @retval VINF_EM_RAW_EMULATE_INSTR
188	*
189	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
190	* @param pWalk The guest page table walk result.
191	* @param uErr The error code.
192	*/
193	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPUCC pVCpu, PPGMPTWALK pWalk, RTGCUINT uErr)
194	{
195	/*
196	* Calc the error code for the guest trap.
197	*/
198	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
199	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
200	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
201	if ( pWalk->fRsvdError
202	\|\| pWalk->fBadPhysAddr)
203	{
204	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
205	Assert(!pWalk->fNotPresent);
206	}
207	else if (!pWalk->fNotPresent)
208	uNewErr \|= X86_TRAP_PF_P;
209	TRPMSetErrorCode(pVCpu, uNewErr);
210
211	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pWalk->GCPtr, uErr, pWalk->uLevel));
212	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
213	return VINF_EM_RAW_GUEST_TRAP;
214	}
215	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
216
217
218	#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
219	/**
220	* Deal with a guest page fault.
221	*
222	* The caller has taken the PGM lock.
223	*
224	* @returns Strict VBox status code.
225	*
226	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
227	* @param uErr The error code.
228	* @param pCtx Pointer to the register context for the CPU.
229	* @param pvFault The fault address.
230	* @param pPage The guest page at @a pvFault.
231	* @param pWalk The guest page table walk result.
232	* @param pGstWalk The guest paging-mode specific walk information.
233	* @param pfLockTaken PGM lock taken here or not (out). This is true
234	* when we're called.
235	*/
236	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
237	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
238	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
239	, PPGMPTWALK pWalk
240	, PGSTPTWALK pGstWalk
241	# endif
242	)
243	{
244	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
245	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
246	# endif
247	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
248	VBOXSTRICTRC rcStrict;
249
250	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
251	{
252	/*
253	* Physical page access handler.
254	*/
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	const RTGCPHYS GCPhysFault = pWalk->GCPhys;
257	# else
258	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
259	# endif
260	PPGMPHYSHANDLER pCur;
261	rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysFault, &pCur);
262	if (RT_SUCCESS(rcStrict))
263	{
264	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
265
266	# ifdef PGM_SYNC_N_PAGES
267	/*
268	* If the region is write protected and we got a page not present fault, then sync
269	* the pages. If the fault was caused by a read, then restart the instruction.
270	* In case of write access continue to the GC write handler.
271	*
272	* ASSUMES that there is only one handler per page or that they have similar write properties.
273	*/
274	if ( !(uErr & X86_TRAP_PF_P)
275	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
276	{
277	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
278	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
279	# else
280	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
281	# endif
282	if ( RT_FAILURE(rcStrict)
283	\|\| !(uErr & X86_TRAP_PF_RW)
284	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
285	{
286	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
288	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
289	return rcStrict;
290	}
291	}
292	# endif
293	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
294	/*
295	* If the access was not thru a #PF(RSVD\|...) resync the page.
296	*/
297	if ( !(uErr & X86_TRAP_PF_RSVD)
298	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
299	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
300	&& (pWalk->fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK))
301	== PGM_PTATTRS_W_MASK /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
302	# endif
303	)
304	{
305	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
306	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
307	# else
308	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
309	# endif
310	if ( RT_FAILURE(rcStrict)
311	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
312	{
313	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
314	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
315	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
316	return rcStrict;
317	}
318	}
319	# endif
320
321	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
322	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
323	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
324	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
325	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
326	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
327	else
328	{
329	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
330	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
331	}
332
333	if (pCurType->pfnPfHandler)
334	{
335	STAM_PROFILE_START(&pCur->Stat, h);
336
337	if (pCurType->fKeepPgmLock)
338	{
339	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault,
340	!pCurType->fRing0DevInsIdx ? pCur->uUser
341	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser));
342
343	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
344	}
345	else
346	{
347	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
348	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
349	PGM_UNLOCK(pVM);
350	*pfLockTaken = false;
351
352	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, pvFault, GCPhysFault, uUser);
353
354	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
355	}
356	}
357	else
358	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
359
360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
361	return rcStrict;
362	}
363	AssertMsgReturn(rcStrict == VERR_NOT_FOUND, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)), rcStrict);
364	}
365
366	/*
367	* There is a handled area of the page, but this fault doesn't belong to it.
368	* We must emulate the instruction.
369	*
370	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
371	* we first check if this was a page-not-present fault for a page with only
372	* write access handlers. Restart the instruction if it wasn't a write access.
373	*/
374	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersUnhandled);
375
376	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
377	&& !(uErr & X86_TRAP_PF_P))
378	{
379	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
380	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
381	# else
382	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
383	# endif
384	if ( RT_FAILURE(rcStrict)
385	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
386	\|\| !(uErr & X86_TRAP_PF_RW))
387	{
388	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
389	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
390	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
391	return rcStrict;
392	}
393	}
394
395	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
396	* It's writing to an unhandled part of the LDT page several million times.
397	*/
398	rcStrict = PGMInterpretInstruction(pVCpu, pvFault);
399	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
400	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndUnhandled; });
401	return rcStrict;
402	} /* if any kind of handler */
403	# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
404
405
406	/**
407	* \#PF Handler for raw-mode guest execution.
408	*
409	* @returns VBox status code (appropriate for trap handling and GC return).
410	*
411	* @param pVCpu The cross context virtual CPU structure.
412	* @param uErr The trap error code.
413	* @param pCtx Pointer to the register context for the CPU.
414	* @param pvFault The fault address.
415	* @param pfLockTaken PGM lock taken here or not (out)
416	*/
417	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken)
418	{
419	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
420
421	*pfLockTaken = false;
422
423	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
424	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
425	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
426	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
427	&& PGM_SHW_TYPE != PGM_TYPE_NONE
428	int rc;
429
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	/*
432	* Walk the guest page translation tables and check if it's a guest fault.
433	*/
434	PGMPTWALK Walk;
435	GSTPTWALK GstWalk;
436	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &Walk, &GstWalk);
437	if (RT_FAILURE_NP(rc))
438	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
439
440	/* assert some GstWalk sanity. */
441	# if PGM_GST_TYPE == PGM_TYPE_AMD64
442	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
443	# endif
444	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
445	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
446	# endif
447	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
448	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
449	Assert(Walk.fSucceeded);
450	Assert(Walk.fEffective & PGM_PTATTRS_R_MASK);
451
452	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
453	{
454	if ( ( (uErr & X86_TRAP_PF_RW)
455	&& !(Walk.fEffective & PGM_PTATTRS_W_MASK)
456	&& ( (uErr & X86_TRAP_PF_US)
457	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
458	\|\| ((uErr & X86_TRAP_PF_US) && !(Walk.fEffective & PGM_PTATTRS_US_MASK))
459	\|\| ((uErr & X86_TRAP_PF_ID) && (Walk.fEffective & PGM_PTATTRS_NX_MASK))
460	)
461	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &Walk, uErr));
462	}
463
464	/* Take the big lock now before we update flags. */
465	*pfLockTaken = true;
466	PGM_LOCK_VOID(pVM);
467
468	/*
469	* Set the accessed and dirty flags.
470	*/
471	/** @todo Should probably use cmpxchg logic here as we're potentially racing
472	* other CPUs in SMP configs. (the lock isn't enough, since we take it
473	* after walking and the page tables could be stale already) */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	if (!(GstWalk.Pml4e.u & X86_PML4E_A))
476	{
477	GstWalk.Pml4e.u \|= X86_PML4E_A;
478	GST_ATOMIC_OR(&GstWalk.pPml4e->u, X86_PML4E_A);
479	}
480	if (!(GstWalk.Pdpe.u & X86_PDPE_A))
481	{
482	GstWalk.Pdpe.u \|= X86_PDPE_A;
483	GST_ATOMIC_OR(&GstWalk.pPdpe->u, X86_PDPE_A);
484	}
485	# endif
486	if (Walk.fBigPage)
487	{
488	Assert(GstWalk.Pde.u & X86_PDE_PS);
489	if (uErr & X86_TRAP_PF_RW)
490	{
491	if ((GstWalk.Pde.u & (X86_PDE4M_A \| X86_PDE4M_D)) != (X86_PDE4M_A \| X86_PDE4M_D))
492	{
493	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
494	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A \| X86_PDE4M_D);
495	}
496	}
497	else
498	{
499	if (!(GstWalk.Pde.u & X86_PDE4M_A))
500	{
501	GstWalk.Pde.u \|= X86_PDE4M_A;
502	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE4M_A);
503	}
504	}
505	}
506	else
507	{
508	Assert(!(GstWalk.Pde.u & X86_PDE_PS));
509	if (!(GstWalk.Pde.u & X86_PDE_A))
510	{
511	GstWalk.Pde.u \|= X86_PDE_A;
512	GST_ATOMIC_OR(&GstWalk.pPde->u, X86_PDE_A);
513	}
514
515	if (uErr & X86_TRAP_PF_RW)
516	{
517	# ifdef VBOX_WITH_STATISTICS
518	if (GstWalk.Pte.u & X86_PTE_D)
519	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageAlreadyDirty));
520	else
521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtiedPage));
522	# endif
523	if ((GstWalk.Pte.u & (X86_PTE_A \| X86_PTE_D)) != (X86_PTE_A \| X86_PTE_D))
524	{
525	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
526	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A \| X86_PTE_D);
527	}
528	}
529	else
530	{
531	if (!(GstWalk.Pte.u & X86_PTE_A))
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GST_ATOMIC_OR(&GstWalk.pPte->u, X86_PTE_A);
535	}
536	}
537	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538	}
539	#if 0
540	/* Disabling this since it's not reliable for SMP, see @bugref{10092#c22}. */
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	#endif
544
545	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	PGM_LOCK_VOID(pVM);
551	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
554	/*
555	* If it is a reserved bit fault we know that it is an MMIO (access
556	* handler) related fault and can skip some 200 lines of code.
557	*/
558	if (uErr & X86_TRAP_PF_RSVD)
559	{
560	Assert(uErr & X86_TRAP_PF_P);
561	PPGMPAGE pPage;
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	rc = pgmPhysGetPageEx(pVM, Walk.GCPhys, &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage,
566	pfLockTaken, &Walk, &GstWalk));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
568	# else
569	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
570	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
571	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
572	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
573	# endif
574	AssertRC(rc);
575	PGM_INVL_PG(pVCpu, pvFault);
576	return rc; /* Restart with the corrected entry. */
577	}
578	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
579
580	/*
581	* Fetch the guest PDE, PDPE and PML4E.
582	*/
583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
584	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
585	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
588	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PAE
591	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
592	# else
593	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PX86PDPAE pPDDst;
600	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
602	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
603	# else
604	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
605	# endif
606	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
607
608	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
609	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
610	PEPTPD pPDDst;
611	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
612	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
613	# endif
614	Assert(pPDDst);
615
616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
617	/*
618	* Dirty page handling.
619	*
620	* If we successfully correct the write protection fault due to dirty bit
621	* tracking, then return immediately.
622	*/
623	if (uErr & X86_TRAP_PF_RW) /* write fault? */
624	{
625	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
626	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyBitTracking), a);
628	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
629	{
630	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0
631	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
632	? &pVCpu->pgm.s.Stats.StatRZTrap0eTime2DirtyAndAccessed
633	: &pVCpu->pgm.s.Stats.StatRZTrap0eTime2GuestTrap; });
634	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
635	return VINF_SUCCESS;
636	}
637	#ifdef DEBUG_bird
638	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
639	AssertMsg(Walk.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
640	#endif
641	}
642
643	# if 0 /* rarely useful; leave for debugging. */
644	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
645	# endif
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647
648	/*
649	* A common case is the not-present error caused by lazy page table syncing.
650	*
651	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
652	* here so we can safely assume that the shadow PT is present when calling
653	* SyncPage later.
654	*
655	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
656	* of mapping conflict and defer to SyncCR3 in R3.
657	* (Again, we do NOT support access handlers for non-present guest pages.)
658	*
659	*/
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	Assert(GstWalk.Pde.u & X86_PDE_P);
662	# endif
663	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
664	&& !SHW_PDE_IS_P(pPDDst->a[iPDDst]))
665	{
666	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
668	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
670	# else
671	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
672	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
673	# endif
674	if (RT_SUCCESS(rc))
675	return rc;
676	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
677	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
678	return VINF_PGM_SYNC_CR3;
679	}
680
681	/*
682	* Check if this fault address is flagged for special treatment,
683	* which means we'll have to figure out the physical address and
684	* check flags associated with it.
685	*
686	* ASSUME that we can limit any special access handling to pages
687	* in page tables which the guest believes to be present.
688	*/
689	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
690	RTGCPHYS GCPhys = Walk.GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
691	# else
692	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK);
693	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
694	PPGMPAGE pPage;
695	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
696	if (RT_FAILURE(rc))
697	{
698	/*
699	* When the guest accesses invalid physical memory (e.g. probing
700	* of RAM or accessing a remapped MMIO range), then we'll fall
701	* back to the recompiler to emulate the instruction.
702	*/
703	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
704	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
705	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
706	return VINF_EM_RAW_EMULATE_INSTR;
707	}
708
709	/*
710	* Any handlers for this page?
711	*/
712	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
713	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
714	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken,
715	&Walk, &GstWalk));
716	# else
717	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, pvFault, pPage, pfLockTaken));
718	# endif
719
720	/*
721	* We are here only if page is present in Guest page tables and
722	* trap is not handled by our handlers.
723	*
724	* Check it for page out-of-sync situation.
725	*/
726	if (!(uErr & X86_TRAP_PF_P))
727	{
728	/*
729	* Page is not present in our page tables. Try to sync it!
730	*/
731	if (uErr & X86_TRAP_PF_US)
732	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
733	else /* supervisor */
734	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
735
736	if (PGM_PAGE_IS_BALLOONED(pPage))
737	{
738	/* Emulate reads from ballooned pages as they are not present in
739	our shadow page tables. (Required for e.g. Solaris guests; soft
740	ecc, random nr generator.) */
741	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
742	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
743	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
744	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Ballooned; });
745	return rc;
746	}
747
748	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
749	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
750	# else
751	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
752	# endif
753	if (RT_SUCCESS(rc))
754	{
755	/* The page was successfully synced, return to the guest. */
756	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
757	return VINF_SUCCESS;
758	}
759	}
760	else /* uErr & X86_TRAP_PF_P: */
761	{
762	/*
763	* Write protected pages are made writable when the guest makes the
764	* first write to it. This happens for pages that are shared, write
765	* monitored or not yet allocated.
766	*
767	* We may also end up here when CR0.WP=0 in the guest.
768	*
769	* Also, a side effect of not flushing global PDEs are out of sync
770	* pages due to physical monitored regions, that are no longer valid.
771	* Assume for now it only applies to the read/write flag.
772	*/
773	if (uErr & X86_TRAP_PF_RW)
774	{
775	/*
776	* Check if it is a read-only page.
777	*/
778	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
779	{
780	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
781	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
782	Assert(!PGM_PAGE_IS_ZERO(pPage));
783	# endif
784	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
785	# ifdef PGM_WITH_PAGE_ZEROING_DETECTION
786	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO
787	&& (pvFault & X86_PAGE_OFFSET_MASK) == 0
788	&& pgmHandlePageZeroingCode(pVCpu, pCtx))
789	{
790	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2PageZeroing; });
791	return VINF_SUCCESS;
792	}
793	# endif
794	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
795
796	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
797	if (rc != VINF_SUCCESS)
798	{
799	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
800	return rc;
801	}
802	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
803	return VINF_EM_NO_MEMORY;
804	}
805
806	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
807	/*
808	* Check to see if we need to emulate the instruction if CR0.WP=0.
809	*/
810	if ( !(Walk.fEffective & PGM_PTATTRS_W_MASK)
811	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
812	&& CPUMGetGuestCPL(pVCpu) < 3)
813	{
814	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
815
816	/*
817	* The Netware WP0+RO+US hack.
818	*
819	* Netware sometimes(/always?) runs with WP0. It has been observed doing
820	* excessive write accesses to pages which are mapped with US=1 and RW=0
821	* while WP=0. This causes a lot of exits and extremely slow execution.
822	* To avoid trapping and emulating every write here, we change the shadow
823	* page table entry to map it as US=0 and RW=1 until user mode tries to
824	* access it again (see further below). We count these shadow page table
825	* changes so we can avoid having to clear the page pool every time the WP
826	* bit changes to 1 (see PGMCr0WpEnabled()).
827	*/
828	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
829	if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
830	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
831	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
832	{
833	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, Walk.fBigPage));
834	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, Walk.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
835	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
836	{
837	PGM_INVL_PG(pVCpu, pvFault);
838	pVCpu->pgm.s.cNetwareWp0Hacks++;
839	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsHack; });
840	return rc;
841	}
842	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
843	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
844	}
845	# endif
846
847	/* Interpret the access. */
848	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVCpu, pvFault));
849	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), Walk.fBigPage, !!(Walk.fEffective & PGM_PTATTRS_US_MASK)));
850	if (RT_SUCCESS(rc))
851	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulInRZ);
852	else
853	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eWPEmulToR3);
854	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2WPEmulation; });
855	return rc;
856	}
857	# endif
858	/// @todo count the above case; else
859	if (uErr & X86_TRAP_PF_US)
860	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
861	else /* supervisor */
862	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
863
864	/*
865	* Sync the page.
866	*
867	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
868	* page is not present, which is not true in this case.
869	*/
870	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
871	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
872	# else
873	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
874	# endif
875	if (RT_SUCCESS(rc))
876	{
877	/*
878	* Page was successfully synced, return to guest but invalidate
879	* the TLB first as the page is very likely to be in it.
880	*/
881	# if PGM_SHW_TYPE == PGM_TYPE_EPT
882	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
883	# else
884	PGM_INVL_PG(pVCpu, pvFault);
885	# endif
886	# ifdef VBOX_STRICT
887	PGMPTWALK GstPageWalk;
888	GstPageWalk.GCPhys = RTGCPHYS_MAX;
889	if (!pVM->pgm.s.fNestedPaging)
890	{
891	rc = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
892	AssertMsg(RT_SUCCESS(rc) && ((GstPageWalk.fEffective & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, GstPageWalk.fEffective));
893	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GstPageWalk.GCPhys, GstPageWalk.fEffective));
894	}
895	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
896	uint64_t fPageShw = 0;
897	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
898	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
899	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GstPageWalk.GCPhys, fPageGst, pvFault));
900	# endif
901	# endif /* VBOX_STRICT */
902	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
903	return VINF_SUCCESS;
904	}
905	}
906	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
907	/*
908	* Check for Netware WP0+RO+US hack from above and undo it when user
909	* mode accesses the page again.
910	*/
911	else if ( (Walk.fEffective & (PGM_PTATTRS_W_MASK \| PGM_PTATTRS_US_MASK)) == PGM_PTATTRS_US_MASK
912	&& (Walk.fBigPage \|\| (GstWalk.Pde.u & X86_PDE_RW))
913	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
914	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
915	&& CPUMGetGuestCPL(pVCpu) == 3
916	&& pVM->cCpus == 1
917	)
918	{
919	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
920	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
921	if (RT_SUCCESS(rc))
922	{
923	PGM_INVL_PG(pVCpu, pvFault);
924	pVCpu->pgm.s.cNetwareWp0Hacks--;
925	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2Wp0RoUsUnhack; });
926	return VINF_SUCCESS;
927	}
928	}
929	# endif /* PGM_WITH_PAGING */
930
931	/** @todo else: why are we here? */
932
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
934	/*
935	* Check for VMM page flags vs. Guest page flags consistency.
936	* Currently only for debug purposes.
937	*/
938	if (RT_SUCCESS(rc))
939	{
940	/* Get guest page flags. */
941	PGMPTWALK GstPageWalk;
942	int rc2 = PGMGstGetPage(pVCpu, pvFault, &GstPageWalk);
943	if (RT_SUCCESS(rc2))
944	{
945	uint64_t fPageShw = 0;
946	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
947
948	#if 0
949	/*
950	* Compare page flags.
951	* Note: we have AVL, A, D bits desynced.
952	*/
953	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
954	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
955	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
956	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
957	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
958	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
959	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
960	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
961	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
962	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
963	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
964
965	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
966	01:01:15.625516 00:08:43.268051 Location :
967	e:\vbox\svn\trunk\srcPage flags mismatch!
968	pvFault=fffff801b0d7b000
969	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
970	GCPhys=0000000019b52000
971	fPageShw=0
972	fPageGst=77b0000000000121
973	rc=0
974	#endif
975
976	}
977	else
978	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
979	}
980	else
981	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
982	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
983	}
984
985
986	/*
987	* If we get here it is because something failed above, i.e. most like guru
988	* meditiation time.
989	*/
990	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
991	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pCtx->cs.Sel, pCtx->rip));
992	return rc;
993
994	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE. */
995	NOREF(uErr); NOREF(pCtx); NOREF(pvFault);
996	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
997	return VERR_PGM_NOT_USED_IN_MODE;
998	# endif
999	}
1000
1001
1002	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT)
1003	/**
1004	* Deals with a nested-guest \#PF fault for a guest-physical page with a handler.
1005	*
1006	* @returns Strict VBox status code.
1007	* @param pVCpu The cross context virtual CPU structure.
1008	* @param uErr The error code.
1009	* @param pCtx Pointer to the register context for the CPU.
1010	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1011	* @param pPage The guest page at @a GCPhysNestedFault.
1012	* @param GCPhysFault The guest-physical address of the fault.
1013	* @param pGstWalkAll The guest page walk result.
1014	* @param pfLockTaken Where to store whether the PGM is still held when
1015	* this function completes.
1016	*
1017	* @note The caller has taken the PGM lock.
1018	*/
1019	static VBOXSTRICTRC PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx,
1020	RTGCPHYS GCPhysNestedFault, PPGMPAGE pPage,
1021	RTGCPHYS GCPhysFault, PPGMPTWALKGST pGstWalkAll,
1022	bool *pfLockTaken)
1023	{
1024	# if PGM_GST_TYPE == PGM_TYPE_PROT \
1025	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1026
1027	/** @todo Assert uErr isn't X86_TRAP_PF_RSVD and remove release checks. */
1028	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysFault);
1029	AssertMsgReturn(PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage), ("%RGp %RGp uErr=%u\n", GCPhysNestedFault, GCPhysFault, uErr),
1030	VERR_PGM_HANDLER_IPE_1);
1031
1032	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1033	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1034	RTGCPHYS const GCPhysPage = GCPhysFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1035
1036	/*
1037	* Physical page access handler.
1038	*/
1039	PPGMPHYSHANDLER pCur;
1040	VBOXSTRICTRC rcStrict = pgmHandlerPhysicalLookup(pVM, GCPhysPage, &pCur);
1041	AssertRCReturn(VBOXSTRICTRC_VAL(rcStrict), rcStrict);
1042
1043	PCPGMPHYSHANDLERTYPEINT const pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
1044	Assert(pCurType);
1045
1046	/*
1047	* If the region is write protected and we got a page not present fault, then sync
1048	* the pages. If the fault was caused by a read, then restart the instruction.
1049	* In case of write access continue to the GC write handler.
1050	*/
1051	if ( !(uErr & X86_TRAP_PF_P)
1052	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1053	{
1054	Log7Func(("Syncing Monitored: GCPhysNestedPage=%RGp GCPhysPage=%RGp uErr=%#x\n", GCPhysNestedPage, GCPhysPage, uErr));
1055	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1056	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1057	if ( RT_FAILURE(rcStrict)
1058	\|\| !(uErr & X86_TRAP_PF_RW))
1059	{
1060	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1061	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1062	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1063	return rcStrict;
1064	}
1065	}
1066	else if ( !(uErr & X86_TRAP_PF_RSVD)
1067	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE)
1068	{
1069	/*
1070	* If the access was NOT through an EPT misconfig (i.e. RSVD), sync the page.
1071	* This can happen for the VMX APIC-access page.
1072	*/
1073	Log7Func(("Syncing MMIO: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1074	rcStrict = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /cPages/, uErr, pGstWalkAll);
1075	Assert(rcStrict != VINF_PGM_SYNCPAGE_MODIFIED_PDE);
1076	if (RT_FAILURE(rcStrict))
1077	{
1078	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
1079	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersOutOfSync);
1080	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndPhys; });
1081	return rcStrict;
1082	}
1083	}
1084
1085	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
1086	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
1087	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
1088	GCPhysNestedFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
1089	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
1090	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysWrite);
1091	else
1092	{
1093	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAll);
1094	if (uErr & X86_TRAP_PF_RSVD)
1095	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersPhysAllOpt);
1096	}
1097
1098	if (pCurType->pfnPfHandler)
1099	{
1100	STAM_PROFILE_START(&pCur->Stat, h);
1101	uint64_t const uUser = !pCurType->fRing0DevInsIdx ? pCur->uUser
1102	: (uintptr_t)PDMDeviceRing0IdxToInstance(pVM, pCur->uUser);
1103
1104	if (pCurType->fKeepPgmLock)
1105	{
1106	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1107	STAM_PROFILE_STOP(&pCur->Stat, h);
1108	}
1109	else
1110	{
1111	PGM_UNLOCK(pVM);
1112	*pfLockTaken = false;
1113	rcStrict = pCurType->pfnPfHandler(pVM, pVCpu, uErr, pCtx, GCPhysNestedFault, GCPhysFault, uUser);
1114	STAM_PROFILE_STOP(&pCur->Stat, h); /* no locking needed, entry is unlikely reused before we get here. */
1115	}
1116	}
1117	else
1118	{
1119	AssertMsgFailed(("What's going on here!? Fault falls outside handler range!?\n"));
1120	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
1121	}
1122
1123	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2HndPhys; });
1124	return rcStrict;
1125
1126	# else
1127	RT_NOREF8(pVCpu, uErr, pCtx, GCPhysNestedFault, pPage, GCPhysFault, pGstWalkAll, pfLockTaken);
1128	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1129	return VERR_PGM_NOT_USED_IN_MODE;
1130	# endif
1131	}
1132	# endif /* VBOX_WITH_NESTED_HWVIRT_VMX_EPT */
1133
1134
1135	/**
1136	* Nested \#PF handler for nested-guest hardware-assisted execution using nested
1137	* paging.
1138	*
1139	* @returns VBox status code (appropriate for trap handling and GC return).
1140	* @param pVCpu The cross context virtual CPU structure.
1141	* @param uErr The fault error (X86_TRAP_PF_*).
1142	* @param pCtx Pointer to the register context for the CPU.
1143	* @param GCPhysNestedFault The nested-guest physical address of the fault.
1144	* @param fIsLinearAddrValid Whether translation of a nested-guest linear address
1145	* caused this fault. If @c false, GCPtrNestedFault
1146	* must be 0.
1147	* @param GCPtrNestedFault The nested-guest linear address of this fault.
1148	* @param pWalk The guest page table walk result.
1149	* @param pfLockTaken Where to store whether the PGM lock is still held
1150	* when this function completes.
1151	*/
1152	PGM_BTH_DECL(int, NestedTrap0eHandler)(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNestedFault,
1153	bool fIsLinearAddrValid, RTGCPTR GCPtrNestedFault, PPGMPTWALK pWalk, bool *pfLockTaken)
1154	{
1155	*pfLockTaken = false;
1156	# if defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) \
1157	&& PGM_GST_TYPE == PGM_TYPE_PROT \
1158	&& PGM_SHW_TYPE == PGM_TYPE_EPT
1159
1160	Assert(CPUMIsGuestVmxEptPagingEnabled(pVCpu));
1161	Assert(PGM_A20_IS_ENABLED(pVCpu));
1162
1163	/* We don't support mode-based execute control for EPT yet. */
1164	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
1165	Assert(!(uErr & X86_TRAP_PF_US));
1166
1167	/* Take the big lock now. */
1168	*pfLockTaken = true;
1169	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1170	PGM_LOCK_VOID(pVM);
1171
1172	/*
1173	* Walk the guest EPT tables and check if it's an EPT violation or misconfiguration.
1174	*/
1175	if (fIsLinearAddrValid)
1176	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x GCPtrNestedFault=%RGv\n",
1177	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr, GCPtrNestedFault));
1178	else
1179	Log7Func(("cs:rip=%04x:%#08RX64 GCPhysNestedFault=%RGp uErr=%#x\n",
1180	pCtx->cs.Sel, pCtx->rip, GCPhysNestedFault, uErr));
1181	PGMPTWALKGST GstWalkAll;
1182	int rc = pgmGstSlatWalk(pVCpu, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk, &GstWalkAll);
1183	if (RT_FAILURE(rc))
1184	return rc;
1185
1186	Assert(GstWalkAll.enmType == PGMPTWALKGSTTYPE_EPT);
1187	Assert(pWalk->fSucceeded);
1188	Assert(pWalk->fEffective & (PGM_PTATTRS_EPT_R_MASK \| PGM_PTATTRS_EPT_W_MASK \| PGM_PTATTRS_EPT_X_SUPER_MASK));
1189	Assert(pWalk->fIsSlat);
1190
1191	# ifdef DEBUG_ramshankar
1192	/* Paranoia. */
1193	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_R_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_R_MASK));
1194	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_W_MASK) == RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_W_MASK));
1195	Assert(RT_BOOL(pWalk->fEffective & PGM_PTATTRS_NX_MASK) == !RT_BOOL(pWalk->fEffective & PGM_PTATTRS_EPT_X_SUPER_MASK));
1196	# endif
1197
1198	Log7Func(("SLAT: GCPhysNestedFault=%RGp -> GCPhys=%#RGp\n", GCPhysNestedFault, pWalk->GCPhys));
1199
1200	/*
1201	* Check page-access permissions.
1202	*/
1203	if ( ((uErr & X86_TRAP_PF_RW) && !(pWalk->fEffective & PGM_PTATTRS_W_MASK))
1204	\|\| ((uErr & X86_TRAP_PF_ID) && (pWalk->fEffective & PGM_PTATTRS_NX_MASK)))
1205	{
1206	Log7Func(("Permission failed! GCPtrNested=%RGv GCPhysNested=%RGp uErr=%#x fEffective=%#RX64\n", GCPtrNestedFault,
1207	GCPhysNestedFault, uErr, pWalk->fEffective));
1208	pWalk->fFailed = PGM_WALKFAIL_EPT_VIOLATION;
1209	return VERR_ACCESS_DENIED;
1210	}
1211
1212	PGM_A20_ASSERT_MASKED(pVCpu, pWalk->GCPhys);
1213	RTGCPHYS const GCPhysPage = pWalk->GCPhys & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1214	RTGCPHYS const GCPhysNestedPage = GCPhysNestedFault & ~(RTGCPHYS)GUEST_PAGE_OFFSET_MASK;
1215
1216	/*
1217	* If we were called via an EPT misconfig, it should've already resulted in a nested-guest VM-exit.
1218	*/
1219	AssertMsgReturn(!(uErr & X86_TRAP_PF_RSVD),
1220	("Unexpected EPT misconfig VM-exit. GCPhysPage=%RGp GCPhysNestedPage=%RGp\n", GCPhysPage, GCPhysNestedPage),
1221	VERR_PGM_MAPPING_IPE);
1222
1223	/*
1224	* Fetch and sync the nested-guest EPT page directory pointer.
1225	*/
1226	PEPTPD pEptPd;
1227	rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL /ppPdpt/, &pEptPd, &GstWalkAll);
1228	AssertRCReturn(rc, rc);
1229	Assert(pEptPd);
1230
1231	/*
1232	* A common case is the not-present error caused by lazy page table syncing.
1233	*
1234	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
1235	* here so we can safely assume that the shadow PT is present when calling
1236	* NestedSyncPage later.
1237	*
1238	* NOTE: It's possible we will be syncing the VMX APIC-access page here.
1239	* In that case, we would sync the page but will NOT go ahead with emulating
1240	* the APIC-access VM-exit through IEM. However, once the page is mapped in
1241	* the shadow tables, subsequent APIC-access VM-exits for the nested-guest
1242	* will be triggered by hardware. Maybe calling the IEM #PF handler can be
1243	* considered as an optimization later.
1244	*/
1245	unsigned const iPde = (GCPhysNestedPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1246	if ( !(uErr & X86_TRAP_PF_P)
1247	&& !(pEptPd->a[iPde].u & EPT_PRESENT_MASK))
1248	{
1249	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2SyncPT; });
1250	Log7Func(("NestedSyncPT: Lazy. GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
1251	rc = PGM_BTH_NAME(NestedSyncPT)(pVCpu, GCPhysNestedPage, GCPhysPage, &GstWalkAll);
1252	if (RT_SUCCESS(rc))
1253	return rc;
1254	AssertMsgFailedReturn(("NestedSyncPT: %RGv failed! rc=%Rrc\n", GCPhysNestedPage, rc), VERR_PGM_MAPPING_IPE);
1255	}
1256
1257	/*
1258	* Check if this fault address is flagged for special treatment.
1259	* This handles faults on an MMIO or write-monitored page.
1260	*
1261	* If this happens to be the VMX APIC-access page, we don't treat is as MMIO
1262	* but rather sync it further below (as a regular guest page) which lets
1263	* hardware-assisted execution trigger the APIC-access VM-exits of the
1264	* nested-guest directly.
1265	*/
1266	PPGMPAGE pPage;
1267	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1268	if (RT_FAILURE(rc))
1269	{
1270	/*
1271	* We failed to get the physical page which means it's a reserved/invalid
1272	* page address (not MMIO even). This can typically be observed with
1273	* Microsoft Hyper-V enabled Windows guests. We must fall back to emulating
1274	* the instruction, see @bugref{10318#c7}.
1275	*/
1276	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.StatRZTrap0eHandlersInvalid);
1277	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2InvalidPhys; });
1278	return VINF_EM_RAW_EMULATE_INSTR;
1279	}
1280	/* Check if this is an MMIO page and NOT the VMX APIC-access page. */
1281	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1282	{
1283	Log7Func(("MMIO: Calling NestedTrap0eHandlerDoAccessHandlers for GCPhys %RGp\n", GCPhysPage));
1284	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(NestedTrap0eHandlerDoAccessHandlers)(pVCpu, uErr, pCtx, GCPhysNestedFault,
1285	pPage, pWalk->GCPhys, &GstWalkAll,
1286	pfLockTaken));
1287	}
1288
1289	/*
1290	* We are here only if page is present in nested-guest page tables but the
1291	* trap is not handled by our handlers. Check for page out-of-sync situation.
1292	*/
1293	if (!(uErr & X86_TRAP_PF_P))
1294	{
1295	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
1296	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1297	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
1298
1299	Log7Func(("SyncPage: Not-Present: GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedFault, GCPhysPage));
1300	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, PGM_SYNC_NR_PAGES, uErr, &GstWalkAll);
1301	if (RT_SUCCESS(rc))
1302	{
1303	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSync; });
1304	return VINF_SUCCESS;
1305	}
1306	}
1307	else if (uErr & X86_TRAP_PF_RW)
1308	{
1309	/*
1310	* Write protected pages are made writable when the guest makes the
1311	* first write to it. This happens for pages that are shared, write
1312	* monitored or not yet allocated.
1313	*
1314	* We may also end up here when CR0.WP=0 in the guest.
1315	*
1316	* Also, a side effect of not flushing global PDEs are out of sync
1317	* pages due to physical monitored regions, that are no longer valid.
1318	* Assume for now it only applies to the read/write flag.
1319	*/
1320	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1321	{
1322	/* This is a read-only page. */
1323	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhysPage));
1324	#ifdef PGM_WITH_PAGE_ZEROING_DETECTION
1325	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ZERO
1326	&& (GCPhysNestedFault & X86_PAGE_OFFSET_MASK) == 0
1327	&& pgmHandlePageZeroingCode(pVCpu, pCtx))
1328	{
1329	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2PageZeroing; });
1330	return VINF_SUCCESS;
1331	}
1332	#endif
1333	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2MakeWritable; });
1334
1335	Log7Func(("Calling pgmPhysPageMakeWritable for GCPhysPage=%RGp\n", GCPhysPage));
1336	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1337	if (rc != VINF_SUCCESS)
1338	{
1339	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
1340	return rc;
1341	}
1342	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
1343	return VINF_EM_NO_MEMORY;
1344	}
1345
1346	Assert(!(uErr & X86_TRAP_PF_US)); /* Mode-based execute not supported yet. */
1347	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1348
1349	/*
1350	* Sync the write-protected page.
1351	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1352	* page is not present, which is not true in this case.
1353	*/
1354	Log7Func(("SyncPage: RW: cs:rip=%04x:%#RX64 GCPhysNestedPage=%RGp uErr=%#RX32 GCPhysPage=%RGp WalkGCPhys=%RGp\n",
1355	pCtx->cs.Sel, pCtx->rip, GCPhysNestedPage, (uint32_t)uErr, GCPhysPage, pWalk->GCPhys));
1356	rc = PGM_BTH_NAME(NestedSyncPage)(pVCpu, GCPhysNestedPage, GCPhysPage, 1 /* cPages */, uErr, &GstWalkAll);
1357	if (RT_SUCCESS(rc))
1358	{
1359	HMInvalidatePhysPage(pVM, GCPhysPage);
1360	STAM_STATS({ pVCpu->pgmr0.s.pStatTrap0eAttributionR0 = &pVCpu->pgm.s.Stats.StatRZTrap0eTime2OutOfSyncHndObs; });
1361	return VINF_SUCCESS;
1362	}
1363	}
1364
1365	/*
1366	* If we get here it is because something failed above => guru meditation time?
1367	*/
1368	LogRelMaxFunc(32, ("rc=%Rrc GCPhysNestedFault=%#RGp (%#RGp) uErr=%#RX32 cs:rip=%04x:%08RX64\n",
1369	rc, GCPhysNestedFault, GCPhysPage, (uint32_t)uErr, pCtx->cs.Sel, pCtx->rip));
1370	return VERR_PGM_MAPPING_IPE;
1371
1372	# else /* !VBOX_WITH_NESTED_HWVIRT_VMX_EPT \|\| PGM_GST_TYPE != PGM_TYPE_PROT \|\| PGM_SHW_TYPE != PGM_TYPE_EPT */
1373	RT_NOREF7(pVCpu, uErr, pCtx, GCPhysNestedFault, fIsLinearAddrValid, GCPtrNestedFault, pWalk);
1374	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
1375	return VERR_PGM_NOT_USED_IN_MODE;
1376	# endif
1377	}
1378
1379	#endif /* !IN_RING3 */
1380
1381
1382	/**
1383	* Emulation of the invlpg instruction.
1384	*
1385	*
1386	* @returns VBox status code.
1387	*
1388	* @param pVCpu The cross context virtual CPU structure.
1389	* @param GCPtrPage Page to invalidate.
1390	*
1391	* @remark ASSUMES that the guest is updating before invalidating. This order
1392	* isn't required by the CPU, so this is speculative and could cause
1393	* trouble.
1394	* @remark No TLB shootdown is done on any other VCPU as we assume that
1395	* invlpg emulation is the only reason for calling this function.
1396	* (The guest has to shoot down TLB entries on other CPUs itself)
1397	* Currently true, but keep in mind!
1398	*
1399	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1400	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1401	*/
1402	PGM_BTH_DECL(int, InvalidatePage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
1403	{
1404	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1405	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
1406	&& PGM_SHW_TYPE != PGM_TYPE_NONE
1407	int rc;
1408	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1409	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1410
1411	PGM_LOCK_ASSERT_OWNER(pVM);
1412
1413	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1414
1415	/*
1416	* Get the shadow PD entry and skip out if this PD isn't present.
1417	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1418	*/
1419	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1420	const unsigned iPDDst = (uint32_t)GCPtrPage >> SHW_PD_SHIFT;
1421	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1422	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR_3);
1423
1424	/* Fetch the pgm pool shadow descriptor. */
1425	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1426	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1427	if (!pShwPde)
1428	{
1429	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1430	return VINF_SUCCESS;
1431	}
1432	# else
1433	Assert(pShwPde);
1434	# endif
1435
1436	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1437	const unsigned iPdpt = (uint32_t)GCPtrPage >> X86_PDPT_SHIFT;
1438	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1439
1440	/* If the shadow PDPE isn't present, then skip the invalidate. */
1441	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1442	if (!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1443	# else
1444	if (!(pPdptDst->a[iPdpt].u & X86_PDPE_P))
1445	# endif
1446	{
1447	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1448	PGM_INVL_PG(pVCpu, GCPtrPage);
1449	return VINF_SUCCESS;
1450	}
1451
1452	/* Fetch the pgm pool shadow descriptor. */
1453	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1454	AssertReturn(pShwPde, VERR_PGM_POOL_GET_PAGE_FAILED);
1455
1456	PX86PDPAE pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1457	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1458	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1459
1460	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1461	/* PML4 */
1462	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1463	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1464	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1465	PX86PDPAE pPDDst;
1466	PX86PDPT pPdptDst;
1467	PX86PML4E pPml4eDst;
1468	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1469	if (rc != VINF_SUCCESS)
1470	{
1471	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1472	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1473	PGM_INVL_PG(pVCpu, GCPtrPage);
1474	return VINF_SUCCESS;
1475	}
1476	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1477	Assert(pPDDst);
1478	Assert(pPdptDst->a[iPdpt].u & X86_PDPE_P);
1479
1480	/* Fetch the pgm pool shadow descriptor. */
1481	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1482	Assert(pShwPde);
1483
1484	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1485
1486	const SHWPDE PdeDst = *pPdeDst;
1487	if (!(PdeDst.u & X86_PDE_P))
1488	{
1489	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1490	PGM_INVL_PG(pVCpu, GCPtrPage);
1491	return VINF_SUCCESS;
1492	}
1493
1494	/*
1495	* Get the guest PD entry and calc big page.
1496	*/
1497	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1498	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1499	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
1500	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1501	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1502	unsigned iPDSrc = 0;
1503	# if PGM_GST_TYPE == PGM_TYPE_PAE
1504	X86PDPE PdpeSrcIgn;
1505	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1506	# else /* AMD64 */
1507	PX86PML4E pPml4eSrcIgn;
1508	X86PDPE PdpeSrcIgn;
1509	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1510	# endif
1511	GSTPDE PdeSrc;
1512
1513	if (pPDSrc)
1514	PdeSrc = pPDSrc->a[iPDSrc];
1515	else
1516	PdeSrc.u = 0;
1517	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1518	const bool fWasBigPage = RT_BOOL(PdeDst.u & PGM_PDFLAGS_BIG_PAGE);
1519	const bool fIsBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
1520	if (fWasBigPage != fIsBigPage)
1521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1522
1523	# ifdef IN_RING3
1524	/*
1525	* If a CR3 Sync is pending we may ignore the invalidate page operation
1526	* depending on the kind of sync and if it's a global page or not.
1527	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1528	*/
1529	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1530	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1531	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1532	&& fIsBigPage
1533	&& (PdeSrc.u & X86_PDE4M_G)
1534	)
1535	)
1536	# else
1537	if (VM_FF_IS_ANY_SET(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1538	# endif
1539	{
1540	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePageSkipped));
1541	return VINF_SUCCESS;
1542	}
1543	# endif /* IN_RING3 */
1544
1545	/*
1546	* Deal with the Guest PDE.
1547	*/
1548	rc = VINF_SUCCESS;
1549	if (PdeSrc.u & X86_PDE_P)
1550	{
1551	Assert( (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
1552	&& ((PdeSrc.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW) \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1553	if (!fIsBigPage)
1554	{
1555	/*
1556	* 4KB - page.
1557	*/
1558	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1559	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1560
1561	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1562	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1563	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
1564	# endif
1565	if (pShwPage->GCPhys == GCPhys)
1566	{
1567	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1568	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1569
1570	PGSTPT pPTSrc;
1571	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1572	if (RT_SUCCESS(rc))
1573	{
1574	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1575	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1576	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1577	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1578	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1579	GCPtrPage, PteSrc.u & X86_PTE_P,
1580	(PteSrc.u & PdeSrc.u & X86_PTE_RW),
1581	(PteSrc.u & PdeSrc.u & X86_PTE_US),
1582	(uint64_t)PteSrc.u,
1583	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1584	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1585	}
1586	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1587	PGM_INVL_PG(pVCpu, GCPtrPage);
1588	}
1589	else
1590	{
1591	/*
1592	* The page table address changed.
1593	*/
1594	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1595	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1596	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1597	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1598	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1599	PGM_INVL_VCPU_TLBS(pVCpu);
1600	}
1601	}
1602	else
1603	{
1604	/*
1605	* 2/4MB - page.
1606	*/
1607	/* Before freeing the page, check if anything really changed. */
1608	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1609	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1610	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1611	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1612	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1613	# endif
1614	if ( pShwPage->GCPhys == GCPhys
1615	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1616	{
1617	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1618	/** @todo This test is wrong as it cannot check the G bit!
1619	* FIXME */
1620	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1621	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1622	&& ( (PdeSrc.u & X86_PDE4M_D) /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1623	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1624	{
1625	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1626	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1627	return VINF_SUCCESS;
1628	}
1629	}
1630
1631	/*
1632	* Ok, the page table is present and it's been changed in the guest.
1633	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1634	* We could do this for some flushes in GC too, but we need an algorithm for
1635	* deciding which 4MB pages containing code likely to be executed very soon.
1636	*/
1637	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1638	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1639	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1640	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1641	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1642	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1643	}
1644	}
1645	else
1646	{
1647	/*
1648	* Page directory is not present, mark shadow PDE not present.
1649	*/
1650	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1651	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
1652	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1653	PGM_INVL_PG(pVCpu, GCPtrPage);
1654	}
1655	return rc;
1656
1657	#else /* guest real and protected mode, nested + ept, none. */
1658	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1659	NOREF(pVCpu); NOREF(GCPtrPage);
1660	return VINF_SUCCESS;
1661	#endif
1662	}
1663
1664	#if PGM_SHW_TYPE != PGM_TYPE_NONE
1665
1666	/**
1667	* Update the tracking of shadowed pages.
1668	*
1669	* @param pVCpu The cross context virtual CPU structure.
1670	* @param pShwPage The shadow page.
1671	* @param HCPhys The physical page we is being dereferenced.
1672	* @param iPte Shadow PTE index
1673	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1674	*/
1675	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1676	RTGCPHYS GCPhysPage)
1677	{
1678	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1679
1680	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1681	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1682	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1683
1684	/* Use the hint we retrieved from the cached guest PT. */
1685	if (pShwPage->fDirty)
1686	{
1687	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1688
1689	Assert(pShwPage->cPresent);
1690	Assert(pPool->cPresent);
1691	pShwPage->cPresent--;
1692	pPool->cPresent--;
1693
1694	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1695	AssertRelease(pPhysPage);
1696	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1697	return;
1698	}
1699	# else
1700	NOREF(GCPhysPage);
1701	# endif
1702
1703	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1704	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1705	* 2. write protect all shadowed pages. I.e. implement caching.
1706	*
1707	* 2023-08-24 bird: If we allow the ZeroPg to enter the shadow page tables,
1708	* this becomes a common occurence and we screw up. A better to the above would
1709	* be to have a parallel table that records the guest physical addresses of the
1710	* pages mapped by the shadow page table... For nested page tables,
1711	* we can easily correleate a table entry to a page entry, so it won't be
1712	* needed for those.
1713	*/
1714	# if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1715	/*
1716	* For non-paged guest tables, EPT and nested tables we can figure out the
1717	* physical page corresponding to the entry and dereference it.
1718	* (This ASSUMES that shadow PTs won't be used ever be used out of place.)
1719	*/
1720	if ( pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_PHYS
1721	\|\| pShwPage->enmKind == PGMPOOLKIND_PAE_PT_FOR_PHYS
1722	\|\| pShwPage->enmKind == PGMPOOLKIND_32BIT_PT_FOR_PHYS)
1723	{
1724	RTGCPHYS GCPhysNestedEntry = pShwPage->GCPhys + ((uint32_t)iPte << X86_PAGE_SHIFT);
1725	if (!pShwPage->fA20Enabled)
1726	GCPhysNestedEntry &= ~(uint64_t)RT_BIT_64(20);
1727	PPGMPAGE const pPhysPage = pgmPhysGetPage(pVM, GCPhysNestedEntry);
1728	AssertRelease(pPhysPage);
1729	pgmTrackDerefGCPhys(pVM->pgm.s.CTX_SUFF(pPool), pShwPage, pPhysPage, iPte);
1730	}
1731	else
1732	AssertMsgFailed(("enmKind=%d GCPhys=%RGp\n", pShwPage->enmKind, pShwPage->GCPhys));
1733	# endif
1734
1735	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1736
1737	/*
1738	* Find the guest address.
1739	*/
1740	STAM_PROFILE_START(&pVM->pgm.s.Stats.StatTrackDeref, a);
1741	LogFlow(("SyncPageWorkerTrackDeref(%d,%d): Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n",
1742	PGM_SHW_TYPE, PGM_GST_TYPE, HCPhys, pShwPage->idx));
1743	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1744	pRam;
1745	pRam = pRam->CTX_SUFF(pNext))
1746	{
1747	unsigned iPage = pRam->cb >> GUEST_PAGE_SHIFT;
1748	while (iPage-- > 0)
1749	{
1750	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1751	{
1752	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1753
1754	Assert(pShwPage->cPresent);
1755	Assert(pPool->cPresent);
1756	pShwPage->cPresent--;
1757	pPool->cPresent--;
1758
1759	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1760	STAM_PROFILE_STOP(&pVM->pgm.s.Stats.StatTrackDeref, a);
1761	return;
1762	}
1763	}
1764	}
1765
1766	for (;;)
1767	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1768	}
1769
1770
1771	/**
1772	* Update the tracking of shadowed pages.
1773	*
1774	* @param pVCpu The cross context virtual CPU structure.
1775	* @param pShwPage The shadow page.
1776	* @param u16 The top 16-bit of the pPage->HCPhys.
1777	* @param pPage Pointer to the guest page. this will be modified.
1778	* @param iPTDst The index into the shadow table.
1779	*/
1780	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPUCC pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16,
1781	PPGMPAGE pPage, const unsigned iPTDst)
1782	{
1783	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1784
1785	/*
1786	* Just deal with the simple first time here.
1787	*/
1788	if (!u16)
1789	{
1790	STAM_COUNTER_INC(&pVM->pgm.s.Stats.StatTrackVirgin);
1791	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1792	/* Save the page table index. */
1793	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1794	}
1795	else
1796	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1797
1798	/* write back */
1799	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x pPage=%p\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst, pPage));
1800	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1801
1802	/* update statistics. */
1803	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1804	pShwPage->cPresent++;
1805	if (pShwPage->iFirstPresent > iPTDst)
1806	pShwPage->iFirstPresent = iPTDst;
1807	}
1808
1809
1810	/**
1811	* Modifies a shadow PTE to account for access handlers.
1812	*
1813	* @param pVM The cross context VM structure.
1814	* @param pVCpu The cross context virtual CPU structure.
1815	* @param pPage The page in question.
1816	* @param GCPhysPage The guest-physical address of the page.
1817	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1818	* A (accessed) bit so it can be emulated correctly.
1819	* @param pPteDst The shadow PTE (output). This is temporary storage and
1820	* does not need to be set atomically.
1821	*/
1822	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVMCC pVM, PVMCPUCC pVCpu, PCPGMPAGE pPage, RTGCPHYS GCPhysPage, uint64_t fPteSrc,
1823	PSHWPTE pPteDst)
1824	{
1825	RT_NOREF_PV(pVM); RT_NOREF_PV(fPteSrc); RT_NOREF_PV(pVCpu); RT_NOREF_PV(GCPhysPage);
1826
1827	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1828	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1829	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1830	{
1831	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1832	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1833	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage) \| EPT_E_READ \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
1834	# else
1835	if (fPteSrc & X86_PTE_A)
1836	{
1837	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1838	SHW_PTE_SET_RO(*pPteDst);
1839	}
1840	else
1841	SHW_PTE_SET(*pPteDst, 0);
1842	# endif
1843	}
1844	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1845	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1846	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1847	&& ( BTH_IS_NP_ACTIVE(pVM)
1848	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1849	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1850	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1851	# endif
1852	)
1853	{
1854	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1855	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1856	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1857	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg
1858	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1859	\| EPT_E_WRITE
1860	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1861	\| EPT_E_MEMTYPE_INVALID_3;
1862	# else
1863	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1864	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1865	# endif
1866	}
1867	# endif
1868	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1869	else
1870	{
1871	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1872	SHW_PTE_SET(*pPteDst, 0);
1873	}
1874	/** @todo count these kinds of entries. */
1875	}
1876
1877
1878	/**
1879	* Creates a 4K shadow page for a guest page.
1880	*
1881	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1882	* physical address. The PdeSrc argument only the flags are used. No page
1883	* structured will be mapped in this function.
1884	*
1885	* @param pVCpu The cross context virtual CPU structure.
1886	* @param pPteDst Destination page table entry.
1887	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1888	* Can safely assume that only the flags are being used.
1889	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1890	* @param pShwPage Pointer to the shadow page.
1891	* @param iPTDst The index into the shadow table.
1892	*
1893	* @remark Not used for 2/4MB pages!
1894	*/
1895	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1896	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1897	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1898	# else
1899	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1900	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1901	# endif
1902	{
1903	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1904	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1905
1906	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1907	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1908	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1909
1910	if (pShwPage->fDirty)
1911	{
1912	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1913	PGSTPT pGstPT;
1914
1915	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1916	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1917	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1918	pGstPT->a[iPTDst].u = PteSrc.u;
1919	}
1920	# else
1921	Assert(!pShwPage->fDirty);
1922	# endif
1923
1924	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1925	if ( (PteSrc.u & X86_PTE_P)
1926	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1927	# endif
1928	{
1929	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1930	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1931	# endif
1932	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1933
1934	/*
1935	* Find the ram range.
1936	*/
1937	PPGMPAGE pPage;
1938	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1939	if (RT_SUCCESS(rc))
1940	{
1941	/* Ignore ballooned pages.
1942	Don't return errors or use a fatal assert here as part of a
1943	shadow sync range might included ballooned pages. */
1944	if (PGM_PAGE_IS_BALLOONED(pPage))
1945	{
1946	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1947	return;
1948	}
1949
1950	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1951	/* Make the page writable if necessary. */
1952	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1953	&& ( PGM_PAGE_IS_ZERO(pPage)
1954	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1955	\|\| ( (PteSrc.u & X86_PTE_RW)
1956	# else
1957	\|\| ( 1
1958	# endif
1959	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1960	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1961	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1962	# endif
1963	# ifdef VBOX_WITH_PAGE_SHARING
1964	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1965	# endif
1966	)
1967	)
1968	)
1969	{
1970	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1971	AssertRC(rc);
1972	}
1973	# endif
1974
1975	/*
1976	* Make page table entry.
1977	*/
1978	SHWPTE PteDst;
1979	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1980	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1981	# else
1982	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1983	# endif
1984	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
1985	{
1986	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1987	/*
1988	* If the page or page directory entry is not marked accessed,
1989	* we mark the page not present.
1990	*/
1991	if (!(PteSrc.u & X86_PTE_A) \|\| !(PdeSrc.u & X86_PDE_A))
1992	{
1993	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1994	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,AccessedPage));
1995	SHW_PTE_SET(PteDst, 0);
1996	}
1997	/*
1998	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1999	* when the page is modified.
2000	*/
2001	else if (!(PteSrc.u & X86_PTE_D) && (PdeSrc.u & PteSrc.u & X86_PTE_RW))
2002	{
2003	AssertCompile(X86_PTE_RW == X86_PDE_RW);
2004	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPage));
2005	SHW_PTE_SET(PteDst,
2006	fGstShwPteFlags
2007	\| PGM_PAGE_GET_HCPHYS(pPage)
2008	\| PGM_PTFLAGS_TRACK_DIRTY);
2009	SHW_PTE_SET_RO(PteDst);
2010	}
2011	else
2012	# endif
2013	{
2014	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageSkipped));
2015	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2016	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage)
2017	\| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2018	# else
2019	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
2020	# endif
2021	}
2022
2023	/*
2024	* Make sure only allocated pages are mapped writable.
2025	*/
2026	if ( SHW_PTE_IS_P_RW(PteDst)
2027	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2028	{
2029	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2030	/* Still applies to shared pages. */
2031	Assert(!PGM_PAGE_IS_ZERO(pPage));
2032	# endif
2033	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
2034	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
2035	}
2036	}
2037	else
2038	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhysPage, fGstShwPteFlags, &PteDst);
2039
2040	/*
2041	* Keep user track up to date.
2042	*/
2043	if (SHW_PTE_IS_P(PteDst))
2044	{
2045	if (!SHW_PTE_IS_P(*pPteDst))
2046	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2047	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
2048	{
2049	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
2050	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2051	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2052	}
2053	}
2054	else if (SHW_PTE_IS_P(*pPteDst))
2055	{
2056	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2057	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2058	}
2059
2060	/*
2061	* Update statistics and commit the entry.
2062	*/
2063	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2064	if (!(PteSrc.u & X86_PTE_G))
2065	pShwPage->fSeenNonGlobal = true;
2066	# endif
2067	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2068	return;
2069	}
2070
2071	/** @todo count these three different kinds. */
2072	Log2(("SyncPageWorker: invalid address in Pte\n"));
2073	}
2074	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2075	else if (!(PteSrc.u & X86_PTE_P))
2076	Log2(("SyncPageWorker: page not present in Pte\n"));
2077	else
2078	Log2(("SyncPageWorker: invalid Pte\n"));
2079	# endif
2080
2081	/*
2082	* The page is not present or the PTE is bad. Replace the shadow PTE by
2083	* an empty entry, making sure to keep the user tracking up to date.
2084	*/
2085	if (SHW_PTE_IS_P(*pPteDst))
2086	{
2087	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
2088	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
2089	}
2090	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
2091	}
2092
2093
2094	/**
2095	* Syncs a guest OS page.
2096	*
2097	* There are no conflicts at this point, neither is there any need for
2098	* page table allocations.
2099	*
2100	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
2101	* When called in AMD64 guest mode, the guest PML4E shall be valid.
2102	*
2103	* @returns VBox status code.
2104	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
2105	* @param pVCpu The cross context virtual CPU structure.
2106	* @param PdeSrc Page directory entry of the guest.
2107	* @param GCPtrPage Guest context page address.
2108	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2109	* @param uErr Fault error (X86_TRAP_PF_*).
2110	*/
2111	static int PGM_BTH_NAME(SyncPage)(PVMCPUCC pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
2112	{
2113	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2114	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2115	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
2116	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
2117
2118	PGM_LOCK_ASSERT_OWNER(pVM);
2119
2120	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2121	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2122	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2123	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
2124
2125	/*
2126	* Assert preconditions.
2127	*/
2128	Assert(PdeSrc.u & X86_PDE_P);
2129	Assert(cPages);
2130	# if 0 /* rarely useful; leave for debugging. */
2131	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
2132	# endif
2133
2134	/*
2135	* Get the shadow PDE, find the shadow page table in the pool.
2136	*/
2137	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2138	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2139	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2140	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR_3);
2141
2142	/* Fetch the pgm pool shadow descriptor. */
2143	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2144	Assert(pShwPde);
2145
2146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2147	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2148	PPGMPOOLPAGE pShwPde = NULL;
2149	PX86PDPAE pPDDst;
2150
2151	/* Fetch the pgm pool shadow descriptor. */
2152	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2153	AssertRCSuccessReturn(rc2, rc2);
2154	Assert(pShwPde);
2155
2156	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2157	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2158
2159	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2160	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2161	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2162	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2163	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2164
2165	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2166	AssertRCSuccessReturn(rc2, rc2);
2167	Assert(pPDDst && pPdptDst);
2168	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
2169	# endif
2170	SHWPDE PdeDst = *pPdeDst;
2171
2172	/*
2173	* - In the guest SMP case we could have blocked while another VCPU reused
2174	* this page table.
2175	* - With W7-64 we may also take this path when the A bit is cleared on
2176	* higher level tables (PDPE/PML4E). The guest does not invalidate the
2177	* relevant TLB entries. If we're write monitoring any page mapped by
2178	* the modified entry, we may end up here with a "stale" TLB entry.
2179	*/
2180	if (!(PdeDst.u & X86_PDE_P))
2181	{
2182	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2183	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
2184	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2185	if (uErr & X86_TRAP_PF_P)
2186	PGM_INVL_PG(pVCpu, GCPtrPage);
2187	return VINF_SUCCESS; /* force the instruction to be executed again. */
2188	}
2189
2190	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2191	Assert(pShwPage);
2192
2193	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2194	/* Fetch the pgm pool shadow descriptor. */
2195	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2196	Assert(pShwPde);
2197	# endif
2198
2199	/*
2200	* Check that the page is present and that the shadow PDE isn't out of sync.
2201	*/
2202	const bool fBigPage = (PdeSrc.u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu);
2203	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2204	RTGCPHYS GCPhys;
2205	if (!fBigPage)
2206	{
2207	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2208	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2209	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2210	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
2211	# endif
2212	}
2213	else
2214	{
2215	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2216	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2217	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2218	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2219	# endif
2220	}
2221	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2222	if ( fPdeValid
2223	&& pShwPage->GCPhys == GCPhys
2224	&& (PdeSrc.u & X86_PDE_P)
2225	&& (PdeSrc.u & X86_PDE_US) == (PdeDst.u & X86_PDE_US)
2226	&& ((PdeSrc.u & X86_PDE_RW) == (PdeDst.u & X86_PDE_RW) \|\| !(PdeDst.u & X86_PDE_RW))
2227	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2228	&& ((PdeSrc.u & X86_PDE_PAE_NX) == (PdeDst.u & X86_PDE_PAE_NX) \|\| !GST_IS_NX_ACTIVE(pVCpu))
2229	# endif
2230	)
2231	{
2232	/*
2233	* Check that the PDE is marked accessed already.
2234	* Since we set the accessed bit before getting here on a #PF, this
2235	* check is only meant for dealing with non-#PF'ing paths.
2236	*/
2237	if (PdeSrc.u & X86_PDE_A)
2238	{
2239	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2240	if (!fBigPage)
2241	{
2242	/*
2243	* 4KB Page - Map the guest page table.
2244	*/
2245	PGSTPT pPTSrc;
2246	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2247	if (RT_SUCCESS(rc))
2248	{
2249	# ifdef PGM_SYNC_N_PAGES
2250	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2251	if ( cPages > 1
2252	&& !(uErr & X86_TRAP_PF_P)
2253	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2254	{
2255	/*
2256	* This code path is currently only taken when the caller is PGMTrap0eHandler
2257	* for non-present pages!
2258	*
2259	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2260	* deal with locality.
2261	*/
2262	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2263	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2264	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2265	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2266	# else
2267	const unsigned offPTSrc = 0;
2268	# endif
2269	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2270	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2271	iPTDst = 0;
2272	else
2273	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2274
2275	for (; iPTDst < iPTDstEnd; iPTDst++)
2276	{
2277	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2278
2279	if ( (pPteSrc->u & X86_PTE_P)
2280	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2281	{
2282	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT))
2283	\| ((offPTSrc + iPTDst) << GUEST_PAGE_SHIFT);
2284	NOREF(GCPtrCurPage);
2285	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2286	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2287	GCPtrCurPage, pPteSrc->u & X86_PTE_P,
2288	!!(pPteSrc->u & PdeSrc.u & X86_PTE_RW),
2289	!!(pPteSrc->u & PdeSrc.u & X86_PTE_US),
2290	(uint64_t)pPteSrc->u,
2291	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2292	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2293	}
2294	}
2295	}
2296	else
2297	# endif /* PGM_SYNC_N_PAGES */
2298	{
2299	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2300	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2301	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2302	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2303	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2304	GCPtrPage, PteSrc.u & X86_PTE_P,
2305	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
2306	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
2307	(uint64_t)PteSrc.u,
2308	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2309	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2310	}
2311	}
2312	else /* MMIO or invalid page: emulated in #PF handler. */
2313	{
2314	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2315	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2316	}
2317	}
2318	else
2319	{
2320	/*
2321	* 4/2MB page - lazy syncing shadow 4K pages.
2322	* (There are many causes of getting here, it's no longer only CSAM.)
2323	*/
2324	/* Calculate the GC physical address of this 4KB shadow page. */
2325	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2326	/* Find ram range. */
2327	PPGMPAGE pPage;
2328	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2329	if (RT_SUCCESS(rc))
2330	{
2331	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2332
2333	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2334	/* Try to make the page writable if necessary. */
2335	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2336	&& ( PGM_PAGE_IS_ZERO(pPage)
2337	\|\| ( (PdeSrc.u & X86_PDE_RW)
2338	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2339	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2340	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2341	# endif
2342	# ifdef VBOX_WITH_PAGE_SHARING
2343	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2344	# endif
2345	)
2346	)
2347	)
2348	{
2349	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2350	AssertRC(rc);
2351	}
2352	# endif
2353
2354	/*
2355	* Make shadow PTE entry.
2356	*/
2357	SHWPTE PteDst;
2358	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2359	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2360	else
2361	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2362
2363	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2364	if ( SHW_PTE_IS_P(PteDst)
2365	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2366	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2367
2368	/* Make sure only allocated pages are mapped writable. */
2369	if ( SHW_PTE_IS_P_RW(PteDst)
2370	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2371	{
2372	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2373	/* Still applies to shared pages. */
2374	Assert(!PGM_PAGE_IS_ZERO(pPage));
2375	# endif
2376	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2377	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2378	}
2379
2380	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2381
2382	/*
2383	* If the page is not flagged as dirty and is writable, then make it read-only
2384	* at PD level, so we can set the dirty bit when the page is modified.
2385	*
2386	* ASSUMES that page access handlers are implemented on page table entry level.
2387	* Thus we will first catch the dirty access and set PDE.D and restart. If
2388	* there is an access handler, we'll trap again and let it work on the problem.
2389	*/
2390	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2391	* As for invlpg, it simply frees the whole shadow PT.
2392	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2393	if ((PdeSrc.u & (X86_PDE4M_D \| X86_PDE_RW)) == X86_PDE_RW)
2394	{
2395	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
2396	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2397	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
2398	}
2399	else
2400	{
2401	PdeDst.u &= ~(SHWUINT)(PGM_PDFLAGS_TRACK_DIRTY \| X86_PDE_RW);
2402	PdeDst.u \|= PdeSrc.u & X86_PDE_RW;
2403	}
2404	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
2405	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2406	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US),
2407	(uint64_t)PdeSrc.u, GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2408	}
2409	else
2410	{
2411	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2412	/** @todo must wipe the shadow page table entry in this
2413	* case. */
2414	}
2415	}
2416	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2417	return VINF_SUCCESS;
2418	}
2419
2420	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDNAs));
2421	}
2422	else if (fPdeValid)
2423	{
2424	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2425	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2426	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2427	}
2428	else
2429	{
2430	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2431	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2432	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2433	}
2434
2435	/*
2436	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2437	* Yea, I'm lazy.
2438	*/
2439	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2440	SHW_PDE_ATOMIC_SET(*pPdeDst, 0);
2441
2442	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2443	PGM_INVL_VCPU_TLBS(pVCpu);
2444	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2445
2446
2447	# elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2448	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
2449	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2450	NOREF(PdeSrc);
2451
2452	# ifdef PGM_SYNC_N_PAGES
2453	/*
2454	* Get the shadow PDE, find the shadow page table in the pool.
2455	*/
2456	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2457	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2458
2459	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2460	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2461
2462	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2463	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2464	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2465	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2466	X86PDEPAE PdeDst;
2467	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2468
2469	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2470	AssertRCSuccessReturn(rc, rc);
2471	Assert(pPDDst && pPdptDst);
2472	PdeDst = pPDDst->a[iPDDst];
2473
2474	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2475	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2476	PEPTPD pPDDst;
2477	EPTPDE PdeDst;
2478
2479	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2480	if (rc != VINF_SUCCESS)
2481	{
2482	AssertRC(rc);
2483	return rc;
2484	}
2485	Assert(pPDDst);
2486	PdeDst = pPDDst->a[iPDDst];
2487	# endif
2488	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2489	if (!SHW_PDE_IS_P(PdeDst))
2490	{
2491	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2492	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2493	return VINF_SUCCESS; /* force the instruction to be executed again. */
2494	}
2495
2496	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2497	if (SHW_PDE_IS_BIG(PdeDst))
2498	{
2499	Assert(pVM->pgm.s.fNestedPaging);
2500	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2501	return VINF_SUCCESS;
2502	}
2503
2504	/* Mask away the page offset. */
2505	GCPtrPage &= ~((RTGCPTR)0xfff);
2506
2507	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2508	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2509
2510	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2511	if ( cPages > 1
2512	&& !(uErr & X86_TRAP_PF_P)
2513	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2514	{
2515	/*
2516	* This code path is currently only taken when the caller is PGMTrap0eHandler
2517	* for non-present pages!
2518	*
2519	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2520	* deal with locality.
2521	*/
2522	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2523	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2524	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2525	iPTDst = 0;
2526	else
2527	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2528	for (; iPTDst < iPTDstEnd; iPTDst++)
2529	{
2530	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2531	{
2532	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2533	\| (iPTDst << GUEST_PAGE_SHIFT));
2534
2535	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2536	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2537	GCPtrCurPage,
2538	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2539	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2540
2541	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2542	break;
2543	}
2544	else
2545	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n",
2546	(GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << GUEST_PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2547	}
2548	}
2549	else
2550	# endif /* PGM_SYNC_N_PAGES */
2551	{
2552	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2553	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2554	\| (iPTDst << GUEST_PAGE_SHIFT));
2555
2556	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2557
2558	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2559	GCPtrPage,
2560	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2561	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2562	}
2563	return VINF_SUCCESS;
2564
2565	# else
2566	NOREF(PdeSrc);
2567	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2568	return VERR_PGM_NOT_USED_IN_MODE;
2569	# endif
2570	}
2571
2572	#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
2573
2574	#if !defined(IN_RING3) && defined(VBOX_WITH_NESTED_HWVIRT_VMX_EPT) && PGM_SHW_TYPE == PGM_TYPE_EPT
2575
2576	/**
2577	* Sync a shadow page for a nested-guest page.
2578	*
2579	* @param pVCpu The cross context virtual CPU structure.
2580	* @param pPte The shadow page table entry.
2581	* @param GCPhysPage The guest-physical address of the page.
2582	* @param pShwPage The shadow page of the page table.
2583	* @param iPte The index of the page table entry.
2584	* @param pGstSlatPte The guest SLAT page table entry.
2585	*
2586	* @note Not to be used for 2/4MB pages!
2587	*/
2588	static void PGM_BTH_NAME(NestedSyncPageWorker)(PVMCPUCC pVCpu, PSHWPTE pPte, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage,
2589	unsigned iPte, SLATPTE GstSlatPte)
2590	{
2591	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2592	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
2593	Assert(!pShwPage->fDirty);
2594	Assert(pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT);
2595	AssertMsg(!(GstSlatPte.u & EPT_E_LEAF), ("Large page unexpected: %RX64\n", GstSlatPte.u));
2596	AssertMsg((GstSlatPte.u & EPT_PTE_PG_MASK) == GCPhysPage,
2597	("PTE address mismatch. GCPhysPage=%RGp Pte=%RX64\n", GCPhysPage, GstSlatPte.u & EPT_PTE_PG_MASK));
2598
2599	/*
2600	* Find the ram range.
2601	*/
2602	PPGMPAGE pPage;
2603	int rc = pgmPhysGetPageEx(pVCpu->CTX_SUFF(pVM), GCPhysPage, &pPage);
2604	if (RT_SUCCESS(rc))
2605	{ /* likely */ }
2606	else
2607	{
2608	/*
2609	* This is a RAM hole/invalid/reserved address (not MMIO).
2610	* Nested Microsoft Hyper-V maps addresses like 0xf0220000 as RW WB memory.
2611	* Shadow a not-present page similar to MMIO, see @bugref{10318#c7}.
2612	*/
2613	Assert(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS);
2614	if (SHW_PTE_IS_P(*pPte))
2615	{
2616	Log2(("NestedSyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2617	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2618	}
2619	Log7Func(("RAM hole/reserved %RGp -> ShwPte=0\n", GCPhysPage));
2620	SHW_PTE_ATOMIC_SET(*pPte, 0);
2621	return;
2622	}
2623
2624	Assert(!PGM_PAGE_IS_BALLOONED(pPage));
2625
2626	/*
2627	* Make page table entry.
2628	*/
2629	SHWPTE Pte;
2630	uint64_t const fGstShwPteFlags = (GstSlatPte.u & pVCpu->pgm.s.fGstEptShadowedPteMask)
2631	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2632	if (!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \|\| PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
2633	{
2634	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2635	/* If it's the zero page or write to an unallocated page, allocate it to make it writable. */
2636	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2637	&& ( PGM_PAGE_IS_ZERO(pPage)
2638	\|\| ( (GstSlatPte.u & EPT_E_WRITE)
2639	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2640	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2641	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2642	# endif
2643	# ifdef VBOX_WITH_PAGE_SHARING
2644	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2645	# endif
2646	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_BALLOONED
2647	)
2648	)
2649	)
2650	{
2651	rc = pgmPhysPageMakeWritable(pVCpu->CTX_SUFF(pVM), pPage, GCPhysPage);
2652	AssertRC(rc);
2653	Log7Func(("made writable (%R[pgmpage]) at %RGp\n", pPage, GCPhysPage));
2654	}
2655	# endif
2656	/** @todo access bit. */
2657	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| fGstShwPteFlags;
2658	Log7Func(("regular page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2659
2660	/* Make sure only allocated pages are mapped writable. */
2661	if ( (fGstShwPteFlags & EPT_E_WRITE)
2662	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2663	{
2664	Pte.u &= ~EPT_E_WRITE;
2665	Log7Func(("write-protecting page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2666	}
2667	}
2668	else if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2669	{
2670	/** @todo access bit. */
2671	Pte.u = PGM_PAGE_GET_HCPHYS(pPage) \| (fGstShwPteFlags & ~EPT_E_WRITE);
2672	Log7Func(("monitored page (%R[pgmpage]) at %RGp -> %RX64\n", pPage, GCPhysPage, Pte.u));
2673	}
2674	else
2675	{
2676	/** @todo Do MMIO optimizations here too? */
2677	Log7Func(("mmio/all page (%R[pgmpage]) at %RGp -> 0\n", pPage, GCPhysPage));
2678	Pte.u = 0;
2679	}
2680
2681	/* Make sure only allocated pages are mapped writable. */
2682	Assert(!SHW_PTE_IS_P_RW(Pte) \|\| PGM_PAGE_IS_ALLOCATED(pPage));
2683
2684	/*
2685	* Keep user track up to date.
2686	*/
2687	if (SHW_PTE_IS_P(Pte))
2688	{
2689	if (!SHW_PTE_IS_P(*pPte))
2690	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2691	else if (SHW_PTE_GET_HCPHYS(*pPte) != SHW_PTE_GET_HCPHYS(Pte))
2692	{
2693	Log2(("NestedSyncPageWorker: deref! pPte=%RX64 Pte=%RX64\n", SHW_PTE_LOG64(pPte), SHW_PTE_LOG64(Pte)));
2694	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2695	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPte);
2696	}
2697	}
2698	else if (SHW_PTE_IS_P(*pPte))
2699	{
2700	Log2(("NestedSyncPageWorker: deref! pPte=%RX64\n", SHW_PTE_LOG64(pPte)));
2701	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPte), iPte, NIL_RTGCPHYS);
2702	}
2703
2704	/*
2705	* Commit the entry.
2706	*/
2707	SHW_PTE_ATOMIC_SET2(*pPte, Pte);
2708	return;
2709	}
2710
2711
2712	/**
2713	* Syncs a nested-guest page.
2714	*
2715	* There are no conflicts at this point, neither is there any need for
2716	* page table allocations.
2717	*
2718	* @returns VBox status code.
2719	* @param pVCpu The cross context virtual CPU structure.
2720	* @param GCPhysNestedPage The nested-guest physical address of the page being
2721	* synced.
2722	* @param GCPhysPage The guest-physical address of the page being synced.
2723	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
2724	* @param uErr The page fault error (X86_TRAP_PF_XXX).
2725	* @param pGstWalkAll The guest page table walk result.
2726	*/
2727	static int PGM_BTH_NAME(NestedSyncPage)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, unsigned cPages,
2728	uint32_t uErr, PPGMPTWALKGST pGstWalkAll)
2729	{
2730	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2731	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2732	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2733
2734	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2735	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2736	Log7Func(("GCPhysNestedPage=%RGv GCPhysPage=%RGp cPages=%u uErr=%#x\n", GCPhysNestedPage, GCPhysPage, cPages, uErr));
2737	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages);
2738
2739	PGM_LOCK_ASSERT_OWNER(pVM);
2740
2741	/*
2742	* Get the shadow PDE, find the shadow page table in the pool.
2743	*/
2744	unsigned const iPde = ((GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK);
2745	PEPTPD pPd;
2746	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, NULL, &pPd, pGstWalkAll);
2747	if (RT_SUCCESS(rc))
2748	{ /* likely */ }
2749	else
2750	{
2751	Log(("Failed to fetch EPT PD for %RGp (%RGp) rc=%Rrc\n", GCPhysNestedPage, GCPhysPage, rc));
2752	return rc;
2753	}
2754	Assert(pPd);
2755	EPTPDE Pde = pPd->a[iPde];
2756
2757	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2758	if (!SHW_PDE_IS_P(Pde))
2759	{
2760	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)Pde.u));
2761	Log7Func(("CPU%d: SyncPage: Pde at %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2762	return VINF_SUCCESS; /* force the instruction to be executed again. */
2763	}
2764
2765	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2766	if (SHW_PDE_IS_BIG(Pde))
2767	{
2768	Log7Func(("CPU%d: SyncPage: %RGp changed behind our back!\n", pVCpu->idCpu, GCPhysNestedPage));
2769	return VINF_SUCCESS;
2770	}
2771
2772	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, Pde.u & EPT_PDE_PG_MASK);
2773	PEPTPT pPt = (PEPTPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2774
2775	/*
2776	* If we've shadowed a guest EPT PDE that maps a 2M page using a 4K table,
2777	* then sync the 4K sub-page in the 2M range.
2778	*/
2779	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2780	{
2781	Assert(!SHW_PDE_IS_BIG(Pde));
2782
2783	Assert(pGstWalkAll->u.Ept.Pte.u == 0);
2784	Assert((Pde.u & EPT_PRESENT_MASK) == (pGstWalkAll->u.Ept.Pde.u & EPT_PRESENT_MASK));
2785	Assert(pShwPage->GCPhys == (pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK));
2786
2787	#if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
2788	PPGMPAGE pPage;
2789	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage); AssertRC(rc);
2790	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
2791	Assert(pShwPage->enmKind == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB);
2792	#endif
2793	uint64_t const fGstShwPteFlags = (pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask & ~EPT_E_LEAF)
2794	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2795	SLATPTE GstSlatPte;
2796	GstSlatPte.u = GCPhysPage \| fGstShwPteFlags;
2797
2798	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2799	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, GstSlatPte);
2800	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2801	return VINF_SUCCESS;
2802	}
2803
2804	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2805	# ifdef PGM_SYNC_N_PAGES
2806	if ( cPages > 1
2807	&& !(uErr & X86_TRAP_PF_P)
2808	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
2809	{
2810	/*
2811	* This code path is currently only taken for non-present pages!
2812	*
2813	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2814	* deal with locality.
2815	*/
2816	unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2817	unsigned const iPteEnd = RT_MIN(iPte + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPt->a));
2818	if (iPte < PGM_SYNC_NR_PAGES / 2)
2819	iPte = 0;
2820	else
2821	iPte -= PGM_SYNC_NR_PAGES / 2;
2822	for (; iPte < iPteEnd; iPte++)
2823	{
2824	if (!SHW_PTE_IS_P(pPt->a[iPte]))
2825	{
2826	PGMPTWALKGST GstWalkPt;
2827	PGMPTWALK WalkPt;
2828	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2829	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2830	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt,
2831	&GstWalkPt);
2832	if (RT_SUCCESS(rc))
2833	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], WalkPt.GCPhys, pShwPage, iPte, GstWalkPt.u.Ept.Pte);
2834	else
2835	{
2836	/*
2837	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
2838	* Ensure the shadow tables entry is not-present.
2839	*/
2840	/** @todo Potential room for optimization (explained in NestedSyncPT). */
2841	AssertMsg(!pPt->a[iPte].u, ("%RX64\n", pPt->a[iPte].u));
2842	}
2843	Log7Func(("Many: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2844	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
2845	break;
2846	}
2847	else
2848	{
2849	# ifdef VBOX_STRICT
2850	/* Paranoia - Verify address of the page is what it should be. */
2851	PGMPTWALKGST GstWalkPt;
2852	PGMPTWALK WalkPt;
2853	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
2854	GCPhysNestedPage \|= (iPte << GUEST_PAGE_SHIFT);
2855	rc = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/, &WalkPt, &GstWalkPt);
2856	AssertRC(rc);
2857	PPGMPAGE pPage;
2858	rc = pgmPhysGetPageEx(pVM, WalkPt.GCPhys, &pPage);
2859	AssertRC(rc);
2860	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]),
2861	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp HCPhys=%RHp Shw=%RHp\n",
2862	GCPhysNestedPage, WalkPt.GCPhys, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
2863	# endif
2864	Log7Func(("Many3: %RGp iPte=%u ShwPte=%RX64\n", GCPhysNestedPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2865	}
2866	}
2867	}
2868	else
2869	# endif /* PGM_SYNC_N_PAGES */
2870	{
2871	unsigned const iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2872	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll->u.Ept.Pte);
2873	Log7Func(("4K: GCPhysPage=%RGp iPte=%u ShwPte=%08llx\n", GCPhysPage, iPte, SHW_PTE_LOG64(pPt->a[iPte])));
2874	}
2875
2876	return VINF_SUCCESS;
2877	}
2878
2879
2880	/**
2881	* Sync a shadow page table for a nested-guest page table.
2882	*
2883	* The shadow page table is not present in the shadow PDE.
2884	*
2885	* Handles mapping conflicts.
2886	*
2887	* A precondition for this method is that the shadow PDE is not present. The
2888	* caller must take the PGM lock before checking this and continue to hold it
2889	* when calling this method.
2890	*
2891	* @returns VBox status code.
2892	* @param pVCpu The cross context virtual CPU structure.
2893	* @param GCPhysNestedPage The nested-guest physical page address of the page
2894	* being synced.
2895	* @param GCPhysPage The guest-physical address of the page being synced.
2896	* @param pGstWalkAll The guest page table walk result.
2897	*/
2898	static int PGM_BTH_NAME(NestedSyncPT)(PVMCPUCC pVCpu, RTGCPHYS GCPhysNestedPage, RTGCPHYS GCPhysPage, PPGMPTWALKGST pGstWalkAll)
2899	{
2900	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
2901	Assert(!(GCPhysNestedPage & GUEST_PAGE_OFFSET_MASK));
2902	Assert(!(GCPhysPage & GUEST_PAGE_OFFSET_MASK));
2903
2904	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2905	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2906
2907	Log7Func(("GCPhysNestedPage=%RGp GCPhysPage=%RGp\n", GCPhysNestedPage, GCPhysPage));
2908
2909	PGM_LOCK_ASSERT_OWNER(pVM);
2910	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2911
2912	PEPTPD pPd;
2913	PEPTPDPT pPdpt;
2914	unsigned const iPde = (GCPhysNestedPage >> EPT_PD_SHIFT) & EPT_PD_MASK;
2915	int rc = pgmShwGetNestedEPTPDPtr(pVCpu, GCPhysNestedPage, &pPdpt, &pPd, pGstWalkAll);
2916	if (RT_SUCCESS(rc))
2917	{ /* likely */ }
2918	else
2919	{
2920	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2921	AssertRC(rc);
2922	return rc;
2923	}
2924	Assert(pPd);
2925	PSHWPDE pPde = &pPd->a[iPde];
2926
2927	unsigned const iPdpt = (GCPhysNestedPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2928	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdpt->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2929	Assert(pShwPde->enmKind == PGMPOOLKIND_EPT_PD_FOR_EPT_PD);
2930
2931	SHWPDE Pde = *pPde;
2932	Assert(!SHW_PDE_IS_P(Pde)); /* We're only supposed to call SyncPT on PDE!P and conflicts. */
2933
2934	# ifdef PGM_WITH_LARGE_PAGES
2935	Assert(BTH_IS_NP_ACTIVE(pVM));
2936
2937	/*
2938	* Check if the guest is mapping a 2M page.
2939	*/
2940	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF)
2941	{
2942	PPGMPAGE pPage;
2943	rc = pgmPhysGetPageEx(pVM, GCPhysPage & X86_PDE2M_PAE_PG_MASK, &pPage);
2944	AssertRCReturn(rc, rc);
2945
2946	/* A20 is always enabled in VMX root and non-root operation. */
2947	Assert(PGM_A20_IS_ENABLED(pVCpu));
2948
2949	/*
2950	* Check if we have or can get a 2M backing page here.
2951	*/
2952	RTHCPHYS HCPhys = NIL_RTHCPHYS;
2953	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
2954	{
2955	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
2956	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2957	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2958	}
2959	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
2960	{
2961	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
2962	rc = pgmPhysRecheckLargePage(pVM, GCPhysPage, pPage);
2963	if (RT_SUCCESS(rc))
2964	{
2965	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2966	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2967	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2968	}
2969	}
2970	else if (PGMIsUsingLargePages(pVM))
2971	{
2972	rc = pgmPhysAllocLargePage(pVM, GCPhysPage);
2973	if (RT_SUCCESS(rc))
2974	{
2975	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
2976	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
2977	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
2978	}
2979	}
2980
2981	/*
2982	* If we have a 2M backing page, we can map the guest's 2M page right away.
2983	*/
2984	uint64_t const fGstShwBigPdeFlags = (pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedBigPdeMask)
2985	\| EPT_E_MEMTYPE_WB \| EPT_E_IGNORE_PAT;
2986	if (HCPhys != NIL_RTHCPHYS)
2987	{
2988	Pde.u = HCPhys \| fGstShwBigPdeFlags;
2989	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzBigPdeMask));
2990	Assert(Pde.u & EPT_E_LEAF);
2991	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
2992
2993	/* Add a reference to the first page only. */
2994	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPde);
2995
2996	Assert(PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED);
2997
2998	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
2999	Log7Func(("GstPde=%RGp ShwPde=%RX64 [2M]\n", pGstWalkAll->u.Ept.Pde.u, Pde.u));
3000	return VINF_SUCCESS;
3001	}
3002
3003	/*
3004	* We didn't get a perfect 2M fit. Split the 2M page into 4K pages.
3005	* The page ought not to be marked as a big (2M) page at this point.
3006	*/
3007	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) != PGM_PAGE_PDE_TYPE_PDE);
3008
3009	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3010	PGMPOOLACCESS enmAccess;
3011	{
3012	/*
3013	* Mode-based execute control for EPT not supported.
3014	*
3015	* However, Windows 10 with Hyper-V enabled sets the EPT_E_USER_EXECUTE bit but does
3016	* not enable "mode-based execute control for EPT" in the VT-x secondary VM-execution
3017	* controls. The CPU ignores this bit when the control isn't set. Hence, the assertion
3018	* below is commented out.
3019	*/
3020	/* Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_USER_EXECUTE)); */
3021	Assert(!pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt);
3022	bool const fNoExecute = !(pGstWalkAll->u.Ept.Pde.u & EPT_E_EXECUTE);
3023	if (pGstWalkAll->u.Ept.Pde.u & EPT_E_WRITE)
3024	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3025	else
3026	enmAccess = fNoExecute ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3027	}
3028
3029	/*
3030	* Allocate & map a 4K shadow table to cover the 2M guest page.
3031	*/
3032	PPGMPOOLPAGE pShwPage;
3033	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE2M_PG_MASK;
3034	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_2MB, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3035	pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3036	if ( rc == VINF_SUCCESS
3037	\|\| rc == VINF_PGM_CACHED_PAGE)
3038	{ /* likely */ }
3039	else
3040	{
3041	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3042	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3043	}
3044
3045	PSHWPT pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3046	Assert(pPt);
3047	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3048	if (rc == VINF_SUCCESS)
3049	{
3050	/* The 4K PTEs shall inherit the flags of the 2M PDE page sans the leaf bit. */
3051	uint64_t const fGstShwPteFlags = fGstShwBigPdeFlags & ~EPT_E_LEAF;
3052
3053	/* Sync each 4K pages in the 2M range. */
3054	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++)
3055	{
3056	RTGCPHYS const GCPhysSubPage = GCPhysPt \| (iPte << GUEST_PAGE_SHIFT);
3057	SLATPTE GstSlatPte;
3058	GstSlatPte.u = GCPhysSubPage \| fGstShwPteFlags;
3059	Assert(!(GstSlatPte.u & pVCpu->pgm.s.fGstEptMbzPteMask));
3060	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysSubPage, pShwPage, iPte, GstSlatPte);
3061	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [2M->4K]\n", pGstWalkAll->u.Ept.Pte, pPt->a[iPte].u, iPte));
3062	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3063	break;
3064	}
3065	}
3066	else
3067	{
3068	Assert(rc == VINF_PGM_CACHED_PAGE);
3069	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3070	/* Paranoia - Verify address of each of the subpages are what they should be. */
3071	RTGCPHYS GCPhysSubPage = GCPhysPt;
3072	for (unsigned iPte = 0; iPte < RT_ELEMENTS(pPt->a); iPte++, GCPhysSubPage += GUEST_PAGE_SIZE)
3073	{
3074	PPGMPAGE pSubPage;
3075	rc = pgmPhysGetPageEx(pVM, GCPhysSubPage, &pSubPage);
3076	AssertRC(rc);
3077	AssertMsg( PGM_PAGE_GET_HCPHYS(pSubPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte])
3078	\|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3079	("PGM 2M page and shadow PTE conflict. GCPhysSubPage=%RGp Page=%RHp Shw=%RHp\n",
3080	GCPhysSubPage, PGM_PAGE_GET_HCPHYS(pSubPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3081	}
3082	# endif
3083	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3084	}
3085
3086	/* Save the new PDE. */
3087	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3088	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3089	Assert(!(Pde.u & EPT_E_LEAF));
3090	Assert(!(Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3091	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3092	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3093	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3094	return rc;
3095	}
3096	# endif /* PGM_WITH_LARGE_PAGES */
3097
3098	/*
3099	* Allocate & map the shadow page table.
3100	*/
3101	PSHWPT pPt;
3102	PPGMPOOLPAGE pShwPage;
3103
3104	RTGCPHYS const GCPhysPt = pGstWalkAll->u.Ept.Pde.u & EPT_PDE_PG_MASK;
3105	rc = pgmPoolAlloc(pVM, GCPhysPt, PGMPOOLKIND_EPT_PT_FOR_EPT_PT, PGMPOOLACCESS_DONTCARE,
3106	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPde, false /fLockPage/, &pShwPage);
3107	if ( rc == VINF_SUCCESS
3108	\|\| rc == VINF_PGM_CACHED_PAGE)
3109	{ /* likely */ }
3110	else
3111	{
3112	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3113	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3114	}
3115
3116	pPt = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3117	Assert(pPt);
3118	Assert(PGMPOOL_PAGE_IS_NESTED(pShwPage));
3119
3120	if (rc == VINF_SUCCESS)
3121	{
3122	/* Sync the page we've already translated through SLAT. */
3123	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3124	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPte], GCPhysPage, pShwPage, iPte, pGstWalkAll->u.Ept.Pte);
3125	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3126
3127	/* Sync the rest of page table (expensive but might be cheaper than nested-guest VM-exits in hardware). */
3128	for (unsigned iPteCur = 0; iPteCur < RT_ELEMENTS(pPt->a); iPteCur++)
3129	{
3130	if (iPteCur != iPte)
3131	{
3132	PGMPTWALKGST GstWalkPt;
3133	PGMPTWALK WalkPt;
3134	GCPhysNestedPage &= ~(SHW_PT_MASK << SHW_PT_SHIFT);
3135	GCPhysNestedPage \|= (iPteCur << GUEST_PAGE_SHIFT);
3136	int const rc2 = pgmGstSlatWalk(pVCpu, GCPhysNestedPage, false /fIsLinearAddrValid/, 0 /GCPtrNested/,
3137	&WalkPt, &GstWalkPt);
3138	if (RT_SUCCESS(rc2))
3139	{
3140	PGM_BTH_NAME(NestedSyncPageWorker)(pVCpu, &pPt->a[iPteCur], WalkPt.GCPhys, pShwPage, iPteCur,
3141	GstWalkPt.u.Ept.Pte);
3142	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u\n", GstWalkPt.u.Ept.Pte.u, pPt->a[iPteCur].u, iPteCur));
3143	}
3144	else
3145	{
3146	/*
3147	* This could be MMIO pages reserved by the nested-hypevisor or genuinely not-present pages.
3148	* Ensure the shadow tables entry is not-present.
3149	*/
3150	/** @todo We currently don't configure these to cause EPT misconfigs but rather trap
3151	* them using EPT violations and walk the guest EPT tables to determine
3152	* whether they are EPT misconfigs VM-exits for the nested-hypervisor. We
3153	* could optimize this by using a specific combination of reserved bits
3154	* which we could immediately identify as EPT misconfigs of the
3155	* nested-hypervisor without having to walk its EPT tables. However, tracking
3156	* non-present entries might be tricky...
3157	*/
3158	AssertMsg(!pPt->a[iPteCur].u, ("%RX64\n", pPt->a[iPteCur].u));
3159	}
3160	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3161	break;
3162	}
3163	}
3164	}
3165	else
3166	{
3167	Assert(rc == VINF_PGM_CACHED_PAGE);
3168	# if defined(VBOX_STRICT) && defined(DEBUG_ramshankar)
3169	/* Paranoia - Verify address of the page is what it should be. */
3170	PPGMPAGE pPage;
3171	rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
3172	AssertRC(rc);
3173	const unsigned iPte = (GCPhysNestedPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3174	AssertMsg(PGM_PAGE_GET_HCPHYS(pPage) == SHW_PTE_GET_HCPHYS(pPt->a[iPte]) \|\| !SHW_PTE_IS_P(pPt->a[iPte]),
3175	("PGM page and shadow PTE address conflict. GCPhysNestedPage=%RGp GCPhysPage=%RGp Page=%RHp Shw=%RHp\n",
3176	GCPhysNestedPage, GCPhysPage, PGM_PAGE_GET_HCPHYS(pPage), SHW_PTE_GET_HCPHYS(pPt->a[iPte])));
3177	Log7Func(("GstPte=%RGp ShwPte=%RX64 iPte=%u [cache]\n", pGstWalkAll->u.Ept.Pte.u, pPt->a[iPte].u, iPte));
3178	# endif
3179	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3180	}
3181
3182	/* Save the new PDE. */
3183	uint64_t const fShwPdeFlags = pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptShadowedPdeMask;
3184	Assert(!(pGstWalkAll->u.Ept.Pde.u & EPT_E_LEAF));
3185	Assert(!(pGstWalkAll->u.Ept.Pde.u & pVCpu->pgm.s.fGstEptMbzPdeMask));
3186	Pde.u = pShwPage->Core.Key \| fShwPdeFlags;
3187	SHW_PDE_ATOMIC_SET2(*pPde, Pde);
3188	Log7Func(("GstPde=%RGp ShwPde=%RX64 iPde=%u\n", pGstWalkAll->u.Ept.Pde.u, pPde->u, iPde));
3189
3190	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3191	return rc;
3192	}
3193
3194	#endif /* !IN_RING3 && VBOX_WITH_NESTED_HWVIRT_VMX_EPT && PGM_SHW_TYPE == PGM_TYPE_EPT*/
3195	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
3196
3197	/**
3198	* Handle dirty bit tracking faults.
3199	*
3200	* @returns VBox status code.
3201	* @param pVCpu The cross context virtual CPU structure.
3202	* @param uErr Page fault error code.
3203	* @param pPdeSrc Guest page directory entry.
3204	* @param pPdeDst Shadow page directory entry.
3205	* @param GCPtrPage Guest context page address.
3206	*/
3207	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPUCC pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
3208	RTGCPTR GCPtrPage)
3209	{
3210	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3211	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3212	NOREF(uErr);
3213
3214	PGM_LOCK_ASSERT_OWNER(pVM);
3215
3216	/*
3217	* Handle big page.
3218	*/
3219	if ((pPdeSrc->u & X86_PDE_PS) && GST_IS_PSE_ACTIVE(pVCpu))
3220	{
3221	if ((pPdeDst->u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3222	{
3223	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3224	Assert(pPdeSrc->u & X86_PDE_RW);
3225
3226	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
3227	* fault again and take this path to only invalidate the entry (see below). */
3228	SHWPDE PdeDst = *pPdeDst;
3229	PdeDst.u &= ~(SHWUINT)PGM_PDFLAGS_TRACK_DIRTY;
3230	PdeDst.u \|= X86_PDE_RW \| X86_PDE_A;
3231	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3232	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
3233	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3234	}
3235
3236	# ifdef IN_RING0
3237	/* Check for stale TLB entry; only applies to the SMP guest case. */
3238	if ( pVM->cCpus > 1
3239	&& (pPdeDst->u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_RW \| X86_PDE_A))
3240	{
3241	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3242	if (pShwPage)
3243	{
3244	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3245	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3246	if (SHW_PTE_IS_P_RW(*pPteDst))
3247	{
3248	/* Stale TLB entry. */
3249	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3250	PGM_INVL_PG(pVCpu, GCPtrPage);
3251	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3252	}
3253	}
3254	}
3255	# endif /* IN_RING0 */
3256	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3257	}
3258
3259	/*
3260	* Map the guest page table.
3261	*/
3262	PGSTPT pPTSrc;
3263	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
3264	AssertRCReturn(rc, rc);
3265
3266	if (SHW_PDE_IS_P(*pPdeDst))
3267	{
3268	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
3269	const GSTPTE PteSrc = *pPteSrc;
3270
3271	/*
3272	* Map shadow page table.
3273	*/
3274	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
3275	if (pShwPage)
3276	{
3277	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3278	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
3279	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
3280	{
3281	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
3282	{
3283	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
3284	SHWPTE PteDst = *pPteDst;
3285
3286	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
3287	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageTrap));
3288
3289	Assert(PteSrc.u & X86_PTE_RW);
3290
3291	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
3292	* entry will not harm; write access will simply fault again and
3293	* take this path to only invalidate the entry.
3294	*/
3295	if (RT_LIKELY(pPage))
3296	{
3297	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3298	{
3299	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
3300	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
3301	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
3302	SHW_PTE_SET_RO(PteDst);
3303	}
3304	else
3305	{
3306	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
3307	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
3308	{
3309	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
3310	AssertRC(rc);
3311	}
3312	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
3313	SHW_PTE_SET_RW(PteDst);
3314	else
3315	{
3316	/* Still applies to shared pages. */
3317	Assert(!PGM_PAGE_IS_ZERO(pPage));
3318	SHW_PTE_SET_RO(PteDst);
3319	}
3320	}
3321	}
3322	else
3323	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
3324
3325	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
3326	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
3327	PGM_INVL_PG(pVCpu, GCPtrPage);
3328	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3329	}
3330
3331	# ifdef IN_RING0
3332	/* Check for stale TLB entry; only applies to the SMP guest case. */
3333	if ( pVM->cCpus > 1
3334	&& SHW_PTE_IS_RW(*pPteDst)
3335	&& SHW_PTE_IS_A(*pPteDst))
3336	{
3337	/* Stale TLB entry. */
3338	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageStale));
3339	PGM_INVL_PG(pVCpu, GCPtrPage);
3340	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
3341	}
3342	# endif
3343	}
3344	}
3345	else
3346	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
3347	}
3348
3349	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
3350	}
3351
3352	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
3353
3354	/**
3355	* Sync a shadow page table.
3356	*
3357	* The shadow page table is not present in the shadow PDE.
3358	*
3359	* Handles mapping conflicts.
3360	*
3361	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
3362	* conflict), and Trap0eHandler.
3363	*
3364	* A precondition for this method is that the shadow PDE is not present. The
3365	* caller must take the PGM lock before checking this and continue to hold it
3366	* when calling this method.
3367	*
3368	* @returns VBox status code.
3369	* @param pVCpu The cross context virtual CPU structure.
3370	* @param iPDSrc Page directory index.
3371	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
3372	* Assume this is a temporary mapping.
3373	* @param GCPtrPage GC Pointer of the page that caused the fault
3374	*/
3375	static int PGM_BTH_NAME(SyncPT)(PVMCPUCC pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
3376	{
3377	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
3378	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3379
3380	#if 0 /* rarely useful; leave for debugging. */
3381	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
3382	#endif
3383	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
3384
3385	PGM_LOCK_ASSERT_OWNER(pVM);
3386
3387	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3388	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3389	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3390	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
3391	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3392	int rc = VINF_SUCCESS;
3393
3394	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3395
3396	/*
3397	* Some input validation first.
3398	*/
3399	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
3400
3401	/*
3402	* Get the relevant shadow PDE entry.
3403	*/
3404	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3405	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
3406	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3407	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR_3);
3408
3409	/* Fetch the pgm pool shadow descriptor. */
3410	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3411	Assert(pShwPde);
3412
3413	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3414	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3415	PPGMPOOLPAGE pShwPde = NULL;
3416	PX86PDPAE pPDDst;
3417	PSHWPDE pPdeDst;
3418
3419	/* Fetch the pgm pool shadow descriptor. */
3420	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3421	AssertRCSuccessReturn(rc, rc);
3422	Assert(pShwPde);
3423
3424	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3425	pPdeDst = &pPDDst->a[iPDDst];
3426
3427	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3428	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3429	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3430	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3431	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
3432	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3433	AssertRCSuccessReturn(rc, rc);
3434	Assert(pPDDst);
3435	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3436
3437	# endif
3438	SHWPDE PdeDst = *pPdeDst;
3439
3440	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3441	/* Fetch the pgm pool shadow descriptor. */
3442	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3443	Assert(pShwPde);
3444	# endif
3445
3446	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P.*/
3447
3448	/*
3449	* Sync the page directory entry.
3450	*/
3451	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3452	const bool fPageTable = !(PdeSrc.u & X86_PDE_PS) \|\| !GST_IS_PSE_ACTIVE(pVCpu);
3453	if ( (PdeSrc.u & X86_PDE_P)
3454	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
3455	{
3456	/*
3457	* Allocate & map the page table.
3458	*/
3459	PSHWPT pPTDst;
3460	PPGMPOOLPAGE pShwPage;
3461	RTGCPHYS GCPhys;
3462	if (fPageTable)
3463	{
3464	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
3465	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3466	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3467	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
3468	# endif
3469	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
3470	pShwPde->idx, iPDDst, false /fLockPage/,
3471	&pShwPage);
3472	}
3473	else
3474	{
3475	PGMPOOLACCESS enmAccess;
3476	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
3477	const bool fNoExecute = (PdeSrc.u & X86_PDE_PAE_NX) && GST_IS_NX_ACTIVE(pVCpu);
3478	# else
3479	const bool fNoExecute = false;
3480	# endif
3481
3482	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3483	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3484	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3485	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
3486	# endif
3487	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
3488	if (PdeSrc.u & X86_PDE_US)
3489	{
3490	if (PdeSrc.u & X86_PDE_RW)
3491	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
3492	else
3493	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
3494	}
3495	else
3496	{
3497	if (PdeSrc.u & X86_PDE_RW)
3498	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
3499	else
3500	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
3501	}
3502	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
3503	pShwPde->idx, iPDDst, false /fLockPage/,
3504	&pShwPage);
3505	}
3506	if (rc == VINF_SUCCESS)
3507	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3508	else if (rc == VINF_PGM_CACHED_PAGE)
3509	{
3510	/*
3511	* The PT was cached, just hook it up.
3512	*/
3513	if (fPageTable)
3514	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3515	else
3516	{
3517	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3518	/* (see explanation and assumptions further down.) */
3519	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3520	{
3521	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3522	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3523	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3524	}
3525	}
3526	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3527	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3528	return VINF_SUCCESS;
3529	}
3530	else
3531	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3532	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
3533	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
3534	* irrelevant at this point. */
3535	PdeDst.u &= X86_PDE_AVL_MASK;
3536	PdeDst.u \|= pShwPage->Core.Key;
3537
3538	/*
3539	* Page directory has been accessed (this is a fault situation, remember).
3540	*/
3541	/** @todo
3542	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
3543	* fault situation. What's more, the Trap0eHandler has already set the
3544	* accessed bit. So, it's actually just VerifyAccessSyncPage which
3545	* might need setting the accessed flag.
3546	*
3547	* The best idea is to leave this change to the caller and add an
3548	* assertion that it's set already. */
3549	pPDSrc->a[iPDSrc].u \|= X86_PDE_A;
3550	if (fPageTable)
3551	{
3552	/*
3553	* Page table - 4KB.
3554	*
3555	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
3556	*/
3557	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
3558	GCPtrPage, PdeSrc.u & X86_PTE_P, !!(PdeSrc.u & X86_PTE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u));
3559	PGSTPT pPTSrc;
3560	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
3561	if (RT_SUCCESS(rc))
3562	{
3563	/*
3564	* Start by syncing the page directory entry so CSAM's TLB trick works.
3565	*/
3566	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
3567	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3568	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3569	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3570
3571	/*
3572	* Directory/page user or supervisor privilege: (same goes for read/write)
3573	*
3574	* Directory Page Combined
3575	* U/S U/S U/S
3576	* 0 0 0
3577	* 0 1 0
3578	* 1 0 0
3579	* 1 1 1
3580	*
3581	* Simple AND operation. Table listed for completeness.
3582	*
3583	*/
3584	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4K));
3585	# ifdef PGM_SYNC_N_PAGES
3586	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
3587	unsigned iPTDst = iPTBase;
3588	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
3589	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
3590	iPTDst = 0;
3591	else
3592	iPTDst -= PGM_SYNC_NR_PAGES / 2;
3593	# else /* !PGM_SYNC_N_PAGES */
3594	unsigned iPTDst = 0;
3595	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
3596	# endif /* !PGM_SYNC_N_PAGES */
3597	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
3598	\| ((RTGCPTR)iPTDst << GUEST_PAGE_SHIFT);
3599	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3600	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3601	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
3602	# else
3603	const unsigned offPTSrc = 0;
3604	# endif
3605	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += GUEST_PAGE_SIZE)
3606	{
3607	const unsigned iPTSrc = iPTDst + offPTSrc;
3608	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
3609	if (PteSrc.u & X86_PTE_P)
3610	{
3611	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
3612	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
3613	GCPtrCur,
3614	PteSrc.u & X86_PTE_P,
3615	!!(PteSrc.u & PdeSrc.u & X86_PTE_RW),
3616	!!(PteSrc.u & PdeSrc.u & X86_PTE_US),
3617	(uint64_t)PteSrc.u,
3618	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
3619	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
3620	}
3621	/* else: the page table was cleared by the pool */
3622	} /* for PTEs */
3623	}
3624	}
3625	else
3626	{
3627	/*
3628	* Big page - 2/4MB.
3629	*
3630	* We'll walk the ram range list in parallel and optimize lookups.
3631	* We will only sync one shadow page table at a time.
3632	*/
3633	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT4M));
3634
3635	/**
3636	* @todo It might be more efficient to sync only a part of the 4MB
3637	* page (similar to what we do for 4KB PDs).
3638	*/
3639
3640	/*
3641	* Start by syncing the page directory entry.
3642	*/
3643	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
3644	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
3645
3646	/*
3647	* If the page is not flagged as dirty and is writable, then make it read-only
3648	* at PD level, so we can set the dirty bit when the page is modified.
3649	*
3650	* ASSUMES that page access handlers are implemented on page table entry level.
3651	* Thus we will first catch the dirty access and set PDE.D and restart. If
3652	* there is an access handler, we'll trap again and let it work on the problem.
3653	*/
3654	/** @todo move the above stuff to a section in the PGM documentation. */
3655	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3656	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
3657	{
3658	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,DirtyPageBig));
3659	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3660	PdeDst.u &= ~(SHWUINT)X86_PDE_RW;
3661	}
3662	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3663	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3664
3665	/*
3666	* Fill the shadow page table.
3667	*/
3668	/* Get address and flags from the source PDE. */
3669	SHWPTE PteDstBase;
3670	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3671
3672	/* Loop thru the entries in the shadow PT. */
3673	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3674	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3675	GCPtrPage, PdeSrc.u & X86_PDE_P, !!(PdeSrc.u & X86_PDE_RW), !!(PdeSrc.u & X86_PDE_US), (uint64_t)PdeSrc.u, GCPtr,
3676	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3677	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3678	unsigned iPTDst = 0;
3679	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3680	&& !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3681	{
3682	if (pRam && GCPhys >= pRam->GCPhys)
3683	{
3684	# ifndef PGM_WITH_A20
3685	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT;
3686	# endif
3687	do
3688	{
3689	/* Make shadow PTE. */
3690	# ifdef PGM_WITH_A20
3691	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> GUEST_PAGE_SHIFT];
3692	# else
3693	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3694	# endif
3695	SHWPTE PteDst;
3696
3697	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3698	/* Try to make the page writable if necessary. */
3699	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3700	&& ( PGM_PAGE_IS_ZERO(pPage)
3701	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3702	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3703	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3704	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3705	# endif
3706	# ifdef VBOX_WITH_PAGE_SHARING
3707	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3708	# endif
3709	&& !PGM_PAGE_IS_BALLOONED(pPage))
3710	)
3711	)
3712	{
3713	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3714	AssertRCReturn(rc, rc);
3715	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
3716	break;
3717	}
3718	# endif
3719
3720	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPage))
3721	PGM_BTH_NAME(SyncHandlerPte)(pVM, pVCpu, pPage, GCPhys, SHW_PTE_GET_U(PteDstBase), &PteDst);
3722	else if (PGM_PAGE_IS_BALLOONED(pPage))
3723	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3724	else
3725	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3726
3727	/* Only map writable pages writable. */
3728	if ( SHW_PTE_IS_P_RW(PteDst)
3729	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3730	{
3731	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3732	/* Still applies to shared pages. */
3733	Assert(!PGM_PAGE_IS_ZERO(pPage));
3734	# endif
3735	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3736	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3737	}
3738
3739	if (SHW_PTE_IS_P(PteDst))
3740	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3741
3742	/* commit it (not atomic, new table) */
3743	pPTDst->a[iPTDst] = PteDst;
3744	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3745	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3746	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3747
3748	/* advance */
3749	GCPhys += GUEST_PAGE_SIZE;
3750	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3751	# ifndef PGM_WITH_A20
3752	iHCPage++;
3753	# endif
3754	iPTDst++;
3755	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3756	&& GCPhys <= pRam->GCPhysLast);
3757
3758	/* Advance ram range list. */
3759	while (pRam && GCPhys > pRam->GCPhysLast)
3760	pRam = pRam->CTX_SUFF(pNext);
3761	}
3762	else if (pRam)
3763	{
3764	Log(("Invalid pages at %RGp\n", GCPhys));
3765	do
3766	{
3767	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3768	GCPhys += GUEST_PAGE_SIZE;
3769	iPTDst++;
3770	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3771	&& GCPhys < pRam->GCPhys);
3772	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3773	}
3774	else
3775	{
3776	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3777	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3778	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3779	}
3780	} /* while more PTEs */
3781	} /* 4KB / 4MB */
3782	}
3783	else
3784	AssertRelease(!SHW_PDE_IS_P(PdeDst));
3785
3786	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3787	if (RT_FAILURE(rc))
3788	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
3789	return rc;
3790
3791	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3792	&& !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
3793	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3794	&& PGM_SHW_TYPE != PGM_TYPE_NONE
3795	NOREF(iPDSrc); NOREF(pPDSrc);
3796
3797	STAM_PROFILE_START(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3798
3799	/*
3800	* Validate input a little bit.
3801	*/
3802	int rc = VINF_SUCCESS;
3803	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3804	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3805	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3806	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR_3);
3807
3808	/* Fetch the pgm pool shadow descriptor. */
3809	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3810	Assert(pShwPde);
3811
3812	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3813	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3814	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3815	PX86PDPAE pPDDst;
3816	PSHWPDE pPdeDst;
3817
3818	/* Fetch the pgm pool shadow descriptor. */
3819	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3820	AssertRCSuccessReturn(rc, rc);
3821	Assert(pShwPde);
3822
3823	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3824	pPdeDst = &pPDDst->a[iPDDst];
3825
3826	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3827	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3828	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3829	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3830	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3831	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3832	AssertRCSuccessReturn(rc, rc);
3833	Assert(pPDDst);
3834	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3835
3836	/* Fetch the pgm pool shadow descriptor. */
3837	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3838	Assert(pShwPde);
3839
3840	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3841	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3842	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3843	PEPTPD pPDDst;
3844	PEPTPDPT pPdptDst;
3845
3846	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3847	if (rc != VINF_SUCCESS)
3848	{
3849	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3850	AssertRC(rc);
3851	return rc;
3852	}
3853	Assert(pPDDst);
3854	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3855
3856	/* Fetch the pgm pool shadow descriptor. */
3857	/** @todo r=bird: didn't pgmShwGetEPTPDPtr just do this lookup already? */
3858	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3859	Assert(pShwPde);
3860	# endif
3861	SHWPDE PdeDst = *pPdeDst;
3862
3863	Assert(!SHW_PDE_IS_P(PdeDst)); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3864
3865	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3866	if (BTH_IS_NP_ACTIVE(pVM))
3867	{
3868	Assert(!VM_IS_NEM_ENABLED(pVM));
3869
3870	/* Check if we allocated a big page before for this 2 MB range. */
3871	PPGMPAGE pPage;
3872	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3873	if (RT_SUCCESS(rc))
3874	{
3875	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3876	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3877	{
3878	if (PGM_A20_IS_ENABLED(pVCpu))
3879	{
3880	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3881	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3882	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3883	}
3884	else
3885	{
3886	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3887	pVM->pgm.s.cLargePagesDisabled++;
3888	}
3889	}
3890	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3891	&& PGM_A20_IS_ENABLED(pVCpu))
3892	{
3893	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3894	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3895	if (RT_SUCCESS(rc))
3896	{
3897	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3898	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3899	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3900	}
3901	}
3902	# if !defined(VBOX_WITH_NEW_LAZY_PAGE_ALLOC) && !defined(PGM_WITH_PAGE_ZEROING_DETECTION) /* This code is too aggresive! */
3903	else if ( PGMIsUsingLargePages(pVM)
3904	&& PGM_A20_IS_ENABLED(pVCpu))
3905	{
3906	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3907	if (RT_SUCCESS(rc))
3908	{
3909	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3910	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3911	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3912	}
3913	else
3914	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3915	}
3916	# endif
3917
3918	if (HCPhys != NIL_RTHCPHYS)
3919	{
3920	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3921	PdeDst.u = HCPhys \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE \| EPT_E_LEAF \| EPT_E_IGNORE_PAT \| EPT_E_MEMTYPE_WB
3922	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo do we need this? */;
3923	# else
3924	PdeDst.u = HCPhys \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PS
3925	\| (PdeDst.u & X86_PDE_AVL_MASK) /** @todo PGM_PD_FLAGS? */;
3926	# endif
3927	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3928
3929	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3930	/* Add a reference to the first page only. */
3931	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3932
3933	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3934	return VINF_SUCCESS;
3935	}
3936	}
3937	}
3938	# endif /* defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE */
3939
3940	/*
3941	* Allocate & map the page table.
3942	*/
3943	PSHWPT pPTDst;
3944	PPGMPOOLPAGE pShwPage;
3945	RTGCPHYS GCPhys;
3946
3947	/* Virtual address = physical address */
3948	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3949	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3950	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3951	&pShwPage);
3952	if ( rc == VINF_SUCCESS
3953	\|\| rc == VINF_PGM_CACHED_PAGE)
3954	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3955	else
3956	{
3957	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3958	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3959	}
3960
3961	if (rc == VINF_SUCCESS)
3962	{
3963	/* New page table; fully set it up. */
3964	Assert(pPTDst);
3965
3966	/* Mask away the page offset. */
3967	GCPtrPage &= ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
3968
3969	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3970	{
3971	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3972	\| (iPTDst << GUEST_PAGE_SHIFT));
3973
3974	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3975	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3976	GCPtrCurPage,
3977	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3978	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3979
3980	if (RT_UNLIKELY(VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY)))
3981	break;
3982	}
3983	}
3984	else
3985	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3986
3987	/* Save the new PDE. */
3988	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3989	PdeDst.u = pShwPage->Core.Key \| EPT_E_READ \| EPT_E_WRITE \| EPT_E_EXECUTE
3990	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo do we really need this? */);
3991	# else
3992	PdeDst.u = pShwPage->Core.Key \| X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A
3993	\| (PdeDst.u & X86_PDE_AVL_MASK /** @todo use a PGM_PD_FLAGS define */);
3994	# endif
3995	SHW_PDE_ATOMIC_SET2(*pPdeDst, PdeDst);
3996
3997	STAM_PROFILE_STOP(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPT), a);
3998	if (RT_FAILURE(rc))
3999	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,SyncPTFailed));
4000	return rc;
4001
4002	#else
4003	NOREF(iPDSrc); NOREF(pPDSrc);
4004	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
4005	return VERR_PGM_NOT_USED_IN_MODE;
4006	#endif
4007	}
4008
4009
4010
4011	/**
4012	* Prefetch a page/set of pages.
4013	*
4014	* Typically used to sync commonly used pages before entering raw mode
4015	* after a CR3 reload.
4016	*
4017	* @returns VBox status code.
4018	* @param pVCpu The cross context virtual CPU structure.
4019	* @param GCPtrPage Page to invalidate.
4020	*/
4021	PGM_BTH_DECL(int, PrefetchPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage)
4022	{
4023	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4024	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4025	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4026	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4027	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4028	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4029	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4030	/*
4031	* Check that all Guest levels thru the PDE are present, getting the
4032	* PD and PDE in the processes.
4033	*/
4034	int rc = VINF_SUCCESS;
4035	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4036	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4037	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4038	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4039	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4040	unsigned iPDSrc;
4041	X86PDPE PdpeSrc;
4042	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4043	if (!pPDSrc)
4044	return VINF_SUCCESS; /* not present */
4045	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4046	unsigned iPDSrc;
4047	PX86PML4E pPml4eSrc;
4048	X86PDPE PdpeSrc;
4049	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4050	if (!pPDSrc)
4051	return VINF_SUCCESS; /* not present */
4052	# endif
4053	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4054	# else
4055	PGSTPD pPDSrc = NULL;
4056	const unsigned iPDSrc = 0;
4057	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4058	# endif
4059
4060	if ((PdeSrc.u & (X86_PDE_P \| X86_PDE_A)) == (X86_PDE_P \| X86_PDE_A))
4061	{
4062	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4063	PGM_LOCK_VOID(pVM);
4064
4065	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4066	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
4067	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4068	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4069	PX86PDPAE pPDDst;
4070	X86PDEPAE PdeDst;
4071	# if PGM_GST_TYPE != PGM_TYPE_PAE
4072	X86PDPE PdpeSrc;
4073
4074	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4075	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4076	# endif
4077	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4078	if (rc != VINF_SUCCESS)
4079	{
4080	PGM_UNLOCK(pVM);
4081	AssertRC(rc);
4082	return rc;
4083	}
4084	Assert(pPDDst);
4085	PdeDst = pPDDst->a[iPDDst];
4086
4087	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4088	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4089	PX86PDPAE pPDDst;
4090	X86PDEPAE PdeDst;
4091
4092	# if PGM_GST_TYPE == PGM_TYPE_PROT
4093	/* AMD-V nested paging */
4094	X86PML4E Pml4eSrc;
4095	X86PDPE PdpeSrc;
4096	PX86PML4E pPml4eSrc = &Pml4eSrc;
4097
4098	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4099	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4100	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4101	# endif
4102
4103	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4104	if (rc != VINF_SUCCESS)
4105	{
4106	PGM_UNLOCK(pVM);
4107	AssertRC(rc);
4108	return rc;
4109	}
4110	Assert(pPDDst);
4111	PdeDst = pPDDst->a[iPDDst];
4112	# endif
4113	if (!(PdeDst.u & X86_PDE_P))
4114	{
4115	/** @todo r=bird: This guy will set the A bit on the PDE,
4116	* probably harmless. */
4117	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4118	}
4119	else
4120	{
4121	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
4122	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
4123	* makes no sense to prefetch more than one page.
4124	*/
4125	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4126	if (RT_SUCCESS(rc))
4127	rc = VINF_SUCCESS;
4128	}
4129	PGM_UNLOCK(pVM);
4130	}
4131	return rc;
4132
4133	#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4134	NOREF(pVCpu); NOREF(GCPtrPage);
4135	return VINF_SUCCESS; /* ignore */
4136	#else
4137	AssertCompile(0);
4138	#endif
4139	}
4140
4141
4142
4143
4144	/**
4145	* Syncs a page during a PGMVerifyAccess() call.
4146	*
4147	* @returns VBox status code (informational included).
4148	* @param pVCpu The cross context virtual CPU structure.
4149	* @param GCPtrPage The address of the page to sync.
4150	* @param fPage The effective guest page flags.
4151	* @param uErr The trap error code.
4152	* @remarks This will normally never be called on invalid guest page
4153	* translation entries.
4154	*/
4155	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
4156	{
4157	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4158
4159	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
4160	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
4161
4162	Assert(!pVM->pgm.s.fNestedPaging);
4163	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
4164	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
4165	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
4166	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4167	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
4168	&& !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
4169	&& PGM_SHW_TYPE != PGM_TYPE_NONE
4170
4171	/*
4172	* Get guest PD and index.
4173	*/
4174	/** @todo Performance: We've done all this a jiffy ago in the
4175	* PGMGstGetPage call. */
4176	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4177	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4178	const unsigned iPDSrc = (uint32_t)GCPtrPage >> GST_PD_SHIFT;
4179	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4180
4181	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4182	unsigned iPDSrc = 0;
4183	X86PDPE PdpeSrc;
4184	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
4185	if (RT_UNLIKELY(!pPDSrc))
4186	{
4187	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4188	return VINF_EM_RAW_GUEST_TRAP;
4189	}
4190
4191	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4192	unsigned iPDSrc = 0; /* shut up gcc */
4193	PX86PML4E pPml4eSrc = NULL; /* ditto */
4194	X86PDPE PdpeSrc;
4195	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
4196	if (RT_UNLIKELY(!pPDSrc))
4197	{
4198	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
4199	return VINF_EM_RAW_GUEST_TRAP;
4200	}
4201	# endif
4202
4203	# else /* !PGM_WITH_PAGING */
4204	PGSTPD pPDSrc = NULL;
4205	const unsigned iPDSrc = 0;
4206	# endif /* !PGM_WITH_PAGING */
4207	int rc = VINF_SUCCESS;
4208
4209	PGM_LOCK_VOID(pVM);
4210
4211	/*
4212	* First check if the shadow pd is present.
4213	*/
4214	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4215	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
4216	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR_3);
4217
4218	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4219	PX86PDEPAE pPdeDst;
4220	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4221	PX86PDPAE pPDDst;
4222	# if PGM_GST_TYPE != PGM_TYPE_PAE
4223	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
4224	X86PDPE PdpeSrc;
4225	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
4226	# endif
4227	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
4228	if (rc != VINF_SUCCESS)
4229	{
4230	PGM_UNLOCK(pVM);
4231	AssertRC(rc);
4232	return rc;
4233	}
4234	Assert(pPDDst);
4235	pPdeDst = &pPDDst->a[iPDDst];
4236
4237	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4238	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
4239	PX86PDPAE pPDDst;
4240	PX86PDEPAE pPdeDst;
4241
4242	# if PGM_GST_TYPE == PGM_TYPE_PROT
4243	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
4244	X86PML4E Pml4eSrc;
4245	X86PDPE PdpeSrc;
4246	PX86PML4E pPml4eSrc = &Pml4eSrc;
4247	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
4248	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
4249	# endif
4250
4251	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
4252	if (rc != VINF_SUCCESS)
4253	{
4254	PGM_UNLOCK(pVM);
4255	AssertRC(rc);
4256	return rc;
4257	}
4258	Assert(pPDDst);
4259	pPdeDst = &pPDDst->a[iPDDst];
4260	# endif
4261
4262	if (!(pPdeDst->u & X86_PDE_P))
4263	{
4264	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
4265	if (rc != VINF_SUCCESS)
4266	{
4267	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4268	PGM_UNLOCK(pVM);
4269	AssertRC(rc);
4270	return rc;
4271	}
4272	}
4273
4274	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4275	/* Check for dirty bit fault */
4276	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
4277	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
4278	Log(("PGMVerifyAccess: success (dirty)\n"));
4279	else
4280	# endif
4281	{
4282	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4283	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
4284	# else
4285	GSTPDE const PdeSrc = { X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A }; /* faked so we don't have to #ifdef everything */
4286	# endif
4287
4288	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
4289	if (uErr & X86_TRAP_PF_US)
4290	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncUser));
4291	else /* supervisor */
4292	STAM_COUNTER_INC(&pVCpu->pgm.s.Stats.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
4293
4294	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
4295	if (RT_SUCCESS(rc))
4296	{
4297	/* Page was successfully synced */
4298	Log2(("PGMVerifyAccess: success (sync)\n"));
4299	rc = VINF_SUCCESS;
4300	}
4301	else
4302	{
4303	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
4304	rc = VINF_EM_RAW_GUEST_TRAP;
4305	}
4306	}
4307	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
4308	PGM_UNLOCK(pVM);
4309	return rc;
4310
4311	#else /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4312
4313	AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
4314	return VERR_PGM_NOT_USED_IN_MODE;
4315	#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
4316	}
4317
4318
4319	/**
4320	* Syncs the paging hierarchy starting at CR3.
4321	*
4322	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
4323	* informational status codes.
4324	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
4325	* the VMM into guest context.
4326	* @param pVCpu The cross context virtual CPU structure.
4327	* @param cr0 Guest context CR0 register.
4328	* @param cr3 Guest context CR3 register. Not subjected to the A20
4329	* mask.
4330	* @param cr4 Guest context CR4 register.
4331	* @param fGlobal Including global page directories or not
4332	*/
4333	PGM_BTH_DECL(int, SyncCR3)(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
4334	{
4335	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4336	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
4337
4338	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
4339
4340	#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
4341	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4342	PGM_LOCK_VOID(pVM);
4343	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4344	if (pPool->cDirtyPages)
4345	pgmPoolResetDirtyPages(pVM);
4346	PGM_UNLOCK(pVM);
4347	# endif
4348	#endif /* !NESTED && !EPT */
4349
4350	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4351	/*
4352	* Nested / EPT / None - No work.
4353	*/
4354	return VINF_SUCCESS;
4355
4356	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4357	/*
4358	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
4359	* out the shadow parts when the guest modifies its tables.
4360	*/
4361	return VINF_SUCCESS;
4362
4363	#else /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4364
4365	return VINF_SUCCESS;
4366	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
4367	}
4368
4369
4370
4371
4372	#ifdef VBOX_STRICT
4373
4374	/**
4375	* Checks that the shadow page table is in sync with the guest one.
4376	*
4377	* @returns The number of errors.
4378	* @param pVCpu The cross context virtual CPU structure.
4379	* @param cr3 Guest context CR3 register.
4380	* @param cr4 Guest context CR4 register.
4381	* @param GCPtr Where to start. Defaults to 0.
4382	* @param cb How much to check. Defaults to everything.
4383	*/
4384	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
4385	{
4386	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
4387	#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \|\| PGM_SHW_TYPE == PGM_TYPE_NONE
4388	return 0;
4389	#else
4390	unsigned cErrors = 0;
4391	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
4392	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
4393
4394	# if PGM_GST_TYPE == PGM_TYPE_PAE
4395	/** @todo currently broken; crashes below somewhere */
4396	AssertFailed();
4397	# endif
4398
4399	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
4400	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4401	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4402
4403	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
4404	PPGMCPU pPGM = &pVCpu->pgm.s;
4405	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
4406	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
4407	# ifndef IN_RING0
4408	RTHCPHYS HCPhys; /* general usage. */
4409	# endif
4410	int rc;
4411
4412	/*
4413	* Check that the Guest CR3 and all its mappings are correct.
4414	*/
4415	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
4416	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
4417	false);
4418	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
4419	# if 0
4420	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4421	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
4422	# else
4423	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
4424	# endif
4425	AssertRCReturn(rc, 1);
4426	HCPhys = NIL_RTHCPHYS;
4427	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
4428	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
4429	# endif
4430	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
4431	pgmGstGet32bitPDPtr(pVCpu);
4432	RTGCPHYS GCPhys;
4433	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
4434	AssertRCReturn(rc, 1);
4435	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
4436	# endif
4437	# endif /* !IN_RING0 */
4438
4439	/*
4440	* Get and check the Shadow CR3.
4441	*/
4442	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4443	unsigned cPDEs = X86_PG_ENTRIES;
4444	unsigned cIncrement = X86_PG_ENTRIES * GUEST_PAGE_SIZE;
4445	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
4446	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4447	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
4448	# else
4449	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4450	# endif
4451	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4452	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
4453	unsigned cPDEs = X86_PG_PAE_ENTRIES;
4454	unsigned cIncrement = X86_PG_PAE_ENTRIES * GUEST_PAGE_SIZE;
4455	# endif
4456	if (cb != ~(RTGCPTR)0)
4457	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
4458
4459	/** @todo call the other two PGMAssert() functions. /
4460
4461	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4462	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
4463
4464	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
4465	{
4466	PX86PML4E const pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
4467	AssertContinueStmt(pPml4eSrc, cErrors++);
4468
4469	PX86PML4E const pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
4470	AssertContinueStmt(pPml4eDst, cErrors++);
4471
4472	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
4473	if (!(pPml4eDst->u & X86_PML4E_P))
4474	{
4475	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4476	continue;
4477	}
4478
4479	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
4480	RTGCPHYS GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
4481
4482	if ((pPml4eSrc->u & X86_PML4E_P) != (pPml4eDst->u & X86_PML4E_P))
4483	{
4484	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4485	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4486	cErrors++;
4487	continue;
4488	}
4489
4490	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
4491	{
4492	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
4493	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4494	cErrors++;
4495	continue;
4496	}
4497
4498	if ( (pPml4eDst->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX))
4499	!= (pPml4eSrc->u & (X86_PML4E_US \| X86_PML4E_RW \| X86_PML4E_NX)))
4500	{
4501	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
4502	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
4503	cErrors++;
4504	continue;
4505	}
4506	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4507	{
4508	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
4509
4510	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
4511	/*
4512	* Check the PDPTEs too.
4513	*/
4514	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
4515
4516	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
4517	{
4518	unsigned iPDSrc = 0; /* initialized to shut up gcc */
4519	PPGMPOOLPAGE pShwPde = NULL;
4520	PX86PDPE pPdpeDst;
4521	RTGCPHYS GCPhysPdeSrc;
4522	X86PDPE PdpeSrc;
4523	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
4524	# if PGM_GST_TYPE == PGM_TYPE_PAE
4525	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
4526	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
4527	# else
4528	PX86PML4E pPml4eSrcIgn;
4529	PX86PDPT pPdptDst;
4530	PX86PDPAE pPDDst;
4531	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
4532
4533	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
4534	if (rc != VINF_SUCCESS)
4535	{
4536	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
4537	GCPtr += 512 * _2M;
4538	continue; /* next PDPTE */
4539	}
4540	Assert(pPDDst);
4541	# endif
4542	Assert(iPDSrc == 0);
4543
4544	pPdpeDst = &pPdptDst->a[iPdpt];
4545
4546	if (!(pPdpeDst->u & X86_PDPE_P))
4547	{
4548	GCPtr += 512 * _2M;
4549	continue; /* next PDPTE */
4550	}
4551
4552	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
4553	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
4554
4555	if ((pPdpeDst->u & X86_PDPE_P) != (PdpeSrc.u & X86_PDPE_P))
4556	{
4557	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4558	GCPtr += 512 * _2M;
4559	cErrors++;
4560	continue;
4561	}
4562
4563	if (GCPhysPdeSrc != pShwPde->GCPhys)
4564	{
4565	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4566	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4567	# else
4568	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4569	# endif
4570	GCPtr += 512 * _2M;
4571	cErrors++;
4572	continue;
4573	}
4574
4575	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4576	if ( (pPdpeDst->u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX))
4577	!= (PdpeSrc.u & (X86_PDPE_US \| X86_PDPE_RW \| X86_PDPE_LM_NX)))
4578	{
4579	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4580	GCPtr += 512 * _2M;
4581	cErrors++;
4582	continue;
4583	}
4584	# endif
4585
4586	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4587	{
4588	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4589	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4590	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4591	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4592	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4593	# endif
4594	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4595	/*
4596	* Iterate the shadow page directory.
4597	*/
4598	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4599	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4600
4601	for (;
4602	iPDDst < cPDEs;
4603	iPDDst++, GCPtr += cIncrement)
4604	{
4605	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4606	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4607	# else
4608	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4609	# endif
4610	if ( (PdeDst.u & X86_PDE_P)
4611	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) )
4612	{
4613	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4614	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4615	if (!pPoolPage)
4616	{
4617	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4618	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4619	cErrors++;
4620	continue;
4621	}
4622	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4623
4624	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4625	{
4626	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4627	GCPtr, (uint64_t)PdeDst.u));
4628	cErrors++;
4629	}
4630
4631	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4632	{
4633	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4634	GCPtr, (uint64_t)PdeDst.u));
4635	cErrors++;
4636	}
4637
4638	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4639	if (!(PdeSrc.u & X86_PDE_P))
4640	{
4641	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4642	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4643	cErrors++;
4644	continue;
4645	}
4646
4647	if ( !(PdeSrc.u & X86_PDE_PS)
4648	\|\| !fBigPagesSupported)
4649	{
4650	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4651	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4652	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (GUEST_PAGE_SIZE / 2)));
4653	# endif
4654	}
4655	else
4656	{
4657	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4658	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4659	{
4660	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4661	GCPtr, (uint64_t)PdeSrc.u));
4662	cErrors++;
4663	continue;
4664	}
4665	# endif
4666	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4667	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4668	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4669	# endif
4670	}
4671
4672	if ( pPoolPage->enmKind
4673	!= (!(PdeSrc.u & X86_PDE_PS) \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4674	{
4675	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4676	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4677	cErrors++;
4678	}
4679
4680	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4681	if (!pPhysPage)
4682	{
4683	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4684	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4685	cErrors++;
4686	continue;
4687	}
4688
4689	if (GCPhysGst != pPoolPage->GCPhys)
4690	{
4691	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4692	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4693	cErrors++;
4694	continue;
4695	}
4696
4697	if ( !(PdeSrc.u & X86_PDE_PS)
4698	\|\| !fBigPagesSupported)
4699	{
4700	/*
4701	* Page Table.
4702	*/
4703	const GSTPT *pPTSrc;
4704	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(GUEST_PAGE_SIZE - 1)),
4705	&pPTSrc);
4706	if (RT_FAILURE(rc))
4707	{
4708	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4709	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4710	cErrors++;
4711	continue;
4712	}
4713	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4714	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4715	{
4716	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4717	// (This problem will go away when/if we shadow multiple CR3s.)
4718	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4719	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4720	cErrors++;
4721	continue;
4722	}
4723	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4724	{
4725	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4726	GCPtr, (uint64_t)PdeDst.u));
4727	cErrors++;
4728	continue;
4729	}
4730
4731	/* iterate the page table. */
4732	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4733	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4734	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4735	# else
4736	const unsigned offPTSrc = 0;
4737	# endif
4738	for (unsigned iPT = 0, off = 0;
4739	iPT < RT_ELEMENTS(pPTDst->a);
4740	iPT++, off += GUEST_PAGE_SIZE)
4741	{
4742	const SHWPTE PteDst = pPTDst->a[iPT];
4743
4744	/* skip not-present and dirty tracked entries. */
4745	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4746	continue;
4747	Assert(SHW_PTE_IS_P(PteDst));
4748
4749	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4750	if (!(PteSrc.u & X86_PTE_P))
4751	{
4752	# ifdef IN_RING3
4753	PGMAssertHandlerAndFlagsInSync(pVM);
4754	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4755	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4756	0, 0, UINT64_MAX, 99, NULL);
4757	# endif
4758	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4759	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4760	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4761	cErrors++;
4762	continue;
4763	}
4764
4765	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4766	# if 1 /** @todo sync accessed bit properly... */
4767	fIgnoreFlags \|= X86_PTE_A;
4768	# endif
4769
4770	/* match the physical addresses */
4771	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4772	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4773
4774	# ifdef IN_RING3
4775	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4776	if (RT_FAILURE(rc))
4777	{
4778	# if 0
4779	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4780	{
4781	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4782	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4783	cErrors++;
4784	continue;
4785	}
4786	# endif
4787	}
4788	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4789	{
4790	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4791	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4792	cErrors++;
4793	continue;
4794	}
4795	# endif
4796
4797	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4798	if (!pPhysPage)
4799	{
4800	# if 0
4801	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4802	{
4803	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4804	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4805	cErrors++;
4806	continue;
4807	}
4808	# endif
4809	if (SHW_PTE_IS_RW(PteDst))
4810	{
4811	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4812	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4813	cErrors++;
4814	}
4815	fIgnoreFlags \|= X86_PTE_RW;
4816	}
4817	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4818	{
4819	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4820	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4821	cErrors++;
4822	continue;
4823	}
4824
4825	/* flags */
4826	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage) && !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
4827	{
4828	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4829	{
4830	if (SHW_PTE_IS_RW(PteDst))
4831	{
4832	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4833	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4834	cErrors++;
4835	continue;
4836	}
4837	fIgnoreFlags \|= X86_PTE_RW;
4838	}
4839	else
4840	{
4841	if ( SHW_PTE_IS_P(PteDst)
4842	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4843	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4844	# endif
4845	)
4846	{
4847	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4848	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4849	cErrors++;
4850	continue;
4851	}
4852	fIgnoreFlags \|= X86_PTE_P;
4853	}
4854	}
4855	else
4856	{
4857	if ((PteSrc.u & (X86_PTE_RW \| X86_PTE_D)) == X86_PTE_RW)
4858	{
4859	if (SHW_PTE_IS_RW(PteDst))
4860	{
4861	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4862	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4863	cErrors++;
4864	continue;
4865	}
4866	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4867	{
4868	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4869	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4870	cErrors++;
4871	continue;
4872	}
4873	if (SHW_PTE_IS_D(PteDst))
4874	{
4875	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4876	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4877	cErrors++;
4878	}
4879	# if 0 /** @todo sync access bit properly... */
4880	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4881	{
4882	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4883	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4884	cErrors++;
4885	}
4886	fIgnoreFlags \|= X86_PTE_RW;
4887	# else
4888	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4889	# endif
4890	}
4891	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4892	{
4893	/* access bit emulation (not implemented). */
4894	if ((PteSrc.u & X86_PTE_A) \|\| SHW_PTE_IS_P(PteDst))
4895	{
4896	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4897	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4898	cErrors++;
4899	continue;
4900	}
4901	if (!SHW_PTE_IS_A(PteDst))
4902	{
4903	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4904	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4905	cErrors++;
4906	}
4907	fIgnoreFlags \|= X86_PTE_P;
4908	}
4909	# ifdef DEBUG_sandervl
4910	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4911	# endif
4912	}
4913
4914	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4915	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4916	)
4917	{
4918	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4919	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4920	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4921	cErrors++;
4922	continue;
4923	}
4924	} /* foreach PTE */
4925	}
4926	else
4927	{
4928	/*
4929	* Big Page.
4930	*/
4931	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4932	if ((PdeSrc.u & (X86_PDE_RW \| X86_PDE4M_D)) == X86_PDE_RW)
4933	{
4934	if (PdeDst.u & X86_PDE_RW)
4935	{
4936	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4937	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4938	cErrors++;
4939	continue;
4940	}
4941	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4942	{
4943	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4944	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4945	cErrors++;
4946	continue;
4947	}
4948	# if 0 /** @todo sync access bit properly... */
4949	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4950	{
4951	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4952	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4953	cErrors++;
4954	}
4955	fIgnoreFlags \|= X86_PTE_RW;
4956	# else
4957	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4958	# endif
4959	}
4960	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4961	{
4962	/* access bit emulation (not implemented). */
4963	if ((PdeSrc.u & X86_PDE_A) \|\| SHW_PDE_IS_P(PdeDst))
4964	{
4965	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4966	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4967	cErrors++;
4968	continue;
4969	}
4970	if (!SHW_PDE_IS_A(PdeDst))
4971	{
4972	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4973	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4974	cErrors++;
4975	}
4976	fIgnoreFlags \|= X86_PTE_P;
4977	}
4978
4979	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4980	{
4981	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4982	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4983	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4984	cErrors++;
4985	}
4986
4987	/* iterate the page table. */
4988	for (unsigned iPT = 0, off = 0;
4989	iPT < RT_ELEMENTS(pPTDst->a);
4990	iPT++, off += GUEST_PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + GUEST_PAGE_SIZE))
4991	{
4992	const SHWPTE PteDst = pPTDst->a[iPT];
4993
4994	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4995	{
4996	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4997	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4998	cErrors++;
4999	}
5000
5001	/* skip not-present entries. */
5002	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
5003	continue;
5004
5005	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
5006
5007	/* match the physical addresses */
5008	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
5009
5010	# ifdef IN_RING3
5011	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
5012	if (RT_FAILURE(rc))
5013	{
5014	# if 0
5015	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
5016	{
5017	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
5018	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5019	cErrors++;
5020	}
5021	# endif
5022	}
5023	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
5024	{
5025	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5026	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5027	cErrors++;
5028	continue;
5029	}
5030	# endif
5031	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
5032	if (!pPhysPage)
5033	{
5034	# if 0 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
5035	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
5036	{
5037	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
5038	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5039	cErrors++;
5040	continue;
5041	}
5042	# endif
5043	if (SHW_PTE_IS_RW(PteDst))
5044	{
5045	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5046	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5047	cErrors++;
5048	}
5049	fIgnoreFlags \|= X86_PTE_RW;
5050	}
5051	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
5052	{
5053	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
5054	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5055	cErrors++;
5056	continue;
5057	}
5058
5059	/* flags */
5060	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
5061	{
5062	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
5063	{
5064	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
5065	{
5066	if ( SHW_PTE_IS_RW(PteDst)
5067	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage))
5068	{
5069	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
5070	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5071	cErrors++;
5072	continue;
5073	}
5074	fIgnoreFlags \|= X86_PTE_RW;
5075	}
5076	}
5077	else
5078	{
5079	if ( SHW_PTE_IS_P(PteDst)
5080	&& !PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(pPhysPage)
5081	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
5082	&& !PGM_PAGE_IS_MMIO(pPhysPage)
5083	# endif
5084	)
5085	{
5086	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
5087	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5088	cErrors++;
5089	continue;
5090	}
5091	fIgnoreFlags \|= X86_PTE_P;
5092	}
5093	}
5094
5095	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
5096	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
5097	)
5098	{
5099	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
5100	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
5101	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
5102	cErrors++;
5103	continue;
5104	}
5105	} /* for each PTE */
5106	}
5107	}
5108	/* not present */
5109
5110	} /* for each PDE */
5111
5112	} /* for each PDPTE */
5113
5114	} /* for each PML4E */
5115
5116	# ifdef DEBUG
5117	if (cErrors)
5118	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
5119	# endif
5120	# endif /* GST is in {32BIT, PAE, AMD64} */
5121	return cErrors;
5122	#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
5123	}
5124	#endif /* VBOX_STRICT */
5125
5126
5127	/**
5128	* Sets up the CR3 for shadow paging
5129	*
5130	* @returns Strict VBox status code.
5131	* @retval VINF_SUCCESS.
5132	*
5133	* @param pVCpu The cross context virtual CPU structure.
5134	* @param GCPhysCR3 The physical address in the CR3 register. (A20 mask
5135	* already applied.)
5136	*/
5137	PGM_BTH_DECL(int, MapCR3)(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3)
5138	{
5139	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5140	int rc = VINF_SUCCESS;
5141
5142	/* Update guest paging info. */
5143	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
5144	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
5145	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
5146
5147	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
5148	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5149
5150	# if PGM_GST_TYPE == PGM_TYPE_PAE
5151	if ( !pVCpu->pgm.s.CTX_SUFF(fPaePdpesAndCr3Mapped)
5152	\|\| pVCpu->pgm.s.GCPhysPaeCR3 != GCPhysCR3)
5153	# endif
5154	{
5155	/*
5156	* Map the page CR3 points at.
5157	*/
5158	RTHCPTR HCPtrGuestCR3;
5159	rc = pgmGstMapCr3(pVCpu, GCPhysCR3, &HCPtrGuestCR3);
5160	if (RT_SUCCESS(rc))
5161	{
5162	# if PGM_GST_TYPE == PGM_TYPE_32BIT
5163	# ifdef IN_RING3
5164	pVCpu->pgm.s.pGst32BitPdR3 = (PX86PD)HCPtrGuestCR3;
5165	pVCpu->pgm.s.pGst32BitPdR0 = NIL_RTR0PTR;
5166	# else
5167	pVCpu->pgm.s.pGst32BitPdR3 = NIL_RTR3PTR;
5168	pVCpu->pgm.s.pGst32BitPdR0 = (PX86PD)HCPtrGuestCR3;
5169	# endif
5170
5171	# elif PGM_GST_TYPE == PGM_TYPE_PAE
5172	# ifdef IN_RING3
5173	pVCpu->pgm.s.pGstPaePdptR3 = (PX86PDPT)HCPtrGuestCR3;
5174	pVCpu->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
5175	# else
5176	pVCpu->pgm.s.pGstPaePdptR3 = NIL_RTR3PTR;
5177	pVCpu->pgm.s.pGstPaePdptR0 = (PX86PDPT)HCPtrGuestCR3;
5178	# endif
5179
5180	X86PDPE aGstPaePdpes[X86_PG_PAE_PDPE_ENTRIES];
5181	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
5182	/*
5183	* When EPT is enabled by the nested-hypervisor and the nested-guest is in PAE mode,
5184	* the guest-CPU context would've already been updated with the 4 PAE PDPEs specified
5185	* in the virtual VMCS. The PDPEs can differ from those in guest memory referenced by
5186	* the translated nested-guest CR3. We -MUST- use the PDPEs provided in the virtual VMCS
5187	* rather than those in guest memory.
5188	*
5189	* See Intel spec. 26.3.2.4 "Loading Page-Directory-Pointer-Table Entries".
5190	*/
5191	if (pVCpu->pgm.s.enmGuestSlatMode == PGMSLAT_EPT)
5192	CPUMGetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5193	else
5194	#endif
5195	{
5196	/* Update CPUM with the PAE PDPEs referenced by CR3. */
5197	memcpy(&aGstPaePdpes, HCPtrGuestCR3, sizeof(aGstPaePdpes));
5198	CPUMSetGuestPaePdpes(pVCpu, &aGstPaePdpes[0]);
5199	}
5200
5201	/*
5202	* Map the 4 PAE PDPEs.
5203	*/
5204	rc = PGMGstMapPaePdpes(pVCpu, &aGstPaePdpes[0]);
5205	if (RT_SUCCESS(rc))
5206	{
5207	# ifdef IN_RING3
5208	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = true;
5209	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5210	# else
5211	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5212	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = true;
5213	# endif
5214	pVCpu->pgm.s.GCPhysPaeCR3 = GCPhysCR3;
5215	}
5216
5217	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
5218	# ifdef IN_RING3
5219	pVCpu->pgm.s.pGstAmd64Pml4R3 = (PX86PML4)HCPtrGuestCR3;
5220	pVCpu->pgm.s.pGstAmd64Pml4R0 = NIL_RTR0PTR;
5221	# else
5222	pVCpu->pgm.s.pGstAmd64Pml4R3 = NIL_RTR3PTR;
5223	pVCpu->pgm.s.pGstAmd64Pml4R0 = (PX86PML4)HCPtrGuestCR3;
5224	# endif
5225	# endif
5226	}
5227	else
5228	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
5229	}
5230	#endif
5231
5232	/*
5233	* Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
5234	*/
5235	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5236	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5237	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
5238	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
5239	&& PGM_GST_TYPE != PGM_TYPE_PROT))
5240
5241	Assert(!pVM->pgm.s.fNestedPaging);
5242	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
5243
5244	/*
5245	* Update the shadow root page as well since that's not fixed.
5246	*/
5247	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5248	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
5249	PPGMPOOLPAGE pNewShwPageCR3;
5250
5251	PGM_LOCK_VOID(pVM);
5252
5253	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5254	if (pPool->cDirtyPages)
5255	pgmPoolResetDirtyPages(pVM);
5256	# endif
5257
5258	Assert(!(GCPhysCR3 >> (GUEST_PAGE_SHIFT + 32))); /** @todo what is this for? */
5259	int const rc2 = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE,
5260	PGM_A20_IS_ENABLED(pVCpu), NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/, &pNewShwPageCR3);
5261	AssertFatalRC(rc2);
5262
5263	pVCpu->pgm.s.pShwPageCR3R3 = pgmPoolConvertPageToR3(pPool, pNewShwPageCR3);
5264	pVCpu->pgm.s.pShwPageCR3R0 = pgmPoolConvertPageToR0(pPool, pNewShwPageCR3);
5265
5266	/* Set the current hypervisor CR3. */
5267	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
5268
5269	/* Clean up the old CR3 root. */
5270	if ( pOldShwPageCR3
5271	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
5272	{
5273	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
5274
5275	/* Mark the page as unlocked; allow flushing again. */
5276	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
5277
5278	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
5279	}
5280	PGM_UNLOCK(pVM);
5281	# else
5282	NOREF(GCPhysCR3);
5283	# endif
5284
5285	return rc;
5286	}
5287
5288	/**
5289	* Unmaps the shadow CR3.
5290	*
5291	* @returns VBox status, no specials.
5292	* @param pVCpu The cross context virtual CPU structure.
5293	*/
5294	PGM_BTH_DECL(int, UnmapCR3)(PVMCPUCC pVCpu)
5295	{
5296	LogFlow(("UnmapCR3\n"));
5297
5298	int rc = VINF_SUCCESS;
5299	PVMCC pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
5300
5301	/*
5302	* Update guest paging info.
5303	*/
5304	#if PGM_GST_TYPE == PGM_TYPE_32BIT
5305	pVCpu->pgm.s.pGst32BitPdR3 = 0;
5306	pVCpu->pgm.s.pGst32BitPdR0 = 0;
5307
5308	#elif PGM_GST_TYPE == PGM_TYPE_PAE
5309	pVCpu->pgm.s.pGstPaePdptR3 = 0;
5310	pVCpu->pgm.s.pGstPaePdptR0 = 0;
5311	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
5312	{
5313	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
5314	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
5315	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
5316	}
5317
5318	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
5319	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
5320	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
5321
5322	#else /* prot/real mode stub */
5323	/* nothing to do */
5324	#endif
5325
5326	/*
5327	* PAE PDPEs (and CR3) might have been mapped via PGMGstMapPaePdpesAtCr3()
5328	* prior to switching to PAE in pfnMapCr3(), so we need to clear them here.
5329	*/
5330	pVCpu->pgm.s.fPaePdpesAndCr3MappedR3 = false;
5331	pVCpu->pgm.s.fPaePdpesAndCr3MappedR0 = false;
5332	pVCpu->pgm.s.GCPhysPaeCR3 = NIL_RTGCPHYS;
5333
5334	/*
5335	* Update shadow paging info.
5336	*/
5337	#if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
5338	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
5339	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
5340	# if PGM_GST_TYPE != PGM_TYPE_REAL
5341	Assert(!pVM->pgm.s.fNestedPaging);
5342	# endif
5343	PGM_LOCK_VOID(pVM);
5344
5345	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
5346	{
5347	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
5348
5349	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
5350	if (pPool->cDirtyPages)
5351	pgmPoolResetDirtyPages(pVM);
5352	# endif
5353
5354	/* Mark the page as unlocked; allow flushing again. */
5355	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
5356
5357	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
5358	pVCpu->pgm.s.pShwPageCR3R3 = 0;
5359	pVCpu->pgm.s.pShwPageCR3R0 = 0;
5360	}
5361
5362	PGM_UNLOCK(pVM);
5363	#endif
5364
5365	return rc;
5366	}
5367

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 103917

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