PGMAllBth.h@ 11976

Last change on this file since 11976 was 11525, checked in by vboxsync, 17 years ago
Added support for PSE-36.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 189.5 KB

Line
1	/* $Id: PGMAllBth.h 11525 2008-08-21 09:07:51Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69	/**
70	* #PF Handler for raw-mode guest execution.
71	*
72	* @returns VBox status code (appropriate for trap handling and GC return).
73	* @param pVM VM Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	*/
78	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
79	{
80	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
81	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
82
83	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
84	/*
85	* Hide the instruction fetch trap indicator for now.
86	*/
87	/** @todo NXE will change this and we must fix NXE in the switcher too! */
88	if (uErr & X86_TRAP_PF_ID)
89	{
90	uErr &= ~X86_TRAP_PF_ID;
91	TRPMSetErrorCode(pVM, uErr);
92	}
93	# endif
94
95	/*
96	* Get PDs.
97	*/
98	int rc;
99	# if PGM_WITH_PAGING(PGM_GST_TYPE)
100	# if PGM_GST_TYPE == PGM_TYPE_32BIT
101	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
102	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
103
104	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
105
106	# if PGM_GST_TYPE == PGM_TYPE_PAE
107	unsigned iPDSrc;
108	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
109
110	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
111	unsigned iPDSrc;
112	PX86PML4E pPml4eSrc;
113	X86PDPE PdpeSrc;
114	PGSTPD pPDSrc;
115
116	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
117	Assert(pPml4eSrc);
118	# endif
119	/* Quick check for a valid guest trap. */
120	if (!pPDSrc)
121	{
122	LogFlow(("Trap0eHandler: guest PDPTR %d not present CR3=%VGp\n", (pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK, (CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK)));
123	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
124	TRPMSetErrorCode(pVM, uErr);
125	return VINF_EM_RAW_GUEST_TRAP;
126	}
127	# endif
128	# else
129	PGSTPD pPDSrc = NULL;
130	const unsigned iPDSrc = 0;
131	# endif
132
133	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
134	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
135	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
136	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
137	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
138	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
139
140	# if PGM_GST_TYPE == PGM_TYPE_PAE
141	/* Did we mark the PDPT as not present in SyncCR3? */
142	unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
143	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
144	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
145
146	# endif
147
148	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
149	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
150	PX86PDPAE pPDDst;
151	# if PGM_GST_TYPE == PGM_TYPE_PROT
152	/* AMD-V nested paging */
153	X86PML4E Pml4eSrc;
154	X86PDPE PdpeSrc;
155	PX86PML4E pPml4eSrc = &Pml4eSrc;
156
157	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
158	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
159	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
160	# endif
161
162	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
163	if (rc != VINF_SUCCESS)
164	{
165	AssertRC(rc);
166	return rc;
167	}
168	Assert(pPDDst);
169	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
170	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
171	PX86PDPAE pPDDst;
172
173	AssertFailed();
174	# endif
175
176	# if PGM_WITH_PAGING(PGM_GST_TYPE)
177	/*
178	* If we successfully correct the write protection fault due to dirty bit
179	* tracking, or this page fault is a genuine one, then return immediately.
180	*/
181	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
182	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
183	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
184	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
185	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
186	{
187	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
188	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
189	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
190	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
191	}
192
193	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
194	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
195
196	/*
197	* A common case is the not-present error caused by lazy page table syncing.
198	*
199	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
200	* so we can safely assume that the shadow PT is present when calling SyncPage later.
201	*
202	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
203	* of mapping conflict and defer to SyncCR3 in R3.
204	* (Again, we do NOT support access handlers for non-present guest pages.)
205	*
206	*/
207	# if PGM_WITH_PAGING(PGM_GST_TYPE)
208	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
209	# else
210	GSTPDE PdeSrc;
211	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
212	PdeSrc.n.u1Present = 1;
213	PdeSrc.n.u1Write = 1;
214	PdeSrc.n.u1Accessed = 1;
215	PdeSrc.n.u1User = 1;
216	# endif
217	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
218	&& !pPDDst->a[iPDDst].n.u1Present
219	&& PdeSrc.n.u1Present
220	)
221
222	{
223	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
224	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
225	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
226	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
227	if (VBOX_SUCCESS(rc))
228	{
229	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
230	return rc;
231	}
232	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
233	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
234	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
235	return VINF_PGM_SYNC_CR3;
236	}
237
238	# if PGM_WITH_PAGING(PGM_GST_TYPE)
239	/*
240	* Check if this address is within any of our mappings.
241	*
242	* This is very fast and it's gonna save us a bit of effort below and prevent
243	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
244	* (BTW, it's impossible to have physical access handlers in a mapping.)
245	*/
246	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
247	{
248	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
249	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
250	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
251	{
252	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
253	break;
254	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
255	{
256	/*
257	* The first thing we check is if we've got an undetected conflict.
258	*/
259	if (!pVM->pgm.s.fMappingsFixed)
260	{
261	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
262	while (iPT-- > 0)
263	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
264	{
265	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
266	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
267	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
268	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
269	return VINF_PGM_SYNC_CR3;
270	}
271	}
272
273	/*
274	* Check if the fault address is in a virtual page access handler range.
275	*/
276	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
277	if ( pCur
278	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
279	&& uErr & X86_TRAP_PF_RW)
280	{
281	# ifdef IN_GC
282	STAM_PROFILE_START(&pCur->Stat, h);
283	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
284	STAM_PROFILE_STOP(&pCur->Stat, h);
285	# else
286	AssertFailed();
287	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
288	# endif
289	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
290	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
291	return rc;
292	}
293
294	/*
295	* Pretend we're not here and let the guest handle the trap.
296	*/
297	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
298	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
299	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
300	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
301	return VINF_EM_RAW_GUEST_TRAP;
302	}
303	}
304	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
305	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
306	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
307
308	/*
309	* Check if this fault address is flagged for special treatment,
310	* which means we'll have to figure out the physical address and
311	* check flags associated with it.
312	*
313	* ASSUME that we can limit any special access handling to pages
314	* in page tables which the guest believes to be present.
315	*/
316	if (PdeSrc.n.u1Present)
317	{
318	RTGCPHYS GCPhys = NIL_RTGCPHYS;
319
320	# if PGM_WITH_PAGING(PGM_GST_TYPE)
321	# if PGM_GST_TYPE == PGM_TYPE_AMD64
322	bool fBigPagesSupported = true;
323	# else
324	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
325	# endif
326	if ( PdeSrc.b.u1Size
327	&& fBigPagesSupported)
328	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
329	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
330	else
331	{
332	PGSTPT pPTSrc;
333	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
334	if (VBOX_SUCCESS(rc))
335	{
336	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
337	if (pPTSrc->a[iPTESrc].n.u1Present)
338	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
339	}
340	}
341	# else
342	/* No paging so the fault address is the physical address */
343	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
344	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
345
346	/*
347	* If we have a GC address we'll check if it has any flags set.
348	*/
349	if (GCPhys != NIL_RTGCPHYS)
350	{
351	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
352
353	PPGMPAGE pPage;
354	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
355	if (VBOX_SUCCESS(rc))
356	{
357	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
358	{
359	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
360	{
361	/*
362	* Physical page access handler.
363	*/
364	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
365	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
366	if (pCur)
367	{
368	# ifdef PGM_SYNC_N_PAGES
369	/*
370	* If the region is write protected and we got a page not present fault, then sync
371	* the pages. If the fault was caused by a read, then restart the instruction.
372	* In case of write access continue to the GC write handler.
373	*
374	* ASSUMES that there is only one handler per page or that they have similar write properties.
375	*/
376	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
377	&& !(uErr & X86_TRAP_PF_P))
378	{
379	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
380	if ( VBOX_FAILURE(rc)
381	\|\| !(uErr & X86_TRAP_PF_RW)
382	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
383	{
384	AssertRC(rc);
385	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
386	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
387	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
388	return rc;
389	}
390	}
391	# endif
392
393	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
394	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
395	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
396
397	#if defined(IN_GC) \|\| defined(IN_RING0)
398	if (CTXALLSUFF(pCur->pfnHandler))
399	{
400	STAM_PROFILE_START(&pCur->Stat, h);
401	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
402	STAM_PROFILE_STOP(&pCur->Stat, h);
403	}
404	else
405	#endif
406	rc = VINF_EM_RAW_EMULATE_INSTR;
407	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
408	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
409	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
410	return rc;
411	}
412	}
413	# if PGM_WITH_PAGING(PGM_GST_TYPE)
414	else
415	{
416	# ifdef PGM_SYNC_N_PAGES
417	/*
418	* If the region is write protected and we got a page not present fault, then sync
419	* the pages. If the fault was caused by a read, then restart the instruction.
420	* In case of write access continue to the GC write handler.
421	*/
422	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
423	&& !(uErr & X86_TRAP_PF_P))
424	{
425	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
426	if ( VBOX_FAILURE(rc)
427	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
428	\|\| !(uErr & X86_TRAP_PF_RW))
429	{
430	AssertRC(rc);
431	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
432	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
433	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
434	return rc;
435	}
436	}
437	# endif
438	/*
439	* Ok, it's an virtual page access handler.
440	*
441	* Since it's faster to search by address, we'll do that first
442	* and then retry by GCPhys if that fails.
443	*/
444	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
445	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
446	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
447	*/
448	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
449	if (pCur)
450	{
451	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
452	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
453	\|\| !(uErr & X86_TRAP_PF_P)
454	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
455	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
456
457	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
458	&& ( uErr & X86_TRAP_PF_RW
459	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
460	{
461	# ifdef IN_GC
462	STAM_PROFILE_START(&pCur->Stat, h);
463	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
464	STAM_PROFILE_STOP(&pCur->Stat, h);
465	# else
466	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
467	# endif
468	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
469	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
470	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
471	return rc;
472	}
473	/* Unhandled part of a monitored page */
474	}
475	else
476	{
477	/* Check by physical address. */
478	PPGMVIRTHANDLER pCur;
479	unsigned iPage;
480	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
481	&pCur, &iPage);
482	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
483	if ( pCur
484	&& ( uErr & X86_TRAP_PF_RW
485	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
486	{
487	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
488	# ifdef IN_GC
489	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
490	Assert(off < pCur->cb);
491	STAM_PROFILE_START(&pCur->Stat, h);
492	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
493	STAM_PROFILE_STOP(&pCur->Stat, h);
494	# else
495	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
496	# endif
497	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
498	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
499	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
500	return rc;
501	}
502	}
503	}
504	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
505
506	/*
507	* There is a handled area of the page, but this fault doesn't belong to it.
508	* We must emulate the instruction.
509	*
510	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
511	* we first check if this was a page-not-present fault for a page with only
512	* write access handlers. Restart the instruction if it wasn't a write access.
513	*/
514	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
515
516	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
517	&& !(uErr & X86_TRAP_PF_P))
518	{
519	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
520	if ( VBOX_FAILURE(rc)
521	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
522	\|\| !(uErr & X86_TRAP_PF_RW))
523	{
524	AssertRC(rc);
525	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
526	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
527	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
528	return rc;
529	}
530	}
531
532	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
533	* It's writing to an unhandled part of the LDT page several million times.
534	*/
535	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
536	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
537	rc, pPage->HCPhys,
538	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
539	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
540	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
541	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
542	return rc;
543	} /* if any kind of handler */
544
545	# if PGM_WITH_PAGING(PGM_GST_TYPE)
546	if (uErr & X86_TRAP_PF_P)
547	{
548	/*
549	* The page isn't marked, but it might still be monitored by a virtual page access handler.
550	* (ASSUMES no temporary disabling of virtual handlers.)
551	*/
552	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
553	* we should correct both the shadow page table and physical memory flags, and not only check for
554	* accesses within the handler region but for access to pages with virtual handlers. */
555	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
556	if (pCur)
557	{
558	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
559	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
560	\|\| !(uErr & X86_TRAP_PF_P)
561	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
562	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
563
564	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
565	&& ( uErr & X86_TRAP_PF_RW
566	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
567	{
568	# ifdef IN_GC
569	STAM_PROFILE_START(&pCur->Stat, h);
570	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
571	STAM_PROFILE_STOP(&pCur->Stat, h);
572	# else
573	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
574	# endif
575	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
576	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
577	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
578	return rc;
579	}
580	}
581	}
582	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
583	}
584	else
585	{
586	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
587	* back to the recompiler to emulate the instruction.
588	*/
589	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
590	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersInvalid);
591	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
592	return VINF_EM_RAW_EMULATE_INSTR;
593	}
594
595	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
596
597	# ifdef PGM_OUT_OF_SYNC_IN_GC
598	/*
599	* We are here only if page is present in Guest page tables and trap is not handled
600	* by our handlers.
601	* Check it for page out-of-sync situation.
602	*/
603	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
604
605	if (!(uErr & X86_TRAP_PF_P))
606	{
607	/*
608	* Page is not present in our page tables.
609	* Try to sync it!
610	* BTW, fPageShw is invalid in this branch!
611	*/
612	if (uErr & X86_TRAP_PF_US)
613	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
614	else /* supervisor */
615	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
616
617	# if defined(LOG_ENABLED) && !defined(IN_RING0)
618	RTGCPHYS GCPhys;
619	uint64_t fPageGst;
620	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
621	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
622	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
623	# endif /* LOG_ENABLED */
624
625	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
626	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
627	{
628	uint64_t fPageGst;
629	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
630	if ( VBOX_SUCCESS(rc)
631	&& !(fPageGst & X86_PTE_US))
632	{
633	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
634	if ( pvFault == (RTGCPTR)pRegFrame->eip
635	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
636	# ifdef CSAM_DETECT_NEW_CODE_PAGES
637	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
638	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
639	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
640	)
641	{
642	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
643	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
644	if (rc != VINF_SUCCESS)
645	{
646	/*
647	* CSAM needs to perform a job in ring 3.
648	*
649	* Sync the page before going to the host context; otherwise we'll end up in a loop if
650	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
651	*/
652	LogFlow(("CSAM ring 3 job\n"));
653	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
654	AssertRC(rc2);
655
656	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
657	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
658	return rc;
659	}
660	}
661	# ifdef CSAM_DETECT_NEW_CODE_PAGES
662	else
663	if ( uErr == X86_TRAP_PF_RW
664	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
665	&& pRegFrame->ecx < 0x10000
666	)
667	{
668	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
669	* to detect loading of new code pages.
670	*/
671
672	/*
673	* Decode the instruction.
674	*/
675	RTGCPTR PC;
676	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
677	if (rc == VINF_SUCCESS)
678	{
679	DISCPUSTATE Cpu;
680	uint32_t cbOp;
681	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
682
683	/* For now we'll restrict this to rep movsw/d instructions */
684	if ( rc == VINF_SUCCESS
685	&& Cpu.pCurInstr->opcode == OP_MOVSWD
686	&& (Cpu.prefix & PREFIX_REP))
687	{
688	CSAMMarkPossibleCodePage(pVM, pvFault);
689	}
690	}
691	}
692	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
693
694	/*
695	* Mark this page as safe.
696	*/
697	/** @todo not correct for pages that contain both code and data!! */
698	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
699	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
700	}
701	}
702	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
703	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
704	if (VBOX_SUCCESS(rc))
705	{
706	/* The page was successfully synced, return to the guest. */
707	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
708	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
709	return VINF_SUCCESS;
710	}
711	}
712	else
713	{
714	/*
715	* A side effect of not flushing global PDEs are out of sync pages due
716	* to physical monitored regions, that are no longer valid.
717	* Assume for now it only applies to the read/write flag
718	*/
719	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
720	{
721	if (uErr & X86_TRAP_PF_US)
722	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
723	else /* supervisor */
724	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
725
726
727	/*
728	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
729	*/
730	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
731	if (VBOX_SUCCESS(rc))
732	{
733	/*
734	* Page was successfully synced, return to guest.
735	*/
736	# ifdef VBOX_STRICT
737	RTGCPHYS GCPhys;
738	uint64_t fPageGst;
739	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
740	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
741	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
742
743	uint64_t fPageShw;
744	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
745	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
746	# endif /* VBOX_STRICT */
747	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
748	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
749	return VINF_SUCCESS;
750	}
751
752	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
753	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
754	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
755	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
756	{
757	uint64_t fPageGst;
758	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
759	if ( VBOX_SUCCESS(rc)
760	&& !(fPageGst & X86_PTE_RW))
761	{
762	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
763	if (VBOX_SUCCESS(rc))
764	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
765	else
766	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
767	return rc;
768	}
769	else
770	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
771	}
772
773	}
774
775	# if PGM_WITH_PAGING(PGM_GST_TYPE)
776	# ifdef VBOX_STRICT
777	/*
778	* Check for VMM page flags vs. Guest page flags consistency.
779	* Currently only for debug purposes.
780	*/
781	if (VBOX_SUCCESS(rc))
782	{
783	/* Get guest page flags. */
784	uint64_t fPageGst;
785	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
786	if (VBOX_SUCCESS(rc))
787	{
788	uint64_t fPageShw;
789	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
790
791	/*
792	* Compare page flags.
793	* Note: we have AVL, A, D bits desynched.
794	*/
795	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
796	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
797	}
798	else
799	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
800	}
801	else
802	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
803	# endif /* VBOX_STRICT */
804	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
805	}
806	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
807	# endif /* PGM_OUT_OF_SYNC_IN_GC */
808	}
809	else
810	{
811	/*
812	* Page not present in Guest OS or invalid page table address.
813	* This is potential virtual page access handler food.
814	*
815	* For the present we'll say that our access handlers don't
816	* work for this case - we've already discarded the page table
817	* not present case which is identical to this.
818	*
819	* When we perchance find we need this, we will probably have AVL
820	* trees (offset based) to operate on and we can measure their speed
821	* agains mapping a page table and probably rearrange this handling
822	* a bit. (Like, searching virtual ranges before checking the
823	* physical address.)
824	*/
825	}
826	}
827
828
829	# if PGM_WITH_PAGING(PGM_GST_TYPE)
830	/*
831	* Conclusion, this is a guest trap.
832	*/
833	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
834	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
835	return VINF_EM_RAW_GUEST_TRAP;
836	# else
837	/* present, but not a monitored page; perhaps the guest is probing physical memory */
838	return VINF_EM_RAW_EMULATE_INSTR;
839	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
840
841
842	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
843
844	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
845	return VERR_INTERNAL_ERROR;
846	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
847	}
848
849
850	/**
851	* Emulation of the invlpg instruction.
852	*
853	*
854	* @returns VBox status code.
855	*
856	* @param pVM VM handle.
857	* @param GCPtrPage Page to invalidate.
858	*
859	* @remark ASSUMES that the guest is updating before invalidating. This order
860	* isn't required by the CPU, so this is speculative and could cause
861	* trouble.
862	*
863	* @todo Flush page or page directory only if necessary!
864	* @todo Add a #define for simply invalidating the page.
865	*/
866	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
867	{
868	#if PGM_WITH_PAGING(PGM_GST_TYPE) \
869	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
870	int rc;
871
872	LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
873	/*
874	* Get the shadow PD entry and skip out if this PD isn't present.
875	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
876	*/
877	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
878	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
879	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
880	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
881	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
882	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
883	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
884	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
885
886	/* If the shadow PDPE isn't present, then skip the invalidate. */
887	if (!pPdptDst->a[iPdpte].n.u1Present)
888	{
889	Assert(!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING));
890	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
891	return VINF_SUCCESS;
892	}
893
894	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
895	/* PML4 */
896	AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
897
898	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
899	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
900	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
901	PX86PDPAE pPDDst;
902	PX86PDPT pPdptDst;
903	PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
904	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
905	if (rc != VINF_SUCCESS)
906	{
907	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
908	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
909	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
910	PGM_INVL_GUEST_TLBS();
911	return VINF_SUCCESS;
912	}
913	Assert(pPDDst);
914
915	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
916	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
917
918	if (!pPdpeDst->n.u1Present)
919	{
920	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
921	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
922	PGM_INVL_GUEST_TLBS();
923	return VINF_SUCCESS;
924	}
925
926	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
927
928	const SHWPDE PdeDst = *pPdeDst;
929	if (!PdeDst.n.u1Present)
930	{
931	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
932	return VINF_SUCCESS;
933	}
934
935	/*
936	* Get the guest PD entry and calc big page.
937	*/
938	# if PGM_GST_TYPE == PGM_TYPE_32BIT
939	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
940	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
941	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
942	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
943	unsigned iPDSrc;
944	# if PGM_GST_TYPE == PGM_TYPE_PAE
945	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
946	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
947	# else /* AMD64 */
948	PX86PML4E pPml4eSrc;
949	X86PDPE PdpeSrc;
950	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
951	# endif
952	GSTPDE PdeSrc;
953
954	if (pPDSrc)
955	PdeSrc = pPDSrc->a[iPDSrc];
956	else
957	PdeSrc.u = 0;
958	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
959
960	# if PGM_GST_TYPE == PGM_TYPE_AMD64
961	const bool fIsBigPage = PdeSrc.b.u1Size;
962	# else
963	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
964	# endif
965
966	# ifdef IN_RING3
967	/*
968	* If a CR3 Sync is pending we may ignore the invalidate page operation
969	* depending on the kind of sync and if it's a global page or not.
970	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
971	*/
972	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
973	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
974	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
975	&& fIsBigPage
976	&& PdeSrc.b.u1Global
977	)
978	)
979	# else
980	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
981	# endif
982	{
983	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
984	return VINF_SUCCESS;
985	}
986	# endif /* IN_RING3 */
987
988	# if PGM_GST_TYPE == PGM_TYPE_AMD64
989	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
990
991	/* Fetch the pgm pool shadow descriptor. */
992	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
993	Assert(pShwPdpt);
994
995	/* Fetch the pgm pool shadow descriptor. */
996	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
997	Assert(pShwPde);
998
999	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1000	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1001
1002	if ( !pPml4eSrc->n.u1Present
1003	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1004	{
1005	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1006	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1007	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1008	pPml4eDst->u = 0;
1009	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1010	PGM_INVL_GUEST_TLBS();
1011	return VINF_SUCCESS;
1012	}
1013	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1014	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1015	{
1016	/*
1017	* Mark not present so we can resync the PML4E when it's used.
1018	*/
1019	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1020	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1021	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1022	pPml4eDst->u = 0;
1023	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1024	PGM_INVL_GUEST_TLBS();
1025	}
1026	else if (!pPml4eSrc->n.u1Accessed)
1027	{
1028	/*
1029	* Mark not present so we can set the accessed bit.
1030	*/
1031	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1032	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1033	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1034	pPml4eDst->u = 0;
1035	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1036	PGM_INVL_GUEST_TLBS();
1037	}
1038
1039	/* Check if the PDPT entry has changed. */
1040	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1041	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1042	if ( !PdpeSrc.n.u1Present
1043	\|\| pShwPde->GCPhys != GCPhysPd)
1044	{
1045	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1046	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1047	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1048	pPdpeDst->u = 0;
1049	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1050	PGM_INVL_GUEST_TLBS();
1051	return VINF_SUCCESS;
1052	}
1053	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1054	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1055	{
1056	/*
1057	* Mark not present so we can resync the PDPTE when it's used.
1058	*/
1059	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1060	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1061	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1062	pPdpeDst->u = 0;
1063	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1064	PGM_INVL_GUEST_TLBS();
1065	}
1066	else if (!PdpeSrc.lm.u1Accessed)
1067	{
1068	/*
1069	* Mark not present so we can set the accessed bit.
1070	*/
1071	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1072	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1073	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1074	pPdpeDst->u = 0;
1075	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1076	PGM_INVL_GUEST_TLBS();
1077	}
1078	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1079
1080	# if PGM_GST_TYPE == PGM_TYPE_PAE
1081	/* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes. */
1082	if (!pPDSrc)
1083	{
1084	/* Guest PDPE not present */
1085	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* root of the 2048 PDE array */
1086	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
1087	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1088
1089	Assert(!(CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte].n.u1Present));
1090	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
1091	/* for each page directory entry */
1092	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1093	{
1094	if ( pPDEDst[iPD].n.u1Present
1095	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
1096	{
1097	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
1098	pPDEDst[iPD].u = 0;
1099	}
1100	}
1101	if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
1102	pPdptDst->a[iPdpte].n.u1Present = 0;
1103	PGM_INVL_GUEST_TLBS();
1104	}
1105	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte], ("%VGp vs %VGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte]));
1106	# endif
1107
1108
1109	/*
1110	* Deal with the Guest PDE.
1111	*/
1112	rc = VINF_SUCCESS;
1113	if (PdeSrc.n.u1Present)
1114	{
1115	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1116	{
1117	/*
1118	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1119	*/
1120	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1121	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1122	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1123	}
1124	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1125	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1126	{
1127	/*
1128	* Mark not present so we can resync the PDE when it's used.
1129	*/
1130	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1131	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1132	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1133	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1134	# else
1135	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1136	# endif
1137	pPdeDst->u = 0;
1138	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1139	PGM_INVL_GUEST_TLBS();
1140	}
1141	else if (!PdeSrc.n.u1Accessed)
1142	{
1143	/*
1144	* Mark not present so we can set the accessed bit.
1145	*/
1146	LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1147	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1148	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1149	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1150	# else
1151	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1152	# endif
1153	pPdeDst->u = 0;
1154	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
1155	PGM_INVL_GUEST_TLBS();
1156	}
1157	else if (!fIsBigPage)
1158	{
1159	/*
1160	* 4KB - page.
1161	*/
1162	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1163	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1164	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1165	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1166	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1167	# endif
1168	if (pShwPage->GCPhys == GCPhys)
1169	{
1170	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1171	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1172	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1173	if (pPT->a[iPTEDst].n.u1Present)
1174	{
1175	# ifdef PGMPOOL_WITH_USER_TRACKING
1176	/* This is very unlikely with caching/monitoring enabled. */
1177	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1178	# endif
1179	pPT->a[iPTEDst].u = 0;
1180	}
1181	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1182	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1183	if (VBOX_SUCCESS(rc))
1184	rc = VINF_SUCCESS;
1185	# endif
1186	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
1187	PGM_INVL_PG(GCPtrPage);
1188	}
1189	else
1190	{
1191	/*
1192	* The page table address changed.
1193	*/
1194	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1195	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1196	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1197	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1198	# else
1199	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1200	# endif
1201	pPdeDst->u = 0;
1202	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
1203	PGM_INVL_GUEST_TLBS();
1204	}
1205	}
1206	else
1207	{
1208	/*
1209	* 2/4MB - page.
1210	*/
1211	/* Before freeing the page, check if anything really changed. */
1212	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1213	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1214	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1215	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1216	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1217	# endif
1218	if ( pShwPage->GCPhys == GCPhys
1219	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1220	{
1221	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1222	/** @todo PAT */
1223	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1224	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1225	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1226	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1227	{
1228	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1229	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
1230	return VINF_SUCCESS;
1231	}
1232	}
1233
1234	/*
1235	* Ok, the page table is present and it's been changed in the guest.
1236	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1237	* We could do this for some flushes in GC too, but we need an algorithm for
1238	* deciding which 4MB pages containing code likely to be executed very soon.
1239	*/
1240	LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1241	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1242	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1243	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1244	# else
1245	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1246	# endif
1247	pPdeDst->u = 0;
1248	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1249	PGM_INVL_BIG_PG(GCPtrPage);
1250	}
1251	}
1252	else
1253	{
1254	/*
1255	* Page directory is not present, mark shadow PDE not present.
1256	*/
1257	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1258	{
1259	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1260	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1261	# else
1262	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1263	# endif
1264	pPdeDst->u = 0;
1265	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1266	PGM_INVL_PG(GCPtrPage);
1267	}
1268	else
1269	{
1270	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1271	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1272	}
1273	}
1274
1275	return rc;
1276
1277	#else /* guest real and protected mode */
1278	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1279	return VINF_SUCCESS;
1280	#endif
1281	}
1282
1283
1284	#ifdef PGMPOOL_WITH_USER_TRACKING
1285	/**
1286	* Update the tracking of shadowed pages.
1287	*
1288	* @param pVM The VM handle.
1289	* @param pShwPage The shadow page.
1290	* @param HCPhys The physical page we is being dereferenced.
1291	*/
1292	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1293	{
1294	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1295	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1296	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1297
1298	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1299	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1300	* 2. write protect all shadowed pages. I.e. implement caching.
1301	*/
1302	/*
1303	* Find the guest address.
1304	*/
1305	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1306	pRam;
1307	pRam = CTXALLSUFF(pRam->pNext))
1308	{
1309	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1310	while (iPage-- > 0)
1311	{
1312	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1313	{
1314	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1315	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1316	pShwPage->cPresent--;
1317	pPool->cPresent--;
1318	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1319	return;
1320	}
1321	}
1322	}
1323
1324	for (;;)
1325	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1326	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1327	pShwPage->cPresent--;
1328	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1329	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1330	}
1331
1332
1333	/**
1334	* Update the tracking of shadowed pages.
1335	*
1336	* @param pVM The VM handle.
1337	* @param pShwPage The shadow page.
1338	* @param u16 The top 16-bit of the pPage->HCPhys.
1339	* @param pPage Pointer to the guest page. this will be modified.
1340	* @param iPTDst The index into the shadow table.
1341	*/
1342	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1343	{
1344	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1345	/*
1346	* We're making certain assumptions about the placement of cRef and idx.
1347	*/
1348	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1349	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1350
1351	/*
1352	* Just deal with the simple first time here.
1353	*/
1354	if (!u16)
1355	{
1356	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1357	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1358	}
1359	else
1360	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1361
1362	/* write back, trying to be clever... */
1363	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1364	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1365	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1366	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1367
1368	/* update statistics. */
1369	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1370	pShwPage->cPresent++;
1371	if (pShwPage->iFirstPresent > iPTDst)
1372	pShwPage->iFirstPresent = iPTDst;
1373	}
1374	#endif /* PGMPOOL_WITH_USER_TRACKING */
1375
1376
1377	/**
1378	* Creates a 4K shadow page for a guest page.
1379	*
1380	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1381	* physical address. The PdeSrc argument only the flags are used. No page structured
1382	* will be mapped in this function.
1383	*
1384	* @param pVM VM handle.
1385	* @param pPteDst Destination page table entry.
1386	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1387	* Can safely assume that only the flags are being used.
1388	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1389	* @param pShwPage Pointer to the shadow page.
1390	* @param iPTDst The index into the shadow table.
1391	*
1392	* @remark Not used for 2/4MB pages!
1393	*/
1394	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1395	{
1396	if (PteSrc.n.u1Present)
1397	{
1398	/*
1399	* Find the ram range.
1400	*/
1401	PPGMPAGE pPage;
1402	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1403	if (VBOX_SUCCESS(rc))
1404	{
1405	/** @todo investiage PWT, PCD and PAT. */
1406	/*
1407	* Make page table entry.
1408	*/
1409	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1410	SHWPTE PteDst;
1411	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1412	{
1413	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1414	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1415	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1416	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1417	else
1418	{
1419	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1420	PteDst.u = 0;
1421	}
1422	/** @todo count these two kinds. */
1423	}
1424	else
1425	{
1426	/*
1427	* If the page or page directory entry is not marked accessed,
1428	* we mark the page not present.
1429	*/
1430	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1431	{
1432	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1433	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1434	PteDst.u = 0;
1435	}
1436	else
1437	/*
1438	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1439	* when the page is modified.
1440	*/
1441	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1442	{
1443	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1444	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1445	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1446	\| PGM_PTFLAGS_TRACK_DIRTY;
1447	}
1448	else
1449	{
1450	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1451	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1452	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1453	}
1454	}
1455
1456	#ifdef PGMPOOL_WITH_USER_TRACKING
1457	/*
1458	* Keep user track up to date.
1459	*/
1460	if (PteDst.n.u1Present)
1461	{
1462	if (!pPteDst->n.u1Present)
1463	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1464	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1465	{
1466	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1467	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1468	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1469	}
1470	}
1471	else if (pPteDst->n.u1Present)
1472	{
1473	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1474	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1475	}
1476	#endif /* PGMPOOL_WITH_USER_TRACKING */
1477
1478	/*
1479	* Update statistics and commit the entry.
1480	*/
1481	if (!PteSrc.n.u1Global)
1482	pShwPage->fSeenNonGlobal = true;
1483	*pPteDst = PteDst;
1484	}
1485	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1486	/** @todo count these. */
1487	}
1488	else
1489	{
1490	/*
1491	* Page not-present.
1492	*/
1493	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1494	#ifdef PGMPOOL_WITH_USER_TRACKING
1495	/* Keep user track up to date. */
1496	if (pPteDst->n.u1Present)
1497	{
1498	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1499	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1500	}
1501	#endif /* PGMPOOL_WITH_USER_TRACKING */
1502	pPteDst->u = 0;
1503	/** @todo count these. */
1504	}
1505	}
1506
1507
1508	/**
1509	* Syncs a guest OS page.
1510	*
1511	* There are no conflicts at this point, neither is there any need for
1512	* page table allocations.
1513	*
1514	* @returns VBox status code.
1515	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1516	* @param pVM VM handle.
1517	* @param PdeSrc Page directory entry of the guest.
1518	* @param GCPtrPage Guest context page address.
1519	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1520	* @param uErr Fault error (X86_TRAP_PF_*).
1521	*/
1522	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1523	{
1524	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1525
1526	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1527	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1528	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1529	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1530
1531	# if PGM_WITH_NX(PGM_GST_TYPE)
1532	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1533	# endif
1534
1535	/*
1536	* Assert preconditions.
1537	*/
1538	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1539	Assert(PdeSrc.n.u1Present);
1540	Assert(cPages);
1541
1542	/*
1543	* Get the shadow PDE, find the shadow page table in the pool.
1544	*/
1545	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1546	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1547	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1548	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1549	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1550	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte); /* no mask; flat index into the 2048 entry array. */
1551	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
1552	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1553	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1554	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1555	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1556	PX86PDPAE pPDDst;
1557	X86PDEPAE PdeDst;
1558	PX86PDPT pPdptDst;
1559
1560	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1561	AssertRCReturn(rc, rc);
1562	Assert(pPDDst && pPdptDst);
1563	PdeDst = pPDDst->a[iPDDst];
1564	# endif
1565	Assert(PdeDst.n.u1Present);
1566	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1567
1568	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1569	/* Fetch the pgm pool shadow descriptor. */
1570	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1571	Assert(pShwPde);
1572	# endif
1573
1574	/*
1575	* Check that the page is present and that the shadow PDE isn't out of sync.
1576	*/
1577	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1578	const bool fBigPage = PdeSrc.b.u1Size;
1579	# else
1580	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1581	# endif
1582	RTGCPHYS GCPhys;
1583	if (!fBigPage)
1584	{
1585	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1586	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1587	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1588	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1589	# endif
1590	}
1591	else
1592	{
1593	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1594	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1595	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1596	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1597	# endif
1598	}
1599	if ( pShwPage->GCPhys == GCPhys
1600	&& PdeSrc.n.u1Present
1601	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1602	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1603	# if PGM_WITH_NX(PGM_GST_TYPE)
1604	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1605	# endif
1606	)
1607	{
1608	/*
1609	* Check that the PDE is marked accessed already.
1610	* Since we set the accessed bit before getting here on a #PF, this
1611	* check is only meant for dealing with non-#PF'ing paths.
1612	*/
1613	if (PdeSrc.n.u1Accessed)
1614	{
1615	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1616	if (!fBigPage)
1617	{
1618	/*
1619	* 4KB Page - Map the guest page table.
1620	*/
1621	PGSTPT pPTSrc;
1622	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1623	if (VBOX_SUCCESS(rc))
1624	{
1625	# ifdef PGM_SYNC_N_PAGES
1626	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1627	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1628	{
1629	/*
1630	* This code path is currently only taken when the caller is PGMTrap0eHandler
1631	* for non-present pages!
1632	*
1633	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1634	* deal with locality.
1635	*/
1636	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1637	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1638	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1639	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1640	# else
1641	const unsigned offPTSrc = 0;
1642	# endif
1643	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1644	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1645	iPTDst = 0;
1646	else
1647	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1648	for (; iPTDst < iPTDstEnd; iPTDst++)
1649	{
1650	if (!pPTDst->a[iPTDst].n.u1Present)
1651	{
1652	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1653	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1654	NOREF(GCPtrCurPage);
1655	#ifndef IN_RING0
1656	/*
1657	* Assuming kernel code will be marked as supervisor - and not as user level
1658	* and executed using a conforming code selector - And marked as readonly.
1659	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1660	*/
1661	PPGMPAGE pPage;
1662	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1663	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1664	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1665	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1666	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1667	)
1668	#endif /* else: CSAM not active */
1669	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1670	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1671	GCPtrCurPage, PteSrc.n.u1Present,
1672	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1673	PteSrc.n.u1User & PdeSrc.n.u1User,
1674	(uint64_t)PteSrc.u,
1675	(uint64_t)pPTDst->a[iPTDst].u,
1676	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1677	}
1678	}
1679	}
1680	else
1681	# endif /* PGM_SYNC_N_PAGES */
1682	{
1683	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1684	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1685	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1686	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1687	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1688	GCPtrPage, PteSrc.n.u1Present,
1689	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1690	PteSrc.n.u1User & PdeSrc.n.u1User,
1691	(uint64_t)PteSrc.u,
1692	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1693	}
1694	}
1695	else /* MMIO or invalid page: emulated in #PF handler. */
1696	{
1697	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1698	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1699	}
1700	}
1701	else
1702	{
1703	/*
1704	* 4/2MB page - lazy syncing shadow 4K pages.
1705	* (There are many causes of getting here, it's no longer only CSAM.)
1706	*/
1707	/* Calculate the GC physical address of this 4KB shadow page. */
1708	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1709	/* Find ram range. */
1710	PPGMPAGE pPage;
1711	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1712	if (VBOX_SUCCESS(rc))
1713	{
1714	/*
1715	* Make shadow PTE entry.
1716	*/
1717	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1718	SHWPTE PteDst;
1719	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1720	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1721	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1722	{
1723	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1724	PteDst.n.u1Write = 0;
1725	else
1726	PteDst.u = 0;
1727	}
1728	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1729	# ifdef PGMPOOL_WITH_USER_TRACKING
1730	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1731	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1732	# endif
1733	pPTDst->a[iPTDst] = PteDst;
1734
1735
1736	/*
1737	* If the page is not flagged as dirty and is writable, then make it read-only
1738	* at PD level, so we can set the dirty bit when the page is modified.
1739	*
1740	* ASSUMES that page access handlers are implemented on page table entry level.
1741	* Thus we will first catch the dirty access and set PDE.D and restart. If
1742	* there is an access handler, we'll trap again and let it work on the problem.
1743	*/
1744	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1745	* As for invlpg, it simply frees the whole shadow PT.
1746	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1747	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1748	{
1749	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1750	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1751	PdeDst.n.u1Write = 0;
1752	}
1753	else
1754	{
1755	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1756	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1757	}
1758	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1759	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1760	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1761	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1762	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1763	pPDDst->a[iPDDst] = PdeDst;
1764	# endif
1765	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1766	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1767	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1768	}
1769	else
1770	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1771	}
1772	return VINF_SUCCESS;
1773	}
1774	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1775	}
1776	else
1777	{
1778	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1779	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1780	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1781	}
1782
1783	/*
1784	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1785	* Yea, I'm lazy.
1786	*/
1787	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1788	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1789	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1790	# else
1791	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1792	# endif
1793
1794	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1795	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1796	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1797	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1798	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1799	pPDDst->a[iPDDst].u = 0;
1800	# endif
1801	PGM_INVL_GUEST_TLBS();
1802	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1803
1804	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1805	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
1806
1807	# ifdef PGM_SYNC_N_PAGES
1808	/*
1809	* Get the shadow PDE, find the shadow page table in the pool.
1810	*/
1811	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1812	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1813	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1814	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1815	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
1816	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1817	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1818	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1819	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpte);
1820	PX86PDPAE pPDDst;
1821	X86PDEPAE PdeDst;
1822	PX86PDPT pPdptDst;
1823
1824	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1825	AssertRCReturn(rc, rc);
1826	Assert(pPDDst && pPdptDst);
1827	PdeDst = pPDDst->a[iPDDst];
1828	# endif
1829	Assert(PdeDst.n.u1Present);
1830	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1831	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1832
1833	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1834	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1835	{
1836	/*
1837	* This code path is currently only taken when the caller is PGMTrap0eHandler
1838	* for non-present pages!
1839	*
1840	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1841	* deal with locality.
1842	*/
1843	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1844	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1845	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1846	iPTDst = 0;
1847	else
1848	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1849	for (; iPTDst < iPTDstEnd; iPTDst++)
1850	{
1851	if (!pPTDst->a[iPTDst].n.u1Present)
1852	{
1853	GSTPTE PteSrc;
1854
1855	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1856
1857	/* Fake the page table entry */
1858	PteSrc.u = GCPtrCurPage;
1859	PteSrc.n.u1Present = 1;
1860	PteSrc.n.u1Dirty = 1;
1861	PteSrc.n.u1Accessed = 1;
1862	PteSrc.n.u1Write = 1;
1863	PteSrc.n.u1User = 1;
1864
1865	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1866
1867	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1868	GCPtrCurPage, PteSrc.n.u1Present,
1869	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1870	PteSrc.n.u1User & PdeSrc.n.u1User,
1871	(uint64_t)PteSrc.u,
1872	(uint64_t)pPTDst->a[iPTDst].u,
1873	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1874	}
1875	else
1876	Log4(("%VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1877	}
1878	}
1879	else
1880	# endif /* PGM_SYNC_N_PAGES */
1881	{
1882	GSTPTE PteSrc;
1883	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1884	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1885
1886	/* Fake the page table entry */
1887	PteSrc.u = GCPtrCurPage;
1888	PteSrc.n.u1Present = 1;
1889	PteSrc.n.u1Dirty = 1;
1890	PteSrc.n.u1Accessed = 1;
1891	PteSrc.n.u1Write = 1;
1892	PteSrc.n.u1User = 1;
1893	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1894
1895	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1896	GCPtrPage, PteSrc.n.u1Present,
1897	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1898	PteSrc.n.u1User & PdeSrc.n.u1User,
1899	(uint64_t)PteSrc.u,
1900	(uint64_t)pPTDst->a[iPTDst].u,
1901	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1902	}
1903	return VINF_SUCCESS;
1904
1905	#else
1906	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1907	return VERR_INTERNAL_ERROR;
1908	#endif
1909	}
1910
1911
1912
1913	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1914
1915	/**
1916	* Investigate page fault and handle write protection page faults caused by
1917	* dirty bit tracking.
1918	*
1919	* @returns VBox status code.
1920	* @param pVM VM handle.
1921	* @param uErr Page fault error code.
1922	* @param pPdeDst Shadow page directory entry.
1923	* @param pPdeSrc Guest page directory entry.
1924	* @param GCPtrPage Guest context page address.
1925	*/
1926	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1927	{
1928	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1929	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1930	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1931	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1932	bool fBigPagesSupported = true;
1933	# else
1934	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1935	# endif
1936	# if PGM_WITH_NX(PGM_GST_TYPE)
1937	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1938	# endif
1939	unsigned uPageFaultLevel;
1940	int rc;
1941
1942	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1943	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1944
1945	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1946	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1947
1948	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1949	PX86PML4E pPml4eSrc;
1950	PX86PDPE pPdpeSrc;
1951
1952	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
1953	Assert(pPml4eSrc);
1954
1955	/*
1956	* Real page fault? (PML4E level)
1957	*/
1958	if ( (uErr & X86_TRAP_PF_RSVD)
1959	\|\| !pPml4eSrc->n.u1Present
1960	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
1961	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1962	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
1963	)
1964	{
1965	uPageFaultLevel = 0;
1966	goto UpperLevelPageFault;
1967	}
1968	Assert(pPdpeSrc);
1969
1970	# else /* PAE */
1971	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1972	# endif
1973
1974	/*
1975	* Real page fault? (PDPE level)
1976	*/
1977	if ( (uErr & X86_TRAP_PF_RSVD)
1978	\|\| !pPdpeSrc->n.u1Present
1979	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1980	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
1981	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
1982	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
1983	# endif
1984	)
1985	{
1986	uPageFaultLevel = 1;
1987	goto UpperLevelPageFault;
1988	}
1989	# endif
1990
1991	/*
1992	* Real page fault? (PDE level)
1993	*/
1994	if ( (uErr & X86_TRAP_PF_RSVD)
1995	\|\| !pPdeSrc->n.u1Present
1996	# if PGM_WITH_NX(PGM_GST_TYPE)
1997	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1998	# endif
1999	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2000	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2001	{
2002	uPageFaultLevel = 2;
2003	goto UpperLevelPageFault;
2004	}
2005
2006	/*
2007	* First check the easy case where the page directory has been marked read-only to track
2008	* the dirty bit of an emulated BIG page
2009	*/
2010	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2011	{
2012	/* Mark guest page directory as accessed */
2013	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2014	pPml4eSrc->n.u1Accessed = 1;
2015	pPdpeSrc->lm.u1Accessed = 1;
2016	# endif
2017	pPdeSrc->b.u1Accessed = 1;
2018
2019	/*
2020	* Only write protection page faults are relevant here.
2021	*/
2022	if (fWriteFault)
2023	{
2024	/* Mark guest page directory as dirty (BIG page only). */
2025	pPdeSrc->b.u1Dirty = 1;
2026
2027	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2028	{
2029	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
2030
2031	Assert(pPdeSrc->b.u1Write);
2032
2033	pPdeDst->n.u1Write = 1;
2034	pPdeDst->n.u1Accessed = 1;
2035	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2036	PGM_INVL_BIG_PG(GCPtrPage);
2037	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2038	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2039	}
2040	}
2041	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2042	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2043	}
2044	/* else: 4KB page table */
2045
2046	/*
2047	* Map the guest page table.
2048	*/
2049	PGSTPT pPTSrc;
2050	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2051	if (VBOX_SUCCESS(rc))
2052	{
2053	/*
2054	* Real page fault?
2055	*/
2056	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2057	const GSTPTE PteSrc = *pPteSrc;
2058	if ( !PteSrc.n.u1Present
2059	# if PGM_WITH_NX(PGM_GST_TYPE)
2060	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2061	# endif
2062	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2063	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2064	)
2065	{
2066	# ifdef IN_GC
2067	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2068	# endif
2069	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2070	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2071
2072	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2073	* See the 2nd case above as well.
2074	*/
2075	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2076	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2077
2078	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2079	return VINF_EM_RAW_GUEST_TRAP;
2080	}
2081	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2082
2083	/*
2084	* Set the accessed bits in the page directory and the page table.
2085	*/
2086	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2087	pPml4eSrc->n.u1Accessed = 1;
2088	pPdpeSrc->lm.u1Accessed = 1;
2089	# endif
2090	pPdeSrc->n.u1Accessed = 1;
2091	pPteSrc->n.u1Accessed = 1;
2092
2093	/*
2094	* Only write protection page faults are relevant here.
2095	*/
2096	if (fWriteFault)
2097	{
2098	/* Write access, so mark guest entry as dirty. */
2099	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
2100	if (!pPteSrc->n.u1Dirty)
2101	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
2102	else
2103	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
2104	# endif
2105
2106	pPteSrc->n.u1Dirty = 1;
2107
2108	if (pPdeDst->n.u1Present)
2109	{
2110	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2111	* Our individual shadow handlers will provide more information and force a fatal exit.
2112	*/
2113	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2114	{
2115	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2116	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2117	return VINF_SUCCESS;
2118	}
2119
2120	/*
2121	* Map shadow page table.
2122	*/
2123	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2124	if (pShwPage)
2125	{
2126	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2127	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2128	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2129	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2130	{
2131	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2132	# ifdef VBOX_STRICT
2133	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2134	if (pPage)
2135	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2136	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2137	# endif
2138	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
2139
2140	Assert(pPteSrc->n.u1Write);
2141
2142	pPteDst->n.u1Write = 1;
2143	pPteDst->n.u1Dirty = 1;
2144	pPteDst->n.u1Accessed = 1;
2145	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2146	PGM_INVL_PG(GCPtrPage);
2147
2148	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2149	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2150	}
2151	}
2152	else
2153	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2154	}
2155	}
2156	/** @todo Optimize accessed bit emulation? */
2157	# ifdef VBOX_STRICT
2158	/*
2159	* Sanity check.
2160	*/
2161	else if ( !pPteSrc->n.u1Dirty
2162	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2163	&& pPdeDst->n.u1Present)
2164	{
2165	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2166	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2167	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2168	if ( pPteDst->n.u1Present
2169	&& pPteDst->n.u1Write)
2170	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2171	}
2172	# endif /* VBOX_STRICT */
2173	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2174	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2175	}
2176	AssertRC(rc);
2177	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
2178	return rc;
2179
2180
2181	UpperLevelPageFault:
2182	/* Pagefault detected while checking the PML4E, PDPE or PDE.
2183	* Single exit handler to get rid of duplicate code paths.
2184	*/
2185	# ifdef IN_GC
2186	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
2187	# endif
2188	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
2189	LogFlow(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2190
2191	if (
2192	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2193	pPml4eSrc->n.u1Present &&
2194	# endif
2195	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2196	pPdpeSrc->n.u1Present &&
2197	# endif
2198	pPdeSrc->n.u1Present)
2199	{
2200	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2201	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2202	{
2203	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2204	}
2205	else
2206	{
2207	/*
2208	* Map the guest page table.
2209	*/
2210	PGSTPT pPTSrc;
2211	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2212	if (VBOX_SUCCESS(rc))
2213	{
2214	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2215	const GSTPTE PteSrc = *pPteSrc;
2216	if (pPteSrc->n.u1Present)
2217	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2218	}
2219	AssertRC(rc);
2220	}
2221	}
2222	return VINF_EM_RAW_GUEST_TRAP;
2223	}
2224
2225	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2226
2227
2228	/**
2229	* Sync a shadow page table.
2230	*
2231	* The shadow page table is not present. This includes the case where
2232	* there is a conflict with a mapping.
2233	*
2234	* @returns VBox status code.
2235	* @param pVM VM handle.
2236	* @param iPD Page directory index.
2237	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2238	* Assume this is a temporary mapping.
2239	* @param GCPtrPage GC Pointer of the page that caused the fault
2240	*/
2241	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2242	{
2243	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2244	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
2245	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2246
2247	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2248	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2249	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2250	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2251
2252	int rc = VINF_SUCCESS;
2253
2254	/*
2255	* Validate input a little bit.
2256	*/
2257	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2258	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2259	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2260	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2261	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2262	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2263	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
2264	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
2265	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2266	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2267	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2268	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2269	PX86PDPAE pPDDst;
2270	PX86PDPT pPdptDst;
2271	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2272	if (rc != VINF_SUCCESS)
2273	{
2274	AssertRC(rc);
2275	return rc;
2276	}
2277	Assert(pPDDst);
2278	# endif
2279
2280	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2281	SHWPDE PdeDst = *pPdeDst;
2282
2283	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2284	/* Fetch the pgm pool shadow descriptor. */
2285	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2286	Assert(pShwPde);
2287	# endif
2288
2289	# ifndef PGM_WITHOUT_MAPPINGS
2290	/*
2291	* Check for conflicts.
2292	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2293	* HC: Simply resolve the conflict.
2294	*/
2295	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2296	{
2297	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2298	# ifndef IN_RING3
2299	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2300	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2301	return VERR_ADDRESS_CONFLICT;
2302	# else
2303	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2304	Assert(pMapping);
2305	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2306	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2307	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2308	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2309	# else
2310	AssertFailed(); /* can't happen for amd64 */
2311	# endif
2312	if (VBOX_FAILURE(rc))
2313	{
2314	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2315	return rc;
2316	}
2317	PdeDst = *pPdeDst;
2318	# endif
2319	}
2320	# else /* PGM_WITHOUT_MAPPINGS */
2321	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2322	# endif /* PGM_WITHOUT_MAPPINGS */
2323	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2324
2325	/*
2326	* Sync page directory entry.
2327	*/
2328	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2329	if (PdeSrc.n.u1Present)
2330	{
2331	/*
2332	* Allocate & map the page table.
2333	*/
2334	PSHWPT pPTDst;
2335	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2336	const bool fPageTable = !PdeSrc.b.u1Size;
2337	# else
2338	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2339	# endif
2340	PPGMPOOLPAGE pShwPage;
2341	RTGCPHYS GCPhys;
2342	if (fPageTable)
2343	{
2344	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2345	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2346	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2347	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2348	# endif
2349	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2350	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2351	# else
2352	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2353	# endif
2354	}
2355	else
2356	{
2357	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2358	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2359	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2360	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2361	# endif
2362	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2363	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2364	# else
2365	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2366	# endif
2367	}
2368	if (rc == VINF_SUCCESS)
2369	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2370	else if (rc == VINF_PGM_CACHED_PAGE)
2371	{
2372	/*
2373	* The PT was cached, just hook it up.
2374	*/
2375	if (fPageTable)
2376	PdeDst.u = pShwPage->Core.Key
2377	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2378	else
2379	{
2380	PdeDst.u = pShwPage->Core.Key
2381	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2382	/* (see explanation and assumptions further down.) */
2383	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2384	{
2385	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2386	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2387	PdeDst.b.u1Write = 0;
2388	}
2389	}
2390	*pPdeDst = PdeDst;
2391	return VINF_SUCCESS;
2392	}
2393	else if (rc == VERR_PGM_POOL_FLUSHED)
2394	{
2395	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2396	return VINF_PGM_SYNC_CR3;
2397	}
2398	else
2399	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2400	PdeDst.u &= X86_PDE_AVL_MASK;
2401	PdeDst.u \|= pShwPage->Core.Key;
2402
2403	/*
2404	* Page directory has been accessed (this is a fault situation, remember).
2405	*/
2406	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2407	if (fPageTable)
2408	{
2409	/*
2410	* Page table - 4KB.
2411	*
2412	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2413	*/
2414	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2415	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2416	PGSTPT pPTSrc;
2417	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2418	if (VBOX_SUCCESS(rc))
2419	{
2420	/*
2421	* Start by syncing the page directory entry so CSAM's TLB trick works.
2422	*/
2423	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2424	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2425	*pPdeDst = PdeDst;
2426
2427	/*
2428	* Directory/page user or supervisor privilege: (same goes for read/write)
2429	*
2430	* Directory Page Combined
2431	* U/S U/S U/S
2432	* 0 0 0
2433	* 0 1 0
2434	* 1 0 0
2435	* 1 1 1
2436	*
2437	* Simple AND operation. Table listed for completeness.
2438	*
2439	*/
2440	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2441	# ifdef PGM_SYNC_N_PAGES
2442	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2443	unsigned iPTDst = iPTBase;
2444	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2445	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2446	iPTDst = 0;
2447	else
2448	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2449	# else /* !PGM_SYNC_N_PAGES */
2450	unsigned iPTDst = 0;
2451	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2452	# endif /* !PGM_SYNC_N_PAGES */
2453	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2454	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2455	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2456	# else
2457	const unsigned offPTSrc = 0;
2458	# endif
2459	for (; iPTDst < iPTDstEnd; iPTDst++)
2460	{
2461	const unsigned iPTSrc = iPTDst + offPTSrc;
2462	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2463
2464	if (PteSrc.n.u1Present) /* we've already cleared it above */
2465	{
2466	# ifndef IN_RING0
2467	/*
2468	* Assuming kernel code will be marked as supervisor - and not as user level
2469	* and executed using a conforming code selector - And marked as readonly.
2470	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2471	*/
2472	PPGMPAGE pPage;
2473	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2474	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2475	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2476	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2477	)
2478	# endif
2479	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2480	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2481	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2482	PteSrc.n.u1Present,
2483	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2484	PteSrc.n.u1User & PdeSrc.n.u1User,
2485	(uint64_t)PteSrc.u,
2486	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2487	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2488	}
2489	} /* for PTEs */
2490	}
2491	}
2492	else
2493	{
2494	/*
2495	* Big page - 2/4MB.
2496	*
2497	* We'll walk the ram range list in parallel and optimize lookups.
2498	* We will only sync on shadow page table at a time.
2499	*/
2500	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2501
2502	/**
2503	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2504	*/
2505
2506	/*
2507	* Start by syncing the page directory entry.
2508	*/
2509	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2510	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2511
2512	/*
2513	* If the page is not flagged as dirty and is writable, then make it read-only
2514	* at PD level, so we can set the dirty bit when the page is modified.
2515	*
2516	* ASSUMES that page access handlers are implemented on page table entry level.
2517	* Thus we will first catch the dirty access and set PDE.D and restart. If
2518	* there is an access handler, we'll trap again and let it work on the problem.
2519	*/
2520	/** @todo move the above stuff to a section in the PGM documentation. */
2521	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2522	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2523	{
2524	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2525	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2526	PdeDst.b.u1Write = 0;
2527	}
2528	*pPdeDst = PdeDst;
2529
2530	/*
2531	* Fill the shadow page table.
2532	*/
2533	/* Get address and flags from the source PDE. */
2534	SHWPTE PteDstBase;
2535	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2536
2537	/* Loop thru the entries in the shadow PT. */
2538	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2539	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2540	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2541	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2542	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2543	unsigned iPTDst = 0;
2544	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2545	{
2546	/* Advance ram range list. */
2547	while (pRam && GCPhys > pRam->GCPhysLast)
2548	pRam = CTXALLSUFF(pRam->pNext);
2549	if (pRam && GCPhys >= pRam->GCPhys)
2550	{
2551	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2552	do
2553	{
2554	/* Make shadow PTE. */
2555	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2556	SHWPTE PteDst;
2557
2558	/* Make sure the RAM has already been allocated. */
2559	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2560	{
2561	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2562	{
2563	# ifdef IN_RING3
2564	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2565	# else
2566	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2567	# endif
2568	if (rc != VINF_SUCCESS)
2569	return rc;
2570	}
2571	}
2572
2573	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2574	{
2575	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2576	{
2577	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2578	PteDst.n.u1Write = 0;
2579	}
2580	else
2581	PteDst.u = 0;
2582	}
2583	# ifndef IN_RING0
2584	/*
2585	* Assuming kernel code will be marked as supervisor and not as user level and executed
2586	* using a conforming code selector. Don't check for readonly, as that implies the whole
2587	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2588	*/
2589	else if ( !PdeSrc.n.u1User
2590	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2591	PteDst.u = 0;
2592	# endif
2593	else
2594	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2595	# ifdef PGMPOOL_WITH_USER_TRACKING
2596	if (PteDst.n.u1Present)
2597	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2598	# endif
2599	/* commit it */
2600	pPTDst->a[iPTDst] = PteDst;
2601	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2602	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2603	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2604
2605	/* advance */
2606	GCPhys += PAGE_SIZE;
2607	iHCPage++;
2608	iPTDst++;
2609	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2610	&& GCPhys <= pRam->GCPhysLast);
2611	}
2612	else if (pRam)
2613	{
2614	Log(("Invalid pages at %VGp\n", GCPhys));
2615	do
2616	{
2617	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2618	GCPhys += PAGE_SIZE;
2619	iPTDst++;
2620	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2621	&& GCPhys < pRam->GCPhys);
2622	}
2623	else
2624	{
2625	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2626	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2627	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2628	}
2629	} /* while more PTEs */
2630	} /* 4KB / 4MB */
2631	}
2632	else
2633	AssertRelease(!PdeDst.n.u1Present);
2634
2635	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2636	# ifdef IN_GC
2637	if (VBOX_FAILURE(rc))
2638	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2639	# endif
2640	return rc;
2641
2642	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2643	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2644
2645	int rc = VINF_SUCCESS;
2646
2647	/*
2648	* Validate input a little bit.
2649	*/
2650	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2651	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2652	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2653	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2654	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2655	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2656	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2657	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2658	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2659	PX86PDPAE pPDDst;
2660	PX86PDPT pPdptDst;
2661	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2662	if (rc != VINF_SUCCESS)
2663	{
2664	AssertRC(rc);
2665	return rc;
2666	}
2667	Assert(pPDDst);
2668
2669	/* Fetch the pgm pool shadow descriptor. */
2670	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2671	Assert(pShwPde);
2672	# endif
2673	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2674	SHWPDE PdeDst = *pPdeDst;
2675
2676	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2677	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2678
2679	GSTPDE PdeSrc;
2680	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2681	PdeSrc.n.u1Present = 1;
2682	PdeSrc.n.u1Write = 1;
2683	PdeSrc.n.u1Accessed = 1;
2684	PdeSrc.n.u1User = 1;
2685
2686	/*
2687	* Allocate & map the page table.
2688	*/
2689	PSHWPT pPTDst;
2690	PPGMPOOLPAGE pShwPage;
2691	RTGCPHYS GCPhys;
2692
2693	/* Virtual address = physical address */
2694	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2695	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2696	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2697	# else
2698	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2699	# endif
2700
2701	if ( rc == VINF_SUCCESS
2702	\|\| rc == VINF_PGM_CACHED_PAGE)
2703	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2704	else
2705	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2706
2707	PdeDst.u &= X86_PDE_AVL_MASK;
2708	PdeDst.u \|= pShwPage->Core.Key;
2709	PdeDst.n.u1Present = 1;
2710	PdeDst.n.u1Write = 1;
2711	PdeDst.n.u1User = 1;
2712	PdeDst.n.u1Accessed = 1;
2713	*pPdeDst = PdeDst;
2714
2715	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2716	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2717	return rc;
2718
2719	#else
2720	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2721	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2722	return VERR_INTERNAL_ERROR;
2723	#endif
2724	}
2725
2726
2727
2728	/**
2729	* Prefetch a page/set of pages.
2730	*
2731	* Typically used to sync commonly used pages before entering raw mode
2732	* after a CR3 reload.
2733	*
2734	* @returns VBox status code.
2735	* @param pVM VM handle.
2736	* @param GCPtrPage Page to invalidate.
2737	*/
2738	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2739	{
2740	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2741	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2742	/*
2743	* Check that all Guest levels thru the PDE are present, getting the
2744	* PD and PDE in the processes.
2745	*/
2746	int rc = VINF_SUCCESS;
2747	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2748	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2749	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2750	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2751	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2752	unsigned iPDSrc;
2753	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2754	if (!pPDSrc)
2755	return VINF_SUCCESS; /* not present */
2756	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2757	unsigned iPDSrc;
2758	PX86PML4E pPml4eSrc;
2759	X86PDPE PdpeSrc;
2760	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2761	if (!pPDSrc)
2762	return VINF_SUCCESS; /* not present */
2763	# endif
2764	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2765	# else
2766	PGSTPD pPDSrc = NULL;
2767	const unsigned iPDSrc = 0;
2768	GSTPDE PdeSrc;
2769
2770	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2771	PdeSrc.n.u1Present = 1;
2772	PdeSrc.n.u1Write = 1;
2773	PdeSrc.n.u1Accessed = 1;
2774	PdeSrc.n.u1User = 1;
2775	# endif
2776
2777	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2778	{
2779	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2780	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2781	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2782	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2783	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2784	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2785	PX86PDPAE pPDDst;
2786	X86PDEPAE PdeDst;
2787
2788	# if PGM_GST_TYPE == PGM_TYPE_PROT
2789	/* AMD-V nested paging */
2790	X86PML4E Pml4eSrc;
2791	X86PDPE PdpeSrc;
2792	PX86PML4E pPml4eSrc = &Pml4eSrc;
2793
2794	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2795	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2796	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2797	# endif
2798
2799	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2800	if (rc != VINF_SUCCESS)
2801	{
2802	AssertRC(rc);
2803	return rc;
2804	}
2805	Assert(pPDDst);
2806	PdeDst = pPDDst->a[iPDDst];
2807	# endif
2808	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2809	{
2810	if (!PdeDst.n.u1Present)
2811	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2812	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2813	else
2814	{
2815	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2816	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2817	* makes no sense to prefetch more than one page.
2818	*/
2819	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2820	if (VBOX_SUCCESS(rc))
2821	rc = VINF_SUCCESS;
2822	}
2823	}
2824	}
2825	return rc;
2826	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED
2827	return VINF_SUCCESS; /* ignore */
2828	#endif
2829	}
2830
2831
2832
2833
2834	/**
2835	* Syncs a page during a PGMVerifyAccess() call.
2836	*
2837	* @returns VBox status code (informational included).
2838	* @param GCPtrPage The address of the page to sync.
2839	* @param fPage The effective guest page flags.
2840	* @param uErr The trap error code.
2841	*/
2842	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2843	{
2844	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2845
2846	Assert(!HWACCMIsNestedPagingActive(pVM));
2847	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2848	&& PGM_SHW_TYPE != PGM_TYPE_NESTED
2849
2850	# ifndef IN_RING0
2851	if (!(fPage & X86_PTE_US))
2852	{
2853	/*
2854	* Mark this page as safe.
2855	*/
2856	/** @todo not correct for pages that contain both code and data!! */
2857	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2858	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2859	}
2860	# endif
2861	/*
2862	* Get guest PD and index.
2863	*/
2864
2865	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2866	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2867	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2868	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2869	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2870	unsigned iPDSrc;
2871	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2872
2873	if (pPDSrc)
2874	{
2875	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2876	return VINF_EM_RAW_GUEST_TRAP;
2877	}
2878	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2879	unsigned iPDSrc;
2880	PX86PML4E pPml4eSrc;
2881	X86PDPE PdpeSrc;
2882	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2883	if (!pPDSrc)
2884	{
2885	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2886	return VINF_EM_RAW_GUEST_TRAP;
2887	}
2888	# endif
2889	# else
2890	PGSTPD pPDSrc = NULL;
2891	const unsigned iPDSrc = 0;
2892	# endif
2893	int rc = VINF_SUCCESS;
2894
2895	/*
2896	* First check if the shadow pd is present.
2897	*/
2898	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2899	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2900	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2901	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2902	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2903	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2904	PX86PDPAE pPDDst;
2905	PX86PDEPAE pPdeDst;
2906
2907	# if PGM_GST_TYPE == PGM_TYPE_PROT
2908	/* AMD-V nested paging */
2909	X86PML4E Pml4eSrc;
2910	X86PDPE PdpeSrc;
2911	PX86PML4E pPml4eSrc = &Pml4eSrc;
2912
2913	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2914	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2915	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2916	# endif
2917
2918	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2919	if (rc != VINF_SUCCESS)
2920	{
2921	AssertRC(rc);
2922	return rc;
2923	}
2924	Assert(pPDDst);
2925	pPdeDst = &pPDDst->a[iPDDst];
2926	# endif
2927	if (!pPdeDst->n.u1Present)
2928	{
2929	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2930	AssertRC(rc);
2931	if (rc != VINF_SUCCESS)
2932	return rc;
2933	}
2934
2935	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2936	/* Check for dirty bit fault */
2937	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2938	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2939	Log(("PGMVerifyAccess: success (dirty)\n"));
2940	else
2941	{
2942	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2943	#else
2944	{
2945	GSTPDE PdeSrc;
2946	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2947	PdeSrc.n.u1Present = 1;
2948	PdeSrc.n.u1Write = 1;
2949	PdeSrc.n.u1Accessed = 1;
2950	PdeSrc.n.u1User = 1;
2951
2952	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2953	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2954	if (uErr & X86_TRAP_PF_US)
2955	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2956	else /* supervisor */
2957	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2958
2959	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2960	if (VBOX_SUCCESS(rc))
2961	{
2962	/* Page was successfully synced */
2963	Log2(("PGMVerifyAccess: success (sync)\n"));
2964	rc = VINF_SUCCESS;
2965	}
2966	else
2967	{
2968	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2969	return VINF_EM_RAW_GUEST_TRAP;
2970	}
2971	}
2972	return rc;
2973
2974	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2975
2976	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2977	return VERR_INTERNAL_ERROR;
2978	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2979	}
2980
2981
2982	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2983	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
2984	/**
2985	* Figures out which kind of shadow page this guest PDE warrants.
2986	*
2987	* @returns Shadow page kind.
2988	* @param pPdeSrc The guest PDE in question.
2989	* @param cr4 The current guest cr4 value.
2990	*/
2991	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2992	{
2993	# if PMG_GST_TYPE == PGM_TYPE_AMD64
2994	if (!pPdeSrc->n.u1Size)
2995	# else
2996	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2997	# endif
2998	return BTH_PGMPOOLKIND_PT_FOR_PT;
2999	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3000	//{
3001	// case 0:
3002	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3003	// case X86_PDE4M_RW:
3004	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3005	// case X86_PDE4M_US:
3006	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3007	// case X86_PDE4M_RW \| X86_PDE4M_US:
3008	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3009	# if 0
3010	// case X86_PDE4M_PAE_NX:
3011	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3012	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3013	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3014	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3015	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3016	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3017	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3018	# endif
3019	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3020	//}
3021	}
3022	# endif
3023	#endif
3024
3025	#undef MY_STAM_COUNTER_INC
3026	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3027
3028
3029	/**
3030	* Syncs the paging hierarchy starting at CR3.
3031	*
3032	* @returns VBox status code, no specials.
3033	* @param pVM The virtual machine.
3034	* @param cr0 Guest context CR0 register
3035	* @param cr3 Guest context CR3 register
3036	* @param cr4 Guest context CR4 register
3037	* @param fGlobal Including global page directories or not
3038	*/
3039	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3040	{
3041	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3042	fGlobal = true; /* Change this CR3 reload to be a global one. */
3043
3044	#if PGM_SHW_TYPE != PGM_TYPE_NESTED
3045	/*
3046	* Update page access handlers.
3047	* The virtual are always flushed, while the physical are only on demand.
3048	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3049	* have to look into that later because it will have a bad influence on the performance.
3050	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3051	* bird: Yes, but that won't work for aliases.
3052	*/
3053	/** @todo this MUST go away. See #1557. */
3054	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
3055	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3056	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
3057	#endif
3058
3059	#ifdef PGMPOOL_WITH_MONITORING
3060	int rc = pgmPoolSyncCR3(pVM);
3061	if (rc != VINF_SUCCESS)
3062	return rc;
3063	#endif
3064
3065	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
3066	/** @todo check if this is really necessary */
3067	HWACCMFlushTLB(pVM);
3068	return VINF_SUCCESS;
3069
3070	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3071	/* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
3072	return VINF_SUCCESS;
3073	#else
3074
3075	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3076	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
3077
3078	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3079	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3080	bool fBigPagesSupported = true;
3081	# else
3082	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3083	# endif
3084
3085	/*
3086	* Get page directory addresses.
3087	*/
3088	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3089	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3090	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3091	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3092	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3093	# endif
3094	# endif
3095
3096	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3097	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
3098	Assert(pPDSrc);
3099	# ifndef IN_GC
3100	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3101	# endif
3102	# endif
3103
3104	/*
3105	* Iterate the page directory.
3106	*/
3107	PPGMMAPPING pMapping;
3108	unsigned iPdNoMapping;
3109	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3110	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
3111
3112	/* Only check mappings if they are supposed to be put into the shadow page table. */
3113	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3114	{
3115	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3116	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3117	}
3118	else
3119	{
3120	pMapping = 0;
3121	iPdNoMapping = ~0U;
3122	}
3123	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3124	for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3125	{
3126	PPGMPOOLPAGE pShwPdpt = NULL;
3127	PX86PML4E pPml4eSrc, pPml4eDst;
3128	RTGCPHYS GCPhysPdptSrc;
3129
3130	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3131	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3132
3133	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3134	if (!pPml4eDst->n.u1Present)
3135	continue;
3136	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3137
3138	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3139
3140	/* Anything significant changed? */
3141	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3142	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3143	{
3144	/* Free it. */
3145	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3146	(uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3147	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
3148	pPml4eDst->u = 0;
3149	continue;
3150	}
3151	/* Force an attribute sync. */
3152	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3153	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3154	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3155
3156	# else
3157	{
3158	# endif
3159	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3160	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3161	{
3162	unsigned iPDSrc;
3163	# if PGM_GST_TYPE == PGM_TYPE_PAE
3164	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3165	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3166	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
3167	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
3168	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3169
3170	if (pPDSrc == NULL)
3171	{
3172	/* PDPE not present */
3173	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
3174	{
3175	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3176	/* for each page directory entry */
3177	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3178	{
3179	if ( pPDEDst[iPD].n.u1Present
3180	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3181	{
3182	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3183	pPDEDst[iPD].u = 0;
3184	}
3185	}
3186	}
3187	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3188	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
3189	continue;
3190	}
3191	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3192	PPGMPOOLPAGE pShwPde = NULL;
3193	RTGCPHYS GCPhysPdeSrc;
3194	PX86PDPE pPdpeDst;
3195	PX86PML4E pPml4eSrc;
3196	X86PDPE PdpeSrc;
3197	PX86PDPT pPdptDst;
3198	PX86PDPAE pPDDst;
3199	PX86PDEPAE pPDEDst;
3200	RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3201	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3202
3203	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3204	if (rc != VINF_SUCCESS)
3205	{
3206	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3207	break; /* next PML4E */
3208
3209	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3210	continue; /* next PDPTE */
3211	}
3212	Assert(pPDDst);
3213	pPDEDst = &pPDDst->a[0];
3214	Assert(iPDSrc == 0);
3215
3216	pPdpeDst = &pPdptDst->a[iPdpte];
3217
3218	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3219	if (!pPdpeDst->n.u1Present)
3220	continue; /* next PDPTE */
3221
3222	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3223	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3224
3225	/* Anything significant changed? */
3226	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3227	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3228	{
3229	/* Free it. */
3230	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3231	((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3232
3233	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3234	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3235	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3236	pPdpeDst->u = 0;
3237	continue; /* next guest PDPTE */
3238	}
3239	/* Force an attribute sync. */
3240	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3241	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3242	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3243	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3244
3245	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3246	{
3247	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3248	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3249	{
3250	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3251	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3252	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3253	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3254	# endif
3255	register GSTPDE PdeSrc = pPDSrc->a[iPD];
3256	if ( PdeSrc.n.u1Present
3257	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3258	{
3259	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3260	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3261	&& !defined(PGM_WITHOUT_MAPPINGS)
3262
3263	/*
3264	* Check for conflicts with GC mappings.
3265	*/
3266	# if PGM_GST_TYPE == PGM_TYPE_PAE
3267	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3268	# else
3269	if (iPD == iPdNoMapping)
3270	# endif
3271	{
3272	if (pVM->pgm.s.fMappingsFixed)
3273	{
3274	/* It's fixed, just skip the mapping. */
3275	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3276	iPD += cPTs - 1;
3277	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3278	pMapping = pMapping->CTXALLSUFF(pNext);
3279	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3280	continue;
3281	}
3282	# ifdef IN_RING3
3283	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3284	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3285	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3286	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3287	# endif
3288	if (VBOX_FAILURE(rc))
3289	return rc;
3290
3291	/*
3292	* Update iPdNoMapping and pMapping.
3293	*/
3294	pMapping = pVM->pgm.s.pMappingsR3;
3295	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3296	pMapping = pMapping->pNextR3;
3297	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3298	# else
3299	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3300	return VINF_PGM_SYNC_CR3;
3301	# endif
3302	}
3303	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3304	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3305	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3306	/*
3307	* Sync page directory entry.
3308	*
3309	* The current approach is to allocated the page table but to set
3310	* the entry to not-present and postpone the page table synching till
3311	* it's actually used.
3312	*/
3313	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3314	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3315	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3316	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3317	# else
3318	const unsigned iPdShw = iPD; NOREF(iPdShw);
3319	# endif
3320	{
3321	SHWPDE PdeDst = *pPDEDst;
3322	if (PdeDst.n.u1Present)
3323	{
3324	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3325	RTGCPHYS GCPhys;
3326	if ( !PdeSrc.b.u1Size
3327	\|\| !fBigPagesSupported)
3328	{
3329	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3330	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3331	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3332	GCPhys \|= i * (PAGE_SIZE / 2);
3333	# endif
3334	}
3335	else
3336	{
3337	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3338	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3339	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3340	GCPhys \|= i * X86_PAGE_2M_SIZE;
3341	# endif
3342	}
3343
3344	if ( pShwPage->GCPhys == GCPhys
3345	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3346	&& ( pShwPage->fCached
3347	\|\| ( !fGlobal
3348	&& ( false
3349	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3350	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3351	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3352	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3353	# else
3354	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3355	# endif
3356	\|\| ( !pShwPage->fSeenNonGlobal
3357	&& (cr4 & X86_CR4_PGE))
3358	# endif
3359	)
3360	)
3361	)
3362	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3363	\|\| ( fBigPagesSupported
3364	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3365	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3366	)
3367	)
3368	{
3369	# ifdef VBOX_WITH_STATISTICS
3370	if ( !fGlobal
3371	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3372	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3373	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3374	# else
3375	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3376	# endif
3377	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
3378	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3379	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
3380	else
3381	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
3382	# endif /* VBOX_WITH_STATISTICS */
3383	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3384	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3385	//# ifdef PGMPOOL_WITH_CACHE
3386	// pgmPoolCacheUsed(pPool, pShwPage);
3387	//# endif
3388	}
3389	else
3390	{
3391	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3392	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3393	# else
3394	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3395	# endif
3396	pPDEDst->u = 0;
3397	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
3398	}
3399	}
3400	else
3401	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
3402	pPDEDst++;
3403	}
3404	}
3405	# if PGM_GST_TYPE == PGM_TYPE_PAE
3406	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3407	# else
3408	else if (iPD != iPdNoMapping)
3409	# endif
3410	{
3411	/*
3412	* Check if there is any page directory to mark not present here.
3413	*/
3414	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3415	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3416	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3417	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3418	# else
3419	const unsigned iPdShw = iPD; NOREF(iPdShw);
3420	# endif
3421	{
3422	if (pPDEDst->n.u1Present)
3423	{
3424	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3425	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3426	# else
3427	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3428	# endif
3429	pPDEDst->u = 0;
3430	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
3431	}
3432	pPDEDst++;
3433	}
3434	}
3435	else
3436	{
3437	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3438	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3439	&& !defined(PGM_WITHOUT_MAPPINGS)
3440
3441	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3442
3443	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3444	if (pVM->pgm.s.fMappingsFixed)
3445	{
3446	/* It's fixed, just skip the mapping. */
3447	pMapping = pMapping->CTXALLSUFF(pNext);
3448	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3449	}
3450	else
3451	{
3452	/*
3453	* Check for conflicts for subsequent pagetables
3454	* and advance to the next mapping.
3455	*/
3456	iPdNoMapping = ~0U;
3457	unsigned iPT = cPTs;
3458	while (iPT-- > 1)
3459	{
3460	if ( pPDSrc->a[iPD + iPT].n.u1Present
3461	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3462	{
3463	# ifdef IN_RING3
3464	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3465	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3466	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3467	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3468	# endif
3469	if (VBOX_FAILURE(rc))
3470	return rc;
3471
3472	/*
3473	* Update iPdNoMapping and pMapping.
3474	*/
3475	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
3476	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3477	pMapping = pMapping->CTXALLSUFF(pNext);
3478	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3479	break;
3480	# else
3481	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3482	return VINF_PGM_SYNC_CR3;
3483	# endif
3484	}
3485	}
3486	if (iPdNoMapping == ~0U && pMapping)
3487	{
3488	pMapping = pMapping->CTXALLSUFF(pNext);
3489	if (pMapping)
3490	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3491	}
3492	}
3493
3494	/* advance. */
3495	iPD += cPTs - 1;
3496	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3497	# if PGM_GST_TYPE != PGM_SHW_TYPE
3498	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3499	# endif
3500	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3501	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3502	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3503	}
3504
3505	} /* for iPD */
3506	} /* for each PDPTE (PAE) */
3507	} /* for each page map level 4 entry (amd64) */
3508	return VINF_SUCCESS;
3509
3510	# else /* guest real and protected mode */
3511	return VINF_SUCCESS;
3512	# endif
3513	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
3514	}
3515
3516
3517
3518
3519	#ifdef VBOX_STRICT
3520	#ifdef IN_GC
3521	# undef AssertMsgFailed
3522	# define AssertMsgFailed Log
3523	#endif
3524	#ifdef IN_RING3
3525	# include <VBox/dbgf.h>
3526
3527	/**
3528	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3529	*
3530	* @returns VBox status code (VINF_SUCCESS).
3531	* @param pVM The VM handle.
3532	* @param cr3 The root of the hierarchy.
3533	* @param crr The cr4, only PAE and PSE is currently used.
3534	* @param fLongMode Set if long mode, false if not long mode.
3535	* @param cMaxDepth Number of levels to dump.
3536	* @param pHlp Pointer to the output functions.
3537	*/
3538	__BEGIN_DECLS
3539	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3540	__END_DECLS
3541
3542	#endif
3543
3544	/**
3545	* Checks that the shadow page table is in sync with the guest one.
3546	*
3547	* @returns The number of errors.
3548	* @param pVM The virtual machine.
3549	* @param cr3 Guest context CR3 register
3550	* @param cr4 Guest context CR4 register
3551	* @param GCPtr Where to start. Defaults to 0.
3552	* @param cb How much to check. Defaults to everything.
3553	*/
3554	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3555	{
3556	#if PGM_SHW_TYPE == PGM_TYPE_NESTED
3557	return 0;
3558	#else
3559	unsigned cErrors = 0;
3560
3561	#if PGM_GST_TYPE == PGM_TYPE_PAE
3562	/* @todo currently broken; crashes below somewhere */
3563	AssertFailed();
3564	#endif
3565
3566	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3567	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3568	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3569
3570	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3571	bool fBigPagesSupported = true;
3572	# else
3573	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3574	# endif
3575	PPGM pPGM = &pVM->pgm.s;
3576	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3577	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3578	# ifndef IN_RING0
3579	RTHCPHYS HCPhys; /* general usage. */
3580	# endif
3581	int rc;
3582
3583	/*
3584	* Check that the Guest CR3 and all its mappings are correct.
3585	*/
3586	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3587	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3588	false);
3589	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3590	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3591	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3592	# else
3593	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3594	# endif
3595	AssertRCReturn(rc, 1);
3596	HCPhys = NIL_RTHCPHYS;
3597	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3598	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3599	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3600	RTGCPHYS GCPhys;
3601	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3602	AssertRCReturn(rc, 1);
3603	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3604	# endif
3605	#endif /* !IN_RING0 */
3606
3607	/*
3608	* Get and check the Shadow CR3.
3609	*/
3610	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3611	unsigned cPDEs = X86_PG_ENTRIES;
3612	unsigned ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3613	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3614	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3615	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3616	# else
3617	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3618	# endif
3619	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3620	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3621	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3622	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3623	# endif
3624	if (cb != ~(RTGCUINTPTR)0)
3625	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3626
3627	/** @todo call the other two PGMAssert() functions. /
3628
3629	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3630	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
3631	# endif
3632
3633	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3634	unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3635
3636	for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3637	{
3638	PPGMPOOLPAGE pShwPdpt = NULL;
3639	PX86PML4E pPml4eSrc, pPml4eDst;
3640	RTGCPHYS GCPhysPdptSrc;
3641
3642	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3643	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3644
3645	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3646	if (!pPml4eDst->n.u1Present)
3647	{
3648	GCPtr += UINT64_C(_2M * 512 * 512);
3649	continue;
3650	}
3651
3652	# if PGM_GST_TYPE == PGM_TYPE_PAE
3653	/* not correct to call pgmPoolGetPage */
3654	AssertFailed();
3655	# endif
3656	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3657	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3658
3659	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3660	{
3661	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3662	GCPtr += UINT64_C(_2M * 512 * 512);
3663	cErrors++;
3664	continue;
3665	}
3666
3667	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3668	{
3669	AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3670	GCPtr += UINT64_C(_2M * 512 * 512);
3671	cErrors++;
3672	continue;
3673	}
3674
3675	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3676	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3677	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3678	{
3679	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3680	GCPtr += UINT64_C(_2M * 512 * 512);
3681	cErrors++;
3682	continue;
3683	}
3684	# else
3685	{
3686	# endif
3687
3688	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3689	/*
3690	* Check the PDPTEs too.
3691	*/
3692	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3693
3694	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3695	{
3696	unsigned iPDSrc;
3697	PPGMPOOLPAGE pShwPde = NULL;
3698	PX86PDPE pPdpeDst;
3699	RTGCPHYS GCPhysPdeSrc;
3700	# if PGM_GST_TYPE == PGM_TYPE_PAE
3701	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3702	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
3703	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3704	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3705	# else
3706	PX86PML4E pPml4eSrc;
3707	X86PDPE PdpeSrc;
3708	PX86PDPT pPdptDst;
3709	PX86PDPAE pPDDst;
3710	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3711
3712	rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3713	if (rc != VINF_SUCCESS)
3714	{
3715	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3716	GCPtr += 512 * _2M;
3717	continue; /* next PDPTE */
3718	}
3719	Assert(pPDDst);
3720	# endif
3721	Assert(iPDSrc == 0);
3722
3723	pPdpeDst = &pPdptDst->a[iPdpte];
3724
3725	if (!pPdpeDst->n.u1Present)
3726	{
3727	GCPtr += 512 * _2M;
3728	continue; /* next PDPTE */
3729	}
3730
3731	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3732	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3733
3734	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3735	{
3736	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3737	GCPtr += 512 * _2M;
3738	cErrors++;
3739	continue;
3740	}
3741
3742	if (GCPhysPdeSrc != pShwPde->GCPhys)
3743	{
3744	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3745	AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3746	# else
3747	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3748	# endif
3749	GCPtr += 512 * _2M;
3750	cErrors++;
3751	continue;
3752	}
3753
3754	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3755	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3756	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3757	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3758	{
3759	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3760	GCPtr += 512 * _2M;
3761	cErrors++;
3762	continue;
3763	}
3764	# endif
3765
3766	# else
3767	{
3768	# endif
3769	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3770	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3771	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3772	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3773	# else
3774	const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3775	# endif
3776	# endif
3777	/*
3778	* Iterate the shadow page directory.
3779	*/
3780	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3781	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3782
3783	for (;
3784	iPDDst < cPDEs;
3785	iPDDst++, GCPtr += ulIncrement)
3786	{
3787	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3788	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3789	{
3790	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3791	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3792	{
3793	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3794	cErrors++;
3795	continue;
3796	}
3797	}
3798	else if ( (PdeDst.u & X86_PDE_P)
3799	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3800	)
3801	{
3802	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3803	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3804	if (!pPoolPage)
3805	{
3806	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3807	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3808	cErrors++;
3809	continue;
3810	}
3811	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3812
3813	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3814	{
3815	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3816	GCPtr, (uint64_t)PdeDst.u));
3817	cErrors++;
3818	}
3819
3820	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3821	{
3822	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3823	GCPtr, (uint64_t)PdeDst.u));
3824	cErrors++;
3825	}
3826
3827	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3828	if (!PdeSrc.n.u1Present)
3829	{
3830	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3831	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3832	cErrors++;
3833	continue;
3834	}
3835
3836	if ( !PdeSrc.b.u1Size
3837	\|\| !fBigPagesSupported)
3838	{
3839	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3840	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3841	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3842	# endif
3843	}
3844	else
3845	{
3846	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3847	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3848	{
3849	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3850	GCPtr, (uint64_t)PdeSrc.u));
3851	cErrors++;
3852	continue;
3853	}
3854	# endif
3855	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3856	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3857	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3858	# endif
3859	}
3860
3861	if ( pPoolPage->enmKind
3862	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3863	{
3864	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3865	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3866	cErrors++;
3867	}
3868
3869	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3870	if (!pPhysPage)
3871	{
3872	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3873	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3874	cErrors++;
3875	continue;
3876	}
3877
3878	if (GCPhysGst != pPoolPage->GCPhys)
3879	{
3880	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3881	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3882	cErrors++;
3883	continue;
3884	}
3885
3886	if ( !PdeSrc.b.u1Size
3887	\|\| !fBigPagesSupported)
3888	{
3889	/*
3890	* Page Table.
3891	*/
3892	const GSTPT *pPTSrc;
3893	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3894	if (VBOX_FAILURE(rc))
3895	{
3896	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3897	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3898	cErrors++;
3899	continue;
3900	}
3901	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3902	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3903	{
3904	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3905	// (This problem will go away when/if we shadow multiple CR3s.)
3906	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3907	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3908	cErrors++;
3909	continue;
3910	}
3911	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3912	{
3913	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3914	GCPtr, (uint64_t)PdeDst.u));
3915	cErrors++;
3916	continue;
3917	}
3918
3919	/* iterate the page table. */
3920	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3921	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3922	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3923	# else
3924	const unsigned offPTSrc = 0;
3925	# endif
3926	for (unsigned iPT = 0, off = 0;
3927	iPT < RT_ELEMENTS(pPTDst->a);
3928	iPT++, off += PAGE_SIZE)
3929	{
3930	const SHWPTE PteDst = pPTDst->a[iPT];
3931
3932	/* skip not-present entries. */
3933	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3934	continue;
3935	Assert(PteDst.n.u1Present);
3936
3937	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3938	if (!PteSrc.n.u1Present)
3939	{
3940	# ifdef IN_RING3
3941	PGMAssertHandlerAndFlagsInSync(pVM);
3942	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3943	# endif
3944	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3945	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3946	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3947	cErrors++;
3948	continue;
3949	}
3950
3951	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3952	# if 1 /** @todo sync accessed bit properly... */
3953	fIgnoreFlags \|= X86_PTE_A;
3954	# endif
3955
3956	/* match the physical addresses */
3957	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3958	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3959
3960	# ifdef IN_RING3
3961	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3962	if (VBOX_FAILURE(rc))
3963	{
3964	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3965	{
3966	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3967	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3968	cErrors++;
3969	continue;
3970	}
3971	}
3972	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3973	{
3974	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3975	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3976	cErrors++;
3977	continue;
3978	}
3979	# endif
3980
3981	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3982	if (!pPhysPage)
3983	{
3984	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3985	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3986	{
3987	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3988	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3989	cErrors++;
3990	continue;
3991	}
3992	# endif
3993	if (PteDst.n.u1Write)
3994	{
3995	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3996	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3997	cErrors++;
3998	}
3999	fIgnoreFlags \|= X86_PTE_RW;
4000	}
4001	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4002	{
4003	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4004	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4005	cErrors++;
4006	continue;
4007	}
4008
4009	/* flags */
4010	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4011	{
4012	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4013	{
4014	if (PteDst.n.u1Write)
4015	{
4016	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
4017	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4018	cErrors++;
4019	continue;
4020	}
4021	fIgnoreFlags \|= X86_PTE_RW;
4022	}
4023	else
4024	{
4025	if (PteDst.n.u1Present)
4026	{
4027	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4029	cErrors++;
4030	continue;
4031	}
4032	fIgnoreFlags \|= X86_PTE_P;
4033	}
4034	}
4035	else
4036	{
4037	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4038	{
4039	if (PteDst.n.u1Write)
4040	{
4041	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4042	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4043	cErrors++;
4044	continue;
4045	}
4046	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4047	{
4048	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4050	cErrors++;
4051	continue;
4052	}
4053	if (PteDst.n.u1Dirty)
4054	{
4055	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4056	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4057	cErrors++;
4058	}
4059	# if 0 /** @todo sync access bit properly... */
4060	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4061	{
4062	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4063	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4064	cErrors++;
4065	}
4066	fIgnoreFlags \|= X86_PTE_RW;
4067	# else
4068	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4069	# endif
4070	}
4071	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4072	{
4073	/* access bit emulation (not implemented). */
4074	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4075	{
4076	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4077	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4078	cErrors++;
4079	continue;
4080	}
4081	if (!PteDst.n.u1Accessed)
4082	{
4083	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4084	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4085	cErrors++;
4086	}
4087	fIgnoreFlags \|= X86_PTE_P;
4088	}
4089	# ifdef DEBUG_sandervl
4090	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4091	# endif
4092	}
4093
4094	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4095	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4096	)
4097	{
4098	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4100	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4101	cErrors++;
4102	continue;
4103	}
4104	} /* foreach PTE */
4105	}
4106	else
4107	{
4108	/*
4109	* Big Page.
4110	*/
4111	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4112	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4113	{
4114	if (PdeDst.n.u1Write)
4115	{
4116	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4117	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4118	cErrors++;
4119	continue;
4120	}
4121	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4122	{
4123	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4125	cErrors++;
4126	continue;
4127	}
4128	# if 0 /** @todo sync access bit properly... */
4129	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4130	{
4131	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4132	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4133	cErrors++;
4134	}
4135	fIgnoreFlags \|= X86_PTE_RW;
4136	# else
4137	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4138	# endif
4139	}
4140	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4141	{
4142	/* access bit emulation (not implemented). */
4143	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4144	{
4145	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4146	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4147	cErrors++;
4148	continue;
4149	}
4150	if (!PdeDst.n.u1Accessed)
4151	{
4152	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4153	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4154	cErrors++;
4155	}
4156	fIgnoreFlags \|= X86_PTE_P;
4157	}
4158
4159	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4160	{
4161	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4162	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4163	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4164	cErrors++;
4165	}
4166
4167	/* iterate the page table. */
4168	for (unsigned iPT = 0, off = 0;
4169	iPT < RT_ELEMENTS(pPTDst->a);
4170	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4171	{
4172	const SHWPTE PteDst = pPTDst->a[iPT];
4173
4174	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4175	{
4176	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4177	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4178	cErrors++;
4179	}
4180
4181	/* skip not-present entries. */
4182	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4183	continue;
4184
4185	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4186
4187	/* match the physical addresses */
4188	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4189
4190	# ifdef IN_RING3
4191	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4192	if (VBOX_FAILURE(rc))
4193	{
4194	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4195	{
4196	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4197	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4198	cErrors++;
4199	}
4200	}
4201	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4202	{
4203	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4204	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4205	cErrors++;
4206	continue;
4207	}
4208	# endif
4209	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4210	if (!pPhysPage)
4211	{
4212	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4213	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4214	{
4215	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4217	cErrors++;
4218	continue;
4219	}
4220	# endif
4221	if (PteDst.n.u1Write)
4222	{
4223	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4224	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4225	cErrors++;
4226	}
4227	fIgnoreFlags \|= X86_PTE_RW;
4228	}
4229	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4230	{
4231	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4232	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4233	cErrors++;
4234	continue;
4235	}
4236
4237	/* flags */
4238	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4239	{
4240	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4241	{
4242	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4243	{
4244	if (PteDst.n.u1Write)
4245	{
4246	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4247	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4248	cErrors++;
4249	continue;
4250	}
4251	fIgnoreFlags \|= X86_PTE_RW;
4252	}
4253	}
4254	else
4255	{
4256	if (PteDst.n.u1Present)
4257	{
4258	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4259	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4260	cErrors++;
4261	continue;
4262	}
4263	fIgnoreFlags \|= X86_PTE_P;
4264	}
4265	}
4266
4267	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4268	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4269	)
4270	{
4271	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4272	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4273	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4274	cErrors++;
4275	continue;
4276	}
4277	} /* for each PTE */
4278	}
4279	}
4280	/* not present */
4281
4282	} /* for each PDE */
4283
4284	} /* for each PDPTE */
4285
4286	} /* for each PML4E */
4287
4288	# ifdef DEBUG
4289	if (cErrors)
4290	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4291	# endif
4292
4293	#endif
4294	return cErrors;
4295
4296	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED */
4297	}
4298	#endif /* VBOX_STRICT */
4299

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 11976

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