PGMAllBth.h@ 13150

Last change on this file since 13150 was 13134, checked in by vboxsync, 16 years ago
EPT: set the ignore PAT and WB cache flags in page table entries.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 193.5 KB

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1	/* $Id: PGMAllBth.h 13134 2008-10-09 14:24:07Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%VGp\n", (int)(((RTGCUINTPTR)pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%VGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135	# else
136	PGSTPD pPDSrc = NULL;
137	const unsigned iPDSrc = 0;
138	# endif
139
140	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
141	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
142	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
143	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
144	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
145	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
146
147	# if PGM_GST_TYPE == PGM_TYPE_PAE
148	/* Did we mark the PDPT as not present in SyncCR3? */
149	unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
150	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
151	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
152
153	# endif
154
155	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
156	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
157	PX86PDPAE pPDDst;
158	# if PGM_GST_TYPE == PGM_TYPE_PROT
159	/* AMD-V nested paging */
160	X86PML4E Pml4eSrc;
161	X86PDPE PdpeSrc;
162	PX86PML4E pPml4eSrc = &Pml4eSrc;
163
164	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
165	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
166	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
167	# endif
168
169	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
170	if (rc != VINF_SUCCESS)
171	{
172	AssertRC(rc);
173	return rc;
174	}
175	Assert(pPDDst);
176	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
177	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
178	PEPTPD pPDDst;
179
180	rc = PGMShwGetEPTPDPtr(pVM, (RTGCUINTPTR)pvFault, NULL, &pPDDst);
181	if (rc != VINF_SUCCESS)
182	{
183	AssertRC(rc);
184	return rc;
185	}
186	Assert(pPDDst);
187	# endif
188
189	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
190	/*
191	* If we successfully correct the write protection fault due to dirty bit
192	* tracking, or this page fault is a genuine one, then return immediately.
193	*/
194	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
195	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
196	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
197	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
198	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
199	{
200	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
201	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
202	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
203	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
204	}
205
206	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
207	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
208
209	/*
210	* A common case is the not-present error caused by lazy page table syncing.
211	*
212	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
213	* so we can safely assume that the shadow PT is present when calling SyncPage later.
214	*
215	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
216	* of mapping conflict and defer to SyncCR3 in R3.
217	* (Again, we do NOT support access handlers for non-present guest pages.)
218	*
219	*/
220	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
221	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
222	# else
223	GSTPDE PdeSrc;
224	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
225	PdeSrc.n.u1Present = 1;
226	PdeSrc.n.u1Write = 1;
227	PdeSrc.n.u1Accessed = 1;
228	PdeSrc.n.u1User = 1;
229	# endif
230	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
231	&& !pPDDst->a[iPDDst].n.u1Present
232	&& PdeSrc.n.u1Present
233	)
234
235	{
236	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
237	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
238	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
239	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
240	if (VBOX_SUCCESS(rc))
241	{
242	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
243	return rc;
244	}
245	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
246	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
247	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
248	return VINF_PGM_SYNC_CR3;
249	}
250
251	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
252	/*
253	* Check if this address is within any of our mappings.
254	*
255	* This is very fast and it's gonna save us a bit of effort below and prevent
256	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
257	* (BTW, it's impossible to have physical access handlers in a mapping.)
258	*/
259	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
260	{
261	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
262	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
263	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
264	{
265	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
266	break;
267	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
268	{
269	/*
270	* The first thing we check is if we've got an undetected conflict.
271	*/
272	if (!pVM->pgm.s.fMappingsFixed)
273	{
274	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
275	while (iPT-- > 0)
276	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
277	{
278	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
279	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
280	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
281	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
282	return VINF_PGM_SYNC_CR3;
283	}
284	}
285
286	/*
287	* Check if the fault address is in a virtual page access handler range.
288	*/
289	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
290	if ( pCur
291	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
292	&& uErr & X86_TRAP_PF_RW)
293	{
294	# ifdef IN_GC
295	STAM_PROFILE_START(&pCur->Stat, h);
296	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
297	STAM_PROFILE_STOP(&pCur->Stat, h);
298	# else
299	AssertFailed();
300	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
301	# endif
302	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
303	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
304	return rc;
305	}
306
307	/*
308	* Pretend we're not here and let the guest handle the trap.
309	*/
310	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
311	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
312	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
313	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
314	return VINF_EM_RAW_GUEST_TRAP;
315	}
316	}
317	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
318	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
319	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
320
321	/*
322	* Check if this fault address is flagged for special treatment,
323	* which means we'll have to figure out the physical address and
324	* check flags associated with it.
325	*
326	* ASSUME that we can limit any special access handling to pages
327	* in page tables which the guest believes to be present.
328	*/
329	if (PdeSrc.n.u1Present)
330	{
331	RTGCPHYS GCPhys = NIL_RTGCPHYS;
332
333	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
334	# if PGM_GST_TYPE == PGM_TYPE_AMD64
335	bool fBigPagesSupported = true;
336	# else
337	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
338	# endif
339	if ( PdeSrc.b.u1Size
340	&& fBigPagesSupported)
341	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
342	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
343	else
344	{
345	PGSTPT pPTSrc;
346	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
347	if (VBOX_SUCCESS(rc))
348	{
349	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
350	if (pPTSrc->a[iPTESrc].n.u1Present)
351	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
352	}
353	}
354	# else
355	/* No paging so the fault address is the physical address */
356	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
357	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
358
359	/*
360	* If we have a GC address we'll check if it has any flags set.
361	*/
362	if (GCPhys != NIL_RTGCPHYS)
363	{
364	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
365
366	PPGMPAGE pPage;
367	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
368	if (VBOX_SUCCESS(rc))
369	{
370	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
371	{
372	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
373	{
374	/*
375	* Physical page access handler.
376	*/
377	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
378	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
379	if (pCur)
380	{
381	# ifdef PGM_SYNC_N_PAGES
382	/*
383	* If the region is write protected and we got a page not present fault, then sync
384	* the pages. If the fault was caused by a read, then restart the instruction.
385	* In case of write access continue to the GC write handler.
386	*
387	* ASSUMES that there is only one handler per page or that they have similar write properties.
388	*/
389	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
390	&& !(uErr & X86_TRAP_PF_P))
391	{
392	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
393	if ( VBOX_FAILURE(rc)
394	\|\| !(uErr & X86_TRAP_PF_RW)
395	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
396	{
397	AssertRC(rc);
398	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
399	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
400	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
401	return rc;
402	}
403	}
404	# endif
405
406	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
407	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
408	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
409
410	# if defined(IN_GC) \|\| defined(IN_RING0)
411	if (pCur->CTX_SUFF(pfnHandler))
412	{
413	STAM_PROFILE_START(&pCur->Stat, h);
414	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
415	STAM_PROFILE_STOP(&pCur->Stat, h);
416	}
417	else
418	# endif
419	rc = VINF_EM_RAW_EMULATE_INSTR;
420	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
421	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
422	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
423	return rc;
424	}
425	}
426	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
427	else
428	{
429	# ifdef PGM_SYNC_N_PAGES
430	/*
431	* If the region is write protected and we got a page not present fault, then sync
432	* the pages. If the fault was caused by a read, then restart the instruction.
433	* In case of write access continue to the GC write handler.
434	*/
435	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
436	&& !(uErr & X86_TRAP_PF_P))
437	{
438	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
439	if ( VBOX_FAILURE(rc)
440	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
441	\|\| !(uErr & X86_TRAP_PF_RW))
442	{
443	AssertRC(rc);
444	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
445	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
446	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
447	return rc;
448	}
449	}
450	# endif
451	/*
452	* Ok, it's an virtual page access handler.
453	*
454	* Since it's faster to search by address, we'll do that first
455	* and then retry by GCPhys if that fails.
456	*/
457	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
458	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
459	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
460	*/
461	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
462	if (pCur)
463	{
464	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
465	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
466	\|\| !(uErr & X86_TRAP_PF_P)
467	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
468	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
469
470	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
471	&& ( uErr & X86_TRAP_PF_RW
472	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
473	{
474	# ifdef IN_GC
475	STAM_PROFILE_START(&pCur->Stat, h);
476	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
477	STAM_PROFILE_STOP(&pCur->Stat, h);
478	# else
479	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
480	# endif
481	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
482	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
483	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
484	return rc;
485	}
486	/* Unhandled part of a monitored page */
487	}
488	else
489	{
490	/* Check by physical address. */
491	PPGMVIRTHANDLER pCur;
492	unsigned iPage;
493	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
494	&pCur, &iPage);
495	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
496	if ( pCur
497	&& ( uErr & X86_TRAP_PF_RW
498	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
499	{
500	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
501	# ifdef IN_GC
502	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->Core.Key & PAGE_OFFSET_MASK);
503	Assert(off < pCur->cb);
504	STAM_PROFILE_START(&pCur->Stat, h);
505	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
506	STAM_PROFILE_STOP(&pCur->Stat, h);
507	# else
508	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
509	# endif
510	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
511	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
512	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
513	return rc;
514	}
515	}
516	}
517	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
518
519	/*
520	* There is a handled area of the page, but this fault doesn't belong to it.
521	* We must emulate the instruction.
522	*
523	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
524	* we first check if this was a page-not-present fault for a page with only
525	* write access handlers. Restart the instruction if it wasn't a write access.
526	*/
527	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
528
529	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
530	&& !(uErr & X86_TRAP_PF_P))
531	{
532	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
533	if ( VBOX_FAILURE(rc)
534	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
535	\|\| !(uErr & X86_TRAP_PF_RW))
536	{
537	AssertRC(rc);
538	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
539	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
540	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
541	return rc;
542	}
543	}
544
545	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
546	* It's writing to an unhandled part of the LDT page several million times.
547	*/
548	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
549	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
550	rc, pPage->HCPhys,
551	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
552	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
553	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
554	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
555	return rc;
556	} /* if any kind of handler */
557
558	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
559	if (uErr & X86_TRAP_PF_P)
560	{
561	/*
562	* The page isn't marked, but it might still be monitored by a virtual page access handler.
563	* (ASSUMES no temporary disabling of virtual handlers.)
564	*/
565	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
566	* we should correct both the shadow page table and physical memory flags, and not only check for
567	* accesses within the handler region but for access to pages with virtual handlers. */
568	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
569	if (pCur)
570	{
571	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
572	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
573	\|\| !(uErr & X86_TRAP_PF_P)
574	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
575	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
576
577	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
578	&& ( uErr & X86_TRAP_PF_RW
579	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
580	{
581	# ifdef IN_GC
582	STAM_PROFILE_START(&pCur->Stat, h);
583	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
584	STAM_PROFILE_STOP(&pCur->Stat, h);
585	# else
586	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
587	# endif
588	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
589	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
590	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
591	return rc;
592	}
593	}
594	}
595	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
596	}
597	else
598	{
599	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
600	* back to the recompiler to emulate the instruction.
601	*/
602	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
603	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
604	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
605	return VINF_EM_RAW_EMULATE_INSTR;
606	}
607
608	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
609
610	# ifdef PGM_OUT_OF_SYNC_IN_GC
611	/*
612	* We are here only if page is present in Guest page tables and trap is not handled
613	* by our handlers.
614	* Check it for page out-of-sync situation.
615	*/
616	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
617
618	if (!(uErr & X86_TRAP_PF_P))
619	{
620	/*
621	* Page is not present in our page tables.
622	* Try to sync it!
623	* BTW, fPageShw is invalid in this branch!
624	*/
625	if (uErr & X86_TRAP_PF_US)
626	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
627	else /* supervisor */
628	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
629
630	# if defined(LOG_ENABLED) && !defined(IN_RING0)
631	RTGCPHYS GCPhys;
632	uint64_t fPageGst;
633	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
634	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
635	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
636	# endif /* LOG_ENABLED */
637
638	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
639	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
640	{
641	uint64_t fPageGst;
642	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
643	if ( VBOX_SUCCESS(rc)
644	&& !(fPageGst & X86_PTE_US))
645	{
646	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
647	if ( pvFault == (RTGCPTR)pRegFrame->eip
648	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
649	# ifdef CSAM_DETECT_NEW_CODE_PAGES
650	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
651	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
652	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
653	)
654	{
655	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
656	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
657	if (rc != VINF_SUCCESS)
658	{
659	/*
660	* CSAM needs to perform a job in ring 3.
661	*
662	* Sync the page before going to the host context; otherwise we'll end up in a loop if
663	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
664	*/
665	LogFlow(("CSAM ring 3 job\n"));
666	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
667	AssertRC(rc2);
668
669	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
670	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
671	return rc;
672	}
673	}
674	# ifdef CSAM_DETECT_NEW_CODE_PAGES
675	else
676	if ( uErr == X86_TRAP_PF_RW
677	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
678	&& pRegFrame->ecx < 0x10000
679	)
680	{
681	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
682	* to detect loading of new code pages.
683	*/
684
685	/*
686	* Decode the instruction.
687	*/
688	RTGCPTR PC;
689	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
690	if (rc == VINF_SUCCESS)
691	{
692	DISCPUSTATE Cpu;
693	uint32_t cbOp;
694	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
695
696	/* For now we'll restrict this to rep movsw/d instructions */
697	if ( rc == VINF_SUCCESS
698	&& Cpu.pCurInstr->opcode == OP_MOVSWD
699	&& (Cpu.prefix & PREFIX_REP))
700	{
701	CSAMMarkPossibleCodePage(pVM, pvFault);
702	}
703	}
704	}
705	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
706
707	/*
708	* Mark this page as safe.
709	*/
710	/** @todo not correct for pages that contain both code and data!! */
711	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
712	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
713	}
714	}
715	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
716	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
717	if (VBOX_SUCCESS(rc))
718	{
719	/* The page was successfully synced, return to the guest. */
720	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
721	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
722	return VINF_SUCCESS;
723	}
724	}
725	else
726	{
727	/*
728	* A side effect of not flushing global PDEs are out of sync pages due
729	* to physical monitored regions, that are no longer valid.
730	* Assume for now it only applies to the read/write flag
731	*/
732	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
733	{
734	if (uErr & X86_TRAP_PF_US)
735	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
736	else /* supervisor */
737	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
738
739
740	/*
741	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
742	*/
743	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
744	if (VBOX_SUCCESS(rc))
745	{
746	/*
747	* Page was successfully synced, return to guest.
748	*/
749	# ifdef VBOX_STRICT
750	RTGCPHYS GCPhys;
751	uint64_t fPageGst;
752	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
753	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
754	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
755
756	uint64_t fPageShw;
757	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
758	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
759	# endif /* VBOX_STRICT */
760	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
761	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
762	return VINF_SUCCESS;
763	}
764
765	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
766	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
767	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
768	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
769	{
770	uint64_t fPageGst;
771	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
772	if ( VBOX_SUCCESS(rc)
773	&& !(fPageGst & X86_PTE_RW))
774	{
775	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
776	if (VBOX_SUCCESS(rc))
777	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
778	else
779	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
780	return rc;
781	}
782	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
783	}
784	}
785
786	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
787	# ifdef VBOX_STRICT
788	/*
789	* Check for VMM page flags vs. Guest page flags consistency.
790	* Currently only for debug purposes.
791	*/
792	if (VBOX_SUCCESS(rc))
793	{
794	/* Get guest page flags. */
795	uint64_t fPageGst;
796	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
797	if (VBOX_SUCCESS(rc))
798	{
799	uint64_t fPageShw;
800	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
801
802	/*
803	* Compare page flags.
804	* Note: we have AVL, A, D bits desynched.
805	*/
806	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
807	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
808	}
809	else
810	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
811	}
812	else
813	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
814	# endif /* VBOX_STRICT */
815	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
816	}
817	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
818	# endif /* PGM_OUT_OF_SYNC_IN_GC */
819	}
820	else
821	{
822	/*
823	* Page not present in Guest OS or invalid page table address.
824	* This is potential virtual page access handler food.
825	*
826	* For the present we'll say that our access handlers don't
827	* work for this case - we've already discarded the page table
828	* not present case which is identical to this.
829	*
830	* When we perchance find we need this, we will probably have AVL
831	* trees (offset based) to operate on and we can measure their speed
832	* agains mapping a page table and probably rearrange this handling
833	* a bit. (Like, searching virtual ranges before checking the
834	* physical address.)
835	*/
836	}
837	}
838
839
840	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
841	/*
842	* Conclusion, this is a guest trap.
843	*/
844	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
845	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
846	return VINF_EM_RAW_GUEST_TRAP;
847	# else
848	/* present, but not a monitored page; perhaps the guest is probing physical memory */
849	return VINF_EM_RAW_EMULATE_INSTR;
850	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
851
852
853	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
854
855	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
856	return VERR_INTERNAL_ERROR;
857	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
858	}
859	#endif /* !IN_RING3 */
860
861
862	/**
863	* Emulation of the invlpg instruction.
864	*
865	*
866	* @returns VBox status code.
867	*
868	* @param pVM VM handle.
869	* @param GCPtrPage Page to invalidate.
870	*
871	* @remark ASSUMES that the guest is updating before invalidating. This order
872	* isn't required by the CPU, so this is speculative and could cause
873	* trouble.
874	*
875	* @todo Flush page or page directory only if necessary!
876	* @todo Add a #define for simply invalidating the page.
877	*/
878	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
879	{
880	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
881	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
882	&& PGM_SHW_TYPE != PGM_TYPE_EPT
883	int rc;
884
885	LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
886	/*
887	* Get the shadow PD entry and skip out if this PD isn't present.
888	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
889	*/
890	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
891	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
892	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
893	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
894	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
895	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
896	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
897	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
898
899	/* If the shadow PDPE isn't present, then skip the invalidate. */
900	if (!pPdptDst->a[iPdpte].n.u1Present)
901	{
902	Assert(!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING));
903	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
904	return VINF_SUCCESS;
905	}
906
907	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
908	/* PML4 */
909	AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
910
911	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
912	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
913	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
914	PX86PDPAE pPDDst;
915	PX86PDPT pPdptDst;
916	PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
917	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
918	if (rc != VINF_SUCCESS)
919	{
920	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
921	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
922	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
923	PGM_INVL_GUEST_TLBS();
924	return VINF_SUCCESS;
925	}
926	Assert(pPDDst);
927
928	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
929	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
930
931	if (!pPdpeDst->n.u1Present)
932	{
933	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
934	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
935	PGM_INVL_GUEST_TLBS();
936	return VINF_SUCCESS;
937	}
938
939	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
940
941	const SHWPDE PdeDst = *pPdeDst;
942	if (!PdeDst.n.u1Present)
943	{
944	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
945	return VINF_SUCCESS;
946	}
947
948	/*
949	* Get the guest PD entry and calc big page.
950	*/
951	# if PGM_GST_TYPE == PGM_TYPE_32BIT
952	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
953	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
954	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
955	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
956	unsigned iPDSrc;
957	# if PGM_GST_TYPE == PGM_TYPE_PAE
958	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
959	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
960	# else /* AMD64 */
961	PX86PML4E pPml4eSrc;
962	X86PDPE PdpeSrc;
963	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
964	# endif
965	GSTPDE PdeSrc;
966
967	if (pPDSrc)
968	PdeSrc = pPDSrc->a[iPDSrc];
969	else
970	PdeSrc.u = 0;
971	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
972
973	# if PGM_GST_TYPE == PGM_TYPE_AMD64
974	const bool fIsBigPage = PdeSrc.b.u1Size;
975	# else
976	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
977	# endif
978
979	# ifdef IN_RING3
980	/*
981	* If a CR3 Sync is pending we may ignore the invalidate page operation
982	* depending on the kind of sync and if it's a global page or not.
983	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
984	*/
985	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
986	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
987	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
988	&& fIsBigPage
989	&& PdeSrc.b.u1Global
990	)
991	)
992	# else
993	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
994	# endif
995	{
996	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
997	return VINF_SUCCESS;
998	}
999	# endif /* IN_RING3 */
1000
1001	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1002	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1003
1004	/* Fetch the pgm pool shadow descriptor. */
1005	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1006	Assert(pShwPdpt);
1007
1008	/* Fetch the pgm pool shadow descriptor. */
1009	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
1010	Assert(pShwPde);
1011
1012	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1013	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1014
1015	if ( !pPml4eSrc->n.u1Present
1016	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1017	{
1018	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1019	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1020	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1021	pPml4eDst->u = 0;
1022	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1023	PGM_INVL_GUEST_TLBS();
1024	return VINF_SUCCESS;
1025	}
1026	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1027	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1028	{
1029	/*
1030	* Mark not present so we can resync the PML4E when it's used.
1031	*/
1032	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1033	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1034	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1035	pPml4eDst->u = 0;
1036	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1037	PGM_INVL_GUEST_TLBS();
1038	}
1039	else if (!pPml4eSrc->n.u1Accessed)
1040	{
1041	/*
1042	* Mark not present so we can set the accessed bit.
1043	*/
1044	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1045	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1046	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1047	pPml4eDst->u = 0;
1048	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1049	PGM_INVL_GUEST_TLBS();
1050	}
1051
1052	/* Check if the PDPT entry has changed. */
1053	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1054	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1055	if ( !PdpeSrc.n.u1Present
1056	\|\| pShwPde->GCPhys != GCPhysPd)
1057	{
1058	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1059	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1060	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1061	pPdpeDst->u = 0;
1062	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1063	PGM_INVL_GUEST_TLBS();
1064	return VINF_SUCCESS;
1065	}
1066	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1067	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1068	{
1069	/*
1070	* Mark not present so we can resync the PDPTE when it's used.
1071	*/
1072	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1073	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1074	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1075	pPdpeDst->u = 0;
1076	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1077	PGM_INVL_GUEST_TLBS();
1078	}
1079	else if (!PdpeSrc.lm.u1Accessed)
1080	{
1081	/*
1082	* Mark not present so we can set the accessed bit.
1083	*/
1084	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1085	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1086	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1087	pPdpeDst->u = 0;
1088	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1089	PGM_INVL_GUEST_TLBS();
1090	}
1091	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1092
1093	# if PGM_GST_TYPE == PGM_TYPE_PAE
1094	/* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes. */
1095	if (!pPDSrc)
1096	{
1097	/* Guest PDPE not present */
1098	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* root of the 2048 PDE array */
1099	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
1100	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1101
1102	Assert(!(CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte].n.u1Present));
1103	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
1104	/* for each page directory entry */
1105	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1106	{
1107	if ( pPDEDst[iPD].n.u1Present
1108	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
1109	{
1110	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
1111	pPDEDst[iPD].u = 0;
1112	}
1113	}
1114	if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
1115	pPdptDst->a[iPdpte].n.u1Present = 0;
1116	PGM_INVL_GUEST_TLBS();
1117	}
1118	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte], ("%VGp vs %VGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte]));
1119	# endif
1120
1121
1122	/*
1123	* Deal with the Guest PDE.
1124	*/
1125	rc = VINF_SUCCESS;
1126	if (PdeSrc.n.u1Present)
1127	{
1128	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1129	{
1130	/*
1131	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1132	*/
1133	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1134	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1135	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1136	}
1137	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1138	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1139	{
1140	/*
1141	* Mark not present so we can resync the PDE when it's used.
1142	*/
1143	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1144	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1145	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1146	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1147	# else
1148	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1149	# endif
1150	pPdeDst->u = 0;
1151	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1152	PGM_INVL_GUEST_TLBS();
1153	}
1154	else if (!PdeSrc.n.u1Accessed)
1155	{
1156	/*
1157	* Mark not present so we can set the accessed bit.
1158	*/
1159	LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1160	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1161	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1162	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1163	# else
1164	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1165	# endif
1166	pPdeDst->u = 0;
1167	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1168	PGM_INVL_GUEST_TLBS();
1169	}
1170	else if (!fIsBigPage)
1171	{
1172	/*
1173	* 4KB - page.
1174	*/
1175	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1176	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1177	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1178	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1179	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1180	# endif
1181	if (pShwPage->GCPhys == GCPhys)
1182	{
1183	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1184	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1185	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1186	if (pPT->a[iPTEDst].n.u1Present)
1187	{
1188	# ifdef PGMPOOL_WITH_USER_TRACKING
1189	/* This is very unlikely with caching/monitoring enabled. */
1190	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1191	# endif
1192	pPT->a[iPTEDst].u = 0;
1193	}
1194	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1195	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1196	if (VBOX_SUCCESS(rc))
1197	rc = VINF_SUCCESS;
1198	# endif
1199	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1200	PGM_INVL_PG(GCPtrPage);
1201	}
1202	else
1203	{
1204	/*
1205	* The page table address changed.
1206	*/
1207	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1208	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1209	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1210	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1211	# else
1212	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1213	# endif
1214	pPdeDst->u = 0;
1215	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1216	PGM_INVL_GUEST_TLBS();
1217	}
1218	}
1219	else
1220	{
1221	/*
1222	* 2/4MB - page.
1223	*/
1224	/* Before freeing the page, check if anything really changed. */
1225	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1226	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1227	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1228	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1229	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1230	# endif
1231	if ( pShwPage->GCPhys == GCPhys
1232	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1233	{
1234	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1235	/** @todo PAT */
1236	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1237	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1238	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1239	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1240	{
1241	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1242	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1243	return VINF_SUCCESS;
1244	}
1245	}
1246
1247	/*
1248	* Ok, the page table is present and it's been changed in the guest.
1249	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1250	* We could do this for some flushes in GC too, but we need an algorithm for
1251	* deciding which 4MB pages containing code likely to be executed very soon.
1252	*/
1253	LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1254	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1255	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1256	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1257	# else
1258	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1259	# endif
1260	pPdeDst->u = 0;
1261	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1262	PGM_INVL_BIG_PG(GCPtrPage);
1263	}
1264	}
1265	else
1266	{
1267	/*
1268	* Page directory is not present, mark shadow PDE not present.
1269	*/
1270	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1271	{
1272	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1273	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1274	# else
1275	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1276	# endif
1277	pPdeDst->u = 0;
1278	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1279	PGM_INVL_PG(GCPtrPage);
1280	}
1281	else
1282	{
1283	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1284	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1285	}
1286	}
1287
1288	return rc;
1289
1290	#else /* guest real and protected mode */
1291	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1292	return VINF_SUCCESS;
1293	#endif
1294	}
1295
1296
1297	#ifdef PGMPOOL_WITH_USER_TRACKING
1298	/**
1299	* Update the tracking of shadowed pages.
1300	*
1301	* @param pVM The VM handle.
1302	* @param pShwPage The shadow page.
1303	* @param HCPhys The physical page we is being dereferenced.
1304	*/
1305	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1306	{
1307	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1308	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1309	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1310
1311	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1312	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1313	* 2. write protect all shadowed pages. I.e. implement caching.
1314	*/
1315	/*
1316	* Find the guest address.
1317	*/
1318	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1319	pRam;
1320	pRam = pRam->CTX_SUFF(pNext))
1321	{
1322	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1323	while (iPage-- > 0)
1324	{
1325	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1326	{
1327	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1328	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1329	pShwPage->cPresent--;
1330	pPool->cPresent--;
1331	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1332	return;
1333	}
1334	}
1335	}
1336
1337	for (;;)
1338	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1339	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1340	pShwPage->cPresent--;
1341	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1342	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1343	}
1344
1345
1346	/**
1347	* Update the tracking of shadowed pages.
1348	*
1349	* @param pVM The VM handle.
1350	* @param pShwPage The shadow page.
1351	* @param u16 The top 16-bit of the pPage->HCPhys.
1352	* @param pPage Pointer to the guest page. this will be modified.
1353	* @param iPTDst The index into the shadow table.
1354	*/
1355	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1356	{
1357	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1358	/*
1359	* We're making certain assumptions about the placement of cRef and idx.
1360	*/
1361	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1362	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1363
1364	/*
1365	* Just deal with the simple first time here.
1366	*/
1367	if (!u16)
1368	{
1369	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1370	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1371	}
1372	else
1373	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1374
1375	/* write back, trying to be clever... */
1376	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1377	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1378	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1379	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1380
1381	/* update statistics. */
1382	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1383	pShwPage->cPresent++;
1384	if (pShwPage->iFirstPresent > iPTDst)
1385	pShwPage->iFirstPresent = iPTDst;
1386	}
1387	#endif /* PGMPOOL_WITH_USER_TRACKING */
1388
1389
1390	/**
1391	* Creates a 4K shadow page for a guest page.
1392	*
1393	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1394	* physical address. The PdeSrc argument only the flags are used. No page structured
1395	* will be mapped in this function.
1396	*
1397	* @param pVM VM handle.
1398	* @param pPteDst Destination page table entry.
1399	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1400	* Can safely assume that only the flags are being used.
1401	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1402	* @param pShwPage Pointer to the shadow page.
1403	* @param iPTDst The index into the shadow table.
1404	*
1405	* @remark Not used for 2/4MB pages!
1406	*/
1407	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1408	{
1409	if (PteSrc.n.u1Present)
1410	{
1411	/*
1412	* Find the ram range.
1413	*/
1414	PPGMPAGE pPage;
1415	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1416	if (VBOX_SUCCESS(rc))
1417	{
1418	/** @todo investiage PWT, PCD and PAT. */
1419	/*
1420	* Make page table entry.
1421	*/
1422	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1423	SHWPTE PteDst;
1424	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1425	{
1426	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1427	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1428	{
1429	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1430	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1431	PteDst.n.u1Present = 1;
1432	PteDst.n.u1Execute = 1;
1433	PteDst.n.u1IgnorePAT = 1;
1434	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1435	/* PteDst.n.u1Write = 0 && PteDst.n.u1Big = 0 */
1436	#else
1437	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1438	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1439	#endif
1440	}
1441	else
1442	{
1443	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1444	PteDst.u = 0;
1445	}
1446	/** @todo count these two kinds. */
1447	}
1448	else
1449	{
1450	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1451	/*
1452	* If the page or page directory entry is not marked accessed,
1453	* we mark the page not present.
1454	*/
1455	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1456	{
1457	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1458	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1459	PteDst.u = 0;
1460	}
1461	else
1462	/*
1463	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1464	* when the page is modified.
1465	*/
1466	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1467	{
1468	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1469	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1470	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1471	\| PGM_PTFLAGS_TRACK_DIRTY;
1472	}
1473	else
1474	#endif
1475	{
1476	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1477	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1478	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1479	PteDst.n.u1Present = 1;
1480	PteDst.n.u1Write = 1;
1481	PteDst.n.u1Execute = 1;
1482	PteDst.n.u1IgnorePAT = 1;
1483	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1484	/* PteDst.n.u1Big = 0 */
1485	#else
1486	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1487	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1488	#endif
1489	}
1490	}
1491
1492	#ifdef PGMPOOL_WITH_USER_TRACKING
1493	/*
1494	* Keep user track up to date.
1495	*/
1496	if (PteDst.n.u1Present)
1497	{
1498	if (!pPteDst->n.u1Present)
1499	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1500	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1501	{
1502	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1503	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1504	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1505	}
1506	}
1507	else if (pPteDst->n.u1Present)
1508	{
1509	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1510	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1511	}
1512	#endif /* PGMPOOL_WITH_USER_TRACKING */
1513
1514	/*
1515	* Update statistics and commit the entry.
1516	*/
1517	if (!PteSrc.n.u1Global)
1518	pShwPage->fSeenNonGlobal = true;
1519	*pPteDst = PteDst;
1520	}
1521	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1522	/** @todo count these. */
1523	}
1524	else
1525	{
1526	/*
1527	* Page not-present.
1528	*/
1529	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1530	#ifdef PGMPOOL_WITH_USER_TRACKING
1531	/* Keep user track up to date. */
1532	if (pPteDst->n.u1Present)
1533	{
1534	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1535	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1536	}
1537	#endif /* PGMPOOL_WITH_USER_TRACKING */
1538	pPteDst->u = 0;
1539	/** @todo count these. */
1540	}
1541	}
1542
1543
1544	/**
1545	* Syncs a guest OS page.
1546	*
1547	* There are no conflicts at this point, neither is there any need for
1548	* page table allocations.
1549	*
1550	* @returns VBox status code.
1551	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1552	* @param pVM VM handle.
1553	* @param PdeSrc Page directory entry of the guest.
1554	* @param GCPtrPage Guest context page address.
1555	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1556	* @param uErr Fault error (X86_TRAP_PF_*).
1557	*/
1558	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1559	{
1560	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1561
1562	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1563	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1564	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1565	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1566	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1567
1568	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1569	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1570	# endif
1571
1572	/*
1573	* Assert preconditions.
1574	*/
1575	Assert(PdeSrc.n.u1Present);
1576	Assert(cPages);
1577	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1578
1579	/*
1580	* Get the shadow PDE, find the shadow page table in the pool.
1581	*/
1582	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1583	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1584	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1585	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1586	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1587	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte); /* no mask; flat index into the 2048 entry array. */
1588	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
1589	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1590	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1591	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1592	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1593	PX86PDPAE pPDDst;
1594	X86PDEPAE PdeDst;
1595	PX86PDPT pPdptDst;
1596
1597	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1598	AssertRCSuccessReturn(rc, rc);
1599	Assert(pPDDst && pPdptDst);
1600	PdeDst = pPDDst->a[iPDDst];
1601	# endif
1602	Assert(PdeDst.n.u1Present);
1603	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1604
1605	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1606	/* Fetch the pgm pool shadow descriptor. */
1607	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1608	Assert(pShwPde);
1609	# endif
1610
1611	/*
1612	* Check that the page is present and that the shadow PDE isn't out of sync.
1613	*/
1614	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1615	const bool fBigPage = PdeSrc.b.u1Size;
1616	# else
1617	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1618	# endif
1619	RTGCPHYS GCPhys;
1620	if (!fBigPage)
1621	{
1622	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1623	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1624	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1625	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1626	# endif
1627	}
1628	else
1629	{
1630	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1631	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1632	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1633	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1634	# endif
1635	}
1636	if ( pShwPage->GCPhys == GCPhys
1637	&& PdeSrc.n.u1Present
1638	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1639	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1640	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1641	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1642	# endif
1643	)
1644	{
1645	/*
1646	* Check that the PDE is marked accessed already.
1647	* Since we set the accessed bit before getting here on a #PF, this
1648	* check is only meant for dealing with non-#PF'ing paths.
1649	*/
1650	if (PdeSrc.n.u1Accessed)
1651	{
1652	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1653	if (!fBigPage)
1654	{
1655	/*
1656	* 4KB Page - Map the guest page table.
1657	*/
1658	PGSTPT pPTSrc;
1659	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1660	if (VBOX_SUCCESS(rc))
1661	{
1662	# ifdef PGM_SYNC_N_PAGES
1663	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1664	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1665	{
1666	/*
1667	* This code path is currently only taken when the caller is PGMTrap0eHandler
1668	* for non-present pages!
1669	*
1670	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1671	* deal with locality.
1672	*/
1673	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1674	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1675	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1676	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1677	# else
1678	const unsigned offPTSrc = 0;
1679	# endif
1680	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1681	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1682	iPTDst = 0;
1683	else
1684	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1685	for (; iPTDst < iPTDstEnd; iPTDst++)
1686	{
1687	if (!pPTDst->a[iPTDst].n.u1Present)
1688	{
1689	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1690	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1691	NOREF(GCPtrCurPage);
1692	#ifndef IN_RING0
1693	/*
1694	* Assuming kernel code will be marked as supervisor - and not as user level
1695	* and executed using a conforming code selector - And marked as readonly.
1696	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1697	*/
1698	PPGMPAGE pPage;
1699	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1700	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1701	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1702	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1703	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1704	)
1705	#endif /* else: CSAM not active */
1706	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1707	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1708	GCPtrCurPage, PteSrc.n.u1Present,
1709	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1710	PteSrc.n.u1User & PdeSrc.n.u1User,
1711	(uint64_t)PteSrc.u,
1712	(uint64_t)pPTDst->a[iPTDst].u,
1713	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1714	}
1715	}
1716	}
1717	else
1718	# endif /* PGM_SYNC_N_PAGES */
1719	{
1720	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1721	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1722	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1723	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1724	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1725	GCPtrPage, PteSrc.n.u1Present,
1726	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1727	PteSrc.n.u1User & PdeSrc.n.u1User,
1728	(uint64_t)PteSrc.u,
1729	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1730	}
1731	}
1732	else /* MMIO or invalid page: emulated in #PF handler. */
1733	{
1734	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1735	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1736	}
1737	}
1738	else
1739	{
1740	/*
1741	* 4/2MB page - lazy syncing shadow 4K pages.
1742	* (There are many causes of getting here, it's no longer only CSAM.)
1743	*/
1744	/* Calculate the GC physical address of this 4KB shadow page. */
1745	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1746	/* Find ram range. */
1747	PPGMPAGE pPage;
1748	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1749	if (VBOX_SUCCESS(rc))
1750	{
1751	/*
1752	* Make shadow PTE entry.
1753	*/
1754	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1755	SHWPTE PteDst;
1756	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1757	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1758	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1759	{
1760	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1761	PteDst.n.u1Write = 0;
1762	else
1763	PteDst.u = 0;
1764	}
1765	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1766	# ifdef PGMPOOL_WITH_USER_TRACKING
1767	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1768	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1769	# endif
1770	pPTDst->a[iPTDst] = PteDst;
1771
1772
1773	/*
1774	* If the page is not flagged as dirty and is writable, then make it read-only
1775	* at PD level, so we can set the dirty bit when the page is modified.
1776	*
1777	* ASSUMES that page access handlers are implemented on page table entry level.
1778	* Thus we will first catch the dirty access and set PDE.D and restart. If
1779	* there is an access handler, we'll trap again and let it work on the problem.
1780	*/
1781	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1782	* As for invlpg, it simply frees the whole shadow PT.
1783	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1784	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1785	{
1786	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1787	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1788	PdeDst.n.u1Write = 0;
1789	}
1790	else
1791	{
1792	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1793	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1794	}
1795	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1796	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1797	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1798	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1799	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1800	pPDDst->a[iPDDst] = PdeDst;
1801	# endif
1802	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1803	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1804	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1805	}
1806	else
1807	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1808	}
1809	return VINF_SUCCESS;
1810	}
1811	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1812	}
1813	else
1814	{
1815	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1816	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1817	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1818	}
1819
1820	/*
1821	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1822	* Yea, I'm lazy.
1823	*/
1824	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1825	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1826	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1827	# else
1828	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1829	# endif
1830
1831	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1832	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1833	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1834	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1835	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1836	pPDDst->a[iPDDst].u = 0;
1837	# endif
1838	PGM_INVL_GUEST_TLBS();
1839	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1840
1841	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1842	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1843	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1844
1845	# ifdef PGM_SYNC_N_PAGES
1846	/*
1847	* Get the shadow PDE, find the shadow page table in the pool.
1848	*/
1849	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1850	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1851	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1852	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1853	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
1854	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1855	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1856	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1857	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpte);
1858	PX86PDPAE pPDDst;
1859	X86PDEPAE PdeDst;
1860	PX86PDPT pPdptDst;
1861
1862	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1863	AssertRCSuccessReturn(rc, rc);
1864	Assert(pPDDst && pPdptDst);
1865	PdeDst = pPDDst->a[iPDDst];
1866	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1867	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1868	PEPTPD pPDDst;
1869	EPTPDE PdeDst;
1870
1871	int rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1872	if (rc != VINF_SUCCESS)
1873	{
1874	AssertRC(rc);
1875	return rc;
1876	}
1877	Assert(pPDDst);
1878	PdeDst = pPDDst->a[iPDDst];
1879	# endif
1880	Assert(PdeDst.n.u1Present);
1881	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1882	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1883
1884	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1885	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1886	{
1887	/*
1888	* This code path is currently only taken when the caller is PGMTrap0eHandler
1889	* for non-present pages!
1890	*
1891	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1892	* deal with locality.
1893	*/
1894	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1895	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1896	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1897	iPTDst = 0;
1898	else
1899	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1900	for (; iPTDst < iPTDstEnd; iPTDst++)
1901	{
1902	if (!pPTDst->a[iPTDst].n.u1Present)
1903	{
1904	GSTPTE PteSrc;
1905
1906	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1907
1908	/* Fake the page table entry */
1909	PteSrc.u = GCPtrCurPage;
1910	PteSrc.n.u1Present = 1;
1911	PteSrc.n.u1Dirty = 1;
1912	PteSrc.n.u1Accessed = 1;
1913	PteSrc.n.u1Write = 1;
1914	PteSrc.n.u1User = 1;
1915
1916	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1917
1918	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1919	GCPtrCurPage, PteSrc.n.u1Present,
1920	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1921	PteSrc.n.u1User & PdeSrc.n.u1User,
1922	(uint64_t)PteSrc.u,
1923	(uint64_t)pPTDst->a[iPTDst].u,
1924	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1925	}
1926	else
1927	Log4(("%VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1928	}
1929	}
1930	else
1931	# endif /* PGM_SYNC_N_PAGES */
1932	{
1933	GSTPTE PteSrc;
1934	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1935	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1936
1937	/* Fake the page table entry */
1938	PteSrc.u = GCPtrCurPage;
1939	PteSrc.n.u1Present = 1;
1940	PteSrc.n.u1Dirty = 1;
1941	PteSrc.n.u1Accessed = 1;
1942	PteSrc.n.u1Write = 1;
1943	PteSrc.n.u1User = 1;
1944	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1945
1946	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1947	GCPtrPage, PteSrc.n.u1Present,
1948	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1949	PteSrc.n.u1User & PdeSrc.n.u1User,
1950	(uint64_t)PteSrc.u,
1951	(uint64_t)pPTDst->a[iPTDst].u,
1952	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1953	}
1954	return VINF_SUCCESS;
1955
1956	#else
1957	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1958	return VERR_INTERNAL_ERROR;
1959	#endif
1960	}
1961
1962
1963
1964	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1965
1966	/**
1967	* Investigate page fault and handle write protection page faults caused by
1968	* dirty bit tracking.
1969	*
1970	* @returns VBox status code.
1971	* @param pVM VM handle.
1972	* @param uErr Page fault error code.
1973	* @param pPdeDst Shadow page directory entry.
1974	* @param pPdeSrc Guest page directory entry.
1975	* @param GCPtrPage Guest context page address.
1976	*/
1977	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1978	{
1979	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1980	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1981	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1982	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1983	bool fBigPagesSupported = true;
1984	# else
1985	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1986	# endif
1987	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1988	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1989	# endif
1990	unsigned uPageFaultLevel;
1991	int rc;
1992
1993	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
1994	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1995
1996	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1997	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1998
1999	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2000	PX86PML4E pPml4eSrc;
2001	PX86PDPE pPdpeSrc;
2002
2003	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2004	Assert(pPml4eSrc);
2005
2006	/*
2007	* Real page fault? (PML4E level)
2008	*/
2009	if ( (uErr & X86_TRAP_PF_RSVD)
2010	\|\| !pPml4eSrc->n.u1Present
2011	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2012	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2013	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2014	)
2015	{
2016	uPageFaultLevel = 0;
2017	goto UpperLevelPageFault;
2018	}
2019	Assert(pPdpeSrc);
2020
2021	# else /* PAE */
2022	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
2023	# endif
2024
2025	/*
2026	* Real page fault? (PDPE level)
2027	*/
2028	if ( (uErr & X86_TRAP_PF_RSVD)
2029	\|\| !pPdpeSrc->n.u1Present
2030	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2031	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2032	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2033	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2034	# endif
2035	)
2036	{
2037	uPageFaultLevel = 1;
2038	goto UpperLevelPageFault;
2039	}
2040	# endif
2041
2042	/*
2043	* Real page fault? (PDE level)
2044	*/
2045	if ( (uErr & X86_TRAP_PF_RSVD)
2046	\|\| !pPdeSrc->n.u1Present
2047	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2048	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2049	# endif
2050	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2051	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2052	{
2053	uPageFaultLevel = 2;
2054	goto UpperLevelPageFault;
2055	}
2056
2057	/*
2058	* First check the easy case where the page directory has been marked read-only to track
2059	* the dirty bit of an emulated BIG page
2060	*/
2061	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2062	{
2063	/* Mark guest page directory as accessed */
2064	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2065	pPml4eSrc->n.u1Accessed = 1;
2066	pPdpeSrc->lm.u1Accessed = 1;
2067	# endif
2068	pPdeSrc->b.u1Accessed = 1;
2069
2070	/*
2071	* Only write protection page faults are relevant here.
2072	*/
2073	if (fWriteFault)
2074	{
2075	/* Mark guest page directory as dirty (BIG page only). */
2076	pPdeSrc->b.u1Dirty = 1;
2077
2078	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2079	{
2080	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2081
2082	Assert(pPdeSrc->b.u1Write);
2083
2084	pPdeDst->n.u1Write = 1;
2085	pPdeDst->n.u1Accessed = 1;
2086	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2087	PGM_INVL_BIG_PG(GCPtrPage);
2088	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2089	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2090	}
2091	}
2092	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2093	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2094	}
2095	/* else: 4KB page table */
2096
2097	/*
2098	* Map the guest page table.
2099	*/
2100	PGSTPT pPTSrc;
2101	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2102	if (VBOX_SUCCESS(rc))
2103	{
2104	/*
2105	* Real page fault?
2106	*/
2107	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2108	const GSTPTE PteSrc = *pPteSrc;
2109	if ( !PteSrc.n.u1Present
2110	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2111	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2112	# endif
2113	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2114	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2115	)
2116	{
2117	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2118	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2119	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2120
2121	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2122	* See the 2nd case above as well.
2123	*/
2124	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2125	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2126
2127	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2128	return VINF_EM_RAW_GUEST_TRAP;
2129	}
2130	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2131
2132	/*
2133	* Set the accessed bits in the page directory and the page table.
2134	*/
2135	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2136	pPml4eSrc->n.u1Accessed = 1;
2137	pPdpeSrc->lm.u1Accessed = 1;
2138	# endif
2139	pPdeSrc->n.u1Accessed = 1;
2140	pPteSrc->n.u1Accessed = 1;
2141
2142	/*
2143	* Only write protection page faults are relevant here.
2144	*/
2145	if (fWriteFault)
2146	{
2147	/* Write access, so mark guest entry as dirty. */
2148	# ifdef VBOX_WITH_STATISTICS
2149	if (!pPteSrc->n.u1Dirty)
2150	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2151	else
2152	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2153	# endif
2154
2155	pPteSrc->n.u1Dirty = 1;
2156
2157	if (pPdeDst->n.u1Present)
2158	{
2159	#ifndef IN_RING0
2160	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2161	* Our individual shadow handlers will provide more information and force a fatal exit.
2162	*/
2163	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2164	{
2165	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2166	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2167	return VINF_SUCCESS;
2168	}
2169	#endif
2170	/*
2171	* Map shadow page table.
2172	*/
2173	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2174	if (pShwPage)
2175	{
2176	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2177	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2178	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2179	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2180	{
2181	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2182	# ifdef VBOX_STRICT
2183	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2184	if (pPage)
2185	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2186	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2187	# endif
2188	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2189
2190	Assert(pPteSrc->n.u1Write);
2191
2192	pPteDst->n.u1Write = 1;
2193	pPteDst->n.u1Dirty = 1;
2194	pPteDst->n.u1Accessed = 1;
2195	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2196	PGM_INVL_PG(GCPtrPage);
2197
2198	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2199	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2200	}
2201	}
2202	else
2203	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2204	}
2205	}
2206	/** @todo Optimize accessed bit emulation? */
2207	# ifdef VBOX_STRICT
2208	/*
2209	* Sanity check.
2210	*/
2211	else if ( !pPteSrc->n.u1Dirty
2212	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2213	&& pPdeDst->n.u1Present)
2214	{
2215	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2216	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2217	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2218	if ( pPteDst->n.u1Present
2219	&& pPteDst->n.u1Write)
2220	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2221	}
2222	# endif /* VBOX_STRICT */
2223	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2224	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2225	}
2226	AssertRC(rc);
2227	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2228	return rc;
2229
2230
2231	UpperLevelPageFault:
2232	/* Pagefault detected while checking the PML4E, PDPE or PDE.
2233	* Single exit handler to get rid of duplicate code paths.
2234	*/
2235	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2236	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2237	Log(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2238
2239	if (
2240	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2241	pPml4eSrc->n.u1Present &&
2242	# endif
2243	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2244	pPdpeSrc->n.u1Present &&
2245	# endif
2246	pPdeSrc->n.u1Present)
2247	{
2248	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2249	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2250	{
2251	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2252	}
2253	else
2254	{
2255	/*
2256	* Map the guest page table.
2257	*/
2258	PGSTPT pPTSrc;
2259	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2260	if (VBOX_SUCCESS(rc))
2261	{
2262	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2263	const GSTPTE PteSrc = *pPteSrc;
2264	if (pPteSrc->n.u1Present)
2265	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2266	}
2267	AssertRC(rc);
2268	}
2269	}
2270	return VINF_EM_RAW_GUEST_TRAP;
2271	}
2272
2273	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2274
2275
2276	/**
2277	* Sync a shadow page table.
2278	*
2279	* The shadow page table is not present. This includes the case where
2280	* there is a conflict with a mapping.
2281	*
2282	* @returns VBox status code.
2283	* @param pVM VM handle.
2284	* @param iPD Page directory index.
2285	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2286	* Assume this is a temporary mapping.
2287	* @param GCPtrPage GC Pointer of the page that caused the fault
2288	*/
2289	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2290	{
2291	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2292	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2293	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2294
2295	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2296	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2297	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2298	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2299	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2300
2301	int rc = VINF_SUCCESS;
2302
2303	/*
2304	* Validate input a little bit.
2305	*/
2306	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2307	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2308	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2309	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2310	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2311	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2312	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
2313	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
2314	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2315	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2316	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2317	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2318	PX86PDPAE pPDDst;
2319	PX86PDPT pPdptDst;
2320	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2321	AssertRCSuccessReturn(rc, rc);
2322	Assert(pPDDst);
2323	# endif
2324
2325	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2326	SHWPDE PdeDst = *pPdeDst;
2327
2328	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2329	/* Fetch the pgm pool shadow descriptor. */
2330	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2331	Assert(pShwPde);
2332	# endif
2333
2334	# ifndef PGM_WITHOUT_MAPPINGS
2335	/*
2336	* Check for conflicts.
2337	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2338	* HC: Simply resolve the conflict.
2339	*/
2340	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2341	{
2342	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2343	# ifndef IN_RING3
2344	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2345	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2346	return VERR_ADDRESS_CONFLICT;
2347	# else
2348	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2349	Assert(pMapping);
2350	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2351	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2352	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2353	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2354	# else
2355	AssertFailed(); /* can't happen for amd64 */
2356	# endif
2357	if (VBOX_FAILURE(rc))
2358	{
2359	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2360	return rc;
2361	}
2362	PdeDst = *pPdeDst;
2363	# endif
2364	}
2365	# else /* PGM_WITHOUT_MAPPINGS */
2366	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2367	# endif /* PGM_WITHOUT_MAPPINGS */
2368	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2369
2370	/*
2371	* Sync page directory entry.
2372	*/
2373	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2374	if (PdeSrc.n.u1Present)
2375	{
2376	/*
2377	* Allocate & map the page table.
2378	*/
2379	PSHWPT pPTDst;
2380	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2381	const bool fPageTable = !PdeSrc.b.u1Size;
2382	# else
2383	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2384	# endif
2385	PPGMPOOLPAGE pShwPage;
2386	RTGCPHYS GCPhys;
2387	if (fPageTable)
2388	{
2389	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2390	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2391	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2392	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2393	# endif
2394	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2395	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2396	# else
2397	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2398	# endif
2399	}
2400	else
2401	{
2402	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2403	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2404	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2405	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2406	# endif
2407	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2408	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2409	# else
2410	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2411	# endif
2412	}
2413	if (rc == VINF_SUCCESS)
2414	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2415	else if (rc == VINF_PGM_CACHED_PAGE)
2416	{
2417	/*
2418	* The PT was cached, just hook it up.
2419	*/
2420	if (fPageTable)
2421	PdeDst.u = pShwPage->Core.Key
2422	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2423	else
2424	{
2425	PdeDst.u = pShwPage->Core.Key
2426	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2427	/* (see explanation and assumptions further down.) */
2428	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2429	{
2430	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2431	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2432	PdeDst.b.u1Write = 0;
2433	}
2434	}
2435	*pPdeDst = PdeDst;
2436	return VINF_SUCCESS;
2437	}
2438	else if (rc == VERR_PGM_POOL_FLUSHED)
2439	{
2440	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2441	return VINF_PGM_SYNC_CR3;
2442	}
2443	else
2444	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2445	PdeDst.u &= X86_PDE_AVL_MASK;
2446	PdeDst.u \|= pShwPage->Core.Key;
2447
2448	/*
2449	* Page directory has been accessed (this is a fault situation, remember).
2450	*/
2451	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2452	if (fPageTable)
2453	{
2454	/*
2455	* Page table - 4KB.
2456	*
2457	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2458	*/
2459	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2460	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2461	PGSTPT pPTSrc;
2462	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2463	if (VBOX_SUCCESS(rc))
2464	{
2465	/*
2466	* Start by syncing the page directory entry so CSAM's TLB trick works.
2467	*/
2468	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2469	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2470	*pPdeDst = PdeDst;
2471
2472	/*
2473	* Directory/page user or supervisor privilege: (same goes for read/write)
2474	*
2475	* Directory Page Combined
2476	* U/S U/S U/S
2477	* 0 0 0
2478	* 0 1 0
2479	* 1 0 0
2480	* 1 1 1
2481	*
2482	* Simple AND operation. Table listed for completeness.
2483	*
2484	*/
2485	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2486	# ifdef PGM_SYNC_N_PAGES
2487	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2488	unsigned iPTDst = iPTBase;
2489	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2490	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2491	iPTDst = 0;
2492	else
2493	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2494	# else /* !PGM_SYNC_N_PAGES */
2495	unsigned iPTDst = 0;
2496	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2497	# endif /* !PGM_SYNC_N_PAGES */
2498	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2499	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2500	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2501	# else
2502	const unsigned offPTSrc = 0;
2503	# endif
2504	for (; iPTDst < iPTDstEnd; iPTDst++)
2505	{
2506	const unsigned iPTSrc = iPTDst + offPTSrc;
2507	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2508
2509	if (PteSrc.n.u1Present) /* we've already cleared it above */
2510	{
2511	# ifndef IN_RING0
2512	/*
2513	* Assuming kernel code will be marked as supervisor - and not as user level
2514	* and executed using a conforming code selector - And marked as readonly.
2515	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2516	*/
2517	PPGMPAGE pPage;
2518	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2519	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2520	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2521	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2522	)
2523	# endif
2524	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2525	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2526	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2527	PteSrc.n.u1Present,
2528	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2529	PteSrc.n.u1User & PdeSrc.n.u1User,
2530	(uint64_t)PteSrc.u,
2531	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2532	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2533	}
2534	} /* for PTEs */
2535	}
2536	}
2537	else
2538	{
2539	/*
2540	* Big page - 2/4MB.
2541	*
2542	* We'll walk the ram range list in parallel and optimize lookups.
2543	* We will only sync on shadow page table at a time.
2544	*/
2545	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2546
2547	/**
2548	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2549	*/
2550
2551	/*
2552	* Start by syncing the page directory entry.
2553	*/
2554	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2555	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2556
2557	/*
2558	* If the page is not flagged as dirty and is writable, then make it read-only
2559	* at PD level, so we can set the dirty bit when the page is modified.
2560	*
2561	* ASSUMES that page access handlers are implemented on page table entry level.
2562	* Thus we will first catch the dirty access and set PDE.D and restart. If
2563	* there is an access handler, we'll trap again and let it work on the problem.
2564	*/
2565	/** @todo move the above stuff to a section in the PGM documentation. */
2566	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2567	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2568	{
2569	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2570	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2571	PdeDst.b.u1Write = 0;
2572	}
2573	*pPdeDst = PdeDst;
2574
2575	/*
2576	* Fill the shadow page table.
2577	*/
2578	/* Get address and flags from the source PDE. */
2579	SHWPTE PteDstBase;
2580	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2581
2582	/* Loop thru the entries in the shadow PT. */
2583	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2584	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2585	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2586	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2587	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2588	unsigned iPTDst = 0;
2589	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2590	{
2591	/* Advance ram range list. */
2592	while (pRam && GCPhys > pRam->GCPhysLast)
2593	pRam = pRam->CTX_SUFF(pNext);
2594	if (pRam && GCPhys >= pRam->GCPhys)
2595	{
2596	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2597	do
2598	{
2599	/* Make shadow PTE. */
2600	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2601	SHWPTE PteDst;
2602
2603	/* Make sure the RAM has already been allocated. */
2604	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2605	{
2606	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2607	{
2608	# ifdef IN_RING3
2609	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2610	# else
2611	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2612	# endif
2613	if (rc != VINF_SUCCESS)
2614	return rc;
2615	}
2616	}
2617
2618	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2619	{
2620	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2621	{
2622	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2623	PteDst.n.u1Write = 0;
2624	}
2625	else
2626	PteDst.u = 0;
2627	}
2628	# ifndef IN_RING0
2629	/*
2630	* Assuming kernel code will be marked as supervisor and not as user level and executed
2631	* using a conforming code selector. Don't check for readonly, as that implies the whole
2632	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2633	*/
2634	else if ( !PdeSrc.n.u1User
2635	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2636	PteDst.u = 0;
2637	# endif
2638	else
2639	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2640	# ifdef PGMPOOL_WITH_USER_TRACKING
2641	if (PteDst.n.u1Present)
2642	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2643	# endif
2644	/* commit it */
2645	pPTDst->a[iPTDst] = PteDst;
2646	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2647	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2648	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2649
2650	/* advance */
2651	GCPhys += PAGE_SIZE;
2652	iHCPage++;
2653	iPTDst++;
2654	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2655	&& GCPhys <= pRam->GCPhysLast);
2656	}
2657	else if (pRam)
2658	{
2659	Log(("Invalid pages at %VGp\n", GCPhys));
2660	do
2661	{
2662	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2663	GCPhys += PAGE_SIZE;
2664	iPTDst++;
2665	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2666	&& GCPhys < pRam->GCPhys);
2667	}
2668	else
2669	{
2670	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2671	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2672	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2673	}
2674	} /* while more PTEs */
2675	} /* 4KB / 4MB */
2676	}
2677	else
2678	AssertRelease(!PdeDst.n.u1Present);
2679
2680	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2681	if (VBOX_FAILURE(rc))
2682	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2683	return rc;
2684
2685	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2686	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2687	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2688
2689	int rc = VINF_SUCCESS;
2690
2691	/*
2692	* Validate input a little bit.
2693	*/
2694	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2695	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2696	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2697	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2698	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2699	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2700	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2701	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2702	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2703	PX86PDPAE pPDDst;
2704	PX86PDPT pPdptDst;
2705	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2706	AssertRCSuccessReturn(rc, rc);
2707	Assert(pPDDst);
2708
2709	/* Fetch the pgm pool shadow descriptor. */
2710	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2711	Assert(pShwPde);
2712	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2713	const unsigned iPdpte = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2714	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2715	PEPTPD pPDDst;
2716	PEPTPDPT pPdptDst;
2717
2718	rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2719	if (rc != VINF_SUCCESS)
2720	{
2721	AssertRC(rc);
2722	return rc;
2723	}
2724	Assert(pPDDst);
2725
2726	/* Fetch the pgm pool shadow descriptor. */
2727	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & EPT_PDPTE_PG_MASK);
2728	Assert(pShwPde);
2729	# endif
2730	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2731	SHWPDE PdeDst = *pPdeDst;
2732
2733	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2734	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2735
2736	GSTPDE PdeSrc;
2737	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2738	PdeSrc.n.u1Present = 1;
2739	PdeSrc.n.u1Write = 1;
2740	PdeSrc.n.u1Accessed = 1;
2741	PdeSrc.n.u1User = 1;
2742
2743	/*
2744	* Allocate & map the page table.
2745	*/
2746	PSHWPT pPTDst;
2747	PPGMPOOLPAGE pShwPage;
2748	RTGCPHYS GCPhys;
2749
2750	/* Virtual address = physical address */
2751	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2752	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2753	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2754	# else
2755	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2756	# endif
2757
2758	if ( rc == VINF_SUCCESS
2759	\|\| rc == VINF_PGM_CACHED_PAGE)
2760	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2761	else
2762	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2763
2764	PdeDst.u &= X86_PDE_AVL_MASK;
2765	PdeDst.u \|= pShwPage->Core.Key;
2766	PdeDst.n.u1Present = 1;
2767	PdeDst.n.u1Write = 1;
2768	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2769	PdeDst.n.u1Execute = 1;
2770	# else
2771	PdeDst.n.u1User = 1;
2772	PdeDst.n.u1Accessed = 1;
2773	# endif
2774	*pPdeDst = PdeDst;
2775
2776	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2777	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2778	return rc;
2779
2780	#else
2781	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2782	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2783	return VERR_INTERNAL_ERROR;
2784	#endif
2785	}
2786
2787
2788
2789	/**
2790	* Prefetch a page/set of pages.
2791	*
2792	* Typically used to sync commonly used pages before entering raw mode
2793	* after a CR3 reload.
2794	*
2795	* @returns VBox status code.
2796	* @param pVM VM handle.
2797	* @param GCPtrPage Page to invalidate.
2798	*/
2799	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2800	{
2801	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2802	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2803	/*
2804	* Check that all Guest levels thru the PDE are present, getting the
2805	* PD and PDE in the processes.
2806	*/
2807	int rc = VINF_SUCCESS;
2808	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2809	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2810	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2811	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2812	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2813	unsigned iPDSrc;
2814	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2815	if (!pPDSrc)
2816	return VINF_SUCCESS; /* not present */
2817	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2818	unsigned iPDSrc;
2819	PX86PML4E pPml4eSrc;
2820	X86PDPE PdpeSrc;
2821	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2822	if (!pPDSrc)
2823	return VINF_SUCCESS; /* not present */
2824	# endif
2825	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2826	# else
2827	PGSTPD pPDSrc = NULL;
2828	const unsigned iPDSrc = 0;
2829	GSTPDE PdeSrc;
2830
2831	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2832	PdeSrc.n.u1Present = 1;
2833	PdeSrc.n.u1Write = 1;
2834	PdeSrc.n.u1Accessed = 1;
2835	PdeSrc.n.u1User = 1;
2836	# endif
2837
2838	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2839	{
2840	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2841	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2842	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2843	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2844	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2845	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2846	PX86PDPAE pPDDst;
2847	X86PDEPAE PdeDst;
2848
2849	# if PGM_GST_TYPE == PGM_TYPE_PROT
2850	/* AMD-V nested paging */
2851	X86PML4E Pml4eSrc;
2852	X86PDPE PdpeSrc;
2853	PX86PML4E pPml4eSrc = &Pml4eSrc;
2854
2855	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2856	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2857	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2858	# endif
2859
2860	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2861	if (rc != VINF_SUCCESS)
2862	{
2863	AssertRC(rc);
2864	return rc;
2865	}
2866	Assert(pPDDst);
2867	PdeDst = pPDDst->a[iPDDst];
2868	# endif
2869	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2870	{
2871	if (!PdeDst.n.u1Present)
2872	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2873	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2874	else
2875	{
2876	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2877	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2878	* makes no sense to prefetch more than one page.
2879	*/
2880	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2881	if (VBOX_SUCCESS(rc))
2882	rc = VINF_SUCCESS;
2883	}
2884	}
2885	}
2886	return rc;
2887	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2888	return VINF_SUCCESS; /* ignore */
2889	#endif
2890	}
2891
2892
2893
2894
2895	/**
2896	* Syncs a page during a PGMVerifyAccess() call.
2897	*
2898	* @returns VBox status code (informational included).
2899	* @param GCPtrPage The address of the page to sync.
2900	* @param fPage The effective guest page flags.
2901	* @param uErr The trap error code.
2902	*/
2903	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2904	{
2905	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2906
2907	Assert(!HWACCMIsNestedPagingActive(pVM));
2908	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2909	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2910
2911	# ifndef IN_RING0
2912	if (!(fPage & X86_PTE_US))
2913	{
2914	/*
2915	* Mark this page as safe.
2916	*/
2917	/** @todo not correct for pages that contain both code and data!! */
2918	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2919	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2920	}
2921	# endif
2922	/*
2923	* Get guest PD and index.
2924	*/
2925
2926	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2927	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2928	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2929	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2930	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2931	unsigned iPDSrc;
2932	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2933
2934	if (pPDSrc)
2935	{
2936	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2937	return VINF_EM_RAW_GUEST_TRAP;
2938	}
2939	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2940	unsigned iPDSrc;
2941	PX86PML4E pPml4eSrc;
2942	X86PDPE PdpeSrc;
2943	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2944	if (!pPDSrc)
2945	{
2946	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2947	return VINF_EM_RAW_GUEST_TRAP;
2948	}
2949	# endif
2950	# else
2951	PGSTPD pPDSrc = NULL;
2952	const unsigned iPDSrc = 0;
2953	# endif
2954	int rc = VINF_SUCCESS;
2955
2956	/*
2957	* First check if the shadow pd is present.
2958	*/
2959	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2960	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2961	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2962	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2963	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2964	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2965	PX86PDPAE pPDDst;
2966	PX86PDEPAE pPdeDst;
2967
2968	# if PGM_GST_TYPE == PGM_TYPE_PROT
2969	/* AMD-V nested paging */
2970	X86PML4E Pml4eSrc;
2971	X86PDPE PdpeSrc;
2972	PX86PML4E pPml4eSrc = &Pml4eSrc;
2973
2974	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2975	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2976	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2977	# endif
2978
2979	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2980	if (rc != VINF_SUCCESS)
2981	{
2982	AssertRC(rc);
2983	return rc;
2984	}
2985	Assert(pPDDst);
2986	pPdeDst = &pPDDst->a[iPDDst];
2987	# endif
2988	if (!pPdeDst->n.u1Present)
2989	{
2990	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2991	AssertRC(rc);
2992	if (rc != VINF_SUCCESS)
2993	return rc;
2994	}
2995
2996	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2997	/* Check for dirty bit fault */
2998	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2999	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3000	Log(("PGMVerifyAccess: success (dirty)\n"));
3001	else
3002	{
3003	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3004	#else
3005	{
3006	GSTPDE PdeSrc;
3007	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3008	PdeSrc.n.u1Present = 1;
3009	PdeSrc.n.u1Write = 1;
3010	PdeSrc.n.u1Accessed = 1;
3011	PdeSrc.n.u1User = 1;
3012
3013	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3014	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3015	if (uErr & X86_TRAP_PF_US)
3016	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3017	else /* supervisor */
3018	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3019
3020	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3021	if (VBOX_SUCCESS(rc))
3022	{
3023	/* Page was successfully synced */
3024	Log2(("PGMVerifyAccess: success (sync)\n"));
3025	rc = VINF_SUCCESS;
3026	}
3027	else
3028	{
3029	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
3030	return VINF_EM_RAW_GUEST_TRAP;
3031	}
3032	}
3033	return rc;
3034
3035	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3036
3037	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3038	return VERR_INTERNAL_ERROR;
3039	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3040	}
3041
3042
3043	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3044	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3045	/**
3046	* Figures out which kind of shadow page this guest PDE warrants.
3047	*
3048	* @returns Shadow page kind.
3049	* @param pPdeSrc The guest PDE in question.
3050	* @param cr4 The current guest cr4 value.
3051	*/
3052	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3053	{
3054	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3055	if (!pPdeSrc->n.u1Size)
3056	# else
3057	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3058	# endif
3059	return BTH_PGMPOOLKIND_PT_FOR_PT;
3060	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3061	//{
3062	// case 0:
3063	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3064	// case X86_PDE4M_RW:
3065	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3066	// case X86_PDE4M_US:
3067	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3068	// case X86_PDE4M_RW \| X86_PDE4M_US:
3069	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3070	# if 0
3071	// case X86_PDE4M_PAE_NX:
3072	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3073	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3074	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3075	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3076	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3077	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3078	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3079	# endif
3080	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3081	//}
3082	}
3083	# endif
3084	#endif
3085
3086	#undef MY_STAM_COUNTER_INC
3087	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3088
3089
3090	/**
3091	* Syncs the paging hierarchy starting at CR3.
3092	*
3093	* @returns VBox status code, no specials.
3094	* @param pVM The virtual machine.
3095	* @param cr0 Guest context CR0 register
3096	* @param cr3 Guest context CR3 register
3097	* @param cr4 Guest context CR4 register
3098	* @param fGlobal Including global page directories or not
3099	*/
3100	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3101	{
3102	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3103	fGlobal = true; /* Change this CR3 reload to be a global one. */
3104
3105	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3106	/*
3107	* Update page access handlers.
3108	* The virtual are always flushed, while the physical are only on demand.
3109	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3110	* have to look into that later because it will have a bad influence on the performance.
3111	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3112	* bird: Yes, but that won't work for aliases.
3113	*/
3114	/** @todo this MUST go away. See #1557. */
3115	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3116	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3117	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3118	#endif
3119
3120	#ifdef PGMPOOL_WITH_MONITORING
3121	int rc = pgmPoolSyncCR3(pVM);
3122	if (rc != VINF_SUCCESS)
3123	return rc;
3124	#endif
3125
3126	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3127	/** @todo check if this is really necessary */
3128	HWACCMFlushTLB(pVM);
3129	return VINF_SUCCESS;
3130
3131	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3132	/* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
3133	return VINF_SUCCESS;
3134	#else
3135
3136	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3137	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3138
3139	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3140	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3141	bool fBigPagesSupported = true;
3142	# else
3143	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3144	# endif
3145
3146	/*
3147	* Get page directory addresses.
3148	*/
3149	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3150	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3151	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3152	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3153	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3154	# endif
3155	# endif
3156
3157	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3158	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
3159	Assert(pPDSrc);
3160	# ifndef IN_GC
3161	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3162	# endif
3163	# endif
3164
3165	/*
3166	* Iterate the page directory.
3167	*/
3168	PPGMMAPPING pMapping;
3169	unsigned iPdNoMapping;
3170	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3171	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3172
3173	/* Only check mappings if they are supposed to be put into the shadow page table. */
3174	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3175	{
3176	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3177	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3178	}
3179	else
3180	{
3181	pMapping = 0;
3182	iPdNoMapping = ~0U;
3183	}
3184	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3185	for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3186	{
3187	PPGMPOOLPAGE pShwPdpt = NULL;
3188	PX86PML4E pPml4eSrc, pPml4eDst;
3189	RTGCPHYS GCPhysPdptSrc;
3190
3191	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3192	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3193
3194	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3195	if (!pPml4eDst->n.u1Present)
3196	continue;
3197	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3198
3199	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3200
3201	/* Anything significant changed? */
3202	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3203	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3204	{
3205	/* Free it. */
3206	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3207	(uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3208	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
3209	pPml4eDst->u = 0;
3210	continue;
3211	}
3212	/* Force an attribute sync. */
3213	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3214	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3215	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3216
3217	# else
3218	{
3219	# endif
3220	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3221	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3222	{
3223	unsigned iPDSrc;
3224	# if PGM_GST_TYPE == PGM_TYPE_PAE
3225	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3226	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3227	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
3228	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
3229	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3230
3231	if (pPDSrc == NULL)
3232	{
3233	/* PDPE not present */
3234	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
3235	{
3236	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3237	/* for each page directory entry */
3238	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3239	{
3240	if ( pPDEDst[iPD].n.u1Present
3241	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3242	{
3243	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3244	pPDEDst[iPD].u = 0;
3245	}
3246	}
3247	}
3248	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3249	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
3250	continue;
3251	}
3252	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3253	PPGMPOOLPAGE pShwPde = NULL;
3254	RTGCPHYS GCPhysPdeSrc;
3255	PX86PDPE pPdpeDst;
3256	PX86PML4E pPml4eSrc;
3257	X86PDPE PdpeSrc;
3258	PX86PDPT pPdptDst;
3259	PX86PDPAE pPDDst;
3260	PX86PDEPAE pPDEDst;
3261	RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3262	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3263
3264	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3265	if (rc != VINF_SUCCESS)
3266	{
3267	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3268	break; /* next PML4E */
3269
3270	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3271	continue; /* next PDPTE */
3272	}
3273	Assert(pPDDst);
3274	pPDEDst = &pPDDst->a[0];
3275	Assert(iPDSrc == 0);
3276
3277	pPdpeDst = &pPdptDst->a[iPdpte];
3278
3279	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3280	if (!pPdpeDst->n.u1Present)
3281	continue; /* next PDPTE */
3282
3283	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3284	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3285
3286	/* Anything significant changed? */
3287	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3288	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3289	{
3290	/* Free it. */
3291	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3292	((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3293
3294	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3295	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3296	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3297	pPdpeDst->u = 0;
3298	continue; /* next guest PDPTE */
3299	}
3300	/* Force an attribute sync. */
3301	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3302	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3303	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3304	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3305
3306	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3307	{
3308	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3309	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3310	{
3311	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3312	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3313	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3314	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3315	# endif
3316	GSTPDE PdeSrc = pPDSrc->a[iPD];
3317	if ( PdeSrc.n.u1Present
3318	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3319	{
3320	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3321	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3322	&& !defined(PGM_WITHOUT_MAPPINGS)
3323
3324	/*
3325	* Check for conflicts with GC mappings.
3326	*/
3327	# if PGM_GST_TYPE == PGM_TYPE_PAE
3328	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3329	# else
3330	if (iPD == iPdNoMapping)
3331	# endif
3332	{
3333	if (pVM->pgm.s.fMappingsFixed)
3334	{
3335	/* It's fixed, just skip the mapping. */
3336	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3337	iPD += cPTs - 1;
3338	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3339	pMapping = pMapping->CTX_SUFF(pNext);
3340	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3341	continue;
3342	}
3343	# ifdef IN_RING3
3344	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3345	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3346	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3347	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3348	# endif
3349	if (VBOX_FAILURE(rc))
3350	return rc;
3351
3352	/*
3353	* Update iPdNoMapping and pMapping.
3354	*/
3355	pMapping = pVM->pgm.s.pMappingsR3;
3356	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3357	pMapping = pMapping->pNextR3;
3358	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3359	# else
3360	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3361	return VINF_PGM_SYNC_CR3;
3362	# endif
3363	}
3364	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3365	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3366	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3367	/*
3368	* Sync page directory entry.
3369	*
3370	* The current approach is to allocated the page table but to set
3371	* the entry to not-present and postpone the page table synching till
3372	* it's actually used.
3373	*/
3374	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3375	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3376	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3377	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3378	# else
3379	const unsigned iPdShw = iPD; NOREF(iPdShw);
3380	# endif
3381	{
3382	SHWPDE PdeDst = *pPDEDst;
3383	if (PdeDst.n.u1Present)
3384	{
3385	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3386	RTGCPHYS GCPhys;
3387	if ( !PdeSrc.b.u1Size
3388	\|\| !fBigPagesSupported)
3389	{
3390	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3391	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3392	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3393	GCPhys \|= i * (PAGE_SIZE / 2);
3394	# endif
3395	}
3396	else
3397	{
3398	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3399	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3400	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3401	GCPhys \|= i * X86_PAGE_2M_SIZE;
3402	# endif
3403	}
3404
3405	if ( pShwPage->GCPhys == GCPhys
3406	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3407	&& ( pShwPage->fCached
3408	\|\| ( !fGlobal
3409	&& ( false
3410	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3411	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3412	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3413	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3414	# else
3415	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3416	# endif
3417	\|\| ( !pShwPage->fSeenNonGlobal
3418	&& (cr4 & X86_CR4_PGE))
3419	# endif
3420	)
3421	)
3422	)
3423	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3424	\|\| ( fBigPagesSupported
3425	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3426	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3427	)
3428	)
3429	{
3430	# ifdef VBOX_WITH_STATISTICS
3431	if ( !fGlobal
3432	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3433	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3434	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3435	# else
3436	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3437	# endif
3438	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3439	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3440	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3441	else
3442	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3443	# endif /* VBOX_WITH_STATISTICS */
3444	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3445	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3446	//# ifdef PGMPOOL_WITH_CACHE
3447	// pgmPoolCacheUsed(pPool, pShwPage);
3448	//# endif
3449	}
3450	else
3451	{
3452	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3453	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3454	# else
3455	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3456	# endif
3457	pPDEDst->u = 0;
3458	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3459	}
3460	}
3461	else
3462	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3463	pPDEDst++;
3464	}
3465	}
3466	# if PGM_GST_TYPE == PGM_TYPE_PAE
3467	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3468	# else
3469	else if (iPD != iPdNoMapping)
3470	# endif
3471	{
3472	/*
3473	* Check if there is any page directory to mark not present here.
3474	*/
3475	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3476	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3477	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3478	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3479	# else
3480	const unsigned iPdShw = iPD; NOREF(iPdShw);
3481	# endif
3482	{
3483	if (pPDEDst->n.u1Present)
3484	{
3485	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3486	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3487	# else
3488	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3489	# endif
3490	pPDEDst->u = 0;
3491	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3492	}
3493	pPDEDst++;
3494	}
3495	}
3496	else
3497	{
3498	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3499	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3500	&& !defined(PGM_WITHOUT_MAPPINGS)
3501
3502	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3503
3504	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3505	if (pVM->pgm.s.fMappingsFixed)
3506	{
3507	/* It's fixed, just skip the mapping. */
3508	pMapping = pMapping->CTX_SUFF(pNext);
3509	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3510	}
3511	else
3512	{
3513	/*
3514	* Check for conflicts for subsequent pagetables
3515	* and advance to the next mapping.
3516	*/
3517	iPdNoMapping = ~0U;
3518	unsigned iPT = cPTs;
3519	while (iPT-- > 1)
3520	{
3521	if ( pPDSrc->a[iPD + iPT].n.u1Present
3522	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3523	{
3524	# ifdef IN_RING3
3525	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3526	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3527	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3528	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3529	# endif
3530	if (VBOX_FAILURE(rc))
3531	return rc;
3532
3533	/*
3534	* Update iPdNoMapping and pMapping.
3535	*/
3536	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3537	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3538	pMapping = pMapping->CTX_SUFF(pNext);
3539	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3540	break;
3541	# else
3542	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3543	return VINF_PGM_SYNC_CR3;
3544	# endif
3545	}
3546	}
3547	if (iPdNoMapping == ~0U && pMapping)
3548	{
3549	pMapping = pMapping->CTX_SUFF(pNext);
3550	if (pMapping)
3551	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3552	}
3553	}
3554
3555	/* advance. */
3556	iPD += cPTs - 1;
3557	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3558	# if PGM_GST_TYPE != PGM_SHW_TYPE
3559	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3560	# endif
3561	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3562	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3563	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3564	}
3565
3566	} /* for iPD */
3567	} /* for each PDPTE (PAE) */
3568	} /* for each page map level 4 entry (amd64) */
3569	return VINF_SUCCESS;
3570
3571	# else /* guest real and protected mode */
3572	return VINF_SUCCESS;
3573	# endif
3574	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
3575	}
3576
3577
3578
3579
3580	#ifdef VBOX_STRICT
3581	#ifdef IN_GC
3582	# undef AssertMsgFailed
3583	# define AssertMsgFailed Log
3584	#endif
3585	#ifdef IN_RING3
3586	# include <VBox/dbgf.h>
3587
3588	/**
3589	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3590	*
3591	* @returns VBox status code (VINF_SUCCESS).
3592	* @param pVM The VM handle.
3593	* @param cr3 The root of the hierarchy.
3594	* @param crr The cr4, only PAE and PSE is currently used.
3595	* @param fLongMode Set if long mode, false if not long mode.
3596	* @param cMaxDepth Number of levels to dump.
3597	* @param pHlp Pointer to the output functions.
3598	*/
3599	__BEGIN_DECLS
3600	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3601	__END_DECLS
3602
3603	#endif
3604
3605	/**
3606	* Checks that the shadow page table is in sync with the guest one.
3607	*
3608	* @returns The number of errors.
3609	* @param pVM The virtual machine.
3610	* @param cr3 Guest context CR3 register
3611	* @param cr4 Guest context CR4 register
3612	* @param GCPtr Where to start. Defaults to 0.
3613	* @param cb How much to check. Defaults to everything.
3614	*/
3615	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3616	{
3617	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3618	return 0;
3619	#else
3620	unsigned cErrors = 0;
3621
3622	#if PGM_GST_TYPE == PGM_TYPE_PAE
3623	/* @todo currently broken; crashes below somewhere */
3624	AssertFailed();
3625	#endif
3626
3627	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3628	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3629	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3630
3631	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3632	bool fBigPagesSupported = true;
3633	# else
3634	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3635	# endif
3636	PPGM pPGM = &pVM->pgm.s;
3637	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3638	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3639	# ifndef IN_RING0
3640	RTHCPHYS HCPhys; /* general usage. */
3641	# endif
3642	int rc;
3643
3644	/*
3645	* Check that the Guest CR3 and all its mappings are correct.
3646	*/
3647	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3648	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3649	false);
3650	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3651	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3652	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3653	# else
3654	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3655	# endif
3656	AssertRCReturn(rc, 1);
3657	HCPhys = NIL_RTHCPHYS;
3658	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3659	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3660	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3661	RTGCPHYS GCPhys;
3662	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3663	AssertRCReturn(rc, 1);
3664	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3665	# endif
3666	#endif /* !IN_RING0 */
3667
3668	/*
3669	* Get and check the Shadow CR3.
3670	*/
3671	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3672	unsigned cPDEs = X86_PG_ENTRIES;
3673	unsigned ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3674	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3675	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3676	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3677	# else
3678	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3679	# endif
3680	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3681	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3682	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3683	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3684	# endif
3685	if (cb != ~(RTGCUINTPTR)0)
3686	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3687
3688	/** @todo call the other two PGMAssert() functions. /
3689
3690	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3691	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3692	# endif
3693
3694	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3695	unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3696
3697	for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3698	{
3699	PPGMPOOLPAGE pShwPdpt = NULL;
3700	PX86PML4E pPml4eSrc, pPml4eDst;
3701	RTGCPHYS GCPhysPdptSrc;
3702
3703	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3704	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3705
3706	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3707	if (!pPml4eDst->n.u1Present)
3708	{
3709	GCPtr += UINT64_C(_2M * 512 * 512);
3710	continue;
3711	}
3712
3713	# if PGM_GST_TYPE == PGM_TYPE_PAE
3714	/* not correct to call pgmPoolGetPage */
3715	AssertFailed();
3716	# endif
3717	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3718	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3719
3720	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3721	{
3722	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3723	GCPtr += UINT64_C(_2M * 512 * 512);
3724	cErrors++;
3725	continue;
3726	}
3727
3728	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3729	{
3730	AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3731	GCPtr += UINT64_C(_2M * 512 * 512);
3732	cErrors++;
3733	continue;
3734	}
3735
3736	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3737	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3738	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3739	{
3740	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3741	GCPtr += UINT64_C(_2M * 512 * 512);
3742	cErrors++;
3743	continue;
3744	}
3745	# else
3746	{
3747	# endif
3748
3749	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3750	/*
3751	* Check the PDPTEs too.
3752	*/
3753	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3754
3755	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3756	{
3757	unsigned iPDSrc;
3758	PPGMPOOLPAGE pShwPde = NULL;
3759	PX86PDPE pPdpeDst;
3760	RTGCPHYS GCPhysPdeSrc;
3761	# if PGM_GST_TYPE == PGM_TYPE_PAE
3762	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3763	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
3764	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3765	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3766	# else
3767	PX86PML4E pPml4eSrc;
3768	X86PDPE PdpeSrc;
3769	PX86PDPT pPdptDst;
3770	PX86PDPAE pPDDst;
3771	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3772
3773	rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3774	if (rc != VINF_SUCCESS)
3775	{
3776	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3777	GCPtr += 512 * _2M;
3778	continue; /* next PDPTE */
3779	}
3780	Assert(pPDDst);
3781	# endif
3782	Assert(iPDSrc == 0);
3783
3784	pPdpeDst = &pPdptDst->a[iPdpte];
3785
3786	if (!pPdpeDst->n.u1Present)
3787	{
3788	GCPtr += 512 * _2M;
3789	continue; /* next PDPTE */
3790	}
3791
3792	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3793	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3794
3795	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3796	{
3797	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3798	GCPtr += 512 * _2M;
3799	cErrors++;
3800	continue;
3801	}
3802
3803	if (GCPhysPdeSrc != pShwPde->GCPhys)
3804	{
3805	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3806	AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3807	# else
3808	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3809	# endif
3810	GCPtr += 512 * _2M;
3811	cErrors++;
3812	continue;
3813	}
3814
3815	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3816	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3817	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3818	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3819	{
3820	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3821	GCPtr += 512 * _2M;
3822	cErrors++;
3823	continue;
3824	}
3825	# endif
3826
3827	# else
3828	{
3829	# endif
3830	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3831	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3832	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3833	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3834	# else
3835	const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3836	# endif
3837	# endif
3838	/*
3839	* Iterate the shadow page directory.
3840	*/
3841	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3842	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3843
3844	for (;
3845	iPDDst < cPDEs;
3846	iPDDst++, GCPtr += ulIncrement)
3847	{
3848	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3849	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3850	{
3851	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3852	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3853	{
3854	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3855	cErrors++;
3856	continue;
3857	}
3858	}
3859	else if ( (PdeDst.u & X86_PDE_P)
3860	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3861	)
3862	{
3863	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3864	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3865	if (!pPoolPage)
3866	{
3867	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3868	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3869	cErrors++;
3870	continue;
3871	}
3872	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3873
3874	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3875	{
3876	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3877	GCPtr, (uint64_t)PdeDst.u));
3878	cErrors++;
3879	}
3880
3881	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3882	{
3883	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3884	GCPtr, (uint64_t)PdeDst.u));
3885	cErrors++;
3886	}
3887
3888	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3889	if (!PdeSrc.n.u1Present)
3890	{
3891	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3892	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3893	cErrors++;
3894	continue;
3895	}
3896
3897	if ( !PdeSrc.b.u1Size
3898	\|\| !fBigPagesSupported)
3899	{
3900	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3901	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3902	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3903	# endif
3904	}
3905	else
3906	{
3907	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3908	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3909	{
3910	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3911	GCPtr, (uint64_t)PdeSrc.u));
3912	cErrors++;
3913	continue;
3914	}
3915	# endif
3916	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3917	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3918	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3919	# endif
3920	}
3921
3922	if ( pPoolPage->enmKind
3923	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3924	{
3925	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3926	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3927	cErrors++;
3928	}
3929
3930	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3931	if (!pPhysPage)
3932	{
3933	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3934	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3935	cErrors++;
3936	continue;
3937	}
3938
3939	if (GCPhysGst != pPoolPage->GCPhys)
3940	{
3941	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3942	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3943	cErrors++;
3944	continue;
3945	}
3946
3947	if ( !PdeSrc.b.u1Size
3948	\|\| !fBigPagesSupported)
3949	{
3950	/*
3951	* Page Table.
3952	*/
3953	const GSTPT *pPTSrc;
3954	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3955	if (VBOX_FAILURE(rc))
3956	{
3957	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3958	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3959	cErrors++;
3960	continue;
3961	}
3962	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3963	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3964	{
3965	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3966	// (This problem will go away when/if we shadow multiple CR3s.)
3967	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3968	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3969	cErrors++;
3970	continue;
3971	}
3972	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3973	{
3974	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3975	GCPtr, (uint64_t)PdeDst.u));
3976	cErrors++;
3977	continue;
3978	}
3979
3980	/* iterate the page table. */
3981	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3982	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3983	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3984	# else
3985	const unsigned offPTSrc = 0;
3986	# endif
3987	for (unsigned iPT = 0, off = 0;
3988	iPT < RT_ELEMENTS(pPTDst->a);
3989	iPT++, off += PAGE_SIZE)
3990	{
3991	const SHWPTE PteDst = pPTDst->a[iPT];
3992
3993	/* skip not-present entries. */
3994	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3995	continue;
3996	Assert(PteDst.n.u1Present);
3997
3998	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3999	if (!PteSrc.n.u1Present)
4000	{
4001	# ifdef IN_RING3
4002	PGMAssertHandlerAndFlagsInSync(pVM);
4003	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4004	# endif
4005	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
4006	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4007	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4008	cErrors++;
4009	continue;
4010	}
4011
4012	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4013	# if 1 /** @todo sync accessed bit properly... */
4014	fIgnoreFlags \|= X86_PTE_A;
4015	# endif
4016
4017	/* match the physical addresses */
4018	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4019	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4020
4021	# ifdef IN_RING3
4022	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4023	if (VBOX_FAILURE(rc))
4024	{
4025	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4026	{
4027	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4029	cErrors++;
4030	continue;
4031	}
4032	}
4033	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4034	{
4035	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4036	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4037	cErrors++;
4038	continue;
4039	}
4040	# endif
4041
4042	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4043	if (!pPhysPage)
4044	{
4045	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4046	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4047	{
4048	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4050	cErrors++;
4051	continue;
4052	}
4053	# endif
4054	if (PteDst.n.u1Write)
4055	{
4056	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4057	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4058	cErrors++;
4059	}
4060	fIgnoreFlags \|= X86_PTE_RW;
4061	}
4062	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4063	{
4064	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4065	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4066	cErrors++;
4067	continue;
4068	}
4069
4070	/* flags */
4071	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4072	{
4073	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4074	{
4075	if (PteDst.n.u1Write)
4076	{
4077	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
4078	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4079	cErrors++;
4080	continue;
4081	}
4082	fIgnoreFlags \|= X86_PTE_RW;
4083	}
4084	else
4085	{
4086	if (PteDst.n.u1Present)
4087	{
4088	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
4089	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4090	cErrors++;
4091	continue;
4092	}
4093	fIgnoreFlags \|= X86_PTE_P;
4094	}
4095	}
4096	else
4097	{
4098	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4099	{
4100	if (PteDst.n.u1Write)
4101	{
4102	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4103	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4104	cErrors++;
4105	continue;
4106	}
4107	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4108	{
4109	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4110	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4111	cErrors++;
4112	continue;
4113	}
4114	if (PteDst.n.u1Dirty)
4115	{
4116	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4117	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4118	cErrors++;
4119	}
4120	# if 0 /** @todo sync access bit properly... */
4121	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4122	{
4123	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4125	cErrors++;
4126	}
4127	fIgnoreFlags \|= X86_PTE_RW;
4128	# else
4129	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4130	# endif
4131	}
4132	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4133	{
4134	/* access bit emulation (not implemented). */
4135	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4136	{
4137	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4138	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4139	cErrors++;
4140	continue;
4141	}
4142	if (!PteDst.n.u1Accessed)
4143	{
4144	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4145	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4146	cErrors++;
4147	}
4148	fIgnoreFlags \|= X86_PTE_P;
4149	}
4150	# ifdef DEBUG_sandervl
4151	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4152	# endif
4153	}
4154
4155	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4156	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4157	)
4158	{
4159	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4160	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4161	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4162	cErrors++;
4163	continue;
4164	}
4165	} /* foreach PTE */
4166	}
4167	else
4168	{
4169	/*
4170	* Big Page.
4171	*/
4172	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4173	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4174	{
4175	if (PdeDst.n.u1Write)
4176	{
4177	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4178	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4179	cErrors++;
4180	continue;
4181	}
4182	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4183	{
4184	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4185	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4186	cErrors++;
4187	continue;
4188	}
4189	# if 0 /** @todo sync access bit properly... */
4190	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4191	{
4192	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4193	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4194	cErrors++;
4195	}
4196	fIgnoreFlags \|= X86_PTE_RW;
4197	# else
4198	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4199	# endif
4200	}
4201	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4202	{
4203	/* access bit emulation (not implemented). */
4204	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4205	{
4206	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4207	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4208	cErrors++;
4209	continue;
4210	}
4211	if (!PdeDst.n.u1Accessed)
4212	{
4213	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4214	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4215	cErrors++;
4216	}
4217	fIgnoreFlags \|= X86_PTE_P;
4218	}
4219
4220	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4221	{
4222	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4223	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4224	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4225	cErrors++;
4226	}
4227
4228	/* iterate the page table. */
4229	for (unsigned iPT = 0, off = 0;
4230	iPT < RT_ELEMENTS(pPTDst->a);
4231	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4232	{
4233	const SHWPTE PteDst = pPTDst->a[iPT];
4234
4235	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4236	{
4237	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4238	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4239	cErrors++;
4240	}
4241
4242	/* skip not-present entries. */
4243	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4244	continue;
4245
4246	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4247
4248	/* match the physical addresses */
4249	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4250
4251	# ifdef IN_RING3
4252	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4253	if (VBOX_FAILURE(rc))
4254	{
4255	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4256	{
4257	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4258	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4259	cErrors++;
4260	}
4261	}
4262	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4263	{
4264	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4265	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4266	cErrors++;
4267	continue;
4268	}
4269	# endif
4270	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4271	if (!pPhysPage)
4272	{
4273	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4274	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4275	{
4276	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4277	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4278	cErrors++;
4279	continue;
4280	}
4281	# endif
4282	if (PteDst.n.u1Write)
4283	{
4284	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4285	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4286	cErrors++;
4287	}
4288	fIgnoreFlags \|= X86_PTE_RW;
4289	}
4290	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4291	{
4292	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4293	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4294	cErrors++;
4295	continue;
4296	}
4297
4298	/* flags */
4299	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4300	{
4301	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4302	{
4303	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4304	{
4305	if (PteDst.n.u1Write)
4306	{
4307	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4308	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4309	cErrors++;
4310	continue;
4311	}
4312	fIgnoreFlags \|= X86_PTE_RW;
4313	}
4314	}
4315	else
4316	{
4317	if (PteDst.n.u1Present)
4318	{
4319	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4320	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4321	cErrors++;
4322	continue;
4323	}
4324	fIgnoreFlags \|= X86_PTE_P;
4325	}
4326	}
4327
4328	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4329	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4330	)
4331	{
4332	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4333	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4334	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4335	cErrors++;
4336	continue;
4337	}
4338	} /* for each PTE */
4339	}
4340	}
4341	/* not present */
4342
4343	} /* for each PDE */
4344
4345	} /* for each PDPTE */
4346
4347	} /* for each PML4E */
4348
4349	# ifdef DEBUG
4350	if (cErrors)
4351	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4352	# endif
4353
4354	#endif
4355	return cErrors;
4356
4357	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4358	}
4359	#endif /* VBOX_STRICT */
4360

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 13150

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