PGMAllBth.h@ 13188

Last change on this file since 13188 was 13188, checked in by vboxsync, 16 years ago
PGM: polish.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 193.6 KB

Line
1	/* $Id: PGMAllBth.h 13188 2008-10-11 01:58:30Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%VGp\n", (int)(((RTGCUINTPTR)pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%VGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
148	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
149
150	# if PGM_GST_TYPE == PGM_TYPE_PAE
151	/* Did we mark the PDPT as not present in SyncCR3? */
152	unsigned iPdpte = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
153	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
154	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 1;
155
156	# endif
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
159	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
160	PX86PDPAE pPDDst;
161	# if PGM_GST_TYPE == PGM_TYPE_PROT
162	/* AMD-V nested paging */
163	X86PML4E Pml4eSrc;
164	X86PDPE PdpeSrc;
165	PX86PML4E pPml4eSrc = &Pml4eSrc;
166
167	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
168	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
169	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
170	# endif
171
172	rc = PGMShwSyncLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
173	if (rc != VINF_SUCCESS)
174	{
175	AssertRC(rc);
176	return rc;
177	}
178	Assert(pPDDst);
179
180	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
181	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
182	PEPTPD pPDDst;
183
184	rc = PGMShwGetEPTPDPtr(pVM, (RTGCUINTPTR)pvFault, NULL, &pPDDst);
185	if (rc != VINF_SUCCESS)
186	{
187	AssertRC(rc);
188	return rc;
189	}
190	Assert(pPDDst);
191	# endif
192
193	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
194	/*
195	* If we successfully correct the write protection fault due to dirty bit
196	* tracking, or this page fault is a genuine one, then return immediately.
197	*/
198	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
199	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
200	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
201	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
202	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
203	{
204	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
205	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
206	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
207	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
208	}
209
210	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
211	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
212
213	/*
214	* A common case is the not-present error caused by lazy page table syncing.
215	*
216	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
217	* so we can safely assume that the shadow PT is present when calling SyncPage later.
218	*
219	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
220	* of mapping conflict and defer to SyncCR3 in R3.
221	* (Again, we do NOT support access handlers for non-present guest pages.)
222	*
223	*/
224	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
225	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
226	# else
227	GSTPDE PdeSrc;
228	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
229	PdeSrc.n.u1Present = 1;
230	PdeSrc.n.u1Write = 1;
231	PdeSrc.n.u1Accessed = 1;
232	PdeSrc.n.u1User = 1;
233	# endif
234	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
235	&& !pPDDst->a[iPDDst].n.u1Present
236	&& PdeSrc.n.u1Present
237	)
238
239	{
240	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
241	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
242	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
243	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
244	if (VBOX_SUCCESS(rc))
245	{
246	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
247	return rc;
248	}
249	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
250	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
251	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
252	return VINF_PGM_SYNC_CR3;
253	}
254
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	/*
257	* Check if this address is within any of our mappings.
258	*
259	* This is very fast and it's gonna save us a bit of effort below and prevent
260	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
261	* (BTW, it's impossible to have physical access handlers in a mapping.)
262	*/
263	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
264	{
265	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
266	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
267	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
268	{
269	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
270	break;
271	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
272	{
273	/*
274	* The first thing we check is if we've got an undetected conflict.
275	*/
276	if (!pVM->pgm.s.fMappingsFixed)
277	{
278	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
279	while (iPT-- > 0)
280	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
281	{
282	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
283	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
284	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
286	return VINF_PGM_SYNC_CR3;
287	}
288	}
289
290	/*
291	* Check if the fault address is in a virtual page access handler range.
292	*/
293	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
294	if ( pCur
295	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
296	&& uErr & X86_TRAP_PF_RW)
297	{
298	# ifdef IN_GC
299	STAM_PROFILE_START(&pCur->Stat, h);
300	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
301	STAM_PROFILE_STOP(&pCur->Stat, h);
302	# else
303	AssertFailed();
304	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
305	# endif
306	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
307	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
308	return rc;
309	}
310
311	/*
312	* Pretend we're not here and let the guest handle the trap.
313	*/
314	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
315	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
316	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
317	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
318	return VINF_EM_RAW_GUEST_TRAP;
319	}
320	}
321	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
322	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
323	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
324
325	/*
326	* Check if this fault address is flagged for special treatment,
327	* which means we'll have to figure out the physical address and
328	* check flags associated with it.
329	*
330	* ASSUME that we can limit any special access handling to pages
331	* in page tables which the guest believes to be present.
332	*/
333	if (PdeSrc.n.u1Present)
334	{
335	RTGCPHYS GCPhys = NIL_RTGCPHYS;
336
337	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
338	# if PGM_GST_TYPE == PGM_TYPE_AMD64
339	bool fBigPagesSupported = true;
340	# else
341	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
342	# endif
343	if ( PdeSrc.b.u1Size
344	&& fBigPagesSupported)
345	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
346	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
347	else
348	{
349	PGSTPT pPTSrc;
350	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
351	if (VBOX_SUCCESS(rc))
352	{
353	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
354	if (pPTSrc->a[iPTESrc].n.u1Present)
355	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
356	}
357	}
358	# else
359	/* No paging so the fault address is the physical address */
360	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
361	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
362
363	/*
364	* If we have a GC address we'll check if it has any flags set.
365	*/
366	if (GCPhys != NIL_RTGCPHYS)
367	{
368	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
369
370	PPGMPAGE pPage;
371	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
372	if (VBOX_SUCCESS(rc))
373	{
374	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
375	{
376	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
377	{
378	/*
379	* Physical page access handler.
380	*/
381	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
382	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
383	if (pCur)
384	{
385	# ifdef PGM_SYNC_N_PAGES
386	/*
387	* If the region is write protected and we got a page not present fault, then sync
388	* the pages. If the fault was caused by a read, then restart the instruction.
389	* In case of write access continue to the GC write handler.
390	*
391	* ASSUMES that there is only one handler per page or that they have similar write properties.
392	*/
393	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
394	&& !(uErr & X86_TRAP_PF_P))
395	{
396	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
397	if ( VBOX_FAILURE(rc)
398	\|\| !(uErr & X86_TRAP_PF_RW)
399	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
400	{
401	AssertRC(rc);
402	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
403	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
404	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
405	return rc;
406	}
407	}
408	# endif
409
410	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
411	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
412	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
413
414	# if defined(IN_GC) \|\| defined(IN_RING0)
415	if (pCur->CTX_SUFF(pfnHandler))
416	{
417	STAM_PROFILE_START(&pCur->Stat, h);
418	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
419	STAM_PROFILE_STOP(&pCur->Stat, h);
420	}
421	else
422	# endif
423	rc = VINF_EM_RAW_EMULATE_INSTR;
424	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
425	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
426	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
427	return rc;
428	}
429	}
430	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
431	else
432	{
433	# ifdef PGM_SYNC_N_PAGES
434	/*
435	* If the region is write protected and we got a page not present fault, then sync
436	* the pages. If the fault was caused by a read, then restart the instruction.
437	* In case of write access continue to the GC write handler.
438	*/
439	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
440	&& !(uErr & X86_TRAP_PF_P))
441	{
442	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
443	if ( VBOX_FAILURE(rc)
444	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
445	\|\| !(uErr & X86_TRAP_PF_RW))
446	{
447	AssertRC(rc);
448	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
449	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
450	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
451	return rc;
452	}
453	}
454	# endif
455	/*
456	* Ok, it's an virtual page access handler.
457	*
458	* Since it's faster to search by address, we'll do that first
459	* and then retry by GCPhys if that fails.
460	*/
461	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
462	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
463	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
464	*/
465	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
466	if (pCur)
467	{
468	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
469	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
470	\|\| !(uErr & X86_TRAP_PF_P)
471	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
472	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
473
474	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
475	&& ( uErr & X86_TRAP_PF_RW
476	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
477	{
478	# ifdef IN_GC
479	STAM_PROFILE_START(&pCur->Stat, h);
480	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
481	STAM_PROFILE_STOP(&pCur->Stat, h);
482	# else
483	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
484	# endif
485	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
486	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
487	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
488	return rc;
489	}
490	/* Unhandled part of a monitored page */
491	}
492	else
493	{
494	/* Check by physical address. */
495	PPGMVIRTHANDLER pCur;
496	unsigned iPage;
497	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
498	&pCur, &iPage);
499	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
500	if ( pCur
501	&& ( uErr & X86_TRAP_PF_RW
502	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
503	{
504	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
505	# ifdef IN_GC
506	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->Core.Key & PAGE_OFFSET_MASK);
507	Assert(off < pCur->cb);
508	STAM_PROFILE_START(&pCur->Stat, h);
509	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
510	STAM_PROFILE_STOP(&pCur->Stat, h);
511	# else
512	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
513	# endif
514	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
515	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
516	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
517	return rc;
518	}
519	}
520	}
521	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
522
523	/*
524	* There is a handled area of the page, but this fault doesn't belong to it.
525	* We must emulate the instruction.
526	*
527	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
528	* we first check if this was a page-not-present fault for a page with only
529	* write access handlers. Restart the instruction if it wasn't a write access.
530	*/
531	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
532
533	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
534	&& !(uErr & X86_TRAP_PF_P))
535	{
536	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
537	if ( VBOX_FAILURE(rc)
538	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
539	\|\| !(uErr & X86_TRAP_PF_RW))
540	{
541	AssertRC(rc);
542	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
543	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
544	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
545	return rc;
546	}
547	}
548
549	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
550	* It's writing to an unhandled part of the LDT page several million times.
551	*/
552	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
553	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
554	rc, pPage->HCPhys,
555	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
556	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
557	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
558	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
559	return rc;
560	} /* if any kind of handler */
561
562	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
563	if (uErr & X86_TRAP_PF_P)
564	{
565	/*
566	* The page isn't marked, but it might still be monitored by a virtual page access handler.
567	* (ASSUMES no temporary disabling of virtual handlers.)
568	*/
569	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
570	* we should correct both the shadow page table and physical memory flags, and not only check for
571	* accesses within the handler region but for access to pages with virtual handlers. */
572	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
573	if (pCur)
574	{
575	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb)
576	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
577	\|\| !(uErr & X86_TRAP_PF_P)
578	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
579	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
580
581	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key < pCur->cb
582	&& ( uErr & X86_TRAP_PF_RW
583	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
584	{
585	# ifdef IN_GC
586	STAM_PROFILE_START(&pCur->Stat, h);
587	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->Core.Key);
588	STAM_PROFILE_STOP(&pCur->Stat, h);
589	# else
590	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
591	# endif
592	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
593	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
594	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
595	return rc;
596	}
597	}
598	}
599	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
600	}
601	else
602	{
603	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
604	* back to the recompiler to emulate the instruction.
605	*/
606	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
607	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
608	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
609	return VINF_EM_RAW_EMULATE_INSTR;
610	}
611
612	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
613
614	# ifdef PGM_OUT_OF_SYNC_IN_GC
615	/*
616	* We are here only if page is present in Guest page tables and trap is not handled
617	* by our handlers.
618	* Check it for page out-of-sync situation.
619	*/
620	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
621
622	if (!(uErr & X86_TRAP_PF_P))
623	{
624	/*
625	* Page is not present in our page tables.
626	* Try to sync it!
627	* BTW, fPageShw is invalid in this branch!
628	*/
629	if (uErr & X86_TRAP_PF_US)
630	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
631	else /* supervisor */
632	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
633
634	# if defined(LOG_ENABLED) && !defined(IN_RING0)
635	RTGCPHYS GCPhys;
636	uint64_t fPageGst;
637	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
638	Log(("Page out of sync: %VGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
639	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
640	# endif /* LOG_ENABLED */
641
642	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
643	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
644	{
645	uint64_t fPageGst;
646	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
647	if ( VBOX_SUCCESS(rc)
648	&& !(fPageGst & X86_PTE_US))
649	{
650	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
651	if ( pvFault == (RTGCPTR)pRegFrame->eip
652	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
653	# ifdef CSAM_DETECT_NEW_CODE_PAGES
654	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
655	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
656	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
657	)
658	{
659	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
660	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
661	if (rc != VINF_SUCCESS)
662	{
663	/*
664	* CSAM needs to perform a job in ring 3.
665	*
666	* Sync the page before going to the host context; otherwise we'll end up in a loop if
667	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
668	*/
669	LogFlow(("CSAM ring 3 job\n"));
670	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
671	AssertRC(rc2);
672
673	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
674	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
675	return rc;
676	}
677	}
678	# ifdef CSAM_DETECT_NEW_CODE_PAGES
679	else
680	if ( uErr == X86_TRAP_PF_RW
681	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
682	&& pRegFrame->ecx < 0x10000
683	)
684	{
685	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
686	* to detect loading of new code pages.
687	*/
688
689	/*
690	* Decode the instruction.
691	*/
692	RTGCPTR PC;
693	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
694	if (rc == VINF_SUCCESS)
695	{
696	DISCPUSTATE Cpu;
697	uint32_t cbOp;
698	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
699
700	/* For now we'll restrict this to rep movsw/d instructions */
701	if ( rc == VINF_SUCCESS
702	&& Cpu.pCurInstr->opcode == OP_MOVSWD
703	&& (Cpu.prefix & PREFIX_REP))
704	{
705	CSAMMarkPossibleCodePage(pVM, pvFault);
706	}
707	}
708	}
709	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
710
711	/*
712	* Mark this page as safe.
713	*/
714	/** @todo not correct for pages that contain both code and data!! */
715	Log2(("CSAMMarkPage %VGv; scanned=%d\n", pvFault, true));
716	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
717	}
718	}
719	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
720	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
721	if (VBOX_SUCCESS(rc))
722	{
723	/* The page was successfully synced, return to the guest. */
724	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
725	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
726	return VINF_SUCCESS;
727	}
728	}
729	else
730	{
731	/*
732	* A side effect of not flushing global PDEs are out of sync pages due
733	* to physical monitored regions, that are no longer valid.
734	* Assume for now it only applies to the read/write flag
735	*/
736	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
737	{
738	if (uErr & X86_TRAP_PF_US)
739	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
740	else /* supervisor */
741	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
742
743
744	/*
745	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
746	*/
747	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
748	if (VBOX_SUCCESS(rc))
749	{
750	/*
751	* Page was successfully synced, return to guest.
752	*/
753	# ifdef VBOX_STRICT
754	RTGCPHYS GCPhys;
755	uint64_t fPageGst;
756	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
757	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
758	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
759
760	uint64_t fPageShw;
761	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
762	AssertMsg(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Vrc fPageShw=%VX64\n", rc, fPageShw));
763	# endif /* VBOX_STRICT */
764	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
765	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
766	return VINF_SUCCESS;
767	}
768
769	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
770	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
771	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
772	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
773	{
774	uint64_t fPageGst;
775	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
776	if ( VBOX_SUCCESS(rc)
777	&& !(fPageGst & X86_PTE_RW))
778	{
779	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
780	if (VBOX_SUCCESS(rc))
781	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
782	else
783	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
784	return rc;
785	}
786	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
787	}
788	}
789
790	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
791	# ifdef VBOX_STRICT
792	/*
793	* Check for VMM page flags vs. Guest page flags consistency.
794	* Currently only for debug purposes.
795	*/
796	if (VBOX_SUCCESS(rc))
797	{
798	/* Get guest page flags. */
799	uint64_t fPageGst;
800	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
801	if (VBOX_SUCCESS(rc))
802	{
803	uint64_t fPageShw;
804	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
805
806	/*
807	* Compare page flags.
808	* Note: we have AVL, A, D bits desynched.
809	*/
810	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
811	("Page flags mismatch! pvFault=%VGv GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
812	}
813	else
814	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
815	}
816	else
817	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
818	# endif /* VBOX_STRICT */
819	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
820	}
821	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
822	# endif /* PGM_OUT_OF_SYNC_IN_GC */
823	}
824	else
825	{
826	/*
827	* Page not present in Guest OS or invalid page table address.
828	* This is potential virtual page access handler food.
829	*
830	* For the present we'll say that our access handlers don't
831	* work for this case - we've already discarded the page table
832	* not present case which is identical to this.
833	*
834	* When we perchance find we need this, we will probably have AVL
835	* trees (offset based) to operate on and we can measure their speed
836	* agains mapping a page table and probably rearrange this handling
837	* a bit. (Like, searching virtual ranges before checking the
838	* physical address.)
839	*/
840	}
841	}
842
843
844	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
845	/*
846	* Conclusion, this is a guest trap.
847	*/
848	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
849	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
850	return VINF_EM_RAW_GUEST_TRAP;
851	# else
852	/* present, but not a monitored page; perhaps the guest is probing physical memory */
853	return VINF_EM_RAW_EMULATE_INSTR;
854	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
855
856
857	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
858
859	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
860	return VERR_INTERNAL_ERROR;
861	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
862	}
863	#endif /* !IN_RING3 */
864
865
866	/**
867	* Emulation of the invlpg instruction.
868	*
869	*
870	* @returns VBox status code.
871	*
872	* @param pVM VM handle.
873	* @param GCPtrPage Page to invalidate.
874	*
875	* @remark ASSUMES that the guest is updating before invalidating. This order
876	* isn't required by the CPU, so this is speculative and could cause
877	* trouble.
878	*
879	* @todo Flush page or page directory only if necessary!
880	* @todo Add a #define for simply invalidating the page.
881	*/
882	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
883	{
884	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
885	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
886	&& PGM_SHW_TYPE != PGM_TYPE_EPT
887	int rc;
888
889	LogFlow(("InvalidatePage %VGv\n", GCPtrPage));
890	/*
891	* Get the shadow PD entry and skip out if this PD isn't present.
892	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
893	*/
894	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
895	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
896	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
897	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
898	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
899	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
900	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
901	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
902
903	/* If the shadow PDPE isn't present, then skip the invalidate. */
904	if (!pPdptDst->a[iPdpte].n.u1Present)
905	{
906	Assert(!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING));
907	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
908	return VINF_SUCCESS;
909	}
910
911	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
912	/* PML4 */
913	AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
914
915	const unsigned iPml4e = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
916	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
917	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
918	PX86PDPAE pPDDst;
919	PX86PDPT pPdptDst;
920	PX86PML4E pPml4eDst = &pVM->pgm.s.pHCPaePML4->a[iPml4e];
921	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
922	if (rc != VINF_SUCCESS)
923	{
924	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
925	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
926	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
927	PGM_INVL_GUEST_TLBS();
928	return VINF_SUCCESS;
929	}
930	Assert(pPDDst);
931
932	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
933	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpte];
934
935	if (!pPdpeDst->n.u1Present)
936	{
937	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
938	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
939	PGM_INVL_GUEST_TLBS();
940	return VINF_SUCCESS;
941	}
942
943	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
944
945	const SHWPDE PdeDst = *pPdeDst;
946	if (!PdeDst.n.u1Present)
947	{
948	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
949	return VINF_SUCCESS;
950	}
951
952	/*
953	* Get the guest PD entry and calc big page.
954	*/
955	# if PGM_GST_TYPE == PGM_TYPE_32BIT
956	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
957	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
958	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
959	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
960	unsigned iPDSrc;
961	# if PGM_GST_TYPE == PGM_TYPE_PAE
962	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
963	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
964	# else /* AMD64 */
965	PX86PML4E pPml4eSrc;
966	X86PDPE PdpeSrc;
967	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
968	# endif
969	GSTPDE PdeSrc;
970
971	if (pPDSrc)
972	PdeSrc = pPDSrc->a[iPDSrc];
973	else
974	PdeSrc.u = 0;
975	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
976
977	# if PGM_GST_TYPE == PGM_TYPE_AMD64
978	const bool fIsBigPage = PdeSrc.b.u1Size;
979	# else
980	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
981	# endif
982
983	# ifdef IN_RING3
984	/*
985	* If a CR3 Sync is pending we may ignore the invalidate page operation
986	* depending on the kind of sync and if it's a global page or not.
987	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
988	*/
989	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
990	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
991	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
992	&& fIsBigPage
993	&& PdeSrc.b.u1Global
994	)
995	)
996	# else
997	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
998	# endif
999	{
1000	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1001	return VINF_SUCCESS;
1002	}
1003	# endif /* IN_RING3 */
1004
1005	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1006	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1007
1008	/* Fetch the pgm pool shadow descriptor. */
1009	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1010	Assert(pShwPdpt);
1011
1012	/* Fetch the pgm pool shadow descriptor. */
1013	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & SHW_PDPE_PG_MASK);
1014	Assert(pShwPde);
1015
1016	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1017	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1018
1019	if ( !pPml4eSrc->n.u1Present
1020	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1021	{
1022	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1023	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1024	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1025	pPml4eDst->u = 0;
1026	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1027	PGM_INVL_GUEST_TLBS();
1028	return VINF_SUCCESS;
1029	}
1030	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1031	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1032	{
1033	/*
1034	* Mark not present so we can resync the PML4E when it's used.
1035	*/
1036	LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1037	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1038	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1039	pPml4eDst->u = 0;
1040	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1041	PGM_INVL_GUEST_TLBS();
1042	}
1043	else if (!pPml4eSrc->n.u1Accessed)
1044	{
1045	/*
1046	* Mark not present so we can set the accessed bit.
1047	*/
1048	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1049	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1050	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
1051	pPml4eDst->u = 0;
1052	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1053	PGM_INVL_GUEST_TLBS();
1054	}
1055
1056	/* Check if the PDPT entry has changed. */
1057	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1058	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1059	if ( !PdpeSrc.n.u1Present
1060	\|\| pShwPde->GCPhys != GCPhysPd)
1061	{
1062	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %VGv GCPhys=%VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1063	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1064	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1065	pPdpeDst->u = 0;
1066	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1067	PGM_INVL_GUEST_TLBS();
1068	return VINF_SUCCESS;
1069	}
1070	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1071	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1072	{
1073	/*
1074	* Mark not present so we can resync the PDPTE when it's used.
1075	*/
1076	LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1077	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1078	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1079	pPdpeDst->u = 0;
1080	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1081	PGM_INVL_GUEST_TLBS();
1082	}
1083	else if (!PdpeSrc.lm.u1Accessed)
1084	{
1085	/*
1086	* Mark not present so we can set the accessed bit.
1087	*/
1088	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1089	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1090	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpte);
1091	pPdpeDst->u = 0;
1092	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1093	PGM_INVL_GUEST_TLBS();
1094	}
1095	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_PAE
1098	/* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes. */
1099	if (!pPDSrc)
1100	{
1101	/* Guest PDPE not present */
1102	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* root of the 2048 PDE array */
1103	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
1104	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1105
1106	Assert(!(CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte].n.u1Present));
1107	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
1108	/* for each page directory entry */
1109	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1110	{
1111	if ( pPDEDst[iPD].n.u1Present
1112	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
1113	{
1114	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
1115	pPDEDst[iPD].u = 0;
1116	}
1117	}
1118	if (!(pPdptDst->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
1119	pPdptDst->a[iPdpte].n.u1Present = 0;
1120	PGM_INVL_GUEST_TLBS();
1121	}
1122	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte], ("%VGp vs %VGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpte]));
1123	# endif
1124
1125
1126	/*
1127	* Deal with the Guest PDE.
1128	*/
1129	rc = VINF_SUCCESS;
1130	if (PdeSrc.n.u1Present)
1131	{
1132	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1133	{
1134	/*
1135	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1136	*/
1137	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1138	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1139	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1140	}
1141	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1142	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1143	{
1144	/*
1145	* Mark not present so we can resync the PDE when it's used.
1146	*/
1147	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1148	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1149	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1150	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1151	# else
1152	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1153	# endif
1154	pPdeDst->u = 0;
1155	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1156	PGM_INVL_GUEST_TLBS();
1157	}
1158	else if (!PdeSrc.n.u1Accessed)
1159	{
1160	/*
1161	* Mark not present so we can set the accessed bit.
1162	*/
1163	LogFlow(("InvalidatePage: Out-of-sync (A) at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1164	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1165	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1166	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1167	# else
1168	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1169	# endif
1170	pPdeDst->u = 0;
1171	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1172	PGM_INVL_GUEST_TLBS();
1173	}
1174	else if (!fIsBigPage)
1175	{
1176	/*
1177	* 4KB - page.
1178	*/
1179	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1180	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1181	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1182	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1183	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1184	# endif
1185	if (pShwPage->GCPhys == GCPhys)
1186	{
1187	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1188	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1189	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1190	if (pPT->a[iPTEDst].n.u1Present)
1191	{
1192	# ifdef PGMPOOL_WITH_USER_TRACKING
1193	/* This is very unlikely with caching/monitoring enabled. */
1194	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1195	# endif
1196	pPT->a[iPTEDst].u = 0;
1197	}
1198	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1199	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1200	if (VBOX_SUCCESS(rc))
1201	rc = VINF_SUCCESS;
1202	# endif
1203	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1204	PGM_INVL_PG(GCPtrPage);
1205	}
1206	else
1207	{
1208	/*
1209	* The page table address changed.
1210	*/
1211	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
1212	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1213	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1214	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1215	# else
1216	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1217	# endif
1218	pPdeDst->u = 0;
1219	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1220	PGM_INVL_GUEST_TLBS();
1221	}
1222	}
1223	else
1224	{
1225	/*
1226	* 2/4MB - page.
1227	*/
1228	/* Before freeing the page, check if anything really changed. */
1229	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1230	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1231	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1232	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1233	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1234	# endif
1235	if ( pShwPage->GCPhys == GCPhys
1236	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1237	{
1238	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1239	/** @todo PAT */
1240	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1241	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1242	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1243	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1244	{
1245	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1246	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1247	return VINF_SUCCESS;
1248	}
1249	}
1250
1251	/*
1252	* Ok, the page table is present and it's been changed in the guest.
1253	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1254	* We could do this for some flushes in GC too, but we need an algorithm for
1255	* deciding which 4MB pages containing code likely to be executed very soon.
1256	*/
1257	LogFlow(("InvalidatePage: Out-of-sync PD at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1258	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1259	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1260	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1261	# else
1262	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1263	# endif
1264	pPdeDst->u = 0;
1265	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1266	PGM_INVL_BIG_PG(GCPtrPage);
1267	}
1268	}
1269	else
1270	{
1271	/*
1272	* Page directory is not present, mark shadow PDE not present.
1273	*/
1274	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1275	{
1276	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1277	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1278	# else
1279	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1280	# endif
1281	pPdeDst->u = 0;
1282	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1283	PGM_INVL_PG(GCPtrPage);
1284	}
1285	else
1286	{
1287	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1288	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1289	}
1290	}
1291
1292	return rc;
1293
1294	#else /* guest real and protected mode */
1295	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1296	return VINF_SUCCESS;
1297	#endif
1298	}
1299
1300
1301	#ifdef PGMPOOL_WITH_USER_TRACKING
1302	/**
1303	* Update the tracking of shadowed pages.
1304	*
1305	* @param pVM The VM handle.
1306	* @param pShwPage The shadow page.
1307	* @param HCPhys The physical page we is being dereferenced.
1308	*/
1309	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1310	{
1311	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1312	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1313	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1314
1315	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1316	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1317	* 2. write protect all shadowed pages. I.e. implement caching.
1318	*/
1319	/*
1320	* Find the guest address.
1321	*/
1322	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1323	pRam;
1324	pRam = pRam->CTX_SUFF(pNext))
1325	{
1326	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1327	while (iPage-- > 0)
1328	{
1329	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1330	{
1331	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1332	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1333	pShwPage->cPresent--;
1334	pPool->cPresent--;
1335	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1336	return;
1337	}
1338	}
1339	}
1340
1341	for (;;)
1342	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1343	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1344	pShwPage->cPresent--;
1345	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1346	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1347	}
1348
1349
1350	/**
1351	* Update the tracking of shadowed pages.
1352	*
1353	* @param pVM The VM handle.
1354	* @param pShwPage The shadow page.
1355	* @param u16 The top 16-bit of the pPage->HCPhys.
1356	* @param pPage Pointer to the guest page. this will be modified.
1357	* @param iPTDst The index into the shadow table.
1358	*/
1359	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1360	{
1361	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1362	/*
1363	* We're making certain assumptions about the placement of cRef and idx.
1364	*/
1365	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1366	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1367
1368	/*
1369	* Just deal with the simple first time here.
1370	*/
1371	if (!u16)
1372	{
1373	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1374	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1375	}
1376	else
1377	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1378
1379	/* write back, trying to be clever... */
1380	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1381	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1382	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1383	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1384
1385	/* update statistics. */
1386	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1387	pShwPage->cPresent++;
1388	if (pShwPage->iFirstPresent > iPTDst)
1389	pShwPage->iFirstPresent = iPTDst;
1390	}
1391	#endif /* PGMPOOL_WITH_USER_TRACKING */
1392
1393
1394	/**
1395	* Creates a 4K shadow page for a guest page.
1396	*
1397	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1398	* physical address. The PdeSrc argument only the flags are used. No page structured
1399	* will be mapped in this function.
1400	*
1401	* @param pVM VM handle.
1402	* @param pPteDst Destination page table entry.
1403	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1404	* Can safely assume that only the flags are being used.
1405	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1406	* @param pShwPage Pointer to the shadow page.
1407	* @param iPTDst The index into the shadow table.
1408	*
1409	* @remark Not used for 2/4MB pages!
1410	*/
1411	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1412	{
1413	if (PteSrc.n.u1Present)
1414	{
1415	/*
1416	* Find the ram range.
1417	*/
1418	PPGMPAGE pPage;
1419	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1420	if (VBOX_SUCCESS(rc))
1421	{
1422	/** @todo investiage PWT, PCD and PAT. */
1423	/*
1424	* Make page table entry.
1425	*/
1426	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1427	SHWPTE PteDst;
1428	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1429	{
1430	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1431	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1432	{
1433	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1434	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1435	PteDst.n.u1Present = 1;
1436	PteDst.n.u1Execute = 1;
1437	PteDst.n.u1IgnorePAT = 1;
1438	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1439	/* PteDst.n.u1Write = 0 && PteDst.n.u1Big = 0 */
1440	#else
1441	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1442	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1443	#endif
1444	}
1445	else
1446	{
1447	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1448	PteDst.u = 0;
1449	}
1450	/** @todo count these two kinds. */
1451	}
1452	else
1453	{
1454	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1455	/*
1456	* If the page or page directory entry is not marked accessed,
1457	* we mark the page not present.
1458	*/
1459	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1460	{
1461	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1462	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1463	PteDst.u = 0;
1464	}
1465	else
1466	/*
1467	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1468	* when the page is modified.
1469	*/
1470	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1471	{
1472	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1473	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1474	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1475	\| PGM_PTFLAGS_TRACK_DIRTY;
1476	}
1477	else
1478	#endif
1479	{
1480	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1481	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1482	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1483	PteDst.n.u1Present = 1;
1484	PteDst.n.u1Write = 1;
1485	PteDst.n.u1Execute = 1;
1486	PteDst.n.u1IgnorePAT = 1;
1487	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1488	/* PteDst.n.u1Big = 0 */
1489	#else
1490	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1491	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1492	#endif
1493	}
1494	}
1495
1496	#ifdef PGMPOOL_WITH_USER_TRACKING
1497	/*
1498	* Keep user track up to date.
1499	*/
1500	if (PteDst.n.u1Present)
1501	{
1502	if (!pPteDst->n.u1Present)
1503	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1504	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1505	{
1506	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1507	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1508	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1509	}
1510	}
1511	else if (pPteDst->n.u1Present)
1512	{
1513	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1514	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1515	}
1516	#endif /* PGMPOOL_WITH_USER_TRACKING */
1517
1518	/*
1519	* Update statistics and commit the entry.
1520	*/
1521	if (!PteSrc.n.u1Global)
1522	pShwPage->fSeenNonGlobal = true;
1523	*pPteDst = PteDst;
1524	}
1525	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1526	/** @todo count these. */
1527	}
1528	else
1529	{
1530	/*
1531	* Page not-present.
1532	*/
1533	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1534	#ifdef PGMPOOL_WITH_USER_TRACKING
1535	/* Keep user track up to date. */
1536	if (pPteDst->n.u1Present)
1537	{
1538	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1539	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1540	}
1541	#endif /* PGMPOOL_WITH_USER_TRACKING */
1542	pPteDst->u = 0;
1543	/** @todo count these. */
1544	}
1545	}
1546
1547
1548	/**
1549	* Syncs a guest OS page.
1550	*
1551	* There are no conflicts at this point, neither is there any need for
1552	* page table allocations.
1553	*
1554	* @returns VBox status code.
1555	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1556	* @param pVM VM handle.
1557	* @param PdeSrc Page directory entry of the guest.
1558	* @param GCPtrPage Guest context page address.
1559	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1560	* @param uErr Fault error (X86_TRAP_PF_*).
1561	*/
1562	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1563	{
1564	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1565
1566	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1567	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1568	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1569	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1570	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1571
1572	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1573	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1574	# endif
1575
1576	/*
1577	* Assert preconditions.
1578	*/
1579	Assert(PdeSrc.n.u1Present);
1580	Assert(cPages);
1581	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1582
1583	/*
1584	* Get the shadow PDE, find the shadow page table in the pool.
1585	*/
1586	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1587	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1588	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1589	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1590	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1591	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte); /* no mask; flat index into the 2048 entry array. */
1592	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
1593	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1594	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1595	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1596	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1597	PX86PDPAE pPDDst;
1598	X86PDEPAE PdeDst;
1599	PX86PDPT pPdptDst;
1600
1601	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1602	AssertRCSuccessReturn(rc, rc);
1603	Assert(pPDDst && pPdptDst);
1604	PdeDst = pPDDst->a[iPDDst];
1605	# endif
1606	Assert(PdeDst.n.u1Present);
1607	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1608
1609	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1610	/* Fetch the pgm pool shadow descriptor. */
1611	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
1612	Assert(pShwPde);
1613	# endif
1614
1615	/*
1616	* Check that the page is present and that the shadow PDE isn't out of sync.
1617	*/
1618	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1619	const bool fBigPage = PdeSrc.b.u1Size;
1620	# else
1621	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1622	# endif
1623	RTGCPHYS GCPhys;
1624	if (!fBigPage)
1625	{
1626	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1627	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1628	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1629	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1630	# endif
1631	}
1632	else
1633	{
1634	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1635	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1636	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1637	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1638	# endif
1639	}
1640	if ( pShwPage->GCPhys == GCPhys
1641	&& PdeSrc.n.u1Present
1642	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1643	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1644	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1645	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1646	# endif
1647	)
1648	{
1649	/*
1650	* Check that the PDE is marked accessed already.
1651	* Since we set the accessed bit before getting here on a #PF, this
1652	* check is only meant for dealing with non-#PF'ing paths.
1653	*/
1654	if (PdeSrc.n.u1Accessed)
1655	{
1656	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1657	if (!fBigPage)
1658	{
1659	/*
1660	* 4KB Page - Map the guest page table.
1661	*/
1662	PGSTPT pPTSrc;
1663	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1664	if (VBOX_SUCCESS(rc))
1665	{
1666	# ifdef PGM_SYNC_N_PAGES
1667	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1668	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1669	{
1670	/*
1671	* This code path is currently only taken when the caller is PGMTrap0eHandler
1672	* for non-present pages!
1673	*
1674	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1675	* deal with locality.
1676	*/
1677	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1678	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1679	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1680	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1681	# else
1682	const unsigned offPTSrc = 0;
1683	# endif
1684	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1685	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1686	iPTDst = 0;
1687	else
1688	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1689	for (; iPTDst < iPTDstEnd; iPTDst++)
1690	{
1691	if (!pPTDst->a[iPTDst].n.u1Present)
1692	{
1693	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1694	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1695	NOREF(GCPtrCurPage);
1696	#ifndef IN_RING0
1697	/*
1698	* Assuming kernel code will be marked as supervisor - and not as user level
1699	* and executed using a conforming code selector - And marked as readonly.
1700	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1701	*/
1702	PPGMPAGE pPage;
1703	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1704	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1705	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1706	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1707	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1708	)
1709	#endif /* else: CSAM not active */
1710	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1711	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1712	GCPtrCurPage, PteSrc.n.u1Present,
1713	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1714	PteSrc.n.u1User & PdeSrc.n.u1User,
1715	(uint64_t)PteSrc.u,
1716	(uint64_t)pPTDst->a[iPTDst].u,
1717	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1718	}
1719	}
1720	}
1721	else
1722	# endif /* PGM_SYNC_N_PAGES */
1723	{
1724	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1725	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1726	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1727	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1728	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1729	GCPtrPage, PteSrc.n.u1Present,
1730	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1731	PteSrc.n.u1User & PdeSrc.n.u1User,
1732	(uint64_t)PteSrc.u,
1733	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1734	}
1735	}
1736	else /* MMIO or invalid page: emulated in #PF handler. */
1737	{
1738	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1739	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1740	}
1741	}
1742	else
1743	{
1744	/*
1745	* 4/2MB page - lazy syncing shadow 4K pages.
1746	* (There are many causes of getting here, it's no longer only CSAM.)
1747	*/
1748	/* Calculate the GC physical address of this 4KB shadow page. */
1749	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1750	/* Find ram range. */
1751	PPGMPAGE pPage;
1752	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1753	if (VBOX_SUCCESS(rc))
1754	{
1755	/*
1756	* Make shadow PTE entry.
1757	*/
1758	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1759	SHWPTE PteDst;
1760	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1761	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1762	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1763	{
1764	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1765	PteDst.n.u1Write = 0;
1766	else
1767	PteDst.u = 0;
1768	}
1769	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1770	# ifdef PGMPOOL_WITH_USER_TRACKING
1771	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1772	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1773	# endif
1774	pPTDst->a[iPTDst] = PteDst;
1775
1776
1777	/*
1778	* If the page is not flagged as dirty and is writable, then make it read-only
1779	* at PD level, so we can set the dirty bit when the page is modified.
1780	*
1781	* ASSUMES that page access handlers are implemented on page table entry level.
1782	* Thus we will first catch the dirty access and set PDE.D and restart. If
1783	* there is an access handler, we'll trap again and let it work on the problem.
1784	*/
1785	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1786	* As for invlpg, it simply frees the whole shadow PT.
1787	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1788	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1789	{
1790	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1791	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1792	PdeDst.n.u1Write = 0;
1793	}
1794	else
1795	{
1796	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1797	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1798	}
1799	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1800	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1801	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1802	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1803	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1804	pPDDst->a[iPDDst] = PdeDst;
1805	# endif
1806	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1807	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1808	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1809	}
1810	else
1811	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1812	}
1813	return VINF_SUCCESS;
1814	}
1815	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1816	}
1817	else
1818	{
1819	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1820	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1821	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1822	}
1823
1824	/*
1825	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1826	* Yea, I'm lazy.
1827	*/
1828	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1829	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1830	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1831	# else
1832	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1833	# endif
1834
1835	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1836	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1837	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1838	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1839	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1840	pPDDst->a[iPDDst].u = 0;
1841	# endif
1842	PGM_INVL_GUEST_TLBS();
1843	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1844
1845	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1846	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1847	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1848
1849	# ifdef PGM_SYNC_N_PAGES
1850	/*
1851	* Get the shadow PDE, find the shadow page table in the pool.
1852	*/
1853	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1854	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1855	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1856	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1857	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
1858	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1859	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1860	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1861	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpte);
1862	PX86PDPAE pPDDst;
1863	X86PDEPAE PdeDst;
1864	PX86PDPT pPdptDst;
1865
1866	int rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
1867	AssertRCSuccessReturn(rc, rc);
1868	Assert(pPDDst && pPdptDst);
1869	PdeDst = pPDDst->a[iPDDst];
1870	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1871	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1872	PEPTPD pPDDst;
1873	EPTPDE PdeDst;
1874
1875	int rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1876	if (rc != VINF_SUCCESS)
1877	{
1878	AssertRC(rc);
1879	return rc;
1880	}
1881	Assert(pPDDst);
1882	PdeDst = pPDDst->a[iPDDst];
1883	# endif
1884	Assert(PdeDst.n.u1Present);
1885	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1886	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1887
1888	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1889	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1890	{
1891	/*
1892	* This code path is currently only taken when the caller is PGMTrap0eHandler
1893	* for non-present pages!
1894	*
1895	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1896	* deal with locality.
1897	*/
1898	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1899	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1900	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1901	iPTDst = 0;
1902	else
1903	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1904	for (; iPTDst < iPTDstEnd; iPTDst++)
1905	{
1906	if (!pPTDst->a[iPTDst].n.u1Present)
1907	{
1908	GSTPTE PteSrc;
1909
1910	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1911
1912	/* Fake the page table entry */
1913	PteSrc.u = GCPtrCurPage;
1914	PteSrc.n.u1Present = 1;
1915	PteSrc.n.u1Dirty = 1;
1916	PteSrc.n.u1Accessed = 1;
1917	PteSrc.n.u1Write = 1;
1918	PteSrc.n.u1User = 1;
1919
1920	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1921
1922	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1923	GCPtrCurPage, PteSrc.n.u1Present,
1924	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1925	PteSrc.n.u1User & PdeSrc.n.u1User,
1926	(uint64_t)PteSrc.u,
1927	(uint64_t)pPTDst->a[iPTDst].u,
1928	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1929	}
1930	else
1931	Log4(("%VGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1932	}
1933	}
1934	else
1935	# endif /* PGM_SYNC_N_PAGES */
1936	{
1937	GSTPTE PteSrc;
1938	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1939	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1940
1941	/* Fake the page table entry */
1942	PteSrc.u = GCPtrCurPage;
1943	PteSrc.n.u1Present = 1;
1944	PteSrc.n.u1Dirty = 1;
1945	PteSrc.n.u1Accessed = 1;
1946	PteSrc.n.u1Write = 1;
1947	PteSrc.n.u1User = 1;
1948	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1949
1950	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1951	GCPtrPage, PteSrc.n.u1Present,
1952	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1953	PteSrc.n.u1User & PdeSrc.n.u1User,
1954	(uint64_t)PteSrc.u,
1955	(uint64_t)pPTDst->a[iPTDst].u,
1956	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1957	}
1958	return VINF_SUCCESS;
1959
1960	#else
1961	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1962	return VERR_INTERNAL_ERROR;
1963	#endif
1964	}
1965
1966
1967
1968	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1969
1970	/**
1971	* Investigate page fault and handle write protection page faults caused by
1972	* dirty bit tracking.
1973	*
1974	* @returns VBox status code.
1975	* @param pVM VM handle.
1976	* @param uErr Page fault error code.
1977	* @param pPdeDst Shadow page directory entry.
1978	* @param pPdeSrc Guest page directory entry.
1979	* @param GCPtrPage Guest context page address.
1980	*/
1981	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1982	{
1983	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1984	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1985	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1986	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1987	bool fBigPagesSupported = true;
1988	# else
1989	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1990	# endif
1991	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1992	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1993	# endif
1994	unsigned uPageFaultLevel;
1995	int rc;
1996
1997	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
1998	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1999
2000	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2001	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2002
2003	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2004	PX86PML4E pPml4eSrc;
2005	PX86PDPE pPdpeSrc;
2006
2007	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2008	Assert(pPml4eSrc);
2009
2010	/*
2011	* Real page fault? (PML4E level)
2012	*/
2013	if ( (uErr & X86_TRAP_PF_RSVD)
2014	\|\| !pPml4eSrc->n.u1Present
2015	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2016	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2017	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2018	)
2019	{
2020	uPageFaultLevel = 0;
2021	goto UpperLevelPageFault;
2022	}
2023	Assert(pPdpeSrc);
2024
2025	# else /* PAE */
2026	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
2027	# endif
2028
2029	/*
2030	* Real page fault? (PDPE level)
2031	*/
2032	if ( (uErr & X86_TRAP_PF_RSVD)
2033	\|\| !pPdpeSrc->n.u1Present
2034	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2035	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2036	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2037	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2038	# endif
2039	)
2040	{
2041	uPageFaultLevel = 1;
2042	goto UpperLevelPageFault;
2043	}
2044	# endif
2045
2046	/*
2047	* Real page fault? (PDE level)
2048	*/
2049	if ( (uErr & X86_TRAP_PF_RSVD)
2050	\|\| !pPdeSrc->n.u1Present
2051	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2052	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2053	# endif
2054	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2055	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2056	{
2057	uPageFaultLevel = 2;
2058	goto UpperLevelPageFault;
2059	}
2060
2061	/*
2062	* First check the easy case where the page directory has been marked read-only to track
2063	* the dirty bit of an emulated BIG page
2064	*/
2065	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2066	{
2067	/* Mark guest page directory as accessed */
2068	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2069	pPml4eSrc->n.u1Accessed = 1;
2070	pPdpeSrc->lm.u1Accessed = 1;
2071	# endif
2072	pPdeSrc->b.u1Accessed = 1;
2073
2074	/*
2075	* Only write protection page faults are relevant here.
2076	*/
2077	if (fWriteFault)
2078	{
2079	/* Mark guest page directory as dirty (BIG page only). */
2080	pPdeSrc->b.u1Dirty = 1;
2081
2082	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2083	{
2084	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2085
2086	Assert(pPdeSrc->b.u1Write);
2087
2088	pPdeDst->n.u1Write = 1;
2089	pPdeDst->n.u1Accessed = 1;
2090	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2091	PGM_INVL_BIG_PG(GCPtrPage);
2092	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2093	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2094	}
2095	}
2096	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2097	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2098	}
2099	/* else: 4KB page table */
2100
2101	/*
2102	* Map the guest page table.
2103	*/
2104	PGSTPT pPTSrc;
2105	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2106	if (VBOX_SUCCESS(rc))
2107	{
2108	/*
2109	* Real page fault?
2110	*/
2111	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2112	const GSTPTE PteSrc = *pPteSrc;
2113	if ( !PteSrc.n.u1Present
2114	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2115	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2116	# endif
2117	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2118	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2119	)
2120	{
2121	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2122	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2123	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2124
2125	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2126	* See the 2nd case above as well.
2127	*/
2128	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2129	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2130
2131	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2132	return VINF_EM_RAW_GUEST_TRAP;
2133	}
2134	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2135
2136	/*
2137	* Set the accessed bits in the page directory and the page table.
2138	*/
2139	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2140	pPml4eSrc->n.u1Accessed = 1;
2141	pPdpeSrc->lm.u1Accessed = 1;
2142	# endif
2143	pPdeSrc->n.u1Accessed = 1;
2144	pPteSrc->n.u1Accessed = 1;
2145
2146	/*
2147	* Only write protection page faults are relevant here.
2148	*/
2149	if (fWriteFault)
2150	{
2151	/* Write access, so mark guest entry as dirty. */
2152	# ifdef VBOX_WITH_STATISTICS
2153	if (!pPteSrc->n.u1Dirty)
2154	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2155	else
2156	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2157	# endif
2158
2159	pPteSrc->n.u1Dirty = 1;
2160
2161	if (pPdeDst->n.u1Present)
2162	{
2163	#ifndef IN_RING0
2164	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2165	* Our individual shadow handlers will provide more information and force a fatal exit.
2166	*/
2167	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2168	{
2169	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
2170	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2171	return VINF_SUCCESS;
2172	}
2173	#endif
2174	/*
2175	* Map shadow page table.
2176	*/
2177	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2178	if (pShwPage)
2179	{
2180	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2181	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2182	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2183	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2184	{
2185	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
2186	# ifdef VBOX_STRICT
2187	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2188	if (pPage)
2189	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2190	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2191	# endif
2192	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2193
2194	Assert(pPteSrc->n.u1Write);
2195
2196	pPteDst->n.u1Write = 1;
2197	pPteDst->n.u1Dirty = 1;
2198	pPteDst->n.u1Accessed = 1;
2199	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2200	PGM_INVL_PG(GCPtrPage);
2201
2202	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2203	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2204	}
2205	}
2206	else
2207	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2208	}
2209	}
2210	/** @todo Optimize accessed bit emulation? */
2211	# ifdef VBOX_STRICT
2212	/*
2213	* Sanity check.
2214	*/
2215	else if ( !pPteSrc->n.u1Dirty
2216	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2217	&& pPdeDst->n.u1Present)
2218	{
2219	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2220	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2221	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2222	if ( pPteDst->n.u1Present
2223	&& pPteDst->n.u1Write)
2224	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2225	}
2226	# endif /* VBOX_STRICT */
2227	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2228	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2229	}
2230	AssertRC(rc);
2231	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2232	return rc;
2233
2234
2235	UpperLevelPageFault:
2236	/* Pagefault detected while checking the PML4E, PDPE or PDE.
2237	* Single exit handler to get rid of duplicate code paths.
2238	*/
2239	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2240	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2241	Log(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
2242
2243	if (
2244	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2245	pPml4eSrc->n.u1Present &&
2246	# endif
2247	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2248	pPdpeSrc->n.u1Present &&
2249	# endif
2250	pPdeSrc->n.u1Present)
2251	{
2252	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2253	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2254	{
2255	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2256	}
2257	else
2258	{
2259	/*
2260	* Map the guest page table.
2261	*/
2262	PGSTPT pPTSrc;
2263	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2264	if (VBOX_SUCCESS(rc))
2265	{
2266	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2267	const GSTPTE PteSrc = *pPteSrc;
2268	if (pPteSrc->n.u1Present)
2269	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2270	}
2271	AssertRC(rc);
2272	}
2273	}
2274	return VINF_EM_RAW_GUEST_TRAP;
2275	}
2276
2277	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2278
2279
2280	/**
2281	* Sync a shadow page table.
2282	*
2283	* The shadow page table is not present. This includes the case where
2284	* there is a conflict with a mapping.
2285	*
2286	* @returns VBox status code.
2287	* @param pVM VM handle.
2288	* @param iPD Page directory index.
2289	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2290	* Assume this is a temporary mapping.
2291	* @param GCPtrPage GC Pointer of the page that caused the fault
2292	*/
2293	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
2294	{
2295	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2296	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2297	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
2298
2299	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2300	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2301	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2302	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2303	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2304
2305	int rc = VINF_SUCCESS;
2306
2307	/*
2308	* Validate input a little bit.
2309	*/
2310	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
2311	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2312	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2313	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2314	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2315	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2316	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpte);
2317	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
2318	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2319	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2320	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2321	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2322	PX86PDPAE pPDDst;
2323	PX86PDPT pPdptDst;
2324	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2325	AssertRCSuccessReturn(rc, rc);
2326	Assert(pPDDst);
2327	# endif
2328
2329	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2330	SHWPDE PdeDst = *pPdeDst;
2331
2332	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2333	/* Fetch the pgm pool shadow descriptor. */
2334	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2335	Assert(pShwPde);
2336	# endif
2337
2338	# ifndef PGM_WITHOUT_MAPPINGS
2339	/*
2340	* Check for conflicts.
2341	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2342	* HC: Simply resolve the conflict.
2343	*/
2344	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2345	{
2346	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2347	# ifndef IN_RING3
2348	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2349	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2350	return VERR_ADDRESS_CONFLICT;
2351	# else
2352	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2353	Assert(pMapping);
2354	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2355	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2356	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2357	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2358	# else
2359	AssertFailed(); /* can't happen for amd64 */
2360	# endif
2361	if (VBOX_FAILURE(rc))
2362	{
2363	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2364	return rc;
2365	}
2366	PdeDst = *pPdeDst;
2367	# endif
2368	}
2369	# else /* PGM_WITHOUT_MAPPINGS */
2370	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2371	# endif /* PGM_WITHOUT_MAPPINGS */
2372	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2373
2374	/*
2375	* Sync page directory entry.
2376	*/
2377	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2378	if (PdeSrc.n.u1Present)
2379	{
2380	/*
2381	* Allocate & map the page table.
2382	*/
2383	PSHWPT pPTDst;
2384	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2385	const bool fPageTable = !PdeSrc.b.u1Size;
2386	# else
2387	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2388	# endif
2389	PPGMPOOLPAGE pShwPage;
2390	RTGCPHYS GCPhys;
2391	if (fPageTable)
2392	{
2393	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2394	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2395	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2396	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2397	# endif
2398	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2399	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2400	# else
2401	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2402	# endif
2403	}
2404	else
2405	{
2406	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2407	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2408	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2409	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2410	# endif
2411	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2412	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2413	# else
2414	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2415	# endif
2416	}
2417	if (rc == VINF_SUCCESS)
2418	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2419	else if (rc == VINF_PGM_CACHED_PAGE)
2420	{
2421	/*
2422	* The PT was cached, just hook it up.
2423	*/
2424	if (fPageTable)
2425	PdeDst.u = pShwPage->Core.Key
2426	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2427	else
2428	{
2429	PdeDst.u = pShwPage->Core.Key
2430	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2431	/* (see explanation and assumptions further down.) */
2432	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2433	{
2434	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2435	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2436	PdeDst.b.u1Write = 0;
2437	}
2438	}
2439	*pPdeDst = PdeDst;
2440	return VINF_SUCCESS;
2441	}
2442	else if (rc == VERR_PGM_POOL_FLUSHED)
2443	{
2444	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2445	return VINF_PGM_SYNC_CR3;
2446	}
2447	else
2448	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2449	PdeDst.u &= X86_PDE_AVL_MASK;
2450	PdeDst.u \|= pShwPage->Core.Key;
2451
2452	/*
2453	* Page directory has been accessed (this is a fault situation, remember).
2454	*/
2455	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2456	if (fPageTable)
2457	{
2458	/*
2459	* Page table - 4KB.
2460	*
2461	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2462	*/
2463	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2464	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2465	PGSTPT pPTSrc;
2466	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2467	if (VBOX_SUCCESS(rc))
2468	{
2469	/*
2470	* Start by syncing the page directory entry so CSAM's TLB trick works.
2471	*/
2472	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2473	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2474	*pPdeDst = PdeDst;
2475
2476	/*
2477	* Directory/page user or supervisor privilege: (same goes for read/write)
2478	*
2479	* Directory Page Combined
2480	* U/S U/S U/S
2481	* 0 0 0
2482	* 0 1 0
2483	* 1 0 0
2484	* 1 1 1
2485	*
2486	* Simple AND operation. Table listed for completeness.
2487	*
2488	*/
2489	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2490	# ifdef PGM_SYNC_N_PAGES
2491	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2492	unsigned iPTDst = iPTBase;
2493	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2494	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2495	iPTDst = 0;
2496	else
2497	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2498	# else /* !PGM_SYNC_N_PAGES */
2499	unsigned iPTDst = 0;
2500	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2501	# endif /* !PGM_SYNC_N_PAGES */
2502	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2503	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2504	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2505	# else
2506	const unsigned offPTSrc = 0;
2507	# endif
2508	for (; iPTDst < iPTDstEnd; iPTDst++)
2509	{
2510	const unsigned iPTSrc = iPTDst + offPTSrc;
2511	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2512
2513	if (PteSrc.n.u1Present) /* we've already cleared it above */
2514	{
2515	# ifndef IN_RING0
2516	/*
2517	* Assuming kernel code will be marked as supervisor - and not as user level
2518	* and executed using a conforming code selector - And marked as readonly.
2519	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2520	*/
2521	PPGMPAGE pPage;
2522	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2523	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2524	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2525	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2526	)
2527	# endif
2528	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2529	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2530	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2531	PteSrc.n.u1Present,
2532	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2533	PteSrc.n.u1User & PdeSrc.n.u1User,
2534	(uint64_t)PteSrc.u,
2535	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2536	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2537	}
2538	} /* for PTEs */
2539	}
2540	}
2541	else
2542	{
2543	/*
2544	* Big page - 2/4MB.
2545	*
2546	* We'll walk the ram range list in parallel and optimize lookups.
2547	* We will only sync on shadow page table at a time.
2548	*/
2549	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2550
2551	/**
2552	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2553	*/
2554
2555	/*
2556	* Start by syncing the page directory entry.
2557	*/
2558	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2559	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2560
2561	/*
2562	* If the page is not flagged as dirty and is writable, then make it read-only
2563	* at PD level, so we can set the dirty bit when the page is modified.
2564	*
2565	* ASSUMES that page access handlers are implemented on page table entry level.
2566	* Thus we will first catch the dirty access and set PDE.D and restart. If
2567	* there is an access handler, we'll trap again and let it work on the problem.
2568	*/
2569	/** @todo move the above stuff to a section in the PGM documentation. */
2570	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2571	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2572	{
2573	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2574	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2575	PdeDst.b.u1Write = 0;
2576	}
2577	*pPdeDst = PdeDst;
2578
2579	/*
2580	* Fill the shadow page table.
2581	*/
2582	/* Get address and flags from the source PDE. */
2583	SHWPTE PteDstBase;
2584	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2585
2586	/* Loop thru the entries in the shadow PT. */
2587	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2588	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2589	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2590	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2591	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2592	unsigned iPTDst = 0;
2593	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2594	{
2595	/* Advance ram range list. */
2596	while (pRam && GCPhys > pRam->GCPhysLast)
2597	pRam = pRam->CTX_SUFF(pNext);
2598	if (pRam && GCPhys >= pRam->GCPhys)
2599	{
2600	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2601	do
2602	{
2603	/* Make shadow PTE. */
2604	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2605	SHWPTE PteDst;
2606
2607	/* Make sure the RAM has already been allocated. */
2608	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2609	{
2610	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2611	{
2612	# ifdef IN_RING3
2613	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2614	# else
2615	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2616	# endif
2617	if (rc != VINF_SUCCESS)
2618	return rc;
2619	}
2620	}
2621
2622	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2623	{
2624	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2625	{
2626	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2627	PteDst.n.u1Write = 0;
2628	}
2629	else
2630	PteDst.u = 0;
2631	}
2632	# ifndef IN_RING0
2633	/*
2634	* Assuming kernel code will be marked as supervisor and not as user level and executed
2635	* using a conforming code selector. Don't check for readonly, as that implies the whole
2636	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2637	*/
2638	else if ( !PdeSrc.n.u1User
2639	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2640	PteDst.u = 0;
2641	# endif
2642	else
2643	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2644	# ifdef PGMPOOL_WITH_USER_TRACKING
2645	if (PteDst.n.u1Present)
2646	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2647	# endif
2648	/* commit it */
2649	pPTDst->a[iPTDst] = PteDst;
2650	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2651	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2652	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2653
2654	/* advance */
2655	GCPhys += PAGE_SIZE;
2656	iHCPage++;
2657	iPTDst++;
2658	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2659	&& GCPhys <= pRam->GCPhysLast);
2660	}
2661	else if (pRam)
2662	{
2663	Log(("Invalid pages at %VGp\n", GCPhys));
2664	do
2665	{
2666	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2667	GCPhys += PAGE_SIZE;
2668	iPTDst++;
2669	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2670	&& GCPhys < pRam->GCPhys);
2671	}
2672	else
2673	{
2674	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2675	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2676	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2677	}
2678	} /* while more PTEs */
2679	} /* 4KB / 4MB */
2680	}
2681	else
2682	AssertRelease(!PdeDst.n.u1Present);
2683
2684	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2685	if (VBOX_FAILURE(rc))
2686	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2687	return rc;
2688
2689	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2690	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2691	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2692
2693	int rc = VINF_SUCCESS;
2694
2695	/*
2696	* Validate input a little bit.
2697	*/
2698	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2699	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2700	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2701	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2702	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT; /* no mask; flat index into the 2048 entry array. */
2703	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2704	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2705	const unsigned iPdpte = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2706	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2707	PX86PDPAE pPDDst;
2708	PX86PDPT pPdptDst;
2709	rc = PGMShwGetLongModePDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2710	AssertRCSuccessReturn(rc, rc);
2711	Assert(pPDDst);
2712
2713	/* Fetch the pgm pool shadow descriptor. */
2714	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & X86_PDPE_PG_MASK);
2715	Assert(pShwPde);
2716	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2717	const unsigned iPdpte = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2718	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2719	PEPTPD pPDDst;
2720	PEPTPDPT pPdptDst;
2721
2722	rc = PGMShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2723	if (rc != VINF_SUCCESS)
2724	{
2725	AssertRC(rc);
2726	return rc;
2727	}
2728	Assert(pPDDst);
2729
2730	/* Fetch the pgm pool shadow descriptor. */
2731	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpte].u & EPT_PDPTE_PG_MASK);
2732	Assert(pShwPde);
2733	# endif
2734	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2735	SHWPDE PdeDst = *pPdeDst;
2736
2737	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2738	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2739
2740	GSTPDE PdeSrc;
2741	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2742	PdeSrc.n.u1Present = 1;
2743	PdeSrc.n.u1Write = 1;
2744	PdeSrc.n.u1Accessed = 1;
2745	PdeSrc.n.u1User = 1;
2746
2747	/*
2748	* Allocate & map the page table.
2749	*/
2750	PSHWPT pPTDst;
2751	PPGMPOOLPAGE pShwPage;
2752	RTGCPHYS GCPhys;
2753
2754	/* Virtual address = physical address */
2755	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2756	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2757	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2758	# else
2759	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2760	# endif
2761
2762	if ( rc == VINF_SUCCESS
2763	\|\| rc == VINF_PGM_CACHED_PAGE)
2764	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2765	else
2766	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2767
2768	PdeDst.u &= X86_PDE_AVL_MASK;
2769	PdeDst.u \|= pShwPage->Core.Key;
2770	PdeDst.n.u1Present = 1;
2771	PdeDst.n.u1Write = 1;
2772	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2773	PdeDst.n.u1Execute = 1;
2774	# else
2775	PdeDst.n.u1User = 1;
2776	PdeDst.n.u1Accessed = 1;
2777	# endif
2778	*pPdeDst = PdeDst;
2779
2780	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2781	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2782	return rc;
2783
2784	#else
2785	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2786	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2787	return VERR_INTERNAL_ERROR;
2788	#endif
2789	}
2790
2791
2792
2793	/**
2794	* Prefetch a page/set of pages.
2795	*
2796	* Typically used to sync commonly used pages before entering raw mode
2797	* after a CR3 reload.
2798	*
2799	* @returns VBox status code.
2800	* @param pVM VM handle.
2801	* @param GCPtrPage Page to invalidate.
2802	*/
2803	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2804	{
2805	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2806	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2807	/*
2808	* Check that all Guest levels thru the PDE are present, getting the
2809	* PD and PDE in the processes.
2810	*/
2811	int rc = VINF_SUCCESS;
2812	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2813	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2814	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2815	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2816	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2817	unsigned iPDSrc;
2818	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2819	if (!pPDSrc)
2820	return VINF_SUCCESS; /* not present */
2821	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2822	unsigned iPDSrc;
2823	PX86PML4E pPml4eSrc;
2824	X86PDPE PdpeSrc;
2825	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2826	if (!pPDSrc)
2827	return VINF_SUCCESS; /* not present */
2828	# endif
2829	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2830	# else
2831	PGSTPD pPDSrc = NULL;
2832	const unsigned iPDSrc = 0;
2833	GSTPDE PdeSrc;
2834
2835	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2836	PdeSrc.n.u1Present = 1;
2837	PdeSrc.n.u1Write = 1;
2838	PdeSrc.n.u1Accessed = 1;
2839	PdeSrc.n.u1User = 1;
2840	# endif
2841
2842	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2843	{
2844	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2845	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2846	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2847	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2848	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2849	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2850	PX86PDPAE pPDDst;
2851	X86PDEPAE PdeDst;
2852
2853	# if PGM_GST_TYPE == PGM_TYPE_PROT
2854	/* AMD-V nested paging */
2855	X86PML4E Pml4eSrc;
2856	X86PDPE PdpeSrc;
2857	PX86PML4E pPml4eSrc = &Pml4eSrc;
2858
2859	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2860	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2861	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2862	# endif
2863
2864	int rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2865	if (rc != VINF_SUCCESS)
2866	{
2867	AssertRC(rc);
2868	return rc;
2869	}
2870	Assert(pPDDst);
2871	PdeDst = pPDDst->a[iPDDst];
2872	# endif
2873	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2874	{
2875	if (!PdeDst.n.u1Present)
2876	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2877	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2878	else
2879	{
2880	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2881	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2882	* makes no sense to prefetch more than one page.
2883	*/
2884	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2885	if (VBOX_SUCCESS(rc))
2886	rc = VINF_SUCCESS;
2887	}
2888	}
2889	}
2890	return rc;
2891	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2892	return VINF_SUCCESS; /* ignore */
2893	#endif
2894	}
2895
2896
2897
2898
2899	/**
2900	* Syncs a page during a PGMVerifyAccess() call.
2901	*
2902	* @returns VBox status code (informational included).
2903	* @param GCPtrPage The address of the page to sync.
2904	* @param fPage The effective guest page flags.
2905	* @param uErr The trap error code.
2906	*/
2907	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2908	{
2909	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2910
2911	Assert(!HWACCMIsNestedPagingActive(pVM));
2912	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2913	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2914
2915	# ifndef IN_RING0
2916	if (!(fPage & X86_PTE_US))
2917	{
2918	/*
2919	* Mark this page as safe.
2920	*/
2921	/** @todo not correct for pages that contain both code and data!! */
2922	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2923	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2924	}
2925	# endif
2926	/*
2927	* Get guest PD and index.
2928	*/
2929
2930	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2931	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2932	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2933	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2934	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2935	unsigned iPDSrc;
2936	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2937
2938	if (pPDSrc)
2939	{
2940	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2941	return VINF_EM_RAW_GUEST_TRAP;
2942	}
2943	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2944	unsigned iPDSrc;
2945	PX86PML4E pPml4eSrc;
2946	X86PDPE PdpeSrc;
2947	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2948	if (!pPDSrc)
2949	{
2950	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2951	return VINF_EM_RAW_GUEST_TRAP;
2952	}
2953	# endif
2954	# else
2955	PGSTPD pPDSrc = NULL;
2956	const unsigned iPDSrc = 0;
2957	# endif
2958	int rc = VINF_SUCCESS;
2959
2960	/*
2961	* First check if the shadow pd is present.
2962	*/
2963	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2964	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2965	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2966	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2967	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2968	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2969	PX86PDPAE pPDDst;
2970	PX86PDEPAE pPdeDst;
2971
2972	# if PGM_GST_TYPE == PGM_TYPE_PROT
2973	/* AMD-V nested paging */
2974	X86PML4E Pml4eSrc;
2975	X86PDPE PdpeSrc;
2976	PX86PML4E pPml4eSrc = &Pml4eSrc;
2977
2978	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2979	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2980	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2981	# endif
2982
2983	rc = PGMShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2984	if (rc != VINF_SUCCESS)
2985	{
2986	AssertRC(rc);
2987	return rc;
2988	}
2989	Assert(pPDDst);
2990	pPdeDst = &pPDDst->a[iPDDst];
2991	# endif
2992	if (!pPdeDst->n.u1Present)
2993	{
2994	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2995	AssertRC(rc);
2996	if (rc != VINF_SUCCESS)
2997	return rc;
2998	}
2999
3000	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3001	/* Check for dirty bit fault */
3002	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3003	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3004	Log(("PGMVerifyAccess: success (dirty)\n"));
3005	else
3006	{
3007	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3008	#else
3009	{
3010	GSTPDE PdeSrc;
3011	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3012	PdeSrc.n.u1Present = 1;
3013	PdeSrc.n.u1Write = 1;
3014	PdeSrc.n.u1Accessed = 1;
3015	PdeSrc.n.u1User = 1;
3016
3017	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3018	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3019	if (uErr & X86_TRAP_PF_US)
3020	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3021	else /* supervisor */
3022	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3023
3024	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3025	if (VBOX_SUCCESS(rc))
3026	{
3027	/* Page was successfully synced */
3028	Log2(("PGMVerifyAccess: success (sync)\n"));
3029	rc = VINF_SUCCESS;
3030	}
3031	else
3032	{
3033	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
3034	return VINF_EM_RAW_GUEST_TRAP;
3035	}
3036	}
3037	return rc;
3038
3039	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3040
3041	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3042	return VERR_INTERNAL_ERROR;
3043	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3044	}
3045
3046
3047	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3048	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3049	/**
3050	* Figures out which kind of shadow page this guest PDE warrants.
3051	*
3052	* @returns Shadow page kind.
3053	* @param pPdeSrc The guest PDE in question.
3054	* @param cr4 The current guest cr4 value.
3055	*/
3056	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3057	{
3058	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3059	if (!pPdeSrc->n.u1Size)
3060	# else
3061	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3062	# endif
3063	return BTH_PGMPOOLKIND_PT_FOR_PT;
3064	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3065	//{
3066	// case 0:
3067	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3068	// case X86_PDE4M_RW:
3069	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3070	// case X86_PDE4M_US:
3071	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3072	// case X86_PDE4M_RW \| X86_PDE4M_US:
3073	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3074	# if 0
3075	// case X86_PDE4M_PAE_NX:
3076	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3077	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3078	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3079	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3080	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3081	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3082	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3083	# endif
3084	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3085	//}
3086	}
3087	# endif
3088	#endif
3089
3090	#undef MY_STAM_COUNTER_INC
3091	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3092
3093
3094	/**
3095	* Syncs the paging hierarchy starting at CR3.
3096	*
3097	* @returns VBox status code, no specials.
3098	* @param pVM The virtual machine.
3099	* @param cr0 Guest context CR0 register
3100	* @param cr3 Guest context CR3 register
3101	* @param cr4 Guest context CR4 register
3102	* @param fGlobal Including global page directories or not
3103	*/
3104	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3105	{
3106	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3107	fGlobal = true; /* Change this CR3 reload to be a global one. */
3108
3109	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3110	/*
3111	* Update page access handlers.
3112	* The virtual are always flushed, while the physical are only on demand.
3113	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3114	* have to look into that later because it will have a bad influence on the performance.
3115	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3116	* bird: Yes, but that won't work for aliases.
3117	*/
3118	/** @todo this MUST go away. See #1557. */
3119	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3120	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3121	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3122	#endif
3123
3124	#ifdef PGMPOOL_WITH_MONITORING
3125	int rc = pgmPoolSyncCR3(pVM);
3126	if (rc != VINF_SUCCESS)
3127	return rc;
3128	#endif
3129
3130	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3131	/** @todo check if this is really necessary */
3132	HWACCMFlushTLB(pVM);
3133	return VINF_SUCCESS;
3134
3135	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3136	/* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
3137	return VINF_SUCCESS;
3138	#else
3139
3140	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3141	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3142
3143	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3144	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3145	bool fBigPagesSupported = true;
3146	# else
3147	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3148	# endif
3149
3150	/*
3151	* Get page directory addresses.
3152	*/
3153	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3154	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3155	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3156	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3157	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3158	# endif
3159	# endif
3160
3161	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3162	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
3163	Assert(pPDSrc);
3164	# ifndef IN_GC
3165	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3166	# endif
3167	# endif
3168
3169	/*
3170	* Iterate the page directory.
3171	*/
3172	PPGMMAPPING pMapping;
3173	unsigned iPdNoMapping;
3174	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3175	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3176
3177	/* Only check mappings if they are supposed to be put into the shadow page table. */
3178	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3179	{
3180	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3181	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3182	}
3183	else
3184	{
3185	pMapping = 0;
3186	iPdNoMapping = ~0U;
3187	}
3188	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3189	for (uint64_t iPml4e = 0; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3190	{
3191	PPGMPOOLPAGE pShwPdpt = NULL;
3192	PX86PML4E pPml4eSrc, pPml4eDst;
3193	RTGCPHYS GCPhysPdptSrc;
3194
3195	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3196	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3197
3198	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3199	if (!pPml4eDst->n.u1Present)
3200	continue;
3201	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3202
3203	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3204
3205	/* Anything significant changed? */
3206	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3207	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3208	{
3209	/* Free it. */
3210	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3211	(uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3212	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4e);
3213	pPml4eDst->u = 0;
3214	continue;
3215	}
3216	/* Force an attribute sync. */
3217	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3218	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3219	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3220
3221	# else
3222	{
3223	# endif
3224	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3225	for (uint64_t iPdpte = 0; iPdpte < GST_PDPE_ENTRIES; iPdpte++)
3226	{
3227	unsigned iPDSrc;
3228	# if PGM_GST_TYPE == PGM_TYPE_PAE
3229	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3230	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpte * X86_PG_PAE_ENTRIES];
3231	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpte << X86_PDPT_SHIFT, &iPDSrc);
3232	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT); NOREF(pPdptDst);
3233	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3234
3235	if (pPDSrc == NULL)
3236	{
3237	/* PDPE not present */
3238	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present)
3239	{
3240	LogFlow(("SyncCR3: guest PDPE %d not present; clear shw pdpe\n", iPdpte));
3241	/* for each page directory entry */
3242	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3243	{
3244	if ( pPDEDst[iPD].n.u1Present
3245	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3246	{
3247	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpte * X86_PG_PAE_ENTRIES + iPD);
3248	pPDEDst[iPD].u = 0;
3249	}
3250	}
3251	}
3252	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].u & PGM_PLXFLAGS_MAPPING))
3253	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPdpte].n.u1Present = 0;
3254	continue;
3255	}
3256	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3257	PPGMPOOLPAGE pShwPde = NULL;
3258	RTGCPHYS GCPhysPdeSrc;
3259	PX86PDPE pPdpeDst;
3260	PX86PML4E pPml4eSrc;
3261	X86PDPE PdpeSrc;
3262	PX86PDPT pPdptDst;
3263	PX86PDPAE pPDDst;
3264	PX86PDEPAE pPDEDst;
3265	RTGCUINTPTR GCPtr = (iPml4e << X86_PML4_SHIFT) \|\| (iPdpte << X86_PDPT_SHIFT);
3266	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3267
3268	int rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3269	if (rc != VINF_SUCCESS)
3270	{
3271	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3272	break; /* next PML4E */
3273
3274	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3275	continue; /* next PDPTE */
3276	}
3277	Assert(pPDDst);
3278	pPDEDst = &pPDDst->a[0];
3279	Assert(iPDSrc == 0);
3280
3281	pPdpeDst = &pPdptDst->a[iPdpte];
3282
3283	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3284	if (!pPdpeDst->n.u1Present)
3285	continue; /* next PDPTE */
3286
3287	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3288	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3289
3290	/* Anything significant changed? */
3291	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3292	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3293	{
3294	/* Free it. */
3295	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3296	((uint64_t)iPml4e << X86_PML4_SHIFT) + ((uint64_t)iPdpte << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3297
3298	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3299	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3300	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpte);
3301	pPdpeDst->u = 0;
3302	continue; /* next guest PDPTE */
3303	}
3304	/* Force an attribute sync. */
3305	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3306	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3307	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3308	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3309
3310	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3311	{
3312	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3313	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3314	{
3315	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3316	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3317	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3318	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3319	# endif
3320	GSTPDE PdeSrc = pPDSrc->a[iPD];
3321	if ( PdeSrc.n.u1Present
3322	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3323	{
3324	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3325	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3326	&& !defined(PGM_WITHOUT_MAPPINGS)
3327
3328	/*
3329	* Check for conflicts with GC mappings.
3330	*/
3331	# if PGM_GST_TYPE == PGM_TYPE_PAE
3332	if (iPD + iPdpte * X86_PG_PAE_ENTRIES == iPdNoMapping)
3333	# else
3334	if (iPD == iPdNoMapping)
3335	# endif
3336	{
3337	if (pVM->pgm.s.fMappingsFixed)
3338	{
3339	/* It's fixed, just skip the mapping. */
3340	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3341	iPD += cPTs - 1;
3342	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3343	pMapping = pMapping->CTX_SUFF(pNext);
3344	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3345	continue;
3346	}
3347	# ifdef IN_RING3
3348	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3349	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3350	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3351	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3352	# endif
3353	if (VBOX_FAILURE(rc))
3354	return rc;
3355
3356	/*
3357	* Update iPdNoMapping and pMapping.
3358	*/
3359	pMapping = pVM->pgm.s.pMappingsR3;
3360	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3361	pMapping = pMapping->pNextR3;
3362	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3363	# else
3364	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3365	return VINF_PGM_SYNC_CR3;
3366	# endif
3367	}
3368	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3369	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3370	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3371	/*
3372	* Sync page directory entry.
3373	*
3374	* The current approach is to allocated the page table but to set
3375	* the entry to not-present and postpone the page table synching till
3376	* it's actually used.
3377	*/
3378	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3379	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3380	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3381	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3382	# else
3383	const unsigned iPdShw = iPD; NOREF(iPdShw);
3384	# endif
3385	{
3386	SHWPDE PdeDst = *pPDEDst;
3387	if (PdeDst.n.u1Present)
3388	{
3389	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3390	RTGCPHYS GCPhys;
3391	if ( !PdeSrc.b.u1Size
3392	\|\| !fBigPagesSupported)
3393	{
3394	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3395	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3396	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3397	GCPhys \|= i * (PAGE_SIZE / 2);
3398	# endif
3399	}
3400	else
3401	{
3402	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3403	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3404	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3405	GCPhys \|= i * X86_PAGE_2M_SIZE;
3406	# endif
3407	}
3408
3409	if ( pShwPage->GCPhys == GCPhys
3410	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3411	&& ( pShwPage->fCached
3412	\|\| ( !fGlobal
3413	&& ( false
3414	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3415	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3416	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3417	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3418	# else
3419	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3420	# endif
3421	\|\| ( !pShwPage->fSeenNonGlobal
3422	&& (cr4 & X86_CR4_PGE))
3423	# endif
3424	)
3425	)
3426	)
3427	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3428	\|\| ( fBigPagesSupported
3429	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3430	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3431	)
3432	)
3433	{
3434	# ifdef VBOX_WITH_STATISTICS
3435	if ( !fGlobal
3436	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3437	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3438	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3439	# else
3440	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3441	# endif
3442	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3443	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3444	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3445	else
3446	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3447	# endif /* VBOX_WITH_STATISTICS */
3448	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3449	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3450	//# ifdef PGMPOOL_WITH_CACHE
3451	// pgmPoolCacheUsed(pPool, pShwPage);
3452	//# endif
3453	}
3454	else
3455	{
3456	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3457	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3458	# else
3459	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3460	# endif
3461	pPDEDst->u = 0;
3462	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3463	}
3464	}
3465	else
3466	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3467	pPDEDst++;
3468	}
3469	}
3470	# if PGM_GST_TYPE == PGM_TYPE_PAE
3471	else if (iPD + iPdpte * X86_PG_PAE_ENTRIES != iPdNoMapping)
3472	# else
3473	else if (iPD != iPdNoMapping)
3474	# endif
3475	{
3476	/*
3477	* Check if there is any page directory to mark not present here.
3478	*/
3479	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3480	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3481	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3482	const unsigned iPdShw = iPD + iPdpte * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3483	# else
3484	const unsigned iPdShw = iPD; NOREF(iPdShw);
3485	# endif
3486	{
3487	if (pPDEDst->n.u1Present)
3488	{
3489	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3490	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3491	# else
3492	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3493	# endif
3494	pPDEDst->u = 0;
3495	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3496	}
3497	pPDEDst++;
3498	}
3499	}
3500	else
3501	{
3502	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3503	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3504	&& !defined(PGM_WITHOUT_MAPPINGS)
3505
3506	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3507
3508	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3509	if (pVM->pgm.s.fMappingsFixed)
3510	{
3511	/* It's fixed, just skip the mapping. */
3512	pMapping = pMapping->CTX_SUFF(pNext);
3513	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3514	}
3515	else
3516	{
3517	/*
3518	* Check for conflicts for subsequent pagetables
3519	* and advance to the next mapping.
3520	*/
3521	iPdNoMapping = ~0U;
3522	unsigned iPT = cPTs;
3523	while (iPT-- > 1)
3524	{
3525	if ( pPDSrc->a[iPD + iPT].n.u1Present
3526	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3527	{
3528	# ifdef IN_RING3
3529	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3530	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3531	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3532	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpte << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3533	# endif
3534	if (VBOX_FAILURE(rc))
3535	return rc;
3536
3537	/*
3538	* Update iPdNoMapping and pMapping.
3539	*/
3540	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3541	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3542	pMapping = pMapping->CTX_SUFF(pNext);
3543	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3544	break;
3545	# else
3546	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3547	return VINF_PGM_SYNC_CR3;
3548	# endif
3549	}
3550	}
3551	if (iPdNoMapping == ~0U && pMapping)
3552	{
3553	pMapping = pMapping->CTX_SUFF(pNext);
3554	if (pMapping)
3555	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3556	}
3557	}
3558
3559	/* advance. */
3560	iPD += cPTs - 1;
3561	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3562	# if PGM_GST_TYPE != PGM_SHW_TYPE
3563	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3564	# endif
3565	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3566	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3567	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3568	}
3569
3570	} /* for iPD */
3571	} /* for each PDPTE (PAE) */
3572	} /* for each page map level 4 entry (amd64) */
3573	return VINF_SUCCESS;
3574
3575	# else /* guest real and protected mode */
3576	return VINF_SUCCESS;
3577	# endif
3578	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
3579	}
3580
3581
3582
3583
3584	#ifdef VBOX_STRICT
3585	#ifdef IN_GC
3586	# undef AssertMsgFailed
3587	# define AssertMsgFailed Log
3588	#endif
3589	#ifdef IN_RING3
3590	# include <VBox/dbgf.h>
3591
3592	/**
3593	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3594	*
3595	* @returns VBox status code (VINF_SUCCESS).
3596	* @param pVM The VM handle.
3597	* @param cr3 The root of the hierarchy.
3598	* @param crr The cr4, only PAE and PSE is currently used.
3599	* @param fLongMode Set if long mode, false if not long mode.
3600	* @param cMaxDepth Number of levels to dump.
3601	* @param pHlp Pointer to the output functions.
3602	*/
3603	__BEGIN_DECLS
3604	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3605	__END_DECLS
3606
3607	#endif
3608
3609	/**
3610	* Checks that the shadow page table is in sync with the guest one.
3611	*
3612	* @returns The number of errors.
3613	* @param pVM The virtual machine.
3614	* @param cr3 Guest context CR3 register
3615	* @param cr4 Guest context CR4 register
3616	* @param GCPtr Where to start. Defaults to 0.
3617	* @param cb How much to check. Defaults to everything.
3618	*/
3619	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3620	{
3621	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3622	return 0;
3623	#else
3624	unsigned cErrors = 0;
3625
3626	#if PGM_GST_TYPE == PGM_TYPE_PAE
3627	/* @todo currently broken; crashes below somewhere */
3628	AssertFailed();
3629	#endif
3630
3631	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3632	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3633	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3634
3635	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3636	bool fBigPagesSupported = true;
3637	# else
3638	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3639	# endif
3640	PPGM pPGM = &pVM->pgm.s;
3641	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3642	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3643	# ifndef IN_RING0
3644	RTHCPHYS HCPhys; /* general usage. */
3645	# endif
3646	int rc;
3647
3648	/*
3649	* Check that the Guest CR3 and all its mappings are correct.
3650	*/
3651	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3652	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3653	false);
3654	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3655	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3656	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDGC, NULL, &HCPhysShw);
3657	# else
3658	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3659	# endif
3660	AssertRCReturn(rc, 1);
3661	HCPhys = NIL_RTHCPHYS;
3662	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3663	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3664	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3665	RTGCPHYS GCPhys;
3666	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3667	AssertRCReturn(rc, 1);
3668	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3669	# endif
3670	#endif /* !IN_RING0 */
3671
3672	/*
3673	* Get and check the Shadow CR3.
3674	*/
3675	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3676	unsigned cPDEs = X86_PG_ENTRIES;
3677	unsigned ulIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3678	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3679	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3680	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3681	# else
3682	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3683	# endif
3684	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3685	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3686	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3687	unsigned ulIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3688	# endif
3689	if (cb != ~(RTGCUINTPTR)0)
3690	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3691
3692	/** @todo call the other two PGMAssert() functions. /
3693
3694	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3695	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3696	# endif
3697
3698	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3699	unsigned iPml4e = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3700
3701	for (; iPml4e < X86_PG_PAE_ENTRIES; iPml4e++)
3702	{
3703	PPGMPOOLPAGE pShwPdpt = NULL;
3704	PX86PML4E pPml4eSrc, pPml4eDst;
3705	RTGCPHYS GCPhysPdptSrc;
3706
3707	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4e];
3708	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4e];
3709
3710	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3711	if (!pPml4eDst->n.u1Present)
3712	{
3713	GCPtr += UINT64_C(_2M * 512 * 512);
3714	continue;
3715	}
3716
3717	# if PGM_GST_TYPE == PGM_TYPE_PAE
3718	/* not correct to call pgmPoolGetPage */
3719	AssertFailed();
3720	# endif
3721	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3722	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3723
3724	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3725	{
3726	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3727	GCPtr += UINT64_C(_2M * 512 * 512);
3728	cErrors++;
3729	continue;
3730	}
3731
3732	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3733	{
3734	AssertMsgFailed(("Physical address doesn't match! iPml4e %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3735	GCPtr += UINT64_C(_2M * 512 * 512);
3736	cErrors++;
3737	continue;
3738	}
3739
3740	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3741	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3742	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3743	{
3744	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3745	GCPtr += UINT64_C(_2M * 512 * 512);
3746	cErrors++;
3747	continue;
3748	}
3749	# else
3750	{
3751	# endif
3752
3753	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3754	/*
3755	* Check the PDPTEs too.
3756	*/
3757	unsigned iPdpte = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3758
3759	for (;iPdpte <= SHW_PDPT_MASK; iPdpte++)
3760	{
3761	unsigned iPDSrc;
3762	PPGMPOOLPAGE pShwPde = NULL;
3763	PX86PDPE pPdpeDst;
3764	RTGCPHYS GCPhysPdeSrc;
3765	# if PGM_GST_TYPE == PGM_TYPE_PAE
3766	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3767	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc);
3768	PX86PDPT pPdptDst = pVM->pgm.s.CTXMID(p,PaePDPT);
3769	X86PDPE PdpeSrc = CTXSUFF(pVM->pgm.s.pGstPaePDPT)->a[iPdpte];
3770	# else
3771	PX86PML4E pPml4eSrc;
3772	X86PDPE PdpeSrc;
3773	PX86PDPT pPdptDst;
3774	PX86PDPAE pPDDst;
3775	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3776
3777	rc = PGMShwGetLongModePDPtr(pVM, GCPtr, &pPdptDst, &pPDDst);
3778	if (rc != VINF_SUCCESS)
3779	{
3780	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Vrc\n", rc));
3781	GCPtr += 512 * _2M;
3782	continue; /* next PDPTE */
3783	}
3784	Assert(pPDDst);
3785	# endif
3786	Assert(iPDSrc == 0);
3787
3788	pPdpeDst = &pPdptDst->a[iPdpte];
3789
3790	if (!pPdpeDst->n.u1Present)
3791	{
3792	GCPtr += 512 * _2M;
3793	continue; /* next PDPTE */
3794	}
3795
3796	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3797	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3798
3799	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3800	{
3801	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3802	GCPtr += 512 * _2M;
3803	cErrors++;
3804	continue;
3805	}
3806
3807	if (GCPhysPdeSrc != pShwPde->GCPhys)
3808	{
3809	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3810	AssertMsgFailed(("Physical address doesn't match! iPml4e %d iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4e, iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3811	# else
3812	AssertMsgFailed(("Physical address doesn't match! iPdpte %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpte, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3813	# endif
3814	GCPtr += 512 * _2M;
3815	cErrors++;
3816	continue;
3817	}
3818
3819	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3820	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3821	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3822	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3823	{
3824	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3825	GCPtr += 512 * _2M;
3826	cErrors++;
3827	continue;
3828	}
3829	# endif
3830
3831	# else
3832	{
3833	# endif
3834	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3835	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3836	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3837	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3838	# else
3839	const PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3840	# endif
3841	# endif
3842	/*
3843	* Iterate the shadow page directory.
3844	*/
3845	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3846	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3847
3848	for (;
3849	iPDDst < cPDEs;
3850	iPDDst++, GCPtr += ulIncrement)
3851	{
3852	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3853	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3854	{
3855	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3856	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3857	{
3858	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3859	cErrors++;
3860	continue;
3861	}
3862	}
3863	else if ( (PdeDst.u & X86_PDE_P)
3864	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3865	)
3866	{
3867	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3868	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3869	if (!pPoolPage)
3870	{
3871	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3872	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3873	cErrors++;
3874	continue;
3875	}
3876	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3877
3878	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3879	{
3880	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3881	GCPtr, (uint64_t)PdeDst.u));
3882	cErrors++;
3883	}
3884
3885	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3886	{
3887	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3888	GCPtr, (uint64_t)PdeDst.u));
3889	cErrors++;
3890	}
3891
3892	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3893	if (!PdeSrc.n.u1Present)
3894	{
3895	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3896	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3897	cErrors++;
3898	continue;
3899	}
3900
3901	if ( !PdeSrc.b.u1Size
3902	\|\| !fBigPagesSupported)
3903	{
3904	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3905	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3906	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3907	# endif
3908	}
3909	else
3910	{
3911	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3912	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3913	{
3914	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3915	GCPtr, (uint64_t)PdeSrc.u));
3916	cErrors++;
3917	continue;
3918	}
3919	# endif
3920	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3921	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3922	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3923	# endif
3924	}
3925
3926	if ( pPoolPage->enmKind
3927	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3928	{
3929	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3930	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3931	cErrors++;
3932	}
3933
3934	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3935	if (!pPhysPage)
3936	{
3937	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3938	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3939	cErrors++;
3940	continue;
3941	}
3942
3943	if (GCPhysGst != pPoolPage->GCPhys)
3944	{
3945	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3946	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3947	cErrors++;
3948	continue;
3949	}
3950
3951	if ( !PdeSrc.b.u1Size
3952	\|\| !fBigPagesSupported)
3953	{
3954	/*
3955	* Page Table.
3956	*/
3957	const GSTPT *pPTSrc;
3958	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3959	if (VBOX_FAILURE(rc))
3960	{
3961	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3962	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3963	cErrors++;
3964	continue;
3965	}
3966	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3967	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3968	{
3969	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3970	// (This problem will go away when/if we shadow multiple CR3s.)
3971	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3972	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3973	cErrors++;
3974	continue;
3975	}
3976	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3977	{
3978	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3979	GCPtr, (uint64_t)PdeDst.u));
3980	cErrors++;
3981	continue;
3982	}
3983
3984	/* iterate the page table. */
3985	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3986	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3987	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3988	# else
3989	const unsigned offPTSrc = 0;
3990	# endif
3991	for (unsigned iPT = 0, off = 0;
3992	iPT < RT_ELEMENTS(pPTDst->a);
3993	iPT++, off += PAGE_SIZE)
3994	{
3995	const SHWPTE PteDst = pPTDst->a[iPT];
3996
3997	/* skip not-present entries. */
3998	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3999	continue;
4000	Assert(PteDst.n.u1Present);
4001
4002	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4003	if (!PteSrc.n.u1Present)
4004	{
4005	# ifdef IN_RING3
4006	PGMAssertHandlerAndFlagsInSync(pVM);
4007	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4008	# endif
4009	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
4010	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4011	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4012	cErrors++;
4013	continue;
4014	}
4015
4016	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4017	# if 1 /** @todo sync accessed bit properly... */
4018	fIgnoreFlags \|= X86_PTE_A;
4019	# endif
4020
4021	/* match the physical addresses */
4022	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4023	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4024
4025	# ifdef IN_RING3
4026	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4027	if (VBOX_FAILURE(rc))
4028	{
4029	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4030	{
4031	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4032	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4033	cErrors++;
4034	continue;
4035	}
4036	}
4037	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4038	{
4039	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4040	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4041	cErrors++;
4042	continue;
4043	}
4044	# endif
4045
4046	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4047	if (!pPhysPage)
4048	{
4049	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4050	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4051	{
4052	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4053	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4054	cErrors++;
4055	continue;
4056	}
4057	# endif
4058	if (PteDst.n.u1Write)
4059	{
4060	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4061	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4062	cErrors++;
4063	}
4064	fIgnoreFlags \|= X86_PTE_RW;
4065	}
4066	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4067	{
4068	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
4069	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4070	cErrors++;
4071	continue;
4072	}
4073
4074	/* flags */
4075	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4076	{
4077	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4078	{
4079	if (PteDst.n.u1Write)
4080	{
4081	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
4082	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4083	cErrors++;
4084	continue;
4085	}
4086	fIgnoreFlags \|= X86_PTE_RW;
4087	}
4088	else
4089	{
4090	if (PteDst.n.u1Present)
4091	{
4092	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
4093	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4094	cErrors++;
4095	continue;
4096	}
4097	fIgnoreFlags \|= X86_PTE_P;
4098	}
4099	}
4100	else
4101	{
4102	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4103	{
4104	if (PteDst.n.u1Write)
4105	{
4106	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4107	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4108	cErrors++;
4109	continue;
4110	}
4111	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4112	{
4113	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4114	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4115	cErrors++;
4116	continue;
4117	}
4118	if (PteDst.n.u1Dirty)
4119	{
4120	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4121	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4122	cErrors++;
4123	}
4124	# if 0 /** @todo sync access bit properly... */
4125	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4126	{
4127	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4128	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4129	cErrors++;
4130	}
4131	fIgnoreFlags \|= X86_PTE_RW;
4132	# else
4133	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4134	# endif
4135	}
4136	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4137	{
4138	/* access bit emulation (not implemented). */
4139	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4140	{
4141	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4142	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4143	cErrors++;
4144	continue;
4145	}
4146	if (!PteDst.n.u1Accessed)
4147	{
4148	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4149	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4150	cErrors++;
4151	}
4152	fIgnoreFlags \|= X86_PTE_P;
4153	}
4154	# ifdef DEBUG_sandervl
4155	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4156	# endif
4157	}
4158
4159	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4160	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4161	)
4162	{
4163	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4164	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4165	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4166	cErrors++;
4167	continue;
4168	}
4169	} /* foreach PTE */
4170	}
4171	else
4172	{
4173	/*
4174	* Big Page.
4175	*/
4176	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4177	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4178	{
4179	if (PdeDst.n.u1Write)
4180	{
4181	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4182	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4183	cErrors++;
4184	continue;
4185	}
4186	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4187	{
4188	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4189	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4190	cErrors++;
4191	continue;
4192	}
4193	# if 0 /** @todo sync access bit properly... */
4194	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4195	{
4196	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4197	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4198	cErrors++;
4199	}
4200	fIgnoreFlags \|= X86_PTE_RW;
4201	# else
4202	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4203	# endif
4204	}
4205	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4206	{
4207	/* access bit emulation (not implemented). */
4208	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4209	{
4210	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4211	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4212	cErrors++;
4213	continue;
4214	}
4215	if (!PdeDst.n.u1Accessed)
4216	{
4217	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4218	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4219	cErrors++;
4220	}
4221	fIgnoreFlags \|= X86_PTE_P;
4222	}
4223
4224	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4225	{
4226	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4227	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4228	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4229	cErrors++;
4230	}
4231
4232	/* iterate the page table. */
4233	for (unsigned iPT = 0, off = 0;
4234	iPT < RT_ELEMENTS(pPTDst->a);
4235	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4236	{
4237	const SHWPTE PteDst = pPTDst->a[iPT];
4238
4239	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4240	{
4241	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4242	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4243	cErrors++;
4244	}
4245
4246	/* skip not-present entries. */
4247	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4248	continue;
4249
4250	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4251
4252	/* match the physical addresses */
4253	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4254
4255	# ifdef IN_RING3
4256	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4257	if (VBOX_FAILURE(rc))
4258	{
4259	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4260	{
4261	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4262	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4263	cErrors++;
4264	}
4265	}
4266	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4267	{
4268	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4269	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4270	cErrors++;
4271	continue;
4272	}
4273	# endif
4274	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4275	if (!pPhysPage)
4276	{
4277	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4278	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4279	{
4280	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4281	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4282	cErrors++;
4283	continue;
4284	}
4285	# endif
4286	if (PteDst.n.u1Write)
4287	{
4288	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4289	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4290	cErrors++;
4291	}
4292	fIgnoreFlags \|= X86_PTE_RW;
4293	}
4294	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4295	{
4296	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4297	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4298	cErrors++;
4299	continue;
4300	}
4301
4302	/* flags */
4303	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4304	{
4305	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4306	{
4307	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4308	{
4309	if (PteDst.n.u1Write)
4310	{
4311	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4312	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4313	cErrors++;
4314	continue;
4315	}
4316	fIgnoreFlags \|= X86_PTE_RW;
4317	}
4318	}
4319	else
4320	{
4321	if (PteDst.n.u1Present)
4322	{
4323	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
4324	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4325	cErrors++;
4326	continue;
4327	}
4328	fIgnoreFlags \|= X86_PTE_P;
4329	}
4330	}
4331
4332	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4333	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4334	)
4335	{
4336	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4337	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4338	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4339	cErrors++;
4340	continue;
4341	}
4342	} /* for each PTE */
4343	}
4344	}
4345	/* not present */
4346
4347	} /* for each PDE */
4348
4349	} /* for each PDPTE */
4350
4351	} /* for each PML4E */
4352
4353	# ifdef DEBUG
4354	if (cErrors)
4355	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4356	# endif
4357
4358	#endif
4359	return cErrors;
4360
4361	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4362	}
4363	#endif /* VBOX_STRICT */
4364

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 13188

Download in other formats: