PGMAllBth.h@ 14094

Last change on this file since 14094 was 14094, checked in by vboxsync, 16 years ago
#1865: shadow pae, the second bit.
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File size: 192.9 KB

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1	/* $Id: PGMAllBth.h 14094 2008-11-11 16:47:38Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
148	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
149
150	# if PGM_GST_TYPE == PGM_TYPE_PAE
151	/* Did we mark the PDPT as not present in SyncCR3? */
152	unsigned iPdpt = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
153	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
154	if (!pPdptDst->a[iPdpt].n.u1Present)
155	pPdptDst->a[iPdpt].n.u1Present = 1;
156	# endif /* GST PAE */
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
159	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
160	PX86PDPAE pPDDst;
161	# if PGM_GST_TYPE == PGM_TYPE_PROT
162	/* AMD-V nested paging */
163	X86PML4E Pml4eSrc;
164	X86PDPE PdpeSrc;
165	PX86PML4E pPml4eSrc = &Pml4eSrc;
166
167	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
168	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
169	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
170	# endif
171
172	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
173	if (rc != VINF_SUCCESS)
174	{
175	AssertRC(rc);
176	return rc;
177	}
178	Assert(pPDDst);
179
180	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
181	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
182	PEPTPD pPDDst;
183
184	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
185	if (rc != VINF_SUCCESS)
186	{
187	AssertRC(rc);
188	return rc;
189	}
190	Assert(pPDDst);
191	# endif
192
193	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
194	/*
195	* If we successfully correct the write protection fault due to dirty bit
196	* tracking, or this page fault is a genuine one, then return immediately.
197	*/
198	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
199	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
200	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
201	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
202	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
203	{
204	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
205	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
206	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
207	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
208	}
209
210	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
211	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
212
213	/*
214	* A common case is the not-present error caused by lazy page table syncing.
215	*
216	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
217	* so we can safely assume that the shadow PT is present when calling SyncPage later.
218	*
219	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
220	* of mapping conflict and defer to SyncCR3 in R3.
221	* (Again, we do NOT support access handlers for non-present guest pages.)
222	*
223	*/
224	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
225	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
226	# else
227	GSTPDE PdeSrc;
228	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
229	PdeSrc.n.u1Present = 1;
230	PdeSrc.n.u1Write = 1;
231	PdeSrc.n.u1Accessed = 1;
232	PdeSrc.n.u1User = 1;
233	# endif
234	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
235	&& !pPDDst->a[iPDDst].n.u1Present
236	&& PdeSrc.n.u1Present
237	)
238
239	{
240	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
241	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
242	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
243	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
244	if (RT_SUCCESS(rc))
245	{
246	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
247	return rc;
248	}
249	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
250	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
251	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
252	return VINF_PGM_SYNC_CR3;
253	}
254
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	/*
257	* Check if this address is within any of our mappings.
258	*
259	* This is very fast and it's gonna save us a bit of effort below and prevent
260	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
261	* (BTW, it's impossible to have physical access handlers in a mapping.)
262	*/
263	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
264	{
265	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
266	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
267	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
268	{
269	if (pvFault < pMapping->GCPtr)
270	break;
271	if (pvFault - pMapping->GCPtr < pMapping->cb)
272	{
273	/*
274	* The first thing we check is if we've got an undetected conflict.
275	*/
276	if (!pVM->pgm.s.fMappingsFixed)
277	{
278	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
279	while (iPT-- > 0)
280	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
281	{
282	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
283	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
284	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
286	return VINF_PGM_SYNC_CR3;
287	}
288	}
289
290	/*
291	* Check if the fault address is in a virtual page access handler range.
292	*/
293	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
294	if ( pCur
295	&& pvFault - pCur->Core.Key < pCur->cb
296	&& uErr & X86_TRAP_PF_RW)
297	{
298	# ifdef IN_RC
299	STAM_PROFILE_START(&pCur->Stat, h);
300	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
301	STAM_PROFILE_STOP(&pCur->Stat, h);
302	# else
303	AssertFailed();
304	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
305	# endif
306	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
307	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
308	return rc;
309	}
310
311	/*
312	* Pretend we're not here and let the guest handle the trap.
313	*/
314	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
315	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
316	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
317	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
318	return VINF_EM_RAW_GUEST_TRAP;
319	}
320	}
321	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
322	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
323	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
324
325	/*
326	* Check if this fault address is flagged for special treatment,
327	* which means we'll have to figure out the physical address and
328	* check flags associated with it.
329	*
330	* ASSUME that we can limit any special access handling to pages
331	* in page tables which the guest believes to be present.
332	*/
333	if (PdeSrc.n.u1Present)
334	{
335	RTGCPHYS GCPhys = NIL_RTGCPHYS;
336
337	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
338	# if PGM_GST_TYPE == PGM_TYPE_AMD64
339	bool fBigPagesSupported = true;
340	# else
341	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
342	# endif
343	if ( PdeSrc.b.u1Size
344	&& fBigPagesSupported)
345	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
346	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
347	else
348	{
349	PGSTPT pPTSrc;
350	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
351	if (RT_SUCCESS(rc))
352	{
353	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
354	if (pPTSrc->a[iPTESrc].n.u1Present)
355	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
356	}
357	}
358	# else
359	/* No paging so the fault address is the physical address */
360	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
361	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
362
363	/*
364	* If we have a GC address we'll check if it has any flags set.
365	*/
366	if (GCPhys != NIL_RTGCPHYS)
367	{
368	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
369
370	PPGMPAGE pPage;
371	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
372	if (RT_SUCCESS(rc))
373	{
374	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
375	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
376	{
377	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
378	{
379	/*
380	* Physical page access handler.
381	*/
382	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
383	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
384	if (pCur)
385	{
386	# ifdef PGM_SYNC_N_PAGES
387	/*
388	* If the region is write protected and we got a page not present fault, then sync
389	* the pages. If the fault was caused by a read, then restart the instruction.
390	* In case of write access continue to the GC write handler.
391	*
392	* ASSUMES that there is only one handler per page or that they have similar write properties.
393	*/
394	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
395	&& !(uErr & X86_TRAP_PF_P))
396	{
397	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
398	if ( RT_FAILURE(rc)
399	\|\| !(uErr & X86_TRAP_PF_RW)
400	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
401	{
402	AssertRC(rc);
403	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
404	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
405	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
406	return rc;
407	}
408	}
409	# endif
410
411	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
412	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
413	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
414
415	# if defined(IN_RC) \|\| defined(IN_RING0)
416	if (pCur->CTX_SUFF(pfnHandler))
417	{
418	STAM_PROFILE_START(&pCur->Stat, h);
419	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
420	STAM_PROFILE_STOP(&pCur->Stat, h);
421	}
422	else
423	# endif
424	rc = VINF_EM_RAW_EMULATE_INSTR;
425	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
426	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
427	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
428	return rc;
429	}
430	}
431	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
432	else
433	{
434	# ifdef PGM_SYNC_N_PAGES
435	/*
436	* If the region is write protected and we got a page not present fault, then sync
437	* the pages. If the fault was caused by a read, then restart the instruction.
438	* In case of write access continue to the GC write handler.
439	*/
440	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
441	&& !(uErr & X86_TRAP_PF_P))
442	{
443	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
444	if ( RT_FAILURE(rc)
445	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
446	\|\| !(uErr & X86_TRAP_PF_RW))
447	{
448	AssertRC(rc);
449	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
450	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
451	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
452	return rc;
453	}
454	}
455	# endif
456	/*
457	* Ok, it's an virtual page access handler.
458	*
459	* Since it's faster to search by address, we'll do that first
460	* and then retry by GCPhys if that fails.
461	*/
462	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
463	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
464	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
465	*/
466	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
467	if (pCur)
468	{
469	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
470	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
471	\|\| !(uErr & X86_TRAP_PF_P)
472	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
473	("Unexpected trap for virtual handler: %RGv (phys=%RGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
474
475	if ( pvFault - pCur->Core.Key < pCur->cb
476	&& ( uErr & X86_TRAP_PF_RW
477	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
478	{
479	# ifdef IN_RC
480	STAM_PROFILE_START(&pCur->Stat, h);
481	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
482	STAM_PROFILE_STOP(&pCur->Stat, h);
483	# else
484	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
485	# endif
486	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
487	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
488	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
489	return rc;
490	}
491	/* Unhandled part of a monitored page */
492	}
493	else
494	{
495	/* Check by physical address. */
496	PPGMVIRTHANDLER pCur;
497	unsigned iPage;
498	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
499	&pCur, &iPage);
500	Assert(RT_SUCCESS(rc) \|\| !pCur);
501	if ( pCur
502	&& ( uErr & X86_TRAP_PF_RW
503	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
504	{
505	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
506	# ifdef IN_RC
507	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
508	Assert(off < pCur->cb);
509	STAM_PROFILE_START(&pCur->Stat, h);
510	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
511	STAM_PROFILE_STOP(&pCur->Stat, h);
512	# else
513	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
514	# endif
515	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
517	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
518	return rc;
519	}
520	}
521	}
522	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
523
524	/*
525	* There is a handled area of the page, but this fault doesn't belong to it.
526	* We must emulate the instruction.
527	*
528	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
529	* we first check if this was a page-not-present fault for a page with only
530	* write access handlers. Restart the instruction if it wasn't a write access.
531	*/
532	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
533
534	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
535	&& !(uErr & X86_TRAP_PF_P))
536	{
537	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
538	if ( RT_FAILURE(rc)
539	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
540	\|\| !(uErr & X86_TRAP_PF_RW))
541	{
542	AssertRC(rc);
543	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
544	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
545	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
546	return rc;
547	}
548	}
549
550	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
551	* It's writing to an unhandled part of the LDT page several million times.
552	*/
553	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
554	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
555	rc, pPage->HCPhys,
556	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
557	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
558	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
559	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
560	return rc;
561	} /* if any kind of handler */
562
563	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
564	if (uErr & X86_TRAP_PF_P)
565	{
566	/*
567	* The page isn't marked, but it might still be monitored by a virtual page access handler.
568	* (ASSUMES no temporary disabling of virtual handlers.)
569	*/
570	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
571	* we should correct both the shadow page table and physical memory flags, and not only check for
572	* accesses within the handler region but for access to pages with virtual handlers. */
573	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
574	if (pCur)
575	{
576	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
577	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
578	\|\| !(uErr & X86_TRAP_PF_P)
579	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
580	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
581
582	if ( pvFault - pCur->Core.Key < pCur->cb
583	&& ( uErr & X86_TRAP_PF_RW
584	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
585	{
586	# ifdef IN_RC
587	STAM_PROFILE_START(&pCur->Stat, h);
588	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
589	STAM_PROFILE_STOP(&pCur->Stat, h);
590	# else
591	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
592	# endif
593	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
594	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
595	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
596	return rc;
597	}
598	}
599	}
600	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
601	}
602	else
603	{
604	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
605	* back to the recompiler to emulate the instruction.
606	*/
607	LogFlow(("pgmPhysGetPageEx %RGp failed with %Rrc\n", GCPhys, rc));
608	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
609	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
610	return VINF_EM_RAW_EMULATE_INSTR;
611	}
612
613	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
614
615	# ifdef PGM_OUT_OF_SYNC_IN_GC
616	/*
617	* We are here only if page is present in Guest page tables and trap is not handled
618	* by our handlers.
619	* Check it for page out-of-sync situation.
620	*/
621	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
622
623	if (!(uErr & X86_TRAP_PF_P))
624	{
625	/*
626	* Page is not present in our page tables.
627	* Try to sync it!
628	* BTW, fPageShw is invalid in this branch!
629	*/
630	if (uErr & X86_TRAP_PF_US)
631	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
632	else /* supervisor */
633	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
634
635	# if defined(LOG_ENABLED) && !defined(IN_RING0)
636	RTGCPHYS GCPhys;
637	uint64_t fPageGst;
638	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
639	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
640	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
641	# endif /* LOG_ENABLED */
642
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
644	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
645	{
646	uint64_t fPageGst;
647	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
648	if ( RT_SUCCESS(rc)
649	&& !(fPageGst & X86_PTE_US))
650	{
651	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
652	if ( pvFault == (RTGCPTR)pRegFrame->eip
653	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
654	# ifdef CSAM_DETECT_NEW_CODE_PAGES
655	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
656	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
657	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
658	)
659	{
660	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
661	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
662	if (rc != VINF_SUCCESS)
663	{
664	/*
665	* CSAM needs to perform a job in ring 3.
666	*
667	* Sync the page before going to the host context; otherwise we'll end up in a loop if
668	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
669	*/
670	LogFlow(("CSAM ring 3 job\n"));
671	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
672	AssertRC(rc2);
673
674	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
675	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
676	return rc;
677	}
678	}
679	# ifdef CSAM_DETECT_NEW_CODE_PAGES
680	else if ( uErr == X86_TRAP_PF_RW
681	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
682	&& pRegFrame->ecx < 0x10000)
683	{
684	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
685	* to detect loading of new code pages.
686	*/
687
688	/*
689	* Decode the instruction.
690	*/
691	RTGCPTR PC;
692	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
693	if (rc == VINF_SUCCESS)
694	{
695	DISCPUSTATE Cpu;
696	uint32_t cbOp;
697	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
698
699	/* For now we'll restrict this to rep movsw/d instructions */
700	if ( rc == VINF_SUCCESS
701	&& Cpu.pCurInstr->opcode == OP_MOVSWD
702	&& (Cpu.prefix & PREFIX_REP))
703	{
704	CSAMMarkPossibleCodePage(pVM, pvFault);
705	}
706	}
707	}
708	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
709
710	/*
711	* Mark this page as safe.
712	*/
713	/** @todo not correct for pages that contain both code and data!! */
714	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
715	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
716	}
717	}
718	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
719	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
720	if (RT_SUCCESS(rc))
721	{
722	/* The page was successfully synced, return to the guest. */
723	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
724	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
725	return VINF_SUCCESS;
726	}
727	}
728	else
729	{
730	/*
731	* A side effect of not flushing global PDEs are out of sync pages due
732	* to physical monitored regions, that are no longer valid.
733	* Assume for now it only applies to the read/write flag
734	*/
735	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
736	{
737	if (uErr & X86_TRAP_PF_US)
738	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
739	else /* supervisor */
740	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
741
742
743	/*
744	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
745	*/
746	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
747	if (RT_SUCCESS(rc))
748	{
749	/*
750	* Page was successfully synced, return to guest.
751	*/
752	# ifdef VBOX_STRICT
753	RTGCPHYS GCPhys;
754	uint64_t fPageGst;
755	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
756	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
757	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
758
759	uint64_t fPageShw;
760	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
761	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
762	# endif /* VBOX_STRICT */
763	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
764	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
765	return VINF_SUCCESS;
766	}
767
768	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
769	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
770	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
771	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
772	{
773	uint64_t fPageGst;
774	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
775	if ( RT_SUCCESS(rc)
776	&& !(fPageGst & X86_PTE_RW))
777	{
778	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
779	if (RT_SUCCESS(rc))
780	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
781	else
782	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
783	return rc;
784	}
785	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
786	}
787	}
788
789	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
790	# ifdef VBOX_STRICT
791	/*
792	* Check for VMM page flags vs. Guest page flags consistency.
793	* Currently only for debug purposes.
794	*/
795	if (RT_SUCCESS(rc))
796	{
797	/* Get guest page flags. */
798	uint64_t fPageGst;
799	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
800	if (RT_SUCCESS(rc))
801	{
802	uint64_t fPageShw;
803	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
804
805	/*
806	* Compare page flags.
807	* Note: we have AVL, A, D bits desynched.
808	*/
809	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
810	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
811	}
812	else
813	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
814	}
815	else
816	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
817	# endif /* VBOX_STRICT */
818	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
819	}
820	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
821	# endif /* PGM_OUT_OF_SYNC_IN_GC */
822	}
823	else
824	{
825	/*
826	* Page not present in Guest OS or invalid page table address.
827	* This is potential virtual page access handler food.
828	*
829	* For the present we'll say that our access handlers don't
830	* work for this case - we've already discarded the page table
831	* not present case which is identical to this.
832	*
833	* When we perchance find we need this, we will probably have AVL
834	* trees (offset based) to operate on and we can measure their speed
835	* agains mapping a page table and probably rearrange this handling
836	* a bit. (Like, searching virtual ranges before checking the
837	* physical address.)
838	*/
839	}
840	}
841
842
843	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
844	/*
845	* Conclusion, this is a guest trap.
846	*/
847	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
848	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
849	return VINF_EM_RAW_GUEST_TRAP;
850	# else
851	/* present, but not a monitored page; perhaps the guest is probing physical memory */
852	return VINF_EM_RAW_EMULATE_INSTR;
853	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
854
855
856	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
857
858	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
859	return VERR_INTERNAL_ERROR;
860	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
861	}
862	#endif /* !IN_RING3 */
863
864
865	/**
866	* Emulation of the invlpg instruction.
867	*
868	*
869	* @returns VBox status code.
870	*
871	* @param pVM VM handle.
872	* @param GCPtrPage Page to invalidate.
873	*
874	* @remark ASSUMES that the guest is updating before invalidating. This order
875	* isn't required by the CPU, so this is speculative and could cause
876	* trouble.
877	*
878	* @todo Flush page or page directory only if necessary!
879	* @todo Add a #define for simply invalidating the page.
880	*/
881	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
882	{
883	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
884	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
885	&& PGM_SHW_TYPE != PGM_TYPE_EPT
886	int rc;
887
888	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
889	/*
890	* Get the shadow PD entry and skip out if this PD isn't present.
891	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
892	*/
893	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
894	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
895	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
896	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
897	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
898	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
899
900	/* If the shadow PDPE isn't present, then skip the invalidate. */
901	if (!pPdptDst->a[iPdpt].n.u1Present)
902	{
903	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
904	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
905	return VINF_SUCCESS;
906	}
907
908	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - pool index only atm! /;
909	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
910
911	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
912	/* PML4 */
913	AssertReturn(pVM->pgm.s.pShwPaePml4R3, VERR_INTERNAL_ERROR);
914
915	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
916	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
917	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
918	PX86PDPAE pPDDst;
919	PX86PDPT pPdptDst;
920	PX86PML4E pPml4eDst;
921	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
922	if (rc != VINF_SUCCESS)
923	{
924	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
925	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
926	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
927	PGM_INVL_GUEST_TLBS();
928	return VINF_SUCCESS;
929	}
930	Assert(pPDDst);
931
932	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
933	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
934
935	if (!pPdpeDst->n.u1Present)
936	{
937	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
938	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
939	PGM_INVL_GUEST_TLBS();
940	return VINF_SUCCESS;
941	}
942
943	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
944
945	const SHWPDE PdeDst = *pPdeDst;
946	if (!PdeDst.n.u1Present)
947	{
948	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
949	return VINF_SUCCESS;
950	}
951
952	/*
953	* Get the guest PD entry and calc big page.
954	*/
955	# if PGM_GST_TYPE == PGM_TYPE_32BIT
956	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
957	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
958	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
959	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
960	unsigned iPDSrc;
961	# if PGM_GST_TYPE == PGM_TYPE_PAE
962	X86PDPE PdpeSrc;
963	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
964	# else /* AMD64 */
965	PX86PML4E pPml4eSrc;
966	X86PDPE PdpeSrc;
967	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
968	# endif
969	GSTPDE PdeSrc;
970
971	if (pPDSrc)
972	PdeSrc = pPDSrc->a[iPDSrc];
973	else
974	PdeSrc.u = 0;
975	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
976
977	# if PGM_GST_TYPE == PGM_TYPE_AMD64
978	const bool fIsBigPage = PdeSrc.b.u1Size;
979	# else
980	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
981	# endif
982
983	# ifdef IN_RING3
984	/*
985	* If a CR3 Sync is pending we may ignore the invalidate page operation
986	* depending on the kind of sync and if it's a global page or not.
987	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
988	*/
989	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
990	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
991	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
992	&& fIsBigPage
993	&& PdeSrc.b.u1Global
994	)
995	)
996	# else
997	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
998	# endif
999	{
1000	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1001	return VINF_SUCCESS;
1002	}
1003	# endif /* IN_RING3 */
1004
1005	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1006	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1007
1008	/* Fetch the pgm pool shadow descriptor. */
1009	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1010	Assert(pShwPdpt);
1011
1012	/* Fetch the pgm pool shadow descriptor. */
1013	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1014	Assert(pShwPde);
1015
1016	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1017	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1018
1019	if ( !pPml4eSrc->n.u1Present
1020	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1021	{
1022	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1023	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1024	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1025	pPml4eDst->u = 0;
1026	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1027	PGM_INVL_GUEST_TLBS();
1028	return VINF_SUCCESS;
1029	}
1030	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1031	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1032	{
1033	/*
1034	* Mark not present so we can resync the PML4E when it's used.
1035	*/
1036	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1037	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1038	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1039	pPml4eDst->u = 0;
1040	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1041	PGM_INVL_GUEST_TLBS();
1042	}
1043	else if (!pPml4eSrc->n.u1Accessed)
1044	{
1045	/*
1046	* Mark not present so we can set the accessed bit.
1047	*/
1048	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1049	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1050	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1051	pPml4eDst->u = 0;
1052	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1053	PGM_INVL_GUEST_TLBS();
1054	}
1055
1056	/* Check if the PDPT entry has changed. */
1057	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1058	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1059	if ( !PdpeSrc.n.u1Present
1060	\|\| pShwPde->GCPhys != GCPhysPd)
1061	{
1062	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1063	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1064	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1065	pPdpeDst->u = 0;
1066	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1067	PGM_INVL_GUEST_TLBS();
1068	return VINF_SUCCESS;
1069	}
1070	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1071	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1072	{
1073	/*
1074	* Mark not present so we can resync the PDPTE when it's used.
1075	*/
1076	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1077	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1078	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1079	pPdpeDst->u = 0;
1080	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1081	PGM_INVL_GUEST_TLBS();
1082	}
1083	else if (!PdpeSrc.lm.u1Accessed)
1084	{
1085	/*
1086	* Mark not present so we can set the accessed bit.
1087	*/
1088	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1089	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1090	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1091	pPdpeDst->u = 0;
1092	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1093	PGM_INVL_GUEST_TLBS();
1094	}
1095	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_PAE
1098	/*
1099	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1100	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1101	*/
1102	if (!pPDSrc)
1103	{
1104	/* Guest PDPE not present */
1105	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
1106	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1107
1108	Assert(!PdpeSrc.n.u1Present);
1109	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
1110
1111	/* for each page directory entry */
1112	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1113	{
1114	if ( pPDDst->a[iPD].n.u1Present
1115	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
1116	{
1117	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDDst->a[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
1118	pPDDst->a[iPD].u = 0;
1119	}
1120	}
1121	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
1122	pPdptDst->a[iPdpt].n.u1Present = 0;
1123	PGM_INVL_GUEST_TLBS();
1124	}
1125	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
1126	# endif
1127
1128
1129	/*
1130	* Deal with the Guest PDE.
1131	*/
1132	rc = VINF_SUCCESS;
1133	if (PdeSrc.n.u1Present)
1134	{
1135	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1136	{
1137	/*
1138	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1139	*/
1140	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1141	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1142	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1143	}
1144	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1145	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1146	{
1147	/*
1148	* Mark not present so we can resync the PDE when it's used.
1149	*/
1150	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1151	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1152	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1153	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1154	# else
1155	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1156	# endif
1157	pPdeDst->u = 0;
1158	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1159	PGM_INVL_GUEST_TLBS();
1160	}
1161	else if (!PdeSrc.n.u1Accessed)
1162	{
1163	/*
1164	* Mark not present so we can set the accessed bit.
1165	*/
1166	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1167	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1168	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1169	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1170	# else
1171	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1172	# endif
1173	pPdeDst->u = 0;
1174	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1175	PGM_INVL_GUEST_TLBS();
1176	}
1177	else if (!fIsBigPage)
1178	{
1179	/*
1180	* 4KB - page.
1181	*/
1182	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1183	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1184	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1185	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1186	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1187	# endif
1188	if (pShwPage->GCPhys == GCPhys)
1189	{
1190	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1191	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1192	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1193	if (pPT->a[iPTEDst].n.u1Present)
1194	{
1195	# ifdef PGMPOOL_WITH_USER_TRACKING
1196	/* This is very unlikely with caching/monitoring enabled. */
1197	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1198	# endif
1199	pPT->a[iPTEDst].u = 0;
1200	}
1201	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1202	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1203	if (RT_SUCCESS(rc))
1204	rc = VINF_SUCCESS;
1205	# endif
1206	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1207	PGM_INVL_PG(GCPtrPage);
1208	}
1209	else
1210	{
1211	/*
1212	* The page table address changed.
1213	*/
1214	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1215	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1216	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1217	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1218	# else
1219	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1220	# endif
1221	pPdeDst->u = 0;
1222	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1223	PGM_INVL_GUEST_TLBS();
1224	}
1225	}
1226	else
1227	{
1228	/*
1229	* 2/4MB - page.
1230	*/
1231	/* Before freeing the page, check if anything really changed. */
1232	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1233	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1234	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1235	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1236	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1237	# endif
1238	if ( pShwPage->GCPhys == GCPhys
1239	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1240	{
1241	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1242	/** @todo PAT */
1243	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1244	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1245	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1246	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1247	{
1248	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1249	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1250	return VINF_SUCCESS;
1251	}
1252	}
1253
1254	/*
1255	* Ok, the page table is present and it's been changed in the guest.
1256	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1257	* We could do this for some flushes in GC too, but we need an algorithm for
1258	* deciding which 4MB pages containing code likely to be executed very soon.
1259	*/
1260	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1261	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1262	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1263	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1264	# else
1265	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1266	# endif
1267	pPdeDst->u = 0;
1268	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1269	PGM_INVL_BIG_PG(GCPtrPage);
1270	}
1271	}
1272	else
1273	{
1274	/*
1275	* Page directory is not present, mark shadow PDE not present.
1276	*/
1277	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1278	{
1279	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1280	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1281	# else
1282	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1283	# endif
1284	pPdeDst->u = 0;
1285	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1286	PGM_INVL_PG(GCPtrPage);
1287	}
1288	else
1289	{
1290	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1291	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1292	}
1293	}
1294
1295	return rc;
1296
1297	#else /* guest real and protected mode */
1298	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1299	return VINF_SUCCESS;
1300	#endif
1301	}
1302
1303
1304	#ifdef PGMPOOL_WITH_USER_TRACKING
1305	/**
1306	* Update the tracking of shadowed pages.
1307	*
1308	* @param pVM The VM handle.
1309	* @param pShwPage The shadow page.
1310	* @param HCPhys The physical page we is being dereferenced.
1311	*/
1312	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1313	{
1314	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1315	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1316	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1317
1318	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1319	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1320	* 2. write protect all shadowed pages. I.e. implement caching.
1321	*/
1322	/*
1323	* Find the guest address.
1324	*/
1325	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1326	pRam;
1327	pRam = pRam->CTX_SUFF(pNext))
1328	{
1329	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1330	while (iPage-- > 0)
1331	{
1332	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1333	{
1334	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1335	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1336	pShwPage->cPresent--;
1337	pPool->cPresent--;
1338	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1339	return;
1340	}
1341	}
1342	}
1343
1344	for (;;)
1345	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1346	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1347	pShwPage->cPresent--;
1348	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1349	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1350	}
1351
1352
1353	/**
1354	* Update the tracking of shadowed pages.
1355	*
1356	* @param pVM The VM handle.
1357	* @param pShwPage The shadow page.
1358	* @param u16 The top 16-bit of the pPage->HCPhys.
1359	* @param pPage Pointer to the guest page. this will be modified.
1360	* @param iPTDst The index into the shadow table.
1361	*/
1362	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1363	{
1364	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1365	/*
1366	* We're making certain assumptions about the placement of cRef and idx.
1367	*/
1368	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1369	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1370
1371	/*
1372	* Just deal with the simple first time here.
1373	*/
1374	if (!u16)
1375	{
1376	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1377	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1378	}
1379	else
1380	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1381
1382	/* write back, trying to be clever... */
1383	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%RHp->%RHp iPTDst=%#x\n",
1384	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1385	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1386	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1387
1388	/* update statistics. */
1389	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1390	pShwPage->cPresent++;
1391	if (pShwPage->iFirstPresent > iPTDst)
1392	pShwPage->iFirstPresent = iPTDst;
1393	}
1394	#endif /* PGMPOOL_WITH_USER_TRACKING */
1395
1396
1397	/**
1398	* Creates a 4K shadow page for a guest page.
1399	*
1400	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1401	* physical address. The PdeSrc argument only the flags are used. No page structured
1402	* will be mapped in this function.
1403	*
1404	* @param pVM VM handle.
1405	* @param pPteDst Destination page table entry.
1406	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1407	* Can safely assume that only the flags are being used.
1408	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1409	* @param pShwPage Pointer to the shadow page.
1410	* @param iPTDst The index into the shadow table.
1411	*
1412	* @remark Not used for 2/4MB pages!
1413	*/
1414	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1415	{
1416	if (PteSrc.n.u1Present)
1417	{
1418	/*
1419	* Find the ram range.
1420	*/
1421	PPGMPAGE pPage;
1422	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1423	if (RT_SUCCESS(rc))
1424	{
1425	/** @todo investiage PWT, PCD and PAT. */
1426	/*
1427	* Make page table entry.
1428	*/
1429	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1430	SHWPTE PteDst;
1431	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1432	{
1433	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1434	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1435	{
1436	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1437	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1438	PteDst.n.u1Present = 1;
1439	PteDst.n.u1Execute = 1;
1440	PteDst.n.u1IgnorePAT = 1;
1441	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1442	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1443	#else
1444	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1445	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1446	#endif
1447	}
1448	else
1449	{
1450	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", HCPhys));
1451	PteDst.u = 0;
1452	}
1453	/** @todo count these two kinds. */
1454	}
1455	else
1456	{
1457	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1458	/*
1459	* If the page or page directory entry is not marked accessed,
1460	* we mark the page not present.
1461	*/
1462	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1463	{
1464	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1465	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1466	PteDst.u = 0;
1467	}
1468	else
1469	/*
1470	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1471	* when the page is modified.
1472	*/
1473	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1474	{
1475	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1476	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1477	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1478	\| PGM_PTFLAGS_TRACK_DIRTY;
1479	}
1480	else
1481	#endif
1482	{
1483	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1484	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1485	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1486	PteDst.n.u1Present = 1;
1487	PteDst.n.u1Write = 1;
1488	PteDst.n.u1Execute = 1;
1489	PteDst.n.u1IgnorePAT = 1;
1490	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1491	/* PteDst.n.u1Size = 0 */
1492	#else
1493	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1494	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1495	#endif
1496	}
1497	}
1498
1499	#ifdef PGMPOOL_WITH_USER_TRACKING
1500	/*
1501	* Keep user track up to date.
1502	*/
1503	if (PteDst.n.u1Present)
1504	{
1505	if (!pPteDst->n.u1Present)
1506	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1507	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1508	{
1509	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1510	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1511	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1512	}
1513	}
1514	else if (pPteDst->n.u1Present)
1515	{
1516	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1517	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1518	}
1519	#endif /* PGMPOOL_WITH_USER_TRACKING */
1520
1521	/*
1522	* Update statistics and commit the entry.
1523	*/
1524	if (!PteSrc.n.u1Global)
1525	pShwPage->fSeenNonGlobal = true;
1526	*pPteDst = PteDst;
1527	}
1528	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1529	/** @todo count these. */
1530	}
1531	else
1532	{
1533	/*
1534	* Page not-present.
1535	*/
1536	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1537	#ifdef PGMPOOL_WITH_USER_TRACKING
1538	/* Keep user track up to date. */
1539	if (pPteDst->n.u1Present)
1540	{
1541	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1542	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1543	}
1544	#endif /* PGMPOOL_WITH_USER_TRACKING */
1545	pPteDst->u = 0;
1546	/** @todo count these. */
1547	}
1548	}
1549
1550
1551	/**
1552	* Syncs a guest OS page.
1553	*
1554	* There are no conflicts at this point, neither is there any need for
1555	* page table allocations.
1556	*
1557	* @returns VBox status code.
1558	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1559	* @param pVM VM handle.
1560	* @param PdeSrc Page directory entry of the guest.
1561	* @param GCPtrPage Guest context page address.
1562	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1563	* @param uErr Fault error (X86_TRAP_PF_*).
1564	*/
1565	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1566	{
1567	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1568
1569	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1570	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1571	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1572	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1573	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1574
1575	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1576	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1577	# endif
1578
1579	/*
1580	* Assert preconditions.
1581	*/
1582	Assert(PdeSrc.n.u1Present);
1583	Assert(cPages);
1584	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1585
1586	/*
1587	* Get the shadow PDE, find the shadow page table in the pool.
1588	*/
1589	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1590	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1591	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1592
1593	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1594	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
1595	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1596	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1597	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
1598	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
1599	X86PDEPAE PdeDst = *pPdeDst;
1600
1601	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1602	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1603	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1604	PX86PDPAE pPDDst;
1605	X86PDEPAE PdeDst;
1606	PX86PDPT pPdptDst;
1607
1608	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1609	AssertRCSuccessReturn(rc, rc);
1610	Assert(pPDDst && pPdptDst);
1611	PdeDst = pPDDst->a[iPDDst];
1612	# endif
1613	Assert(PdeDst.n.u1Present);
1614	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1615
1616	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1617	/* Fetch the pgm pool shadow descriptor. */
1618	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1619	Assert(pShwPde);
1620	# endif
1621
1622	/*
1623	* Check that the page is present and that the shadow PDE isn't out of sync.
1624	*/
1625	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1626	const bool fBigPage = PdeSrc.b.u1Size;
1627	# else
1628	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1629	# endif
1630	RTGCPHYS GCPhys;
1631	if (!fBigPage)
1632	{
1633	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1634	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1635	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1636	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1637	# endif
1638	}
1639	else
1640	{
1641	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1642	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1643	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1644	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1645	# endif
1646	}
1647	if ( pShwPage->GCPhys == GCPhys
1648	&& PdeSrc.n.u1Present
1649	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1650	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1651	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1652	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1653	# endif
1654	)
1655	{
1656	/*
1657	* Check that the PDE is marked accessed already.
1658	* Since we set the accessed bit before getting here on a #PF, this
1659	* check is only meant for dealing with non-#PF'ing paths.
1660	*/
1661	if (PdeSrc.n.u1Accessed)
1662	{
1663	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1664	if (!fBigPage)
1665	{
1666	/*
1667	* 4KB Page - Map the guest page table.
1668	*/
1669	PGSTPT pPTSrc;
1670	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1671	if (RT_SUCCESS(rc))
1672	{
1673	# ifdef PGM_SYNC_N_PAGES
1674	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1675	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1676	{
1677	/*
1678	* This code path is currently only taken when the caller is PGMTrap0eHandler
1679	* for non-present pages!
1680	*
1681	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1682	* deal with locality.
1683	*/
1684	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1685	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1686	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1687	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1688	# else
1689	const unsigned offPTSrc = 0;
1690	# endif
1691	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1692	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1693	iPTDst = 0;
1694	else
1695	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1696	for (; iPTDst < iPTDstEnd; iPTDst++)
1697	{
1698	if (!pPTDst->a[iPTDst].n.u1Present)
1699	{
1700	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1701	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1702	NOREF(GCPtrCurPage);
1703	#ifndef IN_RING0
1704	/*
1705	* Assuming kernel code will be marked as supervisor - and not as user level
1706	* and executed using a conforming code selector - And marked as readonly.
1707	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1708	*/
1709	PPGMPAGE pPage;
1710	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1711	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1712	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1713	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1714	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1715	)
1716	#endif /* else: CSAM not active */
1717	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1718	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1719	GCPtrCurPage, PteSrc.n.u1Present,
1720	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1721	PteSrc.n.u1User & PdeSrc.n.u1User,
1722	(uint64_t)PteSrc.u,
1723	(uint64_t)pPTDst->a[iPTDst].u,
1724	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1725	}
1726	}
1727	}
1728	else
1729	# endif /* PGM_SYNC_N_PAGES */
1730	{
1731	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1732	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1733	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1734	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1735	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1736	GCPtrPage, PteSrc.n.u1Present,
1737	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1738	PteSrc.n.u1User & PdeSrc.n.u1User,
1739	(uint64_t)PteSrc.u,
1740	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1741	}
1742	}
1743	else /* MMIO or invalid page: emulated in #PF handler. */
1744	{
1745	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1746	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1747	}
1748	}
1749	else
1750	{
1751	/*
1752	* 4/2MB page - lazy syncing shadow 4K pages.
1753	* (There are many causes of getting here, it's no longer only CSAM.)
1754	*/
1755	/* Calculate the GC physical address of this 4KB shadow page. */
1756	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1757	/* Find ram range. */
1758	PPGMPAGE pPage;
1759	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1760	if (RT_SUCCESS(rc))
1761	{
1762	/*
1763	* Make shadow PTE entry.
1764	*/
1765	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1766	SHWPTE PteDst;
1767	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1768	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1769	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1770	{
1771	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1772	PteDst.n.u1Write = 0;
1773	else
1774	PteDst.u = 0;
1775	}
1776	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1777	# ifdef PGMPOOL_WITH_USER_TRACKING
1778	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1779	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1780	# endif
1781	pPTDst->a[iPTDst] = PteDst;
1782
1783
1784	/*
1785	* If the page is not flagged as dirty and is writable, then make it read-only
1786	* at PD level, so we can set the dirty bit when the page is modified.
1787	*
1788	* ASSUMES that page access handlers are implemented on page table entry level.
1789	* Thus we will first catch the dirty access and set PDE.D and restart. If
1790	* there is an access handler, we'll trap again and let it work on the problem.
1791	*/
1792	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1793	* As for invlpg, it simply frees the whole shadow PT.
1794	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1795	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1796	{
1797	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1798	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1799	PdeDst.n.u1Write = 0;
1800	}
1801	else
1802	{
1803	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1804	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1805	}
1806	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1807	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1808	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1809	*pPdeDst = PdeDst;
1810	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1811	pPDDst->a[iPDDst] = PdeDst;
1812	# endif
1813	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1814	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1815	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1816	}
1817	else
1818	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1819	}
1820	return VINF_SUCCESS;
1821	}
1822	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1823	}
1824	else
1825	{
1826	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1827	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1828	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1829	}
1830
1831	/*
1832	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1833	* Yea, I'm lazy.
1834	*/
1835	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1836	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1837	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1838	# else
1839	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1840	# endif
1841
1842	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1843	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1844	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1845	pPdeDst->u = 0;
1846	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1847	pPDDst->a[iPDDst].u = 0;
1848	# endif
1849	PGM_INVL_GUEST_TLBS();
1850	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1851
1852	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1853	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1854	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1855
1856	# ifdef PGM_SYNC_N_PAGES
1857	/*
1858	* Get the shadow PDE, find the shadow page table in the pool.
1859	*/
1860	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1861	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1862	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1863	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1864	X86PDEPAE PdeDst;
1865	PdeDst.u = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1866
1867	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1868	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1869	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1870	PX86PDPAE pPDDst;
1871	X86PDEPAE PdeDst;
1872	PX86PDPT pPdptDst;
1873
1874	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1875	AssertRCSuccessReturn(rc, rc);
1876	Assert(pPDDst && pPdptDst);
1877	PdeDst = pPDDst->a[iPDDst];
1878	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1879	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1880	PEPTPD pPDDst;
1881	EPTPDE PdeDst;
1882
1883	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1884	if (rc != VINF_SUCCESS)
1885	{
1886	AssertRC(rc);
1887	return rc;
1888	}
1889	Assert(pPDDst);
1890	PdeDst = pPDDst->a[iPDDst];
1891	# endif
1892	Assert(PdeDst.n.u1Present);
1893	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1894	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1895
1896	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1897	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1898	{
1899	/*
1900	* This code path is currently only taken when the caller is PGMTrap0eHandler
1901	* for non-present pages!
1902	*
1903	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1904	* deal with locality.
1905	*/
1906	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1907	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1908	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1909	iPTDst = 0;
1910	else
1911	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1912	for (; iPTDst < iPTDstEnd; iPTDst++)
1913	{
1914	if (!pPTDst->a[iPTDst].n.u1Present)
1915	{
1916	GSTPTE PteSrc;
1917
1918	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1919
1920	/* Fake the page table entry */
1921	PteSrc.u = GCPtrCurPage;
1922	PteSrc.n.u1Present = 1;
1923	PteSrc.n.u1Dirty = 1;
1924	PteSrc.n.u1Accessed = 1;
1925	PteSrc.n.u1Write = 1;
1926	PteSrc.n.u1User = 1;
1927
1928	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1929
1930	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1931	GCPtrCurPage, PteSrc.n.u1Present,
1932	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1933	PteSrc.n.u1User & PdeSrc.n.u1User,
1934	(uint64_t)PteSrc.u,
1935	(uint64_t)pPTDst->a[iPTDst].u,
1936	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1937	}
1938	else
1939	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1940	}
1941	}
1942	else
1943	# endif /* PGM_SYNC_N_PAGES */
1944	{
1945	GSTPTE PteSrc;
1946	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1947	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1948
1949	/* Fake the page table entry */
1950	PteSrc.u = GCPtrCurPage;
1951	PteSrc.n.u1Present = 1;
1952	PteSrc.n.u1Dirty = 1;
1953	PteSrc.n.u1Accessed = 1;
1954	PteSrc.n.u1Write = 1;
1955	PteSrc.n.u1User = 1;
1956	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1957
1958	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1959	GCPtrPage, PteSrc.n.u1Present,
1960	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1961	PteSrc.n.u1User & PdeSrc.n.u1User,
1962	(uint64_t)PteSrc.u,
1963	(uint64_t)pPTDst->a[iPTDst].u,
1964	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1965	}
1966	return VINF_SUCCESS;
1967
1968	#else
1969	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1970	return VERR_INTERNAL_ERROR;
1971	#endif
1972	}
1973
1974
1975	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1976	/**
1977	* Investigate page fault and handle write protection page faults caused by
1978	* dirty bit tracking.
1979	*
1980	* @returns VBox status code.
1981	* @param pVM VM handle.
1982	* @param uErr Page fault error code.
1983	* @param pPdeDst Shadow page directory entry.
1984	* @param pPdeSrc Guest page directory entry.
1985	* @param GCPtrPage Guest context page address.
1986	*/
1987	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
1988	{
1989	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1990	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1991	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1992	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1993	bool fBigPagesSupported = true;
1994	# else
1995	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1996	# endif
1997	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1998	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1999	# endif
2000	unsigned uPageFaultLevel;
2001	int rc;
2002
2003	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2004	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2005
2006	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2007	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2008
2009	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2010	PX86PML4E pPml4eSrc;
2011	PX86PDPE pPdpeSrc;
2012
2013	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2014	Assert(pPml4eSrc);
2015
2016	/*
2017	* Real page fault? (PML4E level)
2018	*/
2019	if ( (uErr & X86_TRAP_PF_RSVD)
2020	\|\| !pPml4eSrc->n.u1Present
2021	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2022	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2023	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2024	)
2025	{
2026	uPageFaultLevel = 0;
2027	goto l_UpperLevelPageFault;
2028	}
2029	Assert(pPdpeSrc);
2030
2031	# else /* PAE */
2032	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2033	# endif /* PAE */
2034
2035	/*
2036	* Real page fault? (PDPE level)
2037	*/
2038	if ( (uErr & X86_TRAP_PF_RSVD)
2039	\|\| !pPdpeSrc->n.u1Present
2040	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2041	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2042	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2043	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2044	# endif
2045	)
2046	{
2047	uPageFaultLevel = 1;
2048	goto l_UpperLevelPageFault;
2049	}
2050	# endif
2051
2052	/*
2053	* Real page fault? (PDE level)
2054	*/
2055	if ( (uErr & X86_TRAP_PF_RSVD)
2056	\|\| !pPdeSrc->n.u1Present
2057	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2058	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2059	# endif
2060	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2061	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2062	{
2063	uPageFaultLevel = 2;
2064	goto l_UpperLevelPageFault;
2065	}
2066
2067	/*
2068	* First check the easy case where the page directory has been marked read-only to track
2069	* the dirty bit of an emulated BIG page
2070	*/
2071	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2072	{
2073	/* Mark guest page directory as accessed */
2074	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2075	pPml4eSrc->n.u1Accessed = 1;
2076	pPdpeSrc->lm.u1Accessed = 1;
2077	# endif
2078	pPdeSrc->b.u1Accessed = 1;
2079
2080	/*
2081	* Only write protection page faults are relevant here.
2082	*/
2083	if (fWriteFault)
2084	{
2085	/* Mark guest page directory as dirty (BIG page only). */
2086	pPdeSrc->b.u1Dirty = 1;
2087
2088	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2089	{
2090	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2091
2092	Assert(pPdeSrc->b.u1Write);
2093
2094	pPdeDst->n.u1Write = 1;
2095	pPdeDst->n.u1Accessed = 1;
2096	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2097	PGM_INVL_BIG_PG(GCPtrPage);
2098	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2099	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2100	}
2101	}
2102	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2103	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2104	}
2105	/* else: 4KB page table */
2106
2107	/*
2108	* Map the guest page table.
2109	*/
2110	PGSTPT pPTSrc;
2111	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2112	if (RT_SUCCESS(rc))
2113	{
2114	/*
2115	* Real page fault?
2116	*/
2117	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2118	const GSTPTE PteSrc = *pPteSrc;
2119	if ( !PteSrc.n.u1Present
2120	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2121	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2122	# endif
2123	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2124	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2125	)
2126	{
2127	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2128	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2129	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2130
2131	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2132	* See the 2nd case above as well.
2133	*/
2134	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2135	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2136
2137	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2138	return VINF_EM_RAW_GUEST_TRAP;
2139	}
2140	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2141
2142	/*
2143	* Set the accessed bits in the page directory and the page table.
2144	*/
2145	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2146	pPml4eSrc->n.u1Accessed = 1;
2147	pPdpeSrc->lm.u1Accessed = 1;
2148	# endif
2149	pPdeSrc->n.u1Accessed = 1;
2150	pPteSrc->n.u1Accessed = 1;
2151
2152	/*
2153	* Only write protection page faults are relevant here.
2154	*/
2155	if (fWriteFault)
2156	{
2157	/* Write access, so mark guest entry as dirty. */
2158	# ifdef VBOX_WITH_STATISTICS
2159	if (!pPteSrc->n.u1Dirty)
2160	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2161	else
2162	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2163	# endif
2164
2165	pPteSrc->n.u1Dirty = 1;
2166
2167	if (pPdeDst->n.u1Present)
2168	{
2169	#ifndef IN_RING0
2170	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2171	* Our individual shadow handlers will provide more information and force a fatal exit.
2172	*/
2173	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2174	{
2175	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2176	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2177	return VINF_SUCCESS;
2178	}
2179	#endif
2180	/*
2181	* Map shadow page table.
2182	*/
2183	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2184	if (pShwPage)
2185	{
2186	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2187	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2188	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2189	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2190	{
2191	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2192	# ifdef VBOX_STRICT
2193	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2194	if (pPage)
2195	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2196	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2197	# endif
2198	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2199
2200	Assert(pPteSrc->n.u1Write);
2201
2202	pPteDst->n.u1Write = 1;
2203	pPteDst->n.u1Dirty = 1;
2204	pPteDst->n.u1Accessed = 1;
2205	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2206	PGM_INVL_PG(GCPtrPage);
2207
2208	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2209	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2210	}
2211	}
2212	else
2213	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2214	}
2215	}
2216	/** @todo Optimize accessed bit emulation? */
2217	# ifdef VBOX_STRICT
2218	/*
2219	* Sanity check.
2220	*/
2221	else if ( !pPteSrc->n.u1Dirty
2222	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2223	&& pPdeDst->n.u1Present)
2224	{
2225	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2226	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2227	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2228	if ( pPteDst->n.u1Present
2229	&& pPteDst->n.u1Write)
2230	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2231	}
2232	# endif /* VBOX_STRICT */
2233	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2234	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2235	}
2236	AssertRC(rc);
2237	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2238	return rc;
2239
2240
2241	l_UpperLevelPageFault:
2242	/*
2243	* Pagefault detected while checking the PML4E, PDPE or PDE.
2244	* Single exit handler to get rid of duplicate code paths.
2245	*/
2246	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2247	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2248	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2249
2250	if (
2251	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2252	pPml4eSrc->n.u1Present &&
2253	# endif
2254	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2255	pPdpeSrc->n.u1Present &&
2256	# endif
2257	pPdeSrc->n.u1Present)
2258	{
2259	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2260	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2261	{
2262	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2263	}
2264	else
2265	{
2266	/*
2267	* Map the guest page table.
2268	*/
2269	PGSTPT pPTSrc;
2270	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2271	if (RT_SUCCESS(rc))
2272	{
2273	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2274	const GSTPTE PteSrc = *pPteSrc;
2275	if (pPteSrc->n.u1Present)
2276	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2277	}
2278	AssertRC(rc);
2279	}
2280	}
2281	return VINF_EM_RAW_GUEST_TRAP;
2282	}
2283	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2284
2285
2286	/**
2287	* Sync a shadow page table.
2288	*
2289	* The shadow page table is not present. This includes the case where
2290	* there is a conflict with a mapping.
2291	*
2292	* @returns VBox status code.
2293	* @param pVM VM handle.
2294	* @param iPD Page directory index.
2295	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2296	* Assume this is a temporary mapping.
2297	* @param GCPtrPage GC Pointer of the page that caused the fault
2298	*/
2299	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2300	{
2301	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2302	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2303	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2304
2305	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2306	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2307	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2308	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2309	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2310
2311	int rc = VINF_SUCCESS;
2312
2313	/*
2314	* Validate input a little bit.
2315	*/
2316	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2317	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2318	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2319	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2320	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2321
2322	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2323	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
2324	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
2325	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2326	PSHWPDE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2327
2328	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2329	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2330	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2331	PX86PDPAE pPDDst;
2332	PX86PDPT pPdptDst;
2333	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2334	AssertRCSuccessReturn(rc, rc);
2335	Assert(pPDDst);
2336	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2337	# endif
2338	SHWPDE PdeDst = *pPdeDst;
2339
2340	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2341	/* Fetch the pgm pool shadow descriptor. */
2342	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2343	Assert(pShwPde);
2344	# endif
2345
2346	# ifndef PGM_WITHOUT_MAPPINGS
2347	/*
2348	* Check for conflicts.
2349	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2350	* HC: Simply resolve the conflict.
2351	*/
2352	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2353	{
2354	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2355	# ifndef IN_RING3
2356	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2357	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2358	return VERR_ADDRESS_CONFLICT;
2359	# else
2360	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2361	Assert(pMapping);
2362	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2363	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2364	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2365	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2366	# else
2367	AssertFailed(); /* can't happen for amd64 */
2368	# endif
2369	if (RT_FAILURE(rc))
2370	{
2371	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2372	return rc;
2373	}
2374	PdeDst = *pPdeDst;
2375	# endif
2376	}
2377	# else /* PGM_WITHOUT_MAPPINGS */
2378	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2379	# endif /* PGM_WITHOUT_MAPPINGS */
2380	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2381
2382	/*
2383	* Sync page directory entry.
2384	*/
2385	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2386	if (PdeSrc.n.u1Present)
2387	{
2388	/*
2389	* Allocate & map the page table.
2390	*/
2391	PSHWPT pPTDst;
2392	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2393	const bool fPageTable = !PdeSrc.b.u1Size;
2394	# else
2395	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2396	# endif
2397	PPGMPOOLPAGE pShwPage;
2398	RTGCPHYS GCPhys;
2399	if (fPageTable)
2400	{
2401	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2402	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2403	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2404	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2405	# endif
2406	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2407	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2408	# else
2409	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2410	# endif
2411	}
2412	else
2413	{
2414	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2415	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2416	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2417	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2418	# endif
2419	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2420	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2421	# else
2422	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2423	# endif
2424	}
2425	if (rc == VINF_SUCCESS)
2426	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2427	else if (rc == VINF_PGM_CACHED_PAGE)
2428	{
2429	/*
2430	* The PT was cached, just hook it up.
2431	*/
2432	if (fPageTable)
2433	PdeDst.u = pShwPage->Core.Key
2434	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2435	else
2436	{
2437	PdeDst.u = pShwPage->Core.Key
2438	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2439	/* (see explanation and assumptions further down.) */
2440	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2441	{
2442	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2443	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2444	PdeDst.b.u1Write = 0;
2445	}
2446	}
2447	*pPdeDst = PdeDst;
2448	return VINF_SUCCESS;
2449	}
2450	else if (rc == VERR_PGM_POOL_FLUSHED)
2451	{
2452	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2453	return VINF_PGM_SYNC_CR3;
2454	}
2455	else
2456	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2457	PdeDst.u &= X86_PDE_AVL_MASK;
2458	PdeDst.u \|= pShwPage->Core.Key;
2459
2460	/*
2461	* Page directory has been accessed (this is a fault situation, remember).
2462	*/
2463	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2464	if (fPageTable)
2465	{
2466	/*
2467	* Page table - 4KB.
2468	*
2469	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2470	*/
2471	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2472	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2473	PGSTPT pPTSrc;
2474	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2475	if (RT_SUCCESS(rc))
2476	{
2477	/*
2478	* Start by syncing the page directory entry so CSAM's TLB trick works.
2479	*/
2480	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2481	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2482	*pPdeDst = PdeDst;
2483
2484	/*
2485	* Directory/page user or supervisor privilege: (same goes for read/write)
2486	*
2487	* Directory Page Combined
2488	* U/S U/S U/S
2489	* 0 0 0
2490	* 0 1 0
2491	* 1 0 0
2492	* 1 1 1
2493	*
2494	* Simple AND operation. Table listed for completeness.
2495	*
2496	*/
2497	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2498	# ifdef PGM_SYNC_N_PAGES
2499	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2500	unsigned iPTDst = iPTBase;
2501	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2502	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2503	iPTDst = 0;
2504	else
2505	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2506	# else /* !PGM_SYNC_N_PAGES */
2507	unsigned iPTDst = 0;
2508	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2509	# endif /* !PGM_SYNC_N_PAGES */
2510	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2511	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2512	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2513	# else
2514	const unsigned offPTSrc = 0;
2515	# endif
2516	for (; iPTDst < iPTDstEnd; iPTDst++)
2517	{
2518	const unsigned iPTSrc = iPTDst + offPTSrc;
2519	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2520
2521	if (PteSrc.n.u1Present) /* we've already cleared it above */
2522	{
2523	# ifndef IN_RING0
2524	/*
2525	* Assuming kernel code will be marked as supervisor - and not as user level
2526	* and executed using a conforming code selector - And marked as readonly.
2527	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2528	*/
2529	PPGMPAGE pPage;
2530	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2531	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2532	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2533	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2534	)
2535	# endif
2536	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2537	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2538	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2539	PteSrc.n.u1Present,
2540	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2541	PteSrc.n.u1User & PdeSrc.n.u1User,
2542	(uint64_t)PteSrc.u,
2543	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2544	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2545	}
2546	} /* for PTEs */
2547	}
2548	}
2549	else
2550	{
2551	/*
2552	* Big page - 2/4MB.
2553	*
2554	* We'll walk the ram range list in parallel and optimize lookups.
2555	* We will only sync on shadow page table at a time.
2556	*/
2557	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2558
2559	/**
2560	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2561	*/
2562
2563	/*
2564	* Start by syncing the page directory entry.
2565	*/
2566	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2567	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2568
2569	/*
2570	* If the page is not flagged as dirty and is writable, then make it read-only
2571	* at PD level, so we can set the dirty bit when the page is modified.
2572	*
2573	* ASSUMES that page access handlers are implemented on page table entry level.
2574	* Thus we will first catch the dirty access and set PDE.D and restart. If
2575	* there is an access handler, we'll trap again and let it work on the problem.
2576	*/
2577	/** @todo move the above stuff to a section in the PGM documentation. */
2578	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2579	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2580	{
2581	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2582	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2583	PdeDst.b.u1Write = 0;
2584	}
2585	*pPdeDst = PdeDst;
2586
2587	/*
2588	* Fill the shadow page table.
2589	*/
2590	/* Get address and flags from the source PDE. */
2591	SHWPTE PteDstBase;
2592	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2593
2594	/* Loop thru the entries in the shadow PT. */
2595	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2596	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2597	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2598	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2599	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2600	unsigned iPTDst = 0;
2601	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2602	{
2603	/* Advance ram range list. */
2604	while (pRam && GCPhys > pRam->GCPhysLast)
2605	pRam = pRam->CTX_SUFF(pNext);
2606	if (pRam && GCPhys >= pRam->GCPhys)
2607	{
2608	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2609	do
2610	{
2611	/* Make shadow PTE. */
2612	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2613	SHWPTE PteDst;
2614
2615	/* Make sure the RAM has already been allocated. */
2616	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2617	{
2618	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2619	{
2620	# ifdef IN_RING3
2621	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2622	# else
2623	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2624	# endif
2625	if (rc != VINF_SUCCESS)
2626	return rc;
2627	}
2628	}
2629
2630	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2631	{
2632	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2633	{
2634	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2635	PteDst.n.u1Write = 0;
2636	}
2637	else
2638	PteDst.u = 0;
2639	}
2640	# ifndef IN_RING0
2641	/*
2642	* Assuming kernel code will be marked as supervisor and not as user level and executed
2643	* using a conforming code selector. Don't check for readonly, as that implies the whole
2644	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2645	*/
2646	else if ( !PdeSrc.n.u1User
2647	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2648	PteDst.u = 0;
2649	# endif
2650	else
2651	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2652	# ifdef PGMPOOL_WITH_USER_TRACKING
2653	if (PteDst.n.u1Present)
2654	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2655	# endif
2656	/* commit it */
2657	pPTDst->a[iPTDst] = PteDst;
2658	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2659	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2660	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2661
2662	/* advance */
2663	GCPhys += PAGE_SIZE;
2664	iHCPage++;
2665	iPTDst++;
2666	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2667	&& GCPhys <= pRam->GCPhysLast);
2668	}
2669	else if (pRam)
2670	{
2671	Log(("Invalid pages at %RGp\n", GCPhys));
2672	do
2673	{
2674	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2675	GCPhys += PAGE_SIZE;
2676	iPTDst++;
2677	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2678	&& GCPhys < pRam->GCPhys);
2679	}
2680	else
2681	{
2682	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2683	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2684	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2685	}
2686	} /* while more PTEs */
2687	} /* 4KB / 4MB */
2688	}
2689	else
2690	AssertRelease(!PdeDst.n.u1Present);
2691
2692	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2693	if (RT_FAILURE(rc))
2694	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2695	return rc;
2696
2697	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2698	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2699	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2700
2701
2702	/*
2703	* Validate input a little bit.
2704	*/
2705	int rc = VINF_SUCCESS;
2706	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2707	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2708	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2709	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2710
2711	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2712	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm!/;
2713	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2714
2715	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2716	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2717	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2718	PX86PDPAE pPDDst;
2719	PX86PDPT pPdptDst;
2720	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2721	AssertRCSuccessReturn(rc, rc);
2722	Assert(pPDDst);
2723	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2724
2725	/* Fetch the pgm pool shadow descriptor. */
2726	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2727	Assert(pShwPde);
2728
2729	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2730	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2731	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2732	PEPTPD pPDDst;
2733	PEPTPDPT pPdptDst;
2734
2735	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2736	if (rc != VINF_SUCCESS)
2737	{
2738	AssertRC(rc);
2739	return rc;
2740	}
2741	Assert(pPDDst);
2742	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2743
2744	/* Fetch the pgm pool shadow descriptor. */
2745	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2746	Assert(pShwPde);
2747	# endif
2748	SHWPDE PdeDst = *pPdeDst;
2749
2750	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2751	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2752
2753	GSTPDE PdeSrc;
2754	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2755	PdeSrc.n.u1Present = 1;
2756	PdeSrc.n.u1Write = 1;
2757	PdeSrc.n.u1Accessed = 1;
2758	PdeSrc.n.u1User = 1;
2759
2760	/*
2761	* Allocate & map the page table.
2762	*/
2763	PSHWPT pPTDst;
2764	PPGMPOOLPAGE pShwPage;
2765	RTGCPHYS GCPhys;
2766
2767	/* Virtual address = physical address */
2768	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2769	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2770	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2771	# else
2772	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2773	# endif
2774
2775	if ( rc == VINF_SUCCESS
2776	\|\| rc == VINF_PGM_CACHED_PAGE)
2777	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2778	else
2779	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2780
2781	PdeDst.u &= X86_PDE_AVL_MASK;
2782	PdeDst.u \|= pShwPage->Core.Key;
2783	PdeDst.n.u1Present = 1;
2784	PdeDst.n.u1Write = 1;
2785	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2786	PdeDst.n.u1Execute = 1;
2787	# else
2788	PdeDst.n.u1User = 1;
2789	PdeDst.n.u1Accessed = 1;
2790	# endif
2791	*pPdeDst = PdeDst;
2792
2793	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2794	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2795	return rc;
2796
2797	#else
2798	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2799	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2800	return VERR_INTERNAL_ERROR;
2801	#endif
2802	}
2803
2804
2805
2806	/**
2807	* Prefetch a page/set of pages.
2808	*
2809	* Typically used to sync commonly used pages before entering raw mode
2810	* after a CR3 reload.
2811	*
2812	* @returns VBox status code.
2813	* @param pVM VM handle.
2814	* @param GCPtrPage Page to invalidate.
2815	*/
2816	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2817	{
2818	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2819	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2820	/*
2821	* Check that all Guest levels thru the PDE are present, getting the
2822	* PD and PDE in the processes.
2823	*/
2824	int rc = VINF_SUCCESS;
2825	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2826	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2827	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2828	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2829	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2830	unsigned iPDSrc;
2831	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2832	if (!pPDSrc)
2833	return VINF_SUCCESS; /* not present */
2834	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2835	unsigned iPDSrc;
2836	PX86PML4E pPml4eSrc;
2837	X86PDPE PdpeSrc;
2838	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2839	if (!pPDSrc)
2840	return VINF_SUCCESS; /* not present */
2841	# endif
2842	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2843	# else
2844	PGSTPD pPDSrc = NULL;
2845	const unsigned iPDSrc = 0;
2846	GSTPDE PdeSrc;
2847
2848	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2849	PdeSrc.n.u1Present = 1;
2850	PdeSrc.n.u1Write = 1;
2851	PdeSrc.n.u1Accessed = 1;
2852	PdeSrc.n.u1User = 1;
2853	# endif
2854
2855	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2856	{
2857	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2858	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2859	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2860	X86PDEPAE PdeDst;
2861	PdeDst.u = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
2862	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2863	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2864	PX86PDPAE pPDDst;
2865	X86PDEPAE PdeDst;
2866
2867	# if PGM_GST_TYPE == PGM_TYPE_PROT
2868	/* AMD-V nested paging */
2869	X86PML4E Pml4eSrc;
2870	X86PDPE PdpeSrc;
2871	PX86PML4E pPml4eSrc = &Pml4eSrc;
2872
2873	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2874	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2875	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2876	# endif
2877
2878	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2879	if (rc != VINF_SUCCESS)
2880	{
2881	AssertRC(rc);
2882	return rc;
2883	}
2884	Assert(pPDDst);
2885	PdeDst = pPDDst->a[iPDDst];
2886	# endif
2887	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2888	{
2889	if (!PdeDst.n.u1Present)
2890	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2891	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2892	else
2893	{
2894	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2895	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2896	* makes no sense to prefetch more than one page.
2897	*/
2898	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2899	if (RT_SUCCESS(rc))
2900	rc = VINF_SUCCESS;
2901	}
2902	}
2903	}
2904	return rc;
2905
2906	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2907	return VINF_SUCCESS; /* ignore */
2908	#endif
2909	}
2910
2911
2912
2913
2914	/**
2915	* Syncs a page during a PGMVerifyAccess() call.
2916	*
2917	* @returns VBox status code (informational included).
2918	* @param GCPtrPage The address of the page to sync.
2919	* @param fPage The effective guest page flags.
2920	* @param uErr The trap error code.
2921	*/
2922	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
2923	{
2924	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2925
2926	Assert(!HWACCMIsNestedPagingActive(pVM));
2927	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2928	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2929
2930	# ifndef IN_RING0
2931	if (!(fPage & X86_PTE_US))
2932	{
2933	/*
2934	* Mark this page as safe.
2935	*/
2936	/** @todo not correct for pages that contain both code and data!! */
2937	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
2938	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2939	}
2940	# endif
2941
2942	/*
2943	* Get guest PD and index.
2944	*/
2945	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2946	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2947	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2948	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2949	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2950	unsigned iPDSrc;
2951	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2952
2953	if (pPDSrc)
2954	{
2955	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2956	return VINF_EM_RAW_GUEST_TRAP;
2957	}
2958	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2959	unsigned iPDSrc;
2960	PX86PML4E pPml4eSrc;
2961	X86PDPE PdpeSrc;
2962	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2963	if (!pPDSrc)
2964	{
2965	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2966	return VINF_EM_RAW_GUEST_TRAP;
2967	}
2968	# endif
2969	# else
2970	PGSTPD pPDSrc = NULL;
2971	const unsigned iPDSrc = 0;
2972	# endif
2973	int rc = VINF_SUCCESS;
2974
2975	/*
2976	* First check if the shadow pd is present.
2977	*/
2978	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2979	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2980	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2981	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2982	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2983	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2984	PX86PDPAE pPDDst;
2985	PX86PDEPAE pPdeDst;
2986
2987	# if PGM_GST_TYPE == PGM_TYPE_PROT
2988	/* AMD-V nested paging */
2989	X86PML4E Pml4eSrc;
2990	X86PDPE PdpeSrc;
2991	PX86PML4E pPml4eSrc = &Pml4eSrc;
2992
2993	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2994	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2995	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2996	# endif
2997
2998	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2999	if (rc != VINF_SUCCESS)
3000	{
3001	AssertRC(rc);
3002	return rc;
3003	}
3004	Assert(pPDDst);
3005	pPdeDst = &pPDDst->a[iPDDst];
3006	# endif
3007	if (!pPdeDst->n.u1Present)
3008	{
3009	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3010	AssertRC(rc);
3011	if (rc != VINF_SUCCESS)
3012	return rc;
3013	}
3014
3015	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3016	/* Check for dirty bit fault */
3017	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3018	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3019	Log(("PGMVerifyAccess: success (dirty)\n"));
3020	else
3021	{
3022	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3023	#else
3024	{
3025	GSTPDE PdeSrc;
3026	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3027	PdeSrc.n.u1Present = 1;
3028	PdeSrc.n.u1Write = 1;
3029	PdeSrc.n.u1Accessed = 1;
3030	PdeSrc.n.u1User = 1;
3031
3032	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3033	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3034	if (uErr & X86_TRAP_PF_US)
3035	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3036	else /* supervisor */
3037	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3038
3039	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3040	if (RT_SUCCESS(rc))
3041	{
3042	/* Page was successfully synced */
3043	Log2(("PGMVerifyAccess: success (sync)\n"));
3044	rc = VINF_SUCCESS;
3045	}
3046	else
3047	{
3048	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3049	return VINF_EM_RAW_GUEST_TRAP;
3050	}
3051	}
3052	return rc;
3053
3054	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3055
3056	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3057	return VERR_INTERNAL_ERROR;
3058	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3059	}
3060
3061
3062	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3063	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3064	/**
3065	* Figures out which kind of shadow page this guest PDE warrants.
3066	*
3067	* @returns Shadow page kind.
3068	* @param pPdeSrc The guest PDE in question.
3069	* @param cr4 The current guest cr4 value.
3070	*/
3071	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3072	{
3073	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3074	if (!pPdeSrc->n.u1Size)
3075	# else
3076	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3077	# endif
3078	return BTH_PGMPOOLKIND_PT_FOR_PT;
3079	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3080	//{
3081	// case 0:
3082	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3083	// case X86_PDE4M_RW:
3084	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3085	// case X86_PDE4M_US:
3086	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3087	// case X86_PDE4M_RW \| X86_PDE4M_US:
3088	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3089	# if 0
3090	// case X86_PDE4M_PAE_NX:
3091	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3092	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3093	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3094	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3095	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3096	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3097	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3098	# endif
3099	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3100	//}
3101	}
3102	# endif
3103	#endif
3104
3105	#undef MY_STAM_COUNTER_INC
3106	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3107
3108
3109	/**
3110	* Syncs the paging hierarchy starting at CR3.
3111	*
3112	* @returns VBox status code, no specials.
3113	* @param pVM The virtual machine.
3114	* @param cr0 Guest context CR0 register
3115	* @param cr3 Guest context CR3 register
3116	* @param cr4 Guest context CR4 register
3117	* @param fGlobal Including global page directories or not
3118	*/
3119	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3120	{
3121	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3122	fGlobal = true; /* Change this CR3 reload to be a global one. */
3123
3124	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3125	/*
3126	* Update page access handlers.
3127	* The virtual are always flushed, while the physical are only on demand.
3128	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3129	* have to look into that later because it will have a bad influence on the performance.
3130	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3131	* bird: Yes, but that won't work for aliases.
3132	*/
3133	/** @todo this MUST go away. See #1557. */
3134	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3135	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3136	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3137	#endif
3138
3139	#ifdef PGMPOOL_WITH_MONITORING
3140	int rc = pgmPoolSyncCR3(pVM);
3141	if (rc != VINF_SUCCESS)
3142	return rc;
3143	#endif
3144
3145	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3146	/** @todo check if this is really necessary */
3147	HWACCMFlushTLB(pVM);
3148	return VINF_SUCCESS;
3149
3150	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3151	/* No need to check all paging levels; we zero out the shadow parts when the guest modifies its tables. */
3152	return VINF_SUCCESS;
3153	#else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3154
3155	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3156	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3157
3158	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3159	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3160	bool fBigPagesSupported = true;
3161	# else
3162	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3163	# endif
3164
3165	/*
3166	* Get page directory addresses.
3167	*/
3168	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3169	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
3170	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64*/
3171	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3172	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
3173	# endif
3174	# endif
3175
3176	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3177	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3178	Assert(pPDSrc);
3179	# ifndef IN_RC
3180	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3181	# endif
3182	# endif
3183
3184	/*
3185	* Iterate the page directory.
3186	*/
3187	PPGMMAPPING pMapping;
3188	unsigned iPdNoMapping;
3189	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3190	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3191
3192	/* Only check mappings if they are supposed to be put into the shadow page table. */
3193	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3194	{
3195	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3196	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3197	}
3198	else
3199	{
3200	pMapping = 0;
3201	iPdNoMapping = ~0U;
3202	}
3203	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3204	for (uint64_t iPml4 = 0; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3205	{
3206	PPGMPOOLPAGE pShwPdpt = NULL;
3207	PX86PML4E pPml4eSrc, pPml4eDst;
3208	RTGCPHYS GCPhysPdptSrc;
3209
3210	pPml4eSrc = &pVM->pgm.s.CTXSUFF(pGstPaePML4)->a[iPml4];
3211	pPml4eDst = &pVM->pgm.s.CTXMID(p,PaePML4)->a[iPml4];
3212
3213	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3214	if (!pPml4eDst->n.u1Present)
3215	continue;
3216	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3217
3218	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3219
3220	/* Anything significant changed? */
3221	if ( pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present
3222	\|\| GCPhysPdptSrc != pShwPdpt->GCPhys)
3223	{
3224	/* Free it. */
3225	LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%RX64 %RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3226	(uint64_t)iPml4 << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
3227	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pHCShwAmd64CR3->idx, iPml4);
3228	pPml4eDst->u = 0;
3229	continue;
3230	}
3231	/* Force an attribute sync. */
3232	pPml4eDst->n.u1User = pPml4eSrc->n.u1User;
3233	pPml4eDst->n.u1Write = pPml4eSrc->n.u1Write;
3234	pPml4eDst->n.u1NoExecute = pPml4eSrc->n.u1NoExecute;
3235
3236	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3237	{
3238	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3239	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3240	for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
3241	{
3242	unsigned iPDSrc;
3243	# if PGM_GST_TYPE == PGM_TYPE_PAE
3244	X86PDPE PdpeSrc;
3245	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3246	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3247	PX86PDEPAE pPDEDst = &pPDPAE->a[iPdpt * X86_PG_PAE_ENTRIES];
3248	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3249
3250	if (pPDSrc == NULL)
3251	{
3252	/* PDPE not present */
3253	if (pPdptDst->a[iPdpt].n.u1Present)
3254	{
3255	LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
3256	/* for each page directory entry */
3257	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3258	{
3259	if ( pPDEDst[iPD].n.u1Present
3260	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3261	{
3262	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
3263	pPDEDst[iPD].u = 0;
3264	}
3265	}
3266	}
3267	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
3268	pPdptDst->a[iPdpt].n.u1Present = 0;
3269	continue;
3270	}
3271	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3272	PPGMPOOLPAGE pShwPde = NULL;
3273	RTGCPHYS GCPhysPdeSrc;
3274	PX86PDPE pPdpeDst;
3275	PX86PML4E pPml4eSrc;
3276	X86PDPE PdpeSrc;
3277	PX86PDPT pPdptDst;
3278	PX86PDPAE pPDDst;
3279	PX86PDEPAE pPDEDst;
3280	RTGCPTR GCPtr = (iPml4 << X86_PML4_SHIFT) \|\| (iPdpt << X86_PDPT_SHIFT);
3281	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3282
3283	int rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3284	if (rc != VINF_SUCCESS)
3285	{
3286	if (rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT)
3287	break; /* next PML4E */
3288
3289	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3290	continue; /* next PDPTE */
3291	}
3292	Assert(pPDDst);
3293	pPDEDst = &pPDDst->a[0];
3294	Assert(iPDSrc == 0);
3295
3296	pPdpeDst = &pPdptDst->a[iPdpt];
3297
3298	/* Fetch the pgm pool shadow descriptor if the shadow pdpte is present. */
3299	if (!pPdpeDst->n.u1Present)
3300	continue; /* next PDPTE */
3301
3302	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3303	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3304
3305	/* Anything significant changed? */
3306	if ( PdpeSrc.n.u1Present != pPdpeDst->n.u1Present
3307	\|\| GCPhysPdeSrc != pShwPde->GCPhys)
3308	{
3309	/* Free it. */
3310	LogFlow(("SyncCR3: Out-of-sync PDPE (GCPhys) GCPtr=%RX64 %RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
3311	((uint64_t)iPml4 << X86_PML4_SHIFT) + ((uint64_t)iPdpt << X86_PDPT_SHIFT), pShwPde->GCPhys, GCPhysPdeSrc, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
3312
3313	/* Mark it as not present if there's no hypervisor mapping present. (bit flipped at the top of Trap0eHandler) */
3314	Assert(!(pPdpeDst->u & PGM_PLXFLAGS_MAPPING));
3315	pgmPoolFreeByPage(pPool, pShwPde, pShwPde->idx, iPdpt);
3316	pPdpeDst->u = 0;
3317	continue; /* next guest PDPTE */
3318	}
3319	/* Force an attribute sync. */
3320	pPdpeDst->lm.u1User = PdpeSrc.lm.u1User;
3321	pPdpeDst->lm.u1Write = PdpeSrc.lm.u1Write;
3322	pPdpeDst->lm.u1NoExecute = PdpeSrc.lm.u1NoExecute;
3323	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3324
3325	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3326	{
3327	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
3328	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3329	{
3330	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3331	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
3332	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3333	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
3334	# endif
3335	GSTPDE PdeSrc = pPDSrc->a[iPD];
3336	if ( PdeSrc.n.u1Present
3337	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3338	{
3339	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3340	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3341	&& !defined(PGM_WITHOUT_MAPPINGS)
3342
3343	/*
3344	* Check for conflicts with GC mappings.
3345	*/
3346	# if PGM_GST_TYPE == PGM_TYPE_PAE
3347	if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
3348	# else
3349	if (iPD == iPdNoMapping)
3350	# endif
3351	{
3352	if (pVM->pgm.s.fMappingsFixed)
3353	{
3354	/* It's fixed, just skip the mapping. */
3355	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3356	iPD += cPTs - 1;
3357	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3358	pMapping = pMapping->CTX_SUFF(pNext);
3359	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3360	continue;
3361	}
3362	# ifdef IN_RING3
3363	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3364	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3365	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3366	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3367	# endif
3368	if (RT_FAILURE(rc))
3369	return rc;
3370
3371	/*
3372	* Update iPdNoMapping and pMapping.
3373	*/
3374	pMapping = pVM->pgm.s.pMappingsR3;
3375	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3376	pMapping = pMapping->pNextR3;
3377	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3378	# else
3379	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3380	return VINF_PGM_SYNC_CR3;
3381	# endif
3382	}
3383	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3384	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3385	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3386
3387	/*
3388	* Sync page directory entry.
3389	*
3390	* The current approach is to allocated the page table but to set
3391	* the entry to not-present and postpone the page table synching till
3392	* it's actually used.
3393	*/
3394	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3395	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3396	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3397	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3398	# else
3399	const unsigned iPdShw = iPD; NOREF(iPdShw);
3400	# endif
3401	{
3402	SHWPDE PdeDst = *pPDEDst;
3403	if (PdeDst.n.u1Present)
3404	{
3405	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3406	RTGCPHYS GCPhys;
3407	if ( !PdeSrc.b.u1Size
3408	\|\| !fBigPagesSupported)
3409	{
3410	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3411	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3412	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3413	GCPhys \|= i * (PAGE_SIZE / 2);
3414	# endif
3415	}
3416	else
3417	{
3418	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3419	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3420	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3421	GCPhys \|= i * X86_PAGE_2M_SIZE;
3422	# endif
3423	}
3424
3425	if ( pShwPage->GCPhys == GCPhys
3426	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3427	&& ( pShwPage->fCached
3428	\|\| ( !fGlobal
3429	&& ( false
3430	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3431	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3432	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3433	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3434	# else
3435	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3436	# endif
3437	\|\| ( !pShwPage->fSeenNonGlobal
3438	&& (cr4 & X86_CR4_PGE))
3439	# endif
3440	)
3441	)
3442	)
3443	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3444	\|\| ( fBigPagesSupported
3445	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3446	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3447	)
3448	)
3449	{
3450	# ifdef VBOX_WITH_STATISTICS
3451	if ( !fGlobal
3452	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3453	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3454	&& (cr4 & X86_CR4_PGE)) /* global 2/4MB page. */
3455	# else
3456	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3457	# endif
3458	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3459	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3460	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3461	else
3462	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3463	# endif /* VBOX_WITH_STATISTICS */
3464	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3465	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3466	//# ifdef PGMPOOL_WITH_CACHE
3467	// pgmPoolCacheUsed(pPool, pShwPage);
3468	//# endif
3469	}
3470	else
3471	{
3472	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3473	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPdShw);
3474	# else
3475	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3476	# endif
3477	pPDEDst->u = 0;
3478	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3479	}
3480	}
3481	else
3482	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3483	pPDEDst++;
3484	}
3485	}
3486	# if PGM_GST_TYPE == PGM_TYPE_PAE
3487	else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
3488	# else
3489	else if (iPD != iPdNoMapping)
3490	# endif
3491	{
3492	/*
3493	* Check if there is any page directory to mark not present here.
3494	*/
3495	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3496	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3497	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3498	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3499	# else
3500	const unsigned iPdShw = iPD; NOREF(iPdShw);
3501	# endif
3502	{
3503	if (pPDEDst->n.u1Present)
3504	{
3505	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3506	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), pShwPde->idx, iPdShw);
3507	# else
3508	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
3509	# endif
3510	pPDEDst->u = 0;
3511	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3512	}
3513	pPDEDst++;
3514	}
3515	}
3516	else
3517	{
3518	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3519	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3520	&& !defined(PGM_WITHOUT_MAPPINGS)
3521
3522	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3523
3524	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3525	if (pVM->pgm.s.fMappingsFixed)
3526	{
3527	/* It's fixed, just skip the mapping. */
3528	pMapping = pMapping->CTX_SUFF(pNext);
3529	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3530	}
3531	else
3532	{
3533	/*
3534	* Check for conflicts for subsequent pagetables
3535	* and advance to the next mapping.
3536	*/
3537	iPdNoMapping = ~0U;
3538	unsigned iPT = cPTs;
3539	while (iPT-- > 1)
3540	{
3541	if ( pPDSrc->a[iPD + iPT].n.u1Present
3542	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3543	{
3544	# ifdef IN_RING3
3545	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3546	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3547	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3548	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3549	# endif
3550	if (RT_FAILURE(rc))
3551	return rc;
3552
3553	/*
3554	* Update iPdNoMapping and pMapping.
3555	*/
3556	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3557	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3558	pMapping = pMapping->CTX_SUFF(pNext);
3559	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3560	break;
3561	# else
3562	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3563	return VINF_PGM_SYNC_CR3;
3564	# endif
3565	}
3566	}
3567	if (iPdNoMapping == ~0U && pMapping)
3568	{
3569	pMapping = pMapping->CTX_SUFF(pNext);
3570	if (pMapping)
3571	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3572	}
3573	}
3574
3575	/* advance. */
3576	iPD += cPTs - 1;
3577	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3578	# if PGM_GST_TYPE != PGM_SHW_TYPE
3579	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3580	# endif
3581	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3582	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3583	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3584	}
3585
3586	} /* for iPD */
3587	} /* for each PDPTE (PAE) */
3588	} /* for each page map level 4 entry (amd64) */
3589	return VINF_SUCCESS;
3590
3591	# else /* guest real and protected mode */
3592	return VINF_SUCCESS;
3593	# endif
3594	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
3595	}
3596
3597
3598
3599
3600	#ifdef VBOX_STRICT
3601	#ifdef IN_RC
3602	# undef AssertMsgFailed
3603	# define AssertMsgFailed Log
3604	#endif
3605	#ifdef IN_RING3
3606	# include <VBox/dbgf.h>
3607
3608	/**
3609	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3610	*
3611	* @returns VBox status code (VINF_SUCCESS).
3612	* @param pVM The VM handle.
3613	* @param cr3 The root of the hierarchy.
3614	* @param crr The cr4, only PAE and PSE is currently used.
3615	* @param fLongMode Set if long mode, false if not long mode.
3616	* @param cMaxDepth Number of levels to dump.
3617	* @param pHlp Pointer to the output functions.
3618	*/
3619	__BEGIN_DECLS
3620	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3621	__END_DECLS
3622
3623	#endif
3624
3625	/**
3626	* Checks that the shadow page table is in sync with the guest one.
3627	*
3628	* @returns The number of errors.
3629	* @param pVM The virtual machine.
3630	* @param cr3 Guest context CR3 register
3631	* @param cr4 Guest context CR4 register
3632	* @param GCPtr Where to start. Defaults to 0.
3633	* @param cb How much to check. Defaults to everything.
3634	*/
3635	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3636	{
3637	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3638	return 0;
3639	#else
3640	unsigned cErrors = 0;
3641
3642	#if PGM_GST_TYPE == PGM_TYPE_PAE
3643	/** @todo currently broken; crashes below somewhere */
3644	AssertFailed();
3645	#endif
3646
3647	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3648	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3649	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3650
3651	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3652	bool fBigPagesSupported = true;
3653	# else
3654	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3655	# endif
3656	PPGM pPGM = &pVM->pgm.s;
3657	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3658	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3659	# ifndef IN_RING0
3660	RTHCPHYS HCPhys; /* general usage. */
3661	# endif
3662	int rc;
3663
3664	/*
3665	* Check that the Guest CR3 and all its mappings are correct.
3666	*/
3667	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3668	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3669	false);
3670	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3671	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3672	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGuestPDRC, NULL, &HCPhysShw);
3673	# else
3674	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePDPTRC, NULL, &HCPhysShw);
3675	# endif
3676	AssertRCReturn(rc, 1);
3677	HCPhys = NIL_RTHCPHYS;
3678	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3679	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3680	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3681	RTGCPHYS GCPhys;
3682	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGuestPDR3, &GCPhys);
3683	AssertRCReturn(rc, 1);
3684	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3685	# endif
3686	#endif /* !IN_RING0 */
3687
3688	/*
3689	* Get and check the Shadow CR3.
3690	*/
3691	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3692	unsigned cPDEs = X86_PG_ENTRIES;
3693	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3694	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3695	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3696	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3697	# else
3698	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3699	# endif
3700	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3701	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3702	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3703	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3704	# endif
3705	if (cb != ~(RTGCPTR)0)
3706	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3707
3708	/** @todo call the other two PGMAssert() functions. /
3709
3710	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3711	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3712	# endif
3713
3714	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3715	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3716
3717	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3718	{
3719	PPGMPOOLPAGE pShwPdpt = NULL;
3720	PX86PML4E pPml4eSrc;
3721	PX86PML4E pPml4eDst;
3722	RTGCPHYS GCPhysPdptSrc;
3723
3724	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3725	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3726
3727	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3728	if (!pPml4eDst->n.u1Present)
3729	{
3730	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3731	continue;
3732	}
3733
3734	# if PGM_GST_TYPE == PGM_TYPE_PAE
3735	/* not correct to call pgmPoolGetPage */
3736	AssertFailed();
3737	# endif
3738	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3739	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3740
3741	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3742	{
3743	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3744	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3745	cErrors++;
3746	continue;
3747	}
3748
3749	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3750	{
3751	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3752	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3753	cErrors++;
3754	continue;
3755	}
3756
3757	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3758	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3759	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3760	{
3761	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3762	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3763	cErrors++;
3764	continue;
3765	}
3766	# else
3767	{
3768	# endif
3769
3770	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3771	/*
3772	* Check the PDPTEs too.
3773	*/
3774	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3775
3776	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3777	{
3778	unsigned iPDSrc;
3779	PPGMPOOLPAGE pShwPde = NULL;
3780	PX86PDPE pPdpeDst;
3781	RTGCPHYS GCPhysPdeSrc;
3782	# if PGM_GST_TYPE == PGM_TYPE_PAE
3783	X86PDPE PdpeSrc;
3784	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3785	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
3786	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3787	# else
3788	PX86PML4E pPml4eSrc;
3789	X86PDPE PdpeSrc;
3790	PX86PDPT pPdptDst;
3791	PX86PDPAE pPDDst;
3792	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3793
3794	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3795	if (rc != VINF_SUCCESS)
3796	{
3797	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3798	GCPtr += 512 * _2M;
3799	continue; /* next PDPTE */
3800	}
3801	Assert(pPDDst);
3802	# endif
3803	Assert(iPDSrc == 0);
3804
3805	pPdpeDst = &pPdptDst->a[iPdpt];
3806
3807	if (!pPdpeDst->n.u1Present)
3808	{
3809	GCPtr += 512 * _2M;
3810	continue; /* next PDPTE */
3811	}
3812
3813	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3814	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3815
3816	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3817	{
3818	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3819	GCPtr += 512 * _2M;
3820	cErrors++;
3821	continue;
3822	}
3823
3824	if (GCPhysPdeSrc != pShwPde->GCPhys)
3825	{
3826	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3827	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3828	# else
3829	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3830	# endif
3831	GCPtr += 512 * _2M;
3832	cErrors++;
3833	continue;
3834	}
3835
3836	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3837	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3838	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3839	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3840	{
3841	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3842	GCPtr += 512 * _2M;
3843	cErrors++;
3844	continue;
3845	}
3846	# endif
3847
3848	# else
3849	{
3850	# endif
3851	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3852	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3853	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3854	PCX86PD pPDDst = pPGM->CTXMID(p,32BitPD);
3855	# else
3856	PCX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
3857	# endif
3858	# endif
3859	/*
3860	* Iterate the shadow page directory.
3861	*/
3862	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3863	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3864
3865	for (;
3866	iPDDst < cPDEs;
3867	iPDDst++, GCPtr += cIncrement)
3868	{
3869	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3870	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3871	{
3872	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3873	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3874	{
3875	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3876	cErrors++;
3877	continue;
3878	}
3879	}
3880	else if ( (PdeDst.u & X86_PDE_P)
3881	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3882	)
3883	{
3884	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3885	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3886	if (!pPoolPage)
3887	{
3888	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3889	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3890	cErrors++;
3891	continue;
3892	}
3893	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3894
3895	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3896	{
3897	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3898	GCPtr, (uint64_t)PdeDst.u));
3899	cErrors++;
3900	}
3901
3902	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3903	{
3904	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3905	GCPtr, (uint64_t)PdeDst.u));
3906	cErrors++;
3907	}
3908
3909	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3910	if (!PdeSrc.n.u1Present)
3911	{
3912	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3913	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3914	cErrors++;
3915	continue;
3916	}
3917
3918	if ( !PdeSrc.b.u1Size
3919	\|\| !fBigPagesSupported)
3920	{
3921	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3922	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3923	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3924	# endif
3925	}
3926	else
3927	{
3928	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3929	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3930	{
3931	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3932	GCPtr, (uint64_t)PdeSrc.u));
3933	cErrors++;
3934	continue;
3935	}
3936	# endif
3937	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3938	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3939	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3940	# endif
3941	}
3942
3943	if ( pPoolPage->enmKind
3944	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3945	{
3946	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3947	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3948	cErrors++;
3949	}
3950
3951	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3952	if (!pPhysPage)
3953	{
3954	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3955	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3956	cErrors++;
3957	continue;
3958	}
3959
3960	if (GCPhysGst != pPoolPage->GCPhys)
3961	{
3962	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3963	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3964	cErrors++;
3965	continue;
3966	}
3967
3968	if ( !PdeSrc.b.u1Size
3969	\|\| !fBigPagesSupported)
3970	{
3971	/*
3972	* Page Table.
3973	*/
3974	const GSTPT *pPTSrc;
3975	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3976	if (RT_FAILURE(rc))
3977	{
3978	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3979	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3980	cErrors++;
3981	continue;
3982	}
3983	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3984	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3985	{
3986	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3987	// (This problem will go away when/if we shadow multiple CR3s.)
3988	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3989	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3990	cErrors++;
3991	continue;
3992	}
3993	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3994	{
3995	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3996	GCPtr, (uint64_t)PdeDst.u));
3997	cErrors++;
3998	continue;
3999	}
4000
4001	/* iterate the page table. */
4002	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4003	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4004	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4005	# else
4006	const unsigned offPTSrc = 0;
4007	# endif
4008	for (unsigned iPT = 0, off = 0;
4009	iPT < RT_ELEMENTS(pPTDst->a);
4010	iPT++, off += PAGE_SIZE)
4011	{
4012	const SHWPTE PteDst = pPTDst->a[iPT];
4013
4014	/* skip not-present entries. */
4015	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4016	continue;
4017	Assert(PteDst.n.u1Present);
4018
4019	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4020	if (!PteSrc.n.u1Present)
4021	{
4022	# ifdef IN_RING3
4023	PGMAssertHandlerAndFlagsInSync(pVM);
4024	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4025	# endif
4026	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4027	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4028	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4029	cErrors++;
4030	continue;
4031	}
4032
4033	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4034	# if 1 /** @todo sync accessed bit properly... */
4035	fIgnoreFlags \|= X86_PTE_A;
4036	# endif
4037
4038	/* match the physical addresses */
4039	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4040	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4041
4042	# ifdef IN_RING3
4043	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4044	if (RT_FAILURE(rc))
4045	{
4046	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4047	{
4048	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4050	cErrors++;
4051	continue;
4052	}
4053	}
4054	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4055	{
4056	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4057	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4058	cErrors++;
4059	continue;
4060	}
4061	# endif
4062
4063	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4064	if (!pPhysPage)
4065	{
4066	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4067	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4068	{
4069	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4070	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4071	cErrors++;
4072	continue;
4073	}
4074	# endif
4075	if (PteDst.n.u1Write)
4076	{
4077	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4078	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4079	cErrors++;
4080	}
4081	fIgnoreFlags \|= X86_PTE_RW;
4082	}
4083	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4084	{
4085	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4086	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4087	cErrors++;
4088	continue;
4089	}
4090
4091	/* flags */
4092	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4093	{
4094	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4095	{
4096	if (PteDst.n.u1Write)
4097	{
4098	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4100	cErrors++;
4101	continue;
4102	}
4103	fIgnoreFlags \|= X86_PTE_RW;
4104	}
4105	else
4106	{
4107	if (PteDst.n.u1Present)
4108	{
4109	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4110	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4111	cErrors++;
4112	continue;
4113	}
4114	fIgnoreFlags \|= X86_PTE_P;
4115	}
4116	}
4117	else
4118	{
4119	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4120	{
4121	if (PteDst.n.u1Write)
4122	{
4123	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4125	cErrors++;
4126	continue;
4127	}
4128	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4129	{
4130	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4131	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4132	cErrors++;
4133	continue;
4134	}
4135	if (PteDst.n.u1Dirty)
4136	{
4137	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4138	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4139	cErrors++;
4140	}
4141	# if 0 /** @todo sync access bit properly... */
4142	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4143	{
4144	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4145	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4146	cErrors++;
4147	}
4148	fIgnoreFlags \|= X86_PTE_RW;
4149	# else
4150	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4151	# endif
4152	}
4153	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4154	{
4155	/* access bit emulation (not implemented). */
4156	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4157	{
4158	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4159	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4160	cErrors++;
4161	continue;
4162	}
4163	if (!PteDst.n.u1Accessed)
4164	{
4165	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4166	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4167	cErrors++;
4168	}
4169	fIgnoreFlags \|= X86_PTE_P;
4170	}
4171	# ifdef DEBUG_sandervl
4172	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4173	# endif
4174	}
4175
4176	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4177	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4178	)
4179	{
4180	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4181	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4182	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4183	cErrors++;
4184	continue;
4185	}
4186	} /* foreach PTE */
4187	}
4188	else
4189	{
4190	/*
4191	* Big Page.
4192	*/
4193	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4194	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4195	{
4196	if (PdeDst.n.u1Write)
4197	{
4198	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4199	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4200	cErrors++;
4201	continue;
4202	}
4203	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4204	{
4205	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4206	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4207	cErrors++;
4208	continue;
4209	}
4210	# if 0 /** @todo sync access bit properly... */
4211	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4212	{
4213	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4214	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4215	cErrors++;
4216	}
4217	fIgnoreFlags \|= X86_PTE_RW;
4218	# else
4219	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4220	# endif
4221	}
4222	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4223	{
4224	/* access bit emulation (not implemented). */
4225	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4226	{
4227	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4228	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4229	cErrors++;
4230	continue;
4231	}
4232	if (!PdeDst.n.u1Accessed)
4233	{
4234	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4235	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4236	cErrors++;
4237	}
4238	fIgnoreFlags \|= X86_PTE_P;
4239	}
4240
4241	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4242	{
4243	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4244	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4245	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4246	cErrors++;
4247	}
4248
4249	/* iterate the page table. */
4250	for (unsigned iPT = 0, off = 0;
4251	iPT < RT_ELEMENTS(pPTDst->a);
4252	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4253	{
4254	const SHWPTE PteDst = pPTDst->a[iPT];
4255
4256	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4257	{
4258	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4259	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4260	cErrors++;
4261	}
4262
4263	/* skip not-present entries. */
4264	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4265	continue;
4266
4267	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4268
4269	/* match the physical addresses */
4270	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4271
4272	# ifdef IN_RING3
4273	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4274	if (RT_FAILURE(rc))
4275	{
4276	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4277	{
4278	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4279	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4280	cErrors++;
4281	}
4282	}
4283	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4284	{
4285	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4286	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4287	cErrors++;
4288	continue;
4289	}
4290	# endif
4291	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4292	if (!pPhysPage)
4293	{
4294	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4295	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4296	{
4297	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4298	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4299	cErrors++;
4300	continue;
4301	}
4302	# endif
4303	if (PteDst.n.u1Write)
4304	{
4305	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4306	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4307	cErrors++;
4308	}
4309	fIgnoreFlags \|= X86_PTE_RW;
4310	}
4311	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4312	{
4313	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4314	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4315	cErrors++;
4316	continue;
4317	}
4318
4319	/* flags */
4320	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4321	{
4322	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4323	{
4324	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4325	{
4326	if (PteDst.n.u1Write)
4327	{
4328	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4329	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4330	cErrors++;
4331	continue;
4332	}
4333	fIgnoreFlags \|= X86_PTE_RW;
4334	}
4335	}
4336	else
4337	{
4338	if (PteDst.n.u1Present)
4339	{
4340	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4341	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4342	cErrors++;
4343	continue;
4344	}
4345	fIgnoreFlags \|= X86_PTE_P;
4346	}
4347	}
4348
4349	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4350	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4351	)
4352	{
4353	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4354	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4355	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4356	cErrors++;
4357	continue;
4358	}
4359	} /* for each PTE */
4360	}
4361	}
4362	/* not present */
4363
4364	} /* for each PDE */
4365
4366	} /* for each PDPTE */
4367
4368	} /* for each PML4E */
4369
4370	# ifdef DEBUG
4371	if (cErrors)
4372	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4373	# endif
4374
4375	#endif
4376	return cErrors;
4377
4378	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4379	}
4380	#endif /* VBOX_STRICT */
4381

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 14094

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