PGMAllBth.h@ 14251

Last change on this file since 14251 was 14154, checked in by vboxsync, 16 years ago
PGM: pGuestPD* -> pGst32BitPd*
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 187.7 KB

Line
1	/* $Id: PGMAllBth.h 14154 2008-11-12 23:34:50Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
148	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
149
150	# if PGM_GST_TYPE == PGM_TYPE_PAE
151	/* Did we mark the PDPT as not present in SyncCR3? */
152	unsigned iPdpt = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
153	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
154	if (!pPdptDst->a[iPdpt].n.u1Present)
155	pPdptDst->a[iPdpt].n.u1Present = 1;
156	# endif /* GST PAE */
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
159	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
160	PX86PDPAE pPDDst;
161	# if PGM_GST_TYPE == PGM_TYPE_PROT
162	/* AMD-V nested paging */
163	X86PML4E Pml4eSrc;
164	X86PDPE PdpeSrc;
165	PX86PML4E pPml4eSrc = &Pml4eSrc;
166
167	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
168	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
169	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
170	# endif
171
172	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
173	if (rc != VINF_SUCCESS)
174	{
175	AssertRC(rc);
176	return rc;
177	}
178	Assert(pPDDst);
179
180	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
181	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
182	PEPTPD pPDDst;
183
184	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
185	if (rc != VINF_SUCCESS)
186	{
187	AssertRC(rc);
188	return rc;
189	}
190	Assert(pPDDst);
191	# endif
192
193	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
194	/*
195	* If we successfully correct the write protection fault due to dirty bit
196	* tracking, or this page fault is a genuine one, then return immediately.
197	*/
198	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
199	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
200	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
201	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
202	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
203	{
204	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
205	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
206	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
207	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
208	}
209
210	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
211	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
212
213	/*
214	* A common case is the not-present error caused by lazy page table syncing.
215	*
216	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
217	* so we can safely assume that the shadow PT is present when calling SyncPage later.
218	*
219	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
220	* of mapping conflict and defer to SyncCR3 in R3.
221	* (Again, we do NOT support access handlers for non-present guest pages.)
222	*
223	*/
224	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
225	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
226	# else
227	GSTPDE PdeSrc;
228	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
229	PdeSrc.n.u1Present = 1;
230	PdeSrc.n.u1Write = 1;
231	PdeSrc.n.u1Accessed = 1;
232	PdeSrc.n.u1User = 1;
233	# endif
234	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
235	&& !pPDDst->a[iPDDst].n.u1Present
236	&& PdeSrc.n.u1Present
237	)
238
239	{
240	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
241	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
242	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
243	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
244	if (RT_SUCCESS(rc))
245	{
246	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
247	return rc;
248	}
249	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
250	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
251	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
252	return VINF_PGM_SYNC_CR3;
253	}
254
255	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
256	/*
257	* Check if this address is within any of our mappings.
258	*
259	* This is very fast and it's gonna save us a bit of effort below and prevent
260	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
261	* (BTW, it's impossible to have physical access handlers in a mapping.)
262	*/
263	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
264	{
265	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
266	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
267	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
268	{
269	if (pvFault < pMapping->GCPtr)
270	break;
271	if (pvFault - pMapping->GCPtr < pMapping->cb)
272	{
273	/*
274	* The first thing we check is if we've got an undetected conflict.
275	*/
276	if (!pVM->pgm.s.fMappingsFixed)
277	{
278	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
279	while (iPT-- > 0)
280	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
281	{
282	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
283	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
284	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
285	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
286	return VINF_PGM_SYNC_CR3;
287	}
288	}
289
290	/*
291	* Check if the fault address is in a virtual page access handler range.
292	*/
293	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
294	if ( pCur
295	&& pvFault - pCur->Core.Key < pCur->cb
296	&& uErr & X86_TRAP_PF_RW)
297	{
298	# ifdef IN_RC
299	STAM_PROFILE_START(&pCur->Stat, h);
300	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
301	STAM_PROFILE_STOP(&pCur->Stat, h);
302	# else
303	AssertFailed();
304	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
305	# endif
306	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
307	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
308	return rc;
309	}
310
311	/*
312	* Pretend we're not here and let the guest handle the trap.
313	*/
314	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
315	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
316	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
317	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
318	return VINF_EM_RAW_GUEST_TRAP;
319	}
320	}
321	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
322	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
323	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
324
325	/*
326	* Check if this fault address is flagged for special treatment,
327	* which means we'll have to figure out the physical address and
328	* check flags associated with it.
329	*
330	* ASSUME that we can limit any special access handling to pages
331	* in page tables which the guest believes to be present.
332	*/
333	if (PdeSrc.n.u1Present)
334	{
335	RTGCPHYS GCPhys = NIL_RTGCPHYS;
336
337	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
338	# if PGM_GST_TYPE == PGM_TYPE_AMD64
339	bool fBigPagesSupported = true;
340	# else
341	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
342	# endif
343	if ( PdeSrc.b.u1Size
344	&& fBigPagesSupported)
345	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
346	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
347	else
348	{
349	PGSTPT pPTSrc;
350	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
351	if (RT_SUCCESS(rc))
352	{
353	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
354	if (pPTSrc->a[iPTESrc].n.u1Present)
355	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
356	}
357	}
358	# else
359	/* No paging so the fault address is the physical address */
360	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
361	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
362
363	/*
364	* If we have a GC address we'll check if it has any flags set.
365	*/
366	if (GCPhys != NIL_RTGCPHYS)
367	{
368	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
369
370	PPGMPAGE pPage;
371	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
372	if (RT_SUCCESS(rc))
373	{
374	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
375	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
376	{
377	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
378	{
379	/*
380	* Physical page access handler.
381	*/
382	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
383	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
384	if (pCur)
385	{
386	# ifdef PGM_SYNC_N_PAGES
387	/*
388	* If the region is write protected and we got a page not present fault, then sync
389	* the pages. If the fault was caused by a read, then restart the instruction.
390	* In case of write access continue to the GC write handler.
391	*
392	* ASSUMES that there is only one handler per page or that they have similar write properties.
393	*/
394	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
395	&& !(uErr & X86_TRAP_PF_P))
396	{
397	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
398	if ( RT_FAILURE(rc)
399	\|\| !(uErr & X86_TRAP_PF_RW)
400	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
401	{
402	AssertRC(rc);
403	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
404	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
405	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
406	return rc;
407	}
408	}
409	# endif
410
411	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
412	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
413	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
414
415	# if defined(IN_RC) \|\| defined(IN_RING0)
416	if (pCur->CTX_SUFF(pfnHandler))
417	{
418	STAM_PROFILE_START(&pCur->Stat, h);
419	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
420	STAM_PROFILE_STOP(&pCur->Stat, h);
421	}
422	else
423	# endif
424	rc = VINF_EM_RAW_EMULATE_INSTR;
425	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
426	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
427	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
428	return rc;
429	}
430	}
431	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
432	else
433	{
434	# ifdef PGM_SYNC_N_PAGES
435	/*
436	* If the region is write protected and we got a page not present fault, then sync
437	* the pages. If the fault was caused by a read, then restart the instruction.
438	* In case of write access continue to the GC write handler.
439	*/
440	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
441	&& !(uErr & X86_TRAP_PF_P))
442	{
443	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
444	if ( RT_FAILURE(rc)
445	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
446	\|\| !(uErr & X86_TRAP_PF_RW))
447	{
448	AssertRC(rc);
449	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
450	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
451	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
452	return rc;
453	}
454	}
455	# endif
456	/*
457	* Ok, it's an virtual page access handler.
458	*
459	* Since it's faster to search by address, we'll do that first
460	* and then retry by GCPhys if that fails.
461	*/
462	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
463	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
464	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
465	*/
466	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
467	if (pCur)
468	{
469	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
470	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
471	\|\| !(uErr & X86_TRAP_PF_P)
472	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
473	("Unexpected trap for virtual handler: %RGv (phys=%RGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
474
475	if ( pvFault - pCur->Core.Key < pCur->cb
476	&& ( uErr & X86_TRAP_PF_RW
477	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
478	{
479	# ifdef IN_RC
480	STAM_PROFILE_START(&pCur->Stat, h);
481	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
482	STAM_PROFILE_STOP(&pCur->Stat, h);
483	# else
484	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
485	# endif
486	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
487	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
488	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
489	return rc;
490	}
491	/* Unhandled part of a monitored page */
492	}
493	else
494	{
495	/* Check by physical address. */
496	PPGMVIRTHANDLER pCur;
497	unsigned iPage;
498	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
499	&pCur, &iPage);
500	Assert(RT_SUCCESS(rc) \|\| !pCur);
501	if ( pCur
502	&& ( uErr & X86_TRAP_PF_RW
503	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
504	{
505	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
506	# ifdef IN_RC
507	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
508	Assert(off < pCur->cb);
509	STAM_PROFILE_START(&pCur->Stat, h);
510	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
511	STAM_PROFILE_STOP(&pCur->Stat, h);
512	# else
513	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
514	# endif
515	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
517	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
518	return rc;
519	}
520	}
521	}
522	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
523
524	/*
525	* There is a handled area of the page, but this fault doesn't belong to it.
526	* We must emulate the instruction.
527	*
528	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
529	* we first check if this was a page-not-present fault for a page with only
530	* write access handlers. Restart the instruction if it wasn't a write access.
531	*/
532	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
533
534	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
535	&& !(uErr & X86_TRAP_PF_P))
536	{
537	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
538	if ( RT_FAILURE(rc)
539	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
540	\|\| !(uErr & X86_TRAP_PF_RW))
541	{
542	AssertRC(rc);
543	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
544	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
545	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
546	return rc;
547	}
548	}
549
550	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
551	* It's writing to an unhandled part of the LDT page several million times.
552	*/
553	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
554	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
555	rc, pPage->HCPhys,
556	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
557	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
558	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
559	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
560	return rc;
561	} /* if any kind of handler */
562
563	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
564	if (uErr & X86_TRAP_PF_P)
565	{
566	/*
567	* The page isn't marked, but it might still be monitored by a virtual page access handler.
568	* (ASSUMES no temporary disabling of virtual handlers.)
569	*/
570	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
571	* we should correct both the shadow page table and physical memory flags, and not only check for
572	* accesses within the handler region but for access to pages with virtual handlers. */
573	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
574	if (pCur)
575	{
576	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
577	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
578	\|\| !(uErr & X86_TRAP_PF_P)
579	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
580	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
581
582	if ( pvFault - pCur->Core.Key < pCur->cb
583	&& ( uErr & X86_TRAP_PF_RW
584	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
585	{
586	# ifdef IN_RC
587	STAM_PROFILE_START(&pCur->Stat, h);
588	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
589	STAM_PROFILE_STOP(&pCur->Stat, h);
590	# else
591	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
592	# endif
593	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
594	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
595	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
596	return rc;
597	}
598	}
599	}
600	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
601	}
602	else
603	{
604	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
605	* back to the recompiler to emulate the instruction.
606	*/
607	LogFlow(("pgmPhysGetPageEx %RGp failed with %Rrc\n", GCPhys, rc));
608	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
609	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
610	return VINF_EM_RAW_EMULATE_INSTR;
611	}
612
613	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
614
615	# ifdef PGM_OUT_OF_SYNC_IN_GC
616	/*
617	* We are here only if page is present in Guest page tables and trap is not handled
618	* by our handlers.
619	* Check it for page out-of-sync situation.
620	*/
621	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
622
623	if (!(uErr & X86_TRAP_PF_P))
624	{
625	/*
626	* Page is not present in our page tables.
627	* Try to sync it!
628	* BTW, fPageShw is invalid in this branch!
629	*/
630	if (uErr & X86_TRAP_PF_US)
631	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
632	else /* supervisor */
633	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
634
635	# if defined(LOG_ENABLED) && !defined(IN_RING0)
636	RTGCPHYS GCPhys;
637	uint64_t fPageGst;
638	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
639	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
640	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
641	# endif /* LOG_ENABLED */
642
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
644	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
645	{
646	uint64_t fPageGst;
647	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
648	if ( RT_SUCCESS(rc)
649	&& !(fPageGst & X86_PTE_US))
650	{
651	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
652	if ( pvFault == (RTGCPTR)pRegFrame->eip
653	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
654	# ifdef CSAM_DETECT_NEW_CODE_PAGES
655	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
656	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
657	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
658	)
659	{
660	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
661	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
662	if (rc != VINF_SUCCESS)
663	{
664	/*
665	* CSAM needs to perform a job in ring 3.
666	*
667	* Sync the page before going to the host context; otherwise we'll end up in a loop if
668	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
669	*/
670	LogFlow(("CSAM ring 3 job\n"));
671	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
672	AssertRC(rc2);
673
674	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
675	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
676	return rc;
677	}
678	}
679	# ifdef CSAM_DETECT_NEW_CODE_PAGES
680	else if ( uErr == X86_TRAP_PF_RW
681	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
682	&& pRegFrame->ecx < 0x10000)
683	{
684	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
685	* to detect loading of new code pages.
686	*/
687
688	/*
689	* Decode the instruction.
690	*/
691	RTGCPTR PC;
692	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
693	if (rc == VINF_SUCCESS)
694	{
695	DISCPUSTATE Cpu;
696	uint32_t cbOp;
697	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
698
699	/* For now we'll restrict this to rep movsw/d instructions */
700	if ( rc == VINF_SUCCESS
701	&& Cpu.pCurInstr->opcode == OP_MOVSWD
702	&& (Cpu.prefix & PREFIX_REP))
703	{
704	CSAMMarkPossibleCodePage(pVM, pvFault);
705	}
706	}
707	}
708	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
709
710	/*
711	* Mark this page as safe.
712	*/
713	/** @todo not correct for pages that contain both code and data!! */
714	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
715	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
716	}
717	}
718	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
719	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
720	if (RT_SUCCESS(rc))
721	{
722	/* The page was successfully synced, return to the guest. */
723	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
724	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
725	return VINF_SUCCESS;
726	}
727	}
728	else
729	{
730	/*
731	* A side effect of not flushing global PDEs are out of sync pages due
732	* to physical monitored regions, that are no longer valid.
733	* Assume for now it only applies to the read/write flag
734	*/
735	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
736	{
737	if (uErr & X86_TRAP_PF_US)
738	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
739	else /* supervisor */
740	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
741
742
743	/*
744	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
745	*/
746	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
747	if (RT_SUCCESS(rc))
748	{
749	/*
750	* Page was successfully synced, return to guest.
751	*/
752	# ifdef VBOX_STRICT
753	RTGCPHYS GCPhys;
754	uint64_t fPageGst;
755	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
756	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
757	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
758
759	uint64_t fPageShw;
760	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
761	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
762	# endif /* VBOX_STRICT */
763	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
764	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
765	return VINF_SUCCESS;
766	}
767
768	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
769	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
770	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
771	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
772	{
773	uint64_t fPageGst;
774	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
775	if ( RT_SUCCESS(rc)
776	&& !(fPageGst & X86_PTE_RW))
777	{
778	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
779	if (RT_SUCCESS(rc))
780	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
781	else
782	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
783	return rc;
784	}
785	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
786	}
787	}
788
789	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
790	# ifdef VBOX_STRICT
791	/*
792	* Check for VMM page flags vs. Guest page flags consistency.
793	* Currently only for debug purposes.
794	*/
795	if (RT_SUCCESS(rc))
796	{
797	/* Get guest page flags. */
798	uint64_t fPageGst;
799	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
800	if (RT_SUCCESS(rc))
801	{
802	uint64_t fPageShw;
803	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
804
805	/*
806	* Compare page flags.
807	* Note: we have AVL, A, D bits desynched.
808	*/
809	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
810	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
811	}
812	else
813	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
814	}
815	else
816	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
817	# endif /* VBOX_STRICT */
818	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
819	}
820	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
821	# endif /* PGM_OUT_OF_SYNC_IN_GC */
822	}
823	else
824	{
825	/*
826	* Page not present in Guest OS or invalid page table address.
827	* This is potential virtual page access handler food.
828	*
829	* For the present we'll say that our access handlers don't
830	* work for this case - we've already discarded the page table
831	* not present case which is identical to this.
832	*
833	* When we perchance find we need this, we will probably have AVL
834	* trees (offset based) to operate on and we can measure their speed
835	* agains mapping a page table and probably rearrange this handling
836	* a bit. (Like, searching virtual ranges before checking the
837	* physical address.)
838	*/
839	}
840	}
841
842
843	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
844	/*
845	* Conclusion, this is a guest trap.
846	*/
847	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
848	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
849	return VINF_EM_RAW_GUEST_TRAP;
850	# else
851	/* present, but not a monitored page; perhaps the guest is probing physical memory */
852	return VINF_EM_RAW_EMULATE_INSTR;
853	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
854
855
856	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
857
858	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
859	return VERR_INTERNAL_ERROR;
860	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
861	}
862	#endif /* !IN_RING3 */
863
864
865	/**
866	* Emulation of the invlpg instruction.
867	*
868	*
869	* @returns VBox status code.
870	*
871	* @param pVM VM handle.
872	* @param GCPtrPage Page to invalidate.
873	*
874	* @remark ASSUMES that the guest is updating before invalidating. This order
875	* isn't required by the CPU, so this is speculative and could cause
876	* trouble.
877	*
878	* @todo Flush page or page directory only if necessary!
879	* @todo Add a #define for simply invalidating the page.
880	*/
881	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
882	{
883	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
884	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
885	&& PGM_SHW_TYPE != PGM_TYPE_EPT
886	int rc;
887
888	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
889	/*
890	* Get the shadow PD entry and skip out if this PD isn't present.
891	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
892	*/
893	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
894	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
895	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
896
897	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
898	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
899	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
900
901	/* If the shadow PDPE isn't present, then skip the invalidate. */
902	if (!pPdptDst->a[iPdpt].n.u1Present)
903	{
904	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
905	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
906	return VINF_SUCCESS;
907	}
908
909	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - pool index only atm! /;
910	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
911
912	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
913	/* PML4 */
914	AssertReturn(pVM->pgm.s.pShwPaePml4R3, VERR_INTERNAL_ERROR);
915
916	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
917	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
918	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
919	PX86PDPAE pPDDst;
920	PX86PDPT pPdptDst;
921	PX86PML4E pPml4eDst;
922	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
923	if (rc != VINF_SUCCESS)
924	{
925	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
926	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
927	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
928	PGM_INVL_GUEST_TLBS();
929	return VINF_SUCCESS;
930	}
931	Assert(pPDDst);
932
933	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
934	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
935
936	if (!pPdpeDst->n.u1Present)
937	{
938	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
939	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
940	PGM_INVL_GUEST_TLBS();
941	return VINF_SUCCESS;
942	}
943
944	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
945
946	const SHWPDE PdeDst = *pPdeDst;
947	if (!PdeDst.n.u1Present)
948	{
949	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
950	return VINF_SUCCESS;
951	}
952
953	/*
954	* Get the guest PD entry and calc big page.
955	*/
956	# if PGM_GST_TYPE == PGM_TYPE_32BIT
957	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
958	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
959	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
960	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
961	unsigned iPDSrc;
962	# if PGM_GST_TYPE == PGM_TYPE_PAE
963	X86PDPE PdpeSrc;
964	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
965	# else /* AMD64 */
966	PX86PML4E pPml4eSrc;
967	X86PDPE PdpeSrc;
968	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
969	# endif
970	GSTPDE PdeSrc;
971
972	if (pPDSrc)
973	PdeSrc = pPDSrc->a[iPDSrc];
974	else
975	PdeSrc.u = 0;
976	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
977
978	# if PGM_GST_TYPE == PGM_TYPE_AMD64
979	const bool fIsBigPage = PdeSrc.b.u1Size;
980	# else
981	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
982	# endif
983
984	# ifdef IN_RING3
985	/*
986	* If a CR3 Sync is pending we may ignore the invalidate page operation
987	* depending on the kind of sync and if it's a global page or not.
988	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
989	*/
990	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
991	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
992	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
993	&& fIsBigPage
994	&& PdeSrc.b.u1Global
995	)
996	)
997	# else
998	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
999	# endif
1000	{
1001	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1002	return VINF_SUCCESS;
1003	}
1004	# endif /* IN_RING3 */
1005
1006	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1007	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1008
1009	/* Fetch the pgm pool shadow descriptor. */
1010	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1011	Assert(pShwPdpt);
1012
1013	/* Fetch the pgm pool shadow descriptor. */
1014	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1015	Assert(pShwPde);
1016
1017	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1018	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1019
1020	if ( !pPml4eSrc->n.u1Present
1021	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1022	{
1023	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1024	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1025	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1026	pPml4eDst->u = 0;
1027	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1028	PGM_INVL_GUEST_TLBS();
1029	return VINF_SUCCESS;
1030	}
1031	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1032	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1033	{
1034	/*
1035	* Mark not present so we can resync the PML4E when it's used.
1036	*/
1037	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1038	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1039	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1040	pPml4eDst->u = 0;
1041	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1042	PGM_INVL_GUEST_TLBS();
1043	}
1044	else if (!pPml4eSrc->n.u1Accessed)
1045	{
1046	/*
1047	* Mark not present so we can set the accessed bit.
1048	*/
1049	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1050	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1051	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwAmd64CR3)->idx, iPml4);
1052	pPml4eDst->u = 0;
1053	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1054	PGM_INVL_GUEST_TLBS();
1055	}
1056
1057	/* Check if the PDPT entry has changed. */
1058	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1059	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1060	if ( !PdpeSrc.n.u1Present
1061	\|\| pShwPde->GCPhys != GCPhysPd)
1062	{
1063	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1064	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1065	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1066	pPdpeDst->u = 0;
1067	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1068	PGM_INVL_GUEST_TLBS();
1069	return VINF_SUCCESS;
1070	}
1071	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1072	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1073	{
1074	/*
1075	* Mark not present so we can resync the PDPTE when it's used.
1076	*/
1077	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1078	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1079	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1080	pPdpeDst->u = 0;
1081	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1082	PGM_INVL_GUEST_TLBS();
1083	}
1084	else if (!PdpeSrc.lm.u1Accessed)
1085	{
1086	/*
1087	* Mark not present so we can set the accessed bit.
1088	*/
1089	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1090	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1091	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1092	pPdpeDst->u = 0;
1093	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1094	PGM_INVL_GUEST_TLBS();
1095	}
1096	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1097
1098	# if PGM_GST_TYPE == PGM_TYPE_PAE
1099	/*
1100	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1101	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1102	*/
1103	if (!pPDSrc)
1104	{
1105	/* Guest PDPE not present */
1106	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
1107	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1108
1109	Assert(!PdpeSrc.n.u1Present);
1110	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
1111
1112	/* for each page directory entry */
1113	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1114	{
1115	if ( pPDDst->a[iPD].n.u1Present
1116	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
1117	{
1118	pgmPoolFree(pVM, pPDDst->a[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
1119	pPDDst->a[iPD].u = 0;
1120	}
1121	}
1122	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
1123	pPdptDst->a[iPdpt].n.u1Present = 0;
1124	PGM_INVL_GUEST_TLBS();
1125	}
1126	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
1127	# endif
1128
1129
1130	/*
1131	* Deal with the Guest PDE.
1132	*/
1133	rc = VINF_SUCCESS;
1134	if (PdeSrc.n.u1Present)
1135	{
1136	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1137	{
1138	/*
1139	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1140	*/
1141	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1142	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1143	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1144	}
1145	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1146	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1147	{
1148	/*
1149	* Mark not present so we can resync the PDE when it's used.
1150	*/
1151	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1152	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1153	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1154	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1155	# else
1156	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1157	# endif
1158	pPdeDst->u = 0;
1159	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1160	PGM_INVL_GUEST_TLBS();
1161	}
1162	else if (!PdeSrc.n.u1Accessed)
1163	{
1164	/*
1165	* Mark not present so we can set the accessed bit.
1166	*/
1167	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1168	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1169	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1170	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1171	# else
1172	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1173	# endif
1174	pPdeDst->u = 0;
1175	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1176	PGM_INVL_GUEST_TLBS();
1177	}
1178	else if (!fIsBigPage)
1179	{
1180	/*
1181	* 4KB - page.
1182	*/
1183	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1184	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1185	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1186	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1187	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1188	# endif
1189	if (pShwPage->GCPhys == GCPhys)
1190	{
1191	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1192	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1193	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1194	if (pPT->a[iPTEDst].n.u1Present)
1195	{
1196	# ifdef PGMPOOL_WITH_USER_TRACKING
1197	/* This is very unlikely with caching/monitoring enabled. */
1198	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1199	# endif
1200	pPT->a[iPTEDst].u = 0;
1201	}
1202	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1203	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1204	if (RT_SUCCESS(rc))
1205	rc = VINF_SUCCESS;
1206	# endif
1207	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1208	PGM_INVL_PG(GCPtrPage);
1209	}
1210	else
1211	{
1212	/*
1213	* The page table address changed.
1214	*/
1215	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1216	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1217	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1218	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1219	# else
1220	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1221	# endif
1222	pPdeDst->u = 0;
1223	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1224	PGM_INVL_GUEST_TLBS();
1225	}
1226	}
1227	else
1228	{
1229	/*
1230	* 2/4MB - page.
1231	*/
1232	/* Before freeing the page, check if anything really changed. */
1233	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1234	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1235	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1236	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1237	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1238	# endif
1239	if ( pShwPage->GCPhys == GCPhys
1240	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1241	{
1242	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1243	/** @todo PAT */
1244	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1245	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1246	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1247	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1248	{
1249	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1250	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1251	return VINF_SUCCESS;
1252	}
1253	}
1254
1255	/*
1256	* Ok, the page table is present and it's been changed in the guest.
1257	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1258	* We could do this for some flushes in GC too, but we need an algorithm for
1259	* deciding which 4MB pages containing code likely to be executed very soon.
1260	*/
1261	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1262	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1263	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1264	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1265	# else
1266	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1267	# endif
1268	pPdeDst->u = 0;
1269	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1270	PGM_INVL_BIG_PG(GCPtrPage);
1271	}
1272	}
1273	else
1274	{
1275	/*
1276	* Page directory is not present, mark shadow PDE not present.
1277	*/
1278	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1279	{
1280	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1281	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1282	# else
1283	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1284	# endif
1285	pPdeDst->u = 0;
1286	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1287	PGM_INVL_PG(GCPtrPage);
1288	}
1289	else
1290	{
1291	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1292	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1293	}
1294	}
1295
1296	return rc;
1297
1298	#else /* guest real and protected mode */
1299	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1300	return VINF_SUCCESS;
1301	#endif
1302	}
1303
1304
1305	#ifdef PGMPOOL_WITH_USER_TRACKING
1306	/**
1307	* Update the tracking of shadowed pages.
1308	*
1309	* @param pVM The VM handle.
1310	* @param pShwPage The shadow page.
1311	* @param HCPhys The physical page we is being dereferenced.
1312	*/
1313	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1314	{
1315	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1316	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1317	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1318
1319	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1320	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1321	* 2. write protect all shadowed pages. I.e. implement caching.
1322	*/
1323	/*
1324	* Find the guest address.
1325	*/
1326	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1327	pRam;
1328	pRam = pRam->CTX_SUFF(pNext))
1329	{
1330	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1331	while (iPage-- > 0)
1332	{
1333	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1334	{
1335	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1336	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1337	pShwPage->cPresent--;
1338	pPool->cPresent--;
1339	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1340	return;
1341	}
1342	}
1343	}
1344
1345	for (;;)
1346	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1347	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1348	pShwPage->cPresent--;
1349	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1350	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1351	}
1352
1353
1354	/**
1355	* Update the tracking of shadowed pages.
1356	*
1357	* @param pVM The VM handle.
1358	* @param pShwPage The shadow page.
1359	* @param u16 The top 16-bit of the pPage->HCPhys.
1360	* @param pPage Pointer to the guest page. this will be modified.
1361	* @param iPTDst The index into the shadow table.
1362	*/
1363	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1364	{
1365	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1366	/*
1367	* We're making certain assumptions about the placement of cRef and idx.
1368	*/
1369	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1370	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1371
1372	/*
1373	* Just deal with the simple first time here.
1374	*/
1375	if (!u16)
1376	{
1377	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1378	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1379	}
1380	else
1381	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1382
1383	/* write back, trying to be clever... */
1384	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%RHp->%RHp iPTDst=%#x\n",
1385	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1386	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1387	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1388
1389	/* update statistics. */
1390	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1391	pShwPage->cPresent++;
1392	if (pShwPage->iFirstPresent > iPTDst)
1393	pShwPage->iFirstPresent = iPTDst;
1394	}
1395	#endif /* PGMPOOL_WITH_USER_TRACKING */
1396
1397
1398	/**
1399	* Creates a 4K shadow page for a guest page.
1400	*
1401	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1402	* physical address. The PdeSrc argument only the flags are used. No page structured
1403	* will be mapped in this function.
1404	*
1405	* @param pVM VM handle.
1406	* @param pPteDst Destination page table entry.
1407	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1408	* Can safely assume that only the flags are being used.
1409	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1410	* @param pShwPage Pointer to the shadow page.
1411	* @param iPTDst The index into the shadow table.
1412	*
1413	* @remark Not used for 2/4MB pages!
1414	*/
1415	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1416	{
1417	if (PteSrc.n.u1Present)
1418	{
1419	/*
1420	* Find the ram range.
1421	*/
1422	PPGMPAGE pPage;
1423	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1424	if (RT_SUCCESS(rc))
1425	{
1426	/** @todo investiage PWT, PCD and PAT. */
1427	/*
1428	* Make page table entry.
1429	*/
1430	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1431	SHWPTE PteDst;
1432	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1433	{
1434	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1435	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1436	{
1437	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1438	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1439	PteDst.n.u1Present = 1;
1440	PteDst.n.u1Execute = 1;
1441	PteDst.n.u1IgnorePAT = 1;
1442	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1443	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1444	#else
1445	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1446	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1447	#endif
1448	}
1449	else
1450	{
1451	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", HCPhys));
1452	PteDst.u = 0;
1453	}
1454	/** @todo count these two kinds. */
1455	}
1456	else
1457	{
1458	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1459	/*
1460	* If the page or page directory entry is not marked accessed,
1461	* we mark the page not present.
1462	*/
1463	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1464	{
1465	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1466	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1467	PteDst.u = 0;
1468	}
1469	else
1470	/*
1471	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1472	* when the page is modified.
1473	*/
1474	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1475	{
1476	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1477	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1478	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1479	\| PGM_PTFLAGS_TRACK_DIRTY;
1480	}
1481	else
1482	#endif
1483	{
1484	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1485	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1486	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1487	PteDst.n.u1Present = 1;
1488	PteDst.n.u1Write = 1;
1489	PteDst.n.u1Execute = 1;
1490	PteDst.n.u1IgnorePAT = 1;
1491	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1492	/* PteDst.n.u1Size = 0 */
1493	#else
1494	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1495	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1496	#endif
1497	}
1498	}
1499
1500	#ifdef PGMPOOL_WITH_USER_TRACKING
1501	/*
1502	* Keep user track up to date.
1503	*/
1504	if (PteDst.n.u1Present)
1505	{
1506	if (!pPteDst->n.u1Present)
1507	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1508	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1509	{
1510	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1511	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1512	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1513	}
1514	}
1515	else if (pPteDst->n.u1Present)
1516	{
1517	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1518	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1519	}
1520	#endif /* PGMPOOL_WITH_USER_TRACKING */
1521
1522	/*
1523	* Update statistics and commit the entry.
1524	*/
1525	if (!PteSrc.n.u1Global)
1526	pShwPage->fSeenNonGlobal = true;
1527	*pPteDst = PteDst;
1528	}
1529	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1530	/** @todo count these. */
1531	}
1532	else
1533	{
1534	/*
1535	* Page not-present.
1536	*/
1537	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1538	#ifdef PGMPOOL_WITH_USER_TRACKING
1539	/* Keep user track up to date. */
1540	if (pPteDst->n.u1Present)
1541	{
1542	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1543	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1544	}
1545	#endif /* PGMPOOL_WITH_USER_TRACKING */
1546	pPteDst->u = 0;
1547	/** @todo count these. */
1548	}
1549	}
1550
1551
1552	/**
1553	* Syncs a guest OS page.
1554	*
1555	* There are no conflicts at this point, neither is there any need for
1556	* page table allocations.
1557	*
1558	* @returns VBox status code.
1559	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1560	* @param pVM VM handle.
1561	* @param PdeSrc Page directory entry of the guest.
1562	* @param GCPtrPage Guest context page address.
1563	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1564	* @param uErr Fault error (X86_TRAP_PF_*).
1565	*/
1566	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1567	{
1568	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1569
1570	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1571	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1572	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1573	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1574	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1575
1576	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1577	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1578	# endif
1579
1580	/*
1581	* Assert preconditions.
1582	*/
1583	Assert(PdeSrc.n.u1Present);
1584	Assert(cPages);
1585	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1586
1587	/*
1588	* Get the shadow PDE, find the shadow page table in the pool.
1589	*/
1590	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1591	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1592	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
1593
1594	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1595	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
1596	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1597	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1598	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
1599	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
1600
1601	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1602	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1603	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1604	PX86PDPAE pPDDst;
1605	PX86PDPT pPdptDst;
1606
1607	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1608	AssertRCSuccessReturn(rc, rc);
1609	Assert(pPDDst && pPdptDst);
1610	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1611	# endif
1612
1613	SHWPDE PdeDst = *pPdeDst;
1614	Assert(PdeDst.n.u1Present);
1615	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1616
1617	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1618	/* Fetch the pgm pool shadow descriptor. */
1619	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1620	Assert(pShwPde);
1621	# endif
1622
1623	/*
1624	* Check that the page is present and that the shadow PDE isn't out of sync.
1625	*/
1626	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1627	const bool fBigPage = PdeSrc.b.u1Size;
1628	# else
1629	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1630	# endif
1631	RTGCPHYS GCPhys;
1632	if (!fBigPage)
1633	{
1634	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1635	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1636	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1637	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1638	# endif
1639	}
1640	else
1641	{
1642	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1643	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1644	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1645	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1646	# endif
1647	}
1648	if ( pShwPage->GCPhys == GCPhys
1649	&& PdeSrc.n.u1Present
1650	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1651	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1652	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1653	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1654	# endif
1655	)
1656	{
1657	/*
1658	* Check that the PDE is marked accessed already.
1659	* Since we set the accessed bit before getting here on a #PF, this
1660	* check is only meant for dealing with non-#PF'ing paths.
1661	*/
1662	if (PdeSrc.n.u1Accessed)
1663	{
1664	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1665	if (!fBigPage)
1666	{
1667	/*
1668	* 4KB Page - Map the guest page table.
1669	*/
1670	PGSTPT pPTSrc;
1671	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1672	if (RT_SUCCESS(rc))
1673	{
1674	# ifdef PGM_SYNC_N_PAGES
1675	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1676	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1677	{
1678	/*
1679	* This code path is currently only taken when the caller is PGMTrap0eHandler
1680	* for non-present pages!
1681	*
1682	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1683	* deal with locality.
1684	*/
1685	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1686	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1687	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1688	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1689	# else
1690	const unsigned offPTSrc = 0;
1691	# endif
1692	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1693	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1694	iPTDst = 0;
1695	else
1696	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1697	for (; iPTDst < iPTDstEnd; iPTDst++)
1698	{
1699	if (!pPTDst->a[iPTDst].n.u1Present)
1700	{
1701	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1702	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1703	NOREF(GCPtrCurPage);
1704	#ifndef IN_RING0
1705	/*
1706	* Assuming kernel code will be marked as supervisor - and not as user level
1707	* and executed using a conforming code selector - And marked as readonly.
1708	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1709	*/
1710	PPGMPAGE pPage;
1711	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1712	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1713	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1714	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1715	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1716	)
1717	#endif /* else: CSAM not active */
1718	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1719	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1720	GCPtrCurPage, PteSrc.n.u1Present,
1721	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1722	PteSrc.n.u1User & PdeSrc.n.u1User,
1723	(uint64_t)PteSrc.u,
1724	(uint64_t)pPTDst->a[iPTDst].u,
1725	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1726	}
1727	}
1728	}
1729	else
1730	# endif /* PGM_SYNC_N_PAGES */
1731	{
1732	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1733	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1734	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1735	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1736	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1737	GCPtrPage, PteSrc.n.u1Present,
1738	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1739	PteSrc.n.u1User & PdeSrc.n.u1User,
1740	(uint64_t)PteSrc.u,
1741	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1742	}
1743	}
1744	else /* MMIO or invalid page: emulated in #PF handler. */
1745	{
1746	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1747	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1748	}
1749	}
1750	else
1751	{
1752	/*
1753	* 4/2MB page - lazy syncing shadow 4K pages.
1754	* (There are many causes of getting here, it's no longer only CSAM.)
1755	*/
1756	/* Calculate the GC physical address of this 4KB shadow page. */
1757	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1758	/* Find ram range. */
1759	PPGMPAGE pPage;
1760	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1761	if (RT_SUCCESS(rc))
1762	{
1763	/*
1764	* Make shadow PTE entry.
1765	*/
1766	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1767	SHWPTE PteDst;
1768	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1769	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1770	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1771	{
1772	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1773	PteDst.n.u1Write = 0;
1774	else
1775	PteDst.u = 0;
1776	}
1777	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1778	# ifdef PGMPOOL_WITH_USER_TRACKING
1779	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1780	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1781	# endif
1782	pPTDst->a[iPTDst] = PteDst;
1783
1784
1785	/*
1786	* If the page is not flagged as dirty and is writable, then make it read-only
1787	* at PD level, so we can set the dirty bit when the page is modified.
1788	*
1789	* ASSUMES that page access handlers are implemented on page table entry level.
1790	* Thus we will first catch the dirty access and set PDE.D and restart. If
1791	* there is an access handler, we'll trap again and let it work on the problem.
1792	*/
1793	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1794	* As for invlpg, it simply frees the whole shadow PT.
1795	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1796	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1797	{
1798	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1799	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1800	PdeDst.n.u1Write = 0;
1801	}
1802	else
1803	{
1804	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1805	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1806	}
1807	*pPdeDst = PdeDst;
1808	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1809	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1810	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1811	}
1812	else
1813	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1814	}
1815	return VINF_SUCCESS;
1816	}
1817	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1818	}
1819	else
1820	{
1821	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1822	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1823	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1824	}
1825
1826	/*
1827	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1828	* Yea, I'm lazy.
1829	*/
1830	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1831	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1832	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1833	# else
1834	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1835	# endif
1836
1837	pPdeDst->u = 0;
1838	PGM_INVL_GUEST_TLBS();
1839	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1840
1841	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1842	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1843	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1844
1845	# ifdef PGM_SYNC_N_PAGES
1846	/*
1847	* Get the shadow PDE, find the shadow page table in the pool.
1848	*/
1849	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1850	X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
1851
1852	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1853	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1854
1855	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1856	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1857	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1858	PX86PDPAE pPDDst;
1859	X86PDEPAE PdeDst;
1860	PX86PDPT pPdptDst;
1861
1862	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1863	AssertRCSuccessReturn(rc, rc);
1864	Assert(pPDDst && pPdptDst);
1865	PdeDst = pPDDst->a[iPDDst];
1866	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1867	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1868	PEPTPD pPDDst;
1869	EPTPDE PdeDst;
1870
1871	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1872	if (rc != VINF_SUCCESS)
1873	{
1874	AssertRC(rc);
1875	return rc;
1876	}
1877	Assert(pPDDst);
1878	PdeDst = pPDDst->a[iPDDst];
1879	# endif
1880	Assert(PdeDst.n.u1Present);
1881	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1882	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1883
1884	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1885	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1886	{
1887	/*
1888	* This code path is currently only taken when the caller is PGMTrap0eHandler
1889	* for non-present pages!
1890	*
1891	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1892	* deal with locality.
1893	*/
1894	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1895	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1896	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1897	iPTDst = 0;
1898	else
1899	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1900	for (; iPTDst < iPTDstEnd; iPTDst++)
1901	{
1902	if (!pPTDst->a[iPTDst].n.u1Present)
1903	{
1904	GSTPTE PteSrc;
1905
1906	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1907
1908	/* Fake the page table entry */
1909	PteSrc.u = GCPtrCurPage;
1910	PteSrc.n.u1Present = 1;
1911	PteSrc.n.u1Dirty = 1;
1912	PteSrc.n.u1Accessed = 1;
1913	PteSrc.n.u1Write = 1;
1914	PteSrc.n.u1User = 1;
1915
1916	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1917
1918	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1919	GCPtrCurPage, PteSrc.n.u1Present,
1920	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1921	PteSrc.n.u1User & PdeSrc.n.u1User,
1922	(uint64_t)PteSrc.u,
1923	(uint64_t)pPTDst->a[iPTDst].u,
1924	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1925	}
1926	else
1927	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1928	}
1929	}
1930	else
1931	# endif /* PGM_SYNC_N_PAGES */
1932	{
1933	GSTPTE PteSrc;
1934	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1935	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1936
1937	/* Fake the page table entry */
1938	PteSrc.u = GCPtrCurPage;
1939	PteSrc.n.u1Present = 1;
1940	PteSrc.n.u1Dirty = 1;
1941	PteSrc.n.u1Accessed = 1;
1942	PteSrc.n.u1Write = 1;
1943	PteSrc.n.u1User = 1;
1944	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1945
1946	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1947	GCPtrPage, PteSrc.n.u1Present,
1948	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1949	PteSrc.n.u1User & PdeSrc.n.u1User,
1950	(uint64_t)PteSrc.u,
1951	(uint64_t)pPTDst->a[iPTDst].u,
1952	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1953	}
1954	return VINF_SUCCESS;
1955
1956	#else
1957	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1958	return VERR_INTERNAL_ERROR;
1959	#endif
1960	}
1961
1962
1963	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1964	/**
1965	* Investigate page fault and handle write protection page faults caused by
1966	* dirty bit tracking.
1967	*
1968	* @returns VBox status code.
1969	* @param pVM VM handle.
1970	* @param uErr Page fault error code.
1971	* @param pPdeDst Shadow page directory entry.
1972	* @param pPdeSrc Guest page directory entry.
1973	* @param GCPtrPage Guest context page address.
1974	*/
1975	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
1976	{
1977	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1978	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1979	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1980	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1981	bool fBigPagesSupported = true;
1982	# else
1983	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1984	# endif
1985	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1986	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1987	# endif
1988	unsigned uPageFaultLevel;
1989	int rc;
1990
1991	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
1992	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1993
1994	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1995	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1996
1997	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1998	PX86PML4E pPml4eSrc;
1999	PX86PDPE pPdpeSrc;
2000
2001	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2002	Assert(pPml4eSrc);
2003
2004	/*
2005	* Real page fault? (PML4E level)
2006	*/
2007	if ( (uErr & X86_TRAP_PF_RSVD)
2008	\|\| !pPml4eSrc->n.u1Present
2009	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2010	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2011	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2012	)
2013	{
2014	uPageFaultLevel = 0;
2015	goto l_UpperLevelPageFault;
2016	}
2017	Assert(pPdpeSrc);
2018
2019	# else /* PAE */
2020	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2021	# endif /* PAE */
2022
2023	/*
2024	* Real page fault? (PDPE level)
2025	*/
2026	if ( (uErr & X86_TRAP_PF_RSVD)
2027	\|\| !pPdpeSrc->n.u1Present
2028	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2029	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2030	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2031	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2032	# endif
2033	)
2034	{
2035	uPageFaultLevel = 1;
2036	goto l_UpperLevelPageFault;
2037	}
2038	# endif
2039
2040	/*
2041	* Real page fault? (PDE level)
2042	*/
2043	if ( (uErr & X86_TRAP_PF_RSVD)
2044	\|\| !pPdeSrc->n.u1Present
2045	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2046	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2047	# endif
2048	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2049	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2050	{
2051	uPageFaultLevel = 2;
2052	goto l_UpperLevelPageFault;
2053	}
2054
2055	/*
2056	* First check the easy case where the page directory has been marked read-only to track
2057	* the dirty bit of an emulated BIG page
2058	*/
2059	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2060	{
2061	/* Mark guest page directory as accessed */
2062	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2063	pPml4eSrc->n.u1Accessed = 1;
2064	pPdpeSrc->lm.u1Accessed = 1;
2065	# endif
2066	pPdeSrc->b.u1Accessed = 1;
2067
2068	/*
2069	* Only write protection page faults are relevant here.
2070	*/
2071	if (fWriteFault)
2072	{
2073	/* Mark guest page directory as dirty (BIG page only). */
2074	pPdeSrc->b.u1Dirty = 1;
2075
2076	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2077	{
2078	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2079
2080	Assert(pPdeSrc->b.u1Write);
2081
2082	pPdeDst->n.u1Write = 1;
2083	pPdeDst->n.u1Accessed = 1;
2084	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2085	PGM_INVL_BIG_PG(GCPtrPage);
2086	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2087	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2088	}
2089	}
2090	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2091	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2092	}
2093	/* else: 4KB page table */
2094
2095	/*
2096	* Map the guest page table.
2097	*/
2098	PGSTPT pPTSrc;
2099	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2100	if (RT_SUCCESS(rc))
2101	{
2102	/*
2103	* Real page fault?
2104	*/
2105	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2106	const GSTPTE PteSrc = *pPteSrc;
2107	if ( !PteSrc.n.u1Present
2108	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2109	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2110	# endif
2111	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2112	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2113	)
2114	{
2115	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2116	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2117	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2118
2119	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2120	* See the 2nd case above as well.
2121	*/
2122	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2123	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2124
2125	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2126	return VINF_EM_RAW_GUEST_TRAP;
2127	}
2128	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2129
2130	/*
2131	* Set the accessed bits in the page directory and the page table.
2132	*/
2133	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2134	pPml4eSrc->n.u1Accessed = 1;
2135	pPdpeSrc->lm.u1Accessed = 1;
2136	# endif
2137	pPdeSrc->n.u1Accessed = 1;
2138	pPteSrc->n.u1Accessed = 1;
2139
2140	/*
2141	* Only write protection page faults are relevant here.
2142	*/
2143	if (fWriteFault)
2144	{
2145	/* Write access, so mark guest entry as dirty. */
2146	# ifdef VBOX_WITH_STATISTICS
2147	if (!pPteSrc->n.u1Dirty)
2148	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2149	else
2150	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2151	# endif
2152
2153	pPteSrc->n.u1Dirty = 1;
2154
2155	if (pPdeDst->n.u1Present)
2156	{
2157	#ifndef IN_RING0
2158	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2159	* Our individual shadow handlers will provide more information and force a fatal exit.
2160	*/
2161	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2162	{
2163	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2164	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2165	return VINF_SUCCESS;
2166	}
2167	#endif
2168	/*
2169	* Map shadow page table.
2170	*/
2171	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2172	if (pShwPage)
2173	{
2174	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2175	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2176	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2177	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2178	{
2179	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2180	# ifdef VBOX_STRICT
2181	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2182	if (pPage)
2183	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2184	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2185	# endif
2186	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2187
2188	Assert(pPteSrc->n.u1Write);
2189
2190	pPteDst->n.u1Write = 1;
2191	pPteDst->n.u1Dirty = 1;
2192	pPteDst->n.u1Accessed = 1;
2193	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2194	PGM_INVL_PG(GCPtrPage);
2195
2196	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2197	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2198	}
2199	}
2200	else
2201	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2202	}
2203	}
2204	/** @todo Optimize accessed bit emulation? */
2205	# ifdef VBOX_STRICT
2206	/*
2207	* Sanity check.
2208	*/
2209	else if ( !pPteSrc->n.u1Dirty
2210	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2211	&& pPdeDst->n.u1Present)
2212	{
2213	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2214	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2215	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2216	if ( pPteDst->n.u1Present
2217	&& pPteDst->n.u1Write)
2218	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2219	}
2220	# endif /* VBOX_STRICT */
2221	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2222	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2223	}
2224	AssertRC(rc);
2225	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2226	return rc;
2227
2228
2229	l_UpperLevelPageFault:
2230	/*
2231	* Pagefault detected while checking the PML4E, PDPE or PDE.
2232	* Single exit handler to get rid of duplicate code paths.
2233	*/
2234	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2235	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2236	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2237
2238	if (
2239	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2240	pPml4eSrc->n.u1Present &&
2241	# endif
2242	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2243	pPdpeSrc->n.u1Present &&
2244	# endif
2245	pPdeSrc->n.u1Present)
2246	{
2247	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2248	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2249	{
2250	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2251	}
2252	else
2253	{
2254	/*
2255	* Map the guest page table.
2256	*/
2257	PGSTPT pPTSrc;
2258	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2259	if (RT_SUCCESS(rc))
2260	{
2261	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2262	const GSTPTE PteSrc = *pPteSrc;
2263	if (pPteSrc->n.u1Present)
2264	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2265	}
2266	AssertRC(rc);
2267	}
2268	}
2269	return VINF_EM_RAW_GUEST_TRAP;
2270	}
2271	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2272
2273
2274	/**
2275	* Sync a shadow page table.
2276	*
2277	* The shadow page table is not present. This includes the case where
2278	* there is a conflict with a mapping.
2279	*
2280	* @returns VBox status code.
2281	* @param pVM VM handle.
2282	* @param iPD Page directory index.
2283	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2284	* Assume this is a temporary mapping.
2285	* @param GCPtrPage GC Pointer of the page that caused the fault
2286	*/
2287	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2288	{
2289	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2290	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2291	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2292
2293	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2294	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2295	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2296	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2297	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2298
2299	int rc = VINF_SUCCESS;
2300
2301	/*
2302	* Validate input a little bit.
2303	*/
2304	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2305	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2306	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2307	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2308
2309	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2310	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
2311	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
2312	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2313	PSHWPDE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2314
2315	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2316	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2317	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2318	PX86PDPAE pPDDst;
2319	PX86PDPT pPdptDst;
2320	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2321	AssertRCSuccessReturn(rc, rc);
2322	Assert(pPDDst);
2323	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2324	# endif
2325	SHWPDE PdeDst = *pPdeDst;
2326
2327	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2328	/* Fetch the pgm pool shadow descriptor. */
2329	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2330	Assert(pShwPde);
2331	# endif
2332
2333	# ifndef PGM_WITHOUT_MAPPINGS
2334	/*
2335	* Check for conflicts.
2336	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2337	* HC: Simply resolve the conflict.
2338	*/
2339	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2340	{
2341	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2342	# ifndef IN_RING3
2343	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2344	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2345	return VERR_ADDRESS_CONFLICT;
2346	# else
2347	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2348	Assert(pMapping);
2349	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2350	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2351	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2352	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2353	# else
2354	AssertFailed(); /* can't happen for amd64 */
2355	# endif
2356	if (RT_FAILURE(rc))
2357	{
2358	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2359	return rc;
2360	}
2361	PdeDst = *pPdeDst;
2362	# endif
2363	}
2364	# else /* PGM_WITHOUT_MAPPINGS */
2365	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2366	# endif /* PGM_WITHOUT_MAPPINGS */
2367	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2368
2369	/*
2370	* Sync page directory entry.
2371	*/
2372	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2373	if (PdeSrc.n.u1Present)
2374	{
2375	/*
2376	* Allocate & map the page table.
2377	*/
2378	PSHWPT pPTDst;
2379	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2380	const bool fPageTable = !PdeSrc.b.u1Size;
2381	# else
2382	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2383	# endif
2384	PPGMPOOLPAGE pShwPage;
2385	RTGCPHYS GCPhys;
2386	if (fPageTable)
2387	{
2388	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2389	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2390	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2391	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2392	# endif
2393	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2394	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2395	# else
2396	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2397	# endif
2398	}
2399	else
2400	{
2401	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2402	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2403	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2404	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2405	# endif
2406	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2407	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2408	# else
2409	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2410	# endif
2411	}
2412	if (rc == VINF_SUCCESS)
2413	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2414	else if (rc == VINF_PGM_CACHED_PAGE)
2415	{
2416	/*
2417	* The PT was cached, just hook it up.
2418	*/
2419	if (fPageTable)
2420	PdeDst.u = pShwPage->Core.Key
2421	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2422	else
2423	{
2424	PdeDst.u = pShwPage->Core.Key
2425	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2426	/* (see explanation and assumptions further down.) */
2427	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2428	{
2429	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2430	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2431	PdeDst.b.u1Write = 0;
2432	}
2433	}
2434	*pPdeDst = PdeDst;
2435	return VINF_SUCCESS;
2436	}
2437	else if (rc == VERR_PGM_POOL_FLUSHED)
2438	{
2439	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2440	return VINF_PGM_SYNC_CR3;
2441	}
2442	else
2443	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2444	PdeDst.u &= X86_PDE_AVL_MASK;
2445	PdeDst.u \|= pShwPage->Core.Key;
2446
2447	/*
2448	* Page directory has been accessed (this is a fault situation, remember).
2449	*/
2450	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2451	if (fPageTable)
2452	{
2453	/*
2454	* Page table - 4KB.
2455	*
2456	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2457	*/
2458	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2459	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2460	PGSTPT pPTSrc;
2461	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2462	if (RT_SUCCESS(rc))
2463	{
2464	/*
2465	* Start by syncing the page directory entry so CSAM's TLB trick works.
2466	*/
2467	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2468	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2469	*pPdeDst = PdeDst;
2470
2471	/*
2472	* Directory/page user or supervisor privilege: (same goes for read/write)
2473	*
2474	* Directory Page Combined
2475	* U/S U/S U/S
2476	* 0 0 0
2477	* 0 1 0
2478	* 1 0 0
2479	* 1 1 1
2480	*
2481	* Simple AND operation. Table listed for completeness.
2482	*
2483	*/
2484	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2485	# ifdef PGM_SYNC_N_PAGES
2486	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2487	unsigned iPTDst = iPTBase;
2488	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2489	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2490	iPTDst = 0;
2491	else
2492	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2493	# else /* !PGM_SYNC_N_PAGES */
2494	unsigned iPTDst = 0;
2495	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2496	# endif /* !PGM_SYNC_N_PAGES */
2497	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2498	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2499	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2500	# else
2501	const unsigned offPTSrc = 0;
2502	# endif
2503	for (; iPTDst < iPTDstEnd; iPTDst++)
2504	{
2505	const unsigned iPTSrc = iPTDst + offPTSrc;
2506	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2507
2508	if (PteSrc.n.u1Present) /* we've already cleared it above */
2509	{
2510	# ifndef IN_RING0
2511	/*
2512	* Assuming kernel code will be marked as supervisor - and not as user level
2513	* and executed using a conforming code selector - And marked as readonly.
2514	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2515	*/
2516	PPGMPAGE pPage;
2517	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2518	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2519	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2520	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2521	)
2522	# endif
2523	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2524	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2525	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2526	PteSrc.n.u1Present,
2527	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2528	PteSrc.n.u1User & PdeSrc.n.u1User,
2529	(uint64_t)PteSrc.u,
2530	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2531	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2532	}
2533	} /* for PTEs */
2534	}
2535	}
2536	else
2537	{
2538	/*
2539	* Big page - 2/4MB.
2540	*
2541	* We'll walk the ram range list in parallel and optimize lookups.
2542	* We will only sync on shadow page table at a time.
2543	*/
2544	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2545
2546	/**
2547	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2548	*/
2549
2550	/*
2551	* Start by syncing the page directory entry.
2552	*/
2553	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2554	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2555
2556	/*
2557	* If the page is not flagged as dirty and is writable, then make it read-only
2558	* at PD level, so we can set the dirty bit when the page is modified.
2559	*
2560	* ASSUMES that page access handlers are implemented on page table entry level.
2561	* Thus we will first catch the dirty access and set PDE.D and restart. If
2562	* there is an access handler, we'll trap again and let it work on the problem.
2563	*/
2564	/** @todo move the above stuff to a section in the PGM documentation. */
2565	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2566	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2567	{
2568	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2569	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2570	PdeDst.b.u1Write = 0;
2571	}
2572	*pPdeDst = PdeDst;
2573
2574	/*
2575	* Fill the shadow page table.
2576	*/
2577	/* Get address and flags from the source PDE. */
2578	SHWPTE PteDstBase;
2579	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2580
2581	/* Loop thru the entries in the shadow PT. */
2582	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2583	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2584	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2585	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2586	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2587	unsigned iPTDst = 0;
2588	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2589	{
2590	/* Advance ram range list. */
2591	while (pRam && GCPhys > pRam->GCPhysLast)
2592	pRam = pRam->CTX_SUFF(pNext);
2593	if (pRam && GCPhys >= pRam->GCPhys)
2594	{
2595	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2596	do
2597	{
2598	/* Make shadow PTE. */
2599	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2600	SHWPTE PteDst;
2601
2602	/* Make sure the RAM has already been allocated. */
2603	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2604	{
2605	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2606	{
2607	# ifdef IN_RING3
2608	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2609	# else
2610	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2611	# endif
2612	if (rc != VINF_SUCCESS)
2613	return rc;
2614	}
2615	}
2616
2617	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2618	{
2619	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2620	{
2621	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2622	PteDst.n.u1Write = 0;
2623	}
2624	else
2625	PteDst.u = 0;
2626	}
2627	# ifndef IN_RING0
2628	/*
2629	* Assuming kernel code will be marked as supervisor and not as user level and executed
2630	* using a conforming code selector. Don't check for readonly, as that implies the whole
2631	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2632	*/
2633	else if ( !PdeSrc.n.u1User
2634	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2635	PteDst.u = 0;
2636	# endif
2637	else
2638	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2639	# ifdef PGMPOOL_WITH_USER_TRACKING
2640	if (PteDst.n.u1Present)
2641	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2642	# endif
2643	/* commit it */
2644	pPTDst->a[iPTDst] = PteDst;
2645	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2646	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2647	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2648
2649	/* advance */
2650	GCPhys += PAGE_SIZE;
2651	iHCPage++;
2652	iPTDst++;
2653	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2654	&& GCPhys <= pRam->GCPhysLast);
2655	}
2656	else if (pRam)
2657	{
2658	Log(("Invalid pages at %RGp\n", GCPhys));
2659	do
2660	{
2661	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2662	GCPhys += PAGE_SIZE;
2663	iPTDst++;
2664	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2665	&& GCPhys < pRam->GCPhys);
2666	}
2667	else
2668	{
2669	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2670	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2671	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2672	}
2673	} /* while more PTEs */
2674	} /* 4KB / 4MB */
2675	}
2676	else
2677	AssertRelease(!PdeDst.n.u1Present);
2678
2679	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2680	if (RT_FAILURE(rc))
2681	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2682	return rc;
2683
2684	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2685	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2686	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2687
2688
2689	/*
2690	* Validate input a little bit.
2691	*/
2692	int rc = VINF_SUCCESS;
2693	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2694	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2695	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2696
2697	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2698	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm!/;
2699	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2700
2701	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2702	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2703	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2704	PX86PDPAE pPDDst;
2705	PX86PDPT pPdptDst;
2706	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2707	AssertRCSuccessReturn(rc, rc);
2708	Assert(pPDDst);
2709	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2710
2711	/* Fetch the pgm pool shadow descriptor. */
2712	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2713	Assert(pShwPde);
2714
2715	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2716	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2717	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2718	PEPTPD pPDDst;
2719	PEPTPDPT pPdptDst;
2720
2721	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2722	if (rc != VINF_SUCCESS)
2723	{
2724	AssertRC(rc);
2725	return rc;
2726	}
2727	Assert(pPDDst);
2728	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2729
2730	/* Fetch the pgm pool shadow descriptor. */
2731	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2732	Assert(pShwPde);
2733	# endif
2734	SHWPDE PdeDst = *pPdeDst;
2735
2736	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2737	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2738
2739	GSTPDE PdeSrc;
2740	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2741	PdeSrc.n.u1Present = 1;
2742	PdeSrc.n.u1Write = 1;
2743	PdeSrc.n.u1Accessed = 1;
2744	PdeSrc.n.u1User = 1;
2745
2746	/*
2747	* Allocate & map the page table.
2748	*/
2749	PSHWPT pPTDst;
2750	PPGMPOOLPAGE pShwPage;
2751	RTGCPHYS GCPhys;
2752
2753	/* Virtual address = physical address */
2754	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2755	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2756	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2757	# else
2758	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2759	# endif
2760
2761	if ( rc == VINF_SUCCESS
2762	\|\| rc == VINF_PGM_CACHED_PAGE)
2763	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2764	else
2765	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2766
2767	PdeDst.u &= X86_PDE_AVL_MASK;
2768	PdeDst.u \|= pShwPage->Core.Key;
2769	PdeDst.n.u1Present = 1;
2770	PdeDst.n.u1Write = 1;
2771	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2772	PdeDst.n.u1Execute = 1;
2773	# else
2774	PdeDst.n.u1User = 1;
2775	PdeDst.n.u1Accessed = 1;
2776	# endif
2777	*pPdeDst = PdeDst;
2778
2779	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2780	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2781	return rc;
2782
2783	#else
2784	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2785	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2786	return VERR_INTERNAL_ERROR;
2787	#endif
2788	}
2789
2790
2791
2792	/**
2793	* Prefetch a page/set of pages.
2794	*
2795	* Typically used to sync commonly used pages before entering raw mode
2796	* after a CR3 reload.
2797	*
2798	* @returns VBox status code.
2799	* @param pVM VM handle.
2800	* @param GCPtrPage Page to invalidate.
2801	*/
2802	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2803	{
2804	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2805	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2806	/*
2807	* Check that all Guest levels thru the PDE are present, getting the
2808	* PD and PDE in the processes.
2809	*/
2810	int rc = VINF_SUCCESS;
2811	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2812	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2813	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2814	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2815	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2816	unsigned iPDSrc;
2817	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2818	if (!pPDSrc)
2819	return VINF_SUCCESS; /* not present */
2820	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2821	unsigned iPDSrc;
2822	PX86PML4E pPml4eSrc;
2823	X86PDPE PdpeSrc;
2824	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2825	if (!pPDSrc)
2826	return VINF_SUCCESS; /* not present */
2827	# endif
2828	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2829	# else
2830	PGSTPD pPDSrc = NULL;
2831	const unsigned iPDSrc = 0;
2832	GSTPDE PdeSrc;
2833
2834	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2835	PdeSrc.n.u1Present = 1;
2836	PdeSrc.n.u1Write = 1;
2837	PdeSrc.n.u1Accessed = 1;
2838	PdeSrc.n.u1User = 1;
2839	# endif
2840
2841	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2842	{
2843	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2844	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
2845	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2846	const X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
2847	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2848	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2849	PX86PDPAE pPDDst;
2850	X86PDEPAE PdeDst;
2851
2852	# if PGM_GST_TYPE == PGM_TYPE_PROT
2853	/* AMD-V nested paging */
2854	X86PML4E Pml4eSrc;
2855	X86PDPE PdpeSrc;
2856	PX86PML4E pPml4eSrc = &Pml4eSrc;
2857
2858	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2859	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2860	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2861	# endif
2862
2863	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2864	if (rc != VINF_SUCCESS)
2865	{
2866	AssertRC(rc);
2867	return rc;
2868	}
2869	Assert(pPDDst);
2870	PdeDst = pPDDst->a[iPDDst];
2871	# endif
2872	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2873	{
2874	if (!PdeDst.n.u1Present)
2875	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2876	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2877	else
2878	{
2879	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2880	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2881	* makes no sense to prefetch more than one page.
2882	*/
2883	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2884	if (RT_SUCCESS(rc))
2885	rc = VINF_SUCCESS;
2886	}
2887	}
2888	}
2889	return rc;
2890
2891	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2892	return VINF_SUCCESS; /* ignore */
2893	#endif
2894	}
2895
2896
2897
2898
2899	/**
2900	* Syncs a page during a PGMVerifyAccess() call.
2901	*
2902	* @returns VBox status code (informational included).
2903	* @param GCPtrPage The address of the page to sync.
2904	* @param fPage The effective guest page flags.
2905	* @param uErr The trap error code.
2906	*/
2907	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
2908	{
2909	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2910
2911	Assert(!HWACCMIsNestedPagingActive(pVM));
2912	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2913	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2914
2915	# ifndef IN_RING0
2916	if (!(fPage & X86_PTE_US))
2917	{
2918	/*
2919	* Mark this page as safe.
2920	*/
2921	/** @todo not correct for pages that contain both code and data!! */
2922	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
2923	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
2924	}
2925	# endif
2926
2927	/*
2928	* Get guest PD and index.
2929	*/
2930	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2931	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2932	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2933	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2934	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2935	unsigned iPDSrc;
2936	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2937
2938	if (pPDSrc)
2939	{
2940	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2941	return VINF_EM_RAW_GUEST_TRAP;
2942	}
2943	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2944	unsigned iPDSrc;
2945	PX86PML4E pPml4eSrc;
2946	X86PDPE PdpeSrc;
2947	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2948	if (!pPDSrc)
2949	{
2950	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
2951	return VINF_EM_RAW_GUEST_TRAP;
2952	}
2953	# endif
2954	# else
2955	PGSTPD pPDSrc = NULL;
2956	const unsigned iPDSrc = 0;
2957	# endif
2958	int rc = VINF_SUCCESS;
2959
2960	/*
2961	* First check if the shadow pd is present.
2962	*/
2963	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2964	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2965	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2966	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2967	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2968	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2969	PX86PDPAE pPDDst;
2970	PX86PDEPAE pPdeDst;
2971
2972	# if PGM_GST_TYPE == PGM_TYPE_PROT
2973	/* AMD-V nested paging */
2974	X86PML4E Pml4eSrc;
2975	X86PDPE PdpeSrc;
2976	PX86PML4E pPml4eSrc = &Pml4eSrc;
2977
2978	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2979	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2980	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2981	# endif
2982
2983	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2984	if (rc != VINF_SUCCESS)
2985	{
2986	AssertRC(rc);
2987	return rc;
2988	}
2989	Assert(pPDDst);
2990	pPdeDst = &pPDDst->a[iPDDst];
2991	# endif
2992	if (!pPdeDst->n.u1Present)
2993	{
2994	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2995	AssertRC(rc);
2996	if (rc != VINF_SUCCESS)
2997	return rc;
2998	}
2999
3000	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3001	/* Check for dirty bit fault */
3002	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3003	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3004	Log(("PGMVerifyAccess: success (dirty)\n"));
3005	else
3006	{
3007	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3008	#else
3009	{
3010	GSTPDE PdeSrc;
3011	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3012	PdeSrc.n.u1Present = 1;
3013	PdeSrc.n.u1Write = 1;
3014	PdeSrc.n.u1Accessed = 1;
3015	PdeSrc.n.u1User = 1;
3016
3017	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3018	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3019	if (uErr & X86_TRAP_PF_US)
3020	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3021	else /* supervisor */
3022	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3023
3024	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3025	if (RT_SUCCESS(rc))
3026	{
3027	/* Page was successfully synced */
3028	Log2(("PGMVerifyAccess: success (sync)\n"));
3029	rc = VINF_SUCCESS;
3030	}
3031	else
3032	{
3033	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3034	return VINF_EM_RAW_GUEST_TRAP;
3035	}
3036	}
3037	return rc;
3038
3039	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3040
3041	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3042	return VERR_INTERNAL_ERROR;
3043	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3044	}
3045
3046
3047	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3048	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3049	/**
3050	* Figures out which kind of shadow page this guest PDE warrants.
3051	*
3052	* @returns Shadow page kind.
3053	* @param pPdeSrc The guest PDE in question.
3054	* @param cr4 The current guest cr4 value.
3055	*/
3056	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3057	{
3058	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3059	if (!pPdeSrc->n.u1Size)
3060	# else
3061	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3062	# endif
3063	return BTH_PGMPOOLKIND_PT_FOR_PT;
3064	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3065	//{
3066	// case 0:
3067	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3068	// case X86_PDE4M_RW:
3069	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3070	// case X86_PDE4M_US:
3071	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3072	// case X86_PDE4M_RW \| X86_PDE4M_US:
3073	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3074	# if 0
3075	// case X86_PDE4M_PAE_NX:
3076	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3077	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3078	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3079	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3080	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3081	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3082	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3083	# endif
3084	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3085	//}
3086	}
3087	# endif
3088	#endif
3089
3090	#undef MY_STAM_COUNTER_INC
3091	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3092
3093
3094	/**
3095	* Syncs the paging hierarchy starting at CR3.
3096	*
3097	* @returns VBox status code, no specials.
3098	* @param pVM The virtual machine.
3099	* @param cr0 Guest context CR0 register
3100	* @param cr3 Guest context CR3 register
3101	* @param cr4 Guest context CR4 register
3102	* @param fGlobal Including global page directories or not
3103	*/
3104	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3105	{
3106	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3107	fGlobal = true; /* Change this CR3 reload to be a global one. */
3108
3109	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3110	/*
3111	* Update page access handlers.
3112	* The virtual are always flushed, while the physical are only on demand.
3113	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3114	* have to look into that later because it will have a bad influence on the performance.
3115	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3116	* bird: Yes, but that won't work for aliases.
3117	*/
3118	/** @todo this MUST go away. See #1557. */
3119	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3120	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3121	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3122	#endif
3123
3124	#ifdef PGMPOOL_WITH_MONITORING
3125	int rc = pgmPoolSyncCR3(pVM);
3126	if (rc != VINF_SUCCESS)
3127	return rc;
3128	#endif
3129
3130	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3131	/*
3132	* Nested / EPT - almost no work.
3133	*/
3134	/** @todo check if this is really necessary */
3135	HWACCMFlushTLB(pVM);
3136	return VINF_SUCCESS;
3137
3138	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3139	/*
3140	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3141	* out the shadow parts when the guest modifies its tables.
3142	*/
3143	return VINF_SUCCESS;
3144
3145	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3146	/*
3147	* PAE and 32-bit legacy mode (shadow).
3148	* (Guest PAE, 32-bit legacy, protected and real modes.)
3149	*/
3150	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3151	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3152
3153	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3154	bool const fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3155
3156	/*
3157	* Get page directory addresses.
3158	*/
3159	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3160	PX86PDE pPDEDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, 0);
3161	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
3162	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3163	PX86PDEPAE pPDEDst = NULL;
3164	# endif
3165	# endif
3166
3167	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3168	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3169	Assert(pPDSrc);
3170	# ifndef IN_RC
3171	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3172	# endif
3173	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3174
3175	/*
3176	* Iterate the the CR3 page.
3177	*/
3178	PPGMMAPPING pMapping;
3179	unsigned iPdNoMapping;
3180	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3181	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3182
3183	/* Only check mappings if they are supposed to be put into the shadow page table. */
3184	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3185	{
3186	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3187	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3188	}
3189	else
3190	{
3191	pMapping = 0;
3192	iPdNoMapping = ~0U;
3193	}
3194
3195	# if PGM_GST_TYPE == PGM_TYPE_PAE
3196	for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
3197	{
3198	unsigned iPDSrc;
3199	X86PDPE PdpeSrc;
3200	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3201	PX86PDEPAE pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT);
3202	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3203
3204	if (pPDSrc == NULL)
3205	{
3206	/* PDPE not present */
3207	if (pPdptDst->a[iPdpt].n.u1Present)
3208	{
3209	LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
3210	/* for each page directory entry */
3211	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3212	{
3213	if ( pPDEDst[iPD].n.u1Present
3214	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3215	{
3216	pgmPoolFree(pVM, pPDEDst[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
3217	pPDEDst[iPD].u = 0;
3218	}
3219	}
3220	}
3221	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
3222	pPdptDst->a[iPdpt].n.u1Present = 0;
3223	continue;
3224	}
3225	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3226	{
3227	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3228	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3229	{
3230	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3231	if (!(iPD & (X86_PG_PAE_ENTRIES - 1))) /* Start of new PD. */
3232	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)iPD << GST_PD_SHIFT);
3233	# endif
3234	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3235	Assert(pgmShwGet32BitPDEPtr(&pVM->pgm.s, (uint32_t)iPD << SHW_PD_SHIFT) == pPDEDst);
3236	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3237	# ifdef VBOX_STRICT
3238	RTGCPTR GCPtrStrict = (uint32_t)iPD << GST_PD_SHIFT;
3239	# if PGM_GST_TYPE == PGM_TYPE_PAE
3240	GCPtrStrict \|= iPdpt << X86_PDPT_SHIFT;
3241	# endif
3242	AssertMsg(pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict) == pPDEDst, ("%p vs %p (%RGv)\n", pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict), pPDEDst, GCPtrStrict));
3243	# endif /* VBOX_STRICT */
3244	# endif
3245	GSTPDE PdeSrc = pPDSrc->a[iPD];
3246	if ( PdeSrc.n.u1Present
3247	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3248	{
3249	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3250	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3251	&& !defined(PGM_WITHOUT_MAPPINGS)
3252
3253	/*
3254	* Check for conflicts with GC mappings.
3255	*/
3256	# if PGM_GST_TYPE == PGM_TYPE_PAE
3257	if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
3258	# else
3259	if (iPD == iPdNoMapping)
3260	# endif
3261	{
3262	if (pVM->pgm.s.fMappingsFixed)
3263	{
3264	/* It's fixed, just skip the mapping. */
3265	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3266	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3267	iPD += cPTs - 1;
3268	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3269	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3270	# else
3271	pPDEDst += cPTs;
3272	# endif
3273	pMapping = pMapping->CTX_SUFF(pNext);
3274	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3275	continue;
3276	}
3277	# ifdef IN_RING3
3278	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3279	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3280	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3281	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3282	# endif
3283	if (RT_FAILURE(rc))
3284	return rc;
3285
3286	/*
3287	* Update iPdNoMapping and pMapping.
3288	*/
3289	pMapping = pVM->pgm.s.pMappingsR3;
3290	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3291	pMapping = pMapping->pNextR3;
3292	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3293	# else /* !IN_RING3 */
3294	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3295	return VINF_PGM_SYNC_CR3;
3296	# endif /* !IN_RING3 */
3297	}
3298	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3299	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3300	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3301
3302	/*
3303	* Sync page directory entry.
3304	*
3305	* The current approach is to allocated the page table but to set
3306	* the entry to not-present and postpone the page table synching till
3307	* it's actually used.
3308	*/
3309	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3310	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3311	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3312	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3313	# else
3314	const unsigned iPdShw = iPD; NOREF(iPdShw);
3315	# endif
3316	{
3317	SHWPDE PdeDst = *pPDEDst;
3318	if (PdeDst.n.u1Present)
3319	{
3320	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3321	RTGCPHYS GCPhys;
3322	if ( !PdeSrc.b.u1Size
3323	\|\| !fBigPagesSupported)
3324	{
3325	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3326	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3327	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3328	GCPhys \|= i * (PAGE_SIZE / 2);
3329	# endif
3330	}
3331	else
3332	{
3333	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3334	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3335	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3336	GCPhys \|= i * X86_PAGE_2M_SIZE;
3337	# endif
3338	}
3339
3340	if ( pShwPage->GCPhys == GCPhys
3341	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3342	&& ( pShwPage->fCached
3343	\|\| ( !fGlobal
3344	&& ( false
3345	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3346	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3347	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3348	\|\| ( !pShwPage->fSeenNonGlobal
3349	&& (cr4 & X86_CR4_PGE))
3350	# endif
3351	)
3352	)
3353	)
3354	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3355	\|\| ( fBigPagesSupported
3356	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3357	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3358	)
3359	)
3360	{
3361	# ifdef VBOX_WITH_STATISTICS
3362	if ( !fGlobal
3363	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3364	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3365	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3366	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3367	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3368	else
3369	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3370	# endif /* VBOX_WITH_STATISTICS */
3371	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3372	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3373	//# ifdef PGMPOOL_WITH_CACHE
3374	// pgmPoolCacheUsed(pPool, pShwPage);
3375	//# endif
3376	}
3377	else
3378	{
3379	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3380	pPDEDst->u = 0;
3381	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3382	}
3383	}
3384	else
3385	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3386
3387	/* advance */
3388	pPDEDst++;
3389	} /* foreach 2MB PAE PDE in 4MB guest PDE */
3390	}
3391	# if PGM_GST_TYPE == PGM_TYPE_PAE
3392	else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
3393	# else
3394	else if (iPD != iPdNoMapping)
3395	# endif
3396	{
3397	/*
3398	* Check if there is any page directory to mark not present here.
3399	*/
3400	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3401	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3402	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3403	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES;
3404	# else
3405	const unsigned iPdShw = iPD;
3406	# endif
3407	{
3408	if (pPDEDst->n.u1Present)
3409	{
3410	pgmPoolFree(pVM, pPDEDst->u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdShw);
3411	pPDEDst->u = 0;
3412	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3413	}
3414	pPDEDst++;
3415	}
3416	}
3417	else
3418	{
3419	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3420	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3421	&& !defined(PGM_WITHOUT_MAPPINGS)
3422
3423	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3424
3425	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3426	if (pVM->pgm.s.fMappingsFixed)
3427	{
3428	/* It's fixed, just skip the mapping. */
3429	pMapping = pMapping->CTX_SUFF(pNext);
3430	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3431	}
3432	else
3433	{
3434	/*
3435	* Check for conflicts for subsequent pagetables
3436	* and advance to the next mapping.
3437	*/
3438	iPdNoMapping = ~0U;
3439	unsigned iPT = cPTs;
3440	while (iPT-- > 1)
3441	{
3442	if ( pPDSrc->a[iPD + iPT].n.u1Present
3443	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3444	{
3445	# ifdef IN_RING3
3446	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3447	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3448	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3449	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3450	# endif
3451	if (RT_FAILURE(rc))
3452	return rc;
3453
3454	/*
3455	* Update iPdNoMapping and pMapping.
3456	*/
3457	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3458	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3459	pMapping = pMapping->CTX_SUFF(pNext);
3460	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3461	break;
3462	# else
3463	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3464	return VINF_PGM_SYNC_CR3;
3465	# endif
3466	}
3467	}
3468	if (iPdNoMapping == ~0U && pMapping)
3469	{
3470	pMapping = pMapping->CTX_SUFF(pNext);
3471	if (pMapping)
3472	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3473	}
3474	}
3475
3476	/* advance. */
3477	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3478	iPD += cPTs - 1;
3479	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3480	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3481	# else
3482	pPDEDst += cPTs;
3483	# endif
3484	# if PGM_GST_TYPE != PGM_SHW_TYPE
3485	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3486	# endif
3487	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3488	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3489	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3490	}
3491
3492	} /* for iPD */
3493	} /* for each PDPTE (PAE) */
3494	return VINF_SUCCESS;
3495
3496	# else /* guest real and protected mode */
3497	return VINF_SUCCESS;
3498	# endif
3499	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3500	}
3501
3502
3503
3504
3505	#ifdef VBOX_STRICT
3506	#ifdef IN_RC
3507	# undef AssertMsgFailed
3508	# define AssertMsgFailed Log
3509	#endif
3510	#ifdef IN_RING3
3511	# include <VBox/dbgf.h>
3512
3513	/**
3514	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3515	*
3516	* @returns VBox status code (VINF_SUCCESS).
3517	* @param pVM The VM handle.
3518	* @param cr3 The root of the hierarchy.
3519	* @param crr The cr4, only PAE and PSE is currently used.
3520	* @param fLongMode Set if long mode, false if not long mode.
3521	* @param cMaxDepth Number of levels to dump.
3522	* @param pHlp Pointer to the output functions.
3523	*/
3524	__BEGIN_DECLS
3525	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3526	__END_DECLS
3527
3528	#endif
3529
3530	/**
3531	* Checks that the shadow page table is in sync with the guest one.
3532	*
3533	* @returns The number of errors.
3534	* @param pVM The virtual machine.
3535	* @param cr3 Guest context CR3 register
3536	* @param cr4 Guest context CR4 register
3537	* @param GCPtr Where to start. Defaults to 0.
3538	* @param cb How much to check. Defaults to everything.
3539	*/
3540	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3541	{
3542	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3543	return 0;
3544	#else
3545	unsigned cErrors = 0;
3546
3547	#if PGM_GST_TYPE == PGM_TYPE_PAE
3548	/** @todo currently broken; crashes below somewhere */
3549	AssertFailed();
3550	#endif
3551
3552	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3553	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3554	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3555
3556	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3557	bool fBigPagesSupported = true;
3558	# else
3559	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3560	# endif
3561	PPGM pPGM = &pVM->pgm.s;
3562	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3563	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3564	# ifndef IN_RING0
3565	RTHCPHYS HCPhys; /* general usage. */
3566	# endif
3567	int rc;
3568
3569	/*
3570	* Check that the Guest CR3 and all its mappings are correct.
3571	*/
3572	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3573	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3574	false);
3575	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3576	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3577	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3578	# else
3579	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3580	# endif
3581	AssertRCReturn(rc, 1);
3582	HCPhys = NIL_RTHCPHYS;
3583	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3584	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3585	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3586	RTGCPHYS GCPhys;
3587	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3588	AssertRCReturn(rc, 1);
3589	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3590	# endif
3591	# endif /* !IN_RING0 */
3592
3593	/*
3594	* Get and check the Shadow CR3.
3595	*/
3596	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3597	unsigned cPDEs = X86_PG_ENTRIES;
3598	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3599	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3600	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3601	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3602	# else
3603	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3604	# endif
3605	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3606	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3607	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3608	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3609	# endif
3610	if (cb != ~(RTGCPTR)0)
3611	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3612
3613	/** @todo call the other two PGMAssert() functions. /
3614
3615	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3616	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3617	# endif
3618
3619	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3620	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3621
3622	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3623	{
3624	PPGMPOOLPAGE pShwPdpt = NULL;
3625	PX86PML4E pPml4eSrc;
3626	PX86PML4E pPml4eDst;
3627	RTGCPHYS GCPhysPdptSrc;
3628
3629	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3630	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3631
3632	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3633	if (!pPml4eDst->n.u1Present)
3634	{
3635	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3636	continue;
3637	}
3638
3639	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3640	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3641
3642	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3643	{
3644	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3645	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3646	cErrors++;
3647	continue;
3648	}
3649
3650	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3651	{
3652	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3653	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3654	cErrors++;
3655	continue;
3656	}
3657
3658	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3659	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3660	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3661	{
3662	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3663	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3664	cErrors++;
3665	continue;
3666	}
3667	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3668	{
3669	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3670
3671	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3672	/*
3673	* Check the PDPTEs too.
3674	*/
3675	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3676
3677	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3678	{
3679	unsigned iPDSrc;
3680	PPGMPOOLPAGE pShwPde = NULL;
3681	PX86PDPE pPdpeDst;
3682	RTGCPHYS GCPhysPdeSrc;
3683	# if PGM_GST_TYPE == PGM_TYPE_PAE
3684	X86PDPE PdpeSrc;
3685	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3686	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3687	# else
3688	PX86PML4E pPml4eSrc;
3689	X86PDPE PdpeSrc;
3690	PX86PDPT pPdptDst;
3691	PX86PDPAE pPDDst;
3692	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3693
3694	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3695	if (rc != VINF_SUCCESS)
3696	{
3697	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3698	GCPtr += 512 * _2M;
3699	continue; /* next PDPTE */
3700	}
3701	Assert(pPDDst);
3702	# endif
3703	Assert(iPDSrc == 0);
3704
3705	pPdpeDst = &pPdptDst->a[iPdpt];
3706
3707	if (!pPdpeDst->n.u1Present)
3708	{
3709	GCPtr += 512 * _2M;
3710	continue; /* next PDPTE */
3711	}
3712
3713	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3714	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3715
3716	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3717	{
3718	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3719	GCPtr += 512 * _2M;
3720	cErrors++;
3721	continue;
3722	}
3723
3724	if (GCPhysPdeSrc != pShwPde->GCPhys)
3725	{
3726	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3727	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3728	# else
3729	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3730	# endif
3731	GCPtr += 512 * _2M;
3732	cErrors++;
3733	continue;
3734	}
3735
3736	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3737	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3738	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3739	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3740	{
3741	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3742	GCPtr += 512 * _2M;
3743	cErrors++;
3744	continue;
3745	}
3746	# endif
3747
3748	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3749	{
3750	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3751	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3752	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3753	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3754	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
3755	# endif
3756	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3757	/*
3758	* Iterate the shadow page directory.
3759	*/
3760	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3761	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3762
3763	for (;
3764	iPDDst < cPDEs;
3765	iPDDst++, GCPtr += cIncrement)
3766	{
3767	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3768	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3769	# else
3770	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3771	# endif
3772	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3773	{
3774	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3775	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3776	{
3777	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3778	cErrors++;
3779	continue;
3780	}
3781	}
3782	else if ( (PdeDst.u & X86_PDE_P)
3783	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3784	)
3785	{
3786	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3787	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3788	if (!pPoolPage)
3789	{
3790	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3791	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3792	cErrors++;
3793	continue;
3794	}
3795	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3796
3797	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3798	{
3799	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3800	GCPtr, (uint64_t)PdeDst.u));
3801	cErrors++;
3802	}
3803
3804	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3805	{
3806	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3807	GCPtr, (uint64_t)PdeDst.u));
3808	cErrors++;
3809	}
3810
3811	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3812	if (!PdeSrc.n.u1Present)
3813	{
3814	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3815	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3816	cErrors++;
3817	continue;
3818	}
3819
3820	if ( !PdeSrc.b.u1Size
3821	\|\| !fBigPagesSupported)
3822	{
3823	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3824	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3825	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3826	# endif
3827	}
3828	else
3829	{
3830	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3831	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3832	{
3833	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3834	GCPtr, (uint64_t)PdeSrc.u));
3835	cErrors++;
3836	continue;
3837	}
3838	# endif
3839	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3840	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3841	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3842	# endif
3843	}
3844
3845	if ( pPoolPage->enmKind
3846	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3847	{
3848	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3849	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3850	cErrors++;
3851	}
3852
3853	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3854	if (!pPhysPage)
3855	{
3856	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3857	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3858	cErrors++;
3859	continue;
3860	}
3861
3862	if (GCPhysGst != pPoolPage->GCPhys)
3863	{
3864	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3865	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3866	cErrors++;
3867	continue;
3868	}
3869
3870	if ( !PdeSrc.b.u1Size
3871	\|\| !fBigPagesSupported)
3872	{
3873	/*
3874	* Page Table.
3875	*/
3876	const GSTPT *pPTSrc;
3877	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3878	if (RT_FAILURE(rc))
3879	{
3880	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3881	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3882	cErrors++;
3883	continue;
3884	}
3885	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3886	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3887	{
3888	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3889	// (This problem will go away when/if we shadow multiple CR3s.)
3890	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3891	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3892	cErrors++;
3893	continue;
3894	}
3895	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3896	{
3897	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3898	GCPtr, (uint64_t)PdeDst.u));
3899	cErrors++;
3900	continue;
3901	}
3902
3903	/* iterate the page table. */
3904	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3905	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3906	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3907	# else
3908	const unsigned offPTSrc = 0;
3909	# endif
3910	for (unsigned iPT = 0, off = 0;
3911	iPT < RT_ELEMENTS(pPTDst->a);
3912	iPT++, off += PAGE_SIZE)
3913	{
3914	const SHWPTE PteDst = pPTDst->a[iPT];
3915
3916	/* skip not-present entries. */
3917	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3918	continue;
3919	Assert(PteDst.n.u1Present);
3920
3921	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3922	if (!PteSrc.n.u1Present)
3923	{
3924	# ifdef IN_RING3
3925	PGMAssertHandlerAndFlagsInSync(pVM);
3926	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3927	# endif
3928	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3929	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3930	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3931	cErrors++;
3932	continue;
3933	}
3934
3935	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3936	# if 1 /** @todo sync accessed bit properly... */
3937	fIgnoreFlags \|= X86_PTE_A;
3938	# endif
3939
3940	/* match the physical addresses */
3941	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3942	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3943
3944	# ifdef IN_RING3
3945	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3946	if (RT_FAILURE(rc))
3947	{
3948	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3949	{
3950	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3951	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3952	cErrors++;
3953	continue;
3954	}
3955	}
3956	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3957	{
3958	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3959	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3960	cErrors++;
3961	continue;
3962	}
3963	# endif
3964
3965	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3966	if (!pPhysPage)
3967	{
3968	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3969	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3970	{
3971	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3972	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3973	cErrors++;
3974	continue;
3975	}
3976	# endif
3977	if (PteDst.n.u1Write)
3978	{
3979	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3980	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3981	cErrors++;
3982	}
3983	fIgnoreFlags \|= X86_PTE_RW;
3984	}
3985	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3986	{
3987	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3988	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3989	cErrors++;
3990	continue;
3991	}
3992
3993	/* flags */
3994	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3995	{
3996	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3997	{
3998	if (PteDst.n.u1Write)
3999	{
4000	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4001	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4002	cErrors++;
4003	continue;
4004	}
4005	fIgnoreFlags \|= X86_PTE_RW;
4006	}
4007	else
4008	{
4009	if (PteDst.n.u1Present)
4010	{
4011	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4012	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4013	cErrors++;
4014	continue;
4015	}
4016	fIgnoreFlags \|= X86_PTE_P;
4017	}
4018	}
4019	else
4020	{
4021	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4022	{
4023	if (PteDst.n.u1Write)
4024	{
4025	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4026	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4027	cErrors++;
4028	continue;
4029	}
4030	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4031	{
4032	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4033	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4034	cErrors++;
4035	continue;
4036	}
4037	if (PteDst.n.u1Dirty)
4038	{
4039	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4040	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4041	cErrors++;
4042	}
4043	# if 0 /** @todo sync access bit properly... */
4044	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4045	{
4046	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4047	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4048	cErrors++;
4049	}
4050	fIgnoreFlags \|= X86_PTE_RW;
4051	# else
4052	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4053	# endif
4054	}
4055	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4056	{
4057	/* access bit emulation (not implemented). */
4058	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4059	{
4060	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4061	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4062	cErrors++;
4063	continue;
4064	}
4065	if (!PteDst.n.u1Accessed)
4066	{
4067	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4068	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4069	cErrors++;
4070	}
4071	fIgnoreFlags \|= X86_PTE_P;
4072	}
4073	# ifdef DEBUG_sandervl
4074	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4075	# endif
4076	}
4077
4078	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4079	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4080	)
4081	{
4082	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4083	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4084	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4085	cErrors++;
4086	continue;
4087	}
4088	} /* foreach PTE */
4089	}
4090	else
4091	{
4092	/*
4093	* Big Page.
4094	*/
4095	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4096	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4097	{
4098	if (PdeDst.n.u1Write)
4099	{
4100	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4101	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4102	cErrors++;
4103	continue;
4104	}
4105	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4106	{
4107	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4108	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4109	cErrors++;
4110	continue;
4111	}
4112	# if 0 /** @todo sync access bit properly... */
4113	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4114	{
4115	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4116	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4117	cErrors++;
4118	}
4119	fIgnoreFlags \|= X86_PTE_RW;
4120	# else
4121	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4122	# endif
4123	}
4124	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4125	{
4126	/* access bit emulation (not implemented). */
4127	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4128	{
4129	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4130	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4131	cErrors++;
4132	continue;
4133	}
4134	if (!PdeDst.n.u1Accessed)
4135	{
4136	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4137	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4138	cErrors++;
4139	}
4140	fIgnoreFlags \|= X86_PTE_P;
4141	}
4142
4143	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4144	{
4145	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4146	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4147	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4148	cErrors++;
4149	}
4150
4151	/* iterate the page table. */
4152	for (unsigned iPT = 0, off = 0;
4153	iPT < RT_ELEMENTS(pPTDst->a);
4154	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4155	{
4156	const SHWPTE PteDst = pPTDst->a[iPT];
4157
4158	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4159	{
4160	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4161	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4162	cErrors++;
4163	}
4164
4165	/* skip not-present entries. */
4166	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4167	continue;
4168
4169	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4170
4171	/* match the physical addresses */
4172	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4173
4174	# ifdef IN_RING3
4175	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4176	if (RT_FAILURE(rc))
4177	{
4178	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4179	{
4180	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4181	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4182	cErrors++;
4183	}
4184	}
4185	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4186	{
4187	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4188	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4189	cErrors++;
4190	continue;
4191	}
4192	# endif
4193	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4194	if (!pPhysPage)
4195	{
4196	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4197	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4198	{
4199	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4200	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4201	cErrors++;
4202	continue;
4203	}
4204	# endif
4205	if (PteDst.n.u1Write)
4206	{
4207	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4208	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4209	cErrors++;
4210	}
4211	fIgnoreFlags \|= X86_PTE_RW;
4212	}
4213	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4214	{
4215	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4217	cErrors++;
4218	continue;
4219	}
4220
4221	/* flags */
4222	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4223	{
4224	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4225	{
4226	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4227	{
4228	if (PteDst.n.u1Write)
4229	{
4230	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4232	cErrors++;
4233	continue;
4234	}
4235	fIgnoreFlags \|= X86_PTE_RW;
4236	}
4237	}
4238	else
4239	{
4240	if (PteDst.n.u1Present)
4241	{
4242	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4243	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4244	cErrors++;
4245	continue;
4246	}
4247	fIgnoreFlags \|= X86_PTE_P;
4248	}
4249	}
4250
4251	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4252	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4253	)
4254	{
4255	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4256	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4257	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4258	cErrors++;
4259	continue;
4260	}
4261	} /* for each PTE */
4262	}
4263	}
4264	/* not present */
4265
4266	} /* for each PDE */
4267
4268	} /* for each PDPTE */
4269
4270	} /* for each PML4E */
4271
4272	# ifdef DEBUG
4273	if (cErrors)
4274	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4275	# endif
4276
4277	#endif /* GST == 32BIT, PAE or AMD64 */
4278	return cErrors;
4279
4280	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4281	}
4282	#endif /* VBOX_STRICT */
4283

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 14251

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