PGMAllBth.h@ 16203

Last change on this file since 16203 was 16203, checked in by vboxsync, 16 years ago
Updates in preparation for PGM pool based paging everywhere.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 190.9 KB

Line
1	/* $Id: PGMAllBth.h 16203 2009-01-23 16:36:23Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69
70	#ifndef IN_RING3
71	/**
72	* #PF Handler for raw-mode guest execution.
73	*
74	* @returns VBox status code (appropriate for trap handling and GC return).
75	* @param pVM VM Handle.
76	* @param uErr The trap error code.
77	* @param pRegFrame Trap register frame.
78	* @param pvFault The fault address.
79	*/
80	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
81	{
82	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
83	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
84	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
85
86	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
87	/*
88	* Hide the instruction fetch trap indicator for now.
89	*/
90	/** @todo NXE will change this and we must fix NXE in the switcher too! */
91	if (uErr & X86_TRAP_PF_ID)
92	{
93	uErr &= ~X86_TRAP_PF_ID;
94	TRPMSetErrorCode(pVM, uErr);
95	}
96	# endif
97
98	/*
99	* Get PDs.
100	*/
101	int rc;
102	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
103	# if PGM_GST_TYPE == PGM_TYPE_32BIT
104	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
105	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
106
107	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
108
109	# if PGM_GST_TYPE == PGM_TYPE_PAE
110	unsigned iPDSrc;
111	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
114	unsigned iPDSrc;
115	PX86PML4E pPml4eSrc;
116	X86PDPE PdpeSrc;
117	PGSTPD pPDSrc;
118
119	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
120	Assert(pPml4eSrc);
121	# endif
122	/* Quick check for a valid guest trap. */
123	if (!pPDSrc)
124	{
125	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
126	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
127	# else
128	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
129	# endif
130	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
131	TRPMSetErrorCode(pVM, uErr);
132	return VINF_EM_RAW_GUEST_TRAP;
133	}
134	# endif
135
136	# else /* !PGM_WITH_PAGING */
137	PGSTPD pPDSrc = NULL;
138	const unsigned iPDSrc = 0;
139	# endif /* !PGM_WITH_PAGING */
140
141
142	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
143	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
144	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
145
146	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
147	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
148	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
149
150	/* Did we mark the PDPT as not present in SyncCR3? */
151	unsigned iPdpt = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
152	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
153	if (!pPdptDst->a[iPdpt].n.u1Present)
154	pPdptDst->a[iPdpt].n.u1Present = 1;
155
156	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
157	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
158	PX86PDPAE pPDDst;
159	# if PGM_GST_TYPE == PGM_TYPE_PROT
160	/* AMD-V nested paging */
161	X86PML4E Pml4eSrc;
162	X86PDPE PdpeSrc;
163	PX86PML4E pPml4eSrc = &Pml4eSrc;
164
165	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
166	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
167	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
168	# endif
169
170	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
171	if (rc != VINF_SUCCESS)
172	{
173	AssertRC(rc);
174	return rc;
175	}
176	Assert(pPDDst);
177
178	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
179	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
180	PEPTPD pPDDst;
181
182	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
183	if (rc != VINF_SUCCESS)
184	{
185	AssertRC(rc);
186	return rc;
187	}
188	Assert(pPDDst);
189	# endif
190
191	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
192	/*
193	* If we successfully correct the write protection fault due to dirty bit
194	* tracking, or this page fault is a genuine one, then return immediately.
195	*/
196	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
197	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
198	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
199	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
200	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
201	{
202	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
203	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
204	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
205	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
206	}
207
208	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
209	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
210
211	/*
212	* A common case is the not-present error caused by lazy page table syncing.
213	*
214	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
215	* so we can safely assume that the shadow PT is present when calling SyncPage later.
216	*
217	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
218	* of mapping conflict and defer to SyncCR3 in R3.
219	* (Again, we do NOT support access handlers for non-present guest pages.)
220	*
221	*/
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
224	# else
225	GSTPDE PdeSrc;
226	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
227	PdeSrc.n.u1Present = 1;
228	PdeSrc.n.u1Write = 1;
229	PdeSrc.n.u1Accessed = 1;
230	PdeSrc.n.u1User = 1;
231	# endif
232	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
233	&& !pPDDst->a[iPDDst].n.u1Present
234	&& PdeSrc.n.u1Present
235	)
236
237	{
238	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
239	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
240	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
241	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
242	if (RT_SUCCESS(rc))
243	{
244	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
245	return rc;
246	}
247	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
248	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
249	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
250	return VINF_PGM_SYNC_CR3;
251	}
252
253	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
254	/*
255	* Check if this address is within any of our mappings.
256	*
257	* This is very fast and it's gonna save us a bit of effort below and prevent
258	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
259	* (BTW, it's impossible to have physical access handlers in a mapping.)
260	*/
261	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
262	{
263	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
264	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
265	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
266	{
267	if (pvFault < pMapping->GCPtr)
268	break;
269	if (pvFault - pMapping->GCPtr < pMapping->cb)
270	{
271	/*
272	* The first thing we check is if we've got an undetected conflict.
273	*/
274	if (!pVM->pgm.s.fMappingsFixed)
275	{
276	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
277	while (iPT-- > 0)
278	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
279	{
280	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
281	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
282	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
283	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
284	return VINF_PGM_SYNC_CR3;
285	}
286	}
287
288	/*
289	* Check if the fault address is in a virtual page access handler range.
290	*/
291	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
292	if ( pCur
293	&& pvFault - pCur->Core.Key < pCur->cb
294	&& uErr & X86_TRAP_PF_RW)
295	{
296	# ifdef IN_RC
297	STAM_PROFILE_START(&pCur->Stat, h);
298	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
299	STAM_PROFILE_STOP(&pCur->Stat, h);
300	# else
301	AssertFailed();
302	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
303	# endif
304	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
305	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
306	return rc;
307	}
308
309	/*
310	* Pretend we're not here and let the guest handle the trap.
311	*/
312	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
313	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
314	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
315	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
316	return VINF_EM_RAW_GUEST_TRAP;
317	}
318	}
319	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
320	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
321	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
322
323	/*
324	* Check if this fault address is flagged for special treatment,
325	* which means we'll have to figure out the physical address and
326	* check flags associated with it.
327	*
328	* ASSUME that we can limit any special access handling to pages
329	* in page tables which the guest believes to be present.
330	*/
331	if (PdeSrc.n.u1Present)
332	{
333	RTGCPHYS GCPhys = NIL_RTGCPHYS;
334
335	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
336	# if PGM_GST_TYPE == PGM_TYPE_AMD64
337	bool fBigPagesSupported = true;
338	# else
339	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
340	# endif
341	if ( PdeSrc.b.u1Size
342	&& fBigPagesSupported)
343	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
344	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
345	else
346	{
347	PGSTPT pPTSrc;
348	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
349	if (RT_SUCCESS(rc))
350	{
351	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
352	if (pPTSrc->a[iPTESrc].n.u1Present)
353	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
354	}
355	}
356	# else
357	/* No paging so the fault address is the physical address */
358	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
359	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
360
361	/*
362	* If we have a GC address we'll check if it has any flags set.
363	*/
364	if (GCPhys != NIL_RTGCPHYS)
365	{
366	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
367
368	PPGMPAGE pPage;
369	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
370	if (RT_SUCCESS(rc))
371	{
372	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
373	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
374	{
375	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
376	{
377	/*
378	* Physical page access handler.
379	*/
380	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
381	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
382	if (pCur)
383	{
384	# ifdef PGM_SYNC_N_PAGES
385	/*
386	* If the region is write protected and we got a page not present fault, then sync
387	* the pages. If the fault was caused by a read, then restart the instruction.
388	* In case of write access continue to the GC write handler.
389	*
390	* ASSUMES that there is only one handler per page or that they have similar write properties.
391	*/
392	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
393	&& !(uErr & X86_TRAP_PF_P))
394	{
395	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
396	if ( RT_FAILURE(rc)
397	\|\| !(uErr & X86_TRAP_PF_RW)
398	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
399	{
400	AssertRC(rc);
401	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
402	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
403	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
404	return rc;
405	}
406	}
407	# endif
408
409	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
410	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
411	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
412
413	# if defined(IN_RC) \|\| defined(IN_RING0)
414	if (pCur->CTX_SUFF(pfnHandler))
415	{
416	STAM_PROFILE_START(&pCur->Stat, h);
417	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
418	STAM_PROFILE_STOP(&pCur->Stat, h);
419	}
420	else
421	# endif
422	rc = VINF_EM_RAW_EMULATE_INSTR;
423	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
424	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
425	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
426	return rc;
427	}
428	}
429	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
430	else
431	{
432	# ifdef PGM_SYNC_N_PAGES
433	/*
434	* If the region is write protected and we got a page not present fault, then sync
435	* the pages. If the fault was caused by a read, then restart the instruction.
436	* In case of write access continue to the GC write handler.
437	*/
438	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
439	&& !(uErr & X86_TRAP_PF_P))
440	{
441	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
442	if ( RT_FAILURE(rc)
443	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
444	\|\| !(uErr & X86_TRAP_PF_RW))
445	{
446	AssertRC(rc);
447	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
448	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
449	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
450	return rc;
451	}
452	}
453	# endif
454	/*
455	* Ok, it's an virtual page access handler.
456	*
457	* Since it's faster to search by address, we'll do that first
458	* and then retry by GCPhys if that fails.
459	*/
460	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
461	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
462	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
463	*/
464	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
465	if (pCur)
466	{
467	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
468	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
469	\|\| !(uErr & X86_TRAP_PF_P)
470	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
471	("Unexpected trap for virtual handler: %RGv (phys=%RGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
472
473	if ( pvFault - pCur->Core.Key < pCur->cb
474	&& ( uErr & X86_TRAP_PF_RW
475	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
476	{
477	# ifdef IN_RC
478	STAM_PROFILE_START(&pCur->Stat, h);
479	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
480	STAM_PROFILE_STOP(&pCur->Stat, h);
481	# else
482	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
483	# endif
484	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
485	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
486	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
487	return rc;
488	}
489	/* Unhandled part of a monitored page */
490	}
491	else
492	{
493	/* Check by physical address. */
494	PPGMVIRTHANDLER pCur;
495	unsigned iPage;
496	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
497	&pCur, &iPage);
498	Assert(RT_SUCCESS(rc) \|\| !pCur);
499	if ( pCur
500	&& ( uErr & X86_TRAP_PF_RW
501	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
502	{
503	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
504	# ifdef IN_RC
505	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
506	Assert(off < pCur->cb);
507	STAM_PROFILE_START(&pCur->Stat, h);
508	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
509	STAM_PROFILE_STOP(&pCur->Stat, h);
510	# else
511	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
512	# endif
513	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
514	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
515	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
516	return rc;
517	}
518	}
519	}
520	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
521
522	/*
523	* There is a handled area of the page, but this fault doesn't belong to it.
524	* We must emulate the instruction.
525	*
526	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
527	* we first check if this was a page-not-present fault for a page with only
528	* write access handlers. Restart the instruction if it wasn't a write access.
529	*/
530	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
531
532	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
533	&& !(uErr & X86_TRAP_PF_P))
534	{
535	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
536	if ( RT_FAILURE(rc)
537	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
538	\|\| !(uErr & X86_TRAP_PF_RW))
539	{
540	AssertRC(rc);
541	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
542	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
543	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
544	return rc;
545	}
546	}
547
548	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
549	* It's writing to an unhandled part of the LDT page several million times.
550	*/
551	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
552	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
553	rc, pPage->HCPhys,
554	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
555	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
556	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
557	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
558	return rc;
559	} /* if any kind of handler */
560
561	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
562	if (uErr & X86_TRAP_PF_P)
563	{
564	/*
565	* The page isn't marked, but it might still be monitored by a virtual page access handler.
566	* (ASSUMES no temporary disabling of virtual handlers.)
567	*/
568	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
569	* we should correct both the shadow page table and physical memory flags, and not only check for
570	* accesses within the handler region but for access to pages with virtual handlers. */
571	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
572	if (pCur)
573	{
574	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
575	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
576	\|\| !(uErr & X86_TRAP_PF_P)
577	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
578	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
579
580	if ( pvFault - pCur->Core.Key < pCur->cb
581	&& ( uErr & X86_TRAP_PF_RW
582	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
583	{
584	# ifdef IN_RC
585	STAM_PROFILE_START(&pCur->Stat, h);
586	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
587	STAM_PROFILE_STOP(&pCur->Stat, h);
588	# else
589	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
590	# endif
591	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
592	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
593	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
594	return rc;
595	}
596	}
597	}
598	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
599	}
600	else
601	{
602	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
603	* back to the recompiler to emulate the instruction.
604	*/
605	LogFlow(("pgmPhysGetPageEx %RGp failed with %Rrc\n", GCPhys, rc));
606	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
607	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
608	return VINF_EM_RAW_EMULATE_INSTR;
609	}
610
611	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
612
613	# ifdef PGM_OUT_OF_SYNC_IN_GC
614	/*
615	* We are here only if page is present in Guest page tables and trap is not handled
616	* by our handlers.
617	* Check it for page out-of-sync situation.
618	*/
619	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
620
621	if (!(uErr & X86_TRAP_PF_P))
622	{
623	/*
624	* Page is not present in our page tables.
625	* Try to sync it!
626	* BTW, fPageShw is invalid in this branch!
627	*/
628	if (uErr & X86_TRAP_PF_US)
629	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
630	else /* supervisor */
631	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
632
633	# if defined(LOG_ENABLED) && !defined(IN_RING0)
634	RTGCPHYS GCPhys;
635	uint64_t fPageGst;
636	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
637	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
638	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
639	# endif /* LOG_ENABLED */
640
641	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
642	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
643	{
644	uint64_t fPageGst;
645	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
646	if ( RT_SUCCESS(rc)
647	&& !(fPageGst & X86_PTE_US))
648	{
649	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
650	if ( pvFault == (RTGCPTR)pRegFrame->eip
651	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
652	# ifdef CSAM_DETECT_NEW_CODE_PAGES
653	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
654	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
655	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
656	)
657	{
658	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
659	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
660	if (rc != VINF_SUCCESS)
661	{
662	/*
663	* CSAM needs to perform a job in ring 3.
664	*
665	* Sync the page before going to the host context; otherwise we'll end up in a loop if
666	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
667	*/
668	LogFlow(("CSAM ring 3 job\n"));
669	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
670	AssertRC(rc2);
671
672	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
673	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
674	return rc;
675	}
676	}
677	# ifdef CSAM_DETECT_NEW_CODE_PAGES
678	else if ( uErr == X86_TRAP_PF_RW
679	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
680	&& pRegFrame->ecx < 0x10000)
681	{
682	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
683	* to detect loading of new code pages.
684	*/
685
686	/*
687	* Decode the instruction.
688	*/
689	RTGCPTR PC;
690	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
691	if (rc == VINF_SUCCESS)
692	{
693	DISCPUSTATE Cpu;
694	uint32_t cbOp;
695	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
696
697	/* For now we'll restrict this to rep movsw/d instructions */
698	if ( rc == VINF_SUCCESS
699	&& Cpu.pCurInstr->opcode == OP_MOVSWD
700	&& (Cpu.prefix & PREFIX_REP))
701	{
702	CSAMMarkPossibleCodePage(pVM, pvFault);
703	}
704	}
705	}
706	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
707
708	/*
709	* Mark this page as safe.
710	*/
711	/** @todo not correct for pages that contain both code and data!! */
712	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
713	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
714	}
715	}
716	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
717	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
718	if (RT_SUCCESS(rc))
719	{
720	/* The page was successfully synced, return to the guest. */
721	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
722	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
723	return VINF_SUCCESS;
724	}
725	}
726	else
727	{
728	/*
729	* A side effect of not flushing global PDEs are out of sync pages due
730	* to physical monitored regions, that are no longer valid.
731	* Assume for now it only applies to the read/write flag
732	*/
733	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
734	{
735	if (uErr & X86_TRAP_PF_US)
736	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
737	else /* supervisor */
738	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
739
740
741	/*
742	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
743	*/
744	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
745	if (RT_SUCCESS(rc))
746	{
747	/*
748	* Page was successfully synced, return to guest.
749	*/
750	# ifdef VBOX_STRICT
751	RTGCPHYS GCPhys;
752	uint64_t fPageGst;
753	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
754	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
755	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
756
757	uint64_t fPageShw;
758	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
759	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
760	# endif /* VBOX_STRICT */
761	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
762	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
763	return VINF_SUCCESS;
764	}
765
766	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
767	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
768	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
769	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
770	{
771	uint64_t fPageGst;
772	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
773	if ( RT_SUCCESS(rc)
774	&& !(fPageGst & X86_PTE_RW))
775	{
776	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
777	if (RT_SUCCESS(rc))
778	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
779	else
780	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
781	return rc;
782	}
783	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
784	}
785	}
786
787	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
788	# ifdef VBOX_STRICT
789	/*
790	* Check for VMM page flags vs. Guest page flags consistency.
791	* Currently only for debug purposes.
792	*/
793	if (RT_SUCCESS(rc))
794	{
795	/* Get guest page flags. */
796	uint64_t fPageGst;
797	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
798	if (RT_SUCCESS(rc))
799	{
800	uint64_t fPageShw;
801	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
802
803	/*
804	* Compare page flags.
805	* Note: we have AVL, A, D bits desynched.
806	*/
807	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
808	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
809	}
810	else
811	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
812	}
813	else
814	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
815	# endif /* VBOX_STRICT */
816	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
817	}
818	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
819	# endif /* PGM_OUT_OF_SYNC_IN_GC */
820	}
821	else
822	{
823	/*
824	* Page not present in Guest OS or invalid page table address.
825	* This is potential virtual page access handler food.
826	*
827	* For the present we'll say that our access handlers don't
828	* work for this case - we've already discarded the page table
829	* not present case which is identical to this.
830	*
831	* When we perchance find we need this, we will probably have AVL
832	* trees (offset based) to operate on and we can measure their speed
833	* agains mapping a page table and probably rearrange this handling
834	* a bit. (Like, searching virtual ranges before checking the
835	* physical address.)
836	*/
837	}
838	}
839
840
841	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
842	/*
843	* Conclusion, this is a guest trap.
844	*/
845	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
846	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
847	return VINF_EM_RAW_GUEST_TRAP;
848	# else
849	/* present, but not a monitored page; perhaps the guest is probing physical memory */
850	return VINF_EM_RAW_EMULATE_INSTR;
851	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
852
853
854	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
855
856	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
857	return VERR_INTERNAL_ERROR;
858	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
859	}
860	#endif /* !IN_RING3 */
861
862
863	/**
864	* Emulation of the invlpg instruction.
865	*
866	*
867	* @returns VBox status code.
868	*
869	* @param pVM VM handle.
870	* @param GCPtrPage Page to invalidate.
871	*
872	* @remark ASSUMES that the guest is updating before invalidating. This order
873	* isn't required by the CPU, so this is speculative and could cause
874	* trouble.
875	*
876	* @todo Flush page or page directory only if necessary!
877	* @todo Add a #define for simply invalidating the page.
878	*/
879	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
880	{
881	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
882	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
883	&& PGM_SHW_TYPE != PGM_TYPE_EPT
884	int rc;
885
886	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
887	/*
888	* Get the shadow PD entry and skip out if this PD isn't present.
889	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
890	*/
891	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
892	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
893	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
894
895	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
896	/* Fetch the pgm pool shadow descriptor. */
897	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
898	Assert(pShwPde);
899	# endif
900
901	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
902	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
903	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
904
905	/* If the shadow PDPE isn't present, then skip the invalidate. */
906	if (!pPdptDst->a[iPdpt].n.u1Present)
907	{
908	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
909	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
910	return VINF_SUCCESS;
911	}
912
913	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
914	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
915	PPGMPOOLPAGE pShwPde;
916	PX86PDPAE pPDDst;
917
918	/* Fetch the pgm pool shadow descriptor. */
919	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
920	AssertRCSuccessReturn(rc, rc);
921	Assert(pShwPde);
922
923	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
924	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
925	# else
926	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - pool index only atm! /;
927	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
928	# endif
929
930	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
931	/* PML4 */
932	AssertReturn(pVM->pgm.s.pShwRootR3, VERR_INTERNAL_ERROR);
933
934	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
935	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
936	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
937	PX86PDPAE pPDDst;
938	PX86PDPT pPdptDst;
939	PX86PML4E pPml4eDst;
940	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
941	if (rc != VINF_SUCCESS)
942	{
943	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
944	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
945	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
946	PGM_INVL_GUEST_TLBS();
947	return VINF_SUCCESS;
948	}
949	Assert(pPDDst);
950
951	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
952	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
953
954	if (!pPdpeDst->n.u1Present)
955	{
956	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
957	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
958	PGM_INVL_GUEST_TLBS();
959	return VINF_SUCCESS;
960	}
961
962	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
963
964	const SHWPDE PdeDst = *pPdeDst;
965	if (!PdeDst.n.u1Present)
966	{
967	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
968	return VINF_SUCCESS;
969	}
970
971	/*
972	* Get the guest PD entry and calc big page.
973	*/
974	# if PGM_GST_TYPE == PGM_TYPE_32BIT
975	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
976	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
977	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
978	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
979	unsigned iPDSrc;
980	# if PGM_GST_TYPE == PGM_TYPE_PAE
981	X86PDPE PdpeSrc;
982	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
983	# else /* AMD64 */
984	PX86PML4E pPml4eSrc;
985	X86PDPE PdpeSrc;
986	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
987	# endif
988	GSTPDE PdeSrc;
989
990	if (pPDSrc)
991	PdeSrc = pPDSrc->a[iPDSrc];
992	else
993	PdeSrc.u = 0;
994	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
995
996	# if PGM_GST_TYPE == PGM_TYPE_AMD64
997	const bool fIsBigPage = PdeSrc.b.u1Size;
998	# else
999	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1000	# endif
1001
1002	# ifdef IN_RING3
1003	/*
1004	* If a CR3 Sync is pending we may ignore the invalidate page operation
1005	* depending on the kind of sync and if it's a global page or not.
1006	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1007	*/
1008	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1009	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
1010	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
1011	&& fIsBigPage
1012	&& PdeSrc.b.u1Global
1013	)
1014	)
1015	# else
1016	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1017	# endif
1018	{
1019	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1020	return VINF_SUCCESS;
1021	}
1022	# endif /* IN_RING3 */
1023
1024	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1025	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1026
1027	/* Fetch the pgm pool shadow descriptor. */
1028	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1029	Assert(pShwPdpt);
1030
1031	/* Fetch the pgm pool shadow descriptor. */
1032	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1033	Assert(pShwPde);
1034
1035	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1036	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1037
1038	if ( !pPml4eSrc->n.u1Present
1039	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1040	{
1041	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1042	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1043	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1044	pPml4eDst->u = 0;
1045	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1046	PGM_INVL_GUEST_TLBS();
1047	return VINF_SUCCESS;
1048	}
1049	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1050	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1051	{
1052	/*
1053	* Mark not present so we can resync the PML4E when it's used.
1054	*/
1055	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1056	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1057	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1058	pPml4eDst->u = 0;
1059	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1060	PGM_INVL_GUEST_TLBS();
1061	}
1062	else if (!pPml4eSrc->n.u1Accessed)
1063	{
1064	/*
1065	* Mark not present so we can set the accessed bit.
1066	*/
1067	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1068	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1069	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1070	pPml4eDst->u = 0;
1071	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1072	PGM_INVL_GUEST_TLBS();
1073	}
1074
1075	/* Check if the PDPT entry has changed. */
1076	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1077	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1078	if ( !PdpeSrc.n.u1Present
1079	\|\| pShwPde->GCPhys != GCPhysPd)
1080	{
1081	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1082	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1083	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1084	pPdpeDst->u = 0;
1085	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1086	PGM_INVL_GUEST_TLBS();
1087	return VINF_SUCCESS;
1088	}
1089	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1090	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1091	{
1092	/*
1093	* Mark not present so we can resync the PDPTE when it's used.
1094	*/
1095	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1096	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1097	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1098	pPdpeDst->u = 0;
1099	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1100	PGM_INVL_GUEST_TLBS();
1101	}
1102	else if (!PdpeSrc.lm.u1Accessed)
1103	{
1104	/*
1105	* Mark not present so we can set the accessed bit.
1106	*/
1107	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1108	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1109	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1110	pPdpeDst->u = 0;
1111	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1112	PGM_INVL_GUEST_TLBS();
1113	}
1114	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1115
1116	# if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1117	/*
1118	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1119	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1120	*/
1121	if (!pPDSrc)
1122	{
1123	/* Guest PDPE not present */
1124	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
1125	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1126
1127	Assert(!PdpeSrc.n.u1Present);
1128	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
1129
1130	/* for each page directory entry */
1131	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1132	{
1133	if ( pPDDst->a[iPD].n.u1Present
1134	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
1135	{
1136	pgmPoolFree(pVM, pPDDst->a[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
1137	pPDDst->a[iPD].u = 0;
1138	}
1139	}
1140	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
1141	pPdptDst->a[iPdpt].n.u1Present = 0;
1142	PGM_INVL_GUEST_TLBS();
1143	}
1144	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
1145	# endif
1146
1147
1148	/*
1149	* Deal with the Guest PDE.
1150	*/
1151	rc = VINF_SUCCESS;
1152	if (PdeSrc.n.u1Present)
1153	{
1154	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1155	{
1156	/*
1157	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1158	*/
1159	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1160	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1161	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1162	}
1163	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1164	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1165	{
1166	/*
1167	* Mark not present so we can resync the PDE when it's used.
1168	*/
1169	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1170	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1171	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1172	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1173	# else
1174	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1175	# endif
1176	pPdeDst->u = 0;
1177	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1178	PGM_INVL_GUEST_TLBS();
1179	}
1180	else if (!PdeSrc.n.u1Accessed)
1181	{
1182	/*
1183	* Mark not present so we can set the accessed bit.
1184	*/
1185	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1186	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1187	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1188	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1189	# else
1190	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1191	# endif
1192	pPdeDst->u = 0;
1193	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1194	PGM_INVL_GUEST_TLBS();
1195	}
1196	else if (!fIsBigPage)
1197	{
1198	/*
1199	* 4KB - page.
1200	*/
1201	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1202	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1203	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1204	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1205	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1206	# endif
1207	if (pShwPage->GCPhys == GCPhys)
1208	{
1209	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1210	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1211	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1212	if (pPT->a[iPTEDst].n.u1Present)
1213	{
1214	# ifdef PGMPOOL_WITH_USER_TRACKING
1215	/* This is very unlikely with caching/monitoring enabled. */
1216	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1217	# endif
1218	pPT->a[iPTEDst].u = 0;
1219	}
1220	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1221	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1222	if (RT_SUCCESS(rc))
1223	rc = VINF_SUCCESS;
1224	# endif
1225	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1226	PGM_INVL_PG(GCPtrPage);
1227	}
1228	else
1229	{
1230	/*
1231	* The page table address changed.
1232	*/
1233	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1234	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1235	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1236	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1237	# else
1238	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1239	# endif
1240	pPdeDst->u = 0;
1241	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1242	PGM_INVL_GUEST_TLBS();
1243	}
1244	}
1245	else
1246	{
1247	/*
1248	* 2/4MB - page.
1249	*/
1250	/* Before freeing the page, check if anything really changed. */
1251	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1252	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1253	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1254	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1255	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1256	# endif
1257	if ( pShwPage->GCPhys == GCPhys
1258	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1259	{
1260	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1261	/** @todo PAT */
1262	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1263	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1264	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1265	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1266	{
1267	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1268	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1269	return VINF_SUCCESS;
1270	}
1271	}
1272
1273	/*
1274	* Ok, the page table is present and it's been changed in the guest.
1275	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1276	* We could do this for some flushes in GC too, but we need an algorithm for
1277	* deciding which 4MB pages containing code likely to be executed very soon.
1278	*/
1279	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1280	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1281	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1282	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1283	# else
1284	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1285	# endif
1286	pPdeDst->u = 0;
1287	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1288	PGM_INVL_BIG_PG(GCPtrPage);
1289	}
1290	}
1291	else
1292	{
1293	/*
1294	* Page directory is not present, mark shadow PDE not present.
1295	*/
1296	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1297	{
1298	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1299	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1300	# else
1301	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1302	# endif
1303	pPdeDst->u = 0;
1304	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1305	PGM_INVL_PG(GCPtrPage);
1306	}
1307	else
1308	{
1309	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1310	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1311	}
1312	}
1313
1314	return rc;
1315
1316	#else /* guest real and protected mode */
1317	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1318	return VINF_SUCCESS;
1319	#endif
1320	}
1321
1322
1323	#ifdef PGMPOOL_WITH_USER_TRACKING
1324	/**
1325	* Update the tracking of shadowed pages.
1326	*
1327	* @param pVM The VM handle.
1328	* @param pShwPage The shadow page.
1329	* @param HCPhys The physical page we is being dereferenced.
1330	*/
1331	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1332	{
1333	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1334	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1335	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1336
1337	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1338	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1339	* 2. write protect all shadowed pages. I.e. implement caching.
1340	*/
1341	/*
1342	* Find the guest address.
1343	*/
1344	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1345	pRam;
1346	pRam = pRam->CTX_SUFF(pNext))
1347	{
1348	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1349	while (iPage-- > 0)
1350	{
1351	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1352	{
1353	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1354	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1355	pShwPage->cPresent--;
1356	pPool->cPresent--;
1357	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1358	return;
1359	}
1360	}
1361	}
1362
1363	for (;;)
1364	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1365	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1366	pShwPage->cPresent--;
1367	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1368	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1369	}
1370
1371
1372	/**
1373	* Update the tracking of shadowed pages.
1374	*
1375	* @param pVM The VM handle.
1376	* @param pShwPage The shadow page.
1377	* @param u16 The top 16-bit of the pPage->HCPhys.
1378	* @param pPage Pointer to the guest page. this will be modified.
1379	* @param iPTDst The index into the shadow table.
1380	*/
1381	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1382	{
1383	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1384	/*
1385	* We're making certain assumptions about the placement of cRef and idx.
1386	*/
1387	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1388	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1389
1390	/*
1391	* Just deal with the simple first time here.
1392	*/
1393	if (!u16)
1394	{
1395	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1396	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1397	}
1398	else
1399	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1400
1401	/* write back, trying to be clever... */
1402	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%RHp->%RHp iPTDst=%#x\n",
1403	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1404	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1405	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1406
1407	/* update statistics. */
1408	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1409	pShwPage->cPresent++;
1410	if (pShwPage->iFirstPresent > iPTDst)
1411	pShwPage->iFirstPresent = iPTDst;
1412	}
1413	#endif /* PGMPOOL_WITH_USER_TRACKING */
1414
1415
1416	/**
1417	* Creates a 4K shadow page for a guest page.
1418	*
1419	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1420	* physical address. The PdeSrc argument only the flags are used. No page structured
1421	* will be mapped in this function.
1422	*
1423	* @param pVM VM handle.
1424	* @param pPteDst Destination page table entry.
1425	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1426	* Can safely assume that only the flags are being used.
1427	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1428	* @param pShwPage Pointer to the shadow page.
1429	* @param iPTDst The index into the shadow table.
1430	*
1431	* @remark Not used for 2/4MB pages!
1432	*/
1433	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1434	{
1435	if (PteSrc.n.u1Present)
1436	{
1437	/*
1438	* Find the ram range.
1439	*/
1440	PPGMPAGE pPage;
1441	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1442	if (RT_SUCCESS(rc))
1443	{
1444	/** @todo investiage PWT, PCD and PAT. */
1445	/*
1446	* Make page table entry.
1447	*/
1448	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1449	SHWPTE PteDst;
1450	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1451	{
1452	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1453	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1454	{
1455	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1456	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1457	PteDst.n.u1Present = 1;
1458	PteDst.n.u1Execute = 1;
1459	PteDst.n.u1IgnorePAT = 1;
1460	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1461	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1462	#else
1463	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1464	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1465	#endif
1466	}
1467	else
1468	{
1469	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", HCPhys));
1470	PteDst.u = 0;
1471	}
1472	/** @todo count these two kinds. */
1473	}
1474	else
1475	{
1476	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1477	/*
1478	* If the page or page directory entry is not marked accessed,
1479	* we mark the page not present.
1480	*/
1481	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1482	{
1483	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1484	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1485	PteDst.u = 0;
1486	}
1487	else
1488	/*
1489	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1490	* when the page is modified.
1491	*/
1492	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1493	{
1494	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1495	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1496	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1497	\| PGM_PTFLAGS_TRACK_DIRTY;
1498	}
1499	else
1500	#endif
1501	{
1502	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1503	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1504	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1505	PteDst.n.u1Present = 1;
1506	PteDst.n.u1Write = 1;
1507	PteDst.n.u1Execute = 1;
1508	PteDst.n.u1IgnorePAT = 1;
1509	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1510	/* PteDst.n.u1Size = 0 */
1511	#else
1512	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1513	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1514	#endif
1515	}
1516	}
1517
1518	#ifdef PGMPOOL_WITH_USER_TRACKING
1519	/*
1520	* Keep user track up to date.
1521	*/
1522	if (PteDst.n.u1Present)
1523	{
1524	if (!pPteDst->n.u1Present)
1525	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1526	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1527	{
1528	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1529	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1530	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1531	}
1532	}
1533	else if (pPteDst->n.u1Present)
1534	{
1535	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1536	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1537	}
1538	#endif /* PGMPOOL_WITH_USER_TRACKING */
1539
1540	/*
1541	* Update statistics and commit the entry.
1542	*/
1543	if (!PteSrc.n.u1Global)
1544	pShwPage->fSeenNonGlobal = true;
1545	*pPteDst = PteDst;
1546	}
1547	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1548	/** @todo count these. */
1549	}
1550	else
1551	{
1552	/*
1553	* Page not-present.
1554	*/
1555	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1556	#ifdef PGMPOOL_WITH_USER_TRACKING
1557	/* Keep user track up to date. */
1558	if (pPteDst->n.u1Present)
1559	{
1560	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1561	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1562	}
1563	#endif /* PGMPOOL_WITH_USER_TRACKING */
1564	pPteDst->u = 0;
1565	/** @todo count these. */
1566	}
1567	}
1568
1569
1570	/**
1571	* Syncs a guest OS page.
1572	*
1573	* There are no conflicts at this point, neither is there any need for
1574	* page table allocations.
1575	*
1576	* @returns VBox status code.
1577	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1578	* @param pVM VM handle.
1579	* @param PdeSrc Page directory entry of the guest.
1580	* @param GCPtrPage Guest context page address.
1581	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1582	* @param uErr Fault error (X86_TRAP_PF_*).
1583	*/
1584	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1585	{
1586	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1587
1588	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1589	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1590	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1591	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1592	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1593
1594	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1595	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1596	# endif
1597
1598	/*
1599	* Assert preconditions.
1600	*/
1601	Assert(PdeSrc.n.u1Present);
1602	Assert(cPages);
1603	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1604
1605	/*
1606	* Get the shadow PDE, find the shadow page table in the pool.
1607	*/
1608	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1609	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1610	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
1611
1612	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1613	/* Fetch the pgm pool shadow descriptor. */
1614	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
1615	Assert(pShwPde);
1616	# endif
1617
1618	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1619
1620	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1621	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1622	PPGMPOOLPAGE pShwPde;
1623	PX86PDPAE pPDDst;
1624
1625	/* Fetch the pgm pool shadow descriptor. */
1626	int rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
1627	AssertRCSuccessReturn(rc, rc);
1628	Assert(pShwPde);
1629
1630	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1631	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1632	# else
1633	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
1634	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1635	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1636	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
1637	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
1638	# endif
1639	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1640	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1641	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1642	PX86PDPAE pPDDst;
1643	PX86PDPT pPdptDst;
1644
1645	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1646	AssertRCSuccessReturn(rc, rc);
1647	Assert(pPDDst && pPdptDst);
1648	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1649	# endif
1650
1651	SHWPDE PdeDst = *pPdeDst;
1652	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1653	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1654
1655	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1656	/* Fetch the pgm pool shadow descriptor. */
1657	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1658	Assert(pShwPde);
1659	# endif
1660
1661	/*
1662	* Check that the page is present and that the shadow PDE isn't out of sync.
1663	*/
1664	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1665	const bool fBigPage = PdeSrc.b.u1Size;
1666	# else
1667	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1668	# endif
1669	RTGCPHYS GCPhys;
1670	if (!fBigPage)
1671	{
1672	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1673	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1674	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1675	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1676	# endif
1677	}
1678	else
1679	{
1680	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1681	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1682	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1683	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1684	# endif
1685	}
1686	if ( pShwPage->GCPhys == GCPhys
1687	&& PdeSrc.n.u1Present
1688	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1689	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1690	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1691	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1692	# endif
1693	)
1694	{
1695	/*
1696	* Check that the PDE is marked accessed already.
1697	* Since we set the accessed bit before getting here on a #PF, this
1698	* check is only meant for dealing with non-#PF'ing paths.
1699	*/
1700	if (PdeSrc.n.u1Accessed)
1701	{
1702	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1703	if (!fBigPage)
1704	{
1705	/*
1706	* 4KB Page - Map the guest page table.
1707	*/
1708	PGSTPT pPTSrc;
1709	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1710	if (RT_SUCCESS(rc))
1711	{
1712	# ifdef PGM_SYNC_N_PAGES
1713	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1714	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1715	{
1716	/*
1717	* This code path is currently only taken when the caller is PGMTrap0eHandler
1718	* for non-present pages!
1719	*
1720	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1721	* deal with locality.
1722	*/
1723	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1724	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1725	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1726	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1727	# else
1728	const unsigned offPTSrc = 0;
1729	# endif
1730	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1731	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1732	iPTDst = 0;
1733	else
1734	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1735	for (; iPTDst < iPTDstEnd; iPTDst++)
1736	{
1737	if (!pPTDst->a[iPTDst].n.u1Present)
1738	{
1739	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1740	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1741	NOREF(GCPtrCurPage);
1742	#ifndef IN_RING0
1743	/*
1744	* Assuming kernel code will be marked as supervisor - and not as user level
1745	* and executed using a conforming code selector - And marked as readonly.
1746	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1747	*/
1748	PPGMPAGE pPage;
1749	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1750	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1751	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1752	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1753	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1754	)
1755	#endif /* else: CSAM not active */
1756	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1757	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1758	GCPtrCurPage, PteSrc.n.u1Present,
1759	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1760	PteSrc.n.u1User & PdeSrc.n.u1User,
1761	(uint64_t)PteSrc.u,
1762	(uint64_t)pPTDst->a[iPTDst].u,
1763	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1764	}
1765	}
1766	}
1767	else
1768	# endif /* PGM_SYNC_N_PAGES */
1769	{
1770	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1771	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1772	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1773	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1774	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1775	GCPtrPage, PteSrc.n.u1Present,
1776	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1777	PteSrc.n.u1User & PdeSrc.n.u1User,
1778	(uint64_t)PteSrc.u,
1779	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1780	}
1781	}
1782	else /* MMIO or invalid page: emulated in #PF handler. */
1783	{
1784	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1785	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1786	}
1787	}
1788	else
1789	{
1790	/*
1791	* 4/2MB page - lazy syncing shadow 4K pages.
1792	* (There are many causes of getting here, it's no longer only CSAM.)
1793	*/
1794	/* Calculate the GC physical address of this 4KB shadow page. */
1795	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1796	/* Find ram range. */
1797	PPGMPAGE pPage;
1798	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1799	if (RT_SUCCESS(rc))
1800	{
1801	/*
1802	* Make shadow PTE entry.
1803	*/
1804	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1805	SHWPTE PteDst;
1806	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1807	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1808	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1809	{
1810	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1811	PteDst.n.u1Write = 0;
1812	else
1813	PteDst.u = 0;
1814	}
1815	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1816	# ifdef PGMPOOL_WITH_USER_TRACKING
1817	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1818	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1819	# endif
1820	pPTDst->a[iPTDst] = PteDst;
1821
1822
1823	/*
1824	* If the page is not flagged as dirty and is writable, then make it read-only
1825	* at PD level, so we can set the dirty bit when the page is modified.
1826	*
1827	* ASSUMES that page access handlers are implemented on page table entry level.
1828	* Thus we will first catch the dirty access and set PDE.D and restart. If
1829	* there is an access handler, we'll trap again and let it work on the problem.
1830	*/
1831	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1832	* As for invlpg, it simply frees the whole shadow PT.
1833	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1834	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1835	{
1836	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1837	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1838	PdeDst.n.u1Write = 0;
1839	}
1840	else
1841	{
1842	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1843	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1844	}
1845	*pPdeDst = PdeDst;
1846	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1847	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1848	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1849	}
1850	else
1851	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1852	}
1853	return VINF_SUCCESS;
1854	}
1855	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1856	}
1857	else
1858	{
1859	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1860	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1861	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1862	}
1863
1864	/*
1865	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1866	* Yea, I'm lazy.
1867	*/
1868	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1869	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1870	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1871	# else
1872	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1873	# endif
1874
1875	pPdeDst->u = 0;
1876	PGM_INVL_GUEST_TLBS();
1877	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1878
1879	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1880	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1881	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1882
1883	# ifdef PGM_SYNC_N_PAGES
1884	/*
1885	* Get the shadow PDE, find the shadow page table in the pool.
1886	*/
1887	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1888	X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
1889
1890	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1891	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1892
1893	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1894	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1895	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1896	PX86PDPAE pPDDst;
1897	X86PDEPAE PdeDst;
1898	PX86PDPT pPdptDst;
1899
1900	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1901	AssertRCSuccessReturn(rc, rc);
1902	Assert(pPDDst && pPdptDst);
1903	PdeDst = pPDDst->a[iPDDst];
1904	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1905	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1906	PEPTPD pPDDst;
1907	EPTPDE PdeDst;
1908
1909	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1910	if (rc != VINF_SUCCESS)
1911	{
1912	AssertRC(rc);
1913	return rc;
1914	}
1915	Assert(pPDDst);
1916	PdeDst = pPDDst->a[iPDDst];
1917	# endif
1918	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1919	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1920	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1921
1922	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1923	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1924	{
1925	/*
1926	* This code path is currently only taken when the caller is PGMTrap0eHandler
1927	* for non-present pages!
1928	*
1929	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1930	* deal with locality.
1931	*/
1932	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1933	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1934	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1935	iPTDst = 0;
1936	else
1937	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1938	for (; iPTDst < iPTDstEnd; iPTDst++)
1939	{
1940	if (!pPTDst->a[iPTDst].n.u1Present)
1941	{
1942	GSTPTE PteSrc;
1943
1944	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1945
1946	/* Fake the page table entry */
1947	PteSrc.u = GCPtrCurPage;
1948	PteSrc.n.u1Present = 1;
1949	PteSrc.n.u1Dirty = 1;
1950	PteSrc.n.u1Accessed = 1;
1951	PteSrc.n.u1Write = 1;
1952	PteSrc.n.u1User = 1;
1953
1954	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1955
1956	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1957	GCPtrCurPage, PteSrc.n.u1Present,
1958	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1959	PteSrc.n.u1User & PdeSrc.n.u1User,
1960	(uint64_t)PteSrc.u,
1961	(uint64_t)pPTDst->a[iPTDst].u,
1962	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1963	}
1964	else
1965	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1966	}
1967	}
1968	else
1969	# endif /* PGM_SYNC_N_PAGES */
1970	{
1971	GSTPTE PteSrc;
1972	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1973	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1974
1975	/* Fake the page table entry */
1976	PteSrc.u = GCPtrCurPage;
1977	PteSrc.n.u1Present = 1;
1978	PteSrc.n.u1Dirty = 1;
1979	PteSrc.n.u1Accessed = 1;
1980	PteSrc.n.u1Write = 1;
1981	PteSrc.n.u1User = 1;
1982	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1983
1984	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
1985	GCPtrPage, PteSrc.n.u1Present,
1986	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1987	PteSrc.n.u1User & PdeSrc.n.u1User,
1988	(uint64_t)PteSrc.u,
1989	(uint64_t)pPTDst->a[iPTDst].u,
1990	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1991	}
1992	return VINF_SUCCESS;
1993
1994	#else
1995	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1996	return VERR_INTERNAL_ERROR;
1997	#endif
1998	}
1999
2000
2001	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2002	/**
2003	* Investigate page fault and handle write protection page faults caused by
2004	* dirty bit tracking.
2005	*
2006	* @returns VBox status code.
2007	* @param pVM VM handle.
2008	* @param uErr Page fault error code.
2009	* @param pPdeDst Shadow page directory entry.
2010	* @param pPdeSrc Guest page directory entry.
2011	* @param GCPtrPage Guest context page address.
2012	*/
2013	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2014	{
2015	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
2016	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2017	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2018	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2019	bool fBigPagesSupported = true;
2020	# else
2021	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2022	# endif
2023	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2024	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
2025	# endif
2026	unsigned uPageFaultLevel;
2027	int rc;
2028
2029	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2030	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2031
2032	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2033	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2034
2035	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2036	PX86PML4E pPml4eSrc;
2037	PX86PDPE pPdpeSrc;
2038
2039	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2040	Assert(pPml4eSrc);
2041
2042	/*
2043	* Real page fault? (PML4E level)
2044	*/
2045	if ( (uErr & X86_TRAP_PF_RSVD)
2046	\|\| !pPml4eSrc->n.u1Present
2047	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2048	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2049	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2050	)
2051	{
2052	uPageFaultLevel = 0;
2053	goto l_UpperLevelPageFault;
2054	}
2055	Assert(pPdpeSrc);
2056
2057	# else /* PAE */
2058	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2059	# endif /* PAE */
2060
2061	/*
2062	* Real page fault? (PDPE level)
2063	*/
2064	if ( (uErr & X86_TRAP_PF_RSVD)
2065	\|\| !pPdpeSrc->n.u1Present
2066	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2067	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2068	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2069	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2070	# endif
2071	)
2072	{
2073	uPageFaultLevel = 1;
2074	goto l_UpperLevelPageFault;
2075	}
2076	# endif
2077
2078	/*
2079	* Real page fault? (PDE level)
2080	*/
2081	if ( (uErr & X86_TRAP_PF_RSVD)
2082	\|\| !pPdeSrc->n.u1Present
2083	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2084	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2085	# endif
2086	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2087	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2088	{
2089	uPageFaultLevel = 2;
2090	goto l_UpperLevelPageFault;
2091	}
2092
2093	/*
2094	* First check the easy case where the page directory has been marked read-only to track
2095	* the dirty bit of an emulated BIG page
2096	*/
2097	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2098	{
2099	/* Mark guest page directory as accessed */
2100	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2101	pPml4eSrc->n.u1Accessed = 1;
2102	pPdpeSrc->lm.u1Accessed = 1;
2103	# endif
2104	pPdeSrc->b.u1Accessed = 1;
2105
2106	/*
2107	* Only write protection page faults are relevant here.
2108	*/
2109	if (fWriteFault)
2110	{
2111	/* Mark guest page directory as dirty (BIG page only). */
2112	pPdeSrc->b.u1Dirty = 1;
2113
2114	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2115	{
2116	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2117
2118	Assert(pPdeSrc->b.u1Write);
2119
2120	pPdeDst->n.u1Write = 1;
2121	pPdeDst->n.u1Accessed = 1;
2122	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2123	PGM_INVL_BIG_PG(GCPtrPage);
2124	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2125	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2126	}
2127	}
2128	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2129	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2130	}
2131	/* else: 4KB page table */
2132
2133	/*
2134	* Map the guest page table.
2135	*/
2136	PGSTPT pPTSrc;
2137	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2138	if (RT_SUCCESS(rc))
2139	{
2140	/*
2141	* Real page fault?
2142	*/
2143	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2144	const GSTPTE PteSrc = *pPteSrc;
2145	if ( !PteSrc.n.u1Present
2146	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2147	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2148	# endif
2149	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2150	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2151	)
2152	{
2153	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2154	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2155	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2156
2157	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2158	* See the 2nd case above as well.
2159	*/
2160	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2161	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2162
2163	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2164	return VINF_EM_RAW_GUEST_TRAP;
2165	}
2166	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2167
2168	/*
2169	* Set the accessed bits in the page directory and the page table.
2170	*/
2171	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2172	pPml4eSrc->n.u1Accessed = 1;
2173	pPdpeSrc->lm.u1Accessed = 1;
2174	# endif
2175	pPdeSrc->n.u1Accessed = 1;
2176	pPteSrc->n.u1Accessed = 1;
2177
2178	/*
2179	* Only write protection page faults are relevant here.
2180	*/
2181	if (fWriteFault)
2182	{
2183	/* Write access, so mark guest entry as dirty. */
2184	# ifdef VBOX_WITH_STATISTICS
2185	if (!pPteSrc->n.u1Dirty)
2186	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2187	else
2188	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2189	# endif
2190
2191	pPteSrc->n.u1Dirty = 1;
2192
2193	if (pPdeDst->n.u1Present)
2194	{
2195	#ifndef IN_RING0
2196	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2197	* Our individual shadow handlers will provide more information and force a fatal exit.
2198	*/
2199	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2200	{
2201	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2202	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2203	return VINF_SUCCESS;
2204	}
2205	#endif
2206	/*
2207	* Map shadow page table.
2208	*/
2209	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2210	if (pShwPage)
2211	{
2212	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2213	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2214	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2215	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2216	{
2217	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2218	# ifdef VBOX_STRICT
2219	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2220	if (pPage)
2221	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2222	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2223	# endif
2224	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2225
2226	Assert(pPteSrc->n.u1Write);
2227
2228	pPteDst->n.u1Write = 1;
2229	pPteDst->n.u1Dirty = 1;
2230	pPteDst->n.u1Accessed = 1;
2231	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2232	PGM_INVL_PG(GCPtrPage);
2233
2234	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2235	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2236	}
2237	}
2238	else
2239	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2240	}
2241	}
2242	/** @todo Optimize accessed bit emulation? */
2243	# ifdef VBOX_STRICT
2244	/*
2245	* Sanity check.
2246	*/
2247	else if ( !pPteSrc->n.u1Dirty
2248	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2249	&& pPdeDst->n.u1Present)
2250	{
2251	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2252	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2253	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2254	if ( pPteDst->n.u1Present
2255	&& pPteDst->n.u1Write)
2256	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2257	}
2258	# endif /* VBOX_STRICT */
2259	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2260	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2261	}
2262	AssertRC(rc);
2263	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2264	return rc;
2265
2266
2267	l_UpperLevelPageFault:
2268	/*
2269	* Pagefault detected while checking the PML4E, PDPE or PDE.
2270	* Single exit handler to get rid of duplicate code paths.
2271	*/
2272	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2273	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2274	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2275
2276	if (
2277	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2278	pPml4eSrc->n.u1Present &&
2279	# endif
2280	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2281	pPdpeSrc->n.u1Present &&
2282	# endif
2283	pPdeSrc->n.u1Present)
2284	{
2285	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2286	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2287	{
2288	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2289	}
2290	else
2291	{
2292	/*
2293	* Map the guest page table.
2294	*/
2295	PGSTPT pPTSrc;
2296	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2297	if (RT_SUCCESS(rc))
2298	{
2299	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2300	const GSTPTE PteSrc = *pPteSrc;
2301	if (pPteSrc->n.u1Present)
2302	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2303	}
2304	AssertRC(rc);
2305	}
2306	}
2307	return VINF_EM_RAW_GUEST_TRAP;
2308	}
2309	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2310
2311
2312	/**
2313	* Sync a shadow page table.
2314	*
2315	* The shadow page table is not present. This includes the case where
2316	* there is a conflict with a mapping.
2317	*
2318	* @returns VBox status code.
2319	* @param pVM VM handle.
2320	* @param iPD Page directory index.
2321	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2322	* Assume this is a temporary mapping.
2323	* @param GCPtrPage GC Pointer of the page that caused the fault
2324	*/
2325	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2326	{
2327	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2328	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2329	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2330
2331	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2332	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2333	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2334	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2335	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2336
2337	int rc = VINF_SUCCESS;
2338
2339	/*
2340	* Validate input a little bit.
2341	*/
2342	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2343	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2344	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2345	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2346
2347	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2348	/* Fetch the pgm pool shadow descriptor. */
2349	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2350	Assert(pShwPde);
2351	# endif
2352
2353	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2354	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2355	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2356	PPGMPOOLPAGE pShwPde;
2357	PX86PDPAE pPDDst;
2358	PSHWPDE pPdeDst;
2359
2360	/* Fetch the pgm pool shadow descriptor. */
2361	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2362	AssertRCSuccessReturn(rc, rc);
2363	Assert(pShwPde);
2364
2365	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2366	pPdeDst = &pPDDst->a[iPDDst];
2367	# else
2368	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
2369	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
2370	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2371	PSHWPDE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2372	# endif
2373	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2374	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2375	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2376	PX86PDPAE pPDDst;
2377	PX86PDPT pPdptDst;
2378	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2379	AssertRCSuccessReturn(rc, rc);
2380	Assert(pPDDst);
2381	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2382	# endif
2383	SHWPDE PdeDst = *pPdeDst;
2384
2385	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2386	/* Fetch the pgm pool shadow descriptor. */
2387	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2388	Assert(pShwPde);
2389	# endif
2390
2391	# ifndef PGM_WITHOUT_MAPPINGS
2392	/*
2393	* Check for conflicts.
2394	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2395	* HC: Simply resolve the conflict.
2396	*/
2397	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2398	{
2399	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2400	# ifndef IN_RING3
2401	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2402	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2403	return VERR_ADDRESS_CONFLICT;
2404	# else
2405	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2406	Assert(pMapping);
2407	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2408	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2409	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2410	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2411	# else
2412	AssertFailed(); /* can't happen for amd64 */
2413	# endif
2414	if (RT_FAILURE(rc))
2415	{
2416	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2417	return rc;
2418	}
2419	PdeDst = *pPdeDst;
2420	# endif
2421	}
2422	# else /* PGM_WITHOUT_MAPPINGS */
2423	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2424	# endif /* PGM_WITHOUT_MAPPINGS */
2425	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2426
2427	/*
2428	* Sync page directory entry.
2429	*/
2430	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2431	if (PdeSrc.n.u1Present)
2432	{
2433	/*
2434	* Allocate & map the page table.
2435	*/
2436	PSHWPT pPTDst;
2437	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2438	const bool fPageTable = !PdeSrc.b.u1Size;
2439	# else
2440	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2441	# endif
2442	PPGMPOOLPAGE pShwPage;
2443	RTGCPHYS GCPhys;
2444	if (fPageTable)
2445	{
2446	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2447	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2448	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2449	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2450	# endif
2451	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2452	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2453	# else
2454	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2455	# endif
2456	}
2457	else
2458	{
2459	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2460	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2461	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2462	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2463	# endif
2464	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2465	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2466	# else
2467	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2468	# endif
2469	}
2470	if (rc == VINF_SUCCESS)
2471	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2472	else if (rc == VINF_PGM_CACHED_PAGE)
2473	{
2474	/*
2475	* The PT was cached, just hook it up.
2476	*/
2477	if (fPageTable)
2478	PdeDst.u = pShwPage->Core.Key
2479	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2480	else
2481	{
2482	PdeDst.u = pShwPage->Core.Key
2483	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2484	/* (see explanation and assumptions further down.) */
2485	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2486	{
2487	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2488	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2489	PdeDst.b.u1Write = 0;
2490	}
2491	}
2492	*pPdeDst = PdeDst;
2493	return VINF_SUCCESS;
2494	}
2495	else if (rc == VERR_PGM_POOL_FLUSHED)
2496	{
2497	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2498	return VINF_PGM_SYNC_CR3;
2499	}
2500	else
2501	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2502	PdeDst.u &= X86_PDE_AVL_MASK;
2503	PdeDst.u \|= pShwPage->Core.Key;
2504
2505	/*
2506	* Page directory has been accessed (this is a fault situation, remember).
2507	*/
2508	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2509	if (fPageTable)
2510	{
2511	/*
2512	* Page table - 4KB.
2513	*
2514	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2515	*/
2516	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2517	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2518	PGSTPT pPTSrc;
2519	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2520	if (RT_SUCCESS(rc))
2521	{
2522	/*
2523	* Start by syncing the page directory entry so CSAM's TLB trick works.
2524	*/
2525	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2526	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2527	*pPdeDst = PdeDst;
2528
2529	/*
2530	* Directory/page user or supervisor privilege: (same goes for read/write)
2531	*
2532	* Directory Page Combined
2533	* U/S U/S U/S
2534	* 0 0 0
2535	* 0 1 0
2536	* 1 0 0
2537	* 1 1 1
2538	*
2539	* Simple AND operation. Table listed for completeness.
2540	*
2541	*/
2542	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2543	# ifdef PGM_SYNC_N_PAGES
2544	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2545	unsigned iPTDst = iPTBase;
2546	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2547	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2548	iPTDst = 0;
2549	else
2550	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2551	# else /* !PGM_SYNC_N_PAGES */
2552	unsigned iPTDst = 0;
2553	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2554	# endif /* !PGM_SYNC_N_PAGES */
2555	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2556	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2557	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2558	# else
2559	const unsigned offPTSrc = 0;
2560	# endif
2561	for (; iPTDst < iPTDstEnd; iPTDst++)
2562	{
2563	const unsigned iPTSrc = iPTDst + offPTSrc;
2564	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2565
2566	if (PteSrc.n.u1Present) /* we've already cleared it above */
2567	{
2568	# ifndef IN_RING0
2569	/*
2570	* Assuming kernel code will be marked as supervisor - and not as user level
2571	* and executed using a conforming code selector - And marked as readonly.
2572	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2573	*/
2574	PPGMPAGE pPage;
2575	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2576	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2577	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2578	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2579	)
2580	# endif
2581	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2582	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2583	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2584	PteSrc.n.u1Present,
2585	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2586	PteSrc.n.u1User & PdeSrc.n.u1User,
2587	(uint64_t)PteSrc.u,
2588	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2589	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2590	}
2591	} /* for PTEs */
2592	}
2593	}
2594	else
2595	{
2596	/*
2597	* Big page - 2/4MB.
2598	*
2599	* We'll walk the ram range list in parallel and optimize lookups.
2600	* We will only sync on shadow page table at a time.
2601	*/
2602	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2603
2604	/**
2605	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2606	*/
2607
2608	/*
2609	* Start by syncing the page directory entry.
2610	*/
2611	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2612	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2613
2614	/*
2615	* If the page is not flagged as dirty and is writable, then make it read-only
2616	* at PD level, so we can set the dirty bit when the page is modified.
2617	*
2618	* ASSUMES that page access handlers are implemented on page table entry level.
2619	* Thus we will first catch the dirty access and set PDE.D and restart. If
2620	* there is an access handler, we'll trap again and let it work on the problem.
2621	*/
2622	/** @todo move the above stuff to a section in the PGM documentation. */
2623	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2624	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2625	{
2626	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2627	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2628	PdeDst.b.u1Write = 0;
2629	}
2630	*pPdeDst = PdeDst;
2631
2632	/*
2633	* Fill the shadow page table.
2634	*/
2635	/* Get address and flags from the source PDE. */
2636	SHWPTE PteDstBase;
2637	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2638
2639	/* Loop thru the entries in the shadow PT. */
2640	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2641	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2642	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2643	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2644	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2645	unsigned iPTDst = 0;
2646	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2647	{
2648	/* Advance ram range list. */
2649	while (pRam && GCPhys > pRam->GCPhysLast)
2650	pRam = pRam->CTX_SUFF(pNext);
2651	if (pRam && GCPhys >= pRam->GCPhys)
2652	{
2653	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2654	do
2655	{
2656	/* Make shadow PTE. */
2657	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2658	SHWPTE PteDst;
2659
2660	/* Make sure the RAM has already been allocated. */
2661	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2662	{
2663	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2664	{
2665	# ifdef IN_RING3
2666	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2667	# else
2668	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2669	# endif
2670	if (rc != VINF_SUCCESS)
2671	return rc;
2672	}
2673	}
2674
2675	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2676	{
2677	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2678	{
2679	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2680	PteDst.n.u1Write = 0;
2681	}
2682	else
2683	PteDst.u = 0;
2684	}
2685	# ifndef IN_RING0
2686	/*
2687	* Assuming kernel code will be marked as supervisor and not as user level and executed
2688	* using a conforming code selector. Don't check for readonly, as that implies the whole
2689	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2690	*/
2691	else if ( !PdeSrc.n.u1User
2692	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2693	PteDst.u = 0;
2694	# endif
2695	else
2696	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2697	# ifdef PGMPOOL_WITH_USER_TRACKING
2698	if (PteDst.n.u1Present)
2699	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2700	# endif
2701	/* commit it */
2702	pPTDst->a[iPTDst] = PteDst;
2703	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2704	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2705	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2706
2707	/* advance */
2708	GCPhys += PAGE_SIZE;
2709	iHCPage++;
2710	iPTDst++;
2711	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2712	&& GCPhys <= pRam->GCPhysLast);
2713	}
2714	else if (pRam)
2715	{
2716	Log(("Invalid pages at %RGp\n", GCPhys));
2717	do
2718	{
2719	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2720	GCPhys += PAGE_SIZE;
2721	iPTDst++;
2722	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2723	&& GCPhys < pRam->GCPhys);
2724	}
2725	else
2726	{
2727	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2728	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2729	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2730	}
2731	} /* while more PTEs */
2732	} /* 4KB / 4MB */
2733	}
2734	else
2735	AssertRelease(!PdeDst.n.u1Present);
2736
2737	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2738	if (RT_FAILURE(rc))
2739	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2740	return rc;
2741
2742	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2743	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2744	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2745
2746
2747	/*
2748	* Validate input a little bit.
2749	*/
2750	int rc = VINF_SUCCESS;
2751	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2752	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2753	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2754
2755	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2756	/* Fetch the pgm pool shadow descriptor. */
2757	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2758	Assert(pShwPde);
2759	# endif
2760
2761	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2762	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2763	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2764	PPGMPOOLPAGE pShwPde;
2765	PX86PDPAE pPDDst;
2766	PSHWPDE pPdeDst;
2767
2768	/* Fetch the pgm pool shadow descriptor. */
2769	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2770	AssertRCSuccessReturn(rc, rc);
2771	Assert(pShwPde);
2772
2773	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2774	pPdeDst = &pPDDst->a[iPDDst];
2775	# else
2776	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm!/;
2777	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2778	# endif
2779
2780	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2781	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2782	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2783	PX86PDPAE pPDDst;
2784	PX86PDPT pPdptDst;
2785	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2786	AssertRCSuccessReturn(rc, rc);
2787	Assert(pPDDst);
2788	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2789
2790	/* Fetch the pgm pool shadow descriptor. */
2791	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2792	Assert(pShwPde);
2793
2794	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2795	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2796	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2797	PEPTPD pPDDst;
2798	PEPTPDPT pPdptDst;
2799
2800	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2801	if (rc != VINF_SUCCESS)
2802	{
2803	AssertRC(rc);
2804	return rc;
2805	}
2806	Assert(pPDDst);
2807	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2808
2809	/* Fetch the pgm pool shadow descriptor. */
2810	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2811	Assert(pShwPde);
2812	# endif
2813	SHWPDE PdeDst = *pPdeDst;
2814
2815	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2816	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2817
2818	GSTPDE PdeSrc;
2819	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2820	PdeSrc.n.u1Present = 1;
2821	PdeSrc.n.u1Write = 1;
2822	PdeSrc.n.u1Accessed = 1;
2823	PdeSrc.n.u1User = 1;
2824
2825	/*
2826	* Allocate & map the page table.
2827	*/
2828	PSHWPT pPTDst;
2829	PPGMPOOLPAGE pShwPage;
2830	RTGCPHYS GCPhys;
2831
2832	/* Virtual address = physical address */
2833	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2834	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2835	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2836	# else
2837	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2838	# endif
2839
2840	if ( rc == VINF_SUCCESS
2841	\|\| rc == VINF_PGM_CACHED_PAGE)
2842	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2843	else
2844	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2845
2846	PdeDst.u &= X86_PDE_AVL_MASK;
2847	PdeDst.u \|= pShwPage->Core.Key;
2848	PdeDst.n.u1Present = 1;
2849	PdeDst.n.u1Write = 1;
2850	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2851	PdeDst.n.u1Execute = 1;
2852	# else
2853	PdeDst.n.u1User = 1;
2854	PdeDst.n.u1Accessed = 1;
2855	# endif
2856	*pPdeDst = PdeDst;
2857
2858	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2859	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2860	return rc;
2861
2862	#else
2863	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2864	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2865	return VERR_INTERNAL_ERROR;
2866	#endif
2867	}
2868
2869
2870
2871	/**
2872	* Prefetch a page/set of pages.
2873	*
2874	* Typically used to sync commonly used pages before entering raw mode
2875	* after a CR3 reload.
2876	*
2877	* @returns VBox status code.
2878	* @param pVM VM handle.
2879	* @param GCPtrPage Page to invalidate.
2880	*/
2881	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2882	{
2883	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2884	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2885	/*
2886	* Check that all Guest levels thru the PDE are present, getting the
2887	* PD and PDE in the processes.
2888	*/
2889	int rc = VINF_SUCCESS;
2890	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2891	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2892	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2893	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2894	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2895	unsigned iPDSrc;
2896	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2897	if (!pPDSrc)
2898	return VINF_SUCCESS; /* not present */
2899	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2900	unsigned iPDSrc;
2901	PX86PML4E pPml4eSrc;
2902	X86PDPE PdpeSrc;
2903	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2904	if (!pPDSrc)
2905	return VINF_SUCCESS; /* not present */
2906	# endif
2907	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2908	# else
2909	PGSTPD pPDSrc = NULL;
2910	const unsigned iPDSrc = 0;
2911	GSTPDE PdeSrc;
2912
2913	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2914	PdeSrc.n.u1Present = 1;
2915	PdeSrc.n.u1Write = 1;
2916	PdeSrc.n.u1Accessed = 1;
2917	PdeSrc.n.u1User = 1;
2918	# endif
2919
2920	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2921	{
2922	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2923	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
2924	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2925	const X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
2926	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2927	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2928	PX86PDPAE pPDDst;
2929	X86PDEPAE PdeDst;
2930
2931	# if PGM_GST_TYPE == PGM_TYPE_PROT
2932	/* AMD-V nested paging */
2933	X86PML4E Pml4eSrc;
2934	X86PDPE PdpeSrc;
2935	PX86PML4E pPml4eSrc = &Pml4eSrc;
2936
2937	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2938	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2939	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2940	# endif
2941
2942	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2943	if (rc != VINF_SUCCESS)
2944	{
2945	AssertRC(rc);
2946	return rc;
2947	}
2948	Assert(pPDDst);
2949	PdeDst = pPDDst->a[iPDDst];
2950	# endif
2951	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2952	{
2953	if (!PdeDst.n.u1Present)
2954	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2955	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2956	else
2957	{
2958	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2959	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2960	* makes no sense to prefetch more than one page.
2961	*/
2962	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2963	if (RT_SUCCESS(rc))
2964	rc = VINF_SUCCESS;
2965	}
2966	}
2967	}
2968	return rc;
2969
2970	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
2971	return VINF_SUCCESS; /* ignore */
2972	#endif
2973	}
2974
2975
2976
2977
2978	/**
2979	* Syncs a page during a PGMVerifyAccess() call.
2980	*
2981	* @returns VBox status code (informational included).
2982	* @param GCPtrPage The address of the page to sync.
2983	* @param fPage The effective guest page flags.
2984	* @param uErr The trap error code.
2985	*/
2986	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
2987	{
2988	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2989
2990	Assert(!HWACCMIsNestedPagingActive(pVM));
2991	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
2992	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2993
2994	# ifndef IN_RING0
2995	if (!(fPage & X86_PTE_US))
2996	{
2997	/*
2998	* Mark this page as safe.
2999	*/
3000	/** @todo not correct for pages that contain both code and data!! */
3001	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3002	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3003	}
3004	# endif
3005
3006	/*
3007	* Get guest PD and index.
3008	*/
3009	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3010	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3011	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3012	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3013	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3014	unsigned iPDSrc;
3015	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
3016
3017	if (pPDSrc)
3018	{
3019	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3020	return VINF_EM_RAW_GUEST_TRAP;
3021	}
3022	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3023	unsigned iPDSrc;
3024	PX86PML4E pPml4eSrc;
3025	X86PDPE PdpeSrc;
3026	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3027	if (!pPDSrc)
3028	{
3029	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3030	return VINF_EM_RAW_GUEST_TRAP;
3031	}
3032	# endif
3033	# else
3034	PGSTPD pPDSrc = NULL;
3035	const unsigned iPDSrc = 0;
3036	# endif
3037	int rc = VINF_SUCCESS;
3038
3039	/*
3040	* First check if the shadow pd is present.
3041	*/
3042	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3043	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
3044	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3045	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
3046	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3047	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3048	PX86PDPAE pPDDst;
3049	PX86PDEPAE pPdeDst;
3050
3051	# if PGM_GST_TYPE == PGM_TYPE_PROT
3052	/* AMD-V nested paging */
3053	X86PML4E Pml4eSrc;
3054	X86PDPE PdpeSrc;
3055	PX86PML4E pPml4eSrc = &Pml4eSrc;
3056
3057	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3058	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3059	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3060	# endif
3061
3062	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3063	if (rc != VINF_SUCCESS)
3064	{
3065	AssertRC(rc);
3066	return rc;
3067	}
3068	Assert(pPDDst);
3069	pPdeDst = &pPDDst->a[iPDDst];
3070	# endif
3071	if (!pPdeDst->n.u1Present)
3072	{
3073	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3074	AssertRC(rc);
3075	if (rc != VINF_SUCCESS)
3076	return rc;
3077	}
3078
3079	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3080	/* Check for dirty bit fault */
3081	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3082	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3083	Log(("PGMVerifyAccess: success (dirty)\n"));
3084	else
3085	{
3086	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3087	#else
3088	{
3089	GSTPDE PdeSrc;
3090	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3091	PdeSrc.n.u1Present = 1;
3092	PdeSrc.n.u1Write = 1;
3093	PdeSrc.n.u1Accessed = 1;
3094	PdeSrc.n.u1User = 1;
3095
3096	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3097	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3098	if (uErr & X86_TRAP_PF_US)
3099	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3100	else /* supervisor */
3101	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3102
3103	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3104	if (RT_SUCCESS(rc))
3105	{
3106	/* Page was successfully synced */
3107	Log2(("PGMVerifyAccess: success (sync)\n"));
3108	rc = VINF_SUCCESS;
3109	}
3110	else
3111	{
3112	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3113	return VINF_EM_RAW_GUEST_TRAP;
3114	}
3115	}
3116	return rc;
3117
3118	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3119
3120	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3121	return VERR_INTERNAL_ERROR;
3122	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3123	}
3124
3125
3126	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3127	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3128	/**
3129	* Figures out which kind of shadow page this guest PDE warrants.
3130	*
3131	* @returns Shadow page kind.
3132	* @param pPdeSrc The guest PDE in question.
3133	* @param cr4 The current guest cr4 value.
3134	*/
3135	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3136	{
3137	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3138	if (!pPdeSrc->n.u1Size)
3139	# else
3140	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3141	# endif
3142	return BTH_PGMPOOLKIND_PT_FOR_PT;
3143	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3144	//{
3145	// case 0:
3146	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3147	// case X86_PDE4M_RW:
3148	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3149	// case X86_PDE4M_US:
3150	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3151	// case X86_PDE4M_RW \| X86_PDE4M_US:
3152	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3153	# if 0
3154	// case X86_PDE4M_PAE_NX:
3155	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3156	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3157	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3158	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3159	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3160	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3161	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3162	# endif
3163	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3164	//}
3165	}
3166	# endif
3167	#endif
3168
3169	#undef MY_STAM_COUNTER_INC
3170	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3171
3172
3173	/**
3174	* Syncs the paging hierarchy starting at CR3.
3175	*
3176	* @returns VBox status code, no specials.
3177	* @param pVM The virtual machine.
3178	* @param cr0 Guest context CR0 register
3179	* @param cr3 Guest context CR3 register
3180	* @param cr4 Guest context CR4 register
3181	* @param fGlobal Including global page directories or not
3182	*/
3183	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3184	{
3185	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3186	fGlobal = true; /* Change this CR3 reload to be a global one. */
3187
3188	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3189	/*
3190	* Update page access handlers.
3191	* The virtual are always flushed, while the physical are only on demand.
3192	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3193	* have to look into that later because it will have a bad influence on the performance.
3194	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3195	* bird: Yes, but that won't work for aliases.
3196	*/
3197	/** @todo this MUST go away. See #1557. */
3198	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3199	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3200	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3201	#endif
3202
3203	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3204	/*
3205	* Nested / EPT - almost no work.
3206	*/
3207	/** @todo check if this is really necessary; the call does it as well... */
3208	HWACCMFlushTLB(pVM);
3209	return VINF_SUCCESS;
3210
3211	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
3212	/*
3213	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3214	* out the shadow parts when the guest modifies its tables.
3215	*/
3216	return VINF_SUCCESS;
3217
3218	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3219	/*
3220	* PAE and 32-bit legacy mode (shadow).
3221	* (Guest PAE, 32-bit legacy, protected and real modes.)
3222	*/
3223	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3224	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3225
3226	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3227	bool const fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3228
3229	/*
3230	* Get page directory addresses.
3231	*/
3232	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3233	PX86PDE pPDEDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, 0);
3234	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
3235	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3236	PX86PDEPAE pPDEDst = NULL;
3237	# endif
3238	# endif
3239
3240	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3241	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3242	Assert(pPDSrc);
3243	# if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3244	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == (RTR3PTR)pPDSrc);
3245	# endif
3246	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3247
3248	/*
3249	* Iterate the the CR3 page.
3250	*/
3251	PPGMMAPPING pMapping;
3252	unsigned iPdNoMapping;
3253	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3254	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3255
3256	/* Only check mappings if they are supposed to be put into the shadow page table. */
3257	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3258	{
3259	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3260	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3261	}
3262	else
3263	{
3264	pMapping = 0;
3265	iPdNoMapping = ~0U;
3266	}
3267
3268	# if PGM_GST_TYPE == PGM_TYPE_PAE
3269	for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
3270	{
3271	unsigned iPDSrc;
3272	X86PDPE PdpeSrc;
3273	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3274	PX86PDEPAE pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT);
3275	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3276
3277	if (pPDSrc == NULL)
3278	{
3279	/* PDPE not present */
3280	if (pPdptDst->a[iPdpt].n.u1Present)
3281	{
3282	LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
3283	/* for each page directory entry */
3284	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3285	{
3286	if ( pPDEDst[iPD].n.u1Present
3287	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3288	{
3289	pgmPoolFree(pVM, pPDEDst[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
3290	pPDEDst[iPD].u = 0;
3291	}
3292	}
3293	}
3294	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
3295	pPdptDst->a[iPdpt].n.u1Present = 0;
3296	continue;
3297	}
3298	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3299	{
3300	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3301	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3302	{
3303	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3304	if ((iPD & 255) == 0) /* Start of new PD. */
3305	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)iPD << GST_PD_SHIFT);
3306	# endif
3307	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3308	Assert(pgmShwGet32BitPDEPtr(&pVM->pgm.s, (uint32_t)iPD << SHW_PD_SHIFT) == pPDEDst);
3309	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3310	# if defined(VBOX_STRICT) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* Unfortuantely not reliable with PGMR0DynMap and multiple VMs. */
3311	RTGCPTR GCPtrStrict = (uint32_t)iPD << GST_PD_SHIFT;
3312	# if PGM_GST_TYPE == PGM_TYPE_PAE
3313	GCPtrStrict \|= iPdpt << X86_PDPT_SHIFT;
3314	# endif
3315	AssertMsg(pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict) == pPDEDst, ("%p vs %p (%RGv)\n", pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict), pPDEDst, GCPtrStrict));
3316	# endif /* VBOX_STRICT */
3317	# endif
3318	GSTPDE PdeSrc = pPDSrc->a[iPD];
3319	if ( PdeSrc.n.u1Present
3320	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3321	{
3322	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3323	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3324	&& !defined(PGM_WITHOUT_MAPPINGS)
3325
3326	/*
3327	* Check for conflicts with GC mappings.
3328	*/
3329	# if PGM_GST_TYPE == PGM_TYPE_PAE
3330	if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
3331	# else
3332	if (iPD == iPdNoMapping)
3333	# endif
3334	{
3335	if (pVM->pgm.s.fMappingsFixed)
3336	{
3337	/* It's fixed, just skip the mapping. */
3338	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3339	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3340	iPD += cPTs - 1;
3341	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3342	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3343	# else
3344	pPDEDst += cPTs;
3345	# endif
3346	pMapping = pMapping->CTX_SUFF(pNext);
3347	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3348	continue;
3349	}
3350	# ifdef IN_RING3
3351	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3352	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3353	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3354	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3355	# endif
3356	if (RT_FAILURE(rc))
3357	return rc;
3358
3359	/*
3360	* Update iPdNoMapping and pMapping.
3361	*/
3362	pMapping = pVM->pgm.s.pMappingsR3;
3363	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3364	pMapping = pMapping->pNextR3;
3365	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3366	# else /* !IN_RING3 */
3367	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3368	return VINF_PGM_SYNC_CR3;
3369	# endif /* !IN_RING3 */
3370	}
3371	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3372	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3373	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3374
3375	/*
3376	* Sync page directory entry.
3377	*
3378	* The current approach is to allocated the page table but to set
3379	* the entry to not-present and postpone the page table synching till
3380	* it's actually used.
3381	*/
3382	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3383	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3384	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3385	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3386	# else
3387	const unsigned iPdShw = iPD; NOREF(iPdShw);
3388	# endif
3389	{
3390	SHWPDE PdeDst = *pPDEDst;
3391	if (PdeDst.n.u1Present)
3392	{
3393	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3394	RTGCPHYS GCPhys;
3395	if ( !PdeSrc.b.u1Size
3396	\|\| !fBigPagesSupported)
3397	{
3398	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3399	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3400	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3401	GCPhys \|= i * (PAGE_SIZE / 2);
3402	# endif
3403	}
3404	else
3405	{
3406	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3407	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3408	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3409	GCPhys \|= i * X86_PAGE_2M_SIZE;
3410	# endif
3411	}
3412
3413	if ( pShwPage->GCPhys == GCPhys
3414	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3415	&& ( pShwPage->fCached
3416	\|\| ( !fGlobal
3417	&& ( false
3418	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3419	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3420	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3421	\|\| ( !pShwPage->fSeenNonGlobal
3422	&& (cr4 & X86_CR4_PGE))
3423	# endif
3424	)
3425	)
3426	)
3427	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3428	\|\| ( fBigPagesSupported
3429	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3430	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3431	)
3432	)
3433	{
3434	# ifdef VBOX_WITH_STATISTICS
3435	if ( !fGlobal
3436	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3437	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3438	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3439	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3440	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3441	else
3442	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3443	# endif /* VBOX_WITH_STATISTICS */
3444	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3445	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3446	//# ifdef PGMPOOL_WITH_CACHE
3447	// pgmPoolCacheUsed(pPool, pShwPage);
3448	//# endif
3449	}
3450	else
3451	{
3452	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3453	pPDEDst->u = 0;
3454	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3455	}
3456	}
3457	else
3458	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3459
3460	/* advance */
3461	pPDEDst++;
3462	} /* foreach 2MB PAE PDE in 4MB guest PDE */
3463	}
3464	# if PGM_GST_TYPE == PGM_TYPE_PAE
3465	else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
3466	# else
3467	else if (iPD != iPdNoMapping)
3468	# endif
3469	{
3470	/*
3471	* Check if there is any page directory to mark not present here.
3472	*/
3473	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3474	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3475	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3476	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES;
3477	# else
3478	const unsigned iPdShw = iPD;
3479	# endif
3480	{
3481	if (pPDEDst->n.u1Present)
3482	{
3483	pgmPoolFree(pVM, pPDEDst->u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdShw);
3484	pPDEDst->u = 0;
3485	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3486	}
3487	pPDEDst++;
3488	}
3489	}
3490	else
3491	{
3492	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3493	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3494	&& !defined(PGM_WITHOUT_MAPPINGS)
3495
3496	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3497
3498	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3499	if (pVM->pgm.s.fMappingsFixed)
3500	{
3501	/* It's fixed, just skip the mapping. */
3502	pMapping = pMapping->CTX_SUFF(pNext);
3503	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3504	}
3505	else
3506	{
3507	/*
3508	* Check for conflicts for subsequent pagetables
3509	* and advance to the next mapping.
3510	*/
3511	iPdNoMapping = ~0U;
3512	unsigned iPT = cPTs;
3513	while (iPT-- > 1)
3514	{
3515	if ( pPDSrc->a[iPD + iPT].n.u1Present
3516	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3517	{
3518	# ifdef IN_RING3
3519	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3520	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3521	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3522	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3523	# endif
3524	if (RT_FAILURE(rc))
3525	return rc;
3526
3527	/*
3528	* Update iPdNoMapping and pMapping.
3529	*/
3530	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3531	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3532	pMapping = pMapping->CTX_SUFF(pNext);
3533	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3534	break;
3535	# else
3536	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3537	return VINF_PGM_SYNC_CR3;
3538	# endif
3539	}
3540	}
3541	if (iPdNoMapping == ~0U && pMapping)
3542	{
3543	pMapping = pMapping->CTX_SUFF(pNext);
3544	if (pMapping)
3545	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3546	}
3547	}
3548
3549	/* advance. */
3550	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3551	iPD += cPTs - 1;
3552	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3553	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3554	# else
3555	pPDEDst += cPTs;
3556	# endif
3557	# if PGM_GST_TYPE != PGM_SHW_TYPE
3558	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3559	# endif
3560	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3561	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3562	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3563	}
3564
3565	} /* for iPD */
3566	} /* for each PDPTE (PAE) */
3567	return VINF_SUCCESS;
3568
3569	# else /* guest real and protected mode */
3570	return VINF_SUCCESS;
3571	# endif
3572	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3573	}
3574
3575
3576
3577
3578	#ifdef VBOX_STRICT
3579	#ifdef IN_RC
3580	# undef AssertMsgFailed
3581	# define AssertMsgFailed Log
3582	#endif
3583	#ifdef IN_RING3
3584	# include <VBox/dbgf.h>
3585
3586	/**
3587	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3588	*
3589	* @returns VBox status code (VINF_SUCCESS).
3590	* @param pVM The VM handle.
3591	* @param cr3 The root of the hierarchy.
3592	* @param crr The cr4, only PAE and PSE is currently used.
3593	* @param fLongMode Set if long mode, false if not long mode.
3594	* @param cMaxDepth Number of levels to dump.
3595	* @param pHlp Pointer to the output functions.
3596	*/
3597	__BEGIN_DECLS
3598	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3599	__END_DECLS
3600
3601	#endif
3602
3603	/**
3604	* Checks that the shadow page table is in sync with the guest one.
3605	*
3606	* @returns The number of errors.
3607	* @param pVM The virtual machine.
3608	* @param cr3 Guest context CR3 register
3609	* @param cr4 Guest context CR4 register
3610	* @param GCPtr Where to start. Defaults to 0.
3611	* @param cb How much to check. Defaults to everything.
3612	*/
3613	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3614	{
3615	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3616	return 0;
3617	#else
3618	unsigned cErrors = 0;
3619
3620	#if PGM_GST_TYPE == PGM_TYPE_PAE
3621	/** @todo currently broken; crashes below somewhere */
3622	AssertFailed();
3623	#endif
3624
3625	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3626	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3627	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3628
3629	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3630	bool fBigPagesSupported = true;
3631	# else
3632	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3633	# endif
3634	PPGM pPGM = &pVM->pgm.s;
3635	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3636	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3637	# ifndef IN_RING0
3638	RTHCPHYS HCPhys; /* general usage. */
3639	# endif
3640	int rc;
3641
3642	/*
3643	* Check that the Guest CR3 and all its mappings are correct.
3644	*/
3645	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3646	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3647	false);
3648	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3649	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3650	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3651	# else
3652	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3653	# endif
3654	AssertRCReturn(rc, 1);
3655	HCPhys = NIL_RTHCPHYS;
3656	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3657	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3658	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3659	RTGCPHYS GCPhys;
3660	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3661	AssertRCReturn(rc, 1);
3662	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3663	# endif
3664	# endif /* !IN_RING0 */
3665
3666	/*
3667	* Get and check the Shadow CR3.
3668	*/
3669	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3670	unsigned cPDEs = X86_PG_ENTRIES;
3671	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3672	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3673	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3674	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3675	# else
3676	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3677	# endif
3678	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3679	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3680	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3681	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3682	# endif
3683	if (cb != ~(RTGCPTR)0)
3684	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3685
3686	/** @todo call the other two PGMAssert() functions. /
3687
3688	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3689	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3690	# endif
3691
3692	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3693	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3694
3695	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3696	{
3697	PPGMPOOLPAGE pShwPdpt = NULL;
3698	PX86PML4E pPml4eSrc;
3699	PX86PML4E pPml4eDst;
3700	RTGCPHYS GCPhysPdptSrc;
3701
3702	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3703	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3704
3705	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3706	if (!pPml4eDst->n.u1Present)
3707	{
3708	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3709	continue;
3710	}
3711
3712	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3713	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3714
3715	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3716	{
3717	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3718	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3719	cErrors++;
3720	continue;
3721	}
3722
3723	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3724	{
3725	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3726	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3727	cErrors++;
3728	continue;
3729	}
3730
3731	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3732	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3733	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3734	{
3735	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3736	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3737	cErrors++;
3738	continue;
3739	}
3740	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3741	{
3742	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3743
3744	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3745	/*
3746	* Check the PDPTEs too.
3747	*/
3748	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3749
3750	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3751	{
3752	unsigned iPDSrc;
3753	PPGMPOOLPAGE pShwPde = NULL;
3754	PX86PDPE pPdpeDst;
3755	RTGCPHYS GCPhysPdeSrc;
3756	# if PGM_GST_TYPE == PGM_TYPE_PAE
3757	X86PDPE PdpeSrc;
3758	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3759	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3760	# else
3761	PX86PML4E pPml4eSrc;
3762	X86PDPE PdpeSrc;
3763	PX86PDPT pPdptDst;
3764	PX86PDPAE pPDDst;
3765	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3766
3767	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3768	if (rc != VINF_SUCCESS)
3769	{
3770	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3771	GCPtr += 512 * _2M;
3772	continue; /* next PDPTE */
3773	}
3774	Assert(pPDDst);
3775	# endif
3776	Assert(iPDSrc == 0);
3777
3778	pPdpeDst = &pPdptDst->a[iPdpt];
3779
3780	if (!pPdpeDst->n.u1Present)
3781	{
3782	GCPtr += 512 * _2M;
3783	continue; /* next PDPTE */
3784	}
3785
3786	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3787	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3788
3789	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3790	{
3791	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3792	GCPtr += 512 * _2M;
3793	cErrors++;
3794	continue;
3795	}
3796
3797	if (GCPhysPdeSrc != pShwPde->GCPhys)
3798	{
3799	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3800	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3801	# else
3802	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3803	# endif
3804	GCPtr += 512 * _2M;
3805	cErrors++;
3806	continue;
3807	}
3808
3809	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3810	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3811	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3812	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3813	{
3814	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3815	GCPtr += 512 * _2M;
3816	cErrors++;
3817	continue;
3818	}
3819	# endif
3820
3821	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3822	{
3823	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3824	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3825	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3826	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3827	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
3828	# endif
3829	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3830	/*
3831	* Iterate the shadow page directory.
3832	*/
3833	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3834	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3835
3836	for (;
3837	iPDDst < cPDEs;
3838	iPDDst++, GCPtr += cIncrement)
3839	{
3840	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3841	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3842	# else
3843	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3844	# endif
3845	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3846	{
3847	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3848	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3849	{
3850	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3851	cErrors++;
3852	continue;
3853	}
3854	}
3855	else if ( (PdeDst.u & X86_PDE_P)
3856	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3857	)
3858	{
3859	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3860	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3861	if (!pPoolPage)
3862	{
3863	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3864	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3865	cErrors++;
3866	continue;
3867	}
3868	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3869
3870	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3871	{
3872	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3873	GCPtr, (uint64_t)PdeDst.u));
3874	cErrors++;
3875	}
3876
3877	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3878	{
3879	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3880	GCPtr, (uint64_t)PdeDst.u));
3881	cErrors++;
3882	}
3883
3884	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3885	if (!PdeSrc.n.u1Present)
3886	{
3887	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3888	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3889	cErrors++;
3890	continue;
3891	}
3892
3893	if ( !PdeSrc.b.u1Size
3894	\|\| !fBigPagesSupported)
3895	{
3896	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3897	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3898	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3899	# endif
3900	}
3901	else
3902	{
3903	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3904	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3905	{
3906	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3907	GCPtr, (uint64_t)PdeSrc.u));
3908	cErrors++;
3909	continue;
3910	}
3911	# endif
3912	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3913	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3914	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3915	# endif
3916	}
3917
3918	if ( pPoolPage->enmKind
3919	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3920	{
3921	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3922	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3923	cErrors++;
3924	}
3925
3926	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3927	if (!pPhysPage)
3928	{
3929	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3930	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3931	cErrors++;
3932	continue;
3933	}
3934
3935	if (GCPhysGst != pPoolPage->GCPhys)
3936	{
3937	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3938	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3939	cErrors++;
3940	continue;
3941	}
3942
3943	if ( !PdeSrc.b.u1Size
3944	\|\| !fBigPagesSupported)
3945	{
3946	/*
3947	* Page Table.
3948	*/
3949	const GSTPT *pPTSrc;
3950	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3951	if (RT_FAILURE(rc))
3952	{
3953	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3954	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3955	cErrors++;
3956	continue;
3957	}
3958	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3959	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3960	{
3961	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3962	// (This problem will go away when/if we shadow multiple CR3s.)
3963	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3964	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3965	cErrors++;
3966	continue;
3967	}
3968	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3969	{
3970	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3971	GCPtr, (uint64_t)PdeDst.u));
3972	cErrors++;
3973	continue;
3974	}
3975
3976	/* iterate the page table. */
3977	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3978	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3979	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3980	# else
3981	const unsigned offPTSrc = 0;
3982	# endif
3983	for (unsigned iPT = 0, off = 0;
3984	iPT < RT_ELEMENTS(pPTDst->a);
3985	iPT++, off += PAGE_SIZE)
3986	{
3987	const SHWPTE PteDst = pPTDst->a[iPT];
3988
3989	/* skip not-present entries. */
3990	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3991	continue;
3992	Assert(PteDst.n.u1Present);
3993
3994	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3995	if (!PteSrc.n.u1Present)
3996	{
3997	# ifdef IN_RING3
3998	PGMAssertHandlerAndFlagsInSync(pVM);
3999	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4000	# endif
4001	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4002	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4003	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4004	cErrors++;
4005	continue;
4006	}
4007
4008	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4009	# if 1 /** @todo sync accessed bit properly... */
4010	fIgnoreFlags \|= X86_PTE_A;
4011	# endif
4012
4013	/* match the physical addresses */
4014	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4015	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4016
4017	# ifdef IN_RING3
4018	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4019	if (RT_FAILURE(rc))
4020	{
4021	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4022	{
4023	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4024	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4025	cErrors++;
4026	continue;
4027	}
4028	}
4029	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4030	{
4031	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4032	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4033	cErrors++;
4034	continue;
4035	}
4036	# endif
4037
4038	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4039	if (!pPhysPage)
4040	{
4041	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4042	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4043	{
4044	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4045	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4046	cErrors++;
4047	continue;
4048	}
4049	# endif
4050	if (PteDst.n.u1Write)
4051	{
4052	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4053	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4054	cErrors++;
4055	}
4056	fIgnoreFlags \|= X86_PTE_RW;
4057	}
4058	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4059	{
4060	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4061	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4062	cErrors++;
4063	continue;
4064	}
4065
4066	/* flags */
4067	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4068	{
4069	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4070	{
4071	if (PteDst.n.u1Write)
4072	{
4073	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4074	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4075	cErrors++;
4076	continue;
4077	}
4078	fIgnoreFlags \|= X86_PTE_RW;
4079	}
4080	else
4081	{
4082	if (PteDst.n.u1Present)
4083	{
4084	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4085	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4086	cErrors++;
4087	continue;
4088	}
4089	fIgnoreFlags \|= X86_PTE_P;
4090	}
4091	}
4092	else
4093	{
4094	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4095	{
4096	if (PteDst.n.u1Write)
4097	{
4098	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4100	cErrors++;
4101	continue;
4102	}
4103	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4104	{
4105	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4106	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4107	cErrors++;
4108	continue;
4109	}
4110	if (PteDst.n.u1Dirty)
4111	{
4112	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4113	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4114	cErrors++;
4115	}
4116	# if 0 /** @todo sync access bit properly... */
4117	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4118	{
4119	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4120	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4121	cErrors++;
4122	}
4123	fIgnoreFlags \|= X86_PTE_RW;
4124	# else
4125	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4126	# endif
4127	}
4128	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4129	{
4130	/* access bit emulation (not implemented). */
4131	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4132	{
4133	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4134	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4135	cErrors++;
4136	continue;
4137	}
4138	if (!PteDst.n.u1Accessed)
4139	{
4140	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4141	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4142	cErrors++;
4143	}
4144	fIgnoreFlags \|= X86_PTE_P;
4145	}
4146	# ifdef DEBUG_sandervl
4147	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4148	# endif
4149	}
4150
4151	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4152	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4153	)
4154	{
4155	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4156	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4157	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4158	cErrors++;
4159	continue;
4160	}
4161	} /* foreach PTE */
4162	}
4163	else
4164	{
4165	/*
4166	* Big Page.
4167	*/
4168	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4169	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4170	{
4171	if (PdeDst.n.u1Write)
4172	{
4173	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4174	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4175	cErrors++;
4176	continue;
4177	}
4178	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4179	{
4180	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4181	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4182	cErrors++;
4183	continue;
4184	}
4185	# if 0 /** @todo sync access bit properly... */
4186	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4187	{
4188	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4189	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4190	cErrors++;
4191	}
4192	fIgnoreFlags \|= X86_PTE_RW;
4193	# else
4194	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4195	# endif
4196	}
4197	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4198	{
4199	/* access bit emulation (not implemented). */
4200	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4201	{
4202	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4203	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4204	cErrors++;
4205	continue;
4206	}
4207	if (!PdeDst.n.u1Accessed)
4208	{
4209	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4210	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4211	cErrors++;
4212	}
4213	fIgnoreFlags \|= X86_PTE_P;
4214	}
4215
4216	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4217	{
4218	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4219	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4220	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4221	cErrors++;
4222	}
4223
4224	/* iterate the page table. */
4225	for (unsigned iPT = 0, off = 0;
4226	iPT < RT_ELEMENTS(pPTDst->a);
4227	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4228	{
4229	const SHWPTE PteDst = pPTDst->a[iPT];
4230
4231	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4232	{
4233	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4234	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4235	cErrors++;
4236	}
4237
4238	/* skip not-present entries. */
4239	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4240	continue;
4241
4242	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4243
4244	/* match the physical addresses */
4245	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4246
4247	# ifdef IN_RING3
4248	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4249	if (RT_FAILURE(rc))
4250	{
4251	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4252	{
4253	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4254	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4255	cErrors++;
4256	}
4257	}
4258	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4259	{
4260	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4261	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4262	cErrors++;
4263	continue;
4264	}
4265	# endif
4266	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4267	if (!pPhysPage)
4268	{
4269	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4270	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4271	{
4272	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4273	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4274	cErrors++;
4275	continue;
4276	}
4277	# endif
4278	if (PteDst.n.u1Write)
4279	{
4280	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4281	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4282	cErrors++;
4283	}
4284	fIgnoreFlags \|= X86_PTE_RW;
4285	}
4286	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4287	{
4288	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4289	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4290	cErrors++;
4291	continue;
4292	}
4293
4294	/* flags */
4295	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4296	{
4297	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4298	{
4299	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4300	{
4301	if (PteDst.n.u1Write)
4302	{
4303	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4304	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4305	cErrors++;
4306	continue;
4307	}
4308	fIgnoreFlags \|= X86_PTE_RW;
4309	}
4310	}
4311	else
4312	{
4313	if (PteDst.n.u1Present)
4314	{
4315	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4316	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4317	cErrors++;
4318	continue;
4319	}
4320	fIgnoreFlags \|= X86_PTE_P;
4321	}
4322	}
4323
4324	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4325	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4326	)
4327	{
4328	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4329	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4330	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4331	cErrors++;
4332	continue;
4333	}
4334	} /* for each PTE */
4335	}
4336	}
4337	/* not present */
4338
4339	} /* for each PDE */
4340
4341	} /* for each PDPTE */
4342
4343	} /* for each PML4E */
4344
4345	# ifdef DEBUG
4346	if (cErrors)
4347	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4348	# endif
4349
4350	#endif /* GST == 32BIT, PAE or AMD64 */
4351	return cErrors;
4352
4353	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4354	}
4355	#endif /* VBOX_STRICT */
4356

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 16203

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