PGMAllBth.h@ 17285

Last change on this file since 17285 was 17285, checked in by vboxsync, 16 years ago
PGM: Gone are MM_RAM_FLAGS_CREFS_SHIFT and MM_RAM_FLAGS_CREFS_MASK.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 207.8 KB

Line
1	/* $Id: PGMAllBth.h 17285 2009-03-03 14:34:35Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	* @param pVM VM Handle.
78	* @param uErr The trap error code.
79	* @param pRegFrame Trap register frame.
80	* @param pvFault The fault address.
81	*/
82	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
83	{
84	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && defined(VBOX_STRICT)
85	PGMDynCheckLocks(pVM);
86	# endif
87
88	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
89	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
90	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
91
92	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
93	/*
94	* Hide the instruction fetch trap indicator for now.
95	*/
96	/** @todo NXE will change this and we must fix NXE in the switcher too! */
97	if (uErr & X86_TRAP_PF_ID)
98	{
99	uErr &= ~X86_TRAP_PF_ID;
100	TRPMSetErrorCode(pVM, uErr);
101	}
102	# endif
103
104	/*
105	* Get PDs.
106	*/
107	int rc;
108	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
109	# if PGM_GST_TYPE == PGM_TYPE_32BIT
110	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
111	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
114
115	# if PGM_GST_TYPE == PGM_TYPE_PAE
116	unsigned iPDSrc;
117	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120	# else
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
122	# endif
123
124	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
125	unsigned iPDSrc;
126	PX86PML4E pPml4eSrc;
127	X86PDPE PdpeSrc;
128	PGSTPD pPDSrc;
129
130	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
131	Assert(pPml4eSrc);
132	# endif
133
134	/* Quick check for a valid guest trap. (PAE & AMD64) */
135	if (!pPDSrc)
136	{
137	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
138	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
139	# else
140	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
141	# endif
142	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
143	TRPMSetErrorCode(pVM, uErr);
144	return VINF_EM_RAW_GUEST_TRAP;
145	}
146	# endif
147
148	# else /* !PGM_WITH_PAGING */
149	PGSTPD pPDSrc = NULL;
150	const unsigned iPDSrc = 0;
151	# endif /* !PGM_WITH_PAGING */
152
153
154	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
155	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
156	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
159	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
160
161	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
162	PX86PDPAE pPDDst;
163	# if PGM_GST_TYPE != PGM_TYPE_PAE
164	X86PDPE PdpeSrc;
165
166	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
167	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
168	# endif
169	rc = pgmShwSyncPaePDPtr(pVM, pvFault, &PdpeSrc, &pPDDst);
170	if (rc != VINF_SUCCESS)
171	{
172	AssertRC(rc);
173	return rc;
174	}
175	Assert(pPDDst);
176
177	# else
178	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
179
180	/* Did we mark the PDPT as not present in SyncCR3? */
181	unsigned iPdpt = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
182	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
183	if (!pPdptDst->a[iPdpt].n.u1Present)
184	pPdptDst->a[iPdpt].n.u1Present = 1;
185	# endif
186
187	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
188	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
189	PX86PDPAE pPDDst;
190	# if PGM_GST_TYPE == PGM_TYPE_PROT
191	/* AMD-V nested paging */
192	X86PML4E Pml4eSrc;
193	X86PDPE PdpeSrc;
194	PX86PML4E pPml4eSrc = &Pml4eSrc;
195
196	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
197	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
198	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
199	# endif
200
201	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
202	if (rc != VINF_SUCCESS)
203	{
204	AssertRC(rc);
205	return rc;
206	}
207	Assert(pPDDst);
208
209	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
210	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
211	PEPTPD pPDDst;
212
213	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
214	if (rc != VINF_SUCCESS)
215	{
216	AssertRC(rc);
217	return rc;
218	}
219	Assert(pPDDst);
220	# endif
221
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	/*
224	* If we successfully correct the write protection fault due to dirty bit
225	* tracking, or this page fault is a genuine one, then return immediately.
226	*/
227	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
228	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
229	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
230	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
231	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
232	{
233	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
234	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
235	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
236	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
237	}
238
239	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
240	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
241
242	/*
243	* A common case is the not-present error caused by lazy page table syncing.
244	*
245	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
246	* so we can safely assume that the shadow PT is present when calling SyncPage later.
247	*
248	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
249	* of mapping conflict and defer to SyncCR3 in R3.
250	* (Again, we do NOT support access handlers for non-present guest pages.)
251	*
252	*/
253	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
254	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
255	# else
256	GSTPDE PdeSrc;
257	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
258	PdeSrc.n.u1Present = 1;
259	PdeSrc.n.u1Write = 1;
260	PdeSrc.n.u1Accessed = 1;
261	PdeSrc.n.u1User = 1;
262	# endif
263	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
264	&& !pPDDst->a[iPDDst].n.u1Present
265	&& PdeSrc.n.u1Present
266	)
267
268	{
269	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
270	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
272	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
273	if (RT_SUCCESS(rc))
274	{
275	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
276	return rc;
277	}
278	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
279	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
280	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
281	return VINF_PGM_SYNC_CR3;
282	}
283
284	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
285	/*
286	* Check if this address is within any of our mappings.
287	*
288	* This is very fast and it's gonna save us a bit of effort below and prevent
289	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
290	* (BTW, it's impossible to have physical access handlers in a mapping.)
291	*/
292	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
293	{
294	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
295	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
296	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
297	{
298	if (pvFault < pMapping->GCPtr)
299	break;
300	if (pvFault - pMapping->GCPtr < pMapping->cb)
301	{
302	/*
303	* The first thing we check is if we've got an undetected conflict.
304	*/
305	if (!pVM->pgm.s.fMappingsFixed)
306	{
307	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
308	while (iPT-- > 0)
309	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
310	{
311	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
312	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
313	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
314	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
315	return VINF_PGM_SYNC_CR3;
316	}
317	}
318
319	/*
320	* Check if the fault address is in a virtual page access handler range.
321	*/
322	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
323	if ( pCur
324	&& pvFault - pCur->Core.Key < pCur->cb
325	&& uErr & X86_TRAP_PF_RW)
326	{
327	# ifdef IN_RC
328	STAM_PROFILE_START(&pCur->Stat, h);
329	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
330	STAM_PROFILE_STOP(&pCur->Stat, h);
331	# else
332	AssertFailed();
333	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
334	# endif
335	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
336	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
337	return rc;
338	}
339
340	/*
341	* Pretend we're not here and let the guest handle the trap.
342	*/
343	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
344	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
345	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
346	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
347	return VINF_EM_RAW_GUEST_TRAP;
348	}
349	}
350	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
351	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
352	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
353
354	/*
355	* Check if this fault address is flagged for special treatment,
356	* which means we'll have to figure out the physical address and
357	* check flags associated with it.
358	*
359	* ASSUME that we can limit any special access handling to pages
360	* in page tables which the guest believes to be present.
361	*/
362	if (PdeSrc.n.u1Present)
363	{
364	RTGCPHYS GCPhys = NIL_RTGCPHYS;
365
366	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
367	# if PGM_GST_TYPE == PGM_TYPE_AMD64
368	bool fBigPagesSupported = true;
369	# else
370	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
371	# endif
372	if ( PdeSrc.b.u1Size
373	&& fBigPagesSupported)
374	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
375	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
376	else
377	{
378	PGSTPT pPTSrc;
379	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
380	if (RT_SUCCESS(rc))
381	{
382	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
383	if (pPTSrc->a[iPTESrc].n.u1Present)
384	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
385	}
386	}
387	# else
388	/* No paging so the fault address is the physical address */
389	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
390	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
391
392	/*
393	* If we have a GC address we'll check if it has any flags set.
394	*/
395	if (GCPhys != NIL_RTGCPHYS)
396	{
397	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
398
399	PPGMPAGE pPage;
400	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
401	if (RT_SUCCESS(rc))
402	{
403	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
404	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
405	{
406	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
407	{
408	/*
409	* Physical page access handler.
410	*/
411	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
412	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
413	if (pCur)
414	{
415	# ifdef PGM_SYNC_N_PAGES
416	/*
417	* If the region is write protected and we got a page not present fault, then sync
418	* the pages. If the fault was caused by a read, then restart the instruction.
419	* In case of write access continue to the GC write handler.
420	*
421	* ASSUMES that there is only one handler per page or that they have similar write properties.
422	*/
423	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
424	&& !(uErr & X86_TRAP_PF_P))
425	{
426	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
427	if ( RT_FAILURE(rc)
428	\|\| !(uErr & X86_TRAP_PF_RW)
429	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
430	{
431	AssertRC(rc);
432	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
433	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
434	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
435	return rc;
436	}
437	}
438	# endif
439
440	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
441	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
442	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
443
444	# if defined(IN_RC) \|\| defined(IN_RING0)
445	if (pCur->CTX_SUFF(pfnHandler))
446	{
447	STAM_PROFILE_START(&pCur->Stat, h);
448	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
449	STAM_PROFILE_STOP(&pCur->Stat, h);
450	}
451	else
452	# endif
453	rc = VINF_EM_RAW_EMULATE_INSTR;
454	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
455	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
456	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
457	return rc;
458	}
459	}
460	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
461	else
462	{
463	# ifdef PGM_SYNC_N_PAGES
464	/*
465	* If the region is write protected and we got a page not present fault, then sync
466	* the pages. If the fault was caused by a read, then restart the instruction.
467	* In case of write access continue to the GC write handler.
468	*/
469	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
470	&& !(uErr & X86_TRAP_PF_P))
471	{
472	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
473	if ( RT_FAILURE(rc)
474	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
475	\|\| !(uErr & X86_TRAP_PF_RW))
476	{
477	AssertRC(rc);
478	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
479	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
480	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
481	return rc;
482	}
483	}
484	# endif
485	/*
486	* Ok, it's an virtual page access handler.
487	*
488	* Since it's faster to search by address, we'll do that first
489	* and then retry by GCPhys if that fails.
490	*/
491	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
492	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
493	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
494	*/
495	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
496	if (pCur)
497	{
498	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
499	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
500	\|\| !(uErr & X86_TRAP_PF_P)
501	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
502	("Unexpected trap for virtual handler: %RGv (phys=%RGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
503
504	if ( pvFault - pCur->Core.Key < pCur->cb
505	&& ( uErr & X86_TRAP_PF_RW
506	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
507	{
508	# ifdef IN_RC
509	STAM_PROFILE_START(&pCur->Stat, h);
510	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
511	STAM_PROFILE_STOP(&pCur->Stat, h);
512	# else
513	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
514	# endif
515	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
517	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
518	return rc;
519	}
520	/* Unhandled part of a monitored page */
521	}
522	else
523	{
524	/* Check by physical address. */
525	PPGMVIRTHANDLER pCur;
526	unsigned iPage;
527	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
528	&pCur, &iPage);
529	Assert(RT_SUCCESS(rc) \|\| !pCur);
530	if ( pCur
531	&& ( uErr & X86_TRAP_PF_RW
532	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
533	{
534	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
535	# ifdef IN_RC
536	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
537	Assert(off < pCur->cb);
538	STAM_PROFILE_START(&pCur->Stat, h);
539	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
540	STAM_PROFILE_STOP(&pCur->Stat, h);
541	# else
542	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
543	# endif
544	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
545	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
546	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
547	return rc;
548	}
549	}
550	}
551	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	/*
554	* There is a handled area of the page, but this fault doesn't belong to it.
555	* We must emulate the instruction.
556	*
557	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
558	* we first check if this was a page-not-present fault for a page with only
559	* write access handlers. Restart the instruction if it wasn't a write access.
560	*/
561	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
562
563	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
564	&& !(uErr & X86_TRAP_PF_P))
565	{
566	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
567	if ( RT_FAILURE(rc)
568	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
569	\|\| !(uErr & X86_TRAP_PF_RW))
570	{
571	AssertRC(rc);
572	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
573	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
574	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
575	return rc;
576	}
577	}
578
579	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
580	* It's writing to an unhandled part of the LDT page several million times.
581	*/
582	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
583	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
584	rc, pPage->HCPhys,
585	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
586	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
587	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
588	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
589	return rc;
590	} /* if any kind of handler */
591
592	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
593	if (uErr & X86_TRAP_PF_P)
594	{
595	/*
596	* The page isn't marked, but it might still be monitored by a virtual page access handler.
597	* (ASSUMES no temporary disabling of virtual handlers.)
598	*/
599	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
600	* we should correct both the shadow page table and physical memory flags, and not only check for
601	* accesses within the handler region but for access to pages with virtual handlers. */
602	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
603	if (pCur)
604	{
605	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
606	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
607	\|\| !(uErr & X86_TRAP_PF_P)
608	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
609	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
610
611	if ( pvFault - pCur->Core.Key < pCur->cb
612	&& ( uErr & X86_TRAP_PF_RW
613	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
614	{
615	# ifdef IN_RC
616	STAM_PROFILE_START(&pCur->Stat, h);
617	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
618	STAM_PROFILE_STOP(&pCur->Stat, h);
619	# else
620	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
621	# endif
622	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
623	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
624	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
625	return rc;
626	}
627	}
628	}
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630	}
631	else
632	{
633	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
634	* back to the recompiler to emulate the instruction.
635	*/
636	LogFlow(("pgmPhysGetPageEx %RGp failed with %Rrc\n", GCPhys, rc));
637	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
638	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
639	return VINF_EM_RAW_EMULATE_INSTR;
640	}
641
642	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
643
644	# ifdef PGM_OUT_OF_SYNC_IN_GC
645	/*
646	* We are here only if page is present in Guest page tables and trap is not handled
647	* by our handlers.
648	* Check it for page out-of-sync situation.
649	*/
650	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
651
652	if (!(uErr & X86_TRAP_PF_P))
653	{
654	/*
655	* Page is not present in our page tables.
656	* Try to sync it!
657	* BTW, fPageShw is invalid in this branch!
658	*/
659	if (uErr & X86_TRAP_PF_US)
660	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
661	else /* supervisor */
662	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
663
664	# if defined(LOG_ENABLED) && !defined(IN_RING0)
665	RTGCPHYS GCPhys;
666	uint64_t fPageGst;
667	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
668	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
669	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
670	# endif /* LOG_ENABLED */
671
672	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
673	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
674	{
675	uint64_t fPageGst;
676	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
677	if ( RT_SUCCESS(rc)
678	&& !(fPageGst & X86_PTE_US))
679	{
680	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
681	if ( pvFault == (RTGCPTR)pRegFrame->eip
682	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
683	# ifdef CSAM_DETECT_NEW_CODE_PAGES
684	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
685	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
686	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
687	)
688	{
689	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
690	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
691	if (rc != VINF_SUCCESS)
692	{
693	/*
694	* CSAM needs to perform a job in ring 3.
695	*
696	* Sync the page before going to the host context; otherwise we'll end up in a loop if
697	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
698	*/
699	LogFlow(("CSAM ring 3 job\n"));
700	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
701	AssertRC(rc2);
702
703	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
704	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
705	return rc;
706	}
707	}
708	# ifdef CSAM_DETECT_NEW_CODE_PAGES
709	else if ( uErr == X86_TRAP_PF_RW
710	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
711	&& pRegFrame->ecx < 0x10000)
712	{
713	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
714	* to detect loading of new code pages.
715	*/
716
717	/*
718	* Decode the instruction.
719	*/
720	RTGCPTR PC;
721	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
722	if (rc == VINF_SUCCESS)
723	{
724	DISCPUSTATE Cpu;
725	uint32_t cbOp;
726	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
727
728	/* For now we'll restrict this to rep movsw/d instructions */
729	if ( rc == VINF_SUCCESS
730	&& Cpu.pCurInstr->opcode == OP_MOVSWD
731	&& (Cpu.prefix & PREFIX_REP))
732	{
733	CSAMMarkPossibleCodePage(pVM, pvFault);
734	}
735	}
736	}
737	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
738
739	/*
740	* Mark this page as safe.
741	*/
742	/** @todo not correct for pages that contain both code and data!! */
743	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
744	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
745	}
746	}
747	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
748	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
749	if (RT_SUCCESS(rc))
750	{
751	/* The page was successfully synced, return to the guest. */
752	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
753	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
754	return VINF_SUCCESS;
755	}
756	}
757	else
758	{
759	/*
760	* A side effect of not flushing global PDEs are out of sync pages due
761	* to physical monitored regions, that are no longer valid.
762	* Assume for now it only applies to the read/write flag
763	*/
764	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
765	{
766	if (uErr & X86_TRAP_PF_US)
767	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
768	else /* supervisor */
769	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
770
771
772	/*
773	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
774	*/
775	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
776	if (RT_SUCCESS(rc))
777	{
778	/*
779	* Page was successfully synced, return to guest.
780	*/
781	# ifdef VBOX_STRICT
782	RTGCPHYS GCPhys;
783	uint64_t fPageGst;
784	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
785	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
786	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
787
788	uint64_t fPageShw;
789	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
790	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
791	# endif /* VBOX_STRICT */
792	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
793	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
794	return VINF_SUCCESS;
795	}
796
797	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
798	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
799	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
800	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
801	{
802	uint64_t fPageGst;
803	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
804	if ( RT_SUCCESS(rc)
805	&& !(fPageGst & X86_PTE_RW))
806	{
807	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
808	if (RT_SUCCESS(rc))
809	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
810	else
811	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
812	return rc;
813	}
814	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
815	}
816	}
817
818	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
819	# ifdef VBOX_STRICT
820	/*
821	* Check for VMM page flags vs. Guest page flags consistency.
822	* Currently only for debug purposes.
823	*/
824	if (RT_SUCCESS(rc))
825	{
826	/* Get guest page flags. */
827	uint64_t fPageGst;
828	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
829	if (RT_SUCCESS(rc))
830	{
831	uint64_t fPageShw;
832	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
833
834	/*
835	* Compare page flags.
836	* Note: we have AVL, A, D bits desynched.
837	*/
838	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
839	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
840	}
841	else
842	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
843	}
844	else
845	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
846	# endif /* VBOX_STRICT */
847	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
848	}
849	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
850	# endif /* PGM_OUT_OF_SYNC_IN_GC */
851	}
852	else
853	{
854	/*
855	* Page not present in Guest OS or invalid page table address.
856	* This is potential virtual page access handler food.
857	*
858	* For the present we'll say that our access handlers don't
859	* work for this case - we've already discarded the page table
860	* not present case which is identical to this.
861	*
862	* When we perchance find we need this, we will probably have AVL
863	* trees (offset based) to operate on and we can measure their speed
864	* agains mapping a page table and probably rearrange this handling
865	* a bit. (Like, searching virtual ranges before checking the
866	* physical address.)
867	*/
868	}
869	}
870
871
872	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
873	/*
874	* Conclusion, this is a guest trap.
875	*/
876	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
877	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
878	return VINF_EM_RAW_GUEST_TRAP;
879	# else
880	/* present, but not a monitored page; perhaps the guest is probing physical memory */
881	return VINF_EM_RAW_EMULATE_INSTR;
882	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
883
884
885	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
886
887	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
888	return VERR_INTERNAL_ERROR;
889	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
890	}
891	#endif /* !IN_RING3 */
892
893
894	/**
895	* Emulation of the invlpg instruction.
896	*
897	*
898	* @returns VBox status code.
899	*
900	* @param pVM VM handle.
901	* @param GCPtrPage Page to invalidate.
902	*
903	* @remark ASSUMES that the guest is updating before invalidating. This order
904	* isn't required by the CPU, so this is speculative and could cause
905	* trouble.
906	*
907	* @todo Flush page or page directory only if necessary!
908	* @todo Add a #define for simply invalidating the page.
909	*/
910	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
911	{
912	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
913	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
914	&& PGM_SHW_TYPE != PGM_TYPE_EPT
915	int rc;
916
917	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
918	/*
919	* Get the shadow PD entry and skip out if this PD isn't present.
920	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
921	*/
922	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
923	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
924	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
925
926	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
927	/* Fetch the pgm pool shadow descriptor. */
928	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
929	Assert(pShwPde);
930	# endif
931
932	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
933	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
934	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
935
936	/* If the shadow PDPE isn't present, then skip the invalidate. */
937	if (!pPdptDst->a[iPdpt].n.u1Present)
938	{
939	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
940	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
941	return VINF_SUCCESS;
942	}
943
944	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
945	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
946	PPGMPOOLPAGE pShwPde;
947	PX86PDPAE pPDDst;
948
949	/* Fetch the pgm pool shadow descriptor. */
950	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
951	AssertRCSuccessReturn(rc, rc);
952	Assert(pShwPde);
953
954	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
955	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
956	# else
957	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - pool index only atm! /;
958	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
959	# endif
960
961	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
962	/* PML4 */
963	AssertReturn(pVM->pgm.s.pShwRootR3, VERR_INTERNAL_ERROR);
964
965	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
966	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
967	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
968	PX86PDPAE pPDDst;
969	PX86PDPT pPdptDst;
970	PX86PML4E pPml4eDst;
971	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
972	if (rc != VINF_SUCCESS)
973	{
974	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
975	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
976	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
977	PGM_INVL_GUEST_TLBS();
978	return VINF_SUCCESS;
979	}
980	Assert(pPDDst);
981
982	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
983	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
984
985	if (!pPdpeDst->n.u1Present)
986	{
987	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
988	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
989	PGM_INVL_GUEST_TLBS();
990	return VINF_SUCCESS;
991	}
992
993	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
994
995	const SHWPDE PdeDst = *pPdeDst;
996	if (!PdeDst.n.u1Present)
997	{
998	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
999	return VINF_SUCCESS;
1000	}
1001
1002	/*
1003	* Get the guest PD entry and calc big page.
1004	*/
1005	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1006	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1007	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1008	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1009	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1010	unsigned iPDSrc;
1011	# if PGM_GST_TYPE == PGM_TYPE_PAE
1012	X86PDPE PdpeSrc;
1013	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1014	# else /* AMD64 */
1015	PX86PML4E pPml4eSrc;
1016	X86PDPE PdpeSrc;
1017	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1018	# endif
1019	GSTPDE PdeSrc;
1020
1021	if (pPDSrc)
1022	PdeSrc = pPDSrc->a[iPDSrc];
1023	else
1024	PdeSrc.u = 0;
1025	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1026
1027	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1028	const bool fIsBigPage = PdeSrc.b.u1Size;
1029	# else
1030	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1031	# endif
1032
1033	# ifdef IN_RING3
1034	/*
1035	* If a CR3 Sync is pending we may ignore the invalidate page operation
1036	* depending on the kind of sync and if it's a global page or not.
1037	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1038	*/
1039	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1040	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
1041	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
1042	&& fIsBigPage
1043	&& PdeSrc.b.u1Global
1044	)
1045	)
1046	# else
1047	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1048	# endif
1049	{
1050	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1051	return VINF_SUCCESS;
1052	}
1053	# endif /* IN_RING3 */
1054
1055	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1056	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1057
1058	/* Fetch the pgm pool shadow descriptor. */
1059	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1060	Assert(pShwPdpt);
1061
1062	/* Fetch the pgm pool shadow descriptor. */
1063	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1064	Assert(pShwPde);
1065
1066	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1067	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1068
1069	if ( !pPml4eSrc->n.u1Present
1070	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1071	{
1072	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1073	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1074	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1075	pPml4eDst->u = 0;
1076	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1077	PGM_INVL_GUEST_TLBS();
1078	return VINF_SUCCESS;
1079	}
1080	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1081	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1082	{
1083	/*
1084	* Mark not present so we can resync the PML4E when it's used.
1085	*/
1086	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1087	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1088	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1089	pPml4eDst->u = 0;
1090	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1091	PGM_INVL_GUEST_TLBS();
1092	}
1093	else if (!pPml4eSrc->n.u1Accessed)
1094	{
1095	/*
1096	* Mark not present so we can set the accessed bit.
1097	*/
1098	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1099	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1100	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1101	pPml4eDst->u = 0;
1102	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1103	PGM_INVL_GUEST_TLBS();
1104	}
1105
1106	/* Check if the PDPT entry has changed. */
1107	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1108	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1109	if ( !PdpeSrc.n.u1Present
1110	\|\| pShwPde->GCPhys != GCPhysPd)
1111	{
1112	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1113	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1114	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1115	pPdpeDst->u = 0;
1116	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1117	PGM_INVL_GUEST_TLBS();
1118	return VINF_SUCCESS;
1119	}
1120	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1121	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1122	{
1123	/*
1124	* Mark not present so we can resync the PDPTE when it's used.
1125	*/
1126	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1127	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1128	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1129	pPdpeDst->u = 0;
1130	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1131	PGM_INVL_GUEST_TLBS();
1132	}
1133	else if (!PdpeSrc.lm.u1Accessed)
1134	{
1135	/*
1136	* Mark not present so we can set the accessed bit.
1137	*/
1138	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1139	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1140	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1141	pPdpeDst->u = 0;
1142	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1143	PGM_INVL_GUEST_TLBS();
1144	}
1145	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1146
1147	# if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1148	/*
1149	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1150	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1151	*/
1152	if (!pPDSrc)
1153	{
1154	/* Guest PDPE not present */
1155	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
1156	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1157
1158	Assert(!PdpeSrc.n.u1Present);
1159	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
1160
1161	/* for each page directory entry */
1162	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1163	{
1164	if ( pPDDst->a[iPD].n.u1Present
1165	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
1166	{
1167	pgmPoolFree(pVM, pPDDst->a[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
1168	pPDDst->a[iPD].u = 0;
1169	}
1170	}
1171	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
1172	pPdptDst->a[iPdpt].n.u1Present = 0;
1173	PGM_INVL_GUEST_TLBS();
1174	}
1175	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
1176	# endif
1177
1178
1179	/*
1180	* Deal with the Guest PDE.
1181	*/
1182	rc = VINF_SUCCESS;
1183	if (PdeSrc.n.u1Present)
1184	{
1185	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1186	{
1187	/*
1188	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1189	*/
1190	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1191	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1192	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1193	}
1194	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1195	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1196	{
1197	/*
1198	* Mark not present so we can resync the PDE when it's used.
1199	*/
1200	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1201	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1202	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1203	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1204	# else
1205	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1206	# endif
1207	pPdeDst->u = 0;
1208	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1209	PGM_INVL_GUEST_TLBS();
1210	}
1211	else if (!PdeSrc.n.u1Accessed)
1212	{
1213	/*
1214	* Mark not present so we can set the accessed bit.
1215	*/
1216	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1217	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1218	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1219	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1220	# else
1221	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1222	# endif
1223	pPdeDst->u = 0;
1224	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1225	PGM_INVL_GUEST_TLBS();
1226	}
1227	else if (!fIsBigPage)
1228	{
1229	/*
1230	* 4KB - page.
1231	*/
1232	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1233	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1234	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1235	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1236	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1237	# endif
1238	if (pShwPage->GCPhys == GCPhys)
1239	{
1240	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1241	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1242	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1243	if (pPT->a[iPTEDst].n.u1Present)
1244	{
1245	# ifdef PGMPOOL_WITH_USER_TRACKING
1246	/* This is very unlikely with caching/monitoring enabled. */
1247	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1248	# endif
1249	pPT->a[iPTEDst].u = 0;
1250	}
1251	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1252	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1253	if (RT_SUCCESS(rc))
1254	rc = VINF_SUCCESS;
1255	# endif
1256	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1257	PGM_INVL_PG(GCPtrPage);
1258	}
1259	else
1260	{
1261	/*
1262	* The page table address changed.
1263	*/
1264	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1265	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1266	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1267	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1268	# else
1269	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1270	# endif
1271	pPdeDst->u = 0;
1272	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1273	PGM_INVL_GUEST_TLBS();
1274	}
1275	}
1276	else
1277	{
1278	/*
1279	* 2/4MB - page.
1280	*/
1281	/* Before freeing the page, check if anything really changed. */
1282	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1283	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1284	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1285	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1286	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1287	# endif
1288	if ( pShwPage->GCPhys == GCPhys
1289	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1290	{
1291	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1292	/** @todo PAT */
1293	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1294	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1295	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1296	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1297	{
1298	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1299	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1300	return VINF_SUCCESS;
1301	}
1302	}
1303
1304	/*
1305	* Ok, the page table is present and it's been changed in the guest.
1306	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1307	* We could do this for some flushes in GC too, but we need an algorithm for
1308	* deciding which 4MB pages containing code likely to be executed very soon.
1309	*/
1310	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1311	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1312	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1313	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1314	# else
1315	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1316	# endif
1317	pPdeDst->u = 0;
1318	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1319	PGM_INVL_BIG_PG(GCPtrPage);
1320	}
1321	}
1322	else
1323	{
1324	/*
1325	* Page directory is not present, mark shadow PDE not present.
1326	*/
1327	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1328	{
1329	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1330	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1331	# else
1332	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1333	# endif
1334	pPdeDst->u = 0;
1335	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1336	PGM_INVL_PG(GCPtrPage);
1337	}
1338	else
1339	{
1340	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1341	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1342	}
1343	}
1344
1345	return rc;
1346
1347	#else /* guest real and protected mode */
1348	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1349	return VINF_SUCCESS;
1350	#endif
1351	}
1352
1353
1354	#ifdef PGMPOOL_WITH_USER_TRACKING
1355	/**
1356	* Update the tracking of shadowed pages.
1357	*
1358	* @param pVM The VM handle.
1359	* @param pShwPage The shadow page.
1360	* @param HCPhys The physical page we is being dereferenced.
1361	*/
1362	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1363	{
1364	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1365	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1366	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1367
1368	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1369	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1370	* 2. write protect all shadowed pages. I.e. implement caching.
1371	*/
1372	/*
1373	* Find the guest address.
1374	*/
1375	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1376	pRam;
1377	pRam = pRam->CTX_SUFF(pNext))
1378	{
1379	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1380	while (iPage-- > 0)
1381	{
1382	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1383	{
1384	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1385	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1386	pShwPage->cPresent--;
1387	pPool->cPresent--;
1388	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1389	return;
1390	}
1391	}
1392	}
1393
1394	for (;;)
1395	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1396	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1397	pShwPage->cPresent--;
1398	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1399	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1400	}
1401
1402
1403	/**
1404	* Update the tracking of shadowed pages.
1405	*
1406	* @param pVM The VM handle.
1407	* @param pShwPage The shadow page.
1408	* @param u16 The top 16-bit of the pPage->HCPhys.
1409	* @param pPage Pointer to the guest page. this will be modified.
1410	* @param iPTDst The index into the shadow table.
1411	*/
1412	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1413	{
1414	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1415	/*
1416	* Just deal with the simple first time here.
1417	*/
1418	if (!u16)
1419	{
1420	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1421	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1422	}
1423	else
1424	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1425
1426	/* write back */
1427	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1428	PGM_PAGE_SET_TRACKING(pPage, u16);
1429
1430	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1431
1432	/* update statistics. */
1433	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1434	pShwPage->cPresent++;
1435	if (pShwPage->iFirstPresent > iPTDst)
1436	pShwPage->iFirstPresent = iPTDst;
1437	}
1438	#endif /* PGMPOOL_WITH_USER_TRACKING */
1439
1440
1441	/**
1442	* Creates a 4K shadow page for a guest page.
1443	*
1444	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1445	* physical address. The PdeSrc argument only the flags are used. No page structured
1446	* will be mapped in this function.
1447	*
1448	* @param pVM VM handle.
1449	* @param pPteDst Destination page table entry.
1450	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1451	* Can safely assume that only the flags are being used.
1452	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1453	* @param pShwPage Pointer to the shadow page.
1454	* @param iPTDst The index into the shadow table.
1455	*
1456	* @remark Not used for 2/4MB pages!
1457	*/
1458	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1459	{
1460	if (PteSrc.n.u1Present)
1461	{
1462	/*
1463	* Find the ram range.
1464	*/
1465	PPGMPAGE pPage;
1466	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1467	if (RT_SUCCESS(rc))
1468	{
1469	/** @todo investiage PWT, PCD and PAT. */
1470	/*
1471	* Make page table entry.
1472	*/
1473	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1474	SHWPTE PteDst;
1475	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1476	{
1477	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1478	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1479	{
1480	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1481	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1482	PteDst.n.u1Present = 1;
1483	PteDst.n.u1Execute = 1;
1484	PteDst.n.u1IgnorePAT = 1;
1485	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1486	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1487	#else
1488	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1489	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1490	#endif
1491	}
1492	else
1493	{
1494	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", HCPhys));
1495	PteDst.u = 0;
1496	}
1497	/** @todo count these two kinds. */
1498	}
1499	else
1500	{
1501	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1502	/*
1503	* If the page or page directory entry is not marked accessed,
1504	* we mark the page not present.
1505	*/
1506	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1507	{
1508	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1509	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1510	PteDst.u = 0;
1511	}
1512	else
1513	/*
1514	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1515	* when the page is modified.
1516	*/
1517	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1518	{
1519	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1520	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1521	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1522	\| PGM_PTFLAGS_TRACK_DIRTY;
1523	}
1524	else
1525	#endif
1526	{
1527	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1528	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1529	PteDst.u = (HCPhys & EPT_PTE_PG_MASK);
1530	PteDst.n.u1Present = 1;
1531	PteDst.n.u1Write = 1;
1532	PteDst.n.u1Execute = 1;
1533	PteDst.n.u1IgnorePAT = 1;
1534	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1535	/* PteDst.n.u1Size = 0 */
1536	#else
1537	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1538	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1539	#endif
1540	}
1541	}
1542
1543	#ifdef PGMPOOL_WITH_USER_TRACKING
1544	/*
1545	* Keep user track up to date.
1546	*/
1547	if (PteDst.n.u1Present)
1548	{
1549	if (!pPteDst->n.u1Present)
1550	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1551	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1552	{
1553	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1554	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1555	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1556	}
1557	}
1558	else if (pPteDst->n.u1Present)
1559	{
1560	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1561	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1562	}
1563	#endif /* PGMPOOL_WITH_USER_TRACKING */
1564
1565	/*
1566	* Update statistics and commit the entry.
1567	*/
1568	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1569	if (!PteSrc.n.u1Global)
1570	pShwPage->fSeenNonGlobal = true;
1571	#endif
1572	*pPteDst = PteDst;
1573	}
1574	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1575	/** @todo count these. */
1576	}
1577	else
1578	{
1579	/*
1580	* Page not-present.
1581	*/
1582	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1583	#ifdef PGMPOOL_WITH_USER_TRACKING
1584	/* Keep user track up to date. */
1585	if (pPteDst->n.u1Present)
1586	{
1587	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1588	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1589	}
1590	#endif /* PGMPOOL_WITH_USER_TRACKING */
1591	pPteDst->u = 0;
1592	/** @todo count these. */
1593	}
1594	}
1595
1596
1597	/**
1598	* Syncs a guest OS page.
1599	*
1600	* There are no conflicts at this point, neither is there any need for
1601	* page table allocations.
1602	*
1603	* @returns VBox status code.
1604	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1605	* @param pVM VM handle.
1606	* @param PdeSrc Page directory entry of the guest.
1607	* @param GCPtrPage Guest context page address.
1608	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1609	* @param uErr Fault error (X86_TRAP_PF_*).
1610	*/
1611	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1612	{
1613	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1614
1615	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1616	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1617	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1618	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1619	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1620
1621	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1622	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1623	# endif
1624
1625	/*
1626	* Assert preconditions.
1627	*/
1628	Assert(PdeSrc.n.u1Present);
1629	Assert(cPages);
1630	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1631
1632	/*
1633	* Get the shadow PDE, find the shadow page table in the pool.
1634	*/
1635	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1636	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1637	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
1638
1639	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1640	/* Fetch the pgm pool shadow descriptor. */
1641	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
1642	Assert(pShwPde);
1643	# endif
1644
1645	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1646
1647	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1648	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1649	PPGMPOOLPAGE pShwPde;
1650	PX86PDPAE pPDDst;
1651
1652	/* Fetch the pgm pool shadow descriptor. */
1653	int rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
1654	AssertRCSuccessReturn(rc, rc);
1655	Assert(pShwPde);
1656
1657	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1658	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1659	# else
1660	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
1661	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1662	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1663	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
1664	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
1665	# endif
1666	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1667	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1668	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1669	PX86PDPAE pPDDst;
1670	PX86PDPT pPdptDst;
1671
1672	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1673	AssertRCSuccessReturn(rc, rc);
1674	Assert(pPDDst && pPdptDst);
1675	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1676	# endif
1677
1678	SHWPDE PdeDst = *pPdeDst;
1679	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1680	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1681
1682	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1683	/* Fetch the pgm pool shadow descriptor. */
1684	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1685	Assert(pShwPde);
1686	# endif
1687
1688	/*
1689	* Check that the page is present and that the shadow PDE isn't out of sync.
1690	*/
1691	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1692	const bool fBigPage = PdeSrc.b.u1Size;
1693	# else
1694	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1695	# endif
1696	RTGCPHYS GCPhys;
1697	if (!fBigPage)
1698	{
1699	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1700	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1701	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1702	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1703	# endif
1704	}
1705	else
1706	{
1707	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1708	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1709	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1710	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1711	# endif
1712	}
1713	if ( pShwPage->GCPhys == GCPhys
1714	&& PdeSrc.n.u1Present
1715	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1716	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1717	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1718	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1719	# endif
1720	)
1721	{
1722	/*
1723	* Check that the PDE is marked accessed already.
1724	* Since we set the accessed bit before getting here on a #PF, this
1725	* check is only meant for dealing with non-#PF'ing paths.
1726	*/
1727	if (PdeSrc.n.u1Accessed)
1728	{
1729	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1730	if (!fBigPage)
1731	{
1732	/*
1733	* 4KB Page - Map the guest page table.
1734	*/
1735	PGSTPT pPTSrc;
1736	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1737	if (RT_SUCCESS(rc))
1738	{
1739	# ifdef PGM_SYNC_N_PAGES
1740	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1741	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1742	{
1743	/*
1744	* This code path is currently only taken when the caller is PGMTrap0eHandler
1745	* for non-present pages!
1746	*
1747	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1748	* deal with locality.
1749	*/
1750	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1751	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1752	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1753	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1754	# else
1755	const unsigned offPTSrc = 0;
1756	# endif
1757	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1758	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1759	iPTDst = 0;
1760	else
1761	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1762	for (; iPTDst < iPTDstEnd; iPTDst++)
1763	{
1764	if (!pPTDst->a[iPTDst].n.u1Present)
1765	{
1766	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1767	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1768	NOREF(GCPtrCurPage);
1769	#ifndef IN_RING0
1770	/*
1771	* Assuming kernel code will be marked as supervisor - and not as user level
1772	* and executed using a conforming code selector - And marked as readonly.
1773	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1774	*/
1775	PPGMPAGE pPage;
1776	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1777	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1778	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1779	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1780	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1781	)
1782	#endif /* else: CSAM not active */
1783	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1784	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1785	GCPtrCurPage, PteSrc.n.u1Present,
1786	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1787	PteSrc.n.u1User & PdeSrc.n.u1User,
1788	(uint64_t)PteSrc.u,
1789	(uint64_t)pPTDst->a[iPTDst].u,
1790	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1791	}
1792	}
1793	}
1794	else
1795	# endif /* PGM_SYNC_N_PAGES */
1796	{
1797	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1798	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1799	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1800	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1801	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1802	GCPtrPage, PteSrc.n.u1Present,
1803	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1804	PteSrc.n.u1User & PdeSrc.n.u1User,
1805	(uint64_t)PteSrc.u,
1806	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1807	}
1808	}
1809	else /* MMIO or invalid page: emulated in #PF handler. */
1810	{
1811	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1812	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1813	}
1814	}
1815	else
1816	{
1817	/*
1818	* 4/2MB page - lazy syncing shadow 4K pages.
1819	* (There are many causes of getting here, it's no longer only CSAM.)
1820	*/
1821	/* Calculate the GC physical address of this 4KB shadow page. */
1822	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1823	/* Find ram range. */
1824	PPGMPAGE pPage;
1825	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1826	if (RT_SUCCESS(rc))
1827	{
1828	/*
1829	* Make shadow PTE entry.
1830	*/
1831	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1832	SHWPTE PteDst;
1833	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1834	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1835	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1836	{
1837	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1838	PteDst.n.u1Write = 0;
1839	else
1840	PteDst.u = 0;
1841	}
1842	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1843	# ifdef PGMPOOL_WITH_USER_TRACKING
1844	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1845	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1846	# endif
1847	pPTDst->a[iPTDst] = PteDst;
1848
1849
1850	/*
1851	* If the page is not flagged as dirty and is writable, then make it read-only
1852	* at PD level, so we can set the dirty bit when the page is modified.
1853	*
1854	* ASSUMES that page access handlers are implemented on page table entry level.
1855	* Thus we will first catch the dirty access and set PDE.D and restart. If
1856	* there is an access handler, we'll trap again and let it work on the problem.
1857	*/
1858	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1859	* As for invlpg, it simply frees the whole shadow PT.
1860	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1861	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1862	{
1863	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1864	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1865	PdeDst.n.u1Write = 0;
1866	}
1867	else
1868	{
1869	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1870	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1871	}
1872	*pPdeDst = PdeDst;
1873	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1874	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1875	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1876	}
1877	else
1878	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1879	}
1880	return VINF_SUCCESS;
1881	}
1882	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1883	}
1884	else
1885	{
1886	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1887	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1888	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1889	}
1890
1891	/*
1892	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1893	* Yea, I'm lazy.
1894	*/
1895	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1896	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1897	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1898	# else
1899	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1900	# endif
1901
1902	pPdeDst->u = 0;
1903	PGM_INVL_GUEST_TLBS();
1904	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1905
1906	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1907	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1908	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1909
1910	# ifdef PGM_SYNC_N_PAGES
1911	/*
1912	* Get the shadow PDE, find the shadow page table in the pool.
1913	*/
1914	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1915	X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
1916
1917	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1918	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1919
1920	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1921	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1922	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1923	PX86PDPAE pPDDst;
1924	X86PDEPAE PdeDst;
1925	PX86PDPT pPdptDst;
1926
1927	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1928	AssertRCSuccessReturn(rc, rc);
1929	Assert(pPDDst && pPdptDst);
1930	PdeDst = pPDDst->a[iPDDst];
1931	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1932	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1933	PEPTPD pPDDst;
1934	EPTPDE PdeDst;
1935
1936	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1937	if (rc != VINF_SUCCESS)
1938	{
1939	AssertRC(rc);
1940	return rc;
1941	}
1942	Assert(pPDDst);
1943	PdeDst = pPDDst->a[iPDDst];
1944	# endif
1945	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1946	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1947	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1948
1949	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1950	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1951	{
1952	/*
1953	* This code path is currently only taken when the caller is PGMTrap0eHandler
1954	* for non-present pages!
1955	*
1956	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1957	* deal with locality.
1958	*/
1959	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1960	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1961	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1962	iPTDst = 0;
1963	else
1964	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1965	for (; iPTDst < iPTDstEnd; iPTDst++)
1966	{
1967	if (!pPTDst->a[iPTDst].n.u1Present)
1968	{
1969	GSTPTE PteSrc;
1970
1971	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1972
1973	/* Fake the page table entry */
1974	PteSrc.u = GCPtrCurPage;
1975	PteSrc.n.u1Present = 1;
1976	PteSrc.n.u1Dirty = 1;
1977	PteSrc.n.u1Accessed = 1;
1978	PteSrc.n.u1Write = 1;
1979	PteSrc.n.u1User = 1;
1980
1981	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1982
1983	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1984	GCPtrCurPage, PteSrc.n.u1Present,
1985	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1986	PteSrc.n.u1User & PdeSrc.n.u1User,
1987	(uint64_t)PteSrc.u,
1988	(uint64_t)pPTDst->a[iPTDst].u,
1989	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1990	}
1991	else
1992	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1993	}
1994	}
1995	else
1996	# endif /* PGM_SYNC_N_PAGES */
1997	{
1998	GSTPTE PteSrc;
1999	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2000	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2001
2002	/* Fake the page table entry */
2003	PteSrc.u = GCPtrCurPage;
2004	PteSrc.n.u1Present = 1;
2005	PteSrc.n.u1Dirty = 1;
2006	PteSrc.n.u1Accessed = 1;
2007	PteSrc.n.u1Write = 1;
2008	PteSrc.n.u1User = 1;
2009	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2010
2011	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2012	GCPtrPage, PteSrc.n.u1Present,
2013	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2014	PteSrc.n.u1User & PdeSrc.n.u1User,
2015	(uint64_t)PteSrc.u,
2016	(uint64_t)pPTDst->a[iPTDst].u,
2017	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2018	}
2019	return VINF_SUCCESS;
2020
2021	#else
2022	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2023	return VERR_INTERNAL_ERROR;
2024	#endif
2025	}
2026
2027
2028	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2029	/**
2030	* Investigate page fault and handle write protection page faults caused by
2031	* dirty bit tracking.
2032	*
2033	* @returns VBox status code.
2034	* @param pVM VM handle.
2035	* @param uErr Page fault error code.
2036	* @param pPdeDst Shadow page directory entry.
2037	* @param pPdeSrc Guest page directory entry.
2038	* @param GCPtrPage Guest context page address.
2039	*/
2040	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2041	{
2042	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
2043	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2044	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2045	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2046	bool fBigPagesSupported = true;
2047	# else
2048	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2049	# endif
2050	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2051	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
2052	# endif
2053	unsigned uPageFaultLevel;
2054	int rc;
2055
2056	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2057	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2058
2059	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2060	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2061
2062	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2063	PX86PML4E pPml4eSrc;
2064	PX86PDPE pPdpeSrc;
2065
2066	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2067	Assert(pPml4eSrc);
2068
2069	/*
2070	* Real page fault? (PML4E level)
2071	*/
2072	if ( (uErr & X86_TRAP_PF_RSVD)
2073	\|\| !pPml4eSrc->n.u1Present
2074	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2075	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2076	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2077	)
2078	{
2079	uPageFaultLevel = 0;
2080	goto l_UpperLevelPageFault;
2081	}
2082	Assert(pPdpeSrc);
2083
2084	# else /* PAE */
2085	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2086	# endif /* PAE */
2087
2088	/*
2089	* Real page fault? (PDPE level)
2090	*/
2091	if ( (uErr & X86_TRAP_PF_RSVD)
2092	\|\| !pPdpeSrc->n.u1Present
2093	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2094	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2095	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2096	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2097	# endif
2098	)
2099	{
2100	uPageFaultLevel = 1;
2101	goto l_UpperLevelPageFault;
2102	}
2103	# endif
2104
2105	/*
2106	* Real page fault? (PDE level)
2107	*/
2108	if ( (uErr & X86_TRAP_PF_RSVD)
2109	\|\| !pPdeSrc->n.u1Present
2110	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2111	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2112	# endif
2113	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2114	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2115	{
2116	uPageFaultLevel = 2;
2117	goto l_UpperLevelPageFault;
2118	}
2119
2120	/*
2121	* First check the easy case where the page directory has been marked read-only to track
2122	* the dirty bit of an emulated BIG page
2123	*/
2124	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2125	{
2126	/* Mark guest page directory as accessed */
2127	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2128	pPml4eSrc->n.u1Accessed = 1;
2129	pPdpeSrc->lm.u1Accessed = 1;
2130	# endif
2131	pPdeSrc->b.u1Accessed = 1;
2132
2133	/*
2134	* Only write protection page faults are relevant here.
2135	*/
2136	if (fWriteFault)
2137	{
2138	/* Mark guest page directory as dirty (BIG page only). */
2139	pPdeSrc->b.u1Dirty = 1;
2140
2141	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2142	{
2143	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2144
2145	Assert(pPdeSrc->b.u1Write);
2146
2147	pPdeDst->n.u1Write = 1;
2148	pPdeDst->n.u1Accessed = 1;
2149	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2150	PGM_INVL_BIG_PG(GCPtrPage);
2151	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2152	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2153	}
2154	}
2155	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2156	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2157	}
2158	/* else: 4KB page table */
2159
2160	/*
2161	* Map the guest page table.
2162	*/
2163	PGSTPT pPTSrc;
2164	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2165	if (RT_SUCCESS(rc))
2166	{
2167	/*
2168	* Real page fault?
2169	*/
2170	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2171	const GSTPTE PteSrc = *pPteSrc;
2172	if ( !PteSrc.n.u1Present
2173	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2174	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2175	# endif
2176	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2177	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2178	)
2179	{
2180	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2181	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2182	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2183
2184	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2185	* See the 2nd case above as well.
2186	*/
2187	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2188	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2189
2190	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2191	return VINF_EM_RAW_GUEST_TRAP;
2192	}
2193	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2194
2195	/*
2196	* Set the accessed bits in the page directory and the page table.
2197	*/
2198	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2199	pPml4eSrc->n.u1Accessed = 1;
2200	pPdpeSrc->lm.u1Accessed = 1;
2201	# endif
2202	pPdeSrc->n.u1Accessed = 1;
2203	pPteSrc->n.u1Accessed = 1;
2204
2205	/*
2206	* Only write protection page faults are relevant here.
2207	*/
2208	if (fWriteFault)
2209	{
2210	/* Write access, so mark guest entry as dirty. */
2211	# ifdef VBOX_WITH_STATISTICS
2212	if (!pPteSrc->n.u1Dirty)
2213	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2214	else
2215	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2216	# endif
2217
2218	pPteSrc->n.u1Dirty = 1;
2219
2220	if (pPdeDst->n.u1Present)
2221	{
2222	#ifndef IN_RING0
2223	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2224	* Our individual shadow handlers will provide more information and force a fatal exit.
2225	*/
2226	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2227	{
2228	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2229	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2230	return VINF_SUCCESS;
2231	}
2232	#endif
2233	/*
2234	* Map shadow page table.
2235	*/
2236	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2237	if (pShwPage)
2238	{
2239	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2240	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2241	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2242	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2243	{
2244	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2245	# ifdef VBOX_STRICT
2246	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2247	if (pPage)
2248	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2249	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2250	# endif
2251	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2252
2253	Assert(pPteSrc->n.u1Write);
2254
2255	pPteDst->n.u1Write = 1;
2256	pPteDst->n.u1Dirty = 1;
2257	pPteDst->n.u1Accessed = 1;
2258	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2259	PGM_INVL_PG(GCPtrPage);
2260
2261	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2262	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2263	}
2264	}
2265	else
2266	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2267	}
2268	}
2269	/** @todo Optimize accessed bit emulation? */
2270	# ifdef VBOX_STRICT
2271	/*
2272	* Sanity check.
2273	*/
2274	else if ( !pPteSrc->n.u1Dirty
2275	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2276	&& pPdeDst->n.u1Present)
2277	{
2278	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2279	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2280	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2281	if ( pPteDst->n.u1Present
2282	&& pPteDst->n.u1Write)
2283	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2284	}
2285	# endif /* VBOX_STRICT */
2286	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2287	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2288	}
2289	AssertRC(rc);
2290	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2291	return rc;
2292
2293
2294	l_UpperLevelPageFault:
2295	/*
2296	* Pagefault detected while checking the PML4E, PDPE or PDE.
2297	* Single exit handler to get rid of duplicate code paths.
2298	*/
2299	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2300	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2301	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2302
2303	if (
2304	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2305	pPml4eSrc->n.u1Present &&
2306	# endif
2307	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2308	pPdpeSrc->n.u1Present &&
2309	# endif
2310	pPdeSrc->n.u1Present)
2311	{
2312	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2313	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2314	{
2315	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2316	}
2317	else
2318	{
2319	/*
2320	* Map the guest page table.
2321	*/
2322	PGSTPT pPTSrc;
2323	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2324	if (RT_SUCCESS(rc))
2325	{
2326	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2327	const GSTPTE PteSrc = *pPteSrc;
2328	if (pPteSrc->n.u1Present)
2329	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2330	}
2331	AssertRC(rc);
2332	}
2333	}
2334	return VINF_EM_RAW_GUEST_TRAP;
2335	}
2336	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2337
2338
2339	/**
2340	* Sync a shadow page table.
2341	*
2342	* The shadow page table is not present. This includes the case where
2343	* there is a conflict with a mapping.
2344	*
2345	* @returns VBox status code.
2346	* @param pVM VM handle.
2347	* @param iPD Page directory index.
2348	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2349	* Assume this is a temporary mapping.
2350	* @param GCPtrPage GC Pointer of the page that caused the fault
2351	*/
2352	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2353	{
2354	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2355	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2356	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2357
2358	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2359	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2360	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2361	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2362	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2363
2364	int rc = VINF_SUCCESS;
2365
2366	/*
2367	* Validate input a little bit.
2368	*/
2369	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2370	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2371	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2372	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2373
2374	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2375	/* Fetch the pgm pool shadow descriptor. */
2376	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2377	Assert(pShwPde);
2378	# endif
2379
2380	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2381	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2382	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2383	PPGMPOOLPAGE pShwPde;
2384	PX86PDPAE pPDDst;
2385	PSHWPDE pPdeDst;
2386
2387	/* Fetch the pgm pool shadow descriptor. */
2388	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2389	AssertRCSuccessReturn(rc, rc);
2390	Assert(pShwPde);
2391
2392	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2393	pPdeDst = &pPDDst->a[iPDDst];
2394	# else
2395	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
2396	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
2397	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2398	PSHWPDE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2399	# endif
2400	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2401	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2402	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2403	PX86PDPAE pPDDst;
2404	PX86PDPT pPdptDst;
2405	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2406	AssertRCSuccessReturn(rc, rc);
2407	Assert(pPDDst);
2408	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2409	# endif
2410	SHWPDE PdeDst = *pPdeDst;
2411
2412	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2413	/* Fetch the pgm pool shadow descriptor. */
2414	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2415	Assert(pShwPde);
2416	# endif
2417
2418	# ifndef PGM_WITHOUT_MAPPINGS
2419	/*
2420	* Check for conflicts.
2421	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2422	* HC: Simply resolve the conflict.
2423	*/
2424	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2425	{
2426	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2427	# ifndef IN_RING3
2428	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2429	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2430	return VERR_ADDRESS_CONFLICT;
2431	# else
2432	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2433	Assert(pMapping);
2434	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2435	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2436	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2437	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2438	# else
2439	AssertFailed(); /* can't happen for amd64 */
2440	# endif
2441	if (RT_FAILURE(rc))
2442	{
2443	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2444	return rc;
2445	}
2446	PdeDst = *pPdeDst;
2447	# endif
2448	}
2449	# else /* PGM_WITHOUT_MAPPINGS */
2450	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2451	# endif /* PGM_WITHOUT_MAPPINGS */
2452	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2453
2454	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2455	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2456	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2457	# endif
2458
2459	/*
2460	* Sync page directory entry.
2461	*/
2462	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2463	if (PdeSrc.n.u1Present)
2464	{
2465	/*
2466	* Allocate & map the page table.
2467	*/
2468	PSHWPT pPTDst;
2469	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2470	const bool fPageTable = !PdeSrc.b.u1Size;
2471	# else
2472	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2473	# endif
2474	PPGMPOOLPAGE pShwPage;
2475	RTGCPHYS GCPhys;
2476	if (fPageTable)
2477	{
2478	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2479	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2480	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2481	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2482	# endif
2483	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2484	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2485	# else
2486	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2487	# endif
2488	}
2489	else
2490	{
2491	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2492	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2493	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2494	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2495	# endif
2496	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2497	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2498	# else
2499	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2500	# endif
2501	}
2502	if (rc == VINF_SUCCESS)
2503	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2504	else if (rc == VINF_PGM_CACHED_PAGE)
2505	{
2506	/*
2507	* The PT was cached, just hook it up.
2508	*/
2509	if (fPageTable)
2510	PdeDst.u = pShwPage->Core.Key
2511	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2512	else
2513	{
2514	PdeDst.u = pShwPage->Core.Key
2515	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2516	/* (see explanation and assumptions further down.) */
2517	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2518	{
2519	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2520	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2521	PdeDst.b.u1Write = 0;
2522	}
2523	}
2524	*pPdeDst = PdeDst;
2525	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2526	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2527	# endif
2528	return VINF_SUCCESS;
2529	}
2530	else if (rc == VERR_PGM_POOL_FLUSHED)
2531	{
2532	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2533	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2534	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2535	# endif
2536	return VINF_PGM_SYNC_CR3;
2537	}
2538	else
2539	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2540	PdeDst.u &= X86_PDE_AVL_MASK;
2541	PdeDst.u \|= pShwPage->Core.Key;
2542
2543	/*
2544	* Page directory has been accessed (this is a fault situation, remember).
2545	*/
2546	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2547	if (fPageTable)
2548	{
2549	/*
2550	* Page table - 4KB.
2551	*
2552	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2553	*/
2554	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2555	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2556	PGSTPT pPTSrc;
2557	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2558	if (RT_SUCCESS(rc))
2559	{
2560	/*
2561	* Start by syncing the page directory entry so CSAM's TLB trick works.
2562	*/
2563	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2564	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2565	*pPdeDst = PdeDst;
2566	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2567	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2568	# endif
2569
2570	/*
2571	* Directory/page user or supervisor privilege: (same goes for read/write)
2572	*
2573	* Directory Page Combined
2574	* U/S U/S U/S
2575	* 0 0 0
2576	* 0 1 0
2577	* 1 0 0
2578	* 1 1 1
2579	*
2580	* Simple AND operation. Table listed for completeness.
2581	*
2582	*/
2583	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2584	# ifdef PGM_SYNC_N_PAGES
2585	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2586	unsigned iPTDst = iPTBase;
2587	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2588	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2589	iPTDst = 0;
2590	else
2591	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2592	# else /* !PGM_SYNC_N_PAGES */
2593	unsigned iPTDst = 0;
2594	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2595	# endif /* !PGM_SYNC_N_PAGES */
2596	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2597	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2598	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2599	# else
2600	const unsigned offPTSrc = 0;
2601	# endif
2602	for (; iPTDst < iPTDstEnd; iPTDst++)
2603	{
2604	const unsigned iPTSrc = iPTDst + offPTSrc;
2605	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2606
2607	if (PteSrc.n.u1Present) /* we've already cleared it above */
2608	{
2609	# ifndef IN_RING0
2610	/*
2611	* Assuming kernel code will be marked as supervisor - and not as user level
2612	* and executed using a conforming code selector - And marked as readonly.
2613	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2614	*/
2615	PPGMPAGE pPage;
2616	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2617	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2618	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2619	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2620	)
2621	# endif
2622	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2623	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2624	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2625	PteSrc.n.u1Present,
2626	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2627	PteSrc.n.u1User & PdeSrc.n.u1User,
2628	(uint64_t)PteSrc.u,
2629	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2630	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2631	}
2632	} /* for PTEs */
2633	}
2634	}
2635	else
2636	{
2637	/*
2638	* Big page - 2/4MB.
2639	*
2640	* We'll walk the ram range list in parallel and optimize lookups.
2641	* We will only sync on shadow page table at a time.
2642	*/
2643	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2644
2645	/**
2646	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2647	*/
2648
2649	/*
2650	* Start by syncing the page directory entry.
2651	*/
2652	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2653	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2654
2655	/*
2656	* If the page is not flagged as dirty and is writable, then make it read-only
2657	* at PD level, so we can set the dirty bit when the page is modified.
2658	*
2659	* ASSUMES that page access handlers are implemented on page table entry level.
2660	* Thus we will first catch the dirty access and set PDE.D and restart. If
2661	* there is an access handler, we'll trap again and let it work on the problem.
2662	*/
2663	/** @todo move the above stuff to a section in the PGM documentation. */
2664	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2665	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2666	{
2667	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2668	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2669	PdeDst.b.u1Write = 0;
2670	}
2671	*pPdeDst = PdeDst;
2672	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2673	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2674	# endif
2675
2676	/*
2677	* Fill the shadow page table.
2678	*/
2679	/* Get address and flags from the source PDE. */
2680	SHWPTE PteDstBase;
2681	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2682
2683	/* Loop thru the entries in the shadow PT. */
2684	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2685	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2686	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2687	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2688	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2689	unsigned iPTDst = 0;
2690	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2691	{
2692	/* Advance ram range list. */
2693	while (pRam && GCPhys > pRam->GCPhysLast)
2694	pRam = pRam->CTX_SUFF(pNext);
2695	if (pRam && GCPhys >= pRam->GCPhys)
2696	{
2697	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2698	do
2699	{
2700	/* Make shadow PTE. */
2701	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2702	SHWPTE PteDst;
2703
2704	/* Make sure the RAM has already been allocated. */
2705	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2706	{
2707	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2708	{
2709	# ifdef IN_RING3
2710	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2711	# else
2712	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2713	# endif
2714	if (rc != VINF_SUCCESS)
2715	return rc;
2716	}
2717	}
2718
2719	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2720	{
2721	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2722	{
2723	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2724	PteDst.n.u1Write = 0;
2725	}
2726	else
2727	PteDst.u = 0;
2728	}
2729	# ifndef IN_RING0
2730	/*
2731	* Assuming kernel code will be marked as supervisor and not as user level and executed
2732	* using a conforming code selector. Don't check for readonly, as that implies the whole
2733	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2734	*/
2735	else if ( !PdeSrc.n.u1User
2736	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2737	PteDst.u = 0;
2738	# endif
2739	else
2740	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2741	# ifdef PGMPOOL_WITH_USER_TRACKING
2742	if (PteDst.n.u1Present)
2743	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2744	# endif
2745	/* commit it */
2746	pPTDst->a[iPTDst] = PteDst;
2747	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2748	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2749	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2750
2751	/* advance */
2752	GCPhys += PAGE_SIZE;
2753	iHCPage++;
2754	iPTDst++;
2755	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2756	&& GCPhys <= pRam->GCPhysLast);
2757	}
2758	else if (pRam)
2759	{
2760	Log(("Invalid pages at %RGp\n", GCPhys));
2761	do
2762	{
2763	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2764	GCPhys += PAGE_SIZE;
2765	iPTDst++;
2766	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2767	&& GCPhys < pRam->GCPhys);
2768	}
2769	else
2770	{
2771	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2772	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2773	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2774	}
2775	} /* while more PTEs */
2776	} /* 4KB / 4MB */
2777	}
2778	else
2779	AssertRelease(!PdeDst.n.u1Present);
2780
2781	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2782	if (RT_FAILURE(rc))
2783	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2784	return rc;
2785
2786	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2787	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2788	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2789
2790
2791	/*
2792	* Validate input a little bit.
2793	*/
2794	int rc = VINF_SUCCESS;
2795	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2796	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2797	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2798
2799	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2800	/* Fetch the pgm pool shadow descriptor. */
2801	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2802	Assert(pShwPde);
2803	# endif
2804
2805	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2806	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2807	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2808	PPGMPOOLPAGE pShwPde;
2809	PX86PDPAE pPDDst;
2810	PSHWPDE pPdeDst;
2811
2812	/* Fetch the pgm pool shadow descriptor. */
2813	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2814	AssertRCSuccessReturn(rc, rc);
2815	Assert(pShwPde);
2816
2817	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2818	pPdeDst = &pPDDst->a[iPDDst];
2819	# else
2820	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm!/;
2821	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2822	# endif
2823
2824	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2825	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2826	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2827	PX86PDPAE pPDDst;
2828	PX86PDPT pPdptDst;
2829	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2830	AssertRCSuccessReturn(rc, rc);
2831	Assert(pPDDst);
2832	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2833
2834	/* Fetch the pgm pool shadow descriptor. */
2835	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2836	Assert(pShwPde);
2837
2838	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2839	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2840	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2841	PEPTPD pPDDst;
2842	PEPTPDPT pPdptDst;
2843
2844	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2845	if (rc != VINF_SUCCESS)
2846	{
2847	AssertRC(rc);
2848	return rc;
2849	}
2850	Assert(pPDDst);
2851	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2852
2853	/* Fetch the pgm pool shadow descriptor. */
2854	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2855	Assert(pShwPde);
2856	# endif
2857	SHWPDE PdeDst = *pPdeDst;
2858
2859	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2860	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2861
2862	GSTPDE PdeSrc;
2863	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2864	PdeSrc.n.u1Present = 1;
2865	PdeSrc.n.u1Write = 1;
2866	PdeSrc.n.u1Accessed = 1;
2867	PdeSrc.n.u1User = 1;
2868
2869	/*
2870	* Allocate & map the page table.
2871	*/
2872	PSHWPT pPTDst;
2873	PPGMPOOLPAGE pShwPage;
2874	RTGCPHYS GCPhys;
2875
2876	/* Virtual address = physical address */
2877	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2878	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2879	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2880	# else
2881	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2882	# endif
2883
2884	if ( rc == VINF_SUCCESS
2885	\|\| rc == VINF_PGM_CACHED_PAGE)
2886	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2887	else
2888	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2889
2890	PdeDst.u &= X86_PDE_AVL_MASK;
2891	PdeDst.u \|= pShwPage->Core.Key;
2892	PdeDst.n.u1Present = 1;
2893	PdeDst.n.u1Write = 1;
2894	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2895	PdeDst.n.u1Execute = 1;
2896	# else
2897	PdeDst.n.u1User = 1;
2898	PdeDst.n.u1Accessed = 1;
2899	# endif
2900	*pPdeDst = PdeDst;
2901
2902	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2903	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2904	return rc;
2905
2906	#else
2907	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2908	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2909	return VERR_INTERNAL_ERROR;
2910	#endif
2911	}
2912
2913
2914
2915	/**
2916	* Prefetch a page/set of pages.
2917	*
2918	* Typically used to sync commonly used pages before entering raw mode
2919	* after a CR3 reload.
2920	*
2921	* @returns VBox status code.
2922	* @param pVM VM handle.
2923	* @param GCPtrPage Page to invalidate.
2924	*/
2925	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2926	{
2927	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2928	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2929	/*
2930	* Check that all Guest levels thru the PDE are present, getting the
2931	* PD and PDE in the processes.
2932	*/
2933	int rc = VINF_SUCCESS;
2934	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2935	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2936	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2937	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2938	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2939	unsigned iPDSrc;
2940	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2941	X86PDPE PdpeSrc;
2942	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
2943	# else
2944	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
2945	# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
2946	if (!pPDSrc)
2947	return VINF_SUCCESS; /* not present */
2948	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2949	unsigned iPDSrc;
2950	PX86PML4E pPml4eSrc;
2951	X86PDPE PdpeSrc;
2952	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2953	if (!pPDSrc)
2954	return VINF_SUCCESS; /* not present */
2955	# endif
2956	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2957	# else
2958	PGSTPD pPDSrc = NULL;
2959	const unsigned iPDSrc = 0;
2960	GSTPDE PdeSrc;
2961
2962	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2963	PdeSrc.n.u1Present = 1;
2964	PdeSrc.n.u1Write = 1;
2965	PdeSrc.n.u1Accessed = 1;
2966	PdeSrc.n.u1User = 1;
2967	# endif
2968
2969	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2970	{
2971	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2972	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
2973	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2974	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2975	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2976	PX86PDPAE pPDDst;
2977	X86PDEPAE PdeDst;
2978	# if PGM_GST_TYPE != PGM_TYPE_PAE
2979	X86PDPE PdpeSrc;
2980
2981	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
2982	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
2983	# endif
2984	int rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
2985	if (rc != VINF_SUCCESS)
2986	{
2987	AssertRC(rc);
2988	return rc;
2989	}
2990	Assert(pPDDst);
2991	PdeDst = pPDDst->a[iPDDst];
2992	# else
2993	const X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
2994	# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
2995
2996	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2997	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2998	PX86PDPAE pPDDst;
2999	X86PDEPAE PdeDst;
3000
3001	# if PGM_GST_TYPE == PGM_TYPE_PROT
3002	/* AMD-V nested paging */
3003	X86PML4E Pml4eSrc;
3004	X86PDPE PdpeSrc;
3005	PX86PML4E pPml4eSrc = &Pml4eSrc;
3006
3007	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3008	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3009	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3010	# endif
3011
3012	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3013	if (rc != VINF_SUCCESS)
3014	{
3015	AssertRC(rc);
3016	return rc;
3017	}
3018	Assert(pPDDst);
3019	PdeDst = pPDDst->a[iPDDst];
3020	# endif
3021	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3022	{
3023	if (!PdeDst.n.u1Present)
3024	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3025	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3026	else
3027	{
3028	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3029	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3030	* makes no sense to prefetch more than one page.
3031	*/
3032	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3033	if (RT_SUCCESS(rc))
3034	rc = VINF_SUCCESS;
3035	}
3036	}
3037	}
3038	return rc;
3039
3040	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3041	return VINF_SUCCESS; /* ignore */
3042	#endif
3043	}
3044
3045
3046
3047
3048	/**
3049	* Syncs a page during a PGMVerifyAccess() call.
3050	*
3051	* @returns VBox status code (informational included).
3052	* @param GCPtrPage The address of the page to sync.
3053	* @param fPage The effective guest page flags.
3054	* @param uErr The trap error code.
3055	*/
3056	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3057	{
3058	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3059
3060	Assert(!HWACCMIsNestedPagingActive(pVM));
3061	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3062	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3063
3064	# ifndef IN_RING0
3065	if (!(fPage & X86_PTE_US))
3066	{
3067	/*
3068	* Mark this page as safe.
3069	*/
3070	/** @todo not correct for pages that contain both code and data!! */
3071	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3072	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3073	}
3074	# endif
3075
3076	/*
3077	* Get guest PD and index.
3078	*/
3079	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3080	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3081	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3082	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3083	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3084	unsigned iPDSrc;
3085	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3086	X86PDPE PdpeSrc;
3087	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3088	# else
3089	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
3090	# endif
3091
3092	if (pPDSrc)
3093	{
3094	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3095	return VINF_EM_RAW_GUEST_TRAP;
3096	}
3097	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3098	unsigned iPDSrc;
3099	PX86PML4E pPml4eSrc;
3100	X86PDPE PdpeSrc;
3101	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3102	if (!pPDSrc)
3103	{
3104	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3105	return VINF_EM_RAW_GUEST_TRAP;
3106	}
3107	# endif
3108	# else
3109	PGSTPD pPDSrc = NULL;
3110	const unsigned iPDSrc = 0;
3111	# endif
3112	int rc = VINF_SUCCESS;
3113
3114	/*
3115	* First check if the shadow pd is present.
3116	*/
3117	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3118	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
3119	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3120	PX86PDEPAE pPdeDst;
3121	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3122	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3123	PX86PDPAE pPDDst;
3124	# if PGM_GST_TYPE != PGM_TYPE_PAE
3125	X86PDPE PdpeSrc;
3126
3127	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3128	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3129	# endif
3130	rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
3131	if (rc != VINF_SUCCESS)
3132	{
3133	AssertRC(rc);
3134	return rc;
3135	}
3136	Assert(pPDDst);
3137	pPdeDst = &pPDDst->a[iPDDst];
3138	# else
3139	pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
3140	# endif
3141	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3142	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3143	PX86PDPAE pPDDst;
3144	PX86PDEPAE pPdeDst;
3145
3146	# if PGM_GST_TYPE == PGM_TYPE_PROT
3147	/* AMD-V nested paging */
3148	X86PML4E Pml4eSrc;
3149	X86PDPE PdpeSrc;
3150	PX86PML4E pPml4eSrc = &Pml4eSrc;
3151
3152	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3153	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3154	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3155	# endif
3156
3157	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3158	if (rc != VINF_SUCCESS)
3159	{
3160	AssertRC(rc);
3161	return rc;
3162	}
3163	Assert(pPDDst);
3164	pPdeDst = &pPDDst->a[iPDDst];
3165	# endif
3166	if (!pPdeDst->n.u1Present)
3167	{
3168	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3169	AssertRC(rc);
3170	if (rc != VINF_SUCCESS)
3171	return rc;
3172	}
3173
3174	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3175	/* Check for dirty bit fault */
3176	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3177	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3178	Log(("PGMVerifyAccess: success (dirty)\n"));
3179	else
3180	{
3181	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3182	#else
3183	{
3184	GSTPDE PdeSrc;
3185	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3186	PdeSrc.n.u1Present = 1;
3187	PdeSrc.n.u1Write = 1;
3188	PdeSrc.n.u1Accessed = 1;
3189	PdeSrc.n.u1User = 1;
3190
3191	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3192	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3193	if (uErr & X86_TRAP_PF_US)
3194	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3195	else /* supervisor */
3196	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3197
3198	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3199	if (RT_SUCCESS(rc))
3200	{
3201	/* Page was successfully synced */
3202	Log2(("PGMVerifyAccess: success (sync)\n"));
3203	rc = VINF_SUCCESS;
3204	}
3205	else
3206	{
3207	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3208	return VINF_EM_RAW_GUEST_TRAP;
3209	}
3210	}
3211	return rc;
3212
3213	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3214
3215	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3216	return VERR_INTERNAL_ERROR;
3217	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3218	}
3219
3220
3221	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3222	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3223	/**
3224	* Figures out which kind of shadow page this guest PDE warrants.
3225	*
3226	* @returns Shadow page kind.
3227	* @param pPdeSrc The guest PDE in question.
3228	* @param cr4 The current guest cr4 value.
3229	*/
3230	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3231	{
3232	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3233	if (!pPdeSrc->n.u1Size)
3234	# else
3235	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3236	# endif
3237	return BTH_PGMPOOLKIND_PT_FOR_PT;
3238	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3239	//{
3240	// case 0:
3241	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3242	// case X86_PDE4M_RW:
3243	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3244	// case X86_PDE4M_US:
3245	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3246	// case X86_PDE4M_RW \| X86_PDE4M_US:
3247	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3248	# if 0
3249	// case X86_PDE4M_PAE_NX:
3250	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3251	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3252	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3253	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3254	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3255	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3256	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3257	# endif
3258	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3259	//}
3260	}
3261	# endif
3262	#endif
3263
3264	#undef MY_STAM_COUNTER_INC
3265	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3266
3267
3268	/**
3269	* Syncs the paging hierarchy starting at CR3.
3270	*
3271	* @returns VBox status code, no specials.
3272	* @param pVM The virtual machine.
3273	* @param cr0 Guest context CR0 register
3274	* @param cr3 Guest context CR3 register
3275	* @param cr4 Guest context CR4 register
3276	* @param fGlobal Including global page directories or not
3277	*/
3278	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3279	{
3280	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3281	fGlobal = true; /* Change this CR3 reload to be a global one. */
3282
3283	LogFlow(("SyncCR3 %d\n", fGlobal));
3284
3285	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3286	/*
3287	* Update page access handlers.
3288	* The virtual are always flushed, while the physical are only on demand.
3289	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3290	* have to look into that later because it will have a bad influence on the performance.
3291	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3292	* bird: Yes, but that won't work for aliases.
3293	*/
3294	/** @todo this MUST go away. See #1557. */
3295	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3296	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3297	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3298	#endif
3299
3300	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3301	/*
3302	* Nested / EPT - almost no work.
3303	*/
3304	/** @todo check if this is really necessary; the call does it as well... */
3305	HWACCMFlushTLB(pVM);
3306	return VINF_SUCCESS;
3307
3308	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3309	/*
3310	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3311	* out the shadow parts when the guest modifies its tables.
3312	*/
3313	return VINF_SUCCESS;
3314
3315	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3316
3317	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3318	# ifdef PGM_WITHOUT_MAPPINGS
3319	Assert(pVM->pgm.s.fMappingsFixed);
3320	return VINF_SUCCESS;
3321	# else
3322	/* Nothing to do when mappings are fixed. */
3323	if (pVM->pgm.s.fMappingsFixed)
3324	return VINF_SUCCESS;
3325
3326	int rc = PGMMapResolveConflicts(pVM);
3327	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3328	if (rc == VINF_PGM_SYNC_CR3)
3329	{
3330	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3331	return VINF_PGM_SYNC_CR3;
3332	}
3333	# endif
3334	return VINF_SUCCESS;
3335	# else
3336	/*
3337	* PAE and 32-bit legacy mode (shadow).
3338	* (Guest PAE, 32-bit legacy, protected and real modes.)
3339	*/
3340	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3341	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3342
3343	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3344	bool const fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3345
3346	/*
3347	* Get page directory addresses.
3348	*/
3349	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3350	PX86PDE pPDEDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, 0);
3351	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
3352	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3353	PX86PDEPAE pPDEDst = NULL;
3354	# endif
3355	# endif
3356
3357	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3358	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3359	Assert(pPDSrc);
3360	# if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3361	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == (RTR3PTR)pPDSrc);
3362	# endif
3363	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3364
3365	/*
3366	* Iterate the the CR3 page.
3367	*/
3368	PPGMMAPPING pMapping;
3369	unsigned iPdNoMapping;
3370	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3371	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3372
3373	/* Only check mappings if they are supposed to be put into the shadow page table. */
3374	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3375	{
3376	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3377	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3378	}
3379	else
3380	{
3381	pMapping = 0;
3382	iPdNoMapping = ~0U;
3383	}
3384
3385	# if PGM_GST_TYPE == PGM_TYPE_PAE
3386	for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
3387	{
3388	unsigned iPDSrc;
3389	X86PDPE PdpeSrc;
3390	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3391	PX86PDEPAE pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT);
3392	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3393
3394	if (pPDSrc == NULL)
3395	{
3396	/* PDPE not present */
3397	if (pPdptDst->a[iPdpt].n.u1Present)
3398	{
3399	LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
3400	/* for each page directory entry */
3401	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3402	{
3403	if ( pPDEDst[iPD].n.u1Present
3404	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3405	{
3406	pgmPoolFree(pVM, pPDEDst[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
3407	pPDEDst[iPD].u = 0;
3408	}
3409	}
3410	}
3411	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
3412	pPdptDst->a[iPdpt].n.u1Present = 0;
3413	continue;
3414	}
3415	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3416	{
3417	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3418	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3419	{
3420	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3421	if ((iPD & 255) == 0) /* Start of new PD. */
3422	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)iPD << GST_PD_SHIFT);
3423	# endif
3424	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3425	Assert(pgmShwGet32BitPDEPtr(&pVM->pgm.s, (uint32_t)iPD << SHW_PD_SHIFT) == pPDEDst);
3426	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3427	# if defined(VBOX_STRICT) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* Unfortuantely not reliable with PGMR0DynMap and multiple VMs. */
3428	RTGCPTR GCPtrStrict = (uint32_t)iPD << GST_PD_SHIFT;
3429	# if PGM_GST_TYPE == PGM_TYPE_PAE
3430	GCPtrStrict \|= iPdpt << X86_PDPT_SHIFT;
3431	# endif
3432	AssertMsg(pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict) == pPDEDst, ("%p vs %p (%RGv)\n", pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict), pPDEDst, GCPtrStrict));
3433	# endif /* VBOX_STRICT */
3434	# endif
3435	GSTPDE PdeSrc = pPDSrc->a[iPD];
3436	if ( PdeSrc.n.u1Present
3437	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3438	{
3439	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3440	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3441	&& !defined(PGM_WITHOUT_MAPPINGS)
3442
3443	/*
3444	* Check for conflicts with GC mappings.
3445	*/
3446	# if PGM_GST_TYPE == PGM_TYPE_PAE
3447	if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
3448	# else
3449	if (iPD == iPdNoMapping)
3450	# endif
3451	{
3452	if (pVM->pgm.s.fMappingsFixed)
3453	{
3454	/* It's fixed, just skip the mapping. */
3455	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3456	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3457	iPD += cPTs - 1;
3458	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3459	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3460	# else
3461	pPDEDst += cPTs;
3462	# endif
3463	pMapping = pMapping->CTX_SUFF(pNext);
3464	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3465	continue;
3466	}
3467	# ifdef IN_RING3
3468	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3469	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3470	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3471	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3472	# endif
3473	if (RT_FAILURE(rc))
3474	return rc;
3475
3476	/*
3477	* Update iPdNoMapping and pMapping.
3478	*/
3479	pMapping = pVM->pgm.s.pMappingsR3;
3480	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3481	pMapping = pMapping->pNextR3;
3482	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3483	# else /* !IN_RING3 */
3484	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3485	return VINF_PGM_SYNC_CR3;
3486	# endif /* !IN_RING3 */
3487	}
3488	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3489	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3490	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3491
3492	/*
3493	* Sync page directory entry.
3494	*
3495	* The current approach is to allocated the page table but to set
3496	* the entry to not-present and postpone the page table synching till
3497	* it's actually used.
3498	*/
3499	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3500	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3501	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3502	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3503	# else
3504	const unsigned iPdShw = iPD; NOREF(iPdShw);
3505	# endif
3506	{
3507	SHWPDE PdeDst = *pPDEDst;
3508	if (PdeDst.n.u1Present)
3509	{
3510	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3511	RTGCPHYS GCPhys;
3512	if ( !PdeSrc.b.u1Size
3513	\|\| !fBigPagesSupported)
3514	{
3515	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3516	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3517	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3518	GCPhys \|= i * (PAGE_SIZE / 2);
3519	# endif
3520	}
3521	else
3522	{
3523	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3524	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3525	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3526	GCPhys \|= i * X86_PAGE_2M_SIZE;
3527	# endif
3528	}
3529
3530	if ( pShwPage->GCPhys == GCPhys
3531	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3532	&& ( pShwPage->fCached
3533	\|\| ( !fGlobal
3534	&& ( false
3535	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3536	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3537	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3538	\|\| ( !pShwPage->fSeenNonGlobal
3539	&& (cr4 & X86_CR4_PGE))
3540	# endif
3541	)
3542	)
3543	)
3544	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3545	\|\| ( fBigPagesSupported
3546	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3547	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3548	)
3549	)
3550	{
3551	# ifdef VBOX_WITH_STATISTICS
3552	if ( !fGlobal
3553	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3554	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3555	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3556	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3557	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3558	else
3559	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3560	# endif /* VBOX_WITH_STATISTICS */
3561	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3562	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3563	//# ifdef PGMPOOL_WITH_CACHE
3564	// pgmPoolCacheUsed(pPool, pShwPage);
3565	//# endif
3566	}
3567	else
3568	{
3569	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3570	pPDEDst->u = 0;
3571	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3572	}
3573	}
3574	else
3575	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3576
3577	/* advance */
3578	pPDEDst++;
3579	} /* foreach 2MB PAE PDE in 4MB guest PDE */
3580	}
3581	# if PGM_GST_TYPE == PGM_TYPE_PAE
3582	else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
3583	# else
3584	else if (iPD != iPdNoMapping)
3585	# endif
3586	{
3587	/*
3588	* Check if there is any page directory to mark not present here.
3589	*/
3590	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3591	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3592	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3593	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES;
3594	# else
3595	const unsigned iPdShw = iPD;
3596	# endif
3597	{
3598	if (pPDEDst->n.u1Present)
3599	{
3600	pgmPoolFree(pVM, pPDEDst->u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdShw);
3601	pPDEDst->u = 0;
3602	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3603	}
3604	pPDEDst++;
3605	}
3606	}
3607	else
3608	{
3609	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3610	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3611	&& !defined(PGM_WITHOUT_MAPPINGS)
3612
3613	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3614
3615	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3616	if (pVM->pgm.s.fMappingsFixed)
3617	{
3618	/* It's fixed, just skip the mapping. */
3619	pMapping = pMapping->CTX_SUFF(pNext);
3620	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3621	}
3622	else
3623	{
3624	/*
3625	* Check for conflicts for subsequent pagetables
3626	* and advance to the next mapping.
3627	*/
3628	iPdNoMapping = ~0U;
3629	unsigned iPT = cPTs;
3630	while (iPT-- > 1)
3631	{
3632	if ( pPDSrc->a[iPD + iPT].n.u1Present
3633	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3634	{
3635	# ifdef IN_RING3
3636	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3637	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3638	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3639	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3640	# endif
3641	if (RT_FAILURE(rc))
3642	return rc;
3643
3644	/*
3645	* Update iPdNoMapping and pMapping.
3646	*/
3647	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3648	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3649	pMapping = pMapping->CTX_SUFF(pNext);
3650	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3651	break;
3652	# else
3653	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3654	return VINF_PGM_SYNC_CR3;
3655	# endif
3656	}
3657	}
3658	if (iPdNoMapping == ~0U && pMapping)
3659	{
3660	pMapping = pMapping->CTX_SUFF(pNext);
3661	if (pMapping)
3662	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3663	}
3664	}
3665
3666	/* advance. */
3667	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3668	iPD += cPTs - 1;
3669	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3670	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3671	# else
3672	pPDEDst += cPTs;
3673	# endif
3674	# if PGM_GST_TYPE != PGM_SHW_TYPE
3675	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3676	# endif
3677	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3678	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3679	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3680	}
3681
3682	} /* for iPD */
3683	} /* for each PDPTE (PAE) */
3684	return VINF_SUCCESS;
3685
3686	# else /* guest real and protected mode */
3687	return VINF_SUCCESS;
3688	# endif
3689	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
3690	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3691	}
3692
3693
3694
3695
3696	#ifdef VBOX_STRICT
3697	#ifdef IN_RC
3698	# undef AssertMsgFailed
3699	# define AssertMsgFailed Log
3700	#endif
3701	#ifdef IN_RING3
3702	# include <VBox/dbgf.h>
3703
3704	/**
3705	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3706	*
3707	* @returns VBox status code (VINF_SUCCESS).
3708	* @param pVM The VM handle.
3709	* @param cr3 The root of the hierarchy.
3710	* @param crr The cr4, only PAE and PSE is currently used.
3711	* @param fLongMode Set if long mode, false if not long mode.
3712	* @param cMaxDepth Number of levels to dump.
3713	* @param pHlp Pointer to the output functions.
3714	*/
3715	__BEGIN_DECLS
3716	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3717	__END_DECLS
3718
3719	#endif
3720
3721	/**
3722	* Checks that the shadow page table is in sync with the guest one.
3723	*
3724	* @returns The number of errors.
3725	* @param pVM The virtual machine.
3726	* @param cr3 Guest context CR3 register
3727	* @param cr4 Guest context CR4 register
3728	* @param GCPtr Where to start. Defaults to 0.
3729	* @param cb How much to check. Defaults to everything.
3730	*/
3731	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3732	{
3733	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3734	return 0;
3735	#else
3736	unsigned cErrors = 0;
3737
3738	#if PGM_GST_TYPE == PGM_TYPE_PAE
3739	/** @todo currently broken; crashes below somewhere */
3740	AssertFailed();
3741	#endif
3742
3743	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3744	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3745	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3746
3747	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3748	bool fBigPagesSupported = true;
3749	# else
3750	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3751	# endif
3752	PPGM pPGM = &pVM->pgm.s;
3753	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3754	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3755	# ifndef IN_RING0
3756	RTHCPHYS HCPhys; /* general usage. */
3757	# endif
3758	int rc;
3759
3760	/*
3761	* Check that the Guest CR3 and all its mappings are correct.
3762	*/
3763	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3764	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3765	false);
3766	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3767	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3768	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3769	# else
3770	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3771	# endif
3772	AssertRCReturn(rc, 1);
3773	HCPhys = NIL_RTHCPHYS;
3774	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3775	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3776	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3777	RTGCPHYS GCPhys;
3778	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3779	AssertRCReturn(rc, 1);
3780	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3781	# endif
3782	# endif /* !IN_RING0 */
3783
3784	/*
3785	* Get and check the Shadow CR3.
3786	*/
3787	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3788	unsigned cPDEs = X86_PG_ENTRIES;
3789	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3790	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3791	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3792	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3793	# else
3794	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3795	# endif
3796	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3797	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3798	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3799	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3800	# endif
3801	if (cb != ~(RTGCPTR)0)
3802	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3803
3804	/** @todo call the other two PGMAssert() functions. /
3805
3806	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3807	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3808	# endif
3809
3810	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3811	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3812
3813	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3814	{
3815	PPGMPOOLPAGE pShwPdpt = NULL;
3816	PX86PML4E pPml4eSrc;
3817	PX86PML4E pPml4eDst;
3818	RTGCPHYS GCPhysPdptSrc;
3819
3820	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3821	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3822
3823	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3824	if (!pPml4eDst->n.u1Present)
3825	{
3826	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3827	continue;
3828	}
3829
3830	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3831	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3832
3833	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3834	{
3835	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3836	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3837	cErrors++;
3838	continue;
3839	}
3840
3841	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3842	{
3843	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3844	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3845	cErrors++;
3846	continue;
3847	}
3848
3849	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3850	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3851	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3852	{
3853	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3854	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3855	cErrors++;
3856	continue;
3857	}
3858	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3859	{
3860	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3861
3862	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3863	/*
3864	* Check the PDPTEs too.
3865	*/
3866	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3867
3868	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3869	{
3870	unsigned iPDSrc;
3871	PPGMPOOLPAGE pShwPde = NULL;
3872	PX86PDPE pPdpeDst;
3873	RTGCPHYS GCPhysPdeSrc;
3874	# if PGM_GST_TYPE == PGM_TYPE_PAE
3875	X86PDPE PdpeSrc;
3876	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3877	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3878	# else
3879	PX86PML4E pPml4eSrc;
3880	X86PDPE PdpeSrc;
3881	PX86PDPT pPdptDst;
3882	PX86PDPAE pPDDst;
3883	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3884
3885	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3886	if (rc != VINF_SUCCESS)
3887	{
3888	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3889	GCPtr += 512 * _2M;
3890	continue; /* next PDPTE */
3891	}
3892	Assert(pPDDst);
3893	# endif
3894	Assert(iPDSrc == 0);
3895
3896	pPdpeDst = &pPdptDst->a[iPdpt];
3897
3898	if (!pPdpeDst->n.u1Present)
3899	{
3900	GCPtr += 512 * _2M;
3901	continue; /* next PDPTE */
3902	}
3903
3904	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3905	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3906
3907	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3908	{
3909	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3910	GCPtr += 512 * _2M;
3911	cErrors++;
3912	continue;
3913	}
3914
3915	if (GCPhysPdeSrc != pShwPde->GCPhys)
3916	{
3917	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3918	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3919	# else
3920	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3921	# endif
3922	GCPtr += 512 * _2M;
3923	cErrors++;
3924	continue;
3925	}
3926
3927	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3928	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3929	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3930	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3931	{
3932	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3933	GCPtr += 512 * _2M;
3934	cErrors++;
3935	continue;
3936	}
3937	# endif
3938
3939	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3940	{
3941	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3942	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3943	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3944	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3945	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
3946	# endif
3947	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3948	/*
3949	* Iterate the shadow page directory.
3950	*/
3951	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3952	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3953
3954	for (;
3955	iPDDst < cPDEs;
3956	iPDDst++, GCPtr += cIncrement)
3957	{
3958	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3959	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3960	# else
3961	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3962	# endif
3963	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3964	{
3965	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3966	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3967	{
3968	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3969	cErrors++;
3970	continue;
3971	}
3972	}
3973	else if ( (PdeDst.u & X86_PDE_P)
3974	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3975	)
3976	{
3977	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3978	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3979	if (!pPoolPage)
3980	{
3981	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3982	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3983	cErrors++;
3984	continue;
3985	}
3986	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3987
3988	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3989	{
3990	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3991	GCPtr, (uint64_t)PdeDst.u));
3992	cErrors++;
3993	}
3994
3995	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3996	{
3997	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3998	GCPtr, (uint64_t)PdeDst.u));
3999	cErrors++;
4000	}
4001
4002	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4003	if (!PdeSrc.n.u1Present)
4004	{
4005	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4006	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4007	cErrors++;
4008	continue;
4009	}
4010
4011	if ( !PdeSrc.b.u1Size
4012	\|\| !fBigPagesSupported)
4013	{
4014	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
4015	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4016	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
4017	# endif
4018	}
4019	else
4020	{
4021	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4022	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4023	{
4024	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4025	GCPtr, (uint64_t)PdeSrc.u));
4026	cErrors++;
4027	continue;
4028	}
4029	# endif
4030	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
4031	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4032	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
4033	# endif
4034	}
4035
4036	if ( pPoolPage->enmKind
4037	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4038	{
4039	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4040	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4041	cErrors++;
4042	}
4043
4044	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4045	if (!pPhysPage)
4046	{
4047	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4048	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4049	cErrors++;
4050	continue;
4051	}
4052
4053	if (GCPhysGst != pPoolPage->GCPhys)
4054	{
4055	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4056	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4057	cErrors++;
4058	continue;
4059	}
4060
4061	if ( !PdeSrc.b.u1Size
4062	\|\| !fBigPagesSupported)
4063	{
4064	/*
4065	* Page Table.
4066	*/
4067	const GSTPT *pPTSrc;
4068	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
4069	if (RT_FAILURE(rc))
4070	{
4071	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4072	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4073	cErrors++;
4074	continue;
4075	}
4076	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4077	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4078	{
4079	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4080	// (This problem will go away when/if we shadow multiple CR3s.)
4081	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4082	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4083	cErrors++;
4084	continue;
4085	}
4086	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4087	{
4088	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4089	GCPtr, (uint64_t)PdeDst.u));
4090	cErrors++;
4091	continue;
4092	}
4093
4094	/* iterate the page table. */
4095	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4096	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4097	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4098	# else
4099	const unsigned offPTSrc = 0;
4100	# endif
4101	for (unsigned iPT = 0, off = 0;
4102	iPT < RT_ELEMENTS(pPTDst->a);
4103	iPT++, off += PAGE_SIZE)
4104	{
4105	const SHWPTE PteDst = pPTDst->a[iPT];
4106
4107	/* skip not-present entries. */
4108	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4109	continue;
4110	Assert(PteDst.n.u1Present);
4111
4112	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4113	if (!PteSrc.n.u1Present)
4114	{
4115	# ifdef IN_RING3
4116	PGMAssertHandlerAndFlagsInSync(pVM);
4117	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4118	# endif
4119	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4120	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4121	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4122	cErrors++;
4123	continue;
4124	}
4125
4126	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4127	# if 1 /** @todo sync accessed bit properly... */
4128	fIgnoreFlags \|= X86_PTE_A;
4129	# endif
4130
4131	/* match the physical addresses */
4132	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4133	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4134
4135	# ifdef IN_RING3
4136	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4137	if (RT_FAILURE(rc))
4138	{
4139	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4140	{
4141	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4142	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4143	cErrors++;
4144	continue;
4145	}
4146	}
4147	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4148	{
4149	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4150	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4151	cErrors++;
4152	continue;
4153	}
4154	# endif
4155
4156	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4157	if (!pPhysPage)
4158	{
4159	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4160	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4161	{
4162	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4163	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4164	cErrors++;
4165	continue;
4166	}
4167	# endif
4168	if (PteDst.n.u1Write)
4169	{
4170	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4171	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4172	cErrors++;
4173	}
4174	fIgnoreFlags \|= X86_PTE_RW;
4175	}
4176	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
4177	{
4178	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4179	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4180	cErrors++;
4181	continue;
4182	}
4183
4184	/* flags */
4185	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4186	{
4187	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4188	{
4189	if (PteDst.n.u1Write)
4190	{
4191	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4192	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4193	cErrors++;
4194	continue;
4195	}
4196	fIgnoreFlags \|= X86_PTE_RW;
4197	}
4198	else
4199	{
4200	if (PteDst.n.u1Present)
4201	{
4202	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PteSrc=%#RX64 PteDst=%#RX64\n",
4203	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4204	cErrors++;
4205	continue;
4206	}
4207	fIgnoreFlags \|= X86_PTE_P;
4208	}
4209	}
4210	else
4211	{
4212	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4213	{
4214	if (PteDst.n.u1Write)
4215	{
4216	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4217	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4218	cErrors++;
4219	continue;
4220	}
4221	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4222	{
4223	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4224	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4225	cErrors++;
4226	continue;
4227	}
4228	if (PteDst.n.u1Dirty)
4229	{
4230	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4232	cErrors++;
4233	}
4234	# if 0 /** @todo sync access bit properly... */
4235	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4236	{
4237	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4238	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4239	cErrors++;
4240	}
4241	fIgnoreFlags \|= X86_PTE_RW;
4242	# else
4243	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4244	# endif
4245	}
4246	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4247	{
4248	/* access bit emulation (not implemented). */
4249	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4250	{
4251	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4252	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4253	cErrors++;
4254	continue;
4255	}
4256	if (!PteDst.n.u1Accessed)
4257	{
4258	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4259	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4260	cErrors++;
4261	}
4262	fIgnoreFlags \|= X86_PTE_P;
4263	}
4264	# ifdef DEBUG_sandervl
4265	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4266	# endif
4267	}
4268
4269	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4270	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4271	)
4272	{
4273	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4274	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4275	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4276	cErrors++;
4277	continue;
4278	}
4279	} /* foreach PTE */
4280	}
4281	else
4282	{
4283	/*
4284	* Big Page.
4285	*/
4286	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4287	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4288	{
4289	if (PdeDst.n.u1Write)
4290	{
4291	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4292	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4293	cErrors++;
4294	continue;
4295	}
4296	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4297	{
4298	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4299	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4300	cErrors++;
4301	continue;
4302	}
4303	# if 0 /** @todo sync access bit properly... */
4304	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4305	{
4306	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4307	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4308	cErrors++;
4309	}
4310	fIgnoreFlags \|= X86_PTE_RW;
4311	# else
4312	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4313	# endif
4314	}
4315	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4316	{
4317	/* access bit emulation (not implemented). */
4318	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4319	{
4320	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4321	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4322	cErrors++;
4323	continue;
4324	}
4325	if (!PdeDst.n.u1Accessed)
4326	{
4327	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4328	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4329	cErrors++;
4330	}
4331	fIgnoreFlags \|= X86_PTE_P;
4332	}
4333
4334	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4335	{
4336	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4337	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4338	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4339	cErrors++;
4340	}
4341
4342	/* iterate the page table. */
4343	for (unsigned iPT = 0, off = 0;
4344	iPT < RT_ELEMENTS(pPTDst->a);
4345	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4346	{
4347	const SHWPTE PteDst = pPTDst->a[iPT];
4348
4349	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4350	{
4351	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4352	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4353	cErrors++;
4354	}
4355
4356	/* skip not-present entries. */
4357	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4358	continue;
4359
4360	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4361
4362	/* match the physical addresses */
4363	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4364
4365	# ifdef IN_RING3
4366	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4367	if (RT_FAILURE(rc))
4368	{
4369	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4370	{
4371	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4372	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4373	cErrors++;
4374	}
4375	}
4376	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4377	{
4378	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4379	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4380	cErrors++;
4381	continue;
4382	}
4383	# endif
4384	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4385	if (!pPhysPage)
4386	{
4387	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4388	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4389	{
4390	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4391	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4392	cErrors++;
4393	continue;
4394	}
4395	# endif
4396	if (PteDst.n.u1Write)
4397	{
4398	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4399	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4400	cErrors++;
4401	}
4402	fIgnoreFlags \|= X86_PTE_RW;
4403	}
4404	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
4405	{
4406	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4407	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4408	cErrors++;
4409	continue;
4410	}
4411
4412	/* flags */
4413	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4414	{
4415	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4416	{
4417	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4418	{
4419	if (PteDst.n.u1Write)
4420	{
4421	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4422	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4423	cErrors++;
4424	continue;
4425	}
4426	fIgnoreFlags \|= X86_PTE_RW;
4427	}
4428	}
4429	else
4430	{
4431	if (PteDst.n.u1Present)
4432	{
4433	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! HCPhys=%RHp PdeSrc=%#RX64 PteDst=%#RX64\n",
4434	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4435	cErrors++;
4436	continue;
4437	}
4438	fIgnoreFlags \|= X86_PTE_P;
4439	}
4440	}
4441
4442	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4443	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4444	)
4445	{
4446	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4447	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4448	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4449	cErrors++;
4450	continue;
4451	}
4452	} /* for each PTE */
4453	}
4454	}
4455	/* not present */
4456
4457	} /* for each PDE */
4458
4459	} /* for each PDPTE */
4460
4461	} /* for each PML4E */
4462
4463	# ifdef DEBUG
4464	if (cErrors)
4465	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4466	# endif
4467
4468	#endif /* GST == 32BIT, PAE or AMD64 */
4469	return cErrors;
4470
4471	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4472	}
4473	#endif /* VBOX_STRICT */
4474
4475
4476	/**
4477	* Sets up the CR3 for shadow paging
4478	*
4479	* @returns Strict VBox status code.
4480	* @retval VINF_SUCCESS.
4481	*
4482	* @param pVM VM handle.
4483	* @param GCPhysCR3 The physical address in the CR3 register.
4484	*/
4485	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
4486	{
4487	/* Update guest paging info. */
4488	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4489	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4490	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4491
4492	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4493
4494	/*
4495	* Map the page CR3 points at.
4496	*/
4497	RTHCPHYS HCPhysGuestCR3;
4498	RTHCPTR HCPtrGuestCR3;
4499	int rc = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
4500	if (RT_SUCCESS(rc))
4501	{
4502	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4503	if (RT_SUCCESS(rc))
4504	{
4505	# ifdef IN_RC
4506	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4507	# endif
4508	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4509	pVM->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4510	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4511	pVM->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4512	# endif
4513	pVM->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4514
4515	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4516	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4517	pVM->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4518	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4519	pVM->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4520	# endif
4521	pVM->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4522	Log(("Cached mapping %RRv\n", pVM->pgm.s.pGstPaePdptRC));
4523
4524	/*
4525	* Map the 4 PDs too.
4526	*/
4527	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
4528	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4529	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4530	{
4531	if (pGuestPDPT->a[i].n.u1Present)
4532	{
4533	RTHCPTR HCPtr;
4534	RTHCPHYS HCPhys;
4535	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4536	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
4537	if (RT_SUCCESS(rc2))
4538	{
4539	rc = PGMMap(pVM, GCPtr, HCPhys & X86_PTE_PAE_PG_MASK, PAGE_SIZE, 0);
4540	AssertRCReturn(rc, rc);
4541
4542	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4543	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4544	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4545	# endif
4546	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4547	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4548	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
4549	continue;
4550	}
4551	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4552	}
4553
4554	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4555	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4556	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4557	# endif
4558	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4559	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4560	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4561	}
4562
4563	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4564	pVM->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4565	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4566	pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4567	# endif
4568	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
4569	if (!HWACCMIsNestedPagingActive(pVM))
4570	{
4571	/*
4572	* Update the shadow root page as well since that's not fixed.
4573	*/
4574	/** @todo Move this into PGMAllBth.h. */
4575	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4576	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4577	{
4578	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
4579	/** @todo Coordinate this better with the pool. */
4580	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
4581	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
4582	pVM->pgm.s.pShwPageCR3R3 = 0;
4583	pVM->pgm.s.pShwPageCR3R0 = 0;
4584	pVM->pgm.s.pShwRootR3 = 0;
4585	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4586	pVM->pgm.s.pShwRootR0 = 0;
4587	# endif
4588	pVM->pgm.s.HCPhysShwCR3 = 0;
4589	}
4590
4591	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4592	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4593	if (rc == VERR_PGM_POOL_FLUSHED)
4594	{
4595	Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
4596	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4597	return VINF_PGM_SYNC_CR3;
4598	}
4599	AssertRCReturn(rc, rc);
4600	# ifdef IN_RING0
4601	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4602	# else
4603	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4604	# endif
4605	pVM->pgm.s.pShwRootR3 = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
4606	Assert(pVM->pgm.s.pShwRootR3);
4607	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4608	pVM->pgm.s.pShwRootR0 = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4609	# endif
4610	pVM->pgm.s.HCPhysShwCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
4611	rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
4612	}
4613	# endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
4614	# endif
4615	}
4616	else
4617	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4618	}
4619	else
4620	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4621
4622	#else /* prot/real stub */
4623	int rc = VINF_SUCCESS;
4624	#endif
4625
4626	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4627	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4628	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4629	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4630	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4631	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4632	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4633
4634	Assert(!HWACCMIsNestedPagingActive(pVM));
4635
4636	/*
4637	* Update the shadow root page as well since that's not fixed.
4638	*/
4639	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4640	PPGMPOOLPAGE pOldShwPageCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
4641	uint32_t iOldShwUserTable = pVM->pgm.s.iShwUserTable;
4642	uint32_t iOldShwUser = pVM->pgm.s.iShwUser;
4643	PPGMPOOLPAGE pNewShwPageCR3;
4644
4645	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4646	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4647	if (rc == VERR_PGM_POOL_FLUSHED)
4648	{
4649	Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
4650	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4651	return VINF_PGM_SYNC_CR3;
4652	}
4653	AssertRCReturn(rc, rc);
4654	rc = VINF_SUCCESS;
4655
4656	# ifdef IN_RC
4657	/** NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4658	VMMGCLogDisable(pVM);
4659	# endif
4660	/* Mark the page as locked; disallow flushing. */
4661	pgmPoolLockPage(pPool, pNewShwPageCR3);
4662
4663	pVM->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4664	pVM->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4665	pVM->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4666	# ifdef IN_RING0
4667	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4668	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4669	# elif defined(IN_RC)
4670	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4671	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4672	# else
4673	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4674	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4675	# endif
4676	pVM->pgm.s.pShwRootR3 = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
4677	Assert(pVM->pgm.s.pShwRootR3);
4678	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4679	pVM->pgm.s.pShwRootR0 = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4680	# endif
4681	pVM->pgm.s.HCPhysShwCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
4682
4683	# ifndef PGM_WITHOUT_MAPPINGS
4684	/* Apply all hypervisor mappings to the new CR3.
4685	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4686	* make sure we check for conflicts in the new CR3 root.
4687	*/
4688	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4689	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL));
4690	# endif
4691	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4692	AssertRCReturn(rc, rc);
4693	# endif
4694
4695	/* Set the current hypervisor CR3. */
4696	CPUMSetHyperCR3(pVM, PGMGetHyperCR3(pVM));
4697
4698	# ifdef IN_RC
4699	VMMGCLogEnable(pVM);
4700	# endif
4701
4702	/* Clean up the old CR3 root. */
4703	if (pOldShwPageCR3)
4704	{
4705	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4706	# ifndef PGM_WITHOUT_MAPPINGS
4707	/* Remove the hypervisor mappings from the shadow page table. */
4708	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4709	# endif
4710	/* Mark the page as unlocked; allow flushing again. */
4711	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4712
4713	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4714	}
4715
4716	# endif
4717	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4718
4719	return rc;
4720	}
4721
4722	/**
4723	* Unmaps the shadow CR3.
4724	*
4725	* @returns VBox status, no specials.
4726	* @param pVM VM handle.
4727	*/
4728	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM)
4729	{
4730	LogFlow(("UnmapCR3\n"));
4731
4732	int rc = VINF_SUCCESS;
4733
4734	/* Update guest paging info. */
4735	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4736	pVM->pgm.s.pGst32BitPdR3 = 0;
4737	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4738	pVM->pgm.s.pGst32BitPdR0 = 0;
4739	#endif
4740	pVM->pgm.s.pGst32BitPdRC = 0;
4741
4742	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4743	pVM->pgm.s.pGstPaePdptR3 = 0;
4744	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4745	pVM->pgm.s.pGstPaePdptR0 = 0;
4746	# endif
4747	pVM->pgm.s.pGstPaePdptRC = 0;
4748	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4749	{
4750	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4751	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4752	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4753	# endif
4754	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4755	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4756	}
4757
4758	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4759	pVM->pgm.s.pGstAmd64Pml4R3 = 0;
4760	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4761	pVM->pgm.s.pGstAmd64Pml4R0 = 0;
4762	# endif
4763	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
4764	if (!HWACCMIsNestedPagingActive(pVM))
4765	{
4766	pVM->pgm.s.pShwRootR3 = 0;
4767	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4768	pVM->pgm.s.pShwRootR0 = 0;
4769	# endif
4770	pVM->pgm.s.HCPhysShwCR3 = 0;
4771	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4772	{
4773	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4774	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
4775	pVM->pgm.s.pShwPageCR3R3 = 0;
4776	pVM->pgm.s.pShwPageCR3R0 = 0;
4777	}
4778	}
4779	# endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
4780
4781	#else /* prot/real mode stub */
4782	/* nothing to do */
4783	#endif
4784
4785	#if defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4786	/* Update shadow paging info. */
4787	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4788	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4789	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4790
4791	# if PGM_GST_TYPE != PGM_TYPE_REAL
4792	Assert(!HWACCMIsNestedPagingActive(pVM));
4793	# endif
4794
4795	# ifndef PGM_WITHOUT_MAPPINGS
4796	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4797	/* Remove the hypervisor mappings from the shadow page table. */
4798	pgmMapDeactivateCR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4799	# endif
4800
4801	pVM->pgm.s.pShwRootR3 = 0;
4802	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4803	pVM->pgm.s.pShwRootR0 = 0;
4804	# endif
4805	pVM->pgm.s.HCPhysShwCR3 = 0;
4806	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4807	{
4808	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4809
4810	/* Mark the page as unlocked; allow flushing again. */
4811	pgmPoolUnlockPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4812
4813	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.iShwUser, pVM->pgm.s.iShwUserTable);
4814	pVM->pgm.s.pShwPageCR3R3 = 0;
4815	pVM->pgm.s.pShwPageCR3R0 = 0;
4816	pVM->pgm.s.iShwUser = 0;
4817	pVM->pgm.s.iShwUserTable = 0;
4818	}
4819	# endif
4820	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY && !IN_RC*/
4821
4822	return rc;
4823	}
4824

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 17285

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