PGMAllBth.h@ 17486

Last change on this file since 17486 was 17486, checked in by vboxsync, 16 years ago
Updates
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 211.4 KB

Line
1	/* $Id: PGMAllBth.h 17486 2009-03-06 16:14:24Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	* @param pVM VM Handle.
78	* @param uErr The trap error code.
79	* @param pRegFrame Trap register frame.
80	* @param pvFault The fault address.
81	*/
82	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
83	{
84	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && defined(VBOX_STRICT)
85	PGMDynCheckLocks(pVM);
86	# endif
87
88	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
89	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
90	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
91
92	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
93	/*
94	* Hide the instruction fetch trap indicator for now.
95	*/
96	/** @todo NXE will change this and we must fix NXE in the switcher too! */
97	if (uErr & X86_TRAP_PF_ID)
98	{
99	uErr &= ~X86_TRAP_PF_ID;
100	TRPMSetErrorCode(pVM, uErr);
101	}
102	# endif
103
104	/*
105	* Get PDs.
106	*/
107	int rc;
108	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
109	# if PGM_GST_TYPE == PGM_TYPE_32BIT
110	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
111	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
112
113	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
114
115	# if PGM_GST_TYPE == PGM_TYPE_PAE
116	unsigned iPDSrc;
117	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120	# else
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, NULL);
122	# endif
123
124	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
125	unsigned iPDSrc;
126	PX86PML4E pPml4eSrc;
127	X86PDPE PdpeSrc;
128	PGSTPD pPDSrc;
129
130	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
131	Assert(pPml4eSrc);
132	# endif
133
134	/* Quick check for a valid guest trap. (PAE & AMD64) */
135	if (!pPDSrc)
136	{
137	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
138	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
139	# else
140	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
141	# endif
142	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
143	TRPMSetErrorCode(pVM, uErr);
144	return VINF_EM_RAW_GUEST_TRAP;
145	}
146	# endif
147
148	# else /* !PGM_WITH_PAGING */
149	PGSTPD pPDSrc = NULL;
150	const unsigned iPDSrc = 0;
151	# endif /* !PGM_WITH_PAGING */
152
153
154	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
155	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
156	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
157
158	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
159	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
160
161	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
162	PX86PDPAE pPDDst;
163	# if PGM_GST_TYPE != PGM_TYPE_PAE
164	X86PDPE PdpeSrc;
165
166	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
167	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
168	# endif
169	rc = pgmShwSyncPaePDPtr(pVM, pvFault, &PdpeSrc, &pPDDst);
170	if (rc != VINF_SUCCESS)
171	{
172	AssertRC(rc);
173	return rc;
174	}
175	Assert(pPDDst);
176
177	# else
178	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, pvFault);
179
180	/* Did we mark the PDPT as not present in SyncCR3? */
181	unsigned iPdpt = (pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
182	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
183	if (!pPdptDst->a[iPdpt].n.u1Present)
184	pPdptDst->a[iPdpt].n.u1Present = 1;
185	# endif
186
187	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
188	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
189	PX86PDPAE pPDDst;
190	# if PGM_GST_TYPE == PGM_TYPE_PROT
191	/* AMD-V nested paging */
192	X86PML4E Pml4eSrc;
193	X86PDPE PdpeSrc;
194	PX86PML4E pPml4eSrc = &Pml4eSrc;
195
196	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
197	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
198	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
199	# endif
200
201	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
202	if (rc != VINF_SUCCESS)
203	{
204	AssertRC(rc);
205	return rc;
206	}
207	Assert(pPDDst);
208
209	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
210	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
211	PEPTPD pPDDst;
212
213	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
214	if (rc != VINF_SUCCESS)
215	{
216	AssertRC(rc);
217	return rc;
218	}
219	Assert(pPDDst);
220	# endif
221
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	/*
224	* If we successfully correct the write protection fault due to dirty bit
225	* tracking, or this page fault is a genuine one, then return immediately.
226	*/
227	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
228	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
229	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
230	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
231	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
232	{
233	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
234	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
235	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
236	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
237	}
238
239	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
240	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
241
242	/*
243	* A common case is the not-present error caused by lazy page table syncing.
244	*
245	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
246	* so we can safely assume that the shadow PT is present when calling SyncPage later.
247	*
248	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
249	* of mapping conflict and defer to SyncCR3 in R3.
250	* (Again, we do NOT support access handlers for non-present guest pages.)
251	*
252	*/
253	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
254	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
255	# else
256	GSTPDE PdeSrc;
257	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
258	PdeSrc.n.u1Present = 1;
259	PdeSrc.n.u1Write = 1;
260	PdeSrc.n.u1Accessed = 1;
261	PdeSrc.n.u1User = 1;
262	# endif
263	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
264	&& !pPDDst->a[iPDDst].n.u1Present
265	&& PdeSrc.n.u1Present
266	)
267
268	{
269	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
270	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
272	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
273	if (RT_SUCCESS(rc))
274	{
275	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
276	return rc;
277	}
278	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
279	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
280	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
281	return VINF_PGM_SYNC_CR3;
282	}
283
284	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
285	/*
286	* Check if this address is within any of our mappings.
287	*
288	* This is very fast and it's gonna save us a bit of effort below and prevent
289	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
290	* (BTW, it's impossible to have physical access handlers in a mapping.)
291	*/
292	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
293	{
294	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
295	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
296	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
297	{
298	if (pvFault < pMapping->GCPtr)
299	break;
300	if (pvFault - pMapping->GCPtr < pMapping->cb)
301	{
302	/*
303	* The first thing we check is if we've got an undetected conflict.
304	*/
305	if (!pVM->pgm.s.fMappingsFixed)
306	{
307	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
308	while (iPT-- > 0)
309	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
310	{
311	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
312	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
313	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
314	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
315	return VINF_PGM_SYNC_CR3;
316	}
317	}
318
319	/*
320	* Check if the fault address is in a virtual page access handler range.
321	*/
322	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
323	if ( pCur
324	&& pvFault - pCur->Core.Key < pCur->cb
325	&& uErr & X86_TRAP_PF_RW)
326	{
327	# ifdef IN_RC
328	STAM_PROFILE_START(&pCur->Stat, h);
329	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
330	STAM_PROFILE_STOP(&pCur->Stat, h);
331	# else
332	AssertFailed();
333	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
334	# endif
335	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
336	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
337	return rc;
338	}
339
340	/*
341	* Pretend we're not here and let the guest handle the trap.
342	*/
343	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
344	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
345	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
346	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
347	return VINF_EM_RAW_GUEST_TRAP;
348	}
349	}
350	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
351	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
352	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
353
354	/*
355	* Check if this fault address is flagged for special treatment,
356	* which means we'll have to figure out the physical address and
357	* check flags associated with it.
358	*
359	* ASSUME that we can limit any special access handling to pages
360	* in page tables which the guest believes to be present.
361	*/
362	if (PdeSrc.n.u1Present)
363	{
364	RTGCPHYS GCPhys = NIL_RTGCPHYS;
365
366	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
367	# if PGM_GST_TYPE == PGM_TYPE_AMD64
368	bool fBigPagesSupported = true;
369	# else
370	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
371	# endif
372	if ( PdeSrc.b.u1Size
373	&& fBigPagesSupported)
374	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
375	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
376	else
377	{
378	PGSTPT pPTSrc;
379	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
380	if (RT_SUCCESS(rc))
381	{
382	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
383	if (pPTSrc->a[iPTESrc].n.u1Present)
384	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
385	}
386	}
387	# else
388	/* No paging so the fault address is the physical address */
389	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
390	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
391
392	/*
393	* If we have a GC address we'll check if it has any flags set.
394	*/
395	if (GCPhys != NIL_RTGCPHYS)
396	{
397	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
398
399	PPGMPAGE pPage;
400	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
401	if (RT_SUCCESS(rc))
402	{
403	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
404	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
405	{
406	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
407	{
408	/*
409	* Physical page access handler.
410	*/
411	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
412	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
413	if (pCur)
414	{
415	# ifdef PGM_SYNC_N_PAGES
416	/*
417	* If the region is write protected and we got a page not present fault, then sync
418	* the pages. If the fault was caused by a read, then restart the instruction.
419	* In case of write access continue to the GC write handler.
420	*
421	* ASSUMES that there is only one handler per page or that they have similar write properties.
422	*/
423	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
424	&& !(uErr & X86_TRAP_PF_P))
425	{
426	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
427	if ( RT_FAILURE(rc)
428	\|\| !(uErr & X86_TRAP_PF_RW)
429	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
430	{
431	AssertRC(rc);
432	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
433	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
434	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
435	return rc;
436	}
437	}
438	# endif
439
440	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
441	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
442	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
443
444	# if defined(IN_RC) \|\| defined(IN_RING0)
445	if (pCur->CTX_SUFF(pfnHandler))
446	{
447	STAM_PROFILE_START(&pCur->Stat, h);
448	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
449	STAM_PROFILE_STOP(&pCur->Stat, h);
450	}
451	else
452	# endif
453	rc = VINF_EM_RAW_EMULATE_INSTR;
454	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
455	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
456	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
457	return rc;
458	}
459	}
460	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
461	else
462	{
463	# ifdef PGM_SYNC_N_PAGES
464	/*
465	* If the region is write protected and we got a page not present fault, then sync
466	* the pages. If the fault was caused by a read, then restart the instruction.
467	* In case of write access continue to the GC write handler.
468	*/
469	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
470	&& !(uErr & X86_TRAP_PF_P))
471	{
472	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
473	if ( RT_FAILURE(rc)
474	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
475	\|\| !(uErr & X86_TRAP_PF_RW))
476	{
477	AssertRC(rc);
478	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
479	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
480	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
481	return rc;
482	}
483	}
484	# endif
485	/*
486	* Ok, it's an virtual page access handler.
487	*
488	* Since it's faster to search by address, we'll do that first
489	* and then retry by GCPhys if that fails.
490	*/
491	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
492	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
493	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
494	*/
495	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
496	if (pCur)
497	{
498	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
499	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
500	\|\| !(uErr & X86_TRAP_PF_P)
501	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
502	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
503
504	if ( pvFault - pCur->Core.Key < pCur->cb
505	&& ( uErr & X86_TRAP_PF_RW
506	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
507	{
508	# ifdef IN_RC
509	STAM_PROFILE_START(&pCur->Stat, h);
510	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
511	STAM_PROFILE_STOP(&pCur->Stat, h);
512	# else
513	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
514	# endif
515	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
517	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
518	return rc;
519	}
520	/* Unhandled part of a monitored page */
521	}
522	else
523	{
524	/* Check by physical address. */
525	PPGMVIRTHANDLER pCur;
526	unsigned iPage;
527	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
528	&pCur, &iPage);
529	Assert(RT_SUCCESS(rc) \|\| !pCur);
530	if ( pCur
531	&& ( uErr & X86_TRAP_PF_RW
532	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
533	{
534	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
535	# ifdef IN_RC
536	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
537	Assert(off < pCur->cb);
538	STAM_PROFILE_START(&pCur->Stat, h);
539	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
540	STAM_PROFILE_STOP(&pCur->Stat, h);
541	# else
542	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
543	# endif
544	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
545	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
546	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
547	return rc;
548	}
549	}
550	}
551	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
552
553	/*
554	* There is a handled area of the page, but this fault doesn't belong to it.
555	* We must emulate the instruction.
556	*
557	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
558	* we first check if this was a page-not-present fault for a page with only
559	* write access handlers. Restart the instruction if it wasn't a write access.
560	*/
561	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
562
563	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
564	&& !(uErr & X86_TRAP_PF_P))
565	{
566	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
567	if ( RT_FAILURE(rc)
568	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
569	\|\| !(uErr & X86_TRAP_PF_RW))
570	{
571	AssertRC(rc);
572	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
573	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
574	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
575	return rc;
576	}
577	}
578
579	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
580	* It's writing to an unhandled part of the LDT page several million times.
581	*/
582	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
583	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
584	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
585	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
586	return rc;
587	} /* if any kind of handler */
588
589	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
590	if (uErr & X86_TRAP_PF_P)
591	{
592	/*
593	* The page isn't marked, but it might still be monitored by a virtual page access handler.
594	* (ASSUMES no temporary disabling of virtual handlers.)
595	*/
596	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
597	* we should correct both the shadow page table and physical memory flags, and not only check for
598	* accesses within the handler region but for access to pages with virtual handlers. */
599	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
600	if (pCur)
601	{
602	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
603	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
604	\|\| !(uErr & X86_TRAP_PF_P)
605	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
606	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
607
608	if ( pvFault - pCur->Core.Key < pCur->cb
609	&& ( uErr & X86_TRAP_PF_RW
610	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
611	{
612	# ifdef IN_RC
613	STAM_PROFILE_START(&pCur->Stat, h);
614	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
615	STAM_PROFILE_STOP(&pCur->Stat, h);
616	# else
617	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
618	# endif
619	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
620	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
621	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
622	return rc;
623	}
624	}
625	}
626	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
627	}
628	else
629	{
630	/*
631	* When the guest accesses invalid physical memory (e.g. probing
632	* of RAM or accessing a remapped MMIO range), then we'll fall
633	* back to the recompiler to emulate the instruction.
634	*/
635	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
636	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
637	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
638	return VINF_EM_RAW_EMULATE_INSTR;
639	}
640
641	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
642
643	# ifdef PGM_OUT_OF_SYNC_IN_GC
644	/*
645	* We are here only if page is present in Guest page tables and
646	* trap is not handled by our handlers.
647	*
648	* Check it for page out-of-sync situation.
649	*/
650	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
651
652	if (!(uErr & X86_TRAP_PF_P))
653	{
654	/*
655	* Page is not present in our page tables.
656	* Try to sync it!
657	* BTW, fPageShw is invalid in this branch!
658	*/
659	if (uErr & X86_TRAP_PF_US)
660	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
661	else /* supervisor */
662	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
663
664	# if defined(LOG_ENABLED) && !defined(IN_RING0)
665	RTGCPHYS GCPhys;
666	uint64_t fPageGst;
667	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
668	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
669	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
670	# endif /* LOG_ENABLED */
671
672	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
673	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
674	{
675	uint64_t fPageGst;
676	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
677	if ( RT_SUCCESS(rc)
678	&& !(fPageGst & X86_PTE_US))
679	{
680	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
681	if ( pvFault == (RTGCPTR)pRegFrame->eip
682	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
683	# ifdef CSAM_DETECT_NEW_CODE_PAGES
684	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
685	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
686	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
687	)
688	{
689	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
690	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
691	if (rc != VINF_SUCCESS)
692	{
693	/*
694	* CSAM needs to perform a job in ring 3.
695	*
696	* Sync the page before going to the host context; otherwise we'll end up in a loop if
697	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
698	*/
699	LogFlow(("CSAM ring 3 job\n"));
700	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
701	AssertRC(rc2);
702
703	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
704	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
705	return rc;
706	}
707	}
708	# ifdef CSAM_DETECT_NEW_CODE_PAGES
709	else if ( uErr == X86_TRAP_PF_RW
710	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
711	&& pRegFrame->ecx < 0x10000)
712	{
713	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
714	* to detect loading of new code pages.
715	*/
716
717	/*
718	* Decode the instruction.
719	*/
720	RTGCPTR PC;
721	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
722	if (rc == VINF_SUCCESS)
723	{
724	DISCPUSTATE Cpu;
725	uint32_t cbOp;
726	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
727
728	/* For now we'll restrict this to rep movsw/d instructions */
729	if ( rc == VINF_SUCCESS
730	&& Cpu.pCurInstr->opcode == OP_MOVSWD
731	&& (Cpu.prefix & PREFIX_REP))
732	{
733	CSAMMarkPossibleCodePage(pVM, pvFault);
734	}
735	}
736	}
737	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
738
739	/*
740	* Mark this page as safe.
741	*/
742	/** @todo not correct for pages that contain both code and data!! */
743	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
744	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
745	}
746	}
747	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
748	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
749	if (RT_SUCCESS(rc))
750	{
751	/* The page was successfully synced, return to the guest. */
752	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
753	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
754	return VINF_SUCCESS;
755	}
756	}
757	else
758	{
759	# ifdef VBOX_WITH_NEW_PHYS_CODE
760	/*
761	* Need to deal with these buggers somewhere...
762	*/
763	if ( PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
764	&& (uErr & X86_TRAP_PF_RW))
765	{
766	Log(("PGM #PF: %RGp %R[pgmpage] uErr=%#x\n", GCPhys, pPage, uErr));
767	AssertMsgFailed(("PGM #PF: %RGp %R[pgmpage] uErr=%#x\n", GCPhys, pPage, uErr));
768	}
769	# endif /* VBOX_WITH_NEW_PHYS_CODE */
770
771	/*
772	* A side effect of not flushing global PDEs are out of sync pages due
773	* to physical monitored regions, that are no longer valid.
774	* Assume for now it only applies to the read/write flag
775	*/
776	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
777	{
778	if (uErr & X86_TRAP_PF_US)
779	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
780	else /* supervisor */
781	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
782
783
784	/*
785	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
786	*/
787	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
788	if (RT_SUCCESS(rc))
789	{
790	/*
791	* Page was successfully synced, return to guest.
792	*/
793	# ifdef VBOX_STRICT
794	RTGCPHYS GCPhys;
795	uint64_t fPageGst;
796	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
797	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
798	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
799
800	uint64_t fPageShw;
801	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
802	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
803	# endif /* VBOX_STRICT */
804	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
805	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
806	return VINF_SUCCESS;
807	}
808
809	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
810	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
811	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
812	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
813	{
814	uint64_t fPageGst;
815	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
816	if ( RT_SUCCESS(rc)
817	&& !(fPageGst & X86_PTE_RW))
818	{
819	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
820	if (RT_SUCCESS(rc))
821	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
822	else
823	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
824	return rc;
825	}
826	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
827	}
828	}
829
830	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
831	# ifdef VBOX_STRICT
832	/*
833	* Check for VMM page flags vs. Guest page flags consistency.
834	* Currently only for debug purposes.
835	*/
836	if (RT_SUCCESS(rc))
837	{
838	/* Get guest page flags. */
839	uint64_t fPageGst;
840	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
841	if (RT_SUCCESS(rc))
842	{
843	uint64_t fPageShw;
844	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
845
846	/*
847	* Compare page flags.
848	* Note: we have AVL, A, D bits desynched.
849	*/
850	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
851	("Page flags mismatch! pvFault=%RGv GCPhys=%RGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
852	}
853	else
854	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
855	}
856	else
857	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
858	# endif /* VBOX_STRICT */
859	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
860	}
861	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
862	# endif /* PGM_OUT_OF_SYNC_IN_GC */
863	}
864	else
865	{
866	/*
867	* Page not present in Guest OS or invalid page table address.
868	* This is potential virtual page access handler food.
869	*
870	* For the present we'll say that our access handlers don't
871	* work for this case - we've already discarded the page table
872	* not present case which is identical to this.
873	*
874	* When we perchance find we need this, we will probably have AVL
875	* trees (offset based) to operate on and we can measure their speed
876	* agains mapping a page table and probably rearrange this handling
877	* a bit. (Like, searching virtual ranges before checking the
878	* physical address.)
879	*/
880	}
881	}
882
883
884	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
885	/*
886	* Conclusion, this is a guest trap.
887	*/
888	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
889	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
890	return VINF_EM_RAW_GUEST_TRAP;
891	# else
892	/* present, but not a monitored page; perhaps the guest is probing physical memory */
893	return VINF_EM_RAW_EMULATE_INSTR;
894	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
895
896
897	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
898
899	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
900	return VERR_INTERNAL_ERROR;
901	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
902	}
903	#endif /* !IN_RING3 */
904
905
906	/**
907	* Emulation of the invlpg instruction.
908	*
909	*
910	* @returns VBox status code.
911	*
912	* @param pVM VM handle.
913	* @param GCPtrPage Page to invalidate.
914	*
915	* @remark ASSUMES that the guest is updating before invalidating. This order
916	* isn't required by the CPU, so this is speculative and could cause
917	* trouble.
918	*
919	* @todo Flush page or page directory only if necessary!
920	* @todo Add a #define for simply invalidating the page.
921	*/
922	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
923	{
924	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
925	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
926	&& PGM_SHW_TYPE != PGM_TYPE_EPT
927	int rc;
928
929	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
930	/*
931	* Get the shadow PD entry and skip out if this PD isn't present.
932	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
933	*/
934	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
935	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
936	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
937
938	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
939	/* Fetch the pgm pool shadow descriptor. */
940	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
941	Assert(pShwPde);
942	# endif
943
944	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
945	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
946	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
947
948	/* If the shadow PDPE isn't present, then skip the invalidate. */
949	if (!pPdptDst->a[iPdpt].n.u1Present)
950	{
951	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
952	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
953	return VINF_SUCCESS;
954	}
955
956	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
957	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
958	PPGMPOOLPAGE pShwPde;
959	PX86PDPAE pPDDst;
960
961	/* Fetch the pgm pool shadow descriptor. */
962	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
963	AssertRCSuccessReturn(rc, rc);
964	Assert(pShwPde);
965
966	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
967	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
968	# else
969	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - pool index only atm! /;
970	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
971	# endif
972
973	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
974	/* PML4 */
975	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
976	AssertReturn(pVM->pgm.s.pShwRootR3, VERR_INTERNAL_ERROR);
977	# endif
978
979	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
980	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
981	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
982	PX86PDPAE pPDDst;
983	PX86PDPT pPdptDst;
984	PX86PML4E pPml4eDst;
985	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
986	if (rc != VINF_SUCCESS)
987	{
988	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
989	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
990	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
991	PGM_INVL_GUEST_TLBS();
992	return VINF_SUCCESS;
993	}
994	Assert(pPDDst);
995
996	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
997	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
998
999	if (!pPdpeDst->n.u1Present)
1000	{
1001	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1002	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
1003	PGM_INVL_GUEST_TLBS();
1004	return VINF_SUCCESS;
1005	}
1006
1007	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1008
1009	const SHWPDE PdeDst = *pPdeDst;
1010	if (!PdeDst.n.u1Present)
1011	{
1012	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1013	return VINF_SUCCESS;
1014	}
1015
1016	/*
1017	* Get the guest PD entry and calc big page.
1018	*/
1019	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1020	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1021	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1022	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1023	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1024	unsigned iPDSrc;
1025	# if PGM_GST_TYPE == PGM_TYPE_PAE
1026	X86PDPE PdpeSrc;
1027	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1028	# else /* AMD64 */
1029	PX86PML4E pPml4eSrc;
1030	X86PDPE PdpeSrc;
1031	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1032	# endif
1033	GSTPDE PdeSrc;
1034
1035	if (pPDSrc)
1036	PdeSrc = pPDSrc->a[iPDSrc];
1037	else
1038	PdeSrc.u = 0;
1039	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1040
1041	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1042	const bool fIsBigPage = PdeSrc.b.u1Size;
1043	# else
1044	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1045	# endif
1046
1047	# ifdef IN_RING3
1048	/*
1049	* If a CR3 Sync is pending we may ignore the invalidate page operation
1050	* depending on the kind of sync and if it's a global page or not.
1051	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1052	*/
1053	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1054	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
1055	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
1056	&& fIsBigPage
1057	&& PdeSrc.b.u1Global
1058	)
1059	)
1060	# else
1061	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1062	# endif
1063	{
1064	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1065	return VINF_SUCCESS;
1066	}
1067	# endif /* IN_RING3 */
1068
1069	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1070	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1071
1072	/* Fetch the pgm pool shadow descriptor. */
1073	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1074	Assert(pShwPdpt);
1075
1076	/* Fetch the pgm pool shadow descriptor. */
1077	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1078	Assert(pShwPde);
1079
1080	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1081	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1082
1083	if ( !pPml4eSrc->n.u1Present
1084	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1085	{
1086	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1087	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1088	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1089	pPml4eDst->u = 0;
1090	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1091	PGM_INVL_GUEST_TLBS();
1092	return VINF_SUCCESS;
1093	}
1094	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1095	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1096	{
1097	/*
1098	* Mark not present so we can resync the PML4E when it's used.
1099	*/
1100	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1101	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1102	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1103	pPml4eDst->u = 0;
1104	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1105	PGM_INVL_GUEST_TLBS();
1106	}
1107	else if (!pPml4eSrc->n.u1Accessed)
1108	{
1109	/*
1110	* Mark not present so we can set the accessed bit.
1111	*/
1112	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1113	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1114	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1115	pPml4eDst->u = 0;
1116	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1117	PGM_INVL_GUEST_TLBS();
1118	}
1119
1120	/* Check if the PDPT entry has changed. */
1121	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1122	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1123	if ( !PdpeSrc.n.u1Present
1124	\|\| pShwPde->GCPhys != GCPhysPd)
1125	{
1126	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1127	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1128	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1129	pPdpeDst->u = 0;
1130	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1131	PGM_INVL_GUEST_TLBS();
1132	return VINF_SUCCESS;
1133	}
1134	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1135	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1136	{
1137	/*
1138	* Mark not present so we can resync the PDPTE when it's used.
1139	*/
1140	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1141	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1142	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1143	pPdpeDst->u = 0;
1144	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1145	PGM_INVL_GUEST_TLBS();
1146	}
1147	else if (!PdpeSrc.lm.u1Accessed)
1148	{
1149	/*
1150	* Mark not present so we can set the accessed bit.
1151	*/
1152	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1153	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1154	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1155	pPdpeDst->u = 0;
1156	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1157	PGM_INVL_GUEST_TLBS();
1158	}
1159	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1160
1161	# if PGM_GST_TYPE == PGM_TYPE_PAE && !defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1162	/*
1163	* Update the shadow PDPE and free all the shadow PD entries if the PDPE is marked not present.
1164	* Note: This shouldn't actually be necessary as we monitor the PDPT page for changes.
1165	*/
1166	if (!pPDSrc)
1167	{
1168	/* Guest PDPE not present */
1169	PX86PDPAE pPDDst = pgmShwGetPaePDPtr(&pVM->pgm.s, GCPtrPage);
1170	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1171
1172	Assert(!PdpeSrc.n.u1Present);
1173	LogFlow(("InvalidatePage: guest PDPE %d not present; clear shw pdpe\n", iPdpt));
1174
1175	/* for each page directory entry */
1176	for (unsigned iPD = 0; iPD < X86_PG_PAE_ENTRIES; iPD++)
1177	{
1178	if ( pPDDst->a[iPD].n.u1Present
1179	&& !(pPDDst->a[iPD].u & PGM_PDFLAGS_MAPPING))
1180	{
1181	pgmPoolFree(pVM, pPDDst->a[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
1182	pPDDst->a[iPD].u = 0;
1183	}
1184	}
1185	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
1186	pPdptDst->a[iPdpt].n.u1Present = 0;
1187	PGM_INVL_GUEST_TLBS();
1188	}
1189	AssertMsg(pVM->pgm.s.fMappingsFixed \|\| (PdpeSrc.u & X86_PDPE_PG_MASK) == pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt], ("%RGp vs %RGp (mon)\n", (PdpeSrc.u & X86_PDPE_PG_MASK), pVM->pgm.s.aGCPhysGstPaePDsMonitored[iPdpt]));
1190	# endif
1191
1192
1193	/*
1194	* Deal with the Guest PDE.
1195	*/
1196	rc = VINF_SUCCESS;
1197	if (PdeSrc.n.u1Present)
1198	{
1199	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1200	{
1201	/*
1202	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1203	*/
1204	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1205	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1206	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1207	}
1208	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1209	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1210	{
1211	/*
1212	* Mark not present so we can resync the PDE when it's used.
1213	*/
1214	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1215	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1216	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1217	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1218	# else
1219	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1220	# endif
1221	pPdeDst->u = 0;
1222	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1223	PGM_INVL_GUEST_TLBS();
1224	}
1225	else if (!PdeSrc.n.u1Accessed)
1226	{
1227	/*
1228	* Mark not present so we can set the accessed bit.
1229	*/
1230	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1231	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1232	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1233	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1234	# else
1235	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1236	# endif
1237	pPdeDst->u = 0;
1238	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1239	PGM_INVL_GUEST_TLBS();
1240	}
1241	else if (!fIsBigPage)
1242	{
1243	/*
1244	* 4KB - page.
1245	*/
1246	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1247	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1248	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1249	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1250	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1251	# endif
1252	if (pShwPage->GCPhys == GCPhys)
1253	{
1254	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1255	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1256	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1257	if (pPT->a[iPTEDst].n.u1Present)
1258	{
1259	# ifdef PGMPOOL_WITH_USER_TRACKING
1260	/* This is very unlikely with caching/monitoring enabled. */
1261	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1262	# endif
1263	pPT->a[iPTEDst].u = 0;
1264	}
1265	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1266	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1267	if (RT_SUCCESS(rc))
1268	rc = VINF_SUCCESS;
1269	# endif
1270	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1271	PGM_INVL_PG(GCPtrPage);
1272	}
1273	else
1274	{
1275	/*
1276	* The page table address changed.
1277	*/
1278	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1279	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1280	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1281	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1282	# else
1283	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1284	# endif
1285	pPdeDst->u = 0;
1286	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1287	PGM_INVL_GUEST_TLBS();
1288	}
1289	}
1290	else
1291	{
1292	/*
1293	* 2/4MB - page.
1294	*/
1295	/* Before freeing the page, check if anything really changed. */
1296	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1297	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1298	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1299	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1300	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1301	# endif
1302	if ( pShwPage->GCPhys == GCPhys
1303	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1304	{
1305	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1306	/** @todo PAT */
1307	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1308	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1309	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1310	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1311	{
1312	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1313	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1314	return VINF_SUCCESS;
1315	}
1316	}
1317
1318	/*
1319	* Ok, the page table is present and it's been changed in the guest.
1320	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1321	* We could do this for some flushes in GC too, but we need an algorithm for
1322	* deciding which 4MB pages containing code likely to be executed very soon.
1323	*/
1324	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1325	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1326	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1327	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1328	# else
1329	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1330	# endif
1331	pPdeDst->u = 0;
1332	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1333	PGM_INVL_BIG_PG(GCPtrPage);
1334	}
1335	}
1336	else
1337	{
1338	/*
1339	* Page directory is not present, mark shadow PDE not present.
1340	*/
1341	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1342	{
1343	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1344	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1345	# else
1346	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1347	# endif
1348	pPdeDst->u = 0;
1349	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1350	PGM_INVL_PG(GCPtrPage);
1351	}
1352	else
1353	{
1354	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1355	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1356	}
1357	}
1358
1359	return rc;
1360
1361	#else /* guest real and protected mode */
1362	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1363	return VINF_SUCCESS;
1364	#endif
1365	}
1366
1367
1368	#ifdef PGMPOOL_WITH_USER_TRACKING
1369	/**
1370	* Update the tracking of shadowed pages.
1371	*
1372	* @param pVM The VM handle.
1373	* @param pShwPage The shadow page.
1374	* @param HCPhys The physical page we is being dereferenced.
1375	*/
1376	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1377	{
1378	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1379	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1380	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1381
1382	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1383	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1384	* 2. write protect all shadowed pages. I.e. implement caching.
1385	*/
1386	/*
1387	* Find the guest address.
1388	*/
1389	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1390	pRam;
1391	pRam = pRam->CTX_SUFF(pNext))
1392	{
1393	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1394	while (iPage-- > 0)
1395	{
1396	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1397	{
1398	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1399	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1400	pShwPage->cPresent--;
1401	pPool->cPresent--;
1402	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1403	return;
1404	}
1405	}
1406	}
1407
1408	for (;;)
1409	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1410	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1411	pShwPage->cPresent--;
1412	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1413	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1414	}
1415
1416
1417	/**
1418	* Update the tracking of shadowed pages.
1419	*
1420	* @param pVM The VM handle.
1421	* @param pShwPage The shadow page.
1422	* @param u16 The top 16-bit of the pPage->HCPhys.
1423	* @param pPage Pointer to the guest page. this will be modified.
1424	* @param iPTDst The index into the shadow table.
1425	*/
1426	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1427	{
1428	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1429	/*
1430	* Just deal with the simple first time here.
1431	*/
1432	if (!u16)
1433	{
1434	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1435	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1436	}
1437	else
1438	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1439
1440	/* write back */
1441	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1442	PGM_PAGE_SET_TRACKING(pPage, u16);
1443
1444	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1445
1446	/* update statistics. */
1447	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1448	pShwPage->cPresent++;
1449	if (pShwPage->iFirstPresent > iPTDst)
1450	pShwPage->iFirstPresent = iPTDst;
1451	}
1452	#endif /* PGMPOOL_WITH_USER_TRACKING */
1453
1454
1455	/**
1456	* Creates a 4K shadow page for a guest page.
1457	*
1458	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1459	* physical address. The PdeSrc argument only the flags are used. No page structured
1460	* will be mapped in this function.
1461	*
1462	* @param pVM VM handle.
1463	* @param pPteDst Destination page table entry.
1464	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1465	* Can safely assume that only the flags are being used.
1466	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1467	* @param pShwPage Pointer to the shadow page.
1468	* @param iPTDst The index into the shadow table.
1469	*
1470	* @remark Not used for 2/4MB pages!
1471	*/
1472	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1473	{
1474	if (PteSrc.n.u1Present)
1475	{
1476	/*
1477	* Find the ram range.
1478	*/
1479	PPGMPAGE pPage;
1480	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1481	if (RT_SUCCESS(rc))
1482	{
1483	#ifdef VBOX_WITH_NEW_PHYS_CODE
1484	/* Try make the page writable if necessary. */
1485	if ( PteSrc.n.u1Write
1486	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1487	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1488	{
1489	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1490	AssertRC(rc);
1491	}
1492	#endif
1493
1494	/** @todo investiage PWT, PCD and PAT. */
1495	/*
1496	* Make page table entry.
1497	*/
1498	SHWPTE PteDst;
1499	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1500	{
1501	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1502	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1503	{
1504	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1505	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1506	PteDst.n.u1Present = 1;
1507	PteDst.n.u1Execute = 1;
1508	PteDst.n.u1IgnorePAT = 1;
1509	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1510	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1511	#else
1512	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1513	\| PGM_PAGE_GET_HCPHYS(pPage);
1514	#endif
1515	}
1516	else
1517	{
1518	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1519	PteDst.u = 0;
1520	}
1521	/** @todo count these two kinds. */
1522	}
1523	else
1524	{
1525	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1526	/*
1527	* If the page or page directory entry is not marked accessed,
1528	* we mark the page not present.
1529	*/
1530	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1531	{
1532	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1533	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1534	PteDst.u = 0;
1535	}
1536	else
1537	/*
1538	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1539	* when the page is modified.
1540	*/
1541	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1542	{
1543	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1544	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1545	\| PGM_PAGE_GET_HCPHYS(pPage)
1546	\| PGM_PTFLAGS_TRACK_DIRTY;
1547	}
1548	else
1549	#endif
1550	{
1551	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1552	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1553	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1554	PteDst.n.u1Present = 1;
1555	PteDst.n.u1Write = 1;
1556	PteDst.n.u1Execute = 1;
1557	PteDst.n.u1IgnorePAT = 1;
1558	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1559	/* PteDst.n.u1Size = 0 */
1560	#else
1561	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1562	\| PGM_PAGE_GET_HCPHYS(pPage);
1563	#endif
1564	}
1565	}
1566
1567	#ifdef VBOX_WITH_NEW_PHYS_CODE
1568	/*
1569	* Make sure only allocated pages are mapped writable.
1570	*/
1571	if ( PteDst.n.u1Write
1572	&& PteDst.n.u1Present
1573	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1574	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1575	#endif
1576
1577	#ifdef PGMPOOL_WITH_USER_TRACKING
1578	/*
1579	* Keep user track up to date.
1580	*/
1581	if (PteDst.n.u1Present)
1582	{
1583	if (!pPteDst->n.u1Present)
1584	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1585	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1586	{
1587	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1588	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1589	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1590	}
1591	}
1592	else if (pPteDst->n.u1Present)
1593	{
1594	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1595	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1596	}
1597	#endif /* PGMPOOL_WITH_USER_TRACKING */
1598
1599	/*
1600	* Update statistics and commit the entry.
1601	*/
1602	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1603	if (!PteSrc.n.u1Global)
1604	pShwPage->fSeenNonGlobal = true;
1605	#endif
1606	*pPteDst = PteDst;
1607	}
1608	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1609	/** @todo count these. */
1610	}
1611	else
1612	{
1613	/*
1614	* Page not-present.
1615	*/
1616	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1617	#ifdef PGMPOOL_WITH_USER_TRACKING
1618	/* Keep user track up to date. */
1619	if (pPteDst->n.u1Present)
1620	{
1621	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1622	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1623	}
1624	#endif /* PGMPOOL_WITH_USER_TRACKING */
1625	pPteDst->u = 0;
1626	/** @todo count these. */
1627	}
1628	}
1629
1630
1631	/**
1632	* Syncs a guest OS page.
1633	*
1634	* There are no conflicts at this point, neither is there any need for
1635	* page table allocations.
1636	*
1637	* @returns VBox status code.
1638	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1639	* @param pVM VM handle.
1640	* @param PdeSrc Page directory entry of the guest.
1641	* @param GCPtrPage Guest context page address.
1642	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1643	* @param uErr Fault error (X86_TRAP_PF_*).
1644	*/
1645	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1646	{
1647	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1648
1649	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1650	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1651	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1652	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1653	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1654
1655	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1656	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1657	# endif
1658
1659	/*
1660	* Assert preconditions.
1661	*/
1662	Assert(PdeSrc.n.u1Present);
1663	Assert(cPages);
1664	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1665
1666	/*
1667	* Get the shadow PDE, find the shadow page table in the pool.
1668	*/
1669	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1670	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1671	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
1672
1673	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1674	/* Fetch the pgm pool shadow descriptor. */
1675	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
1676	Assert(pShwPde);
1677	# endif
1678
1679	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1680
1681	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1682	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1683	PPGMPOOLPAGE pShwPde;
1684	PX86PDPAE pPDDst;
1685
1686	/* Fetch the pgm pool shadow descriptor. */
1687	int rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
1688	AssertRCSuccessReturn(rc, rc);
1689	Assert(pShwPde);
1690
1691	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1692	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1693	# else
1694	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
1695	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1696	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
1697	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
1698	AssertReturn(pPdeDst, VERR_INTERNAL_ERROR);
1699	# endif
1700	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1701	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1702	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1703	PX86PDPAE pPDDst;
1704	PX86PDPT pPdptDst;
1705
1706	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1707	AssertRCSuccessReturn(rc, rc);
1708	Assert(pPDDst && pPdptDst);
1709	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1710	# endif
1711
1712	SHWPDE PdeDst = *pPdeDst;
1713	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1714	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1715
1716	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1717	/* Fetch the pgm pool shadow descriptor. */
1718	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1719	Assert(pShwPde);
1720	# endif
1721
1722	/*
1723	* Check that the page is present and that the shadow PDE isn't out of sync.
1724	*/
1725	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1726	const bool fBigPage = PdeSrc.b.u1Size;
1727	# else
1728	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1729	# endif
1730	RTGCPHYS GCPhys;
1731	if (!fBigPage)
1732	{
1733	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1734	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1735	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1736	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1737	# endif
1738	}
1739	else
1740	{
1741	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1742	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1743	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1744	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1745	# endif
1746	}
1747	if ( pShwPage->GCPhys == GCPhys
1748	&& PdeSrc.n.u1Present
1749	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1750	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1751	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1752	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1753	# endif
1754	)
1755	{
1756	/*
1757	* Check that the PDE is marked accessed already.
1758	* Since we set the accessed bit before getting here on a #PF, this
1759	* check is only meant for dealing with non-#PF'ing paths.
1760	*/
1761	if (PdeSrc.n.u1Accessed)
1762	{
1763	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1764	if (!fBigPage)
1765	{
1766	/*
1767	* 4KB Page - Map the guest page table.
1768	*/
1769	PGSTPT pPTSrc;
1770	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1771	if (RT_SUCCESS(rc))
1772	{
1773	# ifdef PGM_SYNC_N_PAGES
1774	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1775	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1776	{
1777	/*
1778	* This code path is currently only taken when the caller is PGMTrap0eHandler
1779	* for non-present pages!
1780	*
1781	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1782	* deal with locality.
1783	*/
1784	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1785	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1786	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1787	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1788	# else
1789	const unsigned offPTSrc = 0;
1790	# endif
1791	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1792	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1793	iPTDst = 0;
1794	else
1795	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1796	for (; iPTDst < iPTDstEnd; iPTDst++)
1797	{
1798	if (!pPTDst->a[iPTDst].n.u1Present)
1799	{
1800	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1801	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1802	NOREF(GCPtrCurPage);
1803	#ifndef IN_RING0
1804	/*
1805	* Assuming kernel code will be marked as supervisor - and not as user level
1806	* and executed using a conforming code selector - And marked as readonly.
1807	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1808	*/
1809	PPGMPAGE pPage;
1810	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1811	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1812	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1813	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1814	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1815	)
1816	#endif /* else: CSAM not active */
1817	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1818	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1819	GCPtrCurPage, PteSrc.n.u1Present,
1820	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1821	PteSrc.n.u1User & PdeSrc.n.u1User,
1822	(uint64_t)PteSrc.u,
1823	(uint64_t)pPTDst->a[iPTDst].u,
1824	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1825	}
1826	}
1827	}
1828	else
1829	# endif /* PGM_SYNC_N_PAGES */
1830	{
1831	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1832	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1833	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1834	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1835	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1836	GCPtrPage, PteSrc.n.u1Present,
1837	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1838	PteSrc.n.u1User & PdeSrc.n.u1User,
1839	(uint64_t)PteSrc.u,
1840	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1841	}
1842	}
1843	else /* MMIO or invalid page: emulated in #PF handler. */
1844	{
1845	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1846	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1847	}
1848	}
1849	else
1850	{
1851	/*
1852	* 4/2MB page - lazy syncing shadow 4K pages.
1853	* (There are many causes of getting here, it's no longer only CSAM.)
1854	*/
1855	/* Calculate the GC physical address of this 4KB shadow page. */
1856	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1857	/* Find ram range. */
1858	PPGMPAGE pPage;
1859	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1860	if (RT_SUCCESS(rc))
1861	{
1862	# ifdef VBOX_WITH_NEW_PHYS_CODE
1863	/* Try make the page writable if necessary. */
1864	if ( PdeSrc.n.u1Write
1865	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1866	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1867	{
1868	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1869	AssertRC(rc);
1870	}
1871	# endif
1872
1873	/*
1874	* Make shadow PTE entry.
1875	*/
1876	SHWPTE PteDst;
1877	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1878	\| PGM_PAGE_GET_HCPHYS(pPage);
1879	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1880	{
1881	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1882	PteDst.n.u1Write = 0;
1883	else
1884	PteDst.u = 0;
1885	}
1886	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1887	# ifdef PGMPOOL_WITH_USER_TRACKING
1888	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1889	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1890	# endif
1891	# ifdef VBOX_WITH_NEW_PHYS_CODE
1892	/* Make sure only allocated pages are mapped writable. */
1893	if ( PteDst.n.u1Write
1894	&& PteDst.n.u1Present
1895	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1896	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1897	# endif
1898
1899	pPTDst->a[iPTDst] = PteDst;
1900
1901
1902	/*
1903	* If the page is not flagged as dirty and is writable, then make it read-only
1904	* at PD level, so we can set the dirty bit when the page is modified.
1905	*
1906	* ASSUMES that page access handlers are implemented on page table entry level.
1907	* Thus we will first catch the dirty access and set PDE.D and restart. If
1908	* there is an access handler, we'll trap again and let it work on the problem.
1909	*/
1910	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1911	* As for invlpg, it simply frees the whole shadow PT.
1912	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1913	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1914	{
1915	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1916	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1917	PdeDst.n.u1Write = 0;
1918	}
1919	else
1920	{
1921	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1922	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1923	}
1924	*pPdeDst = PdeDst;
1925	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1926	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1927	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1928	}
1929	else
1930	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1931	}
1932	return VINF_SUCCESS;
1933	}
1934	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1935	}
1936	else
1937	{
1938	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1939	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1940	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1941	}
1942
1943	/*
1944	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1945	* Yea, I'm lazy.
1946	*/
1947	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1948	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
1949	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1950	# else
1951	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPDDst);
1952	# endif
1953
1954	pPdeDst->u = 0;
1955	PGM_INVL_GUEST_TLBS();
1956	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1957
1958	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1959	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1960	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
1961
1962	# ifdef PGM_SYNC_N_PAGES
1963	/*
1964	* Get the shadow PDE, find the shadow page table in the pool.
1965	*/
1966	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1967	X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
1968
1969	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1970	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1971
1972	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1973	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1974	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1975	PX86PDPAE pPDDst;
1976	X86PDEPAE PdeDst;
1977	PX86PDPT pPdptDst;
1978
1979	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1980	AssertRCSuccessReturn(rc, rc);
1981	Assert(pPDDst && pPdptDst);
1982	PdeDst = pPDDst->a[iPDDst];
1983	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1984	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1985	PEPTPD pPDDst;
1986	EPTPDE PdeDst;
1987
1988	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1989	if (rc != VINF_SUCCESS)
1990	{
1991	AssertRC(rc);
1992	return rc;
1993	}
1994	Assert(pPDDst);
1995	PdeDst = pPDDst->a[iPDDst];
1996	# endif
1997	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1998	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1999	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2000
2001	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2002	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
2003	{
2004	/*
2005	* This code path is currently only taken when the caller is PGMTrap0eHandler
2006	* for non-present pages!
2007	*
2008	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2009	* deal with locality.
2010	*/
2011	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2012	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2013	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2014	iPTDst = 0;
2015	else
2016	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2017	for (; iPTDst < iPTDstEnd; iPTDst++)
2018	{
2019	if (!pPTDst->a[iPTDst].n.u1Present)
2020	{
2021	GSTPTE PteSrc;
2022
2023	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2024
2025	/* Fake the page table entry */
2026	PteSrc.u = GCPtrCurPage;
2027	PteSrc.n.u1Present = 1;
2028	PteSrc.n.u1Dirty = 1;
2029	PteSrc.n.u1Accessed = 1;
2030	PteSrc.n.u1Write = 1;
2031	PteSrc.n.u1User = 1;
2032
2033	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2034
2035	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2036	GCPtrCurPage, PteSrc.n.u1Present,
2037	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2038	PteSrc.n.u1User & PdeSrc.n.u1User,
2039	(uint64_t)PteSrc.u,
2040	(uint64_t)pPTDst->a[iPTDst].u,
2041	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2042	}
2043	else
2044	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2045	}
2046	}
2047	else
2048	# endif /* PGM_SYNC_N_PAGES */
2049	{
2050	GSTPTE PteSrc;
2051	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2052	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2053
2054	/* Fake the page table entry */
2055	PteSrc.u = GCPtrCurPage;
2056	PteSrc.n.u1Present = 1;
2057	PteSrc.n.u1Dirty = 1;
2058	PteSrc.n.u1Accessed = 1;
2059	PteSrc.n.u1Write = 1;
2060	PteSrc.n.u1User = 1;
2061	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2062
2063	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2064	GCPtrPage, PteSrc.n.u1Present,
2065	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2066	PteSrc.n.u1User & PdeSrc.n.u1User,
2067	(uint64_t)PteSrc.u,
2068	(uint64_t)pPTDst->a[iPTDst].u,
2069	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2070	}
2071	return VINF_SUCCESS;
2072
2073	#else
2074	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2075	return VERR_INTERNAL_ERROR;
2076	#endif
2077	}
2078
2079
2080	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2081	/**
2082	* Investigate page fault and handle write protection page faults caused by
2083	* dirty bit tracking.
2084	*
2085	* @returns VBox status code.
2086	* @param pVM VM handle.
2087	* @param uErr Page fault error code.
2088	* @param pPdeDst Shadow page directory entry.
2089	* @param pPdeSrc Guest page directory entry.
2090	* @param GCPtrPage Guest context page address.
2091	*/
2092	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2093	{
2094	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
2095	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2096	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2097	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2098	bool fBigPagesSupported = true;
2099	# else
2100	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2101	# endif
2102	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2103	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
2104	# endif
2105	unsigned uPageFaultLevel;
2106	int rc;
2107
2108	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2109	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2110
2111	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2112	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2113
2114	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2115	PX86PML4E pPml4eSrc;
2116	PX86PDPE pPdpeSrc;
2117
2118	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2119	Assert(pPml4eSrc);
2120
2121	/*
2122	* Real page fault? (PML4E level)
2123	*/
2124	if ( (uErr & X86_TRAP_PF_RSVD)
2125	\|\| !pPml4eSrc->n.u1Present
2126	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2127	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2128	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2129	)
2130	{
2131	uPageFaultLevel = 0;
2132	goto l_UpperLevelPageFault;
2133	}
2134	Assert(pPdpeSrc);
2135
2136	# else /* PAE */
2137	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2138	# endif /* PAE */
2139
2140	/*
2141	* Real page fault? (PDPE level)
2142	*/
2143	if ( (uErr & X86_TRAP_PF_RSVD)
2144	\|\| !pPdpeSrc->n.u1Present
2145	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2146	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2147	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2148	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2149	# endif
2150	)
2151	{
2152	uPageFaultLevel = 1;
2153	goto l_UpperLevelPageFault;
2154	}
2155	# endif
2156
2157	/*
2158	* Real page fault? (PDE level)
2159	*/
2160	if ( (uErr & X86_TRAP_PF_RSVD)
2161	\|\| !pPdeSrc->n.u1Present
2162	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2163	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2164	# endif
2165	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2166	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2167	{
2168	uPageFaultLevel = 2;
2169	goto l_UpperLevelPageFault;
2170	}
2171
2172	/*
2173	* First check the easy case where the page directory has been marked read-only to track
2174	* the dirty bit of an emulated BIG page
2175	*/
2176	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2177	{
2178	/* Mark guest page directory as accessed */
2179	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2180	pPml4eSrc->n.u1Accessed = 1;
2181	pPdpeSrc->lm.u1Accessed = 1;
2182	# endif
2183	pPdeSrc->b.u1Accessed = 1;
2184
2185	/*
2186	* Only write protection page faults are relevant here.
2187	*/
2188	if (fWriteFault)
2189	{
2190	/* Mark guest page directory as dirty (BIG page only). */
2191	pPdeSrc->b.u1Dirty = 1;
2192
2193	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2194	{
2195	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2196
2197	Assert(pPdeSrc->b.u1Write);
2198
2199	pPdeDst->n.u1Write = 1;
2200	pPdeDst->n.u1Accessed = 1;
2201	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2202	PGM_INVL_BIG_PG(GCPtrPage);
2203	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2204	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2205	}
2206	}
2207	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2208	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2209	}
2210	/* else: 4KB page table */
2211
2212	/*
2213	* Map the guest page table.
2214	*/
2215	PGSTPT pPTSrc;
2216	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2217	if (RT_SUCCESS(rc))
2218	{
2219	/*
2220	* Real page fault?
2221	*/
2222	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2223	const GSTPTE PteSrc = *pPteSrc;
2224	if ( !PteSrc.n.u1Present
2225	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2226	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2227	# endif
2228	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2229	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2230	)
2231	{
2232	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2233	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2234	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2235
2236	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2237	* See the 2nd case above as well.
2238	*/
2239	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2240	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2241
2242	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2243	return VINF_EM_RAW_GUEST_TRAP;
2244	}
2245	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2246
2247	/*
2248	* Set the accessed bits in the page directory and the page table.
2249	*/
2250	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2251	pPml4eSrc->n.u1Accessed = 1;
2252	pPdpeSrc->lm.u1Accessed = 1;
2253	# endif
2254	pPdeSrc->n.u1Accessed = 1;
2255	pPteSrc->n.u1Accessed = 1;
2256
2257	/*
2258	* Only write protection page faults are relevant here.
2259	*/
2260	if (fWriteFault)
2261	{
2262	/* Write access, so mark guest entry as dirty. */
2263	# ifdef VBOX_WITH_STATISTICS
2264	if (!pPteSrc->n.u1Dirty)
2265	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2266	else
2267	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2268	# endif
2269
2270	pPteSrc->n.u1Dirty = 1;
2271
2272	if (pPdeDst->n.u1Present)
2273	{
2274	#ifndef IN_RING0
2275	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2276	* Our individual shadow handlers will provide more information and force a fatal exit.
2277	*/
2278	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2279	{
2280	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2281	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2282	return VINF_SUCCESS;
2283	}
2284	#endif
2285	/*
2286	* Map shadow page table.
2287	*/
2288	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2289	if (pShwPage)
2290	{
2291	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2292	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2293	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2294	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2295	{
2296	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2297	# ifdef VBOX_STRICT
2298	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2299	if (pPage)
2300	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2301	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2302	# endif
2303	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2304
2305	Assert(pPteSrc->n.u1Write);
2306
2307	pPteDst->n.u1Write = 1;
2308	pPteDst->n.u1Dirty = 1;
2309	pPteDst->n.u1Accessed = 1;
2310	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2311	PGM_INVL_PG(GCPtrPage);
2312
2313	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2314	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2315	}
2316	}
2317	else
2318	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2319	}
2320	}
2321	/** @todo Optimize accessed bit emulation? */
2322	# ifdef VBOX_STRICT
2323	/*
2324	* Sanity check.
2325	*/
2326	else if ( !pPteSrc->n.u1Dirty
2327	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2328	&& pPdeDst->n.u1Present)
2329	{
2330	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2331	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2332	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2333	if ( pPteDst->n.u1Present
2334	&& pPteDst->n.u1Write)
2335	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2336	}
2337	# endif /* VBOX_STRICT */
2338	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2339	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2340	}
2341	AssertRC(rc);
2342	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2343	return rc;
2344
2345
2346	l_UpperLevelPageFault:
2347	/*
2348	* Pagefault detected while checking the PML4E, PDPE or PDE.
2349	* Single exit handler to get rid of duplicate code paths.
2350	*/
2351	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2352	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2353	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2354
2355	if (
2356	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2357	pPml4eSrc->n.u1Present &&
2358	# endif
2359	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2360	pPdpeSrc->n.u1Present &&
2361	# endif
2362	pPdeSrc->n.u1Present)
2363	{
2364	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2365	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2366	{
2367	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2368	}
2369	else
2370	{
2371	/*
2372	* Map the guest page table.
2373	*/
2374	PGSTPT pPTSrc;
2375	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2376	if (RT_SUCCESS(rc))
2377	{
2378	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2379	const GSTPTE PteSrc = *pPteSrc;
2380	if (pPteSrc->n.u1Present)
2381	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2382	}
2383	AssertRC(rc);
2384	}
2385	}
2386	return VINF_EM_RAW_GUEST_TRAP;
2387	}
2388	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2389
2390
2391	/**
2392	* Sync a shadow page table.
2393	*
2394	* The shadow page table is not present. This includes the case where
2395	* there is a conflict with a mapping.
2396	*
2397	* @returns VBox status code.
2398	* @param pVM VM handle.
2399	* @param iPD Page directory index.
2400	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2401	* Assume this is a temporary mapping.
2402	* @param GCPtrPage GC Pointer of the page that caused the fault
2403	*/
2404	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2405	{
2406	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2407	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2408	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2409
2410	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2411	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2412	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2413	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2414	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2415
2416	int rc = VINF_SUCCESS;
2417
2418	/*
2419	* Validate input a little bit.
2420	*/
2421	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2422	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2423	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2424	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2425
2426	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2427	/* Fetch the pgm pool shadow descriptor. */
2428	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2429	Assert(pShwPde);
2430	# endif
2431
2432	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2433	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2434	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2435	PPGMPOOLPAGE pShwPde;
2436	PX86PDPAE pPDDst;
2437	PSHWPDE pPdeDst;
2438
2439	/* Fetch the pgm pool shadow descriptor. */
2440	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2441	AssertRCSuccessReturn(rc, rc);
2442	Assert(pShwPde);
2443
2444	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2445	pPdeDst = &pPDDst->a[iPDDst];
2446	# else
2447	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm! /;
2448	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT); NOREF(iPdpt);
2449	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s); NOREF(pPdptDst);
2450	PSHWPDE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2451	# endif
2452	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2453	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2454	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2455	PX86PDPAE pPDDst;
2456	PX86PDPT pPdptDst;
2457	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2458	AssertRCSuccessReturn(rc, rc);
2459	Assert(pPDDst);
2460	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2461	# endif
2462	SHWPDE PdeDst = *pPdeDst;
2463
2464	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2465	/* Fetch the pgm pool shadow descriptor. */
2466	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2467	Assert(pShwPde);
2468	# endif
2469
2470	# ifndef PGM_WITHOUT_MAPPINGS
2471	/*
2472	* Check for conflicts.
2473	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2474	* HC: Simply resolve the conflict.
2475	*/
2476	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2477	{
2478	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2479	# ifndef IN_RING3
2480	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2481	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2482	return VERR_ADDRESS_CONFLICT;
2483	# else
2484	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2485	Assert(pMapping);
2486	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2487	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2488	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2489	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2490	# else
2491	AssertFailed(); /* can't happen for amd64 */
2492	# endif
2493	if (RT_FAILURE(rc))
2494	{
2495	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2496	return rc;
2497	}
2498	PdeDst = *pPdeDst;
2499	# endif
2500	}
2501	# else /* PGM_WITHOUT_MAPPINGS */
2502	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2503	# endif /* PGM_WITHOUT_MAPPINGS */
2504	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2505
2506	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2507	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2508	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2509	# endif
2510
2511	/*
2512	* Sync page directory entry.
2513	*/
2514	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2515	if (PdeSrc.n.u1Present)
2516	{
2517	/*
2518	* Allocate & map the page table.
2519	*/
2520	PSHWPT pPTDst;
2521	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2522	const bool fPageTable = !PdeSrc.b.u1Size;
2523	# else
2524	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2525	# endif
2526	PPGMPOOLPAGE pShwPage;
2527	RTGCPHYS GCPhys;
2528	if (fPageTable)
2529	{
2530	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2531	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2532	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2533	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2534	# endif
2535	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2536	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2537	# else
2538	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2539	# endif
2540	}
2541	else
2542	{
2543	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2544	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2545	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2546	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2547	# endif
2548	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2549	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2550	# else
2551	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2552	# endif
2553	}
2554	if (rc == VINF_SUCCESS)
2555	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2556	else if (rc == VINF_PGM_CACHED_PAGE)
2557	{
2558	/*
2559	* The PT was cached, just hook it up.
2560	*/
2561	if (fPageTable)
2562	PdeDst.u = pShwPage->Core.Key
2563	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2564	else
2565	{
2566	PdeDst.u = pShwPage->Core.Key
2567	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2568	/* (see explanation and assumptions further down.) */
2569	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2570	{
2571	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2572	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2573	PdeDst.b.u1Write = 0;
2574	}
2575	}
2576	*pPdeDst = PdeDst;
2577	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2578	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2579	# endif
2580	return VINF_SUCCESS;
2581	}
2582	else if (rc == VERR_PGM_POOL_FLUSHED)
2583	{
2584	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2585	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2586	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2587	# endif
2588	return VINF_PGM_SYNC_CR3;
2589	}
2590	else
2591	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2592	PdeDst.u &= X86_PDE_AVL_MASK;
2593	PdeDst.u \|= pShwPage->Core.Key;
2594
2595	/*
2596	* Page directory has been accessed (this is a fault situation, remember).
2597	*/
2598	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2599	if (fPageTable)
2600	{
2601	/*
2602	* Page table - 4KB.
2603	*
2604	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2605	*/
2606	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2607	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2608	PGSTPT pPTSrc;
2609	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2610	if (RT_SUCCESS(rc))
2611	{
2612	/*
2613	* Start by syncing the page directory entry so CSAM's TLB trick works.
2614	*/
2615	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2616	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2617	*pPdeDst = PdeDst;
2618	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2619	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2620	# endif
2621
2622	/*
2623	* Directory/page user or supervisor privilege: (same goes for read/write)
2624	*
2625	* Directory Page Combined
2626	* U/S U/S U/S
2627	* 0 0 0
2628	* 0 1 0
2629	* 1 0 0
2630	* 1 1 1
2631	*
2632	* Simple AND operation. Table listed for completeness.
2633	*
2634	*/
2635	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2636	# ifdef PGM_SYNC_N_PAGES
2637	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2638	unsigned iPTDst = iPTBase;
2639	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2640	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2641	iPTDst = 0;
2642	else
2643	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2644	# else /* !PGM_SYNC_N_PAGES */
2645	unsigned iPTDst = 0;
2646	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2647	# endif /* !PGM_SYNC_N_PAGES */
2648	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2649	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2650	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2651	# else
2652	const unsigned offPTSrc = 0;
2653	# endif
2654	for (; iPTDst < iPTDstEnd; iPTDst++)
2655	{
2656	const unsigned iPTSrc = iPTDst + offPTSrc;
2657	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2658
2659	if (PteSrc.n.u1Present) /* we've already cleared it above */
2660	{
2661	# ifndef IN_RING0
2662	/*
2663	* Assuming kernel code will be marked as supervisor - and not as user level
2664	* and executed using a conforming code selector - And marked as readonly.
2665	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2666	*/
2667	PPGMPAGE pPage;
2668	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2669	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2670	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2671	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2672	)
2673	# endif
2674	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2675	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2676	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2677	PteSrc.n.u1Present,
2678	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2679	PteSrc.n.u1User & PdeSrc.n.u1User,
2680	(uint64_t)PteSrc.u,
2681	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2682	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2683	}
2684	} /* for PTEs */
2685	}
2686	}
2687	else
2688	{
2689	/*
2690	* Big page - 2/4MB.
2691	*
2692	* We'll walk the ram range list in parallel and optimize lookups.
2693	* We will only sync on shadow page table at a time.
2694	*/
2695	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2696
2697	/**
2698	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2699	*/
2700
2701	/*
2702	* Start by syncing the page directory entry.
2703	*/
2704	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2705	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2706
2707	/*
2708	* If the page is not flagged as dirty and is writable, then make it read-only
2709	* at PD level, so we can set the dirty bit when the page is modified.
2710	*
2711	* ASSUMES that page access handlers are implemented on page table entry level.
2712	* Thus we will first catch the dirty access and set PDE.D and restart. If
2713	* there is an access handler, we'll trap again and let it work on the problem.
2714	*/
2715	/** @todo move the above stuff to a section in the PGM documentation. */
2716	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2717	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2718	{
2719	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2720	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2721	PdeDst.b.u1Write = 0;
2722	}
2723	*pPdeDst = PdeDst;
2724	# if defined(IN_RC) && defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2725	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2726	# endif
2727
2728	/*
2729	* Fill the shadow page table.
2730	*/
2731	/* Get address and flags from the source PDE. */
2732	SHWPTE PteDstBase;
2733	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2734
2735	/* Loop thru the entries in the shadow PT. */
2736	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2737	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2738	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2739	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2740	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2741	unsigned iPTDst = 0;
2742	while (iPTDst < RT_ELEMENTS(pPTDst->a))
2743	{
2744	/* Advance ram range list. */
2745	while (pRam && GCPhys > pRam->GCPhysLast)
2746	pRam = pRam->CTX_SUFF(pNext);
2747	if (pRam && GCPhys >= pRam->GCPhys)
2748	{
2749	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2750	do
2751	{
2752	/* Make shadow PTE. */
2753	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2754	SHWPTE PteDst;
2755
2756	# ifdef VBOX_WITH_NEW_PHYS_CODE
2757	/* Try make the page writable if necessary. */
2758	if ( PteDstBase.n.u1Write
2759	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2760	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2761	{
2762	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2763	AssertRCReturn(rc, rc);
2764	}
2765	# else /* !VBOX_WITH_NEW_PHYS_CODE */
2766	/* Make sure the RAM has already been allocated. */
2767	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2768	{
2769	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2770	{
2771	# ifdef IN_RING3
2772	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2773	# else
2774	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2775	# endif
2776	if (rc != VINF_SUCCESS)
2777	return rc;
2778	}
2779	}
2780	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
2781
2782	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2783	{
2784	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2785	{
2786	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2787	PteDst.n.u1Write = 0;
2788	}
2789	else
2790	PteDst.u = 0;
2791	}
2792	# ifndef IN_RING0
2793	/*
2794	* Assuming kernel code will be marked as supervisor and not as user level and executed
2795	* using a conforming code selector. Don't check for readonly, as that implies the whole
2796	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2797	*/
2798	else if ( !PdeSrc.n.u1User
2799	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2800	PteDst.u = 0;
2801	# endif
2802	else
2803	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2804
2805	# ifdef VBOX_WITH_NEW_PHYS_CODE
2806	/* Only map writable pages writable. */
2807	if ( PteDst.n.u1Write
2808	&& PteDst.n.u1Present
2809	&& !PGMPAGETYPE_IS_WRITEABLE(PGM_PAGE_GET_TYPE(pPage)))
2810	PteDst.n.u1Write = 0;
2811	# endif
2812
2813	# ifdef PGMPOOL_WITH_USER_TRACKING
2814	if (PteDst.n.u1Present)
2815	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2816	# endif
2817	/* commit it */
2818	pPTDst->a[iPTDst] = PteDst;
2819	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2820	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2821	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2822
2823	/* advance */
2824	GCPhys += PAGE_SIZE;
2825	iHCPage++;
2826	iPTDst++;
2827	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2828	&& GCPhys <= pRam->GCPhysLast);
2829	}
2830	else if (pRam)
2831	{
2832	Log(("Invalid pages at %RGp\n", GCPhys));
2833	do
2834	{
2835	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2836	GCPhys += PAGE_SIZE;
2837	iPTDst++;
2838	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2839	&& GCPhys < pRam->GCPhys);
2840	}
2841	else
2842	{
2843	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2844	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2845	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2846	}
2847	} /* while more PTEs */
2848	} /* 4KB / 4MB */
2849	}
2850	else
2851	AssertRelease(!PdeDst.n.u1Present);
2852
2853	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2854	if (RT_FAILURE(rc))
2855	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2856	return rc;
2857
2858	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2859	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2860	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
2861
2862
2863	/*
2864	* Validate input a little bit.
2865	*/
2866	int rc = VINF_SUCCESS;
2867	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2868	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2869	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2870
2871	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2872	/* Fetch the pgm pool shadow descriptor. */
2873	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2874	Assert(pShwPde);
2875	# endif
2876
2877	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2878	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2879	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2880	PPGMPOOLPAGE pShwPde;
2881	PX86PDPAE pPDDst;
2882	PSHWPDE pPdeDst;
2883
2884	/* Fetch the pgm pool shadow descriptor. */
2885	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2886	AssertRCSuccessReturn(rc, rc);
2887	Assert(pShwPde);
2888
2889	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2890	pPdeDst = &pPDDst->a[iPDDst];
2891	# else
2892	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) /& SHW_PD_MASK - only pool index atm!/;
2893	PX86PDEPAE pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
2894	# endif
2895
2896	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2897	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2898	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2899	PX86PDPAE pPDDst;
2900	PX86PDPT pPdptDst;
2901	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2902	AssertRCSuccessReturn(rc, rc);
2903	Assert(pPDDst);
2904	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2905
2906	/* Fetch the pgm pool shadow descriptor. */
2907	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2908	Assert(pShwPde);
2909
2910	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2911	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2912	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2913	PEPTPD pPDDst;
2914	PEPTPDPT pPdptDst;
2915
2916	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2917	if (rc != VINF_SUCCESS)
2918	{
2919	AssertRC(rc);
2920	return rc;
2921	}
2922	Assert(pPDDst);
2923	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2924
2925	/* Fetch the pgm pool shadow descriptor. */
2926	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2927	Assert(pShwPde);
2928	# endif
2929	SHWPDE PdeDst = *pPdeDst;
2930
2931	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2932	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2933
2934	GSTPDE PdeSrc;
2935	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2936	PdeSrc.n.u1Present = 1;
2937	PdeSrc.n.u1Write = 1;
2938	PdeSrc.n.u1Accessed = 1;
2939	PdeSrc.n.u1User = 1;
2940
2941	/*
2942	* Allocate & map the page table.
2943	*/
2944	PSHWPT pPTDst;
2945	PPGMPOOLPAGE pShwPage;
2946	RTGCPHYS GCPhys;
2947
2948	/* Virtual address = physical address */
2949	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2950	# if PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_EPT \|\| defined(VBOX_WITH_PGMPOOL_PAGING_ONLY)
2951	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2952	# else
2953	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2954	# endif
2955
2956	if ( rc == VINF_SUCCESS
2957	\|\| rc == VINF_PGM_CACHED_PAGE)
2958	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2959	else
2960	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2961
2962	PdeDst.u &= X86_PDE_AVL_MASK;
2963	PdeDst.u \|= pShwPage->Core.Key;
2964	PdeDst.n.u1Present = 1;
2965	PdeDst.n.u1Write = 1;
2966	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2967	PdeDst.n.u1Execute = 1;
2968	# else
2969	PdeDst.n.u1User = 1;
2970	PdeDst.n.u1Accessed = 1;
2971	# endif
2972	*pPdeDst = PdeDst;
2973
2974	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2975	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2976	return rc;
2977
2978	#else
2979	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2980	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2981	return VERR_INTERNAL_ERROR;
2982	#endif
2983	}
2984
2985
2986
2987	/**
2988	* Prefetch a page/set of pages.
2989	*
2990	* Typically used to sync commonly used pages before entering raw mode
2991	* after a CR3 reload.
2992	*
2993	* @returns VBox status code.
2994	* @param pVM VM handle.
2995	* @param GCPtrPage Page to invalidate.
2996	*/
2997	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2998	{
2999	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3000	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3001	/*
3002	* Check that all Guest levels thru the PDE are present, getting the
3003	* PD and PDE in the processes.
3004	*/
3005	int rc = VINF_SUCCESS;
3006	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3007	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3008	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3009	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3010	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3011	unsigned iPDSrc;
3012	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3013	X86PDPE PdpeSrc;
3014	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3015	# else
3016	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
3017	# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
3018	if (!pPDSrc)
3019	return VINF_SUCCESS; /* not present */
3020	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3021	unsigned iPDSrc;
3022	PX86PML4E pPml4eSrc;
3023	X86PDPE PdpeSrc;
3024	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3025	if (!pPDSrc)
3026	return VINF_SUCCESS; /* not present */
3027	# endif
3028	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3029	# else
3030	PGSTPD pPDSrc = NULL;
3031	const unsigned iPDSrc = 0;
3032	GSTPDE PdeSrc;
3033
3034	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3035	PdeSrc.n.u1Present = 1;
3036	PdeSrc.n.u1Write = 1;
3037	PdeSrc.n.u1Accessed = 1;
3038	PdeSrc.n.u1User = 1;
3039	# endif
3040
3041	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3042	{
3043	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3044	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
3045	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3046	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3047	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3048	PX86PDPAE pPDDst;
3049	X86PDEPAE PdeDst;
3050	# if PGM_GST_TYPE != PGM_TYPE_PAE
3051	X86PDPE PdpeSrc;
3052
3053	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3054	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3055	# endif
3056	int rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
3057	if (rc != VINF_SUCCESS)
3058	{
3059	AssertRC(rc);
3060	return rc;
3061	}
3062	Assert(pPDDst);
3063	PdeDst = pPDDst->a[iPDDst];
3064	# else
3065	const X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
3066	# endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
3067
3068	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3069	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3070	PX86PDPAE pPDDst;
3071	X86PDEPAE PdeDst;
3072
3073	# if PGM_GST_TYPE == PGM_TYPE_PROT
3074	/* AMD-V nested paging */
3075	X86PML4E Pml4eSrc;
3076	X86PDPE PdpeSrc;
3077	PX86PML4E pPml4eSrc = &Pml4eSrc;
3078
3079	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3080	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3081	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3082	# endif
3083
3084	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3085	if (rc != VINF_SUCCESS)
3086	{
3087	AssertRC(rc);
3088	return rc;
3089	}
3090	Assert(pPDDst);
3091	PdeDst = pPDDst->a[iPDDst];
3092	# endif
3093	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3094	{
3095	if (!PdeDst.n.u1Present)
3096	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3097	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3098	else
3099	{
3100	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3101	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3102	* makes no sense to prefetch more than one page.
3103	*/
3104	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3105	if (RT_SUCCESS(rc))
3106	rc = VINF_SUCCESS;
3107	}
3108	}
3109	}
3110	return rc;
3111
3112	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3113	return VINF_SUCCESS; /* ignore */
3114	#endif
3115	}
3116
3117
3118
3119
3120	/**
3121	* Syncs a page during a PGMVerifyAccess() call.
3122	*
3123	* @returns VBox status code (informational included).
3124	* @param GCPtrPage The address of the page to sync.
3125	* @param fPage The effective guest page flags.
3126	* @param uErr The trap error code.
3127	*/
3128	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3129	{
3130	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3131
3132	Assert(!HWACCMIsNestedPagingActive(pVM));
3133	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3134	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3135
3136	# ifndef IN_RING0
3137	if (!(fPage & X86_PTE_US))
3138	{
3139	/*
3140	* Mark this page as safe.
3141	*/
3142	/** @todo not correct for pages that contain both code and data!! */
3143	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3144	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3145	}
3146	# endif
3147
3148	/*
3149	* Get guest PD and index.
3150	*/
3151	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3152	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3153	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3154	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3155	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3156	unsigned iPDSrc;
3157	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3158	X86PDPE PdpeSrc;
3159	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3160	# else
3161	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, NULL);
3162	# endif
3163
3164	if (pPDSrc)
3165	{
3166	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3167	return VINF_EM_RAW_GUEST_TRAP;
3168	}
3169	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3170	unsigned iPDSrc;
3171	PX86PML4E pPml4eSrc;
3172	X86PDPE PdpeSrc;
3173	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3174	if (!pPDSrc)
3175	{
3176	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3177	return VINF_EM_RAW_GUEST_TRAP;
3178	}
3179	# endif
3180	# else
3181	PGSTPD pPDSrc = NULL;
3182	const unsigned iPDSrc = 0;
3183	# endif
3184	int rc = VINF_SUCCESS;
3185
3186	/*
3187	* First check if the shadow pd is present.
3188	*/
3189	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3190	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
3191	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3192	PX86PDEPAE pPdeDst;
3193	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3194	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3195	PX86PDPAE pPDDst;
3196	# if PGM_GST_TYPE != PGM_TYPE_PAE
3197	X86PDPE PdpeSrc;
3198
3199	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3200	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3201	# endif
3202	rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
3203	if (rc != VINF_SUCCESS)
3204	{
3205	AssertRC(rc);
3206	return rc;
3207	}
3208	Assert(pPDDst);
3209	pPdeDst = &pPDDst->a[iPDDst];
3210	# else
3211	pPdeDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrPage);
3212	# endif
3213	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3214	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3215	PX86PDPAE pPDDst;
3216	PX86PDEPAE pPdeDst;
3217
3218	# if PGM_GST_TYPE == PGM_TYPE_PROT
3219	/* AMD-V nested paging */
3220	X86PML4E Pml4eSrc;
3221	X86PDPE PdpeSrc;
3222	PX86PML4E pPml4eSrc = &Pml4eSrc;
3223
3224	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3225	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3226	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3227	# endif
3228
3229	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3230	if (rc != VINF_SUCCESS)
3231	{
3232	AssertRC(rc);
3233	return rc;
3234	}
3235	Assert(pPDDst);
3236	pPdeDst = &pPDDst->a[iPDDst];
3237	# endif
3238	if (!pPdeDst->n.u1Present)
3239	{
3240	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3241	AssertRC(rc);
3242	if (rc != VINF_SUCCESS)
3243	return rc;
3244	}
3245
3246	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3247	/* Check for dirty bit fault */
3248	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3249	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3250	Log(("PGMVerifyAccess: success (dirty)\n"));
3251	else
3252	{
3253	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3254	#else
3255	{
3256	GSTPDE PdeSrc;
3257	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3258	PdeSrc.n.u1Present = 1;
3259	PdeSrc.n.u1Write = 1;
3260	PdeSrc.n.u1Accessed = 1;
3261	PdeSrc.n.u1User = 1;
3262
3263	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3264	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3265	if (uErr & X86_TRAP_PF_US)
3266	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3267	else /* supervisor */
3268	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3269
3270	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3271	if (RT_SUCCESS(rc))
3272	{
3273	/* Page was successfully synced */
3274	Log2(("PGMVerifyAccess: success (sync)\n"));
3275	rc = VINF_SUCCESS;
3276	}
3277	else
3278	{
3279	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3280	return VINF_EM_RAW_GUEST_TRAP;
3281	}
3282	}
3283	return rc;
3284
3285	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3286
3287	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3288	return VERR_INTERNAL_ERROR;
3289	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3290	}
3291
3292
3293	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3294	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3295	/**
3296	* Figures out which kind of shadow page this guest PDE warrants.
3297	*
3298	* @returns Shadow page kind.
3299	* @param pPdeSrc The guest PDE in question.
3300	* @param cr4 The current guest cr4 value.
3301	*/
3302	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3303	{
3304	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3305	if (!pPdeSrc->n.u1Size)
3306	# else
3307	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3308	# endif
3309	return BTH_PGMPOOLKIND_PT_FOR_PT;
3310	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3311	//{
3312	// case 0:
3313	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3314	// case X86_PDE4M_RW:
3315	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3316	// case X86_PDE4M_US:
3317	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3318	// case X86_PDE4M_RW \| X86_PDE4M_US:
3319	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3320	# if 0
3321	// case X86_PDE4M_PAE_NX:
3322	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3323	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3324	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3325	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3326	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3327	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3328	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3329	# endif
3330	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3331	//}
3332	}
3333	# endif
3334	#endif
3335
3336	#undef MY_STAM_COUNTER_INC
3337	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3338
3339
3340	/**
3341	* Syncs the paging hierarchy starting at CR3.
3342	*
3343	* @returns VBox status code, no specials.
3344	* @param pVM The virtual machine.
3345	* @param cr0 Guest context CR0 register
3346	* @param cr3 Guest context CR3 register
3347	* @param cr4 Guest context CR4 register
3348	* @param fGlobal Including global page directories or not
3349	*/
3350	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3351	{
3352	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3353	fGlobal = true; /* Change this CR3 reload to be a global one. */
3354
3355	LogFlow(("SyncCR3 %d\n", fGlobal));
3356
3357	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3358	/*
3359	* Update page access handlers.
3360	* The virtual are always flushed, while the physical are only on demand.
3361	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3362	* have to look into that later because it will have a bad influence on the performance.
3363	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3364	* bird: Yes, but that won't work for aliases.
3365	*/
3366	/** @todo this MUST go away. See #1557. */
3367	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3368	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3369	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3370	#endif
3371
3372	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3373	/*
3374	* Nested / EPT - almost no work.
3375	*/
3376	/** @todo check if this is really necessary; the call does it as well... */
3377	HWACCMFlushTLB(pVM);
3378	return VINF_SUCCESS;
3379
3380	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3381	/*
3382	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3383	* out the shadow parts when the guest modifies its tables.
3384	*/
3385	return VINF_SUCCESS;
3386
3387	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3388
3389	# ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
3390	# ifdef PGM_WITHOUT_MAPPINGS
3391	Assert(pVM->pgm.s.fMappingsFixed);
3392	return VINF_SUCCESS;
3393	# else
3394	/* Nothing to do when mappings are fixed. */
3395	if (pVM->pgm.s.fMappingsFixed)
3396	return VINF_SUCCESS;
3397
3398	int rc = PGMMapResolveConflicts(pVM);
3399	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3400	if (rc == VINF_PGM_SYNC_CR3)
3401	{
3402	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3403	return VINF_PGM_SYNC_CR3;
3404	}
3405	# endif
3406	return VINF_SUCCESS;
3407	# else
3408	/*
3409	* PAE and 32-bit legacy mode (shadow).
3410	* (Guest PAE, 32-bit legacy, protected and real modes.)
3411	*/
3412	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
3413	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Global) : &pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3NotGlobal));
3414
3415	# if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3416	bool const fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3417
3418	/*
3419	* Get page directory addresses.
3420	*/
3421	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3422	PX86PDE pPDEDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, 0);
3423	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
3424	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3425	PX86PDEPAE pPDEDst = NULL;
3426	# endif
3427	# endif
3428
3429	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3430	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3431	Assert(pPDSrc);
3432	# if !defined(IN_RC) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
3433	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == (RTR3PTR)pPDSrc);
3434	# endif
3435	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3436
3437	/*
3438	* Iterate the the CR3 page.
3439	*/
3440	PPGMMAPPING pMapping;
3441	unsigned iPdNoMapping;
3442	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
3443	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3444
3445	/* Only check mappings if they are supposed to be put into the shadow page table. */
3446	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
3447	{
3448	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3449	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
3450	}
3451	else
3452	{
3453	pMapping = 0;
3454	iPdNoMapping = ~0U;
3455	}
3456
3457	# if PGM_GST_TYPE == PGM_TYPE_PAE
3458	for (uint64_t iPdpt = 0; iPdpt < GST_PDPE_ENTRIES; iPdpt++)
3459	{
3460	unsigned iPDSrc;
3461	X86PDPE PdpeSrc;
3462	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT, &iPDSrc, &PdpeSrc);
3463	PX86PDEPAE pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, iPdpt << X86_PDPT_SHIFT);
3464	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3465
3466	if (pPDSrc == NULL)
3467	{
3468	/* PDPE not present */
3469	if (pPdptDst->a[iPdpt].n.u1Present)
3470	{
3471	LogFlow(("SyncCR3: guest PDPE %lld not present; clear shw pdpe\n", iPdpt));
3472	/* for each page directory entry */
3473	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3474	{
3475	if ( pPDEDst[iPD].n.u1Present
3476	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
3477	{
3478	pgmPoolFree(pVM, pPDEDst[iPD].u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdpt * X86_PG_PAE_ENTRIES + iPD);
3479	pPDEDst[iPD].u = 0;
3480	}
3481	}
3482	}
3483	if (!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING))
3484	pPdptDst->a[iPdpt].n.u1Present = 0;
3485	continue;
3486	}
3487	# else /* PGM_GST_TYPE != PGM_TYPE_PAE */
3488	{
3489	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE */
3490	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3491	{
3492	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3493	if ((iPD & 255) == 0) /* Start of new PD. */
3494	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)iPD << GST_PD_SHIFT);
3495	# endif
3496	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3497	Assert(pgmShwGet32BitPDEPtr(&pVM->pgm.s, (uint32_t)iPD << SHW_PD_SHIFT) == pPDEDst);
3498	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3499	# if defined(VBOX_STRICT) && !defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) /* Unfortuantely not reliable with PGMR0DynMap and multiple VMs. */
3500	RTGCPTR GCPtrStrict = (uint32_t)iPD << GST_PD_SHIFT;
3501	# if PGM_GST_TYPE == PGM_TYPE_PAE
3502	GCPtrStrict \|= iPdpt << X86_PDPT_SHIFT;
3503	# endif
3504	AssertMsg(pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict) == pPDEDst, ("%p vs %p (%RGv)\n", pgmShwGetPaePDEPtr(&pVM->pgm.s, GCPtrStrict), pPDEDst, GCPtrStrict));
3505	# endif /* VBOX_STRICT */
3506	# endif
3507	GSTPDE PdeSrc = pPDSrc->a[iPD];
3508	if ( PdeSrc.n.u1Present
3509	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
3510	{
3511	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3512	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3513	&& !defined(PGM_WITHOUT_MAPPINGS)
3514
3515	/*
3516	* Check for conflicts with GC mappings.
3517	*/
3518	# if PGM_GST_TYPE == PGM_TYPE_PAE
3519	if (iPD + iPdpt * X86_PG_PAE_ENTRIES == iPdNoMapping)
3520	# else
3521	if (iPD == iPdNoMapping)
3522	# endif
3523	{
3524	if (pVM->pgm.s.fMappingsFixed)
3525	{
3526	/* It's fixed, just skip the mapping. */
3527	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3528	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3529	iPD += cPTs - 1;
3530	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3531	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3532	# else
3533	pPDEDst += cPTs;
3534	# endif
3535	pMapping = pMapping->CTX_SUFF(pNext);
3536	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3537	continue;
3538	}
3539	# ifdef IN_RING3
3540	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3541	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3542	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3543	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3544	# endif
3545	if (RT_FAILURE(rc))
3546	return rc;
3547
3548	/*
3549	* Update iPdNoMapping and pMapping.
3550	*/
3551	pMapping = pVM->pgm.s.pMappingsR3;
3552	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3553	pMapping = pMapping->pNextR3;
3554	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3555	# else /* !IN_RING3 */
3556	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3557	return VINF_PGM_SYNC_CR3;
3558	# endif /* !IN_RING3 */
3559	}
3560	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3561	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3562	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3563
3564	/*
3565	* Sync page directory entry.
3566	*
3567	* The current approach is to allocated the page table but to set
3568	* the entry to not-present and postpone the page table synching till
3569	* it's actually used.
3570	*/
3571	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3572	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3573	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3574	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
3575	# else
3576	const unsigned iPdShw = iPD; NOREF(iPdShw);
3577	# endif
3578	{
3579	SHWPDE PdeDst = *pPDEDst;
3580	if (PdeDst.n.u1Present)
3581	{
3582	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
3583	RTGCPHYS GCPhys;
3584	if ( !PdeSrc.b.u1Size
3585	\|\| !fBigPagesSupported)
3586	{
3587	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
3588	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3589	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3590	GCPhys \|= i * (PAGE_SIZE / 2);
3591	# endif
3592	}
3593	else
3594	{
3595	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3596	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3597	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
3598	GCPhys \|= i * X86_PAGE_2M_SIZE;
3599	# endif
3600	}
3601
3602	if ( pShwPage->GCPhys == GCPhys
3603	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
3604	&& ( pShwPage->fCached
3605	\|\| ( !fGlobal
3606	&& ( false
3607	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
3608	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3609	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
3610	\|\| ( !pShwPage->fSeenNonGlobal
3611	&& (cr4 & X86_CR4_PGE))
3612	# endif
3613	)
3614	)
3615	)
3616	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
3617	\|\| ( fBigPagesSupported
3618	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
3619	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
3620	)
3621	)
3622	{
3623	# ifdef VBOX_WITH_STATISTICS
3624	if ( !fGlobal
3625	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
3626	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
3627	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPD));
3628	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
3629	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstSkippedGlobalPT));
3630	else
3631	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstCacheHit));
3632	# endif /* VBOX_WITH_STATISTICS */
3633	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
3634	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
3635	//# ifdef PGMPOOL_WITH_CACHE
3636	// pgmPoolCacheUsed(pPool, pShwPage);
3637	//# endif
3638	}
3639	else
3640	{
3641	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
3642	pPDEDst->u = 0;
3643	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreed));
3644	}
3645	}
3646	else
3647	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstNotPresent));
3648
3649	/* advance */
3650	pPDEDst++;
3651	} /* foreach 2MB PAE PDE in 4MB guest PDE */
3652	}
3653	# if PGM_GST_TYPE == PGM_TYPE_PAE
3654	else if (iPD + iPdpt * X86_PG_PAE_ENTRIES != iPdNoMapping)
3655	# else
3656	else if (iPD != iPdNoMapping)
3657	# endif
3658	{
3659	/*
3660	* Check if there is any page directory to mark not present here.
3661	*/
3662	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3663	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
3664	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3665	const unsigned iPdShw = iPD + iPdpt * X86_PG_PAE_ENTRIES;
3666	# else
3667	const unsigned iPdShw = iPD;
3668	# endif
3669	{
3670	if (pPDEDst->n.u1Present)
3671	{
3672	pgmPoolFree(pVM, pPDEDst->u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPdShw);
3673	pPDEDst->u = 0;
3674	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3DstFreedSrcNP));
3675	}
3676	pPDEDst++;
3677	}
3678	}
3679	else
3680	{
3681	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3682	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
3683	&& !defined(PGM_WITHOUT_MAPPINGS)
3684
3685	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
3686
3687	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3688	if (pVM->pgm.s.fMappingsFixed)
3689	{
3690	/* It's fixed, just skip the mapping. */
3691	pMapping = pMapping->CTX_SUFF(pNext);
3692	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3693	}
3694	else
3695	{
3696	/*
3697	* Check for conflicts for subsequent pagetables
3698	* and advance to the next mapping.
3699	*/
3700	iPdNoMapping = ~0U;
3701	unsigned iPT = cPTs;
3702	while (iPT-- > 1)
3703	{
3704	if ( pPDSrc->a[iPD + iPT].n.u1Present
3705	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
3706	{
3707	# ifdef IN_RING3
3708	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3709	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
3710	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3711	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPdpt << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
3712	# endif
3713	if (RT_FAILURE(rc))
3714	return rc;
3715
3716	/*
3717	* Update iPdNoMapping and pMapping.
3718	*/
3719	pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
3720	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
3721	pMapping = pMapping->CTX_SUFF(pNext);
3722	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
3723	break;
3724	# else
3725	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3726	return VINF_PGM_SYNC_CR3;
3727	# endif
3728	}
3729	}
3730	if (iPdNoMapping == ~0U && pMapping)
3731	{
3732	pMapping = pMapping->CTX_SUFF(pNext);
3733	if (pMapping)
3734	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3735	}
3736	}
3737
3738	/* advance. */
3739	Assert(PGM_GST_TYPE == PGM_TYPE_32BIT \|\| (iPD + cPTs - 1) / X86_PG_PAE_ENTRIES == iPD / X86_PG_PAE_ENTRIES);
3740	iPD += cPTs - 1;
3741	# if PGM_SHW_TYPE != PGM_GST_TYPE /* SHW==PAE && GST==32BIT */
3742	pPDEDst = pgmShwGetPaePDEPtr(&pVM->pgm.s, (uint32_t)(iPD + 1) << GST_PD_SHIFT);
3743	# else
3744	pPDEDst += cPTs;
3745	# endif
3746	# if PGM_GST_TYPE != PGM_SHW_TYPE
3747	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3748	# endif
3749	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3750	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3751	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3752	}
3753
3754	} /* for iPD */
3755	} /* for each PDPTE (PAE) */
3756	return VINF_SUCCESS;
3757
3758	# else /* guest real and protected mode */
3759	return VINF_SUCCESS;
3760	# endif
3761	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
3762	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3763	}
3764
3765
3766
3767
3768	#ifdef VBOX_STRICT
3769	#ifdef IN_RC
3770	# undef AssertMsgFailed
3771	# define AssertMsgFailed Log
3772	#endif
3773	#ifdef IN_RING3
3774	# include <VBox/dbgf.h>
3775
3776	/**
3777	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3778	*
3779	* @returns VBox status code (VINF_SUCCESS).
3780	* @param pVM The VM handle.
3781	* @param cr3 The root of the hierarchy.
3782	* @param crr The cr4, only PAE and PSE is currently used.
3783	* @param fLongMode Set if long mode, false if not long mode.
3784	* @param cMaxDepth Number of levels to dump.
3785	* @param pHlp Pointer to the output functions.
3786	*/
3787	__BEGIN_DECLS
3788	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3789	__END_DECLS
3790
3791	#endif
3792
3793	/**
3794	* Checks that the shadow page table is in sync with the guest one.
3795	*
3796	* @returns The number of errors.
3797	* @param pVM The virtual machine.
3798	* @param cr3 Guest context CR3 register
3799	* @param cr4 Guest context CR4 register
3800	* @param GCPtr Where to start. Defaults to 0.
3801	* @param cb How much to check. Defaults to everything.
3802	*/
3803	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3804	{
3805	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3806	return 0;
3807	#else
3808	unsigned cErrors = 0;
3809
3810	#if PGM_GST_TYPE == PGM_TYPE_PAE
3811	/** @todo currently broken; crashes below somewhere */
3812	AssertFailed();
3813	#endif
3814
3815	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3816	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3817	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3818
3819	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3820	bool fBigPagesSupported = true;
3821	# else
3822	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3823	# endif
3824	PPGM pPGM = &pVM->pgm.s;
3825	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3826	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3827	# ifndef IN_RING0
3828	RTHCPHYS HCPhys; /* general usage. */
3829	# endif
3830	int rc;
3831
3832	/*
3833	* Check that the Guest CR3 and all its mappings are correct.
3834	*/
3835	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3836	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3837	false);
3838	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3839	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3840	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3841	# else
3842	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3843	# endif
3844	AssertRCReturn(rc, 1);
3845	HCPhys = NIL_RTHCPHYS;
3846	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3847	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3848	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3849	RTGCPHYS GCPhys;
3850	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3851	AssertRCReturn(rc, 1);
3852	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3853	# endif
3854	# endif /* !IN_RING0 */
3855
3856	/*
3857	* Get and check the Shadow CR3.
3858	*/
3859	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3860	unsigned cPDEs = X86_PG_ENTRIES;
3861	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3862	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3863	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3864	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3865	# else
3866	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3867	# endif
3868	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3869	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3870	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3871	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3872	# endif
3873	if (cb != ~(RTGCPTR)0)
3874	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3875
3876	/** @todo call the other two PGMAssert() functions. /
3877
3878	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3879	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3880	# endif
3881
3882	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3883	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3884
3885	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3886	{
3887	PPGMPOOLPAGE pShwPdpt = NULL;
3888	PX86PML4E pPml4eSrc;
3889	PX86PML4E pPml4eDst;
3890	RTGCPHYS GCPhysPdptSrc;
3891
3892	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3893	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3894
3895	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3896	if (!pPml4eDst->n.u1Present)
3897	{
3898	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3899	continue;
3900	}
3901
3902	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3903	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3904
3905	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3906	{
3907	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3908	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3909	cErrors++;
3910	continue;
3911	}
3912
3913	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3914	{
3915	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3916	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3917	cErrors++;
3918	continue;
3919	}
3920
3921	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3922	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3923	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3924	{
3925	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3926	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3927	cErrors++;
3928	continue;
3929	}
3930	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3931	{
3932	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3933
3934	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3935	/*
3936	* Check the PDPTEs too.
3937	*/
3938	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3939
3940	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3941	{
3942	unsigned iPDSrc;
3943	PPGMPOOLPAGE pShwPde = NULL;
3944	PX86PDPE pPdpeDst;
3945	RTGCPHYS GCPhysPdeSrc;
3946	# if PGM_GST_TYPE == PGM_TYPE_PAE
3947	X86PDPE PdpeSrc;
3948	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3949	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3950	# else
3951	PX86PML4E pPml4eSrc;
3952	X86PDPE PdpeSrc;
3953	PX86PDPT pPdptDst;
3954	PX86PDPAE pPDDst;
3955	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3956
3957	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3958	if (rc != VINF_SUCCESS)
3959	{
3960	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3961	GCPtr += 512 * _2M;
3962	continue; /* next PDPTE */
3963	}
3964	Assert(pPDDst);
3965	# endif
3966	Assert(iPDSrc == 0);
3967
3968	pPdpeDst = &pPdptDst->a[iPdpt];
3969
3970	if (!pPdpeDst->n.u1Present)
3971	{
3972	GCPtr += 512 * _2M;
3973	continue; /* next PDPTE */
3974	}
3975
3976	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3977	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3978
3979	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3980	{
3981	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3982	GCPtr += 512 * _2M;
3983	cErrors++;
3984	continue;
3985	}
3986
3987	if (GCPhysPdeSrc != pShwPde->GCPhys)
3988	{
3989	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3990	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3991	# else
3992	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3993	# endif
3994	GCPtr += 512 * _2M;
3995	cErrors++;
3996	continue;
3997	}
3998
3999	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4000	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
4001	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
4002	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
4003	{
4004	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4005	GCPtr += 512 * _2M;
4006	cErrors++;
4007	continue;
4008	}
4009	# endif
4010
4011	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4012	{
4013	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4014	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4015	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
4016	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4017	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
4018	# endif
4019	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4020	/*
4021	* Iterate the shadow page directory.
4022	*/
4023	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4024	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4025
4026	for (;
4027	iPDDst < cPDEs;
4028	iPDDst++, GCPtr += cIncrement)
4029	{
4030	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4031	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
4032	# else
4033	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4034	# endif
4035	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4036	{
4037	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
4038	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4039	{
4040	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4041	cErrors++;
4042	continue;
4043	}
4044	}
4045	else if ( (PdeDst.u & X86_PDE_P)
4046	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4047	)
4048	{
4049	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4050	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
4051	if (!pPoolPage)
4052	{
4053	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4054	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4055	cErrors++;
4056	continue;
4057	}
4058	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
4059
4060	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4061	{
4062	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4063	GCPtr, (uint64_t)PdeDst.u));
4064	cErrors++;
4065	}
4066
4067	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4068	{
4069	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4070	GCPtr, (uint64_t)PdeDst.u));
4071	cErrors++;
4072	}
4073
4074	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4075	if (!PdeSrc.n.u1Present)
4076	{
4077	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4078	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4079	cErrors++;
4080	continue;
4081	}
4082
4083	if ( !PdeSrc.b.u1Size
4084	\|\| !fBigPagesSupported)
4085	{
4086	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
4087	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4088	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
4089	# endif
4090	}
4091	else
4092	{
4093	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4094	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4095	{
4096	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4097	GCPtr, (uint64_t)PdeSrc.u));
4098	cErrors++;
4099	continue;
4100	}
4101	# endif
4102	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
4103	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4104	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
4105	# endif
4106	}
4107
4108	if ( pPoolPage->enmKind
4109	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4110	{
4111	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4112	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4113	cErrors++;
4114	}
4115
4116	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4117	if (!pPhysPage)
4118	{
4119	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4120	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4121	cErrors++;
4122	continue;
4123	}
4124
4125	if (GCPhysGst != pPoolPage->GCPhys)
4126	{
4127	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4128	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4129	cErrors++;
4130	continue;
4131	}
4132
4133	if ( !PdeSrc.b.u1Size
4134	\|\| !fBigPagesSupported)
4135	{
4136	/*
4137	* Page Table.
4138	*/
4139	const GSTPT *pPTSrc;
4140	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
4141	if (RT_FAILURE(rc))
4142	{
4143	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4144	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4145	cErrors++;
4146	continue;
4147	}
4148	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4149	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4150	{
4151	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4152	// (This problem will go away when/if we shadow multiple CR3s.)
4153	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4154	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4155	cErrors++;
4156	continue;
4157	}
4158	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4159	{
4160	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4161	GCPtr, (uint64_t)PdeDst.u));
4162	cErrors++;
4163	continue;
4164	}
4165
4166	/* iterate the page table. */
4167	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4168	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4169	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4170	# else
4171	const unsigned offPTSrc = 0;
4172	# endif
4173	for (unsigned iPT = 0, off = 0;
4174	iPT < RT_ELEMENTS(pPTDst->a);
4175	iPT++, off += PAGE_SIZE)
4176	{
4177	const SHWPTE PteDst = pPTDst->a[iPT];
4178
4179	/* skip not-present entries. */
4180	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4181	continue;
4182	Assert(PteDst.n.u1Present);
4183
4184	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4185	if (!PteSrc.n.u1Present)
4186	{
4187	# ifdef IN_RING3
4188	PGMAssertHandlerAndFlagsInSync(pVM);
4189	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4190	# endif
4191	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4192	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4193	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4194	cErrors++;
4195	continue;
4196	}
4197
4198	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4199	# if 1 /** @todo sync accessed bit properly... */
4200	fIgnoreFlags \|= X86_PTE_A;
4201	# endif
4202
4203	/* match the physical addresses */
4204	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4205	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4206
4207	# ifdef IN_RING3
4208	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4209	if (RT_FAILURE(rc))
4210	{
4211	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4212	{
4213	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4214	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4215	cErrors++;
4216	continue;
4217	}
4218	}
4219	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4220	{
4221	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4222	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4223	cErrors++;
4224	continue;
4225	}
4226	# endif
4227
4228	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4229	if (!pPhysPage)
4230	{
4231	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4232	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4233	{
4234	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4235	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4236	cErrors++;
4237	continue;
4238	}
4239	# endif
4240	if (PteDst.n.u1Write)
4241	{
4242	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4243	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4244	cErrors++;
4245	}
4246	fIgnoreFlags \|= X86_PTE_RW;
4247	}
4248	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4249	{
4250	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4251	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4252	cErrors++;
4253	continue;
4254	}
4255
4256	/* flags */
4257	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4258	{
4259	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4260	{
4261	if (PteDst.n.u1Write)
4262	{
4263	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4264	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4265	cErrors++;
4266	continue;
4267	}
4268	fIgnoreFlags \|= X86_PTE_RW;
4269	}
4270	else
4271	{
4272	if (PteDst.n.u1Present)
4273	{
4274	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4275	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4276	cErrors++;
4277	continue;
4278	}
4279	fIgnoreFlags \|= X86_PTE_P;
4280	}
4281	}
4282	else
4283	{
4284	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4285	{
4286	if (PteDst.n.u1Write)
4287	{
4288	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4289	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4290	cErrors++;
4291	continue;
4292	}
4293	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4294	{
4295	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4296	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4297	cErrors++;
4298	continue;
4299	}
4300	if (PteDst.n.u1Dirty)
4301	{
4302	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4303	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4304	cErrors++;
4305	}
4306	# if 0 /** @todo sync access bit properly... */
4307	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4308	{
4309	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4310	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4311	cErrors++;
4312	}
4313	fIgnoreFlags \|= X86_PTE_RW;
4314	# else
4315	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4316	# endif
4317	}
4318	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4319	{
4320	/* access bit emulation (not implemented). */
4321	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4322	{
4323	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4324	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4325	cErrors++;
4326	continue;
4327	}
4328	if (!PteDst.n.u1Accessed)
4329	{
4330	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4331	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4332	cErrors++;
4333	}
4334	fIgnoreFlags \|= X86_PTE_P;
4335	}
4336	# ifdef DEBUG_sandervl
4337	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4338	# endif
4339	}
4340
4341	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4342	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4343	)
4344	{
4345	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4346	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4347	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4348	cErrors++;
4349	continue;
4350	}
4351	} /* foreach PTE */
4352	}
4353	else
4354	{
4355	/*
4356	* Big Page.
4357	*/
4358	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4359	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4360	{
4361	if (PdeDst.n.u1Write)
4362	{
4363	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4364	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4365	cErrors++;
4366	continue;
4367	}
4368	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4369	{
4370	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4371	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4372	cErrors++;
4373	continue;
4374	}
4375	# if 0 /** @todo sync access bit properly... */
4376	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4377	{
4378	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4379	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4380	cErrors++;
4381	}
4382	fIgnoreFlags \|= X86_PTE_RW;
4383	# else
4384	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4385	# endif
4386	}
4387	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4388	{
4389	/* access bit emulation (not implemented). */
4390	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4391	{
4392	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4393	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4394	cErrors++;
4395	continue;
4396	}
4397	if (!PdeDst.n.u1Accessed)
4398	{
4399	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4400	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4401	cErrors++;
4402	}
4403	fIgnoreFlags \|= X86_PTE_P;
4404	}
4405
4406	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4407	{
4408	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4409	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4410	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4411	cErrors++;
4412	}
4413
4414	/* iterate the page table. */
4415	for (unsigned iPT = 0, off = 0;
4416	iPT < RT_ELEMENTS(pPTDst->a);
4417	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4418	{
4419	const SHWPTE PteDst = pPTDst->a[iPT];
4420
4421	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4422	{
4423	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4424	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4425	cErrors++;
4426	}
4427
4428	/* skip not-present entries. */
4429	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4430	continue;
4431
4432	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4433
4434	/* match the physical addresses */
4435	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4436
4437	# ifdef IN_RING3
4438	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4439	if (RT_FAILURE(rc))
4440	{
4441	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4442	{
4443	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4444	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4445	cErrors++;
4446	}
4447	}
4448	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4449	{
4450	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4451	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4452	cErrors++;
4453	continue;
4454	}
4455	# endif
4456	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4457	if (!pPhysPage)
4458	{
4459	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4460	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4461	{
4462	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4463	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4464	cErrors++;
4465	continue;
4466	}
4467	# endif
4468	if (PteDst.n.u1Write)
4469	{
4470	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4471	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4472	cErrors++;
4473	}
4474	fIgnoreFlags \|= X86_PTE_RW;
4475	}
4476	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4477	{
4478	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4479	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4480	cErrors++;
4481	continue;
4482	}
4483
4484	/* flags */
4485	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4486	{
4487	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4488	{
4489	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4490	{
4491	if (PteDst.n.u1Write)
4492	{
4493	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4494	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4495	cErrors++;
4496	continue;
4497	}
4498	fIgnoreFlags \|= X86_PTE_RW;
4499	}
4500	}
4501	else
4502	{
4503	if (PteDst.n.u1Present)
4504	{
4505	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4506	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4507	cErrors++;
4508	continue;
4509	}
4510	fIgnoreFlags \|= X86_PTE_P;
4511	}
4512	}
4513
4514	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4515	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4516	)
4517	{
4518	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4519	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4520	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4521	cErrors++;
4522	continue;
4523	}
4524	} /* for each PTE */
4525	}
4526	}
4527	/* not present */
4528
4529	} /* for each PDE */
4530
4531	} /* for each PDPTE */
4532
4533	} /* for each PML4E */
4534
4535	# ifdef DEBUG
4536	if (cErrors)
4537	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4538	# endif
4539
4540	#endif /* GST == 32BIT, PAE or AMD64 */
4541	return cErrors;
4542
4543	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4544	}
4545	#endif /* VBOX_STRICT */
4546
4547
4548	/**
4549	* Sets up the CR3 for shadow paging
4550	*
4551	* @returns Strict VBox status code.
4552	* @retval VINF_SUCCESS.
4553	*
4554	* @param pVM VM handle.
4555	* @param GCPhysCR3 The physical address in the CR3 register.
4556	*/
4557	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
4558	{
4559	/* Update guest paging info. */
4560	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4561	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4562	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4563
4564	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4565
4566	/*
4567	* Map the page CR3 points at.
4568	*/
4569	RTHCPTR HCPtrGuestCR3;
4570	RTHCPHYS HCPhysGuestCR3;
4571	# ifdef VBOX_WITH_NEW_PHYS_CODE
4572	/** @todo this needs some reworking. current code is just a big hack. */
4573	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4574	AssertFailedReturn(VERR_INTERNAL_ERROR);
4575	int rc = VERR_INTERNAL_ERROR;
4576	# else
4577	pgmLock(pVM);
4578	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4579	AssertReturn(pPage, VERR_INTERNAL_ERROR);
4580	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4581	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4582	pgmUnlock(pVM);
4583	# endif
4584	# else /* !VBOX_WITH_NEW_PHYS_CODE */
4585	int rc = pgmRamGCPhys2HCPtrAndHCPhys(&pVM->pgm.s, GCPhysCR3 & GST_CR3_PAGE_MASK, &HCPtrGuestCR3, &HCPhysGuestCR3);
4586	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
4587	if (RT_SUCCESS(rc))
4588	{
4589	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4590	if (RT_SUCCESS(rc))
4591	{
4592	# ifdef IN_RC
4593	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4594	# endif
4595	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4596	pVM->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4597	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4598	pVM->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4599	# endif
4600	pVM->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4601
4602	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4603	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4604	pVM->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4605	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4606	pVM->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4607	# endif
4608	pVM->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4609	Log(("Cached mapping %RRv\n", pVM->pgm.s.pGstPaePdptRC));
4610
4611	/*
4612	* Map the 4 PDs too.
4613	*/
4614	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
4615	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4616	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4617	{
4618	if (pGuestPDPT->a[i].n.u1Present)
4619	{
4620	RTHCPTR HCPtr;
4621	RTHCPHYS HCPhys;
4622	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4623	# ifdef VBOX_WITH_NEW_PHYS_CODE
4624	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4625	AssertFailedReturn(VERR_INTERNAL_ERROR);
4626	int rc2 = VERR_INTERNAL_ERROR;
4627	# else
4628	pgmLock(pVM);
4629	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4630	AssertReturn(pPage, VERR_INTERNAL_ERROR);
4631	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4632	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4633	pgmUnlock(pVM);
4634	# endif
4635	# else /* !VBOX_WITH_NEW_PHYS_CODE */
4636	int rc2 = pgmRamGCPhys2HCPtrAndHCPhys(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
4637	# endif /* !VBOX_WITH_NEW_PHYS_CODE */
4638	if (RT_SUCCESS(rc2))
4639	{
4640	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4641	AssertRCReturn(rc, rc);
4642
4643	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4644	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4645	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4646	# endif
4647	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4648	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4649	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
4650	continue;
4651	}
4652	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4653	}
4654
4655	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4656	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4657	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4658	# endif
4659	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4660	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4661	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4662	}
4663
4664	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4665	pVM->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4666	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4667	pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4668	# endif
4669	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
4670	if (!HWACCMIsNestedPagingActive(pVM))
4671	{
4672	/*
4673	* Update the shadow root page as well since that's not fixed.
4674	*/
4675	/** @todo Move this into PGMAllBth.h. */
4676	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4677	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4678	{
4679	/* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
4680	/** @todo Coordinate this better with the pool. */
4681	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
4682	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
4683	pVM->pgm.s.pShwPageCR3R3 = 0;
4684	pVM->pgm.s.pShwPageCR3R0 = 0;
4685	pVM->pgm.s.pShwRootR3 = 0;
4686	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4687	pVM->pgm.s.pShwRootR0 = 0;
4688	# endif
4689	pVM->pgm.s.HCPhysShwCR3 = 0;
4690	}
4691
4692	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4693	rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4694	if (rc == VERR_PGM_POOL_FLUSHED)
4695	{
4696	Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
4697	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4698	return VINF_PGM_SYNC_CR3;
4699	}
4700	AssertRCReturn(rc, rc);
4701	# ifdef IN_RING0
4702	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4703	# else
4704	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4705	# endif
4706	pVM->pgm.s.pShwRootR3 = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
4707	Assert(pVM->pgm.s.pShwRootR3);
4708	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4709	pVM->pgm.s.pShwRootR0 = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4710	# endif
4711	pVM->pgm.s.HCPhysShwCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
4712	rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
4713	}
4714	# endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
4715	# endif
4716	}
4717	else
4718	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4719	}
4720	else
4721	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4722
4723	#else /* prot/real stub */
4724	int rc = VINF_SUCCESS;
4725	#endif
4726
4727	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
4728	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4729	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4730	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4731	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4732	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4733	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4734
4735	Assert(!HWACCMIsNestedPagingActive(pVM));
4736
4737	/*
4738	* Update the shadow root page as well since that's not fixed.
4739	*/
4740	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4741	PPGMPOOLPAGE pOldShwPageCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
4742	uint32_t iOldShwUserTable = pVM->pgm.s.iShwUserTable;
4743	uint32_t iOldShwUser = pVM->pgm.s.iShwUser;
4744	PPGMPOOLPAGE pNewShwPageCR3;
4745
4746	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4747	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4748	if (rc == VERR_PGM_POOL_FLUSHED)
4749	{
4750	Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
4751	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4752	return VINF_PGM_SYNC_CR3;
4753	}
4754	AssertRCReturn(rc, rc);
4755	rc = VINF_SUCCESS;
4756
4757	/* Mark the page as locked; disallow flushing. */
4758	pgmPoolLockPage(pPool, pNewShwPageCR3);
4759
4760	# ifdef IN_RC
4761	/** NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4762	bool fLog = VMMGCLogDisable(pVM);
4763	# endif
4764
4765	pVM->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4766	pVM->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4767	pVM->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4768	# ifdef IN_RING0
4769	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4770	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4771	# elif defined(IN_RC)
4772	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4773	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4774	# else
4775	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4776	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4777	# endif
4778
4779	# ifndef PGM_WITHOUT_MAPPINGS
4780	/* Apply all hypervisor mappings to the new CR3.
4781	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4782	* make sure we check for conflicts in the new CR3 root.
4783	*/
4784	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4785	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4786	# endif
4787	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4788	AssertRCReturn(rc, rc);
4789	# endif
4790
4791	/* Set the current hypervisor CR3. */
4792	CPUMSetHyperCR3(pVM, PGMGetHyperCR3(pVM));
4793
4794	# ifdef IN_RC
4795	VMMGCLogRestore(pVM, fLog);
4796	# endif
4797
4798	/* Clean up the old CR3 root. */
4799	if (pOldShwPageCR3)
4800	{
4801	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4802	# ifndef PGM_WITHOUT_MAPPINGS
4803	/* Remove the hypervisor mappings from the shadow page table. */
4804	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4805	# endif
4806	/* Mark the page as unlocked; allow flushing again. */
4807	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4808
4809	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4810	}
4811
4812	# endif
4813	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
4814
4815	return rc;
4816	}
4817
4818	/**
4819	* Unmaps the shadow CR3.
4820	*
4821	* @returns VBox status, no specials.
4822	* @param pVM VM handle.
4823	*/
4824	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM)
4825	{
4826	LogFlow(("UnmapCR3\n"));
4827
4828	int rc = VINF_SUCCESS;
4829
4830	/* Update guest paging info. */
4831	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4832	pVM->pgm.s.pGst32BitPdR3 = 0;
4833	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4834	pVM->pgm.s.pGst32BitPdR0 = 0;
4835	#endif
4836	pVM->pgm.s.pGst32BitPdRC = 0;
4837
4838	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4839	pVM->pgm.s.pGstPaePdptR3 = 0;
4840	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4841	pVM->pgm.s.pGstPaePdptR0 = 0;
4842	# endif
4843	pVM->pgm.s.pGstPaePdptRC = 0;
4844	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4845	{
4846	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4847	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4848	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4849	# endif
4850	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4851	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4852	}
4853
4854	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4855	pVM->pgm.s.pGstAmd64Pml4R3 = 0;
4856	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4857	pVM->pgm.s.pGstAmd64Pml4R0 = 0;
4858	# endif
4859	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
4860	if (!HWACCMIsNestedPagingActive(pVM))
4861	{
4862	pVM->pgm.s.pShwRootR3 = 0;
4863	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4864	pVM->pgm.s.pShwRootR0 = 0;
4865	# endif
4866	pVM->pgm.s.HCPhysShwCR3 = 0;
4867	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4868	{
4869	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4870	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), PGMPOOL_IDX_AMD64_CR3, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
4871	pVM->pgm.s.pShwPageCR3R3 = 0;
4872	pVM->pgm.s.pShwPageCR3R0 = 0;
4873	}
4874	}
4875	# endif /* !VBOX_WITH_PGMPOOL_PAGING_ONLY */
4876
4877	#else /* prot/real mode stub */
4878	/* nothing to do */
4879	#endif
4880
4881	#if defined(VBOX_WITH_PGMPOOL_PAGING_ONLY) && !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4882	/* Update shadow paging info. */
4883	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4884	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4885	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4886
4887	# if PGM_GST_TYPE != PGM_TYPE_REAL
4888	Assert(!HWACCMIsNestedPagingActive(pVM));
4889	# endif
4890
4891	# ifndef PGM_WITHOUT_MAPPINGS
4892	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4893	/* Remove the hypervisor mappings from the shadow page table. */
4894	pgmMapDeactivateCR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4895	# endif
4896
4897	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4898	{
4899	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4900
4901	Assert(pVM->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4902
4903	/* Mark the page as unlocked; allow flushing again. */
4904	pgmPoolUnlockPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4905
4906	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.iShwUser, pVM->pgm.s.iShwUserTable);
4907	pVM->pgm.s.pShwPageCR3R3 = 0;
4908	pVM->pgm.s.pShwPageCR3R0 = 0;
4909	pVM->pgm.s.pShwPageCR3RC = 0;
4910	pVM->pgm.s.iShwUser = 0;
4911	pVM->pgm.s.iShwUserTable = 0;
4912	}
4913	# endif
4914	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY && !IN_RC*/
4915
4916	return rc;
4917	}
4918

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 17486

Download in other formats: