PGMAllBth.h@ 1862

Last change on this file since 1862 was 1839, checked in by vboxsync, 18 years ago
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1	/* $Id: PGMAllBth.h 1839 2007-03-30 18:30:16Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006 InnoTek Systemberatung GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License as published by the Free Software Foundation,
15	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16	* distribution. VirtualBox OSE is distributed in the hope that it will
17	* be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* If you received this file as part of a commercial VirtualBox
20	* distribution, then only the terms of your commercial VirtualBox
21	* license agreement apply instead of the previous paragraph.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/**
46	* #PF Handler for raw-mode guest execution.
47	*
48	* @returns VBox status code (appropriate for trap handling and GC return).
49	* @param pVM VM Handle.
50	* @param uErr The trap error code.
51	* @param pRegFrame Trap register frame.
52	* @param pvFault The fault address.
53	*/
54	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
55	{
56	#if PGM_GST_TYPE == PGM_TYPE_32BIT
57	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
58	# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
59	# endif
60
61	# ifdef PGM_CACHE_VERY_STRICT
62	pgmCacheCheckPD(pVM, CPUMGetGuestCR0(pVM), CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
63	# endif
64
65	# if PGM_SHW_TYPE == PGM_TYPE_PAE
66	/*
67	* Hide the instruction fetch trap indicator for now.
68	*/
69	/** @todo NXE will change this and we must fix NXE in the switcher too! */
70	if (uErr & X86_TRAP_PF_ID)
71	{
72	uErr &= ~X86_TRAP_PF_ID;
73	TRPMSetErrorCode(pVM, uErr);
74	}
75	# endif
76
77	/*
78	* Get PDs.
79	*/
80	int rc;
81	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
82	const unsigned iPDSrc = (uintptr_t)pvFault >> GST_PD_SHIFT;
83	const unsigned iPDDst = (uintptr_t)pvFault >> SHW_PD_SHIFT;
84	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
85	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
86	# else /* PAE */
87	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
88	# endif
89
90	/* Determine current privilege level */
91	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
92
93	# ifdef PGM_SYNC_DIRTY_BIT
94	/*
95	* If we successfully correct the write protection fault due to dirty bit
96	* tracking, or this page fault is a genuine one, then return immediately.
97	*/
98	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
99	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
100	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
101	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
102	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
103	{
104	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
105	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
106	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
107	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
108	}
109	# endif
110	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
111
112	/*
113	* A common case is the not-present error caused by lazy page table syncing.
114	*
115	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
116	* so we can safely assume that the shadow PT is present when calling SyncPage later.
117	*
118	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
119	* of mapping conflict and defer to SyncCR3 in R3.
120	* (Again, we do NOT support access handlers for non-present guest pages.)
121	*
122	*/
123	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
124	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
125	&& !pPDDst->a[iPDDst].n.u1Present
126	&& PdeSrc.n.u1Present)
127
128	{
129	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
130	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
131	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
132	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
133	if (VBOX_SUCCESS(rc))
134	{
135	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
136	return rc;
137	}
138	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
139	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
140	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
141	return VINF_PGM_SYNC_CR3;
142	}
143
144	/*
145	* Check if this address is within any of our mappings.
146	*
147	* This is very fast and it's gonna save us a bit of effort below and prevent
148	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
149	* (BTW, it's impossible to have physical access handlers in a mapping.)
150	*/
151	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
152	{
153	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
154	PPGMMAPPING pMapping = CTXSUFF(pVM->pgm.s.pMappings);
155	for ( ; pMapping; pMapping = CTXSUFF(pMapping->pNext))
156	{
157	if ((uintptr_t)pvFault < (uintptr_t)pMapping->GCPtr)
158	break;
159	if ((uintptr_t)pvFault - (uintptr_t)pMapping->GCPtr < pMapping->cb)
160	{
161	/*
162	* The first thing we check is if we've got an undetected conflict.
163	*/
164	if (!pVM->pgm.s.fMappingsFixed)
165	{
166	unsigned iPT = pMapping->cPTs;
167	while (iPT-- > 0)
168	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
169	{
170	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
171	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
172	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
173	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
174	return VINF_PGM_SYNC_CR3;
175	}
176	}
177
178	/*
179	* Check if the fault address is in a virtual page access handler range.
180	*/
181	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
182	if ( pCur
183	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
184	&& (uintptr_t)pvFault - (uintptr_t)pCur->GCPtr < pCur->cb
185	&& ( uErr & X86_TRAP_PF_RW
186	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
187	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** r=bird: <- this is probably wrong. */
188	{
189	#ifdef IN_GC
190	STAM_PROFILE_START(&pCur->Stat, h);
191	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (uintptr_t)pvFault - (uintptr_t)pCur->GCPtr);
192	STAM_PROFILE_STOP(&pCur->Stat, h);
193	#else
194	AssertFailed();
195	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
196	#endif
197	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
198	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
199	return rc;
200	}
201
202	/*
203	* Check if the EIP is in a virtual page access handler range.
204	*/
205	if (cpl == 0)
206	{
207	RTGCPTR pvEIP;
208	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
209	if (VBOX_SUCCESS(rc))
210	{
211	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
212	if ( pCur
213	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
214	&& (uintptr_t)pvEIP - (uintptr_t)pCur->GCPtr < pCur->cb)
215	{
216	#ifdef IN_GC
217	STAM_PROFILE_START(&pCur->Stat, h);
218	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (uintptr_t)pvEIP - (uintptr_t)pCur->GCPtr);
219	STAM_PROFILE_STOP(&pCur->Stat, h);
220	#else
221	AssertFailed();
222	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
223	#endif
224	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
225	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
226	return rc;
227	}
228	}
229	}
230
231	/*
232	* Pretend we're not here and let the guest handle the trap.
233	*/
234	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
235	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
236	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
237	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
238	return VINF_EM_RAW_GUEST_TRAP;
239	}
240	}
241	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
242	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
243
244	/*
245	* Check if this fault address is flagged for special treatment,
246	* which means we'll have to figure out the physical address and
247	* check flags associated with it.
248	*
249	* ASSUME that we can limit any special access handling to pages
250	* in page tables which the guest believes to be present.
251	*/
252	if (PdeSrc.n.u1Present)
253	{
254	RTGCPHYS GCPhys = ~0U;
255	uint32_t cr4 = CPUMGetGuestCR4(pVM);
256	if ( PdeSrc.b.u1Size
257	&& (cr4 & X86_CR4_PSE))
258	GCPhys = (PdeSrc.u & X86_PDE4M_PG_MASK)
259	\| ((RTGCPHYS)pvFault & (PAGE_OFFSET_MASK_BIG ^ PAGE_OFFSET_MASK));
260	else
261	{
262	PVBOXPT pPTSrc;
263	# ifdef IN_GC
264	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & X86_PDE_PG_MASK, (void **)&pPTSrc);
265	# else
266	pPTSrc = (PVBOXPT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & X86_PDE_PG_MASK, sizeof(*pPTSrc));
267	if (pPTSrc == 0)
268	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
269	# endif
270	if (VBOX_SUCCESS(rc))
271	{
272	unsigned iPTESrc = ((uintptr_t)pvFault >> PAGE_SHIFT) & PTE_MASK;
273	if (pPTSrc->a[iPTESrc].n.u1Present)
274	GCPhys = pPTSrc->a[iPTESrc].u & X86_PTE_PG_MASK;
275	}
276	}
277
278	/*
279	* If we have a GC address we'll check if it has any flags set.
280	*/
281	if (GCPhys != ~0U)
282	{
283	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
284
285	RTHCPHYS HCPhys;
286	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPhys);
287	if (VBOX_SUCCESS(rc))
288	{
289	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_HANDLER))
290	{
291	if (HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER)
292	{
293	/*
294	* Physical page access handler.
295	*/
296	const RTGCPHYS GCPhysFault = GCPhys \| ((uintptr_t)pvFault & PAGE_OFFSET_MASK);
297	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
298	if (pCur)
299	{
300	# ifdef PGM_SYNC_N_PAGES
301	/*
302	* If the region is write protected and we got a page not present fault, then sync
303	* the pages. If the fault was caused by a read, then restart the instruction.
304	* In case of write access continue to the GC write handler.
305	*
306	* ASSUMES that there is only one handler per page or that they have similar write properties.
307	*/
308	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
309	&& !(uErr & X86_TRAP_PF_P))
310	{
311	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
312	if ( VBOX_FAILURE(rc)
313	\|\| !(uErr & X86_TRAP_PF_RW)
314	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
315	{
316	AssertRC(rc);
317	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
318	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
319	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
320	return rc;
321	}
322	}
323	# endif
324
325	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
326	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
327	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
328
329	#ifdef IN_GC
330	Assert(CTXSUFF(pCur->pfnHandler));
331	STAM_PROFILE_START(&pCur->Stat, h);
332	rc = pCur->CTXSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXSUFF(pCur->pvUser));
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	#elif IN_RING0
335	if (CTXALLSUFF(pCur->pfnHandler))
336	{
337	STAM_PROFILE_START(&pCur->Stat, h);
338	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
339	STAM_PROFILE_STOP(&pCur->Stat, h);
340	}
341	else
342	rc = VINF_EM_RAW_EMULATE_INSTR;
343	#else
344	rc = VINF_EM_RAW_EMULATE_INSTR;
345	#endif
346	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
347	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
348	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
349	return rc;
350	}
351	}
352	else
353	{
354	# ifdef PGM_SYNC_N_PAGES
355	/*
356	* If the region is write protected and we got a page not present fault, then sync
357	* the pages. If the fault was caused by a read, then restart the instruction.
358	* In case of write access continue to the GC write handler.
359	*/
360	if ( (HCPhys & (MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL)) == MM_RAM_FLAGS_VIRTUAL_WRITE
361	&& !(uErr & X86_TRAP_PF_P))
362	{
363	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
364	if ( VBOX_FAILURE(rc)
365	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
366	\|\| !(uErr & X86_TRAP_PF_RW))
367	{
368	AssertRC(rc);
369	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
370	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
371	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
372	return rc;
373	}
374	}
375	# endif
376	/*
377	* Ok, it's an virtual page access handler.
378	*
379	* Since it's faster to search by address, we'll do that first
380	* and then retry by GCPhys if that fails.
381	*/
382	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
383	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
384	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
385	*/
386	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
387	if (pCur)
388	{
389	AssertMsg(!((uintptr_t)pvFault - (uintptr_t)pCur->GCPtr < pCur->cb)
390	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
391	\|\| !(uErr & X86_TRAP_PF_P)
392	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
393	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
394
395	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
396	&& (uintptr_t)pvFault - (uintptr_t)pCur->GCPtr < pCur->cb
397	&& ( uErr & X86_TRAP_PF_RW
398	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
399	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
400	{
401	#ifdef IN_GC
402	STAM_PROFILE_START(&pCur->Stat, h);
403	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (uintptr_t)pvFault - (uintptr_t)pCur->GCPtr);
404	STAM_PROFILE_STOP(&pCur->Stat, h);
405	#else
406	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
407	#endif
408	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
409	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
410	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
411	return rc;
412	}
413	/* Unhandled part of a monitored page */
414	}
415	else
416	{
417	/* Check by physical address. */
418	PPGMVIRTHANDLER pCur;
419	unsigned iPage;
420	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((uintptr_t)pvFault & PAGE_OFFSET_MASK),
421	&pCur, &iPage);
422	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
423	if ( pCur
424	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
425	&& ( uErr & X86_TRAP_PF_RW
426	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
427	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) )
428	{
429	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
430	#ifdef IN_GC
431	uintptr_t off = (iPage << PAGE_SHIFT) + ((uintptr_t)pvFault & PAGE_OFFSET_MASK) - ((uintptr_t)pCur->GCPtr & PAGE_OFFSET_MASK);
432	Assert(off < pCur->cb);
433	STAM_PROFILE_START(&pCur->Stat, h);
434	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
435	STAM_PROFILE_STOP(&pCur->Stat, h);
436	#else
437	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
438	#endif
439	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
440	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
441	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
442	return rc;
443	}
444	}
445	}
446
447	/*
448	* There is a handled area of the page, but this fault doesn't belong to it.
449	* We must emulate the instruction.
450	*
451	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
452	* we first check if this was a page-not-present fault for a page with only
453	* write access handlers. Restart the instruction if it wasn't a write access.
454	*/
455	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
456
457	if ( !(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL))
458	&& !(uErr & X86_TRAP_PF_P))
459	{
460	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
461	if ( VBOX_FAILURE(rc)
462	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
463	\|\| !(uErr & X86_TRAP_PF_RW))
464	{
465	AssertRC(rc);
466	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
467	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
468	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
469	return rc;
470	}
471	}
472
473	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
474	* It's writing to an unhandled part of the LDT page several million times.
475	*/
476	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
477	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%VHp%s%s\n",
478	rc, HCPhys, HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER ? " phys" : "",
479	HCPhys & MM_RAM_FLAGS_VIRTUAL_HANDLER ? " virt" : ""));
480	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
481	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
482	return rc;
483	} /* if any kind of handler */
484
485	if (uErr & X86_TRAP_PF_P)
486	{
487	/*
488	* The page isn't marked, but it might still be monitored by a virtual page access handler.
489	* (ASSUMES no temporary disabling of virtual handlers.)
490	*/
491	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
492	* we should correct both the shadow page table and physical memory flags, and not only check for
493	* accesses within the handler region but for access to pages with virtual handlers. */
494	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
495	if (pCur)
496	{
497	AssertMsg( !((uintptr_t)pvFault - (uintptr_t)pCur->GCPtr < pCur->cb)
498	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
499	\|\| !(uErr & X86_TRAP_PF_P)
500	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
501	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
502
503	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
504	&& (uintptr_t)pvFault - (uintptr_t)pCur->GCPtr < pCur->cb
505	&& ( uErr & X86_TRAP_PF_RW
506	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
507	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
508	{
509	#ifdef IN_GC
510	STAM_PROFILE_START(&pCur->Stat, h);
511	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (uintptr_t)pvFault - (uintptr_t)pCur->GCPtr);
512	STAM_PROFILE_STOP(&pCur->Stat, h);
513	#else
514	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
515	#endif
516	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
517	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
518	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
519	return rc;
520	}
521	}
522	}
523	}
524	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
525
526	# ifdef PGM_OUT_OF_SYNC_IN_GC
527	/*
528	* We are here only if page is present in Guest page tables and trap is not handled
529	* by our handlers.
530	* Check it for page out-of-sync situation.
531	*/
532	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
533
534	if (!(uErr & X86_TRAP_PF_P))
535	{
536	/*
537	* Page is not present in our page tables.
538	* Try to sync it!
539	* BTW, fPageShw is invalid in this branch!
540	*/
541	if (uErr & X86_TRAP_PF_US)
542	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
543	else /* supervisor */
544	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
545
546	# ifdef LOG_ENABLED
547	RTGCPHYS GCPhys;
548	uint64_t fPageGst;
549	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
550	LogFlow(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp\n",
551	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys));
552	# endif /* LOG_ENABLED */
553
554	# ifndef IN_RING0
555	if (CSAMIsEnabled(pVM) && (cpl == 0))
556	{
557	uint64_t fPageGst;
558	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
559	if ( VBOX_SUCCESS(rc)
560	&& !(fPageGst & X86_PTE_US))
561	{
562	if (pvFault == (RTGCPTR)pRegFrame->eip)
563	{
564	LogFlow(("CSAMExecFault %VGv\n", pvFault));
565	rc = CSAMExecFault(pVM, pvFault);
566	if (rc != VINF_SUCCESS)
567	{
568	/*
569	* CSAM needs to perform a job in ring 3.
570	*
571	* Sync the page before going to the host context; otherwise we'll end up in a loop if
572	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
573	*/
574	LogFlow(("CSAM ring 3 job\n"));
575	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
576	AssertRC(rc2);
577
578	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
579	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
580	return rc;
581	}
582	}
583
584	/*
585	* Mark this page as safe.
586	*/
587	/** @todo not correct for pages that contain both code and data!! */
588	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
589	CSAMMarkPage(pVM, (RTGCPTR)pvFault, true);
590	}
591	}
592	# endif
593	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
594	if (VBOX_SUCCESS(rc))
595	{
596	/* The page was successfully synced, return to the guest. */
597	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
598	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
599	return VINF_SUCCESS;
600	}
601	}
602	else
603	{
604	/*
605	* A side effect of not flushing global PDEs are out of sync pages due
606	* to physical monitored regions, that are no longer valid.
607	* Assume for now it only applies to the read/write flag
608	*/
609	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
610	{
611	if (uErr & X86_TRAP_PF_US)
612	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
613	else /* supervisor */
614	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
615
616
617	/*
618	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
619	*/
620	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
621	if (VBOX_SUCCESS(rc))
622	{
623	/*
624	* Page was successfully synced, return to guest.
625	*/
626	# ifdef VBOX_STRICT
627	RTGCPHYS GCPhys;
628	uint64_t fPageGst;
629	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
630	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
631	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
632
633	uint64_t fPageShw;
634	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
635	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
636	# endif /* VBOX_STRICT */
637	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
638	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
639	return VINF_SUCCESS;
640	}
641	}
642
643	# ifdef VBOX_STRICT
644	/*
645	* Check for VMM page flags vs. Guest page flags consistency.
646	* Currently only for debug purposes.
647	*/
648	if (VBOX_SUCCESS(rc))
649	{
650	/* Get guest page flags. */
651	uint64_t fPageGst;
652	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
653	if (VBOX_SUCCESS(rc))
654	{
655	uint64_t fPageShw;
656	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
657
658	/*
659	* Compare page flags.
660	* Note: we have AVL, A, D bits desynched.
661	*/
662	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
663	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
664	}
665	else
666	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
667	}
668	else
669	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
670	# endif /* VBOX_STRICT */
671	}
672	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
673	# endif /* PGM_OUT_OF_SYNC_IN_GC */
674	}
675	else
676	{
677	/*
678	* Page not present in Guest OS or invalid page table address.
679	* This is potential virtual page access handler food.
680	*
681	* For the present we'll say that our access handlers don't
682	* work for this case - we've already discarded the page table
683	* not present case which is identical to this.
684	*
685	* When we perchance find we need this, we will probably have AVL
686	* trees (offset based) to operate on and we can measure their speed
687	* agains mapping a page table and probably rearrange this handling
688	* a bit. (Like, searching virtual ranges before checking the
689	* physical address.)
690	*/
691	}
692	}
693
694
695	/*
696	* Check if it's in a EIP based virtual page access handler range.
697	* This is only used for supervisor pages in flat mode.
698	*/
699	/** @todo this stuff is completely broken by the out-of-sync stuff. since we don't use this stuff, that's not really a problem yet. */
700	STAM_PROFILE_START(&pVM->pgm.s.StatEIPHandlers, d);
701	if (cpl == 0)
702	{
703	RTGCPTR pvEIP;
704	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
705	if ( VBOX_SUCCESS(rc)
706	&& pvEIP == (RTGCPTR)pRegFrame->eip)
707	{
708	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
709	if ( pCur
710	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
711	&& (uintptr_t)pvEIP - (uintptr_t)pCur->GCPtr < pCur->cb)
712	{
713	LogFlow(("EIP handler\n"));
714	#ifdef IN_GC
715	STAM_PROFILE_START(&pCur->Stat, h);
716	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (uintptr_t)pvEIP - (uintptr_t)pCur->GCPtr);
717	STAM_PROFILE_STOP(&pCur->Stat, h);
718	#else
719	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
720	#endif
721	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
722	return rc;
723	}
724	}
725	}
726	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
727
728	/*
729	* Conclusion, this is a guest trap.
730	*/
731	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
732	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
733	return VINF_EM_RAW_GUEST_TRAP;
734
735	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
736
737	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
738	return VERR_INTERNAL_ERROR;
739	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
740	}
741
742
743	/**
744	* Emulation of the invlpg instruction.
745	*
746	*
747	* @returns VBox status code.
748	*
749	* @param pVM VM handle.
750	* @param GCPtrPage Page to invalidate.
751	*
752	* @remark ASSUMES that the guest is updating before invalidating. This order
753	* isn't required by the CPU, so this is speculative and could cause
754	* trouble.
755	*
756	* @todo Flush page or page directory only if necessary!
757	* @todo Add a #define for simply invalidating the page.
758	*/
759	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
760	{
761	#if PGM_GST_TYPE == PGM_TYPE_32BIT
762
763	LogFlow(("InvalidatePage %x\n", GCPtrPage));
764	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
765	/*
766	* Get the shadow PD entry and skip out if this PD isn't present.
767	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
768	*/
769	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
770	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
771	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
772	# else
773	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
774	# endif
775	const SHWPDE PdeDst = *pPdeDst;
776	if (!PdeDst.n.u1Present)
777	{
778	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
779	return VINF_SUCCESS;
780	}
781
782	/*
783	* Get the guest PD entry and calc big page.
784	*/
785	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
786	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
787	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
788	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
789	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
790
791	# ifdef IN_RING3
792	/*
793	* If a CR3 Sync is pending we may ignore the invalidate page operation
794	* depending on the kind of sync and if it's a global page or not.
795	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
796	*/
797	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
798	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
799	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
800	&& fIsBigPage
801	&& PdeSrc.b.u1Global
802	&& (cr4 & X86_CR4_PGE)
803	)
804	)
805	# else
806	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
807	# endif
808	{
809	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
810	return VINF_SUCCESS;
811	}
812	# endif /* IN_RING3 */
813
814
815	/*
816	* Deal with the Guest PDE.
817	*/
818	int rc = VINF_SUCCESS;
819	if (PdeSrc.n.u1Present)
820	{
821	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
822	{
823	/*
824	* Conflict - Let SyncPT deal with it to avoid duplicate code.
825	*/
826	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
827	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
828	}
829	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
830	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
831	{
832	/*
833	* Mark not present so we can resync the PDE when it's used.
834	*/
835	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
836	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
837	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
838	pPdeDst->u = 0;
839	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
840	PGM_INVL_GUEST_TLBS();
841	}
842	# ifdef PGM_SYNC_ACCESSED_BIT
843	else if (!PdeSrc.n.u1Accessed)
844	{
845	/*
846	* Mark not present so we can set the accessed bit.
847	*/
848	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
849	pPdeDst->u = 0;
850	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
851	PGM_INVL_GUEST_TLBS();
852	}
853	# endif
854	else if (!fIsBigPage)
855	{
856	/*
857	* 4KB - page.
858	*/
859	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
860	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
861	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
862	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
863	# endif
864	if (pShwPage->GCPhys == GCPhys)
865	{
866	#if 0 /* debug build + flash + xp (=1000Hz timer?) => bad invalidation + sync loops. */
867	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
868	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
869	if (pPT->a[iPTEDst].n.u1Present)
870	{
871	# ifdef PGMPOOL_WITH_USER_TRACKING
872	/* This is very unlikely with caching/monitoring enabled. */
873	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
874	# endif
875	pPT->a[iPTEDst].u = 0;
876	}
877	#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
878	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
879	if (VBOX_SUCCESS(rc))
880	rc = VINF_SUCCESS;
881	#endif
882	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
883	PGM_INVL_PG(GCPtrPage);
884	}
885	else
886	{
887	/*
888	* The page table address changed.
889	*/
890	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
891	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
892	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
893	pPdeDst->u = 0;
894	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
895	PGM_INVL_GUEST_TLBS();
896	}
897	}
898	else
899	{
900	/*
901	* 4MB - page.
902	*/
903	/* Before freeing the page, check if anything really changed. */
904	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
905	RTGCPHYS GCPhys = PdeSrc.u & X86_PDE4M_PG_MASK;
906	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
907	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
908	# endif
909	if ( pShwPage->GCPhys == GCPhys
910	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
911	{
912	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
913	/** @todo PAT */
914	# ifdef PGM_SYNC_DIRTY_BIT
915	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
916	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
917	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
918	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
919	# else
920	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
921	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
922	# endif
923	{
924	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
925	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
926	return VINF_SUCCESS;
927	}
928	}
929
930	/*
931	* Ok, the page table is present and it's been changed in the guest.
932	* If we're in host context, we'll just mark it as not present taking the lazy approach.
933	* We could do this for some flushes in GC too, but we need an algorithm for
934	* deciding which 4MB pages containing code likely to be executed very soon.
935	*/
936	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
937	pPdeDst->u = 0;
938	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
939	DUMP_PDE_BIG("PGMInvalidatePage", iPDSrc, PdeSrc);
940	PGM_INVL_BIG_PG(GCPtrPage);
941	}
942	}
943	else
944	{
945	/*
946	* Page directory is not present, mark shadow PDE not present.
947	*/
948	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
949	{
950	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
951	pPdeDst->u = 0;
952	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
953	PGM_INVL_PG(GCPtrPage);
954	}
955	else
956	{
957	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
958	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
959	}
960	}
961
962	return rc;
963
964	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
965	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
966	# endif
967	return VINF_SUCCESS;
968
969	#elif PGM_GST_TYPE == PGM_TYPE_PAE
970	# if PGM_SHW_TYPE == PGM_TYPE_PAE
971	//# error not implemented
972	return VERR_INTERNAL_ERROR;
973
974	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
975	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
976	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
977
978	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
979	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
980	//# error not implemented
981	return VERR_INTERNAL_ERROR;
982
983	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
984	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
985	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
986
987	#else /* guest real and protected mode */
988
989	return VINF_SUCCESS;
990	#endif
991	}
992
993
994	#ifdef PGMPOOL_WITH_USER_TRACKING
995	/**
996	* Update the tracking of shadowed pages.
997	*
998	* @param pVM The VM handle.
999	* @param pShwPage The shadow page.
1000	* @param HCPhys The physical page we is being dereferenced.
1001	*/
1002	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1003	{
1004	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1005	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1006	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1007
1008	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1009	* 1. have a medium sized HCPhys -> GCPhys cache (hash?)
1010	* 2. write protect all shadowed pages. I.e. implement caching.
1011	*/
1012	/*
1013	* Find the guest address.
1014	*/
1015	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTXSUFF(pRamRanges);
1016	pRam;
1017	pRam = pRam->CTXSUFF(pNext))
1018	{
1019	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1020	while (iPage-- > 0)
1021	{
1022	if ((pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) == HCPhys)
1023	{
1024	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1025	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aHCPhys[iPage]);
1026	pShwPage->cPresent--;
1027	pPool->cPresent--;
1028	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1029	return;
1030	}
1031	}
1032	}
1033
1034	for (;;)
1035	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1036	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1037	pShwPage->cPresent--;
1038	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1039	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1040	}
1041
1042
1043	/**
1044	* Update the tracking of shadowed pages.
1045	*
1046	* @param pVM The VM handle.
1047	* @param pShwPage The shadow page.
1048	* @param u16 The top 16-bit of the *pHCPhys.
1049	* @param pHCPhys Pointer to the ram range physical page entry.
1050	* @param iPTDst The index into the shadow table.
1051	*/
1052	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PRTHCPHYS pHCPhys, const unsigned iPTDst)
1053	{
1054	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1055	/*
1056	* We're making certain assumptions about the placement of cRef and idx.
1057	*/
1058	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1059	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1060
1061	/*
1062	* Just deal with the simple first time here.
1063	*/
1064	if (!u16)
1065	{
1066	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1067	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1068	}
1069	else
1070	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1071
1072	/* write back, trying to be clever... */
1073	Log2(("SyncPageWorkerTrackAddRef: u16=%#x *pHCPhys=%VHp->%VHp iPTDst=%#x\n",
1074	u16, pHCPhys, (pHCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1075	((uint16_t )pHCPhys + 3) = u16;
1076	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1077
1078	/* update statistics. */
1079	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1080	pShwPage->cPresent++;
1081	if (pShwPage->iFirstPresent > iPTDst)
1082	pShwPage->iFirstPresent = iPTDst;
1083	}
1084	#endif /* PGMPOOL_WITH_USER_TRACKING */
1085
1086
1087	/**
1088	* Creates a 4K shadow page for a guest page.
1089	*
1090	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1091	* physical address. The PdeSrc argument only the flags are used. No page structured
1092	* will be mapped in this function.
1093	*
1094	* @param pVM VM handle.
1095	* @param pPteDst Destination page table entry.
1096	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1097	* Can safely assume that only the flags are being used.
1098	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1099	* @param pShwPage Pointer to the shadow page.
1100	* @param iPTDst The index into the shadow table.
1101	*
1102	* @remark Not used for 2/4MB pages!
1103	*/
1104	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, VBOXPDE PdeSrc, VBOXPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1105	{
1106	if (PteSrc.n.u1Present)
1107	{
1108	/*
1109	* Find the ram range.
1110	*/
1111	PRTHCPHYS pHCPhys;
1112	int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, PteSrc.u & X86_PTE_PG_MASK, &pHCPhys);
1113	if (VBOX_SUCCESS(rc))
1114	{
1115	/** @todo investiage PWT, PCD and PAT. */
1116	/*
1117	* Make page table entry.
1118	*/
1119	const RTHCPHYS HCPhys = *pHCPhys;
1120	SHWPTE PteDst;
1121	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1122	{
1123	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1124	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1125	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1126	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1127	else
1128	PteDst.u = 0;
1129	/** @todo count these two kinds. */
1130	}
1131	else
1132	{
1133	#ifdef PGM_SYNC_DIRTY_BIT
1134	# ifdef PGM_SYNC_ACCESSED_BIT
1135	/*
1136	* If the page or page directory entry is not marked accessed,
1137	* we mark the page not present.
1138	*/
1139	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1140	{
1141	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1142	PteDst.u = 0;
1143	}
1144	else
1145	# endif
1146	/*
1147	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1148	* when the page is modified.
1149	*/
1150	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1151	{
1152	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1153	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1154	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1155	\| PGM_PTFLAGS_TRACK_DIRTY;
1156	}
1157	else
1158	{
1159	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1160	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1161	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1162	}
1163	#endif
1164	}
1165
1166	#ifdef PGMPOOL_WITH_USER_TRACKING
1167	/*
1168	* Keep user track up to date.
1169	*/
1170	if (PteDst.n.u1Present)
1171	{
1172	if (!pPteDst->n.u1Present)
1173	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1174	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1175	{
1176	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1177	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1178	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1179	}
1180	}
1181	else if (pPteDst->n.u1Present)
1182	{
1183	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1184	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1185	}
1186	#endif /* PGMPOOL_WITH_USER_TRACKING */
1187
1188	/*
1189	* Update statistics and commit the entry.
1190	*/
1191	if (!PteSrc.n.u1Global)
1192	pShwPage->fSeenNonGlobal = true;
1193	*pPteDst = PteDst;
1194	}
1195	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1196	/** @todo count these. */
1197	}
1198	else
1199	{
1200	/*
1201	* Page not-present.
1202	*/
1203	#ifdef PGMPOOL_WITH_USER_TRACKING
1204	/* Keep user track up to date. */
1205	if (pPteDst->n.u1Present)
1206	{
1207	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1208	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1209	}
1210	#endif /* PGMPOOL_WITH_USER_TRACKING */
1211	pPteDst->u = 0;
1212	/** @todo count these. */
1213	}
1214	}
1215
1216
1217	/**
1218	* Syncs a guest OS page.
1219	*
1220	* There are no conflicts at this point, neither is there any need for
1221	* page table allocations.
1222	*
1223	* @returns VBox status code.
1224	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1225	* @param pVM VM handle.
1226	* @param PdeSrc Page directory entry of the guest.
1227	* @param GCPtrPage Guest context page address.
1228	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1229	* @param uErr Fault error (X86_TRAP_PF_*).
1230	*/
1231	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1232	{
1233	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1234
1235	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1236
1237	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1238	# error "Invalid shadow mode for 32-bit guest mode!"
1239	# endif
1240
1241	/*
1242	* Assert preconditions.
1243	*/
1244	# if GC_ARCH_BITS != 32
1245	Assert(GCPtrPage < _4G); //???
1246	# endif
1247	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & X86_PD_MASK]);
1248	Assert(PdeSrc.n.u1Present);
1249	Assert(cPages);
1250
1251	/*
1252	* Get the shadow PDE, find the shadow page table in the pool.
1253	*/
1254	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1255	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1256	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1257	# else /* PAE */
1258	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1259	# endif
1260	Assert(PdeDst.n.u1Present);
1261	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1262
1263	/*
1264	* Check that the page is present and that the shadow PDE isn't out of sync.
1265	*/
1266	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1267	RTGCPHYS GCPhys;
1268	if (!fBigPage)
1269	{
1270	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1271	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1272	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1273	# endif
1274	}
1275	else
1276	{
1277	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1278	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1279	GCPhys \|= GCPtrPage & X86_PAGE_2M_SIZE;
1280	# endif
1281	}
1282	if ( pShwPage->GCPhys == GCPhys
1283	&& PdeSrc.n.u1Present
1284	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1285	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1286	)
1287	{
1288	# ifdef PGM_SYNC_ACCESSED_BIT
1289	/*
1290	* Check that the PDE is marked accessed already.
1291	* Since we set the accessed bit before getting here on a #PF, this
1292	* check is only meant for dealing with non-#PF'ing paths.
1293	*/
1294	if (PdeSrc.n.u1Accessed)
1295	# endif
1296	{
1297	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1298	if (!fBigPage)
1299	{
1300	/*
1301	* 4KB Page - Map the guest page table.
1302	*/
1303	PVBOXPT pPTSrc;
1304	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & X86_PDE_PG_MASK, &pPTSrc);
1305	if (VBOX_SUCCESS(rc))
1306	{
1307	# ifdef PGM_SYNC_N_PAGES
1308	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1309	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1310	{
1311	/*
1312	* This code path is currently only taken when the caller is PGMTrap0eHandler
1313	* for non-present pages!
1314	*
1315	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1316	* deal with locality.
1317	*/
1318	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1319	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1320	const unsigned offPTSrc = 0;
1321	# else
1322	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1323	# endif
1324	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1325	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1326	iPTDst = 0;
1327	else
1328	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1329	for (; iPTDst < iPTDstEnd; iPTDst++)
1330	{
1331	if (!pPTDst->a[iPTDst].n.u1Present)
1332	{
1333	VBOXPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1334	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1335	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1336	(GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT),
1337	PteSrc.n.u1Present, PteSrc.n.u1Write, PteSrc.n.u1User, (uint64_t)PteSrc.u,
1338	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1339	}
1340	}
1341	}
1342	else
1343	# endif /* PGM_SYNC_N_PAGES */
1344	{
1345	const unsigned iPTSrc = (GCPtrPage >> X86_PT_SHIFT) & X86_PT_MASK;
1346	VBOXPTE PteSrc = pPTSrc->a[iPTSrc];
1347	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1348	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1349	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1350	GCPtrPage, PteSrc.n.u1Present, PteSrc.n.u1Write, PteSrc.n.u1User, (uint64_t)PteSrc.u,
1351	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1352	}
1353	}
1354	else /* MMIO or invalid page: emulated in #PF handler. */
1355	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1356	}
1357	else
1358	{
1359	/*
1360	* 4/2MB page - lazy syncing shadow 4K pages.
1361	* (There are many causes of getting here, it's no longer only CSAM.)
1362	*/
1363	/* Calculate the GC physical address of this 4KB shadow page. */
1364	RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PAE_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & PAGE_OFFSET_MASK_BIG);
1365	/* Find ram range. */
1366	PRTHCPHYS pHCPhys;
1367	int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, GCPhys, &pHCPhys);
1368	if (VBOX_SUCCESS(rc))
1369	{
1370	/*
1371	* Make shadow PTE entry.
1372	*/
1373	RTHCPHYS HCPhys = *pHCPhys;
1374	SHWPTE PteDst;
1375	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1376	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1377	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1378	{
1379	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1380	PteDst.n.u1Write = 0;
1381	else
1382	PteDst.u = 0;
1383	}
1384	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1385	# ifdef PGMPOOL_WITH_USER_TRACKING
1386	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1387	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1388	# endif
1389	pPTDst->a[iPTDst] = PteDst;
1390
1391
1392	# ifdef PGM_SYNC_DIRTY_BIT
1393	/*
1394	* If the page is not flagged as dirty and is writable, then make it read-only
1395	* at PD level, so we can set the dirty bit when the page is modified.
1396	*
1397	* ASSUMES that page access handlers are implemented on page table entry level.
1398	* Thus we will first catch the dirty access and set PDE.D and restart. If
1399	* there is an access handler, we'll trap again and let it work on the problem.
1400	*/
1401	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1402	* As for invlpg, it simply frees the whole shadow PT.
1403	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1404	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1405	{
1406	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1407	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1408	PdeDst.n.u1Write = 0;
1409	}
1410	else
1411	{
1412	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1413	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1414	}
1415	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1416	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1417	# else /* PAE */
1418	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1419	# endif
1420	# endif /* PGM_SYNC_DIRTY_BIT */
1421	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1422	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1423	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1424	}
1425	}
1426	return VINF_SUCCESS;
1427	}
1428	# ifdef PGM_SYNC_ACCESSED_BIT
1429	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1430	#endif
1431	}
1432	else
1433	{
1434	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1435	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1436	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1437	}
1438
1439	/*
1440	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1441	* Yea, I'm lazy.
1442	*/
1443	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1444	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1445	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1446	# else /* PAE */
1447	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1448	# endif
1449	PGM_INVL_GUEST_TLBS();
1450	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1451
1452	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1453
1454	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1455	return VERR_INTERNAL_ERROR;
1456	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1457	}
1458
1459
1460
1461	#ifdef PGM_SYNC_DIRTY_BIT
1462
1463	/**
1464	* Investigate page fault and handle write protection page faults caused by
1465	* dirty bit tracking.
1466	*
1467	* @returns VBox status code.
1468	* @param pVM VM handle.
1469	* @param uErr Page fault error code.
1470	* @param pPdeDst Shadow page directory entry.
1471	* @param pPdeSrc Guest page directory entry.
1472	* @param GCPtrPage Guest context page address.
1473	*/
1474	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1475	{
1476	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1477	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1478
1479	/*
1480	* Real page fault?
1481	*/
1482	if ( (uErr & X86_TRAP_PF_RSVD)
1483	\|\| !pPdeSrc->n.u1Present
1484	\|\| ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1485	\|\| ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1486	{
1487	#ifdef IN_GC
1488	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1489	#endif
1490	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1491	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1492
1493	if (pPdeSrc->n.u1Present)
1494	{
1495	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1496	* See the 2nd case below as well.
1497	*/
1498	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1499	{
1500	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1501	}
1502	else
1503	{
1504	/*
1505	* Map the guest page table.
1506	*/
1507	PVBOXPT pPTSrc;
1508	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1509	if (VBOX_SUCCESS(rc))
1510	{
1511	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1512	const VBOXPTE PteSrc = *pPteSrc;
1513	if (pPteSrc->n.u1Present)
1514	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1515	}
1516	AssertRC(rc);
1517	}
1518	}
1519	return VINF_EM_RAW_GUEST_TRAP;
1520	}
1521
1522	/*
1523	* First check the easy case where the page directory has been marked read-only to track
1524	* the dirty bit of an emulated BIG page
1525	*/
1526	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1527	{
1528	/* Mark guest page directory as accessed */
1529	pPdeSrc->b.u1Accessed = 1;
1530
1531	/*
1532	* Only write protection page faults are relevant here.
1533	*/
1534	if (uErr & X86_TRAP_PF_RW)
1535	{
1536	/* Mark guest page directory as dirty (BIG page only). */
1537	pPdeSrc->b.u1Dirty = 1;
1538
1539	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1540	{
1541	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1542
1543	Assert(pPdeSrc->b.u1Write);
1544
1545	pPdeDst->n.u1Write = 1;
1546	pPdeDst->n.u1Accessed = 1;
1547	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1548	PGM_INVL_BIG_PG(GCPtrPage);
1549	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1550	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1551	}
1552	}
1553	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1554	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1555	}
1556	/* else: 4KB page table */
1557
1558	/*
1559	* Map the guest page table.
1560	*/
1561	PVBOXPT pPTSrc;
1562	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1563	if (VBOX_SUCCESS(rc))
1564	{
1565	/*
1566	* Real page fault?
1567	*/
1568	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1569	const VBOXPTE PteSrc = *pPteSrc;
1570	if ( !PteSrc.n.u1Present
1571	\|\| ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1572	\|\| ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1573	)
1574	{
1575	#ifdef IN_GC
1576	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1577	#endif
1578	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1579	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1580
1581	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1582	* See the 2nd case above as well.
1583	*/
1584	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1585	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1586
1587	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1588	return VINF_EM_RAW_GUEST_TRAP;
1589	}
1590	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1591
1592	/*
1593	* Set the accessed bits in the page directory and the page table.
1594	*/
1595	pPdeSrc->n.u1Accessed = 1;
1596	pPteSrc->n.u1Accessed = 1;
1597
1598	/*
1599	* Only write protection page faults are relevant here.
1600	*/
1601	if (uErr & X86_TRAP_PF_RW)
1602	{
1603	/* Write access, so mark guest entry as dirty. */
1604	#if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1605	if (!pPteSrc->n.u1Dirty)
1606	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1607	else
1608	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1609	#endif
1610	pPteSrc->n.u1Dirty = 1;
1611
1612	if (pPdeDst->n.u1Present)
1613	{
1614	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1615	* Our individual shadow handlers will provide more information and force a fatal exit.
1616	*/
1617	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1618	{
1619	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1620	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1621	return VINF_SUCCESS;
1622	}
1623
1624	/*
1625	* Map shadow page table.
1626	*/
1627	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1628	if (pShwPage)
1629	{
1630	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1631	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1632	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1633	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1634	{
1635	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1636	#ifdef VBOX_STRICT
1637	RTHCPHYS HCPhys;
1638	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, pPteSrc->u & X86_PTE_PG_MASK, &HCPhys);
1639	if (VBOX_SUCCESS(rc))
1640	AssertMsg(!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)),
1641	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1642	#endif
1643	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1644
1645	Assert(pPteSrc->n.u1Write);
1646
1647	pPteDst->n.u1Write = 1;
1648	pPteDst->n.u1Dirty = 1;
1649	pPteDst->n.u1Accessed = 1;
1650	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1651	PGM_INVL_PG(GCPtrPage);
1652
1653	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1654	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1655	}
1656	}
1657	else
1658	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1659	}
1660	}
1661	/** @todo Optimize accessed bit emulation? */
1662	#ifdef VBOX_STRICT
1663	/*
1664	* Sanity check.
1665	*/
1666	else if ( !pPteSrc->n.u1Dirty
1667	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1668	&& pPdeDst->n.u1Present)
1669	{
1670	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1671	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1672	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1673	if ( pPteDst->n.u1Present
1674	&& pPteDst->n.u1Write)
1675	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1676	}
1677	#endif /* VBOX_STRICT */
1678	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1679	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1680	}
1681	AssertRC(rc);
1682	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1683	return rc;
1684	}
1685
1686	#endif
1687
1688
1689	/**
1690	* Sync a shadow page table.
1691	*
1692	* The shadow page table is not present. This includes the case where
1693	* there is a conflict with a mapping.
1694	*
1695	* @returns VBox status code.
1696	* @param pVM VM handle.
1697	* @param iPD Page directory index.
1698	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1699	* Assume this is a temporary mapping.
1700	* @param GCPtrPage GC Pointer of the page that caused the fault
1701	*/
1702	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage)
1703	{
1704	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1705	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1706	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1707
1708	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1709
1710	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1711	# error "Invalid shadow mode for 32-bit guest mode!"
1712	# endif
1713
1714	/*
1715	* Validate input a little bit.
1716	*/
1717	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1718	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1719	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1720	# else
1721	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1722	# endif
1723	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1724	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1725	SHWPDE PdeDst = *pPdeDst;
1726
1727	/*
1728	* Check for conflicts.
1729	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1730	* HC: Simply resolve the conflict.
1731	*/
1732	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1733	{
1734	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1735	# ifndef IN_RING3
1736	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1737	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1738	return VERR_ADDRESS_CONFLICT;
1739	# else
1740	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1741	Assert(pMapping);
1742	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1743	if (VBOX_FAILURE(rc))
1744	{
1745	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1746	return rc;
1747	}
1748	PdeDst = *pPdeDst;
1749	# endif
1750	}
1751	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1752
1753	/*
1754	* Sync page directory entry.
1755	*/
1756	int rc = VINF_SUCCESS;
1757	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1758	if (PdeSrc.n.u1Present)
1759	{
1760	/*
1761	* Allocate & map the page table.
1762	*/
1763	PSHWPT pPTDst;
1764	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1765	PPGMPOOLPAGE pShwPage;
1766	RTGCPHYS GCPhys;
1767	if (fPageTable)
1768	{
1769	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1770	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1771	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1772	# endif
1773	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1774	}
1775	else
1776	{
1777	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1778	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1779	GCPhys \|= GCPtrPage & BIT(X86_PAGE_2M_SHIFT);
1780	# endif
1781	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1782	}
1783	if (rc == VINF_SUCCESS)
1784	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1785	else if (rc == VINF_PGM_CACHED_PAGE)
1786	{
1787	/*
1788	* The PT was cached, just hook it up.
1789	*/
1790	if (fPageTable)
1791	PdeDst.u = pShwPage->Core.Key
1792	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1793	else
1794	{
1795	PdeDst.u = pShwPage->Core.Key
1796	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1797	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1798	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1799	{
1800	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1801	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1802	PdeDst.b.u1Write = 0;
1803	}
1804	# endif
1805	}
1806	*pPdeDst = PdeDst;
1807	return VINF_SUCCESS;
1808	}
1809	else if (rc == VERR_PGM_POOL_FLUSHED)
1810	return VINF_PGM_SYNC_CR3;
1811	else
1812	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1813	PdeDst.u &= X86_PDE_AVL_MASK;
1814	PdeDst.u \|= pShwPage->Core.Key;
1815
1816	# ifdef PGM_SYNC_DIRTY_BIT
1817	/*
1818	* Page directory has been accessed (this is a fault situation, remember).
1819	*/
1820	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
1821	# endif
1822
1823	if (fPageTable)
1824	{
1825	/*
1826	* Page table - 4KB.
1827	*
1828	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
1829	*/
1830	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
1831	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
1832	PGSTPT pPTSrc;
1833	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1834	if (VBOX_SUCCESS(rc))
1835	{
1836	/*
1837	* Start by syncing the page directory entry so CSAM's TLB trick works.
1838	*/
1839	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK))
1840	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1841	*pPdeDst = PdeDst;
1842
1843	/*
1844	* Directory/page user or supervisor privilege: (same goes for read/write)
1845	*
1846	* Directory Page Combined
1847	* U/S U/S U/S
1848	* 0 0 0
1849	* 0 1 0
1850	* 1 0 0
1851	* 1 1 1
1852	*
1853	* Simple AND operation. Table listed for completeness.
1854	*
1855	*/
1856	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
1857	# ifdef PGM_SYNC_N_PAGES
1858	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1859	unsigned iPTDst = iPTBase;
1860	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1861	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
1862	iPTDst = 0;
1863	else
1864	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1865	# else /* !PGM_SYNC_N_PAGES */
1866	unsigned iPTDst = 0;
1867	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
1868	# endif /* !PGM_SYNC_N_PAGES */
1869	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1870	const unsigned offPTSrc = 0;
1871	# else
1872	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1873	# endif
1874	for (; iPTDst < iPTDstEnd; iPTDst++)
1875	{
1876	const unsigned iPTSrc = iPTDst + offPTSrc;
1877	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1878
1879	if (PteSrc.n.u1Present) /* we've already cleared it above */
1880	{
1881	#ifndef IN_RING0
1882	/*
1883	* Assuming kernel code will be marked as supervisor - and not as user level
1884	* and executed using a conforming code selector - And marked as readonly.
1885	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1886	*/
1887	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
1888	\|\| !CSAMIsEnabled(pVM)
1889	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
1890	\|\| PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
1891	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
1892	)
1893	#endif
1894	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1895	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
1896	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
1897	PteSrc.n.u1Present, PteSrc.n.u1Write, PteSrc.n.u1User, (uint64_t)PteSrc.u,
1898	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
1899	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
1900	}
1901	} /* for PTEs */
1902	}
1903	}
1904	else
1905	{
1906	/*
1907	* Big page - 2/4MB.
1908	*
1909	* We'll walk the ram range list in parallel and optimize lookups.
1910	* We will only sync on shadow page table at a time.
1911	*/
1912	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
1913
1914	/**
1915	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
1916	*/
1917
1918	/*
1919	* Start by syncing the page directory entry.
1920	*/
1921	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
1922	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1923
1924	# ifdef PGM_SYNC_DIRTY_BIT
1925	/*
1926	* If the page is not flagged as dirty and is writable, then make it read-only
1927	* at PD level, so we can set the dirty bit when the page is modified.
1928	*
1929	* ASSUMES that page access handlers are implemented on page table entry level.
1930	* Thus we will first catch the dirty access and set PDE.D and restart. If
1931	* there is an access handler, we'll trap again and let it work on the problem.
1932	*/
1933	/** @todo move the above stuff to a section in the PGM documentation. */
1934	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
1935	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1936	{
1937	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1938	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1939	PdeDst.b.u1Write = 0;
1940	}
1941	# endif /* PGM_SYNC_DIRTY_BIT */
1942	*pPdeDst = PdeDst;
1943
1944	/*
1945	* Fill the shadow page table.
1946	*/
1947	/* Get address and flags from the source PDE. */
1948	SHWPTE PteDstBase;
1949	PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
1950
1951	/* Loop thru the entries in the shadow PT. */
1952	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
1953	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
1954	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
1955	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1956	PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
1957	unsigned iPTDst = 0;
1958	while (iPTDst < ELEMENTS(pPTDst->a))
1959	{
1960	/* Advance ram range list. */
1961	while (pRam && GCPhys > pRam->GCPhysLast)
1962	pRam = CTXSUFF(pRam->pNext);
1963	if (pRam && GCPhys >= pRam->GCPhys)
1964	{
1965	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
1966	do
1967	{
1968	/* Make shadow PTE. */
1969	RTHCPHYS HCPhys = pRam->aHCPhys[iHCPage];
1970	SHWPTE PteDst;
1971
1972	/* Make sure the RAM has already been allocated. */
1973	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1974	{
1975	if (RT_UNLIKELY(!(pRam->aHCPhys[iHCPage] & X86_PTE_PAE_PG_MASK)))
1976	{
1977	#ifdef IN_RING3
1978	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
1979	#else
1980	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
1981	#endif
1982	if (rc != VINF_SUCCESS)
1983	return rc;
1984
1985	HCPhys = pRam->aHCPhys[iHCPage];
1986	}
1987	}
1988
1989	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1990	{
1991	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1992	{
1993	PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) \| PteDstBase.u;
1994	PteDst.n.u1Write = 0;
1995	}
1996	else
1997	PteDst.u = 0;
1998	}
1999	#ifndef IN_RING0
2000	/*
2001	* Assuming kernel code will be marked as supervisor and not as user level and executed
2002	* using a conforming code selector. Don't check for readonly, as that implies the whole
2003	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2004	*/
2005	else if ( !PdeSrc.n.u1User
2006	&& CSAMIsEnabled(pVM)
2007	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2008	PteDst.u = 0;
2009	#endif
2010	else
2011	PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) \| PteDstBase.u;
2012	# ifdef PGMPOOL_WITH_USER_TRACKING
2013	if (PteDst.n.u1Present)
2014	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, &pRam->aHCPhys[iHCPage], iPTDst);
2015	# endif
2016	/* commit it */
2017	pPTDst->a[iPTDst] = PteDst;
2018	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2019	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2020	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2021
2022	/* advance */
2023	GCPhys += PAGE_SIZE;
2024	iHCPage++;
2025	iPTDst++;
2026	} while ( iPTDst < ELEMENTS(pPTDst->a)
2027	&& GCPhys <= pRam->GCPhysLast);
2028	}
2029	else if (pRam)
2030	{
2031	Log(("Invalid pages at %VGp\n", GCPhys));
2032	do
2033	{
2034	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2035	GCPhys += PAGE_SIZE;
2036	iPTDst++;
2037	} while ( iPTDst < ELEMENTS(pPTDst->a)
2038	&& GCPhys < pRam->GCPhys);
2039	}
2040	else
2041	{
2042	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2043	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2044	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2045	}
2046	} /* while more PTEs */
2047	} /* 4KB / 4MB */
2048	}
2049	else
2050	AssertRelease(!PdeDst.n.u1Present);
2051
2052	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2053	# ifdef IN_GC
2054	if (VBOX_FAILURE(rc))
2055	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2056	# endif
2057	return rc;
2058
2059	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2060
2061	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2062	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2063	return VERR_INTERNAL_ERROR;
2064	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2065	}
2066
2067
2068
2069	/**
2070	* Prefetch a page/set of pages.
2071	*
2072	* Typically used to sync commonly used pages before entering raw mode
2073	* after a CR3 reload.
2074	*
2075	* @returns VBox status code.
2076	* @param pVM VM handle.
2077	* @param GCPtrPage Page to invalidate.
2078	*/
2079	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2080	{
2081	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2082
2083	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2084	# error "Invalid shadow mode for 32-bit guest mode!"
2085	# endif
2086
2087	/*
2088	* Check that all Guest levels thru the PDE are present, getting the
2089	* PD and PDE in the processes.
2090	*/
2091	int rc = VINF_SUCCESS;
2092	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2093	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2094	const VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2095	# ifdef PGM_SYNC_ACCESSED_BIT
2096	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2097	# else
2098	if (PdeSrc.n.u1Present)
2099	# endif
2100	{
2101	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2102	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2103	# else
2104	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2105	# endif
2106	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2107	{
2108	if (!PdeDst.n.u1Present)
2109	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2110	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2111	else
2112	{
2113	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2114	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2115	* makes no sense to prefetch more than one page.
2116	*/
2117	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2118	if (VBOX_SUCCESS(rc))
2119	rc = VINF_SUCCESS;
2120	}
2121	}
2122	}
2123	return rc;
2124
2125	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2126
2127	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2128	return VERR_INTERNAL_ERROR;
2129	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2130	}
2131
2132
2133
2134
2135	/**
2136	* Syncs a page during a PGMVerifyAccess() call.
2137	*
2138	* @returns VBox status code (informational included).
2139	* @param GCPtrPage The address of the page to sync.
2140	* @param fPage The effective guest page flags.
2141	* @param uErr The trap error code.
2142	*/
2143	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2144	{
2145	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2146
2147	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2148
2149	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2150	# error "Invalid shadow mode for 32-bit guest mode!"
2151	# endif
2152
2153	#ifndef IN_RING0
2154	if (!(fPage & X86_PTE_US))
2155	{
2156	/*
2157	* Mark this page as safe.
2158	*/
2159	/** @todo not correct for pages that contain both code and data!! */
2160	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2161	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2162	}
2163	#endif
2164	/*
2165	* Get guest PD and index.
2166	*/
2167	unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2168	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2169	int rc = VINF_SUCCESS;
2170
2171	# ifdef PGM_SYNC_DIRTY_BIT
2172	/*
2173	* First check if the page fault was caused by dirty bit tracking
2174	*/
2175	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2176	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2177	# else
2178	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2179	# endif
2180	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2181	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2182	Log(("PGMVerifyAccess: success (dirty)\n"));
2183	else
2184	# endif /* PGM_SYNC_DIRTY_BIT */
2185	{
2186	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2187	if (uErr & X86_TRAP_PF_US)
2188	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2189	else /* supervisor */
2190	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2191
2192	rc = PGM_BTH_NAME(SyncPage)(pVM, pPDSrc->a[iPDSrc], GCPtrPage, 1, 0);
2193	if (VBOX_SUCCESS(rc))
2194	{
2195	/* Page was successfully synced */
2196	Log(("PGMVerifyAccess: success (sync)\n"));
2197	rc = VINF_SUCCESS;
2198	}
2199	else
2200	{
2201	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2202	return VINF_EM_RAW_GUEST_TRAP;
2203	}
2204	}
2205	return rc;
2206
2207	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2208
2209	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2210	return VERR_INTERNAL_ERROR;
2211	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2212	}
2213
2214
2215	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2216	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2217	/**
2218	* Figures out which kind of shadow page this guest PDE warrants.
2219	*
2220	* @returns Shadow page kind.
2221	* @param pPdeSrc The guest PDE in question.
2222	* @param cr4 The current guest cr4 value.
2223	*/
2224	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const VBOXPDE *pPdeSrc, uint32_t cr4)
2225	{
2226	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2227	return BTH_PGMPOOLKIND_PT_FOR_PT;
2228	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2229	//{
2230	// case 0:
2231	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2232	// case X86_PDE4M_RW:
2233	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2234	// case X86_PDE4M_US:
2235	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2236	// case X86_PDE4M_RW \| X86_PDE4M_US:
2237	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2238	# if 0
2239	// case X86_PDE4M_PAE_NX:
2240	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2241	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2242	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2243	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2244	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2245	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2246	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2247	# endif
2248	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2249	//}
2250	}
2251	# endif
2252	#endif
2253
2254	#undef MY_STAM_COUNTER_INC
2255	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2256
2257
2258	/**
2259	* Syncs the paging hierarchy starting at CR3.
2260	*
2261	* @returns VBox status code, no specials.
2262	* @param pVM The virtual machine.
2263	* @param cr0 Guest context CR0 register
2264	* @param cr3 Guest context CR3 register
2265	* @param cr4 Guest context CR4 register
2266	* @param fGlobal Including global page directories or not
2267	*/
2268	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2269	{
2270	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2271	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2272	/*
2273	* Inform the PGM PD Cache Manager about the pending sync.
2274	*/
2275	if (fGlobal \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2276	{
2277	# if 0 /** @todo what the heck is this about? */
2278	/* Don't cause an additional global CR3 reload the next time (the flag is cleared in PGMSyncCR3). */
2279	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2280	# endif
2281
2282	/* Change this CR3 reload to be a global one. */
2283	fGlobal = true;
2284	}
2285	# endif
2286	#endif
2287
2288	/*
2289	* Update page access handlers.
2290	* The virtual are always flushed, while the physical are only on demand.
2291	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2292	* have to look into that later because it will have a bad influence on the performance.
2293	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2294	* bird: Yes, but that won't work for aliases.
2295	*/
2296	/** @todo this MUST go away. See #1557. */
2297	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2298	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2299	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2300
2301	#ifdef PGMPOOL_WITH_MONITORING
2302	/*
2303	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2304	* Occationally we will have to clear all the shadow page tables because we wanted
2305	* to monitor a page which was mapped by too many shadowed page tables. This operation
2306	* sometimes refered to as a 'lightweight flush'.
2307	*/
2308	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2309	pgmPoolMonitorModifiedClearAll(pVM);
2310	else
2311	{
2312	# ifdef IN_RING3
2313	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2314	pgmPoolClearAll(pVM);
2315	# else
2316	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2317	return VINF_PGM_SYNC_CR3;
2318	# endif
2319	}
2320	#endif
2321
2322	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2323	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2324
2325	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2326	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2327	/*
2328	* Get page directory addresses.
2329	*/
2330	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2331	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2332	# else
2333	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2334	# endif
2335	PVBOXPD pPDSrc = pVM->pgm.s.CTXSUFF(pGuestPD);
2336
2337	Assert(pPDSrc);
2338	#ifndef IN_GC
2339	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2340	#endif
2341
2342	/*
2343	* Iterate the page directory.
2344	*/
2345	PPGMMAPPING pMapping;
2346	unsigned iPdNoMapping;
2347	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2348	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2349
2350	/* Only check mappings if they are supposed to be put into the shadow page table. */
2351	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2352	{
2353	pMapping = pVM->pgm.s.CTXSUFF(pMappings);
2354	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2355	}
2356	else
2357	{
2358	pMapping = 0;
2359	iPdNoMapping = ~0U;
2360	}
2361
2362	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2363	{
2364	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2365	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2366	# else
2367	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2368	# endif
2369	register VBOXPDE PdeSrc = pPDSrc->a[iPD];
2370	if ( PdeSrc.n.u1Present
2371	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2372	{
2373	/*
2374	* Check for conflicts with GC mappings.
2375	*/
2376	if (iPD == iPdNoMapping)
2377	{
2378	if (pVM->pgm.s.fMappingsFixed)
2379	{
2380	/* It's fixed, just skip the mapping. */
2381	const unsigned cPTs = pMapping->cPTs;
2382	iPD += cPTs - 1;
2383	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2384	pMapping = pMapping->CTXSUFF(pNext);
2385	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2386	continue;
2387	}
2388
2389	#ifdef IN_RING3
2390	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2391	if (VBOX_FAILURE(rc))
2392	return rc;
2393
2394	/*
2395	* Update iPdNoMapping and pMapping.
2396	*/
2397	pMapping = pVM->pgm.s.pMappingsHC;
2398	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2399	pMapping = pMapping->pNextHC;
2400	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2401	#else
2402	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2403	return VINF_PGM_SYNC_CR3;
2404	#endif
2405	}
2406
2407	/*
2408	* Sync page directory entry.
2409	*
2410	* The current approach is to allocated the page table but to set
2411	* the entry to not-present and postpone the page table synching till
2412	* it's actually used.
2413	*/
2414	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2415	const unsigned iPdShw = iPD; NOREF(iPdShw);
2416	# else
2417	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2418	# endif
2419	{
2420	SHWPDE PdeDst = *pPDEDst;
2421	if (PdeDst.n.u1Present)
2422	{
2423	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2424	RTGCPHYS GCPhys;
2425	if ( !PdeSrc.b.u1Size
2426	\|\| !(cr4 & X86_CR4_PSE))
2427	{
2428	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2429	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2430	GCPhys \|= i * (PAGE_SIZE / 2);
2431	# endif
2432	}
2433	else
2434	{
2435	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
2436	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2437	GCPhys \|= i * X86_PAGE_2M_SIZE;
2438	# endif
2439	}
2440
2441	if ( pShwPage->GCPhys == GCPhys
2442	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2443	&& ( pShwPage->fCached
2444	\|\| ( !fGlobal
2445	&& ( false
2446	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2447	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2448	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2449	\|\| ( !pShwPage->fSeenNonGlobal
2450	&& (cr4 & X86_CR4_PGE))
2451	# endif
2452	)
2453	)
2454	)
2455	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2456	\|\| ( (cr4 & X86_CR4_PSE)
2457	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2458	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2459	)
2460	)
2461	{
2462	# ifdef VBOX_WITH_STATISTICS
2463	if ( !fGlobal
2464	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2465	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2466	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2467	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2468	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2469	else
2470	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2471	# endif /* VBOX_WITH_STATISTICS */
2472	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2473	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2474	//# ifdef PGMPOOL_WITH_CACHE
2475	// pgmPoolCacheUsed(pPool, pShwPage);
2476	//# endif
2477	}
2478	else
2479	{
2480	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2481	pPDEDst->u = 0;
2482	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2483	}
2484	}
2485	else
2486	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2487	pPDEDst++;
2488	}
2489	}
2490	else if (iPD != iPdNoMapping)
2491	{
2492	/*
2493	* Check if there is any page directory to mark not present here.
2494	*/
2495	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2496	const unsigned iPdShw = iPD; NOREF(iPdShw);
2497	# else
2498	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2499	# endif
2500	{
2501	if (pPDEDst->n.u1Present)
2502	{
2503	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2504	pPDEDst->u = 0;
2505	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2506	}
2507	pPDEDst++;
2508	}
2509	}
2510	else
2511	{
2512	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2513	const unsigned cPTs = pMapping->cPTs;
2514	if (pVM->pgm.s.fMappingsFixed)
2515	{
2516	/* It's fixed, just skip the mapping. */
2517	pMapping = pMapping->CTXSUFF(pNext);
2518	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2519	}
2520	else
2521	{
2522	/*
2523	* Check for conflicts for subsequent pagetables
2524	* and advance to the next mapping.
2525	*/
2526	iPdNoMapping = ~0U;
2527	unsigned iPT = cPTs;
2528	while (iPT-- > 1)
2529	{
2530	if ( pPDSrc->a[iPD + iPT].n.u1Present
2531	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2532	{
2533	# ifdef IN_RING3
2534	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2535	if (VBOX_FAILURE(rc))
2536	return rc;
2537
2538	/*
2539	* Update iPdNoMapping and pMapping.
2540	*/
2541	pMapping = pVM->pgm.s.CTXSUFF(pMappings);
2542	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2543	pMapping = pMapping->CTXSUFF(pNext);
2544	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2545	break;
2546	# else
2547	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2548	return VINF_PGM_SYNC_CR3;
2549	# endif
2550	}
2551	}
2552	if (iPdNoMapping == ~0U && pMapping)
2553	{
2554	pMapping = pMapping->CTXSUFF(pNext);
2555	if (pMapping)
2556	iPdNoMapping = pMapping->GCPtr >> PGDIR_SHIFT;
2557	}
2558	}
2559	/* advance. */
2560	iPD += cPTs - 1;
2561	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2562	}
2563
2564	} /* for iPD */
2565	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2566	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2567	# endif
2568
2569	return VINF_SUCCESS;
2570
2571	#elif PGM_GST_TYPE == PGM_TYPE_PAE
2572	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2573	//# error not implemented
2574	return VERR_INTERNAL_ERROR;
2575
2576	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2577	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2578	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2579
2580	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2581	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2582	//# error not implemented
2583	return VERR_INTERNAL_ERROR;
2584
2585	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2586	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2587	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2588
2589	#else /* guest real and protected mode */
2590
2591	return VINF_SUCCESS;
2592	#endif
2593	}
2594
2595
2596
2597
2598	#ifdef VBOX_STRICT
2599	#ifdef IN_GC
2600	# undef AssertMsgFailed
2601	# define AssertMsgFailed Log
2602	#endif
2603	#ifdef IN_RING3
2604	# include <VBox/dbgf.h>
2605
2606	/**
2607	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2608	*
2609	* @returns VBox status code (VINF_SUCCESS).
2610	* @param pVM The VM handle.
2611	* @param cr3 The root of the hierarchy.
2612	* @param crr The cr4, only PAE and PSE is currently used.
2613	* @param fLongMode Set if long mode, false if not long mode.
2614	* @param cMaxDepth Number of levels to dump.
2615	* @param pHlp Pointer to the output functions.
2616	*/
2617	__BEGIN_DECLS
2618	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2619	__END_DECLS
2620
2621	#endif
2622
2623	/**
2624	* Checks that the shadow page table is in sync with the guest one.
2625	*
2626	* @returns The number of errors.
2627	* @param pVM The virtual machine.
2628	* @param cr3 Guest context CR3 register
2629	* @param cr4 Guest context CR4 register
2630	* @param GCPtr Where to start. Defaults to 0.
2631	* @param cb How much to check. Defaults to everything.
2632	*/
2633	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2634	{
2635	unsigned cErrors = 0;
2636
2637	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2638
2639	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2640	# error "Invalid shadow mode for 32-bit guest paging."
2641	# endif
2642
2643	PPGM pPGM = &pVM->pgm.s;
2644	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2645	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2646	RTHCPHYS HCPhys; /* general usage. */
2647	int rc;
2648
2649	/*
2650	* Check that the Guest CR3 and all it's mappings are correct.
2651	*/
2652	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & X86_CR3_PAGE_MASK),
2653	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2654	false);
2655	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2656	AssertRCReturn(rc, 1);
2657	rc = PGMRamGCPhys2HCPhys(pPGM, cr3 & X86_CR3_PAGE_MASK, &HCPhys);
2658	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2659	# ifndef IN_GC
2660	RTGCPHYS GCPhys;
2661	rc = PGMPhysHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2662	AssertRCReturn(rc, 1);
2663	AssertMsgReturn((cr3 & X86_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2664	# endif
2665	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2666
2667	/*
2668	* Get and check the Shadow CR3.
2669	*/
2670	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2671	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2672	unsigned cPDEs = ELEMENTS(pPDDst->a);
2673	# else
2674	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2675	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2676	# endif
2677	if (cb != ~(RTGCUINTPTR)0)
2678	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2679
2680	/** @todo call the other two PGMAssert() functions. /
2681
2682	/*
2683	* Iterate the shadow page directory.
2684	*/
2685	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2686	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2687	cPDEs += iPDDst;
2688	for (;
2689	iPDDst < cPDEs;
2690	iPDDst++, GCPtr += _4G / cPDEs)
2691	{
2692	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2693	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2694	{
2695	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2696	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2697	{
2698	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2699	cErrors++;
2700	continue;
2701	}
2702	}
2703	else if ( (PdeDst.u & X86_PDE_P)
2704	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2705	)
2706	{
2707	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2708	PPGMPOOLPAGE pPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2709	if (!pPage)
2710	{
2711	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2712	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2713	cErrors++;
2714	continue;
2715	}
2716	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPage);
2717
2718	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
2719	{
2720	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2721	GCPtr, (uint64_t)PdeDst.u));
2722	cErrors++;
2723	}
2724
2725	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
2726	{
2727	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2728	GCPtr, (uint64_t)PdeDst.u));
2729	cErrors++;
2730	}
2731
2732	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2733	if (!PdeSrc.n.u1Present)
2734	{
2735	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2736	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2737	cErrors++;
2738	continue;
2739	}
2740
2741	if ( !PdeSrc.b.u1Size
2742	\|\| !(cr4 & X86_CR4_PSE))
2743	{
2744	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
2745	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2746	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2747	# endif
2748	}
2749	else
2750	{
2751	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
2752	{
2753	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
2754	GCPtr, (uint64_t)PdeSrc.u));
2755	cErrors++;
2756	continue;
2757	}
2758	GCPhysGst = PdeSrc.u & GST_PDE4M_PG_MASK;
2759	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2760	GCPhysGst \|= GCPtr & BIT(X86_PAGE_2M_SHIFT);
2761	# endif
2762	}
2763
2764	if ( pPage->enmKind
2765	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
2766	{
2767	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
2768	pPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
2769	cErrors++;
2770	}
2771
2772	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
2773	if (VBOX_FAILURE(rc))
2774	{
2775	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
2776	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
2777	cErrors++;
2778	continue;
2779	}
2780
2781	if (GCPhysGst != pPage->GCPhys)
2782	{
2783	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
2784	GCPhysGst, pPage->GCPhys, GCPtr));
2785	cErrors++;
2786	continue;
2787	}
2788
2789	if ( !PdeSrc.b.u1Size
2790	\|\| !(cr4 & X86_CR4_PSE))
2791	{
2792	/*
2793	* Page Table.
2794	*/
2795	const GSTPT *pPTSrc;
2796	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
2797	if (VBOX_FAILURE(rc))
2798	{
2799	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
2800	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
2801	cErrors++;
2802	continue;
2803	}
2804	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
2805	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
2806	{
2807	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
2808	// (This problem will go away when/if we shadow multiple CR3s.)
2809	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
2810	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
2811	cErrors++;
2812	continue;
2813	}
2814	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
2815	{
2816	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
2817	GCPtr, (uint64_t)PdeDst.u));
2818	cErrors++;
2819	continue;
2820	}
2821
2822	/* iterate the page table. */
2823	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2824	const unsigned offPTSrc = 0;
2825	# else
2826	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
2827	# endif
2828	for (unsigned iPT = 0, off = 0;
2829	iPT < ELEMENTS(pPTDst->a);
2830	iPT++, off += PAGE_SIZE)
2831	{
2832	const SHWPTE PteDst = pPTDst->a[iPT];
2833
2834	/* skip not-present entries. */
2835	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
2836	continue;
2837	Assert(PteDst.n.u1Present);
2838
2839	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
2840	if (!PteSrc.n.u1Present)
2841	{
2842	#ifdef IN_RING3
2843	PGMAssertHandlerAndFlagsInSync(pVM);
2844	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
2845	#endif
2846	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
2847	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
2848	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
2849	cErrors++;
2850	continue;
2851	}
2852
2853	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
2854	# if 1 /** @todo sync accessed bit properly... */
2855	fIgnoreFlags \|= X86_PTE_A;
2856	# endif
2857
2858	/* match the physical addresses */
2859	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
2860	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
2861
2862	# ifdef IN_RING3
2863	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
2864	if (VBOX_FAILURE(rc))
2865	{
2866	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
2867	{
2868	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
2869	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2870	cErrors++;
2871	continue;
2872	}
2873	}
2874	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
2875	{
2876	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
2877	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2878	cErrors++;
2879	continue;
2880	}
2881	# endif
2882
2883	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
2884	if (VBOX_FAILURE(rc))
2885	{
2886	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
2887	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
2888	{
2889	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
2890	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2891	cErrors++;
2892	continue;
2893	}
2894	# endif
2895	if (PteDst.n.u1Write)
2896	{
2897	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
2898	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2899	cErrors++;
2900	}
2901	fIgnoreFlags \|= X86_PTE_RW;
2902	}
2903	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
2904	{
2905	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
2906	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2907	cErrors++;
2908	continue;
2909	}
2910
2911	/* flags */
2912	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
2913	{
2914	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
2915	{
2916	if (PteDst.n.u1Write)
2917	{
2918	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
2919	GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2920	cErrors++;
2921	continue;
2922	}
2923	fIgnoreFlags \|= X86_PTE_RW;
2924	}
2925	else
2926	{
2927	if (PteDst.n.u1Present)
2928	{
2929	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
2930	GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2931	cErrors++;
2932	continue;
2933	}
2934	fIgnoreFlags \|= X86_PTE_P;
2935	}
2936	}
2937	else
2938	{
2939	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
2940	{
2941	if (PteDst.n.u1Write)
2942	{
2943	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
2944	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2945	cErrors++;
2946	continue;
2947	}
2948	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
2949	{
2950	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
2951	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2952	cErrors++;
2953	continue;
2954	}
2955	if (PteDst.n.u1Dirty)
2956	{
2957	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
2958	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2959	cErrors++;
2960	}
2961	# if 0 /** @todo sync access bit properly... */
2962	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
2963	{
2964	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
2965	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2966	cErrors++;
2967	}
2968	fIgnoreFlags \|= X86_PTE_RW;
2969	# else
2970	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
2971	# endif
2972	}
2973	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
2974	{
2975	/* access bit emulation (not implemented). */
2976	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
2977	{
2978	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
2979	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2980	cErrors++;
2981	continue;
2982	}
2983	if (!PteDst.n.u1Accessed)
2984	{
2985	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
2986	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
2987	cErrors++;
2988	}
2989	fIgnoreFlags \|= X86_PTE_P;
2990	}
2991	# ifdef DEBUG_sandervl
2992	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
2993	# endif
2994	}
2995
2996	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
2997	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
2998	)
2999	{
3000	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3001	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3002	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3003	cErrors++;
3004	continue;
3005	}
3006	} /* foreach PTE */
3007	}
3008	else
3009	{
3010	/*
3011	* Big Page.
3012	*/
3013	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| X86_PDE_PAE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3014	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3015	{
3016	if (PdeDst.n.u1Write)
3017	{
3018	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3019	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3020	cErrors++;
3021	continue;
3022	}
3023	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3024	{
3025	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3026	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3027	cErrors++;
3028	continue;
3029	}
3030	# if 0 /** @todo sync access bit properly... */
3031	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3032	{
3033	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3034	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3035	cErrors++;
3036	}
3037	fIgnoreFlags \|= X86_PTE_RW;
3038	# else
3039	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3040	# endif
3041	}
3042	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3043	{
3044	/* access bit emulation (not implemented). */
3045	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3046	{
3047	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3048	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3049	cErrors++;
3050	continue;
3051	}
3052	if (!PdeDst.n.u1Accessed)
3053	{
3054	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3055	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3056	cErrors++;
3057	}
3058	fIgnoreFlags \|= X86_PTE_P;
3059	}
3060
3061	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3062	{
3063	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3064	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3065	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3066	cErrors++;
3067	}
3068
3069	/* iterate the page table. */
3070	for (unsigned iPT = 0, off = 0;
3071	iPT < ELEMENTS(pPTDst->a);
3072	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3073	{
3074	const SHWPTE PteDst = pPTDst->a[iPT];
3075
3076	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3077	{
3078	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3079	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3080	cErrors++;
3081	}
3082
3083	/* skip not-present entries. */
3084	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3085	continue;
3086
3087	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3088
3089	/* match the physical addresses */
3090	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3091
3092	# ifdef IN_RING3
3093	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3094	if (VBOX_FAILURE(rc))
3095	{
3096	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3097	{
3098	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3099	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3100	cErrors++;
3101	}
3102	}
3103	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3104	{
3105	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3106	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3107	cErrors++;
3108	continue;
3109	}
3110	# endif
3111
3112	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3113	if (VBOX_FAILURE(rc))
3114	{
3115	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3116	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3117	{
3118	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3119	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3120	cErrors++;
3121	continue;
3122	}
3123	# endif
3124	if (PteDst.n.u1Write)
3125	{
3126	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3127	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3128	cErrors++;
3129	}
3130	fIgnoreFlags \|= X86_PTE_RW;
3131	}
3132	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3133	{
3134	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3135	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3136	cErrors++;
3137	continue;
3138	}
3139
3140	/* flags */
3141	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3142	{
3143	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3144	{
3145	if (!(HCPhys & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF))
3146	{
3147	if (PteDst.n.u1Write)
3148	{
3149	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3150	GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3151	cErrors++;
3152	continue;
3153	}
3154	fIgnoreFlags \|= X86_PTE_RW;
3155	}
3156	}
3157	else
3158	{
3159	if (PteDst.n.u1Present)
3160	{
3161	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3162	GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3163	cErrors++;
3164	continue;
3165	}
3166	fIgnoreFlags \|= X86_PTE_P;
3167	}
3168	}
3169
3170	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3171	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3172	)
3173	{
3174	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3175	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3176	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3177	cErrors++;
3178	continue;
3179	}
3180	} /* foreach PTE */
3181	}
3182	}
3183	/* not present */
3184
3185	} /* forearch PDE */
3186
3187	# ifdef DEBUG
3188	if (cErrors)
3189	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3190	# endif
3191
3192	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3193	//# error not implemented
3194
3195
3196	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3197	//# error not implemented
3198
3199	/#else: guest real and protected mode /
3200	#endif
3201	return cErrors;
3202	}
3203	#endif /* VBOX_STRICT */
3204

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 1862

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