PGMAllBth.h@ 18666

Last change on this file since 18666 was 18666, checked in by vboxsync, 16 years ago
VMM: Clean out the VBOX_WITH_NEW_PHYS_CODE #ifdefs. (part 2)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 187.9 KB

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1	/* $Id: PGMAllBth.h 18666 2009-04-02 23:10:12Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVM VM Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	# if defined(IN_RC) && defined(VBOX_STRICT)
86	PGMDynCheckLocks(pVM);
87	# endif
88
89	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
90	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
91	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
92
93	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
94	/*
95	* Hide the instruction fetch trap indicator for now.
96	*/
97	/** @todo NXE will change this and we must fix NXE in the switcher too! */
98	if (uErr & X86_TRAP_PF_ID)
99	{
100	uErr &= ~X86_TRAP_PF_ID;
101	TRPMSetErrorCode(pVM, uErr);
102	}
103	# endif
104
105	/*
106	* Get PDs.
107	*/
108	int rc;
109	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
110	# if PGM_GST_TYPE == PGM_TYPE_32BIT
111	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
112	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
113
114	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
115
116	# if PGM_GST_TYPE == PGM_TYPE_PAE
117	unsigned iPDSrc;
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
122	unsigned iPDSrc;
123	PX86PML4E pPml4eSrc;
124	X86PDPE PdpeSrc;
125	PGSTPD pPDSrc;
126
127	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
128	Assert(pPml4eSrc);
129	# endif
130
131	/* Quick check for a valid guest trap. (PAE & AMD64) */
132	if (!pPDSrc)
133	{
134	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
135	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
136	# else
137	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK));
138	# endif
139	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
140	TRPMSetErrorCode(pVM, uErr);
141	return VINF_EM_RAW_GUEST_TRAP;
142	}
143	# endif
144
145	# else /* !PGM_WITH_PAGING */
146	PGSTPD pPDSrc = NULL;
147	const unsigned iPDSrc = 0;
148	# endif /* !PGM_WITH_PAGING */
149
150
151	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
152	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
153	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
154
155	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
156	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
157
158	PX86PDPAE pPDDst;
159	# if PGM_GST_TYPE != PGM_TYPE_PAE
160	X86PDPE PdpeSrc;
161
162	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
163	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
164	# endif
165	rc = pgmShwSyncPaePDPtr(pVM, pvFault, &PdpeSrc, &pPDDst);
166	if (rc != VINF_SUCCESS)
167	{
168	AssertRC(rc);
169	return rc;
170	}
171	Assert(pPDDst);
172
173	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
174	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
175	PX86PDPAE pPDDst;
176	# if PGM_GST_TYPE == PGM_TYPE_PROT
177	/* AMD-V nested paging */
178	X86PML4E Pml4eSrc;
179	X86PDPE PdpeSrc;
180	PX86PML4E pPml4eSrc = &Pml4eSrc;
181
182	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
183	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
184	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
185	# endif
186
187	rc = pgmShwSyncLongModePDPtr(pVM, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
188	if (rc != VINF_SUCCESS)
189	{
190	AssertRC(rc);
191	return rc;
192	}
193	Assert(pPDDst);
194
195	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
196	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
197	PEPTPD pPDDst;
198
199	rc = pgmShwGetEPTPDPtr(pVM, pvFault, NULL, &pPDDst);
200	if (rc != VINF_SUCCESS)
201	{
202	AssertRC(rc);
203	return rc;
204	}
205	Assert(pPDDst);
206	# endif
207
208	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
209	/*
210	* If we successfully correct the write protection fault due to dirty bit
211	* tracking, or this page fault is a genuine one, then return immediately.
212	*/
213	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
214	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
215	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
216	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
217	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
218	{
219	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
220	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVM->pgm.s.StatRZTrap0eTime2GuestTrap; });
221	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
222	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
223	}
224
225	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0ePD[iPDSrc]);
226	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
227
228	/*
229	* A common case is the not-present error caused by lazy page table syncing.
230	*
231	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
232	* so we can safely assume that the shadow PT is present when calling SyncPage later.
233	*
234	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
235	* of mapping conflict and defer to SyncCR3 in R3.
236	* (Again, we do NOT support access handlers for non-present guest pages.)
237	*
238	*/
239	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
240	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
241	# else
242	GSTPDE PdeSrc;
243	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
244	PdeSrc.n.u1Present = 1;
245	PdeSrc.n.u1Write = 1;
246	PdeSrc.n.u1Accessed = 1;
247	PdeSrc.n.u1User = 1;
248	# endif
249	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
250	&& !pPDDst->a[iPDDst].n.u1Present
251	&& PdeSrc.n.u1Present
252	)
253
254	{
255	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2SyncPT; });
256	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
257	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
258	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, pvFault);
259	if (RT_SUCCESS(rc))
260	{
261	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
262	return rc;
263	}
264	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
265	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
266	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeSyncPT, f);
267	return VINF_PGM_SYNC_CR3;
268	}
269
270	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
271	/*
272	* Check if this address is within any of our mappings.
273	*
274	* This is very fast and it's gonna save us a bit of effort below and prevent
275	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
276	* (BTW, it's impossible to have physical access handlers in a mapping.)
277	*/
278	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
279	{
280	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
281	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
282	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
283	{
284	if (pvFault < pMapping->GCPtr)
285	break;
286	if (pvFault - pMapping->GCPtr < pMapping->cb)
287	{
288	/*
289	* The first thing we check is if we've got an undetected conflict.
290	*/
291	if (!pVM->pgm.s.fMappingsFixed)
292	{
293	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
294	while (iPT-- > 0)
295	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
296	{
297	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eConflicts);
298	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
299	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
300	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
301	return VINF_PGM_SYNC_CR3;
302	}
303	}
304
305	/*
306	* Check if the fault address is in a virtual page access handler range.
307	*/
308	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
309	if ( pCur
310	&& pvFault - pCur->Core.Key < pCur->cb
311	&& uErr & X86_TRAP_PF_RW)
312	{
313	# ifdef IN_RC
314	STAM_PROFILE_START(&pCur->Stat, h);
315	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
316	STAM_PROFILE_STOP(&pCur->Stat, h);
317	# else
318	AssertFailed();
319	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
320	# endif
321	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersMapping);
322	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
323	return rc;
324	}
325
326	/*
327	* Pretend we're not here and let the guest handle the trap.
328	*/
329	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
330	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFMapping);
331	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
332	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
333	return VINF_EM_RAW_GUEST_TRAP;
334	}
335	}
336	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeMapping, a);
337	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
338	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
339
340	/*
341	* Check if this fault address is flagged for special treatment,
342	* which means we'll have to figure out the physical address and
343	* check flags associated with it.
344	*
345	* ASSUME that we can limit any special access handling to pages
346	* in page tables which the guest believes to be present.
347	*/
348	if (PdeSrc.n.u1Present)
349	{
350	RTGCPHYS GCPhys = NIL_RTGCPHYS;
351
352	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
353	# if PGM_GST_TYPE == PGM_TYPE_AMD64
354	bool fBigPagesSupported = true;
355	# else
356	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
357	# endif
358	if ( PdeSrc.b.u1Size
359	&& fBigPagesSupported)
360	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
361	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
362	else
363	{
364	PGSTPT pPTSrc;
365	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
366	if (RT_SUCCESS(rc))
367	{
368	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
369	if (pPTSrc->a[iPTESrc].n.u1Present)
370	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
371	}
372	}
373	# else
374	/* No paging so the fault address is the physical address */
375	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
376	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
377
378	/*
379	* If we have a GC address we'll check if it has any flags set.
380	*/
381	if (GCPhys != NIL_RTGCPHYS)
382	{
383	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
384
385	PPGMPAGE pPage;
386	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
387	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
388	{
389	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
390	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
391	{
392	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
393	{
394	/*
395	* Physical page access handler.
396	*/
397	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
398	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
399	if (pCur)
400	{
401	# ifdef PGM_SYNC_N_PAGES
402	/*
403	* If the region is write protected and we got a page not present fault, then sync
404	* the pages. If the fault was caused by a read, then restart the instruction.
405	* In case of write access continue to the GC write handler.
406	*
407	* ASSUMES that there is only one handler per page or that they have similar write properties.
408	*/
409	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
410	&& !(uErr & X86_TRAP_PF_P))
411	{
412	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
413	if ( RT_FAILURE(rc)
414	\|\| !(uErr & X86_TRAP_PF_RW)
415	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
416	{
417	AssertRC(rc);
418	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
419	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
420	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
421	return rc;
422	}
423	}
424	# endif
425
426	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
427	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
428	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
429
430	# if defined(IN_RC) \|\| defined(IN_RING0)
431	if (pCur->CTX_SUFF(pfnHandler))
432	{
433	STAM_PROFILE_START(&pCur->Stat, h);
434	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
435	STAM_PROFILE_STOP(&pCur->Stat, h);
436	}
437	else
438	# endif
439	rc = VINF_EM_RAW_EMULATE_INSTR;
440	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersPhysical);
441	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
442	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndPhys; });
443	return rc;
444	}
445	}
446	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
447	else
448	{
449	# ifdef PGM_SYNC_N_PAGES
450	/*
451	* If the region is write protected and we got a page not present fault, then sync
452	* the pages. If the fault was caused by a read, then restart the instruction.
453	* In case of write access continue to the GC write handler.
454	*/
455	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
456	&& !(uErr & X86_TRAP_PF_P))
457	{
458	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
459	if ( RT_FAILURE(rc)
460	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
461	\|\| !(uErr & X86_TRAP_PF_RW))
462	{
463	AssertRC(rc);
464	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
465	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
466	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
467	return rc;
468	}
469	}
470	# endif
471	/*
472	* Ok, it's an virtual page access handler.
473	*
474	* Since it's faster to search by address, we'll do that first
475	* and then retry by GCPhys if that fails.
476	*/
477	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
478	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
479	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
480	*/
481	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
482	if (pCur)
483	{
484	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
485	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
486	\|\| !(uErr & X86_TRAP_PF_P)
487	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
488	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
489
490	if ( pvFault - pCur->Core.Key < pCur->cb
491	&& ( uErr & X86_TRAP_PF_RW
492	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
493	{
494	# ifdef IN_RC
495	STAM_PROFILE_START(&pCur->Stat, h);
496	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
497	STAM_PROFILE_STOP(&pCur->Stat, h);
498	# else
499	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
500	# endif
501	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtual);
502	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
503	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
504	return rc;
505	}
506	/* Unhandled part of a monitored page */
507	}
508	else
509	{
510	/* Check by physical address. */
511	PPGMVIRTHANDLER pCur;
512	unsigned iPage;
513	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
514	&pCur, &iPage);
515	Assert(RT_SUCCESS(rc) \|\| !pCur);
516	if ( pCur
517	&& ( uErr & X86_TRAP_PF_RW
518	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
519	{
520	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
521	# ifdef IN_RC
522	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
523	Assert(off < pCur->cb);
524	STAM_PROFILE_START(&pCur->Stat, h);
525	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
526	STAM_PROFILE_STOP(&pCur->Stat, h);
527	# else
528	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
529	# endif
530	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
531	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
532	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
533	return rc;
534	}
535	}
536	}
537	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
538
539	/*
540	* There is a handled area of the page, but this fault doesn't belong to it.
541	* We must emulate the instruction.
542	*
543	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
544	* we first check if this was a page-not-present fault for a page with only
545	* write access handlers. Restart the instruction if it wasn't a write access.
546	*/
547	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersUnhandled);
548
549	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
550	&& !(uErr & X86_TRAP_PF_P))
551	{
552	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
553	if ( RT_FAILURE(rc)
554	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
555	\|\| !(uErr & X86_TRAP_PF_RW))
556	{
557	AssertRC(rc);
558	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersOutOfSync);
559	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
560	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
561	return rc;
562	}
563	}
564
565	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
566	* It's writing to an unhandled part of the LDT page several million times.
567	*/
568	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
569	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
570	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
571	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndUnhandled; });
572	return rc;
573	} /* if any kind of handler */
574
575	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
576	if (uErr & X86_TRAP_PF_P)
577	{
578	/*
579	* The page isn't marked, but it might still be monitored by a virtual page access handler.
580	* (ASSUMES no temporary disabling of virtual handlers.)
581	*/
582	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
583	* we should correct both the shadow page table and physical memory flags, and not only check for
584	* accesses within the handler region but for access to pages with virtual handlers. */
585	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
586	if (pCur)
587	{
588	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
589	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
590	\|\| !(uErr & X86_TRAP_PF_P)
591	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
592	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
593
594	if ( pvFault - pCur->Core.Key < pCur->cb
595	&& ( uErr & X86_TRAP_PF_RW
596	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
597	{
598	# ifdef IN_RC
599	STAM_PROFILE_START(&pCur->Stat, h);
600	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
601	STAM_PROFILE_STOP(&pCur->Stat, h);
602	# else
603	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
604	# endif
605	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
606	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
607	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2HndVirt; });
608	return rc;
609	}
610	}
611	}
612	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
613	}
614	else
615	{
616	/*
617	* When the guest accesses invalid physical memory (e.g. probing
618	* of RAM or accessing a remapped MMIO range), then we'll fall
619	* back to the recompiler to emulate the instruction.
620	*/
621	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
622	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eHandlersInvalid);
623	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
624	return VINF_EM_RAW_EMULATE_INSTR;
625	}
626
627	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeHandlers, b);
628
629	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
630	/*
631	* We are here only if page is present in Guest page tables and
632	* trap is not handled by our handlers.
633	*
634	* Check it for page out-of-sync situation.
635	*/
636	STAM_PROFILE_START(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
637
638	if (!(uErr & X86_TRAP_PF_P))
639	{
640	/*
641	* Page is not present in our page tables.
642	* Try to sync it!
643	* BTW, fPageShw is invalid in this branch!
644	*/
645	if (uErr & X86_TRAP_PF_US)
646	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
647	else /* supervisor */
648	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
649
650	# if defined(LOG_ENABLED) && !defined(IN_RING0)
651	RTGCPHYS GCPhys;
652	uint64_t fPageGst;
653	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
654	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
655	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
656	# endif /* LOG_ENABLED */
657
658	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
659	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
660	{
661	uint64_t fPageGst;
662	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
663	if ( RT_SUCCESS(rc)
664	&& !(fPageGst & X86_PTE_US))
665	{
666	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
667	if ( pvFault == (RTGCPTR)pRegFrame->eip
668	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
669	# ifdef CSAM_DETECT_NEW_CODE_PAGES
670	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
671	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
672	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
673	)
674	{
675	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
676	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
677	if (rc != VINF_SUCCESS)
678	{
679	/*
680	* CSAM needs to perform a job in ring 3.
681	*
682	* Sync the page before going to the host context; otherwise we'll end up in a loop if
683	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
684	*/
685	LogFlow(("CSAM ring 3 job\n"));
686	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
687	AssertRC(rc2);
688
689	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
690	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2CSAM; });
691	return rc;
692	}
693	}
694	# ifdef CSAM_DETECT_NEW_CODE_PAGES
695	else if ( uErr == X86_TRAP_PF_RW
696	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
697	&& pRegFrame->ecx < 0x10000)
698	{
699	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
700	* to detect loading of new code pages.
701	*/
702
703	/*
704	* Decode the instruction.
705	*/
706	RTGCPTR PC;
707	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
708	if (rc == VINF_SUCCESS)
709	{
710	DISCPUSTATE Cpu;
711	uint32_t cbOp;
712	rc = EMInterpretDisasOneEx(pVM, PC, pRegFrame, &Cpu, &cbOp);
713
714	/* For now we'll restrict this to rep movsw/d instructions */
715	if ( rc == VINF_SUCCESS
716	&& Cpu.pCurInstr->opcode == OP_MOVSWD
717	&& (Cpu.prefix & PREFIX_REP))
718	{
719	CSAMMarkPossibleCodePage(pVM, pvFault);
720	}
721	}
722	}
723	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
724
725	/*
726	* Mark this page as safe.
727	*/
728	/** @todo not correct for pages that contain both code and data!! */
729	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
730	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
731	}
732	}
733	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
734	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
735	if (RT_SUCCESS(rc))
736	{
737	/* The page was successfully synced, return to the guest. */
738	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
739	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSync; });
740	return VINF_SUCCESS;
741	}
742	}
743	else /* uErr & X86_TRAP_PF_P: */
744	{
745	/*
746	* Write protected pages is make writable when the guest makes the first
747	* write to it. This happens for pages that are shared, write monitored
748	* and not yet allocated.
749	*
750	* Also, a side effect of not flushing global PDEs are out of sync pages due
751	* to physical monitored regions, that are no longer valid.
752	* Assume for now it only applies to the read/write flag.
753	*/
754	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
755	{
756	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
757	{
758	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
759	GCPhys, pPage, pvFault, uErr));
760	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
761	if (rc != VINF_SUCCESS)
762	{
763	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
764	return rc;
765	}
766	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
767	return VINF_EM_NO_MEMORY;
768	}
769	/// @todo count the above case; else
770	if (uErr & X86_TRAP_PF_US)
771	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
772	else /* supervisor */
773	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
774
775	/*
776	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
777	* page is not present, which is not true in this case.
778	*/
779	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, pvFault, 1, uErr);
780	if (RT_SUCCESS(rc))
781	{
782	/*
783	* Page was successfully synced, return to guest.
784	*/
785	# ifdef VBOX_STRICT
786	RTGCPHYS GCPhys;
787	uint64_t fPageGst;
788	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
789	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
790	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
791
792	uint64_t fPageShw;
793	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
794	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
795	# endif /* VBOX_STRICT */
796	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
797	STAM_STATS({ pVM->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
798	return VINF_SUCCESS;
799	}
800
801	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
802	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
803	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
804	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
805	{
806	uint64_t fPageGst;
807	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
808	if ( RT_SUCCESS(rc)
809	&& !(fPageGst & X86_PTE_RW))
810	{
811	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
812	if (RT_SUCCESS(rc))
813	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulInRZ);
814	else
815	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eWPEmulToR3);
816	return rc;
817	}
818	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
819	}
820	}
821
822	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
823	# ifdef VBOX_STRICT
824	/*
825	* Check for VMM page flags vs. Guest page flags consistency.
826	* Currently only for debug purposes.
827	*/
828	if (RT_SUCCESS(rc))
829	{
830	/* Get guest page flags. */
831	uint64_t fPageGst;
832	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
833	if (RT_SUCCESS(rc))
834	{
835	uint64_t fPageShw;
836	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
837
838	/*
839	* Compare page flags.
840	* Note: we have AVL, A, D bits desynched.
841	*/
842	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
843	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
844	}
845	else
846	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
847	}
848	else
849	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
850	# endif /* VBOX_STRICT */
851	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
852	}
853	STAM_PROFILE_STOP(&pVM->pgm.s.StatRZTrap0eTimeOutOfSync, c);
854	# endif /* PGM_OUT_OF_SYNC_IN_GC */
855	}
856	else /* GCPhys == NIL_RTGCPHYS */
857	{
858	/*
859	* Page not present in Guest OS or invalid page table address.
860	* This is potential virtual page access handler food.
861	*
862	* For the present we'll say that our access handlers don't
863	* work for this case - we've already discarded the page table
864	* not present case which is identical to this.
865	*
866	* When we perchance find we need this, we will probably have AVL
867	* trees (offset based) to operate on and we can measure their speed
868	* agains mapping a page table and probably rearrange this handling
869	* a bit. (Like, searching virtual ranges before checking the
870	* physical address.)
871	*/
872	}
873	}
874	/* else: !present (guest) */
875
876
877	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
878	/*
879	* Conclusion, this is a guest trap.
880	*/
881	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
882	STAM_COUNTER_INC(&pVM->pgm.s.StatRZTrap0eGuestPFUnh);
883	return VINF_EM_RAW_GUEST_TRAP;
884	# else
885	/* present, but not a monitored page; perhaps the guest is probing physical memory */
886	return VINF_EM_RAW_EMULATE_INSTR;
887	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
888
889
890	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
891
892	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
893	return VERR_INTERNAL_ERROR;
894	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
895	}
896	#endif /* !IN_RING3 */
897
898
899	/**
900	* Emulation of the invlpg instruction.
901	*
902	*
903	* @returns VBox status code.
904	*
905	* @param pVM VM handle.
906	* @param GCPtrPage Page to invalidate.
907	*
908	* @remark ASSUMES that the guest is updating before invalidating. This order
909	* isn't required by the CPU, so this is speculative and could cause
910	* trouble.
911	*
912	* @todo Flush page or page directory only if necessary!
913	* @todo Add a #define for simply invalidating the page.
914	*/
915	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCPTR GCPtrPage)
916	{
917	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
918	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
919	&& PGM_SHW_TYPE != PGM_TYPE_EPT
920	int rc;
921
922	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
923	/*
924	* Get the shadow PD entry and skip out if this PD isn't present.
925	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
926	*/
927	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
928	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
929	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
930
931	/* Fetch the pgm pool shadow descriptor. */
932	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
933	Assert(pShwPde);
934
935	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
936	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
937	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
938
939	/* If the shadow PDPE isn't present, then skip the invalidate. */
940	if (!pPdptDst->a[iPdpt].n.u1Present)
941	{
942	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
943	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
944	return VINF_SUCCESS;
945	}
946
947	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
948	PPGMPOOLPAGE pShwPde;
949	PX86PDPAE pPDDst;
950
951	/* Fetch the pgm pool shadow descriptor. */
952	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
953	AssertRCSuccessReturn(rc, rc);
954	Assert(pShwPde);
955
956	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
957	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
958
959	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
960	/* PML4 */
961	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
962	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
963	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
964	PX86PDPAE pPDDst;
965	PX86PDPT pPdptDst;
966	PX86PML4E pPml4eDst;
967	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
968	if (rc != VINF_SUCCESS)
969	{
970	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
971	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
972	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
973	PGM_INVL_GUEST_TLBS();
974	return VINF_SUCCESS;
975	}
976	Assert(pPDDst);
977
978	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
979	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
980
981	if (!pPdpeDst->n.u1Present)
982	{
983	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
984	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
985	PGM_INVL_GUEST_TLBS();
986	return VINF_SUCCESS;
987	}
988
989	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
990
991	const SHWPDE PdeDst = *pPdeDst;
992	if (!PdeDst.n.u1Present)
993	{
994	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
995	return VINF_SUCCESS;
996	}
997
998	# if defined(IN_RC)
999	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1000	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1001	# endif
1002
1003	/*
1004	* Get the guest PD entry and calc big page.
1005	*/
1006	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1007	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
1008	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1009	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1010	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1011	unsigned iPDSrc;
1012	# if PGM_GST_TYPE == PGM_TYPE_PAE
1013	X86PDPE PdpeSrc;
1014	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1015	# else /* AMD64 */
1016	PX86PML4E pPml4eSrc;
1017	X86PDPE PdpeSrc;
1018	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1019	# endif
1020	GSTPDE PdeSrc;
1021
1022	if (pPDSrc)
1023	PdeSrc = pPDSrc->a[iPDSrc];
1024	else
1025	PdeSrc.u = 0;
1026	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1027
1028	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1029	const bool fIsBigPage = PdeSrc.b.u1Size;
1030	# else
1031	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1032	# endif
1033
1034	# ifdef IN_RING3
1035	/*
1036	* If a CR3 Sync is pending we may ignore the invalidate page operation
1037	* depending on the kind of sync and if it's a global page or not.
1038	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1039	*/
1040	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1041	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
1042	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
1043	&& fIsBigPage
1044	&& PdeSrc.b.u1Global
1045	)
1046	)
1047	# else
1048	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1049	# endif
1050	{
1051	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1052	return VINF_SUCCESS;
1053	}
1054	# endif /* IN_RING3 */
1055
1056	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1057	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1058
1059	/* Fetch the pgm pool shadow descriptor. */
1060	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1061	Assert(pShwPdpt);
1062
1063	/* Fetch the pgm pool shadow descriptor. */
1064	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1065	Assert(pShwPde);
1066
1067	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1068	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1069
1070	if ( !pPml4eSrc->n.u1Present
1071	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1072	{
1073	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1074	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1075	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1076	pPml4eDst->u = 0;
1077	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1078	PGM_INVL_GUEST_TLBS();
1079	return VINF_SUCCESS;
1080	}
1081	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1082	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1083	{
1084	/*
1085	* Mark not present so we can resync the PML4E when it's used.
1086	*/
1087	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1088	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1089	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1090	pPml4eDst->u = 0;
1091	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1092	PGM_INVL_GUEST_TLBS();
1093	}
1094	else if (!pPml4eSrc->n.u1Accessed)
1095	{
1096	/*
1097	* Mark not present so we can set the accessed bit.
1098	*/
1099	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1100	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1101	pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1102	pPml4eDst->u = 0;
1103	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1104	PGM_INVL_GUEST_TLBS();
1105	}
1106
1107	/* Check if the PDPT entry has changed. */
1108	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1109	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1110	if ( !PdpeSrc.n.u1Present
1111	\|\| pShwPde->GCPhys != GCPhysPd)
1112	{
1113	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1114	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1115	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1116	pPdpeDst->u = 0;
1117	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1118	PGM_INVL_GUEST_TLBS();
1119	return VINF_SUCCESS;
1120	}
1121	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1122	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1123	{
1124	/*
1125	* Mark not present so we can resync the PDPTE when it's used.
1126	*/
1127	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1128	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1129	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1130	pPdpeDst->u = 0;
1131	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1132	PGM_INVL_GUEST_TLBS();
1133	}
1134	else if (!PdpeSrc.lm.u1Accessed)
1135	{
1136	/*
1137	* Mark not present so we can set the accessed bit.
1138	*/
1139	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1140	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1141	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1142	pPdpeDst->u = 0;
1143	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1144	PGM_INVL_GUEST_TLBS();
1145	}
1146	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1147
1148
1149	/*
1150	* Deal with the Guest PDE.
1151	*/
1152	rc = VINF_SUCCESS;
1153	if (PdeSrc.n.u1Present)
1154	{
1155	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1156	{
1157	/*
1158	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1159	*/
1160	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1161	Assert(PGMGetGuestMode(pVM) <= PGMMODE_PAE);
1162	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
1163	}
1164	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1165	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1166	{
1167	/*
1168	* Mark not present so we can resync the PDE when it's used.
1169	*/
1170	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1171	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1172	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1173	pPdeDst->u = 0;
1174	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1175	PGM_INVL_GUEST_TLBS();
1176	}
1177	else if (!PdeSrc.n.u1Accessed)
1178	{
1179	/*
1180	* Mark not present so we can set the accessed bit.
1181	*/
1182	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1183	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1184	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1185	pPdeDst->u = 0;
1186	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1187	PGM_INVL_GUEST_TLBS();
1188	}
1189	else if (!fIsBigPage)
1190	{
1191	/*
1192	* 4KB - page.
1193	*/
1194	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1195	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1196	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1197	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1198	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1199	# endif
1200	if (pShwPage->GCPhys == GCPhys)
1201	{
1202	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1203	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1204	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1205	if (pPT->a[iPTEDst].n.u1Present)
1206	{
1207	# ifdef PGMPOOL_WITH_USER_TRACKING
1208	/* This is very unlikely with caching/monitoring enabled. */
1209	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1210	# endif
1211	pPT->a[iPTEDst].u = 0;
1212	}
1213	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1214	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
1215	if (RT_SUCCESS(rc))
1216	rc = VINF_SUCCESS;
1217	# endif
1218	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1219	PGM_INVL_PG(GCPtrPage);
1220	}
1221	else
1222	{
1223	/*
1224	* The page table address changed.
1225	*/
1226	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1227	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1228	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1229	pPdeDst->u = 0;
1230	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1231	PGM_INVL_GUEST_TLBS();
1232	}
1233	}
1234	else
1235	{
1236	/*
1237	* 2/4MB - page.
1238	*/
1239	/* Before freeing the page, check if anything really changed. */
1240	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1241	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1242	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1243	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1244	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1245	# endif
1246	if ( pShwPage->GCPhys == GCPhys
1247	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1248	{
1249	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1250	/** @todo PAT */
1251	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1252	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1253	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1254	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1255	{
1256	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1257	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1258	# if defined(IN_RC)
1259	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1260	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1261	# endif
1262	return VINF_SUCCESS;
1263	}
1264	}
1265
1266	/*
1267	* Ok, the page table is present and it's been changed in the guest.
1268	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1269	* We could do this for some flushes in GC too, but we need an algorithm for
1270	* deciding which 4MB pages containing code likely to be executed very soon.
1271	*/
1272	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1273	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1274	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1275	pPdeDst->u = 0;
1276	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1277	PGM_INVL_BIG_PG(GCPtrPage);
1278	}
1279	}
1280	else
1281	{
1282	/*
1283	* Page directory is not present, mark shadow PDE not present.
1284	*/
1285	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1286	{
1287	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1288	pPdeDst->u = 0;
1289	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1290	PGM_INVL_PG(GCPtrPage);
1291	}
1292	else
1293	{
1294	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1295	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1296	}
1297	}
1298	# if defined(IN_RC)
1299	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1300	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1301	# endif
1302	return rc;
1303
1304	#else /* guest real and protected mode */
1305	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1306	return VINF_SUCCESS;
1307	#endif
1308	}
1309
1310
1311	#ifdef PGMPOOL_WITH_USER_TRACKING
1312	/**
1313	* Update the tracking of shadowed pages.
1314	*
1315	* @param pVM The VM handle.
1316	* @param pShwPage The shadow page.
1317	* @param HCPhys The physical page we is being dereferenced.
1318	*/
1319	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1320	{
1321	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1322	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1323	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1324
1325	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1326	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1327	* 2. write protect all shadowed pages. I.e. implement caching.
1328	*/
1329	/*
1330	* Find the guest address.
1331	*/
1332	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1333	pRam;
1334	pRam = pRam->CTX_SUFF(pNext))
1335	{
1336	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1337	while (iPage-- > 0)
1338	{
1339	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1340	{
1341	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1342	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1343	pShwPage->cPresent--;
1344	pPool->cPresent--;
1345	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1346	return;
1347	}
1348	}
1349	}
1350
1351	for (;;)
1352	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1353	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1354	pShwPage->cPresent--;
1355	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1356	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1357	}
1358
1359
1360	/**
1361	* Update the tracking of shadowed pages.
1362	*
1363	* @param pVM The VM handle.
1364	* @param pShwPage The shadow page.
1365	* @param u16 The top 16-bit of the pPage->HCPhys.
1366	* @param pPage Pointer to the guest page. this will be modified.
1367	* @param iPTDst The index into the shadow table.
1368	*/
1369	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1370	{
1371	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1372	/*
1373	* Just deal with the simple first time here.
1374	*/
1375	if (!u16)
1376	{
1377	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1378	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1379	}
1380	else
1381	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1382
1383	/* write back */
1384	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1385	PGM_PAGE_SET_TRACKING(pPage, u16);
1386
1387	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1388
1389	/* update statistics. */
1390	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1391	pShwPage->cPresent++;
1392	if (pShwPage->iFirstPresent > iPTDst)
1393	pShwPage->iFirstPresent = iPTDst;
1394	}
1395	#endif /* PGMPOOL_WITH_USER_TRACKING */
1396
1397
1398	/**
1399	* Creates a 4K shadow page for a guest page.
1400	*
1401	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1402	* physical address. The PdeSrc argument only the flags are used. No page structured
1403	* will be mapped in this function.
1404	*
1405	* @param pVM VM handle.
1406	* @param pPteDst Destination page table entry.
1407	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1408	* Can safely assume that only the flags are being used.
1409	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1410	* @param pShwPage Pointer to the shadow page.
1411	* @param iPTDst The index into the shadow table.
1412	*
1413	* @remark Not used for 2/4MB pages!
1414	*/
1415	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1416	{
1417	if (PteSrc.n.u1Present)
1418	{
1419	/*
1420	* Find the ram range.
1421	*/
1422	PPGMPAGE pPage;
1423	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1424	if (RT_SUCCESS(rc))
1425	{
1426	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1427	/* Try make the page writable if necessary. */
1428	if ( PteSrc.n.u1Write
1429	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1430	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1431	{
1432	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1433	AssertRC(rc);
1434	}
1435	#endif
1436
1437	/** @todo investiage PWT, PCD and PAT. */
1438	/*
1439	* Make page table entry.
1440	*/
1441	SHWPTE PteDst;
1442	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1443	{
1444	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1445	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1446	{
1447	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1448	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1449	PteDst.n.u1Present = 1;
1450	PteDst.n.u1Execute = 1;
1451	PteDst.n.u1IgnorePAT = 1;
1452	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1453	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1454	#else
1455	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1456	\| PGM_PAGE_GET_HCPHYS(pPage);
1457	#endif
1458	}
1459	else
1460	{
1461	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1462	PteDst.u = 0;
1463	}
1464	/** @todo count these two kinds. */
1465	}
1466	else
1467	{
1468	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1469	/*
1470	* If the page or page directory entry is not marked accessed,
1471	* we mark the page not present.
1472	*/
1473	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1474	{
1475	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1476	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1477	PteDst.u = 0;
1478	}
1479	else
1480	/*
1481	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1482	* when the page is modified.
1483	*/
1484	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1485	{
1486	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1487	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1488	\| PGM_PAGE_GET_HCPHYS(pPage)
1489	\| PGM_PTFLAGS_TRACK_DIRTY;
1490	}
1491	else
1492	#endif
1493	{
1494	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1495	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1496	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1497	PteDst.n.u1Present = 1;
1498	PteDst.n.u1Write = 1;
1499	PteDst.n.u1Execute = 1;
1500	PteDst.n.u1IgnorePAT = 1;
1501	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1502	/* PteDst.n.u1Size = 0 */
1503	#else
1504	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1505	\| PGM_PAGE_GET_HCPHYS(pPage);
1506	#endif
1507	}
1508	}
1509
1510	/*
1511	* Make sure only allocated pages are mapped writable.
1512	*/
1513	if ( PteDst.n.u1Write
1514	&& PteDst.n.u1Present
1515	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1516	{
1517	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1518	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1519	}
1520
1521	#ifdef PGMPOOL_WITH_USER_TRACKING
1522	/*
1523	* Keep user track up to date.
1524	*/
1525	if (PteDst.n.u1Present)
1526	{
1527	if (!pPteDst->n.u1Present)
1528	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1529	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1530	{
1531	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1532	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1533	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1534	}
1535	}
1536	else if (pPteDst->n.u1Present)
1537	{
1538	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1539	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1540	}
1541	#endif /* PGMPOOL_WITH_USER_TRACKING */
1542
1543	/*
1544	* Update statistics and commit the entry.
1545	*/
1546	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1547	if (!PteSrc.n.u1Global)
1548	pShwPage->fSeenNonGlobal = true;
1549	#endif
1550	*pPteDst = PteDst;
1551	}
1552	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1553	/** @todo count these. */
1554	}
1555	else
1556	{
1557	/*
1558	* Page not-present.
1559	*/
1560	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1561	#ifdef PGMPOOL_WITH_USER_TRACKING
1562	/* Keep user track up to date. */
1563	if (pPteDst->n.u1Present)
1564	{
1565	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1566	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1567	}
1568	#endif /* PGMPOOL_WITH_USER_TRACKING */
1569	pPteDst->u = 0;
1570	/** @todo count these. */
1571	}
1572	}
1573
1574
1575	/**
1576	* Syncs a guest OS page.
1577	*
1578	* There are no conflicts at this point, neither is there any need for
1579	* page table allocations.
1580	*
1581	* @returns VBox status code.
1582	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1583	* @param pVM VM handle.
1584	* @param PdeSrc Page directory entry of the guest.
1585	* @param GCPtrPage Guest context page address.
1586	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1587	* @param uErr Fault error (X86_TRAP_PF_*).
1588	*/
1589	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1590	{
1591	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1592
1593	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1594	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1595	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1596	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1597	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1598
1599	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1600	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1601	# endif
1602
1603	/*
1604	* Assert preconditions.
1605	*/
1606	Assert(PdeSrc.n.u1Present);
1607	Assert(cPages);
1608	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1609
1610	/*
1611	* Get the shadow PDE, find the shadow page table in the pool.
1612	*/
1613	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1614	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1615	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
1616
1617	/* Fetch the pgm pool shadow descriptor. */
1618	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
1619	Assert(pShwPde);
1620
1621	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1622	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1623	PPGMPOOLPAGE pShwPde;
1624	PX86PDPAE pPDDst;
1625
1626	/* Fetch the pgm pool shadow descriptor. */
1627	int rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
1628	AssertRCSuccessReturn(rc, rc);
1629	Assert(pShwPde);
1630
1631	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1632	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1633
1634	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1635	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1636	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1637	PX86PDPAE pPDDst;
1638	PX86PDPT pPdptDst;
1639
1640	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1641	AssertRCSuccessReturn(rc, rc);
1642	Assert(pPDDst && pPdptDst);
1643	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1644	# endif
1645
1646	SHWPDE PdeDst = *pPdeDst;
1647	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1648	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1649
1650	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1651	/* Fetch the pgm pool shadow descriptor. */
1652	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1653	Assert(pShwPde);
1654	# endif
1655
1656	# if defined(IN_RC)
1657	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1658	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1659	# endif
1660
1661	/*
1662	* Check that the page is present and that the shadow PDE isn't out of sync.
1663	*/
1664	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1665	const bool fBigPage = PdeSrc.b.u1Size;
1666	# else
1667	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1668	# endif
1669	RTGCPHYS GCPhys;
1670	if (!fBigPage)
1671	{
1672	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1673	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1674	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1675	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1676	# endif
1677	}
1678	else
1679	{
1680	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1681	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1682	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1683	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1684	# endif
1685	}
1686	if ( pShwPage->GCPhys == GCPhys
1687	&& PdeSrc.n.u1Present
1688	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1689	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1690	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1691	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1692	# endif
1693	)
1694	{
1695	/*
1696	* Check that the PDE is marked accessed already.
1697	* Since we set the accessed bit before getting here on a #PF, this
1698	* check is only meant for dealing with non-#PF'ing paths.
1699	*/
1700	if (PdeSrc.n.u1Accessed)
1701	{
1702	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1703	if (!fBigPage)
1704	{
1705	/*
1706	* 4KB Page - Map the guest page table.
1707	*/
1708	PGSTPT pPTSrc;
1709	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1710	if (RT_SUCCESS(rc))
1711	{
1712	# ifdef PGM_SYNC_N_PAGES
1713	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1714	if ( cPages > 1
1715	&& !(uErr & X86_TRAP_PF_P)
1716	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1717	{
1718	/*
1719	* This code path is currently only taken when the caller is PGMTrap0eHandler
1720	* for non-present pages!
1721	*
1722	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1723	* deal with locality.
1724	*/
1725	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1726	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1727	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1728	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1729	# else
1730	const unsigned offPTSrc = 0;
1731	# endif
1732	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1733	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1734	iPTDst = 0;
1735	else
1736	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1737	for (; iPTDst < iPTDstEnd; iPTDst++)
1738	{
1739	if (!pPTDst->a[iPTDst].n.u1Present)
1740	{
1741	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1742	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1743	NOREF(GCPtrCurPage);
1744	#ifndef IN_RING0
1745	/*
1746	* Assuming kernel code will be marked as supervisor - and not as user level
1747	* and executed using a conforming code selector - And marked as readonly.
1748	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1749	*/
1750	PPGMPAGE pPage;
1751	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1752	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1753	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1754	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1755	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1756	)
1757	#endif /* else: CSAM not active */
1758	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1759	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1760	GCPtrCurPage, PteSrc.n.u1Present,
1761	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1762	PteSrc.n.u1User & PdeSrc.n.u1User,
1763	(uint64_t)PteSrc.u,
1764	(uint64_t)pPTDst->a[iPTDst].u,
1765	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1766	}
1767	}
1768	}
1769	else
1770	# endif /* PGM_SYNC_N_PAGES */
1771	{
1772	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1773	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1774	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1775	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1776	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1777	GCPtrPage, PteSrc.n.u1Present,
1778	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1779	PteSrc.n.u1User & PdeSrc.n.u1User,
1780	(uint64_t)PteSrc.u,
1781	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1782	}
1783	}
1784	else /* MMIO or invalid page: emulated in #PF handler. */
1785	{
1786	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1787	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1788	}
1789	}
1790	else
1791	{
1792	/*
1793	* 4/2MB page - lazy syncing shadow 4K pages.
1794	* (There are many causes of getting here, it's no longer only CSAM.)
1795	*/
1796	/* Calculate the GC physical address of this 4KB shadow page. */
1797	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1798	/* Find ram range. */
1799	PPGMPAGE pPage;
1800	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1801	if (RT_SUCCESS(rc))
1802	{
1803	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1804	/* Try make the page writable if necessary. */
1805	if ( PdeSrc.n.u1Write
1806	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1807	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1808	{
1809	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1810	AssertRC(rc);
1811	}
1812	# endif
1813
1814	/*
1815	* Make shadow PTE entry.
1816	*/
1817	SHWPTE PteDst;
1818	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1819	\| PGM_PAGE_GET_HCPHYS(pPage);
1820	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1821	{
1822	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1823	PteDst.n.u1Write = 0;
1824	else
1825	PteDst.u = 0;
1826	}
1827	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1828	# ifdef PGMPOOL_WITH_USER_TRACKING
1829	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1830	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1831	# endif
1832	/* Make sure only allocated pages are mapped writable. */
1833	if ( PteDst.n.u1Write
1834	&& PteDst.n.u1Present
1835	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1836	{
1837	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1838	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1839	}
1840
1841	pPTDst->a[iPTDst] = PteDst;
1842
1843
1844	/*
1845	* If the page is not flagged as dirty and is writable, then make it read-only
1846	* at PD level, so we can set the dirty bit when the page is modified.
1847	*
1848	* ASSUMES that page access handlers are implemented on page table entry level.
1849	* Thus we will first catch the dirty access and set PDE.D and restart. If
1850	* there is an access handler, we'll trap again and let it work on the problem.
1851	*/
1852	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1853	* As for invlpg, it simply frees the whole shadow PT.
1854	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1855	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1856	{
1857	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1858	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1859	PdeDst.n.u1Write = 0;
1860	}
1861	else
1862	{
1863	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1864	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1865	}
1866	*pPdeDst = PdeDst;
1867	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1868	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1869	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1870	}
1871	else
1872	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1873	}
1874	# if defined(IN_RC)
1875	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1876	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1877	# endif
1878	return VINF_SUCCESS;
1879	}
1880	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1881	}
1882	else
1883	{
1884	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1885	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1886	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1887	}
1888
1889	/*
1890	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1891	* Yea, I'm lazy.
1892	*/
1893	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1894	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1895
1896	pPdeDst->u = 0;
1897
1898	# if defined(IN_RC)
1899	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1900	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1901	# endif
1902	PGM_INVL_GUEST_TLBS();
1903	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1904
1905	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1906	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1907	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1908	&& !defined(IN_RC)
1909
1910	# ifdef PGM_SYNC_N_PAGES
1911	/*
1912	* Get the shadow PDE, find the shadow page table in the pool.
1913	*/
1914	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1915	X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
1916
1917	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1918	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVM->pgm.s, GCPtrPage);
1919
1920	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1921	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1922	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1923	PX86PDPAE pPDDst;
1924	X86PDEPAE PdeDst;
1925	PX86PDPT pPdptDst;
1926
1927	int rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1928	AssertRCSuccessReturn(rc, rc);
1929	Assert(pPDDst && pPdptDst);
1930	PdeDst = pPDDst->a[iPDDst];
1931	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1932	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1933	PEPTPD pPDDst;
1934	EPTPDE PdeDst;
1935
1936	int rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, NULL, &pPDDst);
1937	if (rc != VINF_SUCCESS)
1938	{
1939	AssertRC(rc);
1940	return rc;
1941	}
1942	Assert(pPDDst);
1943	PdeDst = pPDDst->a[iPDDst];
1944	# endif
1945	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1946	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1947	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1948
1949	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1950	if ( cPages > 1
1951	&& !(uErr & X86_TRAP_PF_P)
1952	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1953	{
1954	/*
1955	* This code path is currently only taken when the caller is PGMTrap0eHandler
1956	* for non-present pages!
1957	*
1958	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1959	* deal with locality.
1960	*/
1961	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1962	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1963	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1964	iPTDst = 0;
1965	else
1966	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1967	for (; iPTDst < iPTDstEnd; iPTDst++)
1968	{
1969	if (!pPTDst->a[iPTDst].n.u1Present)
1970	{
1971	GSTPTE PteSrc;
1972
1973	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1974
1975	/* Fake the page table entry */
1976	PteSrc.u = GCPtrCurPage;
1977	PteSrc.n.u1Present = 1;
1978	PteSrc.n.u1Dirty = 1;
1979	PteSrc.n.u1Accessed = 1;
1980	PteSrc.n.u1Write = 1;
1981	PteSrc.n.u1User = 1;
1982
1983	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1984
1985	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1986	GCPtrCurPage, PteSrc.n.u1Present,
1987	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1988	PteSrc.n.u1User & PdeSrc.n.u1User,
1989	(uint64_t)PteSrc.u,
1990	(uint64_t)pPTDst->a[iPTDst].u,
1991	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1992
1993	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
1994	break;
1995	}
1996	else
1997	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1998	}
1999	}
2000	else
2001	# endif /* PGM_SYNC_N_PAGES */
2002	{
2003	GSTPTE PteSrc;
2004	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2005	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2006
2007	/* Fake the page table entry */
2008	PteSrc.u = GCPtrCurPage;
2009	PteSrc.n.u1Present = 1;
2010	PteSrc.n.u1Dirty = 1;
2011	PteSrc.n.u1Accessed = 1;
2012	PteSrc.n.u1Write = 1;
2013	PteSrc.n.u1User = 1;
2014	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2015
2016	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2017	GCPtrPage, PteSrc.n.u1Present,
2018	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2019	PteSrc.n.u1User & PdeSrc.n.u1User,
2020	(uint64_t)PteSrc.u,
2021	(uint64_t)pPTDst->a[iPTDst].u,
2022	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2023	}
2024	return VINF_SUCCESS;
2025
2026	#else
2027	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2028	return VERR_INTERNAL_ERROR;
2029	#endif
2030	}
2031
2032
2033	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2034	/**
2035	* Investigate page fault and handle write protection page faults caused by
2036	* dirty bit tracking.
2037	*
2038	* @returns VBox status code.
2039	* @param pVM VM handle.
2040	* @param uErr Page fault error code.
2041	* @param pPdeDst Shadow page directory entry.
2042	* @param pPdeSrc Guest page directory entry.
2043	* @param GCPtrPage Guest context page address.
2044	*/
2045	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2046	{
2047	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
2048	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2049	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2050	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2051	bool fBigPagesSupported = true;
2052	# else
2053	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2054	# endif
2055	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2056	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
2057	# endif
2058	unsigned uPageFaultLevel;
2059	int rc;
2060
2061	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2062	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2063
2064	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2065	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2066
2067	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2068	PX86PML4E pPml4eSrc;
2069	PX86PDPE pPdpeSrc;
2070
2071	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
2072	Assert(pPml4eSrc);
2073
2074	/*
2075	* Real page fault? (PML4E level)
2076	*/
2077	if ( (uErr & X86_TRAP_PF_RSVD)
2078	\|\| !pPml4eSrc->n.u1Present
2079	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2080	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2081	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2082	)
2083	{
2084	uPageFaultLevel = 0;
2085	goto l_UpperLevelPageFault;
2086	}
2087	Assert(pPdpeSrc);
2088
2089	# else /* PAE */
2090	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVM->pgm.s, GCPtrPage);
2091	# endif /* PAE */
2092
2093	/*
2094	* Real page fault? (PDPE level)
2095	*/
2096	if ( (uErr & X86_TRAP_PF_RSVD)
2097	\|\| !pPdpeSrc->n.u1Present
2098	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2099	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2100	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2101	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2102	# endif
2103	)
2104	{
2105	uPageFaultLevel = 1;
2106	goto l_UpperLevelPageFault;
2107	}
2108	# endif
2109
2110	/*
2111	* Real page fault? (PDE level)
2112	*/
2113	if ( (uErr & X86_TRAP_PF_RSVD)
2114	\|\| !pPdeSrc->n.u1Present
2115	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2116	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2117	# endif
2118	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2119	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2120	{
2121	uPageFaultLevel = 2;
2122	goto l_UpperLevelPageFault;
2123	}
2124
2125	/*
2126	* First check the easy case where the page directory has been marked read-only to track
2127	* the dirty bit of an emulated BIG page
2128	*/
2129	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2130	{
2131	/* Mark guest page directory as accessed */
2132	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2133	pPml4eSrc->n.u1Accessed = 1;
2134	pPdpeSrc->lm.u1Accessed = 1;
2135	# endif
2136	pPdeSrc->b.u1Accessed = 1;
2137
2138	/*
2139	* Only write protection page faults are relevant here.
2140	*/
2141	if (fWriteFault)
2142	{
2143	/* Mark guest page directory as dirty (BIG page only). */
2144	pPdeSrc->b.u1Dirty = 1;
2145
2146	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2147	{
2148	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2149
2150	Assert(pPdeSrc->b.u1Write);
2151
2152	pPdeDst->n.u1Write = 1;
2153	pPdeDst->n.u1Accessed = 1;
2154	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2155	PGM_INVL_BIG_PG(GCPtrPage);
2156	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2157	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2158	}
2159	}
2160	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2161	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2162	}
2163	/* else: 4KB page table */
2164
2165	/*
2166	* Map the guest page table.
2167	*/
2168	PGSTPT pPTSrc;
2169	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2170	if (RT_SUCCESS(rc))
2171	{
2172	/*
2173	* Real page fault?
2174	*/
2175	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2176	const GSTPTE PteSrc = *pPteSrc;
2177	if ( !PteSrc.n.u1Present
2178	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2179	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2180	# endif
2181	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2182	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2183	)
2184	{
2185	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2186	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2187	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2188
2189	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2190	* See the 2nd case above as well.
2191	*/
2192	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2193	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2194
2195	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2196	return VINF_EM_RAW_GUEST_TRAP;
2197	}
2198	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2199
2200	/*
2201	* Set the accessed bits in the page directory and the page table.
2202	*/
2203	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2204	pPml4eSrc->n.u1Accessed = 1;
2205	pPdpeSrc->lm.u1Accessed = 1;
2206	# endif
2207	pPdeSrc->n.u1Accessed = 1;
2208	pPteSrc->n.u1Accessed = 1;
2209
2210	/*
2211	* Only write protection page faults are relevant here.
2212	*/
2213	if (fWriteFault)
2214	{
2215	/* Write access, so mark guest entry as dirty. */
2216	# ifdef VBOX_WITH_STATISTICS
2217	if (!pPteSrc->n.u1Dirty)
2218	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2219	else
2220	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2221	# endif
2222
2223	pPteSrc->n.u1Dirty = 1;
2224
2225	if (pPdeDst->n.u1Present)
2226	{
2227	#ifndef IN_RING0
2228	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2229	* Our individual shadow handlers will provide more information and force a fatal exit.
2230	*/
2231	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2232	{
2233	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2234	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2235	return VINF_SUCCESS;
2236	}
2237	#endif
2238	/*
2239	* Map shadow page table.
2240	*/
2241	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2242	if (pShwPage)
2243	{
2244	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2245	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2246	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2247	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2248	{
2249	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2250	# ifdef VBOX_STRICT
2251	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2252	if (pPage)
2253	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2254	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2255	# endif
2256	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2257
2258	Assert(pPteSrc->n.u1Write);
2259
2260	pPteDst->n.u1Write = 1;
2261	pPteDst->n.u1Dirty = 1;
2262	pPteDst->n.u1Accessed = 1;
2263	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2264	PGM_INVL_PG(GCPtrPage);
2265
2266	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2267	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2268	}
2269	}
2270	else
2271	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2272	}
2273	}
2274	/** @todo Optimize accessed bit emulation? */
2275	# ifdef VBOX_STRICT
2276	/*
2277	* Sanity check.
2278	*/
2279	else if ( !pPteSrc->n.u1Dirty
2280	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2281	&& pPdeDst->n.u1Present)
2282	{
2283	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2284	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2285	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2286	if ( pPteDst->n.u1Present
2287	&& pPteDst->n.u1Write)
2288	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2289	}
2290	# endif /* VBOX_STRICT */
2291	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2292	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2293	}
2294	AssertRC(rc);
2295	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2296	return rc;
2297
2298
2299	l_UpperLevelPageFault:
2300	/*
2301	* Pagefault detected while checking the PML4E, PDPE or PDE.
2302	* Single exit handler to get rid of duplicate code paths.
2303	*/
2304	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2305	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2306	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2307
2308	if (
2309	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2310	pPml4eSrc->n.u1Present &&
2311	# endif
2312	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2313	pPdpeSrc->n.u1Present &&
2314	# endif
2315	pPdeSrc->n.u1Present)
2316	{
2317	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2318	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2319	{
2320	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2321	}
2322	else
2323	{
2324	/*
2325	* Map the guest page table.
2326	*/
2327	PGSTPT pPTSrc;
2328	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2329	if (RT_SUCCESS(rc))
2330	{
2331	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2332	const GSTPTE PteSrc = *pPteSrc;
2333	if (pPteSrc->n.u1Present)
2334	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2335	}
2336	AssertRC(rc);
2337	}
2338	}
2339	return VINF_EM_RAW_GUEST_TRAP;
2340	}
2341	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2342
2343
2344	/**
2345	* Sync a shadow page table.
2346	*
2347	* The shadow page table is not present. This includes the case where
2348	* there is a conflict with a mapping.
2349	*
2350	* @returns VBox status code.
2351	* @param pVM VM handle.
2352	* @param iPD Page directory index.
2353	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2354	* Assume this is a temporary mapping.
2355	* @param GCPtrPage GC Pointer of the page that caused the fault
2356	*/
2357	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2358	{
2359	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2360	STAM_COUNTER_INC(&pVM->pgm.s.StatSyncPtPD[iPDSrc]);
2361	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2362
2363	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2364	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2365	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2366	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2367	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2368
2369	int rc = VINF_SUCCESS;
2370
2371	/*
2372	* Validate input a little bit.
2373	*/
2374	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2375	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2376	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2377	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2378
2379	/* Fetch the pgm pool shadow descriptor. */
2380	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2381	Assert(pShwPde);
2382
2383	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2384	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2385	PPGMPOOLPAGE pShwPde;
2386	PX86PDPAE pPDDst;
2387	PSHWPDE pPdeDst;
2388
2389	/* Fetch the pgm pool shadow descriptor. */
2390	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2391	AssertRCSuccessReturn(rc, rc);
2392	Assert(pShwPde);
2393
2394	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2395	pPdeDst = &pPDDst->a[iPDDst];
2396
2397	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2398	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2399	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2400	PX86PDPAE pPDDst;
2401	PX86PDPT pPdptDst;
2402	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2403	AssertRCSuccessReturn(rc, rc);
2404	Assert(pPDDst);
2405	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2406	# endif
2407	SHWPDE PdeDst = *pPdeDst;
2408
2409	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2410	/* Fetch the pgm pool shadow descriptor. */
2411	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2412	Assert(pShwPde);
2413	# endif
2414
2415	# ifndef PGM_WITHOUT_MAPPINGS
2416	/*
2417	* Check for conflicts.
2418	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2419	* HC: Simply resolve the conflict.
2420	*/
2421	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2422	{
2423	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2424	# ifndef IN_RING3
2425	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2426	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2427	return VERR_ADDRESS_CONFLICT;
2428	# else
2429	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2430	Assert(pMapping);
2431	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2432	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2433	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2434	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2435	# else
2436	AssertFailed(); /* can't happen for amd64 */
2437	# endif
2438	if (RT_FAILURE(rc))
2439	{
2440	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2441	return rc;
2442	}
2443	PdeDst = *pPdeDst;
2444	# endif
2445	}
2446	# else /* PGM_WITHOUT_MAPPINGS */
2447	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2448	# endif /* PGM_WITHOUT_MAPPINGS */
2449	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2450
2451	# if defined(IN_RC)
2452	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2453	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2454	# endif
2455
2456	/*
2457	* Sync page directory entry.
2458	*/
2459	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2460	if (PdeSrc.n.u1Present)
2461	{
2462	/*
2463	* Allocate & map the page table.
2464	*/
2465	PSHWPT pPTDst;
2466	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2467	const bool fPageTable = !PdeSrc.b.u1Size;
2468	# else
2469	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2470	# endif
2471	PPGMPOOLPAGE pShwPage;
2472	RTGCPHYS GCPhys;
2473	if (fPageTable)
2474	{
2475	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2476	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2477	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2478	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2479	# endif
2480	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2481	}
2482	else
2483	{
2484	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2485	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2486	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2487	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2488	# endif
2489	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2490	}
2491	if (rc == VINF_SUCCESS)
2492	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2493	else if (rc == VINF_PGM_CACHED_PAGE)
2494	{
2495	/*
2496	* The PT was cached, just hook it up.
2497	*/
2498	if (fPageTable)
2499	PdeDst.u = pShwPage->Core.Key
2500	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2501	else
2502	{
2503	PdeDst.u = pShwPage->Core.Key
2504	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2505	/* (see explanation and assumptions further down.) */
2506	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2507	{
2508	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2509	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2510	PdeDst.b.u1Write = 0;
2511	}
2512	}
2513	*pPdeDst = PdeDst;
2514	# if defined(IN_RC)
2515	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2516	# endif
2517	return VINF_SUCCESS;
2518	}
2519	else if (rc == VERR_PGM_POOL_FLUSHED)
2520	{
2521	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2522	# if defined(IN_RC)
2523	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2524	# endif
2525	return VINF_PGM_SYNC_CR3;
2526	}
2527	else
2528	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2529	PdeDst.u &= X86_PDE_AVL_MASK;
2530	PdeDst.u \|= pShwPage->Core.Key;
2531
2532	/*
2533	* Page directory has been accessed (this is a fault situation, remember).
2534	*/
2535	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2536	if (fPageTable)
2537	{
2538	/*
2539	* Page table - 4KB.
2540	*
2541	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2542	*/
2543	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2544	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2545	PGSTPT pPTSrc;
2546	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2547	if (RT_SUCCESS(rc))
2548	{
2549	/*
2550	* Start by syncing the page directory entry so CSAM's TLB trick works.
2551	*/
2552	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2553	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2554	*pPdeDst = PdeDst;
2555	# if defined(IN_RC)
2556	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2557	# endif
2558
2559	/*
2560	* Directory/page user or supervisor privilege: (same goes for read/write)
2561	*
2562	* Directory Page Combined
2563	* U/S U/S U/S
2564	* 0 0 0
2565	* 0 1 0
2566	* 1 0 0
2567	* 1 1 1
2568	*
2569	* Simple AND operation. Table listed for completeness.
2570	*
2571	*/
2572	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2573	# ifdef PGM_SYNC_N_PAGES
2574	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2575	unsigned iPTDst = iPTBase;
2576	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2577	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2578	iPTDst = 0;
2579	else
2580	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2581	# else /* !PGM_SYNC_N_PAGES */
2582	unsigned iPTDst = 0;
2583	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2584	# endif /* !PGM_SYNC_N_PAGES */
2585	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2586	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2587	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2588	# else
2589	const unsigned offPTSrc = 0;
2590	# endif
2591	for (; iPTDst < iPTDstEnd; iPTDst++)
2592	{
2593	const unsigned iPTSrc = iPTDst + offPTSrc;
2594	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2595
2596	if (PteSrc.n.u1Present) /* we've already cleared it above */
2597	{
2598	# ifndef IN_RING0
2599	/*
2600	* Assuming kernel code will be marked as supervisor - and not as user level
2601	* and executed using a conforming code selector - And marked as readonly.
2602	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2603	*/
2604	PPGMPAGE pPage;
2605	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2606	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2607	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2608	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2609	)
2610	# endif
2611	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2612	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2613	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2614	PteSrc.n.u1Present,
2615	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2616	PteSrc.n.u1User & PdeSrc.n.u1User,
2617	(uint64_t)PteSrc.u,
2618	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2619	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2620	}
2621	} /* for PTEs */
2622	}
2623	}
2624	else
2625	{
2626	/*
2627	* Big page - 2/4MB.
2628	*
2629	* We'll walk the ram range list in parallel and optimize lookups.
2630	* We will only sync on shadow page table at a time.
2631	*/
2632	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2633
2634	/**
2635	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2636	*/
2637
2638	/*
2639	* Start by syncing the page directory entry.
2640	*/
2641	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2642	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2643
2644	/*
2645	* If the page is not flagged as dirty and is writable, then make it read-only
2646	* at PD level, so we can set the dirty bit when the page is modified.
2647	*
2648	* ASSUMES that page access handlers are implemented on page table entry level.
2649	* Thus we will first catch the dirty access and set PDE.D and restart. If
2650	* there is an access handler, we'll trap again and let it work on the problem.
2651	*/
2652	/** @todo move the above stuff to a section in the PGM documentation. */
2653	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2654	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2655	{
2656	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2657	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2658	PdeDst.b.u1Write = 0;
2659	}
2660	*pPdeDst = PdeDst;
2661	# if defined(IN_RC)
2662	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2663	# endif
2664
2665	/*
2666	* Fill the shadow page table.
2667	*/
2668	/* Get address and flags from the source PDE. */
2669	SHWPTE PteDstBase;
2670	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2671
2672	/* Loop thru the entries in the shadow PT. */
2673	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2674	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2675	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2676	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2677	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2678	unsigned iPTDst = 0;
2679	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2680	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2681	{
2682	/* Advance ram range list. */
2683	while (pRam && GCPhys > pRam->GCPhysLast)
2684	pRam = pRam->CTX_SUFF(pNext);
2685	if (pRam && GCPhys >= pRam->GCPhys)
2686	{
2687	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2688	do
2689	{
2690	/* Make shadow PTE. */
2691	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2692	SHWPTE PteDst;
2693
2694	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2695	/* Try make the page writable if necessary. */
2696	if ( PteDstBase.n.u1Write
2697	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2698	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2699	{
2700	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2701	AssertRCReturn(rc, rc);
2702	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2703	break;
2704	}
2705	# endif
2706
2707	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2708	{
2709	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2710	{
2711	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2712	PteDst.n.u1Write = 0;
2713	}
2714	else
2715	PteDst.u = 0;
2716	}
2717	# ifndef IN_RING0
2718	/*
2719	* Assuming kernel code will be marked as supervisor and not as user level and executed
2720	* using a conforming code selector. Don't check for readonly, as that implies the whole
2721	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2722	*/
2723	else if ( !PdeSrc.n.u1User
2724	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2725	PteDst.u = 0;
2726	# endif
2727	else
2728	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2729
2730	/* Only map writable pages writable. */
2731	if ( PteDst.n.u1Write
2732	&& PteDst.n.u1Present
2733	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2734	{
2735	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2736	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2737	}
2738
2739	# ifdef PGMPOOL_WITH_USER_TRACKING
2740	if (PteDst.n.u1Present)
2741	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2742	# endif
2743	/* commit it */
2744	pPTDst->a[iPTDst] = PteDst;
2745	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2746	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2747	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2748
2749	/* advance */
2750	GCPhys += PAGE_SIZE;
2751	iHCPage++;
2752	iPTDst++;
2753	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2754	&& GCPhys <= pRam->GCPhysLast);
2755	}
2756	else if (pRam)
2757	{
2758	Log(("Invalid pages at %RGp\n", GCPhys));
2759	do
2760	{
2761	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2762	GCPhys += PAGE_SIZE;
2763	iPTDst++;
2764	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2765	&& GCPhys < pRam->GCPhys);
2766	}
2767	else
2768	{
2769	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2770	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2771	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2772	}
2773	} /* while more PTEs */
2774	} /* 4KB / 4MB */
2775	}
2776	else
2777	AssertRelease(!PdeDst.n.u1Present);
2778
2779	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2780	if (RT_FAILURE(rc))
2781	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2782	return rc;
2783
2784	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2785	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2786	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2787	&& !defined(IN_RC)
2788
2789	/*
2790	* Validate input a little bit.
2791	*/
2792	int rc = VINF_SUCCESS;
2793	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2794	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2795	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
2796
2797	/* Fetch the pgm pool shadow descriptor. */
2798	PPGMPOOLPAGE pShwPde = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
2799	Assert(pShwPde);
2800
2801	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2802	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2803	PPGMPOOLPAGE pShwPde;
2804	PX86PDPAE pPDDst;
2805	PSHWPDE pPdeDst;
2806
2807	/* Fetch the pgm pool shadow descriptor. */
2808	rc = pgmShwGetPaePoolPagePD(&pVM->pgm.s, GCPtrPage, &pShwPde);
2809	AssertRCSuccessReturn(rc, rc);
2810	Assert(pShwPde);
2811
2812	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2813	pPdeDst = &pPDDst->a[iPDDst];
2814
2815	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2816	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2817	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2818	PX86PDPAE pPDDst;
2819	PX86PDPT pPdptDst;
2820	rc = pgmShwGetLongModePDPtr(pVM, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2821	AssertRCSuccessReturn(rc, rc);
2822	Assert(pPDDst);
2823	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2824
2825	/* Fetch the pgm pool shadow descriptor. */
2826	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2827	Assert(pShwPde);
2828
2829	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2830	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2831	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2832	PEPTPD pPDDst;
2833	PEPTPDPT pPdptDst;
2834
2835	rc = pgmShwGetEPTPDPtr(pVM, GCPtrPage, &pPdptDst, &pPDDst);
2836	if (rc != VINF_SUCCESS)
2837	{
2838	AssertRC(rc);
2839	return rc;
2840	}
2841	Assert(pPDDst);
2842	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2843
2844	/* Fetch the pgm pool shadow descriptor. */
2845	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2846	Assert(pShwPde);
2847	# endif
2848	SHWPDE PdeDst = *pPdeDst;
2849
2850	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2851	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2852
2853	GSTPDE PdeSrc;
2854	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2855	PdeSrc.n.u1Present = 1;
2856	PdeSrc.n.u1Write = 1;
2857	PdeSrc.n.u1Accessed = 1;
2858	PdeSrc.n.u1User = 1;
2859
2860	/*
2861	* Allocate & map the page table.
2862	*/
2863	PSHWPT pPTDst;
2864	PPGMPOOLPAGE pShwPage;
2865	RTGCPHYS GCPhys;
2866
2867	/* Virtual address = physical address */
2868	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2869	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2870
2871	if ( rc == VINF_SUCCESS
2872	\|\| rc == VINF_PGM_CACHED_PAGE)
2873	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2874	else
2875	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2876
2877	PdeDst.u &= X86_PDE_AVL_MASK;
2878	PdeDst.u \|= pShwPage->Core.Key;
2879	PdeDst.n.u1Present = 1;
2880	PdeDst.n.u1Write = 1;
2881	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2882	PdeDst.n.u1Execute = 1;
2883	# else
2884	PdeDst.n.u1User = 1;
2885	PdeDst.n.u1Accessed = 1;
2886	# endif
2887	*pPdeDst = PdeDst;
2888
2889	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2890	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2891	return rc;
2892
2893	#else
2894	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2895	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2896	return VERR_INTERNAL_ERROR;
2897	#endif
2898	}
2899
2900
2901
2902	/**
2903	* Prefetch a page/set of pages.
2904	*
2905	* Typically used to sync commonly used pages before entering raw mode
2906	* after a CR3 reload.
2907	*
2908	* @returns VBox status code.
2909	* @param pVM VM handle.
2910	* @param GCPtrPage Page to invalidate.
2911	*/
2912	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCPTR GCPtrPage)
2913	{
2914	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2915	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2916	/*
2917	* Check that all Guest levels thru the PDE are present, getting the
2918	* PD and PDE in the processes.
2919	*/
2920	int rc = VINF_SUCCESS;
2921	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2922	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2923	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2924	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
2925	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2926	unsigned iPDSrc;
2927	X86PDPE PdpeSrc;
2928	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
2929	if (!pPDSrc)
2930	return VINF_SUCCESS; /* not present */
2931	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2932	unsigned iPDSrc;
2933	PX86PML4E pPml4eSrc;
2934	X86PDPE PdpeSrc;
2935	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2936	if (!pPDSrc)
2937	return VINF_SUCCESS; /* not present */
2938	# endif
2939	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2940	# else
2941	PGSTPD pPDSrc = NULL;
2942	const unsigned iPDSrc = 0;
2943	GSTPDE PdeSrc;
2944
2945	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2946	PdeSrc.n.u1Present = 1;
2947	PdeSrc.n.u1Write = 1;
2948	PdeSrc.n.u1Accessed = 1;
2949	PdeSrc.n.u1User = 1;
2950	# endif
2951
2952	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2953	{
2954	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2955	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVM->pgm.s, GCPtrPage);
2956	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2957	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2958	PX86PDPAE pPDDst;
2959	X86PDEPAE PdeDst;
2960	# if PGM_GST_TYPE != PGM_TYPE_PAE
2961	X86PDPE PdpeSrc;
2962
2963	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
2964	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
2965	# endif
2966	int rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
2967	if (rc != VINF_SUCCESS)
2968	{
2969	AssertRC(rc);
2970	return rc;
2971	}
2972	Assert(pPDDst);
2973	PdeDst = pPDDst->a[iPDDst];
2974
2975	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2976	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2977	PX86PDPAE pPDDst;
2978	X86PDEPAE PdeDst;
2979
2980	# if PGM_GST_TYPE == PGM_TYPE_PROT
2981	/* AMD-V nested paging */
2982	X86PML4E Pml4eSrc;
2983	X86PDPE PdpeSrc;
2984	PX86PML4E pPml4eSrc = &Pml4eSrc;
2985
2986	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2987	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2988	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2989	# endif
2990
2991	int rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
2992	if (rc != VINF_SUCCESS)
2993	{
2994	AssertRC(rc);
2995	return rc;
2996	}
2997	Assert(pPDDst);
2998	PdeDst = pPDDst->a[iPDDst];
2999	# endif
3000	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3001	{
3002	if (!PdeDst.n.u1Present)
3003	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3004	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3005	else
3006	{
3007	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3008	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3009	* makes no sense to prefetch more than one page.
3010	*/
3011	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3012	if (RT_SUCCESS(rc))
3013	rc = VINF_SUCCESS;
3014	}
3015	}
3016	}
3017	return rc;
3018
3019	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3020	return VINF_SUCCESS; /* ignore */
3021	#endif
3022	}
3023
3024
3025
3026
3027	/**
3028	* Syncs a page during a PGMVerifyAccess() call.
3029	*
3030	* @returns VBox status code (informational included).
3031	* @param GCPtrPage The address of the page to sync.
3032	* @param fPage The effective guest page flags.
3033	* @param uErr The trap error code.
3034	*/
3035	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3036	{
3037	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3038
3039	Assert(!HWACCMIsNestedPagingActive(pVM));
3040	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3041	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3042
3043	# ifndef IN_RING0
3044	if (!(fPage & X86_PTE_US))
3045	{
3046	/*
3047	* Mark this page as safe.
3048	*/
3049	/** @todo not correct for pages that contain both code and data!! */
3050	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3051	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3052	}
3053	# endif
3054
3055	/*
3056	* Get guest PD and index.
3057	*/
3058	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3059	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3060	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3061	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3062	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3063	unsigned iPDSrc;
3064	X86PDPE PdpeSrc;
3065	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3066
3067	if (pPDSrc)
3068	{
3069	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3070	return VINF_EM_RAW_GUEST_TRAP;
3071	}
3072	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3073	unsigned iPDSrc;
3074	PX86PML4E pPml4eSrc;
3075	X86PDPE PdpeSrc;
3076	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3077	if (!pPDSrc)
3078	{
3079	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3080	return VINF_EM_RAW_GUEST_TRAP;
3081	}
3082	# endif
3083	# else
3084	PGSTPD pPDSrc = NULL;
3085	const unsigned iPDSrc = 0;
3086	# endif
3087	int rc = VINF_SUCCESS;
3088
3089	/*
3090	* First check if the shadow pd is present.
3091	*/
3092	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3093	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVM->pgm.s, GCPtrPage);
3094	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3095	PX86PDEPAE pPdeDst;
3096	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3097	PX86PDPAE pPDDst;
3098	# if PGM_GST_TYPE != PGM_TYPE_PAE
3099	X86PDPE PdpeSrc;
3100
3101	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3102	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3103	# endif
3104	rc = pgmShwSyncPaePDPtr(pVM, GCPtrPage, &PdpeSrc, &pPDDst);
3105	if (rc != VINF_SUCCESS)
3106	{
3107	AssertRC(rc);
3108	return rc;
3109	}
3110	Assert(pPDDst);
3111	pPdeDst = &pPDDst->a[iPDDst];
3112
3113	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3114	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3115	PX86PDPAE pPDDst;
3116	PX86PDEPAE pPdeDst;
3117
3118	# if PGM_GST_TYPE == PGM_TYPE_PROT
3119	/* AMD-V nested paging */
3120	X86PML4E Pml4eSrc;
3121	X86PDPE PdpeSrc;
3122	PX86PML4E pPml4eSrc = &Pml4eSrc;
3123
3124	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3125	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3126	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3127	# endif
3128
3129	rc = pgmShwSyncLongModePDPtr(pVM, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3130	if (rc != VINF_SUCCESS)
3131	{
3132	AssertRC(rc);
3133	return rc;
3134	}
3135	Assert(pPDDst);
3136	pPdeDst = &pPDDst->a[iPDDst];
3137	# endif
3138
3139	if (!pPdeDst->n.u1Present)
3140	{
3141	# if defined(IN_RC)
3142	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3143	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3144	# endif
3145	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
3146	# if defined(IN_RC)
3147	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3148	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3149	# endif
3150	AssertRC(rc);
3151	if (rc != VINF_SUCCESS)
3152	return rc;
3153	}
3154
3155	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3156	/* Check for dirty bit fault */
3157	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3158	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3159	Log(("PGMVerifyAccess: success (dirty)\n"));
3160	else
3161	{
3162	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3163	#else
3164	{
3165	GSTPDE PdeSrc;
3166	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3167	PdeSrc.n.u1Present = 1;
3168	PdeSrc.n.u1Write = 1;
3169	PdeSrc.n.u1Accessed = 1;
3170	PdeSrc.n.u1User = 1;
3171
3172	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3173	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3174	if (uErr & X86_TRAP_PF_US)
3175	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3176	else /* supervisor */
3177	STAM_COUNTER_INC(&pVM->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3178
3179	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
3180	if (RT_SUCCESS(rc))
3181	{
3182	/* Page was successfully synced */
3183	Log2(("PGMVerifyAccess: success (sync)\n"));
3184	rc = VINF_SUCCESS;
3185	}
3186	else
3187	{
3188	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3189	return VINF_EM_RAW_GUEST_TRAP;
3190	}
3191	}
3192	return rc;
3193
3194	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3195
3196	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3197	return VERR_INTERNAL_ERROR;
3198	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3199	}
3200
3201
3202	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3203	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3204	/**
3205	* Figures out which kind of shadow page this guest PDE warrants.
3206	*
3207	* @returns Shadow page kind.
3208	* @param pPdeSrc The guest PDE in question.
3209	* @param cr4 The current guest cr4 value.
3210	*/
3211	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3212	{
3213	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3214	if (!pPdeSrc->n.u1Size)
3215	# else
3216	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3217	# endif
3218	return BTH_PGMPOOLKIND_PT_FOR_PT;
3219	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3220	//{
3221	// case 0:
3222	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3223	// case X86_PDE4M_RW:
3224	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3225	// case X86_PDE4M_US:
3226	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3227	// case X86_PDE4M_RW \| X86_PDE4M_US:
3228	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3229	# if 0
3230	// case X86_PDE4M_PAE_NX:
3231	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3232	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3233	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3234	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3235	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3236	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3237	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3238	# endif
3239	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3240	//}
3241	}
3242	# endif
3243	#endif
3244
3245	#undef MY_STAM_COUNTER_INC
3246	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3247
3248
3249	/**
3250	* Syncs the paging hierarchy starting at CR3.
3251	*
3252	* @returns VBox status code, no specials.
3253	* @param pVM The virtual machine.
3254	* @param cr0 Guest context CR0 register
3255	* @param cr3 Guest context CR3 register
3256	* @param cr4 Guest context CR4 register
3257	* @param fGlobal Including global page directories or not
3258	*/
3259	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3260	{
3261	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3262	fGlobal = true; /* Change this CR3 reload to be a global one. */
3263
3264	LogFlow(("SyncCR3 %d\n", fGlobal));
3265
3266	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3267	/*
3268	* Update page access handlers.
3269	* The virtual are always flushed, while the physical are only on demand.
3270	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3271	* have to look into that later because it will have a bad influence on the performance.
3272	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3273	* bird: Yes, but that won't work for aliases.
3274	*/
3275	/** @todo this MUST go away. See #1557. */
3276	STAM_PROFILE_START(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3277	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3278	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3279	#endif
3280
3281	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3282	/*
3283	* Nested / EPT - almost no work.
3284	*/
3285	/** @todo check if this is really necessary; the call does it as well... */
3286	HWACCMFlushTLB(pVM);
3287	return VINF_SUCCESS;
3288
3289	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3290	/*
3291	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3292	* out the shadow parts when the guest modifies its tables.
3293	*/
3294	return VINF_SUCCESS;
3295
3296	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3297
3298	# ifdef PGM_WITHOUT_MAPPINGS
3299	Assert(pVM->pgm.s.fMappingsFixed);
3300	return VINF_SUCCESS;
3301	# else
3302	/* Nothing to do when mappings are fixed. */
3303	if (pVM->pgm.s.fMappingsFixed)
3304	return VINF_SUCCESS;
3305
3306	int rc = PGMMapResolveConflicts(pVM);
3307	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3308	if (rc == VINF_PGM_SYNC_CR3)
3309	{
3310	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3311	return VINF_PGM_SYNC_CR3;
3312	}
3313	# endif
3314	return VINF_SUCCESS;
3315	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3316	}
3317
3318
3319
3320
3321	#ifdef VBOX_STRICT
3322	#ifdef IN_RC
3323	# undef AssertMsgFailed
3324	# define AssertMsgFailed Log
3325	#endif
3326	#ifdef IN_RING3
3327	# include <VBox/dbgf.h>
3328
3329	/**
3330	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3331	*
3332	* @returns VBox status code (VINF_SUCCESS).
3333	* @param pVM The VM handle.
3334	* @param cr3 The root of the hierarchy.
3335	* @param crr The cr4, only PAE and PSE is currently used.
3336	* @param fLongMode Set if long mode, false if not long mode.
3337	* @param cMaxDepth Number of levels to dump.
3338	* @param pHlp Pointer to the output functions.
3339	*/
3340	__BEGIN_DECLS
3341	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3342	__END_DECLS
3343
3344	#endif
3345
3346	/**
3347	* Checks that the shadow page table is in sync with the guest one.
3348	*
3349	* @returns The number of errors.
3350	* @param pVM The virtual machine.
3351	* @param cr3 Guest context CR3 register
3352	* @param cr4 Guest context CR4 register
3353	* @param GCPtr Where to start. Defaults to 0.
3354	* @param cb How much to check. Defaults to everything.
3355	*/
3356	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3357	{
3358	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3359	return 0;
3360	#else
3361	unsigned cErrors = 0;
3362
3363	#if PGM_GST_TYPE == PGM_TYPE_PAE
3364	/** @todo currently broken; crashes below somewhere */
3365	AssertFailed();
3366	#endif
3367
3368	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3369	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3370	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3371
3372	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3373	bool fBigPagesSupported = true;
3374	# else
3375	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3376	# endif
3377	PPGM pPGM = &pVM->pgm.s;
3378	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3379	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3380	# ifndef IN_RING0
3381	RTHCPHYS HCPhys; /* general usage. */
3382	# endif
3383	int rc;
3384
3385	/*
3386	* Check that the Guest CR3 and all its mappings are correct.
3387	*/
3388	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3389	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3390	false);
3391	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3392	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3393	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3394	# else
3395	rc = PGMShwGetPage(pVM, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3396	# endif
3397	AssertRCReturn(rc, 1);
3398	HCPhys = NIL_RTHCPHYS;
3399	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3400	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3401	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3402	pgmGstGet32bitPDPtr(pPGM);
3403	RTGCPHYS GCPhys;
3404	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3405	AssertRCReturn(rc, 1);
3406	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3407	# endif
3408	# endif /* !IN_RING0 */
3409
3410	/*
3411	* Get and check the Shadow CR3.
3412	*/
3413	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3414	unsigned cPDEs = X86_PG_ENTRIES;
3415	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3416	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3417	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3418	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3419	# else
3420	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3421	# endif
3422	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3423	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3424	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3425	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3426	# endif
3427	if (cb != ~(RTGCPTR)0)
3428	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3429
3430	/** @todo call the other two PGMAssert() functions. /
3431
3432	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3433	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3434	# endif
3435
3436	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3437	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3438
3439	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3440	{
3441	PPGMPOOLPAGE pShwPdpt = NULL;
3442	PX86PML4E pPml4eSrc;
3443	PX86PML4E pPml4eDst;
3444	RTGCPHYS GCPhysPdptSrc;
3445
3446	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3447	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVM->pgm.s, iPml4);
3448
3449	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3450	if (!pPml4eDst->n.u1Present)
3451	{
3452	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3453	continue;
3454	}
3455
3456	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3457	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3458
3459	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3460	{
3461	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3462	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3463	cErrors++;
3464	continue;
3465	}
3466
3467	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3468	{
3469	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3470	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3471	cErrors++;
3472	continue;
3473	}
3474
3475	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3476	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3477	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3478	{
3479	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3480	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3481	cErrors++;
3482	continue;
3483	}
3484	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3485	{
3486	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3487
3488	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3489	/*
3490	* Check the PDPTEs too.
3491	*/
3492	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3493
3494	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3495	{
3496	unsigned iPDSrc;
3497	PPGMPOOLPAGE pShwPde = NULL;
3498	PX86PDPE pPdpeDst;
3499	RTGCPHYS GCPhysPdeSrc;
3500	# if PGM_GST_TYPE == PGM_TYPE_PAE
3501	X86PDPE PdpeSrc;
3502	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3503	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVM->pgm.s);
3504	# else
3505	PX86PML4E pPml4eSrc;
3506	X86PDPE PdpeSrc;
3507	PX86PDPT pPdptDst;
3508	PX86PDPAE pPDDst;
3509	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3510
3511	rc = pgmShwGetLongModePDPtr(pVM, GCPtr, NULL, &pPdptDst, &pPDDst);
3512	if (rc != VINF_SUCCESS)
3513	{
3514	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3515	GCPtr += 512 * _2M;
3516	continue; /* next PDPTE */
3517	}
3518	Assert(pPDDst);
3519	# endif
3520	Assert(iPDSrc == 0);
3521
3522	pPdpeDst = &pPdptDst->a[iPdpt];
3523
3524	if (!pPdpeDst->n.u1Present)
3525	{
3526	GCPtr += 512 * _2M;
3527	continue; /* next PDPTE */
3528	}
3529
3530	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3531	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3532
3533	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3534	{
3535	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3536	GCPtr += 512 * _2M;
3537	cErrors++;
3538	continue;
3539	}
3540
3541	if (GCPhysPdeSrc != pShwPde->GCPhys)
3542	{
3543	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3544	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3545	# else
3546	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3547	# endif
3548	GCPtr += 512 * _2M;
3549	cErrors++;
3550	continue;
3551	}
3552
3553	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3554	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3555	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3556	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3557	{
3558	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3559	GCPtr += 512 * _2M;
3560	cErrors++;
3561	continue;
3562	}
3563	# endif
3564
3565	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3566	{
3567	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3568	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3569	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3570	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3571	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVM->pgm.s);
3572	# endif
3573	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3574	/*
3575	* Iterate the shadow page directory.
3576	*/
3577	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3578	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3579
3580	for (;
3581	iPDDst < cPDEs;
3582	iPDDst++, GCPtr += cIncrement)
3583	{
3584	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3585	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3586	# else
3587	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3588	# endif
3589	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3590	{
3591	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3592	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3593	{
3594	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3595	cErrors++;
3596	continue;
3597	}
3598	}
3599	else if ( (PdeDst.u & X86_PDE_P)
3600	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3601	)
3602	{
3603	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3604	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3605	if (!pPoolPage)
3606	{
3607	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3608	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3609	cErrors++;
3610	continue;
3611	}
3612	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3613
3614	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3615	{
3616	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3617	GCPtr, (uint64_t)PdeDst.u));
3618	cErrors++;
3619	}
3620
3621	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3622	{
3623	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3624	GCPtr, (uint64_t)PdeDst.u));
3625	cErrors++;
3626	}
3627
3628	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3629	if (!PdeSrc.n.u1Present)
3630	{
3631	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3632	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3633	cErrors++;
3634	continue;
3635	}
3636
3637	if ( !PdeSrc.b.u1Size
3638	\|\| !fBigPagesSupported)
3639	{
3640	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3641	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3642	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3643	# endif
3644	}
3645	else
3646	{
3647	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3648	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3649	{
3650	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3651	GCPtr, (uint64_t)PdeSrc.u));
3652	cErrors++;
3653	continue;
3654	}
3655	# endif
3656	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3657	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3658	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3659	# endif
3660	}
3661
3662	if ( pPoolPage->enmKind
3663	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3664	{
3665	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3666	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3667	cErrors++;
3668	}
3669
3670	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3671	if (!pPhysPage)
3672	{
3673	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3674	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3675	cErrors++;
3676	continue;
3677	}
3678
3679	if (GCPhysGst != pPoolPage->GCPhys)
3680	{
3681	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3682	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3683	cErrors++;
3684	continue;
3685	}
3686
3687	if ( !PdeSrc.b.u1Size
3688	\|\| !fBigPagesSupported)
3689	{
3690	/*
3691	* Page Table.
3692	*/
3693	const GSTPT *pPTSrc;
3694	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3695	if (RT_FAILURE(rc))
3696	{
3697	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3698	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3699	cErrors++;
3700	continue;
3701	}
3702	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3703	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3704	{
3705	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3706	// (This problem will go away when/if we shadow multiple CR3s.)
3707	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3708	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3709	cErrors++;
3710	continue;
3711	}
3712	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3713	{
3714	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3715	GCPtr, (uint64_t)PdeDst.u));
3716	cErrors++;
3717	continue;
3718	}
3719
3720	/* iterate the page table. */
3721	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3722	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3723	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3724	# else
3725	const unsigned offPTSrc = 0;
3726	# endif
3727	for (unsigned iPT = 0, off = 0;
3728	iPT < RT_ELEMENTS(pPTDst->a);
3729	iPT++, off += PAGE_SIZE)
3730	{
3731	const SHWPTE PteDst = pPTDst->a[iPT];
3732
3733	/* skip not-present entries. */
3734	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3735	continue;
3736	Assert(PteDst.n.u1Present);
3737
3738	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3739	if (!PteSrc.n.u1Present)
3740	{
3741	# ifdef IN_RING3
3742	PGMAssertHandlerAndFlagsInSync(pVM);
3743	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3744	# endif
3745	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3746	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3747	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3748	cErrors++;
3749	continue;
3750	}
3751
3752	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3753	# if 1 /** @todo sync accessed bit properly... */
3754	fIgnoreFlags \|= X86_PTE_A;
3755	# endif
3756
3757	/* match the physical addresses */
3758	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3759	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3760
3761	# ifdef IN_RING3
3762	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3763	if (RT_FAILURE(rc))
3764	{
3765	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3766	{
3767	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3768	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3769	cErrors++;
3770	continue;
3771	}
3772	}
3773	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3774	{
3775	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3776	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3777	cErrors++;
3778	continue;
3779	}
3780	# endif
3781
3782	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3783	if (!pPhysPage)
3784	{
3785	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3786	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3787	{
3788	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3789	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3790	cErrors++;
3791	continue;
3792	}
3793	# endif
3794	if (PteDst.n.u1Write)
3795	{
3796	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3797	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3798	cErrors++;
3799	}
3800	fIgnoreFlags \|= X86_PTE_RW;
3801	}
3802	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3803	{
3804	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3805	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3806	cErrors++;
3807	continue;
3808	}
3809
3810	/* flags */
3811	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3812	{
3813	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3814	{
3815	if (PteDst.n.u1Write)
3816	{
3817	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3818	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3819	cErrors++;
3820	continue;
3821	}
3822	fIgnoreFlags \|= X86_PTE_RW;
3823	}
3824	else
3825	{
3826	if (PteDst.n.u1Present)
3827	{
3828	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3829	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3830	cErrors++;
3831	continue;
3832	}
3833	fIgnoreFlags \|= X86_PTE_P;
3834	}
3835	}
3836	else
3837	{
3838	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3839	{
3840	if (PteDst.n.u1Write)
3841	{
3842	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3843	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3844	cErrors++;
3845	continue;
3846	}
3847	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3848	{
3849	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3850	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3851	cErrors++;
3852	continue;
3853	}
3854	if (PteDst.n.u1Dirty)
3855	{
3856	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3857	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3858	cErrors++;
3859	}
3860	# if 0 /** @todo sync access bit properly... */
3861	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3862	{
3863	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3864	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3865	cErrors++;
3866	}
3867	fIgnoreFlags \|= X86_PTE_RW;
3868	# else
3869	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3870	# endif
3871	}
3872	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3873	{
3874	/* access bit emulation (not implemented). */
3875	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3876	{
3877	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3878	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3879	cErrors++;
3880	continue;
3881	}
3882	if (!PteDst.n.u1Accessed)
3883	{
3884	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3885	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3886	cErrors++;
3887	}
3888	fIgnoreFlags \|= X86_PTE_P;
3889	}
3890	# ifdef DEBUG_sandervl
3891	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3892	# endif
3893	}
3894
3895	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3896	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3897	)
3898	{
3899	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3900	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3901	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3902	cErrors++;
3903	continue;
3904	}
3905	} /* foreach PTE */
3906	}
3907	else
3908	{
3909	/*
3910	* Big Page.
3911	*/
3912	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3913	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3914	{
3915	if (PdeDst.n.u1Write)
3916	{
3917	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3918	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3919	cErrors++;
3920	continue;
3921	}
3922	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3923	{
3924	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3925	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3926	cErrors++;
3927	continue;
3928	}
3929	# if 0 /** @todo sync access bit properly... */
3930	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3931	{
3932	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3933	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3934	cErrors++;
3935	}
3936	fIgnoreFlags \|= X86_PTE_RW;
3937	# else
3938	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3939	# endif
3940	}
3941	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3942	{
3943	/* access bit emulation (not implemented). */
3944	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3945	{
3946	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3947	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3948	cErrors++;
3949	continue;
3950	}
3951	if (!PdeDst.n.u1Accessed)
3952	{
3953	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3954	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3955	cErrors++;
3956	}
3957	fIgnoreFlags \|= X86_PTE_P;
3958	}
3959
3960	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3961	{
3962	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3963	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3964	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3965	cErrors++;
3966	}
3967
3968	/* iterate the page table. */
3969	for (unsigned iPT = 0, off = 0;
3970	iPT < RT_ELEMENTS(pPTDst->a);
3971	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3972	{
3973	const SHWPTE PteDst = pPTDst->a[iPT];
3974
3975	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3976	{
3977	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3978	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3979	cErrors++;
3980	}
3981
3982	/* skip not-present entries. */
3983	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3984	continue;
3985
3986	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
3987
3988	/* match the physical addresses */
3989	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3990
3991	# ifdef IN_RING3
3992	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3993	if (RT_FAILURE(rc))
3994	{
3995	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3996	{
3997	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3998	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3999	cErrors++;
4000	}
4001	}
4002	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4003	{
4004	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4005	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4006	cErrors++;
4007	continue;
4008	}
4009	# endif
4010	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
4011	if (!pPhysPage)
4012	{
4013	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4014	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
4015	{
4016	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4017	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4018	cErrors++;
4019	continue;
4020	}
4021	# endif
4022	if (PteDst.n.u1Write)
4023	{
4024	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4025	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4026	cErrors++;
4027	}
4028	fIgnoreFlags \|= X86_PTE_RW;
4029	}
4030	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4031	{
4032	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4033	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4034	cErrors++;
4035	continue;
4036	}
4037
4038	/* flags */
4039	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4040	{
4041	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4042	{
4043	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4044	{
4045	if (PteDst.n.u1Write)
4046	{
4047	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4048	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4049	cErrors++;
4050	continue;
4051	}
4052	fIgnoreFlags \|= X86_PTE_RW;
4053	}
4054	}
4055	else
4056	{
4057	if (PteDst.n.u1Present)
4058	{
4059	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4060	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4061	cErrors++;
4062	continue;
4063	}
4064	fIgnoreFlags \|= X86_PTE_P;
4065	}
4066	}
4067
4068	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4069	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4070	)
4071	{
4072	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4073	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4074	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4075	cErrors++;
4076	continue;
4077	}
4078	} /* for each PTE */
4079	}
4080	}
4081	/* not present */
4082
4083	} /* for each PDE */
4084
4085	} /* for each PDPTE */
4086
4087	} /* for each PML4E */
4088
4089	# ifdef DEBUG
4090	if (cErrors)
4091	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4092	# endif
4093
4094	#endif /* GST == 32BIT, PAE or AMD64 */
4095	return cErrors;
4096
4097	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4098	}
4099	#endif /* VBOX_STRICT */
4100
4101
4102	/**
4103	* Sets up the CR3 for shadow paging
4104	*
4105	* @returns Strict VBox status code.
4106	* @retval VINF_SUCCESS.
4107	*
4108	* @param pVM VM handle.
4109	* @param GCPhysCR3 The physical address in the CR3 register.
4110	*/
4111	PGM_BTH_DECL(int, MapCR3)(PVM pVM, RTGCPHYS GCPhysCR3)
4112	{
4113	/* Update guest paging info. */
4114	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4115	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4116	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4117
4118	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4119
4120	/*
4121	* Map the page CR3 points at.
4122	*/
4123	RTHCPTR HCPtrGuestCR3;
4124	RTHCPHYS HCPhysGuestCR3;
4125	pgmLock(pVM);
4126	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4127	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4128	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4129	/** @todo this needs some reworking wrt. locking. */
4130	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4131	HCPtrGuestCR3 = NIL_RTHCPTR;
4132	int rc = VINF_SUCCESS;
4133	# else
4134	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4135	# endif
4136	pgmUnlock(pVM);
4137	if (RT_SUCCESS(rc))
4138	{
4139	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4140	if (RT_SUCCESS(rc))
4141	{
4142	# ifdef IN_RC
4143	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4144	# endif
4145	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4146	pVM->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4147	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4148	pVM->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4149	# endif
4150	pVM->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4151
4152	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4153	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4154	pVM->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4155	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4156	pVM->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4157	# endif
4158	pVM->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4159	Log(("Cached mapping %RRv\n", pVM->pgm.s.pGstPaePdptRC));
4160
4161	/*
4162	* Map the 4 PDs too.
4163	*/
4164	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVM->pgm.s);
4165	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4166	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4167	{
4168	if (pGuestPDPT->a[i].n.u1Present)
4169	{
4170	RTHCPTR HCPtr;
4171	RTHCPHYS HCPhys;
4172	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4173	pgmLock(pVM);
4174	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4175	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4176	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4177	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4178	HCPtr = NIL_RTHCPTR;
4179	int rc2 = VINF_SUCCESS;
4180	# else
4181	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4182	# endif
4183	pgmUnlock(pVM);
4184	if (RT_SUCCESS(rc2))
4185	{
4186	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4187	AssertRCReturn(rc, rc);
4188
4189	pVM->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4190	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4191	pVM->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4192	# endif
4193	pVM->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4194	pVM->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4195	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
4196	continue;
4197	}
4198	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4199	}
4200
4201	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4202	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4203	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4204	# endif
4205	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4206	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4207	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4208	}
4209
4210	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4211	pVM->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4212	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4213	pVM->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4214	# endif
4215	# endif
4216	}
4217	else
4218	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4219	}
4220	else
4221	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4222
4223	#else /* prot/real stub */
4224	int rc = VINF_SUCCESS;
4225	#endif
4226
4227	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4228	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4229	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4230	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4231	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4232	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4233
4234	Assert(!HWACCMIsNestedPagingActive(pVM));
4235
4236	/*
4237	* Update the shadow root page as well since that's not fixed.
4238	*/
4239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4240	PPGMPOOLPAGE pOldShwPageCR3 = pVM->pgm.s.CTX_SUFF(pShwPageCR3);
4241	uint32_t iOldShwUserTable = pVM->pgm.s.iShwUserTable;
4242	uint32_t iOldShwUser = pVM->pgm.s.iShwUser;
4243	PPGMPOOLPAGE pNewShwPageCR3;
4244
4245	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4246	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4247	AssertFatalRC(rc);
4248	rc = VINF_SUCCESS;
4249
4250	/* Mark the page as locked; disallow flushing. */
4251	pgmPoolLockPage(pPool, pNewShwPageCR3);
4252
4253	# ifdef IN_RC
4254	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4255	bool fLog = VMMGCLogDisable(pVM);
4256	# endif
4257
4258	pVM->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4259	pVM->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4260	pVM->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4261	# ifdef IN_RING0
4262	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4263	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4264	# elif defined(IN_RC)
4265	pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4266	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4267	# else
4268	pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4269	pVM->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4270	# endif
4271
4272	# ifndef PGM_WITHOUT_MAPPINGS
4273	/*
4274	* Apply all hypervisor mappings to the new CR3.
4275	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4276	* make sure we check for conflicts in the new CR3 root.
4277	*/
4278	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4279	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4280	# endif
4281	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4282	AssertRCReturn(rc, rc);
4283	# endif
4284
4285	/* Set the current hypervisor CR3. */
4286	CPUMSetHyperCR3(pVM, PGMGetHyperCR3(pVM));
4287	SELMShadowCR3Changed(pVM);
4288
4289	# ifdef IN_RC
4290	VMMGCLogRestore(pVM, fLog);
4291	# endif
4292
4293	/* Clean up the old CR3 root. */
4294	if (pOldShwPageCR3)
4295	{
4296	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4297	# ifndef PGM_WITHOUT_MAPPINGS
4298	/* Remove the hypervisor mappings from the shadow page table. */
4299	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4300	# endif
4301	/* Mark the page as unlocked; allow flushing again. */
4302	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4303
4304	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4305	}
4306
4307	# endif
4308
4309	return rc;
4310	}
4311
4312	/**
4313	* Unmaps the shadow CR3.
4314	*
4315	* @returns VBox status, no specials.
4316	* @param pVM VM handle.
4317	*/
4318	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM)
4319	{
4320	LogFlow(("UnmapCR3\n"));
4321
4322	int rc = VINF_SUCCESS;
4323
4324	/* Update guest paging info. */
4325	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4326	pVM->pgm.s.pGst32BitPdR3 = 0;
4327	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4328	pVM->pgm.s.pGst32BitPdR0 = 0;
4329	#endif
4330	pVM->pgm.s.pGst32BitPdRC = 0;
4331
4332	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4333	pVM->pgm.s.pGstPaePdptR3 = 0;
4334	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4335	pVM->pgm.s.pGstPaePdptR0 = 0;
4336	# endif
4337	pVM->pgm.s.pGstPaePdptRC = 0;
4338	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4339	{
4340	pVM->pgm.s.apGstPaePDsR3[i] = 0;
4341	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4342	pVM->pgm.s.apGstPaePDsR0[i] = 0;
4343	# endif
4344	pVM->pgm.s.apGstPaePDsRC[i] = 0;
4345	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4346	}
4347
4348	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4349	pVM->pgm.s.pGstAmd64Pml4R3 = 0;
4350	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4351	pVM->pgm.s.pGstAmd64Pml4R0 = 0;
4352	# endif
4353
4354	#else /* prot/real mode stub */
4355	/* nothing to do */
4356	#endif
4357
4358	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4359	/* Update shadow paging info. */
4360	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4361	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4362	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4363
4364	# if PGM_GST_TYPE != PGM_TYPE_REAL
4365	Assert(!HWACCMIsNestedPagingActive(pVM));
4366	# endif
4367
4368	# ifndef PGM_WITHOUT_MAPPINGS
4369	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4370	/* Remove the hypervisor mappings from the shadow page table. */
4371	pgmMapDeactivateCR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4372	# endif
4373
4374	if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
4375	{
4376	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4377
4378	Assert(pVM->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4379
4380	/* Mark the page as unlocked; allow flushing again. */
4381	pgmPoolUnlockPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
4382
4383	pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.iShwUser, pVM->pgm.s.iShwUserTable);
4384	pVM->pgm.s.pShwPageCR3R3 = 0;
4385	pVM->pgm.s.pShwPageCR3R0 = 0;
4386	pVM->pgm.s.pShwPageCR3RC = 0;
4387	pVM->pgm.s.iShwUser = 0;
4388	pVM->pgm.s.iShwUserTable = 0;
4389	}
4390	# endif
4391	#endif /* !IN_RC*/
4392
4393	return rc;
4394	}
4395

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 18666

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