PGMAllBth.h@ 18976

Last change on this file since 18976 was 18947, checked in by vboxsync, 16 years ago
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1	/* $Id: PGMAllBth.h 18947 2009-04-16 14:01:04Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM, PVMCPU pVCpu);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVM VM Handle.
79	* @param pVCpu VMCPU Handle.
80	* @param uErr The trap error code.
81	* @param pRegFrame Trap register frame.
82	* @param pvFault The fault address.
83	*/
84	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
85	{
86	# if defined(IN_RC) && defined(VBOX_STRICT)
87	PGMDynCheckLocks(pVM);
88	# endif
89
90	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
91	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
92	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
93
94	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
95	/*
96	* Hide the instruction fetch trap indicator for now.
97	*/
98	/** @todo NXE will change this and we must fix NXE in the switcher too! */
99	if (uErr & X86_TRAP_PF_ID)
100	{
101	uErr &= ~X86_TRAP_PF_ID;
102	TRPMSetErrorCode(pVM, uErr);
103	}
104	# endif
105
106	/*
107	* Get PDs.
108	*/
109	int rc;
110	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
111	# if PGM_GST_TYPE == PGM_TYPE_32BIT
112	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
113	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
114
115	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
116
117	# if PGM_GST_TYPE == PGM_TYPE_PAE
118	unsigned iPDSrc;
119	X86PDPE PdpeSrc;
120	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
121
122	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
123	unsigned iPDSrc;
124	PX86PML4E pPml4eSrc;
125	X86PDPE PdpeSrc;
126	PGSTPD pPDSrc;
127
128	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
129	Assert(pPml4eSrc);
130	# endif
131
132	/* Quick check for a valid guest trap. (PAE & AMD64) */
133	if (!pPDSrc)
134	{
135	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
136	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
137	# else
138	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
139	# endif
140	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
141	TRPMSetErrorCode(pVM, uErr);
142	return VINF_EM_RAW_GUEST_TRAP;
143	}
144	# endif
145
146	# else /* !PGM_WITH_PAGING */
147	PGSTPD pPDSrc = NULL;
148	const unsigned iPDSrc = 0;
149	# endif /* !PGM_WITH_PAGING */
150
151
152	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
153	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
154	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
155
156	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
157	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
158
159	PX86PDPAE pPDDst;
160	# if PGM_GST_TYPE != PGM_TYPE_PAE
161	X86PDPE PdpeSrc;
162
163	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
164	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
165	# endif
166	rc = pgmShwSyncPaePDPtr(pVM, pVCpu, pvFault, &PdpeSrc, &pPDDst);
167	if (rc != VINF_SUCCESS)
168	{
169	AssertRC(rc);
170	return rc;
171	}
172	Assert(pPDDst);
173
174	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
175	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
176	PX86PDPAE pPDDst;
177	# if PGM_GST_TYPE == PGM_TYPE_PROT
178	/* AMD-V nested paging */
179	X86PML4E Pml4eSrc;
180	X86PDPE PdpeSrc;
181	PX86PML4E pPml4eSrc = &Pml4eSrc;
182
183	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
184	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
185	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
186	# endif
187
188	rc = pgmShwSyncLongModePDPtr(pVM, pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
189	if (rc != VINF_SUCCESS)
190	{
191	AssertRC(rc);
192	return rc;
193	}
194	Assert(pPDDst);
195
196	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
197	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
198	PEPTPD pPDDst;
199
200	rc = pgmShwGetEPTPDPtr(pVM, pVCpu, pvFault, NULL, &pPDDst);
201	if (rc != VINF_SUCCESS)
202	{
203	AssertRC(rc);
204	return rc;
205	}
206	Assert(pPDDst);
207	# endif
208
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	/*
211	* If we successfully correct the write protection fault due to dirty bit
212	* tracking, or this page fault is a genuine one, then return immediately.
213	*/
214	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
215	rc = PGM_BTH_NAME(CheckPageFault)(pVM, pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
216	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
217	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
218	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
219	{
220	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
221	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
222	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
223	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
224	}
225
226	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
227	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
228
229	/*
230	* A common case is the not-present error caused by lazy page table syncing.
231	*
232	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
233	* so we can safely assume that the shadow PT is present when calling SyncPage later.
234	*
235	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
236	* of mapping conflict and defer to SyncCR3 in R3.
237	* (Again, we do NOT support access handlers for non-present guest pages.)
238	*
239	*/
240	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
241	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
242	# else
243	GSTPDE PdeSrc;
244	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
245	PdeSrc.n.u1Present = 1;
246	PdeSrc.n.u1Write = 1;
247	PdeSrc.n.u1Accessed = 1;
248	PdeSrc.n.u1User = 1;
249	# endif
250	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
251	&& !pPDDst->a[iPDDst].n.u1Present
252	&& PdeSrc.n.u1Present
253	)
254
255	{
256	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
257	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
258	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
259	rc = PGM_BTH_NAME(SyncPT)(pVM, pVCpu, iPDSrc, pPDSrc, pvFault);
260	if (RT_SUCCESS(rc))
261	{
262	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
263	return rc;
264	}
265	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
266	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
267	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
268	return VINF_PGM_SYNC_CR3;
269	}
270
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	/*
273	* Check if this address is within any of our mappings.
274	*
275	* This is very fast and it's gonna save us a bit of effort below and prevent
276	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
277	* (BTW, it's impossible to have physical access handlers in a mapping.)
278	*/
279	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
280	{
281	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
282	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
283	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
284	{
285	if (pvFault < pMapping->GCPtr)
286	break;
287	if (pvFault - pMapping->GCPtr < pMapping->cb)
288	{
289	/*
290	* The first thing we check is if we've got an undetected conflict.
291	*/
292	if (!pVM->pgm.s.fMappingsFixed)
293	{
294	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
295	while (iPT-- > 0)
296	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
297	{
298	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
299	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
300	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
301	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
302	return VINF_PGM_SYNC_CR3;
303	}
304	}
305
306	/*
307	* Check if the fault address is in a virtual page access handler range.
308	*/
309	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
310	if ( pCur
311	&& pvFault - pCur->Core.Key < pCur->cb
312	&& uErr & X86_TRAP_PF_RW)
313	{
314	# ifdef IN_RC
315	STAM_PROFILE_START(&pCur->Stat, h);
316	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
317	STAM_PROFILE_STOP(&pCur->Stat, h);
318	# else
319	AssertFailed();
320	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
321	# endif
322	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
323	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
324	return rc;
325	}
326
327	/*
328	* Pretend we're not here and let the guest handle the trap.
329	*/
330	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
331	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
332	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
333	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
334	return VINF_EM_RAW_GUEST_TRAP;
335	}
336	}
337	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
338	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
339	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
340
341	/*
342	* Check if this fault address is flagged for special treatment,
343	* which means we'll have to figure out the physical address and
344	* check flags associated with it.
345	*
346	* ASSUME that we can limit any special access handling to pages
347	* in page tables which the guest believes to be present.
348	*/
349	if (PdeSrc.n.u1Present)
350	{
351	RTGCPHYS GCPhys = NIL_RTGCPHYS;
352
353	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
354	# if PGM_GST_TYPE == PGM_TYPE_AMD64
355	bool fBigPagesSupported = true;
356	# else
357	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
358	# endif
359	if ( PdeSrc.b.u1Size
360	&& fBigPagesSupported)
361	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
362	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
363	else
364	{
365	PGSTPT pPTSrc;
366	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
367	if (RT_SUCCESS(rc))
368	{
369	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
370	if (pPTSrc->a[iPTESrc].n.u1Present)
371	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
372	}
373	}
374	# else
375	/* No paging so the fault address is the physical address */
376	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
377	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
378
379	/*
380	* If we have a GC address we'll check if it has any flags set.
381	*/
382	if (GCPhys != NIL_RTGCPHYS)
383	{
384	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
385
386	PPGMPAGE pPage;
387	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
388	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
389	{
390	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
391	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
392	{
393	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
394	{
395	/*
396	* Physical page access handler.
397	*/
398	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
399	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
400	if (pCur)
401	{
402	# ifdef PGM_SYNC_N_PAGES
403	/*
404	* If the region is write protected and we got a page not present fault, then sync
405	* the pages. If the fault was caused by a read, then restart the instruction.
406	* In case of write access continue to the GC write handler.
407	*
408	* ASSUMES that there is only one handler per page or that they have similar write properties.
409	*/
410	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
411	&& !(uErr & X86_TRAP_PF_P))
412	{
413	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
414	if ( RT_FAILURE(rc)
415	\|\| !(uErr & X86_TRAP_PF_RW)
416	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
417	{
418	AssertRC(rc);
419	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
420	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
422	return rc;
423	}
424	}
425	# endif
426
427	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
428	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
429	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
430
431	# if defined(IN_RC) \|\| defined(IN_RING0)
432	if (pCur->CTX_SUFF(pfnHandler))
433	{
434	STAM_PROFILE_START(&pCur->Stat, h);
435	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
436	STAM_PROFILE_STOP(&pCur->Stat, h);
437	}
438	else
439	# endif
440	rc = VINF_EM_RAW_EMULATE_INSTR;
441	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
442	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
443	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
444	return rc;
445	}
446	}
447	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
448	else
449	{
450	# ifdef PGM_SYNC_N_PAGES
451	/*
452	* If the region is write protected and we got a page not present fault, then sync
453	* the pages. If the fault was caused by a read, then restart the instruction.
454	* In case of write access continue to the GC write handler.
455	*/
456	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
457	&& !(uErr & X86_TRAP_PF_P))
458	{
459	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
460	if ( RT_FAILURE(rc)
461	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
462	\|\| !(uErr & X86_TRAP_PF_RW))
463	{
464	AssertRC(rc);
465	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
466	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
467	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
468	return rc;
469	}
470	}
471	# endif
472	/*
473	* Ok, it's an virtual page access handler.
474	*
475	* Since it's faster to search by address, we'll do that first
476	* and then retry by GCPhys if that fails.
477	*/
478	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
479	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
480	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
481	*/
482	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
483	if (pCur)
484	{
485	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
486	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
487	\|\| !(uErr & X86_TRAP_PF_P)
488	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
489	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
490
491	if ( pvFault - pCur->Core.Key < pCur->cb
492	&& ( uErr & X86_TRAP_PF_RW
493	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
494	{
495	# ifdef IN_RC
496	STAM_PROFILE_START(&pCur->Stat, h);
497	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
498	STAM_PROFILE_STOP(&pCur->Stat, h);
499	# else
500	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
501	# endif
502	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
503	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
504	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
505	return rc;
506	}
507	/* Unhandled part of a monitored page */
508	}
509	else
510	{
511	/* Check by physical address. */
512	PPGMVIRTHANDLER pCur;
513	unsigned iPage;
514	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
515	&pCur, &iPage);
516	Assert(RT_SUCCESS(rc) \|\| !pCur);
517	if ( pCur
518	&& ( uErr & X86_TRAP_PF_RW
519	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
520	{
521	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
522	# ifdef IN_RC
523	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
524	Assert(off < pCur->cb);
525	STAM_PROFILE_START(&pCur->Stat, h);
526	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
527	STAM_PROFILE_STOP(&pCur->Stat, h);
528	# else
529	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
530	# endif
531	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
532	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
533	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
534	return rc;
535	}
536	}
537	}
538	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
539
540	/*
541	* There is a handled area of the page, but this fault doesn't belong to it.
542	* We must emulate the instruction.
543	*
544	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
545	* we first check if this was a page-not-present fault for a page with only
546	* write access handlers. Restart the instruction if it wasn't a write access.
547	*/
548	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
549
550	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
551	&& !(uErr & X86_TRAP_PF_P))
552	{
553	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
554	if ( RT_FAILURE(rc)
555	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
556	\|\| !(uErr & X86_TRAP_PF_RW))
557	{
558	AssertRC(rc);
559	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
560	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
561	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
562	return rc;
563	}
564	}
565
566	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
567	* It's writing to an unhandled part of the LDT page several million times.
568	*/
569	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
570	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
571	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
572	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
573	return rc;
574	} /* if any kind of handler */
575
576	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
577	if (uErr & X86_TRAP_PF_P)
578	{
579	/*
580	* The page isn't marked, but it might still be monitored by a virtual page access handler.
581	* (ASSUMES no temporary disabling of virtual handlers.)
582	*/
583	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
584	* we should correct both the shadow page table and physical memory flags, and not only check for
585	* accesses within the handler region but for access to pages with virtual handlers. */
586	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
587	if (pCur)
588	{
589	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
590	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
591	\|\| !(uErr & X86_TRAP_PF_P)
592	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
593	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
594
595	if ( pvFault - pCur->Core.Key < pCur->cb
596	&& ( uErr & X86_TRAP_PF_RW
597	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
598	{
599	# ifdef IN_RC
600	STAM_PROFILE_START(&pCur->Stat, h);
601	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
602	STAM_PROFILE_STOP(&pCur->Stat, h);
603	# else
604	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
605	# endif
606	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
607	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
608	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
609	return rc;
610	}
611	}
612	}
613	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
614	}
615	else
616	{
617	/*
618	* When the guest accesses invalid physical memory (e.g. probing
619	* of RAM or accessing a remapped MMIO range), then we'll fall
620	* back to the recompiler to emulate the instruction.
621	*/
622	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
623	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
624	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
625	return VINF_EM_RAW_EMULATE_INSTR;
626	}
627
628	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
629
630	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
631	/*
632	* We are here only if page is present in Guest page tables and
633	* trap is not handled by our handlers.
634	*
635	* Check it for page out-of-sync situation.
636	*/
637	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
638
639	if (!(uErr & X86_TRAP_PF_P))
640	{
641	/*
642	* Page is not present in our page tables.
643	* Try to sync it!
644	* BTW, fPageShw is invalid in this branch!
645	*/
646	if (uErr & X86_TRAP_PF_US)
647	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
648	else /* supervisor */
649	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
650
651	# if defined(LOG_ENABLED) && !defined(IN_RING0)
652	RTGCPHYS GCPhys;
653	uint64_t fPageGst;
654	PGMGstGetPage(pVM, pVCpu, pvFault, &fPageGst, &GCPhys);
655	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
656	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
657	# endif /* LOG_ENABLED */
658
659	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
660	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
661	{
662	uint64_t fPageGst;
663	rc = PGMGstGetPage(pVM, pVCpu, pvFault, &fPageGst, NULL);
664	if ( RT_SUCCESS(rc)
665	&& !(fPageGst & X86_PTE_US))
666	{
667	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
668	if ( pvFault == (RTGCPTR)pRegFrame->eip
669	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
670	# ifdef CSAM_DETECT_NEW_CODE_PAGES
671	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
672	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
673	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
674	)
675	{
676	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
677	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
678	if (rc != VINF_SUCCESS)
679	{
680	/*
681	* CSAM needs to perform a job in ring 3.
682	*
683	* Sync the page before going to the host context; otherwise we'll end up in a loop if
684	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
685	*/
686	LogFlow(("CSAM ring 3 job\n"));
687	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, pvFault, 1, uErr);
688	AssertRC(rc2);
689
690	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
691	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
692	return rc;
693	}
694	}
695	# ifdef CSAM_DETECT_NEW_CODE_PAGES
696	else if ( uErr == X86_TRAP_PF_RW
697	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
698	&& pRegFrame->ecx < 0x10000)
699	{
700	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
701	* to detect loading of new code pages.
702	*/
703
704	/*
705	* Decode the instruction.
706	*/
707	RTGCPTR PC;
708	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
709	if (rc == VINF_SUCCESS)
710	{
711	DISCPUSTATE Cpu;
712	uint32_t cbOp;
713	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
714
715	/* For now we'll restrict this to rep movsw/d instructions */
716	if ( rc == VINF_SUCCESS
717	&& Cpu.pCurInstr->opcode == OP_MOVSWD
718	&& (Cpu.prefix & PREFIX_REP))
719	{
720	CSAMMarkPossibleCodePage(pVM, pvFault);
721	}
722	}
723	}
724	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
725
726	/*
727	* Mark this page as safe.
728	*/
729	/** @todo not correct for pages that contain both code and data!! */
730	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
731	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
732	}
733	}
734	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
735	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
736	if (RT_SUCCESS(rc))
737	{
738	/* The page was successfully synced, return to the guest. */
739	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
740	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
741	return VINF_SUCCESS;
742	}
743	}
744	else /* uErr & X86_TRAP_PF_P: */
745	{
746	/*
747	* Write protected pages is make writable when the guest makes the first
748	* write to it. This happens for pages that are shared, write monitored
749	* and not yet allocated.
750	*
751	* Also, a side effect of not flushing global PDEs are out of sync pages due
752	* to physical monitored regions, that are no longer valid.
753	* Assume for now it only applies to the read/write flag.
754	*/
755	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
756	{
757	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
758	{
759	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
760	GCPhys, pPage, pvFault, uErr));
761	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
762	if (rc != VINF_SUCCESS)
763	{
764	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
765	return rc;
766	}
767	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
768	return VINF_EM_NO_MEMORY;
769	}
770	/// @todo count the above case; else
771	if (uErr & X86_TRAP_PF_US)
772	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
773	else /* supervisor */
774	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
775
776	/*
777	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
778	* page is not present, which is not true in this case.
779	*/
780	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, pvFault, 1, uErr);
781	if (RT_SUCCESS(rc))
782	{
783	/*
784	* Page was successfully synced, return to guest.
785	*/
786	# ifdef VBOX_STRICT
787	RTGCPHYS GCPhys;
788	uint64_t fPageGst;
789	rc = PGMGstGetPage(pVM, pVCpu, pvFault, &fPageGst, &GCPhys);
790	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
791	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
792
793	uint64_t fPageShw;
794	rc = PGMShwGetPage(pVM, pVCpu, pvFault, &fPageShw, NULL);
795	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
796	# endif /* VBOX_STRICT */
797	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
798	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
799	return VINF_SUCCESS;
800	}
801
802	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
803	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
804	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
805	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
806	{
807	uint64_t fPageGst;
808	rc = PGMGstGetPage(pVM, pVCpu, pvFault, &fPageGst, NULL);
809	if ( RT_SUCCESS(rc)
810	&& !(fPageGst & X86_PTE_RW))
811	{
812	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
813	if (RT_SUCCESS(rc))
814	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
815	else
816	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
817	return rc;
818	}
819	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
820	}
821	}
822
823	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
824	# ifdef VBOX_STRICT
825	/*
826	* Check for VMM page flags vs. Guest page flags consistency.
827	* Currently only for debug purposes.
828	*/
829	if (RT_SUCCESS(rc))
830	{
831	/* Get guest page flags. */
832	uint64_t fPageGst;
833	rc = PGMGstGetPage(pVM, pVCpu, pvFault, &fPageGst, NULL);
834	if (RT_SUCCESS(rc))
835	{
836	uint64_t fPageShw;
837	rc = PGMShwGetPage(pVM, pVCpu, pvFault, &fPageShw, NULL);
838
839	/*
840	* Compare page flags.
841	* Note: we have AVL, A, D bits desynched.
842	*/
843	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
844	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
845	}
846	else
847	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
848	}
849	else
850	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
851	# endif /* VBOX_STRICT */
852	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
853	}
854	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
855	# endif /* PGM_OUT_OF_SYNC_IN_GC */
856	}
857	else /* GCPhys == NIL_RTGCPHYS */
858	{
859	/*
860	* Page not present in Guest OS or invalid page table address.
861	* This is potential virtual page access handler food.
862	*
863	* For the present we'll say that our access handlers don't
864	* work for this case - we've already discarded the page table
865	* not present case which is identical to this.
866	*
867	* When we perchance find we need this, we will probably have AVL
868	* trees (offset based) to operate on and we can measure their speed
869	* agains mapping a page table and probably rearrange this handling
870	* a bit. (Like, searching virtual ranges before checking the
871	* physical address.)
872	*/
873	}
874	}
875	/* else: !present (guest) */
876
877
878	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
879	/*
880	* Conclusion, this is a guest trap.
881	*/
882	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
883	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
884	return VINF_EM_RAW_GUEST_TRAP;
885	# else
886	/* present, but not a monitored page; perhaps the guest is probing physical memory */
887	return VINF_EM_RAW_EMULATE_INSTR;
888	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
889
890
891	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
892
893	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
894	return VERR_INTERNAL_ERROR;
895	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
896	}
897	#endif /* !IN_RING3 */
898
899
900	/**
901	* Emulation of the invlpg instruction.
902	*
903	*
904	* @returns VBox status code.
905	*
906	* @param pVM VM handle.
907	* @param pVCpu The VMCPU handle.
908	* @param GCPtrPage Page to invalidate.
909	*
910	* @remark ASSUMES that the guest is updating before invalidating. This order
911	* isn't required by the CPU, so this is speculative and could cause
912	* trouble.
913	*
914	* @todo Flush page or page directory only if necessary!
915	* @todo Add a #define for simply invalidating the page.
916	*/
917	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage)
918	{
919	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
920	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
921	&& PGM_SHW_TYPE != PGM_TYPE_EPT
922	int rc;
923
924	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
925	/*
926	* Get the shadow PD entry and skip out if this PD isn't present.
927	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
928	*/
929	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
930	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
931	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
932
933	/* Fetch the pgm pool shadow descriptor. */
934	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
935	Assert(pShwPde);
936
937	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
938	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
939	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
940
941	/* If the shadow PDPE isn't present, then skip the invalidate. */
942	if (!pPdptDst->a[iPdpt].n.u1Present)
943	{
944	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
945	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
946	return VINF_SUCCESS;
947	}
948
949	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
950	PPGMPOOLPAGE pShwPde = NULL;
951	PX86PDPAE pPDDst;
952
953	/* Fetch the pgm pool shadow descriptor. */
954	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
955	AssertRCSuccessReturn(rc, rc);
956	Assert(pShwPde);
957
958	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
959	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
960
961	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
962	/* PML4 */
963	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
964	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
965	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
966	PX86PDPAE pPDDst;
967	PX86PDPT pPdptDst;
968	PX86PML4E pPml4eDst;
969	rc = pgmShwGetLongModePDPtr(pVM, pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
970	if (rc != VINF_SUCCESS)
971	{
972	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
973	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
974	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
975	PGM_INVL_GUEST_TLBS();
976	return VINF_SUCCESS;
977	}
978	Assert(pPDDst);
979
980	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
981	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
982
983	if (!pPdpeDst->n.u1Present)
984	{
985	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
986	if (!VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
987	PGM_INVL_GUEST_TLBS();
988	return VINF_SUCCESS;
989	}
990
991	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
992
993	const SHWPDE PdeDst = *pPdeDst;
994	if (!PdeDst.n.u1Present)
995	{
996	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
997	return VINF_SUCCESS;
998	}
999
1000	# if defined(IN_RC)
1001	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1002	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1003	# endif
1004
1005	/*
1006	* Get the guest PD entry and calc big page.
1007	*/
1008	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1009	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1010	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1011	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1012	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1013	unsigned iPDSrc = 0;
1014	# if PGM_GST_TYPE == PGM_TYPE_PAE
1015	X86PDPE PdpeSrc;
1016	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1017	# else /* AMD64 */
1018	PX86PML4E pPml4eSrc;
1019	X86PDPE PdpeSrc;
1020	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1021	# endif
1022	GSTPDE PdeSrc;
1023
1024	if (pPDSrc)
1025	PdeSrc = pPDSrc->a[iPDSrc];
1026	else
1027	PdeSrc.u = 0;
1028	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1029
1030	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1031	const bool fIsBigPage = PdeSrc.b.u1Size;
1032	# else
1033	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1034	# endif
1035
1036	# ifdef IN_RING3
1037	/*
1038	* If a CR3 Sync is pending we may ignore the invalidate page operation
1039	* depending on the kind of sync and if it's a global page or not.
1040	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1041	*/
1042	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1043	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
1044	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
1045	&& fIsBigPage
1046	&& PdeSrc.b.u1Global
1047	)
1048	)
1049	# else
1050	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1051	# endif
1052	{
1053	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1054	return VINF_SUCCESS;
1055	}
1056	# endif /* IN_RING3 */
1057
1058	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1059	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1060
1061	/* Fetch the pgm pool shadow descriptor. */
1062	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & X86_PML4E_PG_MASK);
1063	Assert(pShwPdpt);
1064
1065	/* Fetch the pgm pool shadow descriptor. */
1066	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1067	Assert(pShwPde);
1068
1069	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1070	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1071
1072	if ( !pPml4eSrc->n.u1Present
1073	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1074	{
1075	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1076	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1077	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1078	pPml4eDst->u = 0;
1079	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1080	PGM_INVL_GUEST_TLBS();
1081	return VINF_SUCCESS;
1082	}
1083	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1084	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1085	{
1086	/*
1087	* Mark not present so we can resync the PML4E when it's used.
1088	*/
1089	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1090	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1091	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1092	pPml4eDst->u = 0;
1093	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1094	PGM_INVL_GUEST_TLBS();
1095	}
1096	else if (!pPml4eSrc->n.u1Accessed)
1097	{
1098	/*
1099	* Mark not present so we can set the accessed bit.
1100	*/
1101	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1102	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1103	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1104	pPml4eDst->u = 0;
1105	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1106	PGM_INVL_GUEST_TLBS();
1107	}
1108
1109	/* Check if the PDPT entry has changed. */
1110	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1111	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1112	if ( !PdpeSrc.n.u1Present
1113	\|\| pShwPde->GCPhys != GCPhysPd)
1114	{
1115	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1116	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1117	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1118	pPdpeDst->u = 0;
1119	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1120	PGM_INVL_GUEST_TLBS();
1121	return VINF_SUCCESS;
1122	}
1123	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1124	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1125	{
1126	/*
1127	* Mark not present so we can resync the PDPTE when it's used.
1128	*/
1129	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1130	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1131	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1132	pPdpeDst->u = 0;
1133	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1134	PGM_INVL_GUEST_TLBS();
1135	}
1136	else if (!PdpeSrc.lm.u1Accessed)
1137	{
1138	/*
1139	* Mark not present so we can set the accessed bit.
1140	*/
1141	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1142	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1143	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1144	pPdpeDst->u = 0;
1145	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1146	PGM_INVL_GUEST_TLBS();
1147	}
1148	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1149
1150
1151	/*
1152	* Deal with the Guest PDE.
1153	*/
1154	rc = VINF_SUCCESS;
1155	if (PdeSrc.n.u1Present)
1156	{
1157	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1158	{
1159	/*
1160	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1161	*/
1162	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1163	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1164	rc = PGM_BTH_NAME(SyncPT)(pVM, pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1165	}
1166	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1167	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1168	{
1169	/*
1170	* Mark not present so we can resync the PDE when it's used.
1171	*/
1172	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1173	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1174	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1175	pPdeDst->u = 0;
1176	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1177	PGM_INVL_GUEST_TLBS();
1178	}
1179	else if (!PdeSrc.n.u1Accessed)
1180	{
1181	/*
1182	* Mark not present so we can set the accessed bit.
1183	*/
1184	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1185	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1186	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1187	pPdeDst->u = 0;
1188	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1189	PGM_INVL_GUEST_TLBS();
1190	}
1191	else if (!fIsBigPage)
1192	{
1193	/*
1194	* 4KB - page.
1195	*/
1196	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1197	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1198	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1199	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1200	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1201	# endif
1202	if (pShwPage->GCPhys == GCPhys)
1203	{
1204	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1205	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1206	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1207	if (pPT->a[iPTEDst].n.u1Present)
1208	{
1209	# ifdef PGMPOOL_WITH_USER_TRACKING
1210	/* This is very unlikely with caching/monitoring enabled. */
1211	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1212	# endif
1213	pPT->a[iPTEDst].u = 0;
1214	}
1215	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1216	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, GCPtrPage, 1, 0);
1217	if (RT_SUCCESS(rc))
1218	rc = VINF_SUCCESS;
1219	# endif
1220	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1221	PGM_INVL_PG(GCPtrPage);
1222	}
1223	else
1224	{
1225	/*
1226	* The page table address changed.
1227	*/
1228	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1229	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1230	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1231	pPdeDst->u = 0;
1232	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1233	PGM_INVL_GUEST_TLBS();
1234	}
1235	}
1236	else
1237	{
1238	/*
1239	* 2/4MB - page.
1240	*/
1241	/* Before freeing the page, check if anything really changed. */
1242	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1243	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1244	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1245	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1246	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1247	# endif
1248	if ( pShwPage->GCPhys == GCPhys
1249	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1250	{
1251	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1252	/** @todo PAT */
1253	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1254	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1255	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1256	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1257	{
1258	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1259	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1260	# if defined(IN_RC)
1261	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1262	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1263	# endif
1264	return VINF_SUCCESS;
1265	}
1266	}
1267
1268	/*
1269	* Ok, the page table is present and it's been changed in the guest.
1270	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1271	* We could do this for some flushes in GC too, but we need an algorithm for
1272	* deciding which 4MB pages containing code likely to be executed very soon.
1273	*/
1274	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1275	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1276	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1277	pPdeDst->u = 0;
1278	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1279	PGM_INVL_BIG_PG(GCPtrPage);
1280	}
1281	}
1282	else
1283	{
1284	/*
1285	* Page directory is not present, mark shadow PDE not present.
1286	*/
1287	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1288	{
1289	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1290	pPdeDst->u = 0;
1291	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1292	PGM_INVL_PG(GCPtrPage);
1293	}
1294	else
1295	{
1296	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1298	}
1299	}
1300	# if defined(IN_RC)
1301	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1302	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1303	# endif
1304	return rc;
1305
1306	#else /* guest real and protected mode */
1307	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1308	return VINF_SUCCESS;
1309	#endif
1310	}
1311
1312
1313	#ifdef PGMPOOL_WITH_USER_TRACKING
1314	/**
1315	* Update the tracking of shadowed pages.
1316	*
1317	* @param pVM The VM handle.
1318	* @param pVCpu The VMCPU handle.
1319	* @param pShwPage The shadow page.
1320	* @param HCPhys The physical page we is being dereferenced.
1321	*/
1322	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1323	{
1324	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1325	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1326	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1327
1328	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1329	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1330	* 2. write protect all shadowed pages. I.e. implement caching.
1331	*/
1332	/*
1333	* Find the guest address.
1334	*/
1335	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1336	pRam;
1337	pRam = pRam->CTX_SUFF(pNext))
1338	{
1339	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1340	while (iPage-- > 0)
1341	{
1342	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1343	{
1344	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1345	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1346	pShwPage->cPresent--;
1347	pPool->cPresent--;
1348	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1349	return;
1350	}
1351	}
1352	}
1353
1354	for (;;)
1355	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1356	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1357	pShwPage->cPresent--;
1358	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1359	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1360	}
1361
1362
1363	/**
1364	* Update the tracking of shadowed pages.
1365	*
1366	* @param pVM The VM handle.
1367	* @param pVCpu The VMCPU handle.
1368	* @param pShwPage The shadow page.
1369	* @param u16 The top 16-bit of the pPage->HCPhys.
1370	* @param pPage Pointer to the guest page. this will be modified.
1371	* @param iPTDst The index into the shadow table.
1372	*/
1373	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1374	{
1375	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1376	/*
1377	* Just deal with the simple first time here.
1378	*/
1379	if (!u16)
1380	{
1381	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1382	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1383	}
1384	else
1385	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1386
1387	/* write back */
1388	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1389	PGM_PAGE_SET_TRACKING(pPage, u16);
1390
1391	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1392
1393	/* update statistics. */
1394	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1395	pShwPage->cPresent++;
1396	if (pShwPage->iFirstPresent > iPTDst)
1397	pShwPage->iFirstPresent = iPTDst;
1398	}
1399	#endif /* PGMPOOL_WITH_USER_TRACKING */
1400
1401
1402	/**
1403	* Creates a 4K shadow page for a guest page.
1404	*
1405	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1406	* physical address. The PdeSrc argument only the flags are used. No page structured
1407	* will be mapped in this function.
1408	*
1409	* @param pVM VM handle.
1410	* @param pVCpu The VMCPU handle.
1411	* @param pPteDst Destination page table entry.
1412	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1413	* Can safely assume that only the flags are being used.
1414	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1415	* @param pShwPage Pointer to the shadow page.
1416	* @param iPTDst The index into the shadow table.
1417	*
1418	* @remark Not used for 2/4MB pages!
1419	*/
1420	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1421	{
1422	if (PteSrc.n.u1Present)
1423	{
1424	/*
1425	* Find the ram range.
1426	*/
1427	PPGMPAGE pPage;
1428	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1429	if (RT_SUCCESS(rc))
1430	{
1431	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1432	/* Try make the page writable if necessary. */
1433	if ( PteSrc.n.u1Write
1434	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1435	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1436	{
1437	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1438	AssertRC(rc);
1439	}
1440	#endif
1441
1442	/** @todo investiage PWT, PCD and PAT. */
1443	/*
1444	* Make page table entry.
1445	*/
1446	SHWPTE PteDst;
1447	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1448	{
1449	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1450	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1451	{
1452	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1453	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1454	PteDst.n.u1Present = 1;
1455	PteDst.n.u1Execute = 1;
1456	PteDst.n.u1IgnorePAT = 1;
1457	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1458	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1459	#else
1460	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1461	\| PGM_PAGE_GET_HCPHYS(pPage);
1462	#endif
1463	}
1464	else
1465	{
1466	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1467	PteDst.u = 0;
1468	}
1469	/** @todo count these two kinds. */
1470	}
1471	else
1472	{
1473	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1474	/*
1475	* If the page or page directory entry is not marked accessed,
1476	* we mark the page not present.
1477	*/
1478	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1479	{
1480	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1481	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1482	PteDst.u = 0;
1483	}
1484	else
1485	/*
1486	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1487	* when the page is modified.
1488	*/
1489	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1490	{
1491	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1492	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1493	\| PGM_PAGE_GET_HCPHYS(pPage)
1494	\| PGM_PTFLAGS_TRACK_DIRTY;
1495	}
1496	else
1497	#endif
1498	{
1499	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1500	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1501	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1502	PteDst.n.u1Present = 1;
1503	PteDst.n.u1Write = 1;
1504	PteDst.n.u1Execute = 1;
1505	PteDst.n.u1IgnorePAT = 1;
1506	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1507	/* PteDst.n.u1Size = 0 */
1508	#else
1509	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1510	\| PGM_PAGE_GET_HCPHYS(pPage);
1511	#endif
1512	}
1513	}
1514
1515	/*
1516	* Make sure only allocated pages are mapped writable.
1517	*/
1518	if ( PteDst.n.u1Write
1519	&& PteDst.n.u1Present
1520	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1521	{
1522	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1523	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1524	}
1525
1526	#ifdef PGMPOOL_WITH_USER_TRACKING
1527	/*
1528	* Keep user track up to date.
1529	*/
1530	if (PteDst.n.u1Present)
1531	{
1532	if (!pPteDst->n.u1Present)
1533	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1534	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1535	{
1536	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1537	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1538	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1539	}
1540	}
1541	else if (pPteDst->n.u1Present)
1542	{
1543	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1544	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1545	}
1546	#endif /* PGMPOOL_WITH_USER_TRACKING */
1547
1548	/*
1549	* Update statistics and commit the entry.
1550	*/
1551	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1552	if (!PteSrc.n.u1Global)
1553	pShwPage->fSeenNonGlobal = true;
1554	#endif
1555	*pPteDst = PteDst;
1556	}
1557	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1558	/** @todo count these. */
1559	}
1560	else
1561	{
1562	/*
1563	* Page not-present.
1564	*/
1565	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1566	#ifdef PGMPOOL_WITH_USER_TRACKING
1567	/* Keep user track up to date. */
1568	if (pPteDst->n.u1Present)
1569	{
1570	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1571	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1572	}
1573	#endif /* PGMPOOL_WITH_USER_TRACKING */
1574	pPteDst->u = 0;
1575	/** @todo count these. */
1576	}
1577	}
1578
1579
1580	/**
1581	* Syncs a guest OS page.
1582	*
1583	* There are no conflicts at this point, neither is there any need for
1584	* page table allocations.
1585	*
1586	* @returns VBox status code.
1587	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1588	* @param pVM VM handle.
1589	* @param pVCpu The VMCPU handle.
1590	* @param PdeSrc Page directory entry of the guest.
1591	* @param GCPtrPage Guest context page address.
1592	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1593	* @param uErr Fault error (X86_TRAP_PF_*).
1594	*/
1595	PGM_BTH_DECL(int, SyncPage)(PVM pVM, PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1596	{
1597	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1598
1599	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1600	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1601	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1602	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1603	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1604
1605	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1606	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1607	# endif
1608
1609	/*
1610	* Assert preconditions.
1611	*/
1612	Assert(PdeSrc.n.u1Present);
1613	Assert(cPages);
1614	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1615
1616	/*
1617	* Get the shadow PDE, find the shadow page table in the pool.
1618	*/
1619	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1620	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1621	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1622
1623	/* Fetch the pgm pool shadow descriptor. */
1624	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1625	Assert(pShwPde);
1626
1627	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1628	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1629	PPGMPOOLPAGE pShwPde = NULL;
1630	PX86PDPAE pPDDst;
1631
1632	/* Fetch the pgm pool shadow descriptor. */
1633	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1634	AssertRCSuccessReturn(rc, rc);
1635	Assert(pShwPde);
1636
1637	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1638	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1639
1640	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1641	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1642	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1643	PX86PDPAE pPDDst;
1644	PX86PDPT pPdptDst;
1645
1646	int rc = pgmShwGetLongModePDPtr(pVM, pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1647	AssertRCSuccessReturn(rc, rc);
1648	Assert(pPDDst && pPdptDst);
1649	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1650	# endif
1651
1652	SHWPDE PdeDst = *pPdeDst;
1653	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1654	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1655
1656	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1657	/* Fetch the pgm pool shadow descriptor. */
1658	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1659	Assert(pShwPde);
1660	# endif
1661
1662	# if defined(IN_RC)
1663	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1664	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1665	# endif
1666
1667	/*
1668	* Check that the page is present and that the shadow PDE isn't out of sync.
1669	*/
1670	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1671	const bool fBigPage = PdeSrc.b.u1Size;
1672	# else
1673	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1674	# endif
1675	RTGCPHYS GCPhys;
1676	if (!fBigPage)
1677	{
1678	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1679	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1680	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1681	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1682	# endif
1683	}
1684	else
1685	{
1686	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1687	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1688	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1689	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1690	# endif
1691	}
1692	if ( pShwPage->GCPhys == GCPhys
1693	&& PdeSrc.n.u1Present
1694	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1695	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1696	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1697	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1698	# endif
1699	)
1700	{
1701	/*
1702	* Check that the PDE is marked accessed already.
1703	* Since we set the accessed bit before getting here on a #PF, this
1704	* check is only meant for dealing with non-#PF'ing paths.
1705	*/
1706	if (PdeSrc.n.u1Accessed)
1707	{
1708	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1709	if (!fBigPage)
1710	{
1711	/*
1712	* 4KB Page - Map the guest page table.
1713	*/
1714	PGSTPT pPTSrc;
1715	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1716	if (RT_SUCCESS(rc))
1717	{
1718	# ifdef PGM_SYNC_N_PAGES
1719	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1720	if ( cPages > 1
1721	&& !(uErr & X86_TRAP_PF_P)
1722	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1723	{
1724	/*
1725	* This code path is currently only taken when the caller is PGMTrap0eHandler
1726	* for non-present pages!
1727	*
1728	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1729	* deal with locality.
1730	*/
1731	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1732	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1733	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1734	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1735	# else
1736	const unsigned offPTSrc = 0;
1737	# endif
1738	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1739	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1740	iPTDst = 0;
1741	else
1742	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1743	for (; iPTDst < iPTDstEnd; iPTDst++)
1744	{
1745	if (!pPTDst->a[iPTDst].n.u1Present)
1746	{
1747	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1748	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1749	NOREF(GCPtrCurPage);
1750	#ifndef IN_RING0
1751	/*
1752	* Assuming kernel code will be marked as supervisor - and not as user level
1753	* and executed using a conforming code selector - And marked as readonly.
1754	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1755	*/
1756	PPGMPAGE pPage;
1757	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1758	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1759	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1760	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1761	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1762	)
1763	#endif /* else: CSAM not active */
1764	PGM_BTH_NAME(SyncPageWorker)(pVM, pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1765	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1766	GCPtrCurPage, PteSrc.n.u1Present,
1767	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1768	PteSrc.n.u1User & PdeSrc.n.u1User,
1769	(uint64_t)PteSrc.u,
1770	(uint64_t)pPTDst->a[iPTDst].u,
1771	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1772	}
1773	}
1774	}
1775	else
1776	# endif /* PGM_SYNC_N_PAGES */
1777	{
1778	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1779	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1780	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1781	PGM_BTH_NAME(SyncPageWorker)(pVM, pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1782	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1783	GCPtrPage, PteSrc.n.u1Present,
1784	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1785	PteSrc.n.u1User & PdeSrc.n.u1User,
1786	(uint64_t)PteSrc.u,
1787	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1788	}
1789	}
1790	else /* MMIO or invalid page: emulated in #PF handler. */
1791	{
1792	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1793	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1794	}
1795	}
1796	else
1797	{
1798	/*
1799	* 4/2MB page - lazy syncing shadow 4K pages.
1800	* (There are many causes of getting here, it's no longer only CSAM.)
1801	*/
1802	/* Calculate the GC physical address of this 4KB shadow page. */
1803	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1804	/* Find ram range. */
1805	PPGMPAGE pPage;
1806	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1807	if (RT_SUCCESS(rc))
1808	{
1809	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1810	/* Try make the page writable if necessary. */
1811	if ( PdeSrc.n.u1Write
1812	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1813	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1814	{
1815	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1816	AssertRC(rc);
1817	}
1818	# endif
1819
1820	/*
1821	* Make shadow PTE entry.
1822	*/
1823	SHWPTE PteDst;
1824	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1825	\| PGM_PAGE_GET_HCPHYS(pPage);
1826	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1827	{
1828	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1829	PteDst.n.u1Write = 0;
1830	else
1831	PteDst.u = 0;
1832	}
1833	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1834	# ifdef PGMPOOL_WITH_USER_TRACKING
1835	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1836	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1837	# endif
1838	/* Make sure only allocated pages are mapped writable. */
1839	if ( PteDst.n.u1Write
1840	&& PteDst.n.u1Present
1841	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1842	{
1843	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1844	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1845	}
1846
1847	pPTDst->a[iPTDst] = PteDst;
1848
1849
1850	/*
1851	* If the page is not flagged as dirty and is writable, then make it read-only
1852	* at PD level, so we can set the dirty bit when the page is modified.
1853	*
1854	* ASSUMES that page access handlers are implemented on page table entry level.
1855	* Thus we will first catch the dirty access and set PDE.D and restart. If
1856	* there is an access handler, we'll trap again and let it work on the problem.
1857	*/
1858	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1859	* As for invlpg, it simply frees the whole shadow PT.
1860	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1861	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1862	{
1863	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1864	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1865	PdeDst.n.u1Write = 0;
1866	}
1867	else
1868	{
1869	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1870	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1871	}
1872	*pPdeDst = PdeDst;
1873	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1874	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1875	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1876	}
1877	else
1878	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1879	}
1880	# if defined(IN_RC)
1881	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1882	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1883	# endif
1884	return VINF_SUCCESS;
1885	}
1886	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1887	}
1888	else
1889	{
1890	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1891	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1892	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1893	}
1894
1895	/*
1896	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1897	* Yea, I'm lazy.
1898	*/
1899	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1900	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1901
1902	pPdeDst->u = 0;
1903
1904	# if defined(IN_RC)
1905	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1906	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1907	# endif
1908	PGM_INVL_GUEST_TLBS();
1909	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1910
1911	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1912	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1913	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1914	&& !defined(IN_RC)
1915
1916	# ifdef PGM_SYNC_N_PAGES
1917	/*
1918	* Get the shadow PDE, find the shadow page table in the pool.
1919	*/
1920	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1921	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1922
1923	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1924	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1925
1926	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1927	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1928	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1929	PX86PDPAE pPDDst;
1930	X86PDEPAE PdeDst;
1931	PX86PDPT pPdptDst;
1932
1933	int rc = pgmShwGetLongModePDPtr(pVM, pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1934	AssertRCSuccessReturn(rc, rc);
1935	Assert(pPDDst && pPdptDst);
1936	PdeDst = pPDDst->a[iPDDst];
1937	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1938	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1939	PEPTPD pPDDst;
1940	EPTPDE PdeDst;
1941
1942	int rc = pgmShwGetEPTPDPtr(pVM, pVCpu, GCPtrPage, NULL, &pPDDst);
1943	if (rc != VINF_SUCCESS)
1944	{
1945	AssertRC(rc);
1946	return rc;
1947	}
1948	Assert(pPDDst);
1949	PdeDst = pPDDst->a[iPDDst];
1950	# endif
1951	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1952	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1953	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1954
1955	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1956	if ( cPages > 1
1957	&& !(uErr & X86_TRAP_PF_P)
1958	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1959	{
1960	/*
1961	* This code path is currently only taken when the caller is PGMTrap0eHandler
1962	* for non-present pages!
1963	*
1964	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1965	* deal with locality.
1966	*/
1967	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1968	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1969	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1970	iPTDst = 0;
1971	else
1972	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1973	for (; iPTDst < iPTDstEnd; iPTDst++)
1974	{
1975	if (!pPTDst->a[iPTDst].n.u1Present)
1976	{
1977	GSTPTE PteSrc;
1978
1979	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1980
1981	/* Fake the page table entry */
1982	PteSrc.u = GCPtrCurPage;
1983	PteSrc.n.u1Present = 1;
1984	PteSrc.n.u1Dirty = 1;
1985	PteSrc.n.u1Accessed = 1;
1986	PteSrc.n.u1Write = 1;
1987	PteSrc.n.u1User = 1;
1988
1989	PGM_BTH_NAME(SyncPageWorker)(pVM, pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1990
1991	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1992	GCPtrCurPage, PteSrc.n.u1Present,
1993	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1994	PteSrc.n.u1User & PdeSrc.n.u1User,
1995	(uint64_t)PteSrc.u,
1996	(uint64_t)pPTDst->a[iPTDst].u,
1997	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1998
1999	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2000	break;
2001	}
2002	else
2003	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2004	}
2005	}
2006	else
2007	# endif /* PGM_SYNC_N_PAGES */
2008	{
2009	GSTPTE PteSrc;
2010	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2011	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2012
2013	/* Fake the page table entry */
2014	PteSrc.u = GCPtrCurPage;
2015	PteSrc.n.u1Present = 1;
2016	PteSrc.n.u1Dirty = 1;
2017	PteSrc.n.u1Accessed = 1;
2018	PteSrc.n.u1Write = 1;
2019	PteSrc.n.u1User = 1;
2020	PGM_BTH_NAME(SyncPageWorker)(pVM, pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2021
2022	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2023	GCPtrPage, PteSrc.n.u1Present,
2024	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2025	PteSrc.n.u1User & PdeSrc.n.u1User,
2026	(uint64_t)PteSrc.u,
2027	(uint64_t)pPTDst->a[iPTDst].u,
2028	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2029	}
2030	return VINF_SUCCESS;
2031
2032	#else
2033	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2034	return VERR_INTERNAL_ERROR;
2035	#endif
2036	}
2037
2038
2039	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2040	/**
2041	* Investigate page fault and handle write protection page faults caused by
2042	* dirty bit tracking.
2043	*
2044	* @returns VBox status code.
2045	* @param pVM VM handle.
2046	* @param pVCpu The VMCPU handle.
2047	* @param uErr Page fault error code.
2048	* @param pPdeDst Shadow page directory entry.
2049	* @param pPdeSrc Guest page directory entry.
2050	* @param GCPtrPage Guest context page address.
2051	*/
2052	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2053	{
2054	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2055	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2056	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2057	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2058	bool fBigPagesSupported = true;
2059	# else
2060	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2061	# endif
2062	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2063	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2064	# endif
2065	unsigned uPageFaultLevel;
2066	int rc;
2067
2068	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2069	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2070
2071	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2072	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2073
2074	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2075	PX86PML4E pPml4eSrc;
2076	PX86PDPE pPdpeSrc;
2077
2078	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2079	Assert(pPml4eSrc);
2080
2081	/*
2082	* Real page fault? (PML4E level)
2083	*/
2084	if ( (uErr & X86_TRAP_PF_RSVD)
2085	\|\| !pPml4eSrc->n.u1Present
2086	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2087	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2088	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2089	)
2090	{
2091	uPageFaultLevel = 0;
2092	goto l_UpperLevelPageFault;
2093	}
2094	Assert(pPdpeSrc);
2095
2096	# else /* PAE */
2097	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2098	# endif /* PAE */
2099
2100	/*
2101	* Real page fault? (PDPE level)
2102	*/
2103	if ( (uErr & X86_TRAP_PF_RSVD)
2104	\|\| !pPdpeSrc->n.u1Present
2105	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2106	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2107	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2108	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2109	# endif
2110	)
2111	{
2112	uPageFaultLevel = 1;
2113	goto l_UpperLevelPageFault;
2114	}
2115	# endif
2116
2117	/*
2118	* Real page fault? (PDE level)
2119	*/
2120	if ( (uErr & X86_TRAP_PF_RSVD)
2121	\|\| !pPdeSrc->n.u1Present
2122	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2123	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2124	# endif
2125	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2126	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2127	{
2128	uPageFaultLevel = 2;
2129	goto l_UpperLevelPageFault;
2130	}
2131
2132	/*
2133	* First check the easy case where the page directory has been marked read-only to track
2134	* the dirty bit of an emulated BIG page
2135	*/
2136	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2137	{
2138	/* Mark guest page directory as accessed */
2139	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2140	pPml4eSrc->n.u1Accessed = 1;
2141	pPdpeSrc->lm.u1Accessed = 1;
2142	# endif
2143	pPdeSrc->b.u1Accessed = 1;
2144
2145	/*
2146	* Only write protection page faults are relevant here.
2147	*/
2148	if (fWriteFault)
2149	{
2150	/* Mark guest page directory as dirty (BIG page only). */
2151	pPdeSrc->b.u1Dirty = 1;
2152
2153	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2154	{
2155	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2156
2157	Assert(pPdeSrc->b.u1Write);
2158
2159	pPdeDst->n.u1Write = 1;
2160	pPdeDst->n.u1Accessed = 1;
2161	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2162	PGM_INVL_BIG_PG(GCPtrPage);
2163	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2164	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2165	}
2166	}
2167	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2168	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2169	}
2170	/* else: 4KB page table */
2171
2172	/*
2173	* Map the guest page table.
2174	*/
2175	PGSTPT pPTSrc;
2176	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2177	if (RT_SUCCESS(rc))
2178	{
2179	/*
2180	* Real page fault?
2181	*/
2182	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2183	const GSTPTE PteSrc = *pPteSrc;
2184	if ( !PteSrc.n.u1Present
2185	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2186	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2187	# endif
2188	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2189	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2190	)
2191	{
2192	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2193	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2194	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2195
2196	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2197	* See the 2nd case above as well.
2198	*/
2199	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2200	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2201
2202	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2203	return VINF_EM_RAW_GUEST_TRAP;
2204	}
2205	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2206
2207	/*
2208	* Set the accessed bits in the page directory and the page table.
2209	*/
2210	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2211	pPml4eSrc->n.u1Accessed = 1;
2212	pPdpeSrc->lm.u1Accessed = 1;
2213	# endif
2214	pPdeSrc->n.u1Accessed = 1;
2215	pPteSrc->n.u1Accessed = 1;
2216
2217	/*
2218	* Only write protection page faults are relevant here.
2219	*/
2220	if (fWriteFault)
2221	{
2222	/* Write access, so mark guest entry as dirty. */
2223	# ifdef VBOX_WITH_STATISTICS
2224	if (!pPteSrc->n.u1Dirty)
2225	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2226	else
2227	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2228	# endif
2229
2230	pPteSrc->n.u1Dirty = 1;
2231
2232	if (pPdeDst->n.u1Present)
2233	{
2234	#ifndef IN_RING0
2235	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2236	* Our individual shadow handlers will provide more information and force a fatal exit.
2237	*/
2238	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2239	{
2240	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2241	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2242	return VINF_SUCCESS;
2243	}
2244	#endif
2245	/*
2246	* Map shadow page table.
2247	*/
2248	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2249	if (pShwPage)
2250	{
2251	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2252	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2253	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2254	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2255	{
2256	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2257	# ifdef VBOX_STRICT
2258	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2259	if (pPage)
2260	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2261	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2262	# endif
2263	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2264
2265	Assert(pPteSrc->n.u1Write);
2266
2267	pPteDst->n.u1Write = 1;
2268	pPteDst->n.u1Dirty = 1;
2269	pPteDst->n.u1Accessed = 1;
2270	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2271	PGM_INVL_PG(GCPtrPage);
2272
2273	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2274	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2275	}
2276	}
2277	else
2278	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2279	}
2280	}
2281	/** @todo Optimize accessed bit emulation? */
2282	# ifdef VBOX_STRICT
2283	/*
2284	* Sanity check.
2285	*/
2286	else if ( !pPteSrc->n.u1Dirty
2287	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2288	&& pPdeDst->n.u1Present)
2289	{
2290	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
2291	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2292	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2293	if ( pPteDst->n.u1Present
2294	&& pPteDst->n.u1Write)
2295	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2296	}
2297	# endif /* VBOX_STRICT */
2298	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2299	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2300	}
2301	AssertRC(rc);
2302	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2303	return rc;
2304
2305
2306	l_UpperLevelPageFault:
2307	/*
2308	* Pagefault detected while checking the PML4E, PDPE or PDE.
2309	* Single exit handler to get rid of duplicate code paths.
2310	*/
2311	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2312	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2313	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2314
2315	if (
2316	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2317	pPml4eSrc->n.u1Present &&
2318	# endif
2319	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2320	pPdpeSrc->n.u1Present &&
2321	# endif
2322	pPdeSrc->n.u1Present)
2323	{
2324	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2325	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2326	{
2327	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2328	}
2329	else
2330	{
2331	/*
2332	* Map the guest page table.
2333	*/
2334	PGSTPT pPTSrc;
2335	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2336	if (RT_SUCCESS(rc))
2337	{
2338	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2339	const GSTPTE PteSrc = *pPteSrc;
2340	if (pPteSrc->n.u1Present)
2341	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2342	}
2343	AssertRC(rc);
2344	}
2345	}
2346	return VINF_EM_RAW_GUEST_TRAP;
2347	}
2348	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2349
2350
2351	/**
2352	* Sync a shadow page table.
2353	*
2354	* The shadow page table is not present. This includes the case where
2355	* there is a conflict with a mapping.
2356	*
2357	* @returns VBox status code.
2358	* @param pVM VM handle.
2359	* @param pVCpu The VMCPU handle.
2360	* @param iPD Page directory index.
2361	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2362	* Assume this is a temporary mapping.
2363	* @param GCPtrPage GC Pointer of the page that caused the fault
2364	*/
2365	PGM_BTH_DECL(int, SyncPT)(PVM pVM, PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2366	{
2367	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2368	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2369	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2370
2371	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2372	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2373	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2374	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2375	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2376
2377	int rc = VINF_SUCCESS;
2378
2379	/*
2380	* Validate input a little bit.
2381	*/
2382	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2383	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2384	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2385	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2386
2387	/* Fetch the pgm pool shadow descriptor. */
2388	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2389	Assert(pShwPde);
2390
2391	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2392	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2393	PPGMPOOLPAGE pShwPde = NULL;
2394	PX86PDPAE pPDDst;
2395	PSHWPDE pPdeDst;
2396
2397	/* Fetch the pgm pool shadow descriptor. */
2398	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2399	AssertRCSuccessReturn(rc, rc);
2400	Assert(pShwPde);
2401
2402	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2403	pPdeDst = &pPDDst->a[iPDDst];
2404
2405	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2406	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2407	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2408	PX86PDPAE pPDDst;
2409	PX86PDPT pPdptDst;
2410	rc = pgmShwGetLongModePDPtr(pVM, pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2411	AssertRCSuccessReturn(rc, rc);
2412	Assert(pPDDst);
2413	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2414	# endif
2415	SHWPDE PdeDst = *pPdeDst;
2416
2417	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2418	/* Fetch the pgm pool shadow descriptor. */
2419	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2420	Assert(pShwPde);
2421	# endif
2422
2423	# ifndef PGM_WITHOUT_MAPPINGS
2424	/*
2425	* Check for conflicts.
2426	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2427	* HC: Simply resolve the conflict.
2428	*/
2429	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2430	{
2431	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2432	# ifndef IN_RING3
2433	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2434	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2435	return VERR_ADDRESS_CONFLICT;
2436	# else
2437	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2438	Assert(pMapping);
2439	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2440	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2441	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2442	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2443	# else
2444	AssertFailed(); /* can't happen for amd64 */
2445	# endif
2446	if (RT_FAILURE(rc))
2447	{
2448	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2449	return rc;
2450	}
2451	PdeDst = *pPdeDst;
2452	# endif
2453	}
2454	# else /* PGM_WITHOUT_MAPPINGS */
2455	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2456	# endif /* PGM_WITHOUT_MAPPINGS */
2457	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2458
2459	# if defined(IN_RC)
2460	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2461	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2462	# endif
2463
2464	/*
2465	* Sync page directory entry.
2466	*/
2467	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2468	if (PdeSrc.n.u1Present)
2469	{
2470	/*
2471	* Allocate & map the page table.
2472	*/
2473	PSHWPT pPTDst;
2474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2475	const bool fPageTable = !PdeSrc.b.u1Size;
2476	# else
2477	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2478	# endif
2479	PPGMPOOLPAGE pShwPage;
2480	RTGCPHYS GCPhys;
2481	if (fPageTable)
2482	{
2483	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2484	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2485	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2486	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2487	# endif
2488	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2489	}
2490	else
2491	{
2492	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2493	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2494	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2495	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2496	# endif
2497	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2498	}
2499	if (rc == VINF_SUCCESS)
2500	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2501	else if (rc == VINF_PGM_CACHED_PAGE)
2502	{
2503	/*
2504	* The PT was cached, just hook it up.
2505	*/
2506	if (fPageTable)
2507	PdeDst.u = pShwPage->Core.Key
2508	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2509	else
2510	{
2511	PdeDst.u = pShwPage->Core.Key
2512	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2513	/* (see explanation and assumptions further down.) */
2514	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2515	{
2516	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2517	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2518	PdeDst.b.u1Write = 0;
2519	}
2520	}
2521	*pPdeDst = PdeDst;
2522	# if defined(IN_RC)
2523	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2524	# endif
2525	return VINF_SUCCESS;
2526	}
2527	else if (rc == VERR_PGM_POOL_FLUSHED)
2528	{
2529	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2530	# if defined(IN_RC)
2531	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2532	# endif
2533	return VINF_PGM_SYNC_CR3;
2534	}
2535	else
2536	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2537	PdeDst.u &= X86_PDE_AVL_MASK;
2538	PdeDst.u \|= pShwPage->Core.Key;
2539
2540	/*
2541	* Page directory has been accessed (this is a fault situation, remember).
2542	*/
2543	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2544	if (fPageTable)
2545	{
2546	/*
2547	* Page table - 4KB.
2548	*
2549	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2550	*/
2551	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2552	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2553	PGSTPT pPTSrc;
2554	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2555	if (RT_SUCCESS(rc))
2556	{
2557	/*
2558	* Start by syncing the page directory entry so CSAM's TLB trick works.
2559	*/
2560	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2561	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2562	*pPdeDst = PdeDst;
2563	# if defined(IN_RC)
2564	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2565	# endif
2566
2567	/*
2568	* Directory/page user or supervisor privilege: (same goes for read/write)
2569	*
2570	* Directory Page Combined
2571	* U/S U/S U/S
2572	* 0 0 0
2573	* 0 1 0
2574	* 1 0 0
2575	* 1 1 1
2576	*
2577	* Simple AND operation. Table listed for completeness.
2578	*
2579	*/
2580	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2581	# ifdef PGM_SYNC_N_PAGES
2582	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2583	unsigned iPTDst = iPTBase;
2584	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2585	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2586	iPTDst = 0;
2587	else
2588	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2589	# else /* !PGM_SYNC_N_PAGES */
2590	unsigned iPTDst = 0;
2591	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2592	# endif /* !PGM_SYNC_N_PAGES */
2593	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2594	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2595	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2596	# else
2597	const unsigned offPTSrc = 0;
2598	# endif
2599	for (; iPTDst < iPTDstEnd; iPTDst++)
2600	{
2601	const unsigned iPTSrc = iPTDst + offPTSrc;
2602	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2603
2604	if (PteSrc.n.u1Present) /* we've already cleared it above */
2605	{
2606	# ifndef IN_RING0
2607	/*
2608	* Assuming kernel code will be marked as supervisor - and not as user level
2609	* and executed using a conforming code selector - And marked as readonly.
2610	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2611	*/
2612	PPGMPAGE pPage;
2613	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2614	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2615	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2616	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2617	)
2618	# endif
2619	PGM_BTH_NAME(SyncPageWorker)(pVM, pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2620	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2621	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2622	PteSrc.n.u1Present,
2623	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2624	PteSrc.n.u1User & PdeSrc.n.u1User,
2625	(uint64_t)PteSrc.u,
2626	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2627	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2628	}
2629	} /* for PTEs */
2630	}
2631	}
2632	else
2633	{
2634	/*
2635	* Big page - 2/4MB.
2636	*
2637	* We'll walk the ram range list in parallel and optimize lookups.
2638	* We will only sync on shadow page table at a time.
2639	*/
2640	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2641
2642	/**
2643	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2644	*/
2645
2646	/*
2647	* Start by syncing the page directory entry.
2648	*/
2649	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2650	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2651
2652	/*
2653	* If the page is not flagged as dirty and is writable, then make it read-only
2654	* at PD level, so we can set the dirty bit when the page is modified.
2655	*
2656	* ASSUMES that page access handlers are implemented on page table entry level.
2657	* Thus we will first catch the dirty access and set PDE.D and restart. If
2658	* there is an access handler, we'll trap again and let it work on the problem.
2659	*/
2660	/** @todo move the above stuff to a section in the PGM documentation. */
2661	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2662	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2663	{
2664	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2665	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2666	PdeDst.b.u1Write = 0;
2667	}
2668	*pPdeDst = PdeDst;
2669	# if defined(IN_RC)
2670	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2671	# endif
2672
2673	/*
2674	* Fill the shadow page table.
2675	*/
2676	/* Get address and flags from the source PDE. */
2677	SHWPTE PteDstBase;
2678	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2679
2680	/* Loop thru the entries in the shadow PT. */
2681	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2682	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2683	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2684	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2685	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2686	unsigned iPTDst = 0;
2687	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2688	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2689	{
2690	/* Advance ram range list. */
2691	while (pRam && GCPhys > pRam->GCPhysLast)
2692	pRam = pRam->CTX_SUFF(pNext);
2693	if (pRam && GCPhys >= pRam->GCPhys)
2694	{
2695	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2696	do
2697	{
2698	/* Make shadow PTE. */
2699	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2700	SHWPTE PteDst;
2701
2702	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2703	/* Try make the page writable if necessary. */
2704	if ( PteDstBase.n.u1Write
2705	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2706	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2707	{
2708	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2709	AssertRCReturn(rc, rc);
2710	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2711	break;
2712	}
2713	# endif
2714
2715	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2716	{
2717	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2718	{
2719	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2720	PteDst.n.u1Write = 0;
2721	}
2722	else
2723	PteDst.u = 0;
2724	}
2725	# ifndef IN_RING0
2726	/*
2727	* Assuming kernel code will be marked as supervisor and not as user level and executed
2728	* using a conforming code selector. Don't check for readonly, as that implies the whole
2729	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2730	*/
2731	else if ( !PdeSrc.n.u1User
2732	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2733	PteDst.u = 0;
2734	# endif
2735	else
2736	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2737
2738	/* Only map writable pages writable. */
2739	if ( PteDst.n.u1Write
2740	&& PteDst.n.u1Present
2741	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2742	{
2743	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2744	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2745	}
2746
2747	# ifdef PGMPOOL_WITH_USER_TRACKING
2748	if (PteDst.n.u1Present)
2749	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2750	# endif
2751	/* commit it */
2752	pPTDst->a[iPTDst] = PteDst;
2753	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2754	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2755	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2756
2757	/* advance */
2758	GCPhys += PAGE_SIZE;
2759	iHCPage++;
2760	iPTDst++;
2761	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2762	&& GCPhys <= pRam->GCPhysLast);
2763	}
2764	else if (pRam)
2765	{
2766	Log(("Invalid pages at %RGp\n", GCPhys));
2767	do
2768	{
2769	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2770	GCPhys += PAGE_SIZE;
2771	iPTDst++;
2772	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2773	&& GCPhys < pRam->GCPhys);
2774	}
2775	else
2776	{
2777	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2778	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2779	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2780	}
2781	} /* while more PTEs */
2782	} /* 4KB / 4MB */
2783	}
2784	else
2785	AssertRelease(!PdeDst.n.u1Present);
2786
2787	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2788	if (RT_FAILURE(rc))
2789	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2790	return rc;
2791
2792	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2793	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2794	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2795	&& !defined(IN_RC)
2796
2797	/*
2798	* Validate input a little bit.
2799	*/
2800	int rc = VINF_SUCCESS;
2801	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2802	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2803	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2804
2805	/* Fetch the pgm pool shadow descriptor. */
2806	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2807	Assert(pShwPde);
2808
2809	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2810	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2811	PPGMPOOLPAGE pShwPde;
2812	PX86PDPAE pPDDst;
2813	PSHWPDE pPdeDst;
2814
2815	/* Fetch the pgm pool shadow descriptor. */
2816	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2817	AssertRCSuccessReturn(rc, rc);
2818	Assert(pShwPde);
2819
2820	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2821	pPdeDst = &pPDDst->a[iPDDst];
2822
2823	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2824	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2825	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2826	PX86PDPAE pPDDst;
2827	PX86PDPT pPdptDst;
2828	rc = pgmShwGetLongModePDPtr(pVM, pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2829	AssertRCSuccessReturn(rc, rc);
2830	Assert(pPDDst);
2831	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2832
2833	/* Fetch the pgm pool shadow descriptor. */
2834	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2835	Assert(pShwPde);
2836
2837	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2838	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2839	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2840	PEPTPD pPDDst;
2841	PEPTPDPT pPdptDst;
2842
2843	rc = pgmShwGetEPTPDPtr(pVM, pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2844	if (rc != VINF_SUCCESS)
2845	{
2846	AssertRC(rc);
2847	return rc;
2848	}
2849	Assert(pPDDst);
2850	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2851
2852	/* Fetch the pgm pool shadow descriptor. */
2853	PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2854	Assert(pShwPde);
2855	# endif
2856	SHWPDE PdeDst = *pPdeDst;
2857
2858	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2859	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2860
2861	GSTPDE PdeSrc;
2862	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2863	PdeSrc.n.u1Present = 1;
2864	PdeSrc.n.u1Write = 1;
2865	PdeSrc.n.u1Accessed = 1;
2866	PdeSrc.n.u1User = 1;
2867
2868	/*
2869	* Allocate & map the page table.
2870	*/
2871	PSHWPT pPTDst;
2872	PPGMPOOLPAGE pShwPage;
2873	RTGCPHYS GCPhys;
2874
2875	/* Virtual address = physical address */
2876	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2877	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2878
2879	if ( rc == VINF_SUCCESS
2880	\|\| rc == VINF_PGM_CACHED_PAGE)
2881	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2882	else
2883	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2884
2885	PdeDst.u &= X86_PDE_AVL_MASK;
2886	PdeDst.u \|= pShwPage->Core.Key;
2887	PdeDst.n.u1Present = 1;
2888	PdeDst.n.u1Write = 1;
2889	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2890	PdeDst.n.u1Execute = 1;
2891	# else
2892	PdeDst.n.u1User = 1;
2893	PdeDst.n.u1Accessed = 1;
2894	# endif
2895	*pPdeDst = PdeDst;
2896
2897	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2898	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2899	return rc;
2900
2901	#else
2902	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2903	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2904	return VERR_INTERNAL_ERROR;
2905	#endif
2906	}
2907
2908
2909
2910	/**
2911	* Prefetch a page/set of pages.
2912	*
2913	* Typically used to sync commonly used pages before entering raw mode
2914	* after a CR3 reload.
2915	*
2916	* @returns VBox status code.
2917	* @param pVM VM handle.
2918	* @param pVCpu The VMCPU handle.
2919	* @param GCPtrPage Page to invalidate.
2920	*/
2921	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage)
2922	{
2923	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2924	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2925	/*
2926	* Check that all Guest levels thru the PDE are present, getting the
2927	* PD and PDE in the processes.
2928	*/
2929	int rc = VINF_SUCCESS;
2930	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2931	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2932	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2933	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2934	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2935	unsigned iPDSrc;
2936	X86PDPE PdpeSrc;
2937	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
2938	if (!pPDSrc)
2939	return VINF_SUCCESS; /* not present */
2940	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2941	unsigned iPDSrc;
2942	PX86PML4E pPml4eSrc;
2943	X86PDPE PdpeSrc;
2944	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2945	if (!pPDSrc)
2946	return VINF_SUCCESS; /* not present */
2947	# endif
2948	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2949	# else
2950	PGSTPD pPDSrc = NULL;
2951	const unsigned iPDSrc = 0;
2952	GSTPDE PdeSrc;
2953
2954	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2955	PdeSrc.n.u1Present = 1;
2956	PdeSrc.n.u1Write = 1;
2957	PdeSrc.n.u1Accessed = 1;
2958	PdeSrc.n.u1User = 1;
2959	# endif
2960
2961	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2962	{
2963	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2964	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
2965	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2966	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2967	PX86PDPAE pPDDst;
2968	X86PDEPAE PdeDst;
2969	# if PGM_GST_TYPE != PGM_TYPE_PAE
2970	X86PDPE PdpeSrc;
2971
2972	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
2973	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
2974	# endif
2975	int rc = pgmShwSyncPaePDPtr(pVM, pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
2976	if (rc != VINF_SUCCESS)
2977	{
2978	AssertRC(rc);
2979	return rc;
2980	}
2981	Assert(pPDDst);
2982	PdeDst = pPDDst->a[iPDDst];
2983
2984	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2985	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2986	PX86PDPAE pPDDst;
2987	X86PDEPAE PdeDst;
2988
2989	# if PGM_GST_TYPE == PGM_TYPE_PROT
2990	/* AMD-V nested paging */
2991	X86PML4E Pml4eSrc;
2992	X86PDPE PdpeSrc;
2993	PX86PML4E pPml4eSrc = &Pml4eSrc;
2994
2995	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
2996	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
2997	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
2998	# endif
2999
3000	int rc = pgmShwSyncLongModePDPtr(pVM, pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3001	if (rc != VINF_SUCCESS)
3002	{
3003	AssertRC(rc);
3004	return rc;
3005	}
3006	Assert(pPDDst);
3007	PdeDst = pPDDst->a[iPDDst];
3008	# endif
3009	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3010	{
3011	if (!PdeDst.n.u1Present)
3012	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3013	rc = PGM_BTH_NAME(SyncPT)(pVM, pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3014	else
3015	{
3016	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3017	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3018	* makes no sense to prefetch more than one page.
3019	*/
3020	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, GCPtrPage, 1, 0);
3021	if (RT_SUCCESS(rc))
3022	rc = VINF_SUCCESS;
3023	}
3024	}
3025	}
3026	return rc;
3027
3028	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3029	return VINF_SUCCESS; /* ignore */
3030	#endif
3031	}
3032
3033
3034
3035
3036	/**
3037	* Syncs a page during a PGMVerifyAccess() call.
3038	*
3039	* @returns VBox status code (informational included).
3040	* @param pVM VM handle.
3041	* @param pVCpu The VMCPU handle.
3042	* @param GCPtrPage The address of the page to sync.
3043	* @param fPage The effective guest page flags.
3044	* @param uErr The trap error code.
3045	*/
3046	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3047	{
3048	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3049
3050	Assert(!HWACCMIsNestedPagingActive(pVM));
3051	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3052	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3053
3054	# ifndef IN_RING0
3055	if (!(fPage & X86_PTE_US))
3056	{
3057	/*
3058	* Mark this page as safe.
3059	*/
3060	/** @todo not correct for pages that contain both code and data!! */
3061	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3062	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3063	}
3064	# endif
3065
3066	/*
3067	* Get guest PD and index.
3068	*/
3069	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3070	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3071	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3072	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3073	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3074	unsigned iPDSrc = 0;
3075	X86PDPE PdpeSrc;
3076	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3077
3078	if (pPDSrc)
3079	{
3080	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3081	return VINF_EM_RAW_GUEST_TRAP;
3082	}
3083	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3084	unsigned iPDSrc;
3085	PX86PML4E pPml4eSrc;
3086	X86PDPE PdpeSrc;
3087	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3088	if (!pPDSrc)
3089	{
3090	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3091	return VINF_EM_RAW_GUEST_TRAP;
3092	}
3093	# endif
3094	# else
3095	PGSTPD pPDSrc = NULL;
3096	const unsigned iPDSrc = 0;
3097	# endif
3098	int rc = VINF_SUCCESS;
3099
3100	/*
3101	* First check if the shadow pd is present.
3102	*/
3103	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3104	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3105	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3106	PX86PDEPAE pPdeDst;
3107	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3108	PX86PDPAE pPDDst;
3109	# if PGM_GST_TYPE != PGM_TYPE_PAE
3110	X86PDPE PdpeSrc;
3111
3112	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3113	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3114	# endif
3115	rc = pgmShwSyncPaePDPtr(pVM, pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3116	if (rc != VINF_SUCCESS)
3117	{
3118	AssertRC(rc);
3119	return rc;
3120	}
3121	Assert(pPDDst);
3122	pPdeDst = &pPDDst->a[iPDDst];
3123
3124	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3125	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3126	PX86PDPAE pPDDst;
3127	PX86PDEPAE pPdeDst;
3128
3129	# if PGM_GST_TYPE == PGM_TYPE_PROT
3130	/* AMD-V nested paging */
3131	X86PML4E Pml4eSrc;
3132	X86PDPE PdpeSrc;
3133	PX86PML4E pPml4eSrc = &Pml4eSrc;
3134
3135	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3136	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3137	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3138	# endif
3139
3140	rc = pgmShwSyncLongModePDPtr(pVM, pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3141	if (rc != VINF_SUCCESS)
3142	{
3143	AssertRC(rc);
3144	return rc;
3145	}
3146	Assert(pPDDst);
3147	pPdeDst = &pPDDst->a[iPDDst];
3148	# endif
3149
3150	if (!pPdeDst->n.u1Present)
3151	{
3152	# if defined(IN_RC)
3153	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3154	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3155	# endif
3156	rc = PGM_BTH_NAME(SyncPT)(pVM, pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3157	# if defined(IN_RC)
3158	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3159	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3160	# endif
3161	AssertRC(rc);
3162	if (rc != VINF_SUCCESS)
3163	return rc;
3164	}
3165
3166	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3167	/* Check for dirty bit fault */
3168	rc = PGM_BTH_NAME(CheckPageFault)(pVM, pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3169	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3170	Log(("PGMVerifyAccess: success (dirty)\n"));
3171	else
3172	{
3173	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3174	#else
3175	{
3176	GSTPDE PdeSrc;
3177	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3178	PdeSrc.n.u1Present = 1;
3179	PdeSrc.n.u1Write = 1;
3180	PdeSrc.n.u1Accessed = 1;
3181	PdeSrc.n.u1User = 1;
3182
3183	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3184	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3185	if (uErr & X86_TRAP_PF_US)
3186	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3187	else /* supervisor */
3188	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3189
3190	rc = PGM_BTH_NAME(SyncPage)(pVM, pVCpu, PdeSrc, GCPtrPage, 1, 0);
3191	if (RT_SUCCESS(rc))
3192	{
3193	/* Page was successfully synced */
3194	Log2(("PGMVerifyAccess: success (sync)\n"));
3195	rc = VINF_SUCCESS;
3196	}
3197	else
3198	{
3199	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3200	return VINF_EM_RAW_GUEST_TRAP;
3201	}
3202	}
3203	return rc;
3204
3205	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3206
3207	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3208	return VERR_INTERNAL_ERROR;
3209	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3210	}
3211
3212
3213	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3214	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3215	/**
3216	* Figures out which kind of shadow page this guest PDE warrants.
3217	*
3218	* @returns Shadow page kind.
3219	* @param pPdeSrc The guest PDE in question.
3220	* @param cr4 The current guest cr4 value.
3221	*/
3222	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3223	{
3224	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3225	if (!pPdeSrc->n.u1Size)
3226	# else
3227	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3228	# endif
3229	return BTH_PGMPOOLKIND_PT_FOR_PT;
3230	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3231	//{
3232	// case 0:
3233	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3234	// case X86_PDE4M_RW:
3235	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3236	// case X86_PDE4M_US:
3237	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3238	// case X86_PDE4M_RW \| X86_PDE4M_US:
3239	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3240	# if 0
3241	// case X86_PDE4M_PAE_NX:
3242	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3243	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3244	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3245	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3246	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3247	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3248	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3249	# endif
3250	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3251	//}
3252	}
3253	# endif
3254	#endif
3255
3256	#undef MY_STAM_COUNTER_INC
3257	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3258
3259
3260	/**
3261	* Syncs the paging hierarchy starting at CR3.
3262	*
3263	* @returns VBox status code, no specials.
3264	* @param pVM VM handle.
3265	* @param pVCpu The VMCPU handle.
3266	* @param cr0 Guest context CR0 register
3267	* @param cr3 Guest context CR3 register
3268	* @param cr4 Guest context CR4 register
3269	* @param fGlobal Including global page directories or not
3270	*/
3271	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3272	{
3273	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
3274	fGlobal = true; /* Change this CR3 reload to be a global one. */
3275
3276	LogFlow(("SyncCR3 %d\n", fGlobal));
3277
3278	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3279	/*
3280	* Update page access handlers.
3281	* The virtual are always flushed, while the physical are only on demand.
3282	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3283	* have to look into that later because it will have a bad influence on the performance.
3284	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3285	* bird: Yes, but that won't work for aliases.
3286	*/
3287	/** @todo this MUST go away. See #1557. */
3288	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3289	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3290	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3291	#endif
3292
3293	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3294	/*
3295	* Nested / EPT - almost no work.
3296	*/
3297	/** @todo check if this is really necessary; the call does it as well... */
3298	HWACCMFlushTLB(pVM);
3299	return VINF_SUCCESS;
3300
3301	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3302	/*
3303	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3304	* out the shadow parts when the guest modifies its tables.
3305	*/
3306	return VINF_SUCCESS;
3307
3308	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3309
3310	# ifdef PGM_WITHOUT_MAPPINGS
3311	Assert(pVM->pgm.s.fMappingsFixed);
3312	return VINF_SUCCESS;
3313	# else
3314	/* Nothing to do when mappings are fixed. */
3315	if (pVM->pgm.s.fMappingsFixed)
3316	return VINF_SUCCESS;
3317
3318	int rc = PGMMapResolveConflicts(pVM);
3319	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3320	if (rc == VINF_PGM_SYNC_CR3)
3321	{
3322	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3323	return VINF_PGM_SYNC_CR3;
3324	}
3325	# endif
3326	return VINF_SUCCESS;
3327	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3328	}
3329
3330
3331
3332
3333	#ifdef VBOX_STRICT
3334	#ifdef IN_RC
3335	# undef AssertMsgFailed
3336	# define AssertMsgFailed Log
3337	#endif
3338	#ifdef IN_RING3
3339	# include <VBox/dbgf.h>
3340
3341	/**
3342	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3343	*
3344	* @returns VBox status code (VINF_SUCCESS).
3345	* @param pVM The VM handle.
3346	* @param cr3 The root of the hierarchy.
3347	* @param crr The cr4, only PAE and PSE is currently used.
3348	* @param fLongMode Set if long mode, false if not long mode.
3349	* @param cMaxDepth Number of levels to dump.
3350	* @param pHlp Pointer to the output functions.
3351	*/
3352	__BEGIN_DECLS
3353	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3354	__END_DECLS
3355
3356	#endif
3357
3358	/**
3359	* Checks that the shadow page table is in sync with the guest one.
3360	*
3361	* @returns The number of errors.
3362	* @param pVM The virtual machine.
3363	* @param pVCpu The VMCPU handle.
3364	* @param cr3 Guest context CR3 register
3365	* @param cr4 Guest context CR4 register
3366	* @param GCPtr Where to start. Defaults to 0.
3367	* @param cb How much to check. Defaults to everything.
3368	*/
3369	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3370	{
3371	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3372	return 0;
3373	#else
3374	unsigned cErrors = 0;
3375
3376	#if PGM_GST_TYPE == PGM_TYPE_PAE
3377	/** @todo currently broken; crashes below somewhere */
3378	AssertFailed();
3379	#endif
3380
3381	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3382	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3383	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3384
3385	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3386	bool fBigPagesSupported = true;
3387	# else
3388	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3389	# endif
3390	PPGMCPU pPGM = &pVCpu->pgm.s;
3391	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3392	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3393	# ifndef IN_RING0
3394	RTHCPHYS HCPhys; /* general usage. */
3395	# endif
3396	int rc;
3397
3398	/*
3399	* Check that the Guest CR3 and all its mappings are correct.
3400	*/
3401	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3402	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3403	false);
3404	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3405	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3406	rc = PGMShwGetPage(pVM, pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3407	# else
3408	rc = PGMShwGetPage(pVM, pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3409	# endif
3410	AssertRCReturn(rc, 1);
3411	HCPhys = NIL_RTHCPHYS;
3412	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3413	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3414	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3415	pgmGstGet32bitPDPtr(pPGM);
3416	RTGCPHYS GCPhys;
3417	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3418	AssertRCReturn(rc, 1);
3419	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3420	# endif
3421	# endif /* !IN_RING0 */
3422
3423	/*
3424	* Get and check the Shadow CR3.
3425	*/
3426	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3427	unsigned cPDEs = X86_PG_ENTRIES;
3428	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3429	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3430	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3431	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3432	# else
3433	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3434	# endif
3435	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3436	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3437	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3438	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3439	# endif
3440	if (cb != ~(RTGCPTR)0)
3441	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3442
3443	/** @todo call the other two PGMAssert() functions. /
3444
3445	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3446	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3447	# endif
3448
3449	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3450	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3451
3452	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3453	{
3454	PPGMPOOLPAGE pShwPdpt = NULL;
3455	PX86PML4E pPml4eSrc;
3456	PX86PML4E pPml4eDst;
3457	RTGCPHYS GCPhysPdptSrc;
3458
3459	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3460	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3461
3462	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3463	if (!pPml4eDst->n.u1Present)
3464	{
3465	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3466	continue;
3467	}
3468
3469	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3470	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3471
3472	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3473	{
3474	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3475	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3476	cErrors++;
3477	continue;
3478	}
3479
3480	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3481	{
3482	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3483	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3484	cErrors++;
3485	continue;
3486	}
3487
3488	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3489	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3490	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3491	{
3492	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3493	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3494	cErrors++;
3495	continue;
3496	}
3497	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3498	{
3499	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3500
3501	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3502	/*
3503	* Check the PDPTEs too.
3504	*/
3505	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3506
3507	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3508	{
3509	unsigned iPDSrc;
3510	PPGMPOOLPAGE pShwPde = NULL;
3511	PX86PDPE pPdpeDst;
3512	RTGCPHYS GCPhysPdeSrc;
3513	# if PGM_GST_TYPE == PGM_TYPE_PAE
3514	X86PDPE PdpeSrc;
3515	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3516	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3517	# else
3518	PX86PML4E pPml4eSrc;
3519	X86PDPE PdpeSrc;
3520	PX86PDPT pPdptDst;
3521	PX86PDPAE pPDDst;
3522	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3523
3524	rc = pgmShwGetLongModePDPtr(pVM, pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3525	if (rc != VINF_SUCCESS)
3526	{
3527	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3528	GCPtr += 512 * _2M;
3529	continue; /* next PDPTE */
3530	}
3531	Assert(pPDDst);
3532	# endif
3533	Assert(iPDSrc == 0);
3534
3535	pPdpeDst = &pPdptDst->a[iPdpt];
3536
3537	if (!pPdpeDst->n.u1Present)
3538	{
3539	GCPtr += 512 * _2M;
3540	continue; /* next PDPTE */
3541	}
3542
3543	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3544	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3545
3546	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3547	{
3548	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3549	GCPtr += 512 * _2M;
3550	cErrors++;
3551	continue;
3552	}
3553
3554	if (GCPhysPdeSrc != pShwPde->GCPhys)
3555	{
3556	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3557	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3558	# else
3559	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3560	# endif
3561	GCPtr += 512 * _2M;
3562	cErrors++;
3563	continue;
3564	}
3565
3566	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3567	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3568	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3569	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3570	{
3571	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3572	GCPtr += 512 * _2M;
3573	cErrors++;
3574	continue;
3575	}
3576	# endif
3577
3578	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3579	{
3580	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3581	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3582	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3584	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3585	# endif
3586	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3587	/*
3588	* Iterate the shadow page directory.
3589	*/
3590	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3591	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3592
3593	for (;
3594	iPDDst < cPDEs;
3595	iPDDst++, GCPtr += cIncrement)
3596	{
3597	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3598	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3599	# else
3600	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3601	# endif
3602	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3603	{
3604	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3605	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3606	{
3607	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3608	cErrors++;
3609	continue;
3610	}
3611	}
3612	else if ( (PdeDst.u & X86_PDE_P)
3613	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3614	)
3615	{
3616	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3617	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3618	if (!pPoolPage)
3619	{
3620	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3621	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3622	cErrors++;
3623	continue;
3624	}
3625	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3626
3627	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3628	{
3629	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3630	GCPtr, (uint64_t)PdeDst.u));
3631	cErrors++;
3632	}
3633
3634	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3635	{
3636	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3637	GCPtr, (uint64_t)PdeDst.u));
3638	cErrors++;
3639	}
3640
3641	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3642	if (!PdeSrc.n.u1Present)
3643	{
3644	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3645	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3646	cErrors++;
3647	continue;
3648	}
3649
3650	if ( !PdeSrc.b.u1Size
3651	\|\| !fBigPagesSupported)
3652	{
3653	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3654	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3655	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3656	# endif
3657	}
3658	else
3659	{
3660	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3661	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3662	{
3663	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3664	GCPtr, (uint64_t)PdeSrc.u));
3665	cErrors++;
3666	continue;
3667	}
3668	# endif
3669	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3670	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3671	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3672	# endif
3673	}
3674
3675	if ( pPoolPage->enmKind
3676	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3677	{
3678	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3679	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3680	cErrors++;
3681	}
3682
3683	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3684	if (!pPhysPage)
3685	{
3686	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3687	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3688	cErrors++;
3689	continue;
3690	}
3691
3692	if (GCPhysGst != pPoolPage->GCPhys)
3693	{
3694	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3695	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3696	cErrors++;
3697	continue;
3698	}
3699
3700	if ( !PdeSrc.b.u1Size
3701	\|\| !fBigPagesSupported)
3702	{
3703	/*
3704	* Page Table.
3705	*/
3706	const GSTPT *pPTSrc;
3707	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3708	if (RT_FAILURE(rc))
3709	{
3710	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3711	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3712	cErrors++;
3713	continue;
3714	}
3715	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3716	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3717	{
3718	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3719	// (This problem will go away when/if we shadow multiple CR3s.)
3720	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3721	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3722	cErrors++;
3723	continue;
3724	}
3725	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3726	{
3727	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3728	GCPtr, (uint64_t)PdeDst.u));
3729	cErrors++;
3730	continue;
3731	}
3732
3733	/* iterate the page table. */
3734	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3735	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3736	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3737	# else
3738	const unsigned offPTSrc = 0;
3739	# endif
3740	for (unsigned iPT = 0, off = 0;
3741	iPT < RT_ELEMENTS(pPTDst->a);
3742	iPT++, off += PAGE_SIZE)
3743	{
3744	const SHWPTE PteDst = pPTDst->a[iPT];
3745
3746	/* skip not-present entries. */
3747	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3748	continue;
3749	Assert(PteDst.n.u1Present);
3750
3751	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3752	if (!PteSrc.n.u1Present)
3753	{
3754	# ifdef IN_RING3
3755	PGMAssertHandlerAndFlagsInSync(pVM);
3756	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3757	# endif
3758	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3759	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3760	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3761	cErrors++;
3762	continue;
3763	}
3764
3765	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3766	# if 1 /** @todo sync accessed bit properly... */
3767	fIgnoreFlags \|= X86_PTE_A;
3768	# endif
3769
3770	/* match the physical addresses */
3771	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3772	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3773
3774	# ifdef IN_RING3
3775	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3776	if (RT_FAILURE(rc))
3777	{
3778	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3779	{
3780	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3781	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3782	cErrors++;
3783	continue;
3784	}
3785	}
3786	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3787	{
3788	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3789	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3790	cErrors++;
3791	continue;
3792	}
3793	# endif
3794
3795	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3796	if (!pPhysPage)
3797	{
3798	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3799	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3800	{
3801	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3802	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3803	cErrors++;
3804	continue;
3805	}
3806	# endif
3807	if (PteDst.n.u1Write)
3808	{
3809	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3810	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3811	cErrors++;
3812	}
3813	fIgnoreFlags \|= X86_PTE_RW;
3814	}
3815	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3816	{
3817	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3818	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3819	cErrors++;
3820	continue;
3821	}
3822
3823	/* flags */
3824	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3825	{
3826	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3827	{
3828	if (PteDst.n.u1Write)
3829	{
3830	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3831	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3832	cErrors++;
3833	continue;
3834	}
3835	fIgnoreFlags \|= X86_PTE_RW;
3836	}
3837	else
3838	{
3839	if (PteDst.n.u1Present)
3840	{
3841	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3842	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3843	cErrors++;
3844	continue;
3845	}
3846	fIgnoreFlags \|= X86_PTE_P;
3847	}
3848	}
3849	else
3850	{
3851	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3852	{
3853	if (PteDst.n.u1Write)
3854	{
3855	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3856	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3857	cErrors++;
3858	continue;
3859	}
3860	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3861	{
3862	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3863	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3864	cErrors++;
3865	continue;
3866	}
3867	if (PteDst.n.u1Dirty)
3868	{
3869	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3870	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3871	cErrors++;
3872	}
3873	# if 0 /** @todo sync access bit properly... */
3874	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3875	{
3876	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3877	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3878	cErrors++;
3879	}
3880	fIgnoreFlags \|= X86_PTE_RW;
3881	# else
3882	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3883	# endif
3884	}
3885	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3886	{
3887	/* access bit emulation (not implemented). */
3888	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3889	{
3890	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3891	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3892	cErrors++;
3893	continue;
3894	}
3895	if (!PteDst.n.u1Accessed)
3896	{
3897	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3898	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3899	cErrors++;
3900	}
3901	fIgnoreFlags \|= X86_PTE_P;
3902	}
3903	# ifdef DEBUG_sandervl
3904	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3905	# endif
3906	}
3907
3908	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3909	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3910	)
3911	{
3912	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3913	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3914	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3915	cErrors++;
3916	continue;
3917	}
3918	} /* foreach PTE */
3919	}
3920	else
3921	{
3922	/*
3923	* Big Page.
3924	*/
3925	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3926	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3927	{
3928	if (PdeDst.n.u1Write)
3929	{
3930	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3931	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3932	cErrors++;
3933	continue;
3934	}
3935	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3936	{
3937	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3938	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3939	cErrors++;
3940	continue;
3941	}
3942	# if 0 /** @todo sync access bit properly... */
3943	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3944	{
3945	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3946	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3947	cErrors++;
3948	}
3949	fIgnoreFlags \|= X86_PTE_RW;
3950	# else
3951	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3952	# endif
3953	}
3954	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3955	{
3956	/* access bit emulation (not implemented). */
3957	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3958	{
3959	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3960	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3961	cErrors++;
3962	continue;
3963	}
3964	if (!PdeDst.n.u1Accessed)
3965	{
3966	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3967	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3968	cErrors++;
3969	}
3970	fIgnoreFlags \|= X86_PTE_P;
3971	}
3972
3973	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3974	{
3975	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3976	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3977	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3978	cErrors++;
3979	}
3980
3981	/* iterate the page table. */
3982	for (unsigned iPT = 0, off = 0;
3983	iPT < RT_ELEMENTS(pPTDst->a);
3984	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3985	{
3986	const SHWPTE PteDst = pPTDst->a[iPT];
3987
3988	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3989	{
3990	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3991	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3992	cErrors++;
3993	}
3994
3995	/* skip not-present entries. */
3996	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3997	continue;
3998
3999	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4000
4001	/* match the physical addresses */
4002	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4003
4004	# ifdef IN_RING3
4005	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4006	if (RT_FAILURE(rc))
4007	{
4008	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4009	{
4010	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4011	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4012	cErrors++;
4013	}
4014	}
4015	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4016	{
4017	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4018	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4019	cErrors++;
4020	continue;
4021	}
4022	# endif
4023	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4024	if (!pPhysPage)
4025	{
4026	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4027	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4028	{
4029	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4030	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4031	cErrors++;
4032	continue;
4033	}
4034	# endif
4035	if (PteDst.n.u1Write)
4036	{
4037	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4038	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4039	cErrors++;
4040	}
4041	fIgnoreFlags \|= X86_PTE_RW;
4042	}
4043	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4044	{
4045	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4046	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4047	cErrors++;
4048	continue;
4049	}
4050
4051	/* flags */
4052	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4053	{
4054	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4055	{
4056	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4057	{
4058	if (PteDst.n.u1Write)
4059	{
4060	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4061	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4062	cErrors++;
4063	continue;
4064	}
4065	fIgnoreFlags \|= X86_PTE_RW;
4066	}
4067	}
4068	else
4069	{
4070	if (PteDst.n.u1Present)
4071	{
4072	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4073	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4074	cErrors++;
4075	continue;
4076	}
4077	fIgnoreFlags \|= X86_PTE_P;
4078	}
4079	}
4080
4081	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4082	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4083	)
4084	{
4085	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4086	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4087	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4088	cErrors++;
4089	continue;
4090	}
4091	} /* for each PTE */
4092	}
4093	}
4094	/* not present */
4095
4096	} /* for each PDE */
4097
4098	} /* for each PDPTE */
4099
4100	} /* for each PML4E */
4101
4102	# ifdef DEBUG
4103	if (cErrors)
4104	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4105	# endif
4106
4107	#endif /* GST == 32BIT, PAE or AMD64 */
4108	return cErrors;
4109
4110	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4111	}
4112	#endif /* VBOX_STRICT */
4113
4114
4115	/**
4116	* Sets up the CR3 for shadow paging
4117	*
4118	* @returns Strict VBox status code.
4119	* @retval VINF_SUCCESS.
4120	*
4121	* @param pVM VM handle.
4122	* @param pVCpu The VMCPU handle.
4123	* @param GCPhysCR3 The physical address in the CR3 register.
4124	*/
4125	PGM_BTH_DECL(int, MapCR3)(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4126	{
4127	/* Update guest paging info. */
4128	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4129	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4130	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4131
4132	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4133
4134	/*
4135	* Map the page CR3 points at.
4136	*/
4137	RTHCPTR HCPtrGuestCR3;
4138	RTHCPHYS HCPhysGuestCR3;
4139	pgmLock(pVM);
4140	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4141	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4142	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4143	/** @todo this needs some reworking wrt. locking. */
4144	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4145	HCPtrGuestCR3 = NIL_RTHCPTR;
4146	int rc = VINF_SUCCESS;
4147	# else
4148	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4149	# endif
4150	pgmUnlock(pVM);
4151	if (RT_SUCCESS(rc))
4152	{
4153	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4154	if (RT_SUCCESS(rc))
4155	{
4156	# ifdef IN_RC
4157	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4158	# endif
4159	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4160	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4161	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4162	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4163	# endif
4164	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4165
4166	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4167	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4168	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4169	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4170	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4171	# endif
4172	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4173	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4174
4175	/*
4176	* Map the 4 PDs too.
4177	*/
4178	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4179	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4180	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4181	{
4182	if (pGuestPDPT->a[i].n.u1Present)
4183	{
4184	RTHCPTR HCPtr;
4185	RTHCPHYS HCPhys;
4186	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4187	pgmLock(pVM);
4188	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4189	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4190	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4191	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4192	HCPtr = NIL_RTHCPTR;
4193	int rc2 = VINF_SUCCESS;
4194	# else
4195	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4196	# endif
4197	pgmUnlock(pVM);
4198	if (RT_SUCCESS(rc2))
4199	{
4200	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4201	AssertRCReturn(rc, rc);
4202
4203	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4204	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4205	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4206	# endif
4207	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4208	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4209	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
4210	continue;
4211	}
4212	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4213	}
4214
4215	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4216	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4217	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4218	# endif
4219	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4220	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4221	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4222	}
4223
4224	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4225	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4226	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4227	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4228	# endif
4229	# endif
4230	}
4231	else
4232	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4233	}
4234	else
4235	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4236
4237	#else /* prot/real stub */
4238	int rc = VINF_SUCCESS;
4239	#endif
4240
4241	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4242	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4243	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4244	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4245	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4246	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4247
4248	Assert(!HWACCMIsNestedPagingActive(pVM));
4249
4250	/*
4251	* Update the shadow root page as well since that's not fixed.
4252	*/
4253	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4254	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4255	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4256	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4257	PPGMPOOLPAGE pNewShwPageCR3;
4258
4259	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4260	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4261	AssertFatalRC(rc);
4262	rc = VINF_SUCCESS;
4263
4264	/* Mark the page as locked; disallow flushing. */
4265	pgmPoolLockPage(pPool, pNewShwPageCR3);
4266
4267	# ifdef IN_RC
4268	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4269	bool fLog = VMMGCLogDisable(pVM);
4270	pgmLock(pVM);
4271	# endif
4272
4273	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4274	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4275	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4276	# ifdef IN_RING0
4277	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4278	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4279	# elif defined(IN_RC)
4280	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4281	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4282	# else
4283	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4284	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4285	# endif
4286
4287	# ifndef PGM_WITHOUT_MAPPINGS
4288	/*
4289	* Apply all hypervisor mappings to the new CR3.
4290	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4291	* make sure we check for conflicts in the new CR3 root.
4292	*/
4293	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4294	Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
4295	# endif
4296	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4297	AssertRCReturn(rc, rc);
4298	# endif
4299
4300	/* Set the current hypervisor CR3. */
4301	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4302	SELMShadowCR3Changed(pVM, pVCpu);
4303
4304	# ifdef IN_RC
4305	pgmUnlock(pVM);
4306	VMMGCLogRestore(pVM, fLog);
4307	# endif
4308
4309	/* Clean up the old CR3 root. */
4310	if (pOldShwPageCR3)
4311	{
4312	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4313	# ifndef PGM_WITHOUT_MAPPINGS
4314	/* Remove the hypervisor mappings from the shadow page table. */
4315	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4316	# endif
4317	/* Mark the page as unlocked; allow flushing again. */
4318	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4319
4320	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4321	}
4322
4323	# endif
4324
4325	return rc;
4326	}
4327
4328	/**
4329	* Unmaps the shadow CR3.
4330	*
4331	* @returns VBox status, no specials.
4332	* @param pVM VM handle.
4333	* @param pVCpu The VMCPU handle.
4334	*/
4335	PGM_BTH_DECL(int, UnmapCR3)(PVM pVM, PVMCPU pVCpu)
4336	{
4337	LogFlow(("UnmapCR3\n"));
4338
4339	int rc = VINF_SUCCESS;
4340
4341	/*
4342	* Update guest paging info.
4343	*/
4344	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4345	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4346	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4347	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4348	# endif
4349	pVCpu->pgm.s.pGst32BitPdRC = 0;
4350
4351	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4352	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4353	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4354	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4355	# endif
4356	pVCpu->pgm.s.pGstPaePdptRC = 0;
4357	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4358	{
4359	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4360	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4361	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4362	# endif
4363	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4364	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4365	}
4366
4367	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4368	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4369	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4370	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4371	# endif
4372
4373	#else /* prot/real mode stub */
4374	/* nothing to do */
4375	#endif
4376
4377	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4378	/*
4379	* Update shadow paging info.
4380	*/
4381	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4382	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4383	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4384
4385	# if PGM_GST_TYPE != PGM_TYPE_REAL
4386	Assert(!HWACCMIsNestedPagingActive(pVM));
4387	# endif
4388
4389	# ifndef PGM_WITHOUT_MAPPINGS
4390	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4391	/* Remove the hypervisor mappings from the shadow page table. */
4392	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4393	# endif
4394
4395	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4396	{
4397	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4398
4399	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4400
4401	/* Mark the page as unlocked; allow flushing again. */
4402	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4403
4404	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4405	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4406	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4407	pVCpu->pgm.s.pShwPageCR3RC = 0;
4408	pVCpu->pgm.s.iShwUser = 0;
4409	pVCpu->pgm.s.iShwUserTable = 0;
4410	}
4411	# endif
4412	#endif /* !IN_RC*/
4413
4414	return rc;
4415	}
4416

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 18976

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