PGMAllBth.h@ 19775

Last change on this file since 19775 was 19775, checked in by vboxsync, 16 years ago
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1	/* $Id: PGMAllBth.h 19775 2009-05-18 10:15:44Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc;
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc;
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152
153	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
154	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
155	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
156
157	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
158	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
159
160	PX86PDPAE pPDDst;
161	# if PGM_GST_TYPE != PGM_TYPE_PAE
162	X86PDPE PdpeSrc;
163
164	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
165	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
166	# endif
167	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
168	if (rc != VINF_SUCCESS)
169	{
170	AssertRC(rc);
171	return rc;
172	}
173	Assert(pPDDst);
174
175	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
176	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
177	PX86PDPAE pPDDst;
178	# if PGM_GST_TYPE == PGM_TYPE_PROT
179	/* AMD-V nested paging */
180	X86PML4E Pml4eSrc;
181	X86PDPE PdpeSrc;
182	PX86PML4E pPml4eSrc = &Pml4eSrc;
183
184	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
185	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
186	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
187	# endif
188
189	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
190	if (rc != VINF_SUCCESS)
191	{
192	AssertRC(rc);
193	return rc;
194	}
195	Assert(pPDDst);
196
197	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
198	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
199	PEPTPD pPDDst;
200
201	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
202	if (rc != VINF_SUCCESS)
203	{
204	AssertRC(rc);
205	return rc;
206	}
207	Assert(pPDDst);
208	# endif
209
210	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
211	/*
212	* If we successfully correct the write protection fault due to dirty bit
213	* tracking, or this page fault is a genuine one, then return immediately.
214	*/
215	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
216	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
217	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
218	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
219	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
220	{
221	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
222	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
223	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
224	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
225	}
226
227	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
228	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
229
230	/*
231	* A common case is the not-present error caused by lazy page table syncing.
232	*
233	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
234	* so we can safely assume that the shadow PT is present when calling SyncPage later.
235	*
236	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
237	* of mapping conflict and defer to SyncCR3 in R3.
238	* (Again, we do NOT support access handlers for non-present guest pages.)
239	*
240	*/
241	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
242	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
243	# else
244	GSTPDE PdeSrc;
245	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
246	PdeSrc.n.u1Present = 1;
247	PdeSrc.n.u1Write = 1;
248	PdeSrc.n.u1Accessed = 1;
249	PdeSrc.n.u1User = 1;
250	# endif
251	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
252	&& !pPDDst->a[iPDDst].n.u1Present
253	&& PdeSrc.n.u1Present
254	)
255
256	{
257	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
258	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
259	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
260	pgmLock(pVM);
261	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
262	pgmUnlock(pVM);
263	if (RT_SUCCESS(rc))
264	{
265	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
266	return rc;
267	}
268	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
269	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return VINF_PGM_SYNC_CR3;
272	}
273
274	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
275	/*
276	* Check if this address is within any of our mappings.
277	*
278	* This is very fast and it's gonna save us a bit of effort below and prevent
279	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
280	* (BTW, it's impossible to have physical access handlers in a mapping.)
281	*/
282	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
283	{
284	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
285	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
286	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
287	{
288	if (pvFault < pMapping->GCPtr)
289	break;
290	if (pvFault - pMapping->GCPtr < pMapping->cb)
291	{
292	/*
293	* The first thing we check is if we've got an undetected conflict.
294	*/
295	if (!pVM->pgm.s.fMappingsFixed)
296	{
297	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
298	while (iPT-- > 0)
299	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
300	{
301	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
302	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
303	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
304	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
305	return VINF_PGM_SYNC_CR3;
306	}
307	}
308
309	/*
310	* Check if the fault address is in a virtual page access handler range.
311	*/
312	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
313	if ( pCur
314	&& pvFault - pCur->Core.Key < pCur->cb
315	&& uErr & X86_TRAP_PF_RW)
316	{
317	# ifdef IN_RC
318	STAM_PROFILE_START(&pCur->Stat, h);
319	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
320	STAM_PROFILE_STOP(&pCur->Stat, h);
321	# else
322	AssertFailed();
323	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
324	# endif
325	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
326	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
327	return rc;
328	}
329
330	/*
331	* Pretend we're not here and let the guest handle the trap.
332	*/
333	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
334	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
335	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
336	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
337	return VINF_EM_RAW_GUEST_TRAP;
338	}
339	}
340	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
341	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
342	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
343
344	/*
345	* Check if this fault address is flagged for special treatment,
346	* which means we'll have to figure out the physical address and
347	* check flags associated with it.
348	*
349	* ASSUME that we can limit any special access handling to pages
350	* in page tables which the guest believes to be present.
351	*/
352	if (PdeSrc.n.u1Present)
353	{
354	RTGCPHYS GCPhys = NIL_RTGCPHYS;
355
356	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
357	# if PGM_GST_TYPE == PGM_TYPE_AMD64
358	bool fBigPagesSupported = true;
359	# else
360	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
361	# endif
362	if ( PdeSrc.b.u1Size
363	&& fBigPagesSupported)
364	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
365	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
366	else
367	{
368	PGSTPT pPTSrc;
369	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
370	if (RT_SUCCESS(rc))
371	{
372	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
373	if (pPTSrc->a[iPTESrc].n.u1Present)
374	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
375	}
376	}
377	# else
378	/* No paging so the fault address is the physical address */
379	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
380	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
381
382	/*
383	* If we have a GC address we'll check if it has any flags set.
384	*/
385	if (GCPhys != NIL_RTGCPHYS)
386	{
387	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
388
389	PPGMPAGE pPage;
390	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
391	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
392	{
393	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
394	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
395	{
396	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
397	{
398	/*
399	* Physical page access handler.
400	*/
401	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
402	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
403	if (pCur)
404	{
405	# ifdef PGM_SYNC_N_PAGES
406	/*
407	* If the region is write protected and we got a page not present fault, then sync
408	* the pages. If the fault was caused by a read, then restart the instruction.
409	* In case of write access continue to the GC write handler.
410	*
411	* ASSUMES that there is only one handler per page or that they have similar write properties.
412	*/
413	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
414	&& !(uErr & X86_TRAP_PF_P))
415	{
416	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
417	if ( RT_FAILURE(rc)
418	\|\| !(uErr & X86_TRAP_PF_RW)
419	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
420	{
421	AssertRC(rc);
422	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
423	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
424	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
425	return rc;
426	}
427	}
428	# endif
429
430	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
431	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
432	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
433
434	# if defined(IN_RC) \|\| defined(IN_RING0)
435	if (pCur->CTX_SUFF(pfnHandler))
436	{
437	STAM_PROFILE_START(&pCur->Stat, h);
438	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
439	STAM_PROFILE_STOP(&pCur->Stat, h);
440	}
441	else
442	# endif
443	rc = VINF_EM_RAW_EMULATE_INSTR;
444	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
445	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
446	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
447	return rc;
448	}
449	}
450	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
451	else
452	{
453	# ifdef PGM_SYNC_N_PAGES
454	/*
455	* If the region is write protected and we got a page not present fault, then sync
456	* the pages. If the fault was caused by a read, then restart the instruction.
457	* In case of write access continue to the GC write handler.
458	*/
459	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
460	&& !(uErr & X86_TRAP_PF_P))
461	{
462	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
463	if ( RT_FAILURE(rc)
464	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
465	\|\| !(uErr & X86_TRAP_PF_RW))
466	{
467	AssertRC(rc);
468	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
469	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
470	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
471	return rc;
472	}
473	}
474	# endif
475	/*
476	* Ok, it's an virtual page access handler.
477	*
478	* Since it's faster to search by address, we'll do that first
479	* and then retry by GCPhys if that fails.
480	*/
481	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
482	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
483	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
484	*/
485	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
486	if (pCur)
487	{
488	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
489	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
490	\|\| !(uErr & X86_TRAP_PF_P)
491	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
492	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
493
494	if ( pvFault - pCur->Core.Key < pCur->cb
495	&& ( uErr & X86_TRAP_PF_RW
496	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
497	{
498	# ifdef IN_RC
499	STAM_PROFILE_START(&pCur->Stat, h);
500	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
501	STAM_PROFILE_STOP(&pCur->Stat, h);
502	# else
503	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
504	# endif
505	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
506	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
507	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
508	return rc;
509	}
510	/* Unhandled part of a monitored page */
511	}
512	else
513	{
514	/* Check by physical address. */
515	PPGMVIRTHANDLER pCur;
516	unsigned iPage;
517	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
518	&pCur, &iPage);
519	Assert(RT_SUCCESS(rc) \|\| !pCur);
520	if ( pCur
521	&& ( uErr & X86_TRAP_PF_RW
522	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
523	{
524	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
525	# ifdef IN_RC
526	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
527	Assert(off < pCur->cb);
528	STAM_PROFILE_START(&pCur->Stat, h);
529	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
530	STAM_PROFILE_STOP(&pCur->Stat, h);
531	# else
532	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
533	# endif
534	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
535	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
536	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
537	return rc;
538	}
539	}
540	}
541	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
542
543	/*
544	* There is a handled area of the page, but this fault doesn't belong to it.
545	* We must emulate the instruction.
546	*
547	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
548	* we first check if this was a page-not-present fault for a page with only
549	* write access handlers. Restart the instruction if it wasn't a write access.
550	*/
551	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
552
553	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
554	&& !(uErr & X86_TRAP_PF_P))
555	{
556	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
557	if ( RT_FAILURE(rc)
558	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
559	\|\| !(uErr & X86_TRAP_PF_RW))
560	{
561	AssertRC(rc);
562	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
563	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
564	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
565	return rc;
566	}
567	}
568
569	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
570	* It's writing to an unhandled part of the LDT page several million times.
571	*/
572	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
573	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
574	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
575	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
576	return rc;
577	} /* if any kind of handler */
578
579	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
580	if (uErr & X86_TRAP_PF_P)
581	{
582	/*
583	* The page isn't marked, but it might still be monitored by a virtual page access handler.
584	* (ASSUMES no temporary disabling of virtual handlers.)
585	*/
586	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
587	* we should correct both the shadow page table and physical memory flags, and not only check for
588	* accesses within the handler region but for access to pages with virtual handlers. */
589	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
590	if (pCur)
591	{
592	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
593	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
594	\|\| !(uErr & X86_TRAP_PF_P)
595	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
596	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
597
598	if ( pvFault - pCur->Core.Key < pCur->cb
599	&& ( uErr & X86_TRAP_PF_RW
600	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
601	{
602	# ifdef IN_RC
603	STAM_PROFILE_START(&pCur->Stat, h);
604	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
605	STAM_PROFILE_STOP(&pCur->Stat, h);
606	# else
607	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
608	# endif
609	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
610	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
611	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
612	return rc;
613	}
614	}
615	}
616	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
617	}
618	else
619	{
620	/*
621	* When the guest accesses invalid physical memory (e.g. probing
622	* of RAM or accessing a remapped MMIO range), then we'll fall
623	* back to the recompiler to emulate the instruction.
624	*/
625	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
626	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
628	return VINF_EM_RAW_EMULATE_INSTR;
629	}
630
631	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
632
633	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
634	/*
635	* We are here only if page is present in Guest page tables and
636	* trap is not handled by our handlers.
637	*
638	* Check it for page out-of-sync situation.
639	*/
640	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
641
642	if (!(uErr & X86_TRAP_PF_P))
643	{
644	/*
645	* Page is not present in our page tables.
646	* Try to sync it!
647	* BTW, fPageShw is invalid in this branch!
648	*/
649	if (uErr & X86_TRAP_PF_US)
650	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
651	else /* supervisor */
652	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
653
654	# if defined(LOG_ENABLED) && !defined(IN_RING0)
655	RTGCPHYS GCPhys;
656	uint64_t fPageGst;
657	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
658	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
659	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
660	# endif /* LOG_ENABLED */
661
662	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
663	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
664	{
665	uint64_t fPageGst;
666	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
667	if ( RT_SUCCESS(rc)
668	&& !(fPageGst & X86_PTE_US))
669	{
670	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
671	if ( pvFault == (RTGCPTR)pRegFrame->eip
672	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
673	# ifdef CSAM_DETECT_NEW_CODE_PAGES
674	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
675	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
676	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
677	)
678	{
679	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
680	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
681	if (rc != VINF_SUCCESS)
682	{
683	/*
684	* CSAM needs to perform a job in ring 3.
685	*
686	* Sync the page before going to the host context; otherwise we'll end up in a loop if
687	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
688	*/
689	LogFlow(("CSAM ring 3 job\n"));
690	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
691	AssertRC(rc2);
692
693	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
694	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
695	return rc;
696	}
697	}
698	# ifdef CSAM_DETECT_NEW_CODE_PAGES
699	else if ( uErr == X86_TRAP_PF_RW
700	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
701	&& pRegFrame->ecx < 0x10000)
702	{
703	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
704	* to detect loading of new code pages.
705	*/
706
707	/*
708	* Decode the instruction.
709	*/
710	RTGCPTR PC;
711	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
712	if (rc == VINF_SUCCESS)
713	{
714	DISCPUSTATE Cpu;
715	uint32_t cbOp;
716	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
717
718	/* For now we'll restrict this to rep movsw/d instructions */
719	if ( rc == VINF_SUCCESS
720	&& Cpu.pCurInstr->opcode == OP_MOVSWD
721	&& (Cpu.prefix & PREFIX_REP))
722	{
723	CSAMMarkPossibleCodePage(pVM, pvFault);
724	}
725	}
726	}
727	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
728
729	/*
730	* Mark this page as safe.
731	*/
732	/** @todo not correct for pages that contain both code and data!! */
733	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
734	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
735	}
736	}
737	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
738	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
739	if (RT_SUCCESS(rc))
740	{
741	/* The page was successfully synced, return to the guest. */
742	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
743	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
744	return VINF_SUCCESS;
745	}
746	}
747	else /* uErr & X86_TRAP_PF_P: */
748	{
749	/*
750	* Write protected pages is make writable when the guest makes the first
751	* write to it. This happens for pages that are shared, write monitored
752	* and not yet allocated.
753	*
754	* Also, a side effect of not flushing global PDEs are out of sync pages due
755	* to physical monitored regions, that are no longer valid.
756	* Assume for now it only applies to the read/write flag.
757	*/
758	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
759	{
760	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
761	{
762	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
763	GCPhys, pPage, pvFault, uErr));
764	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
765	if (rc != VINF_SUCCESS)
766	{
767	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
768	return rc;
769	}
770	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
771	return VINF_EM_NO_MEMORY;
772	}
773	/// @todo count the above case; else
774	if (uErr & X86_TRAP_PF_US)
775	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
776	else /* supervisor */
777	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
778
779	/*
780	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
781	* page is not present, which is not true in this case.
782	*/
783	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
784	if (RT_SUCCESS(rc))
785	{
786	/*
787	* Page was successfully synced, return to guest.
788	*/
789	# ifdef VBOX_STRICT
790	RTGCPHYS GCPhys;
791	uint64_t fPageGst;
792	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
793	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
794	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
795
796	uint64_t fPageShw;
797	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
798	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
799	# endif /* VBOX_STRICT */
800	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
801	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
802	return VINF_SUCCESS;
803	}
804
805	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
806	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
807	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
808	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
809	{
810	uint64_t fPageGst;
811	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
812	if ( RT_SUCCESS(rc)
813	&& !(fPageGst & X86_PTE_RW))
814	{
815	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
816	if (RT_SUCCESS(rc))
817	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
818	else
819	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
820	return rc;
821	}
822	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
823	}
824	}
825
826	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
827	# ifdef VBOX_STRICT
828	/*
829	* Check for VMM page flags vs. Guest page flags consistency.
830	* Currently only for debug purposes.
831	*/
832	if (RT_SUCCESS(rc))
833	{
834	/* Get guest page flags. */
835	uint64_t fPageGst;
836	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
837	if (RT_SUCCESS(rc))
838	{
839	uint64_t fPageShw;
840	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
841
842	/*
843	* Compare page flags.
844	* Note: we have AVL, A, D bits desynched.
845	*/
846	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
847	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
848	}
849	else
850	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
851	}
852	else
853	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
854	# endif /* VBOX_STRICT */
855	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
856	}
857	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
858	# endif /* PGM_OUT_OF_SYNC_IN_GC */
859	}
860	else /* GCPhys == NIL_RTGCPHYS */
861	{
862	/*
863	* Page not present in Guest OS or invalid page table address.
864	* This is potential virtual page access handler food.
865	*
866	* For the present we'll say that our access handlers don't
867	* work for this case - we've already discarded the page table
868	* not present case which is identical to this.
869	*
870	* When we perchance find we need this, we will probably have AVL
871	* trees (offset based) to operate on and we can measure their speed
872	* agains mapping a page table and probably rearrange this handling
873	* a bit. (Like, searching virtual ranges before checking the
874	* physical address.)
875	*/
876	}
877	}
878	/* else: !present (guest) */
879
880
881	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
882	/*
883	* Conclusion, this is a guest trap.
884	*/
885	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
886	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
887	return VINF_EM_RAW_GUEST_TRAP;
888	# else
889	/* present, but not a monitored page; perhaps the guest is probing physical memory */
890	return VINF_EM_RAW_EMULATE_INSTR;
891	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
892
893
894	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
895
896	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
897	return VERR_INTERNAL_ERROR;
898	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
899	}
900	#endif /* !IN_RING3 */
901
902
903	/**
904	* Emulation of the invlpg instruction.
905	*
906	*
907	* @returns VBox status code.
908	*
909	* @param pVCpu The VMCPU handle.
910	* @param GCPtrPage Page to invalidate.
911	*
912	* @remark ASSUMES that the guest is updating before invalidating. This order
913	* isn't required by the CPU, so this is speculative and could cause
914	* trouble.
915	*
916	* @todo Flush page or page directory only if necessary!
917	* @todo Add a #define for simply invalidating the page.
918	*/
919	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
920	{
921	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
922	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
923	&& PGM_SHW_TYPE != PGM_TYPE_EPT
924	int rc;
925	PVM pVM = pVCpu->CTX_SUFF(pVM);
926	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
927
928	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
929	/*
930	* Get the shadow PD entry and skip out if this PD isn't present.
931	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
932	*/
933	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
934	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
935	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
936
937	/* Fetch the pgm pool shadow descriptor. */
938	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
939	Assert(pShwPde);
940
941	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
942	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
943	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
944
945	/* If the shadow PDPE isn't present, then skip the invalidate. */
946	if (!pPdptDst->a[iPdpt].n.u1Present)
947	{
948	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
949	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
950	return VINF_SUCCESS;
951	}
952
953	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
954	PPGMPOOLPAGE pShwPde = NULL;
955	PX86PDPAE pPDDst;
956
957	/* Fetch the pgm pool shadow descriptor. */
958	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
959	AssertRCSuccessReturn(rc, rc);
960	Assert(pShwPde);
961
962	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
963	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
964
965	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
966	/* PML4 */
967	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
968	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
969	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
970	PX86PDPAE pPDDst;
971	PX86PDPT pPdptDst;
972	PX86PML4E pPml4eDst;
973	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
974	if (rc != VINF_SUCCESS)
975	{
976	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
977	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
978	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
979	PGM_INVL_GUEST_TLBS();
980	return VINF_SUCCESS;
981	}
982	Assert(pPDDst);
983
984	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
985	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
986
987	if (!pPdpeDst->n.u1Present)
988	{
989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
990	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
991	PGM_INVL_GUEST_TLBS();
992	return VINF_SUCCESS;
993	}
994
995	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
996
997	const SHWPDE PdeDst = *pPdeDst;
998	if (!PdeDst.n.u1Present)
999	{
1000	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1001	return VINF_SUCCESS;
1002	}
1003
1004	# if defined(IN_RC)
1005	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1006	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1007	# endif
1008
1009	/*
1010	* Get the guest PD entry and calc big page.
1011	*/
1012	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1013	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1014	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1015	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1016	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1017	unsigned iPDSrc = 0;
1018	# if PGM_GST_TYPE == PGM_TYPE_PAE
1019	X86PDPE PdpeSrc;
1020	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1021	# else /* AMD64 */
1022	PX86PML4E pPml4eSrc;
1023	X86PDPE PdpeSrc;
1024	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1025	# endif
1026	GSTPDE PdeSrc;
1027
1028	if (pPDSrc)
1029	PdeSrc = pPDSrc->a[iPDSrc];
1030	else
1031	PdeSrc.u = 0;
1032	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1033
1034	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1035	const bool fIsBigPage = PdeSrc.b.u1Size;
1036	# else
1037	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1038	# endif
1039
1040	# ifdef IN_RING3
1041	/*
1042	* If a CR3 Sync is pending we may ignore the invalidate page operation
1043	* depending on the kind of sync and if it's a global page or not.
1044	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1045	*/
1046	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1047	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1048	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1049	&& fIsBigPage
1050	&& PdeSrc.b.u1Global
1051	)
1052	)
1053	# else
1054	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1055	# endif
1056	{
1057	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1058	return VINF_SUCCESS;
1059	}
1060	# endif /* IN_RING3 */
1061
1062	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1063	/* Fetch the pgm pool shadow descriptor. */
1064	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1065	Assert(pShwPdpt);
1066
1067	/* Fetch the pgm pool shadow descriptor. */
1068	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1069	Assert(pShwPde);
1070
1071	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1072	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1073
1074	if ( !pPml4eSrc->n.u1Present
1075	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1076	{
1077	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1078	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1079	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1080	ASMAtomicWriteSize(pPml4eDst, 0);
1081	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1082	PGM_INVL_GUEST_TLBS();
1083	return VINF_SUCCESS;
1084	}
1085	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1086	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1087	{
1088	/*
1089	* Mark not present so we can resync the PML4E when it's used.
1090	*/
1091	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1092	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1093	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1094	ASMAtomicWriteSize(pPml4eDst, 0);
1095	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1096	PGM_INVL_GUEST_TLBS();
1097	}
1098	else if (!pPml4eSrc->n.u1Accessed)
1099	{
1100	/*
1101	* Mark not present so we can set the accessed bit.
1102	*/
1103	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1104	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1105	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1106	ASMAtomicWriteSize(pPml4eDst, 0);
1107	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1108	PGM_INVL_GUEST_TLBS();
1109	}
1110
1111	/* Check if the PDPT entry has changed. */
1112	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1113	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1114	if ( !PdpeSrc.n.u1Present
1115	\|\| pShwPde->GCPhys != GCPhysPd)
1116	{
1117	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1118	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1119	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1120	ASMAtomicWriteSize(pPdpeDst, 0);
1121	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1122	PGM_INVL_GUEST_TLBS();
1123	return VINF_SUCCESS;
1124	}
1125	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1126	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1127	{
1128	/*
1129	* Mark not present so we can resync the PDPTE when it's used.
1130	*/
1131	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1132	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1133	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1134	ASMAtomicWriteSize(pPdpeDst, 0);
1135	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1136	PGM_INVL_GUEST_TLBS();
1137	}
1138	else if (!PdpeSrc.lm.u1Accessed)
1139	{
1140	/*
1141	* Mark not present so we can set the accessed bit.
1142	*/
1143	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1144	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1145	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1146	ASMAtomicWriteSize(pPdpeDst, 0);
1147	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1148	PGM_INVL_GUEST_TLBS();
1149	}
1150	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1151
1152	/*
1153	* Deal with the Guest PDE.
1154	*/
1155	rc = VINF_SUCCESS;
1156	if (PdeSrc.n.u1Present)
1157	{
1158	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1159	{
1160	/*
1161	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1162	*/
1163	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1164	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1165	pgmLock(pVM);
1166	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1167	pgmUnlock(pVM);
1168	}
1169	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1170	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1171	{
1172	/*
1173	* Mark not present so we can resync the PDE when it's used.
1174	*/
1175	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1176	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1177	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1178	ASMAtomicWriteSize(pPdeDst, 0);
1179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1180	PGM_INVL_GUEST_TLBS();
1181	}
1182	else if (!PdeSrc.n.u1Accessed)
1183	{
1184	/*
1185	* Mark not present so we can set the accessed bit.
1186	*/
1187	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1188	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1189	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1190	ASMAtomicWriteSize(pPdeDst, 0);
1191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1192	PGM_INVL_GUEST_TLBS();
1193	}
1194	else if (!fIsBigPage)
1195	{
1196	/*
1197	* 4KB - page.
1198	*/
1199	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1200	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1201	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1202	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1203	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1204	# endif
1205	if (pShwPage->GCPhys == GCPhys)
1206	{
1207	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1208	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1209	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1210	if (pPT->a[iPTEDst].n.u1Present)
1211	{
1212	# ifdef PGMPOOL_WITH_USER_TRACKING
1213	/* This is very unlikely with caching/monitoring enabled. */
1214	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1215	# endif
1216	pPT->a[iPTEDst].u = 0;
1217	}
1218	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1219	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1220	if (RT_SUCCESS(rc))
1221	rc = VINF_SUCCESS;
1222	# endif
1223	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1224	PGM_INVL_PG(GCPtrPage);
1225	}
1226	else
1227	{
1228	/*
1229	* The page table address changed.
1230	*/
1231	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1232	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1233	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1234	ASMAtomicWriteSize(pPdeDst, 0);
1235	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1236	PGM_INVL_GUEST_TLBS();
1237	}
1238	}
1239	else
1240	{
1241	/*
1242	* 2/4MB - page.
1243	*/
1244	/* Before freeing the page, check if anything really changed. */
1245	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1246	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1247	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1248	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1249	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1250	# endif
1251	if ( pShwPage->GCPhys == GCPhys
1252	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1253	{
1254	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1255	/** @todo PAT */
1256	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1257	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1258	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1259	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1260	{
1261	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1262	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1263	# if defined(IN_RC)
1264	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1265	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1266	# endif
1267	return VINF_SUCCESS;
1268	}
1269	}
1270
1271	/*
1272	* Ok, the page table is present and it's been changed in the guest.
1273	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1274	* We could do this for some flushes in GC too, but we need an algorithm for
1275	* deciding which 4MB pages containing code likely to be executed very soon.
1276	*/
1277	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1278	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1279	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1280	ASMAtomicWriteSize(pPdeDst, 0);
1281	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1282	PGM_INVL_BIG_PG(GCPtrPage);
1283	}
1284	}
1285	else
1286	{
1287	/*
1288	* Page directory is not present, mark shadow PDE not present.
1289	*/
1290	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1291	{
1292	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1293	ASMAtomicWriteSize(pPdeDst, 0);
1294	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1295	PGM_INVL_PG(GCPtrPage);
1296	}
1297	else
1298	{
1299	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1301	}
1302	}
1303	# if defined(IN_RC)
1304	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1305	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1306	# endif
1307	return rc;
1308
1309	#else /* guest real and protected mode */
1310	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1311	return VINF_SUCCESS;
1312	#endif
1313	}
1314
1315
1316	#ifdef PGMPOOL_WITH_USER_TRACKING
1317	/**
1318	* Update the tracking of shadowed pages.
1319	*
1320	* @param pVCpu The VMCPU handle.
1321	* @param pShwPage The shadow page.
1322	* @param HCPhys The physical page we is being dereferenced.
1323	*/
1324	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1325	{
1326	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1327	PVM pVM = pVCpu->CTX_SUFF(pVM);
1328
1329	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1330	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1331
1332	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1333	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1334	* 2. write protect all shadowed pages. I.e. implement caching.
1335	*/
1336	/*
1337	* Find the guest address.
1338	*/
1339	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1340	pRam;
1341	pRam = pRam->CTX_SUFF(pNext))
1342	{
1343	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1344	while (iPage-- > 0)
1345	{
1346	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1347	{
1348	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1349	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1350	pShwPage->cPresent--;
1351	pPool->cPresent--;
1352	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1353	return;
1354	}
1355	}
1356	}
1357
1358	for (;;)
1359	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1360	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1361	pShwPage->cPresent--;
1362	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1363	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1364	}
1365
1366
1367	/**
1368	* Update the tracking of shadowed pages.
1369	*
1370	* @param pVCpu The VMCPU handle.
1371	* @param pShwPage The shadow page.
1372	* @param u16 The top 16-bit of the pPage->HCPhys.
1373	* @param pPage Pointer to the guest page. this will be modified.
1374	* @param iPTDst The index into the shadow table.
1375	*/
1376	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1377	{
1378	PVM pVM = pVCpu->CTX_SUFF(pVM);
1379	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1380	/*
1381	* Just deal with the simple first time here.
1382	*/
1383	if (!u16)
1384	{
1385	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1386	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1387	}
1388	else
1389	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1390
1391	/* write back */
1392	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1393	PGM_PAGE_SET_TRACKING(pPage, u16);
1394
1395	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1396
1397	/* update statistics. */
1398	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1399	pShwPage->cPresent++;
1400	if (pShwPage->iFirstPresent > iPTDst)
1401	pShwPage->iFirstPresent = iPTDst;
1402	}
1403	#endif /* PGMPOOL_WITH_USER_TRACKING */
1404
1405
1406	/**
1407	* Creates a 4K shadow page for a guest page.
1408	*
1409	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1410	* physical address. The PdeSrc argument only the flags are used. No page structured
1411	* will be mapped in this function.
1412	*
1413	* @param pVCpu The VMCPU handle.
1414	* @param pPteDst Destination page table entry.
1415	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1416	* Can safely assume that only the flags are being used.
1417	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1418	* @param pShwPage Pointer to the shadow page.
1419	* @param iPTDst The index into the shadow table.
1420	*
1421	* @remark Not used for 2/4MB pages!
1422	*/
1423	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1424	{
1425	if (PteSrc.n.u1Present)
1426	{
1427	PVM pVM = pVCpu->CTX_SUFF(pVM);
1428
1429	/*
1430	* Find the ram range.
1431	*/
1432	PPGMPAGE pPage;
1433	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1434	if (RT_SUCCESS(rc))
1435	{
1436	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1437	/* Try make the page writable if necessary. */
1438	if ( PteSrc.n.u1Write
1439	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1440	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1441	{
1442	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1443	AssertRC(rc);
1444	}
1445	#endif
1446
1447	/** @todo investiage PWT, PCD and PAT. */
1448	/*
1449	* Make page table entry.
1450	*/
1451	SHWPTE PteDst;
1452	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1453	{
1454	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1455	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1456	{
1457	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1458	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1459	PteDst.n.u1Present = 1;
1460	PteDst.n.u1Execute = 1;
1461	PteDst.n.u1IgnorePAT = 1;
1462	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1463	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1464	#else
1465	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1466	\| PGM_PAGE_GET_HCPHYS(pPage);
1467	#endif
1468	}
1469	else
1470	{
1471	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1472	PteDst.u = 0;
1473	}
1474	/** @todo count these two kinds. */
1475	}
1476	else
1477	{
1478	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1479	/*
1480	* If the page or page directory entry is not marked accessed,
1481	* we mark the page not present.
1482	*/
1483	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1484	{
1485	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1486	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1487	PteDst.u = 0;
1488	}
1489	else
1490	/*
1491	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1492	* when the page is modified.
1493	*/
1494	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1495	{
1496	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1497	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1498	\| PGM_PAGE_GET_HCPHYS(pPage)
1499	\| PGM_PTFLAGS_TRACK_DIRTY;
1500	}
1501	else
1502	#endif
1503	{
1504	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1505	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1506	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1507	PteDst.n.u1Present = 1;
1508	PteDst.n.u1Write = 1;
1509	PteDst.n.u1Execute = 1;
1510	PteDst.n.u1IgnorePAT = 1;
1511	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1512	/* PteDst.n.u1Size = 0 */
1513	#else
1514	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1515	\| PGM_PAGE_GET_HCPHYS(pPage);
1516	#endif
1517	}
1518	}
1519
1520	/*
1521	* Make sure only allocated pages are mapped writable.
1522	*/
1523	if ( PteDst.n.u1Write
1524	&& PteDst.n.u1Present
1525	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1526	{
1527	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1528	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1529	}
1530
1531	#ifdef PGMPOOL_WITH_USER_TRACKING
1532	/*
1533	* Keep user track up to date.
1534	*/
1535	if (PteDst.n.u1Present)
1536	{
1537	if (!pPteDst->n.u1Present)
1538	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1539	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1540	{
1541	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1542	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1543	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1544	}
1545	}
1546	else if (pPteDst->n.u1Present)
1547	{
1548	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1549	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1550	}
1551	#endif /* PGMPOOL_WITH_USER_TRACKING */
1552
1553	/*
1554	* Update statistics and commit the entry.
1555	*/
1556	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1557	if (!PteSrc.n.u1Global)
1558	pShwPage->fSeenNonGlobal = true;
1559	#endif
1560	ASMAtomicWriteSize(pPteDst, PteDst.u);
1561	}
1562	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1563	/** @todo count these. */
1564	}
1565	else
1566	{
1567	/*
1568	* Page not-present.
1569	*/
1570	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1571	#ifdef PGMPOOL_WITH_USER_TRACKING
1572	/* Keep user track up to date. */
1573	if (pPteDst->n.u1Present)
1574	{
1575	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1576	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1577	}
1578	#endif /* PGMPOOL_WITH_USER_TRACKING */
1579	ASMAtomicWriteSize(pPteDst, 0);
1580	/** @todo count these. */
1581	}
1582	}
1583
1584
1585	/**
1586	* Syncs a guest OS page.
1587	*
1588	* There are no conflicts at this point, neither is there any need for
1589	* page table allocations.
1590	*
1591	* @returns VBox status code.
1592	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1593	* @param pVCpu The VMCPU handle.
1594	* @param PdeSrc Page directory entry of the guest.
1595	* @param GCPtrPage Guest context page address.
1596	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1597	* @param uErr Fault error (X86_TRAP_PF_*).
1598	*/
1599	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1600	{
1601	PVM pVM = pVCpu->CTX_SUFF(pVM);
1602	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1603	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1604
1605	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1606	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1607	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1608	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1609	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1610
1611	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1612	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1613	# endif
1614
1615	/*
1616	* Assert preconditions.
1617	*/
1618	Assert(PdeSrc.n.u1Present);
1619	Assert(cPages);
1620	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1621
1622	/*
1623	* Get the shadow PDE, find the shadow page table in the pool.
1624	*/
1625	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1626	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1627	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1628
1629	/* Fetch the pgm pool shadow descriptor. */
1630	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1631	Assert(pShwPde);
1632
1633	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1634	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1635	PPGMPOOLPAGE pShwPde = NULL;
1636	PX86PDPAE pPDDst;
1637
1638	/* Fetch the pgm pool shadow descriptor. */
1639	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1640	AssertRCSuccessReturn(rc, rc);
1641	Assert(pShwPde);
1642
1643	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1644	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1645
1646	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1647	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1648	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1649	PX86PDPAE pPDDst;
1650	PX86PDPT pPdptDst;
1651
1652	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1653	AssertRCSuccessReturn(rc, rc);
1654	Assert(pPDDst && pPdptDst);
1655	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1656	# endif
1657	SHWPDE PdeDst = *pPdeDst;
1658	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1659	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1660
1661	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1662	/* Fetch the pgm pool shadow descriptor. */
1663	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1664	Assert(pShwPde);
1665	# endif
1666
1667	# if defined(IN_RC)
1668	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1669	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1670	# endif
1671
1672	/*
1673	* Check that the page is present and that the shadow PDE isn't out of sync.
1674	*/
1675	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1676	const bool fBigPage = PdeSrc.b.u1Size;
1677	# else
1678	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1679	# endif
1680	RTGCPHYS GCPhys;
1681	if (!fBigPage)
1682	{
1683	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1684	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1685	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1686	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1687	# endif
1688	}
1689	else
1690	{
1691	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1692	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1693	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1694	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1695	# endif
1696	}
1697	if ( pShwPage->GCPhys == GCPhys
1698	&& PdeSrc.n.u1Present
1699	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1700	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1701	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1702	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1703	# endif
1704	)
1705	{
1706	/*
1707	* Check that the PDE is marked accessed already.
1708	* Since we set the accessed bit before getting here on a #PF, this
1709	* check is only meant for dealing with non-#PF'ing paths.
1710	*/
1711	if (PdeSrc.n.u1Accessed)
1712	{
1713	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1714	if (!fBigPage)
1715	{
1716	/*
1717	* 4KB Page - Map the guest page table.
1718	*/
1719	PGSTPT pPTSrc;
1720	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1721	if (RT_SUCCESS(rc))
1722	{
1723	# ifdef PGM_SYNC_N_PAGES
1724	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1725	if ( cPages > 1
1726	&& !(uErr & X86_TRAP_PF_P)
1727	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1728	{
1729	/*
1730	* This code path is currently only taken when the caller is PGMTrap0eHandler
1731	* for non-present pages!
1732	*
1733	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1734	* deal with locality.
1735	*/
1736	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1737	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1738	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1739	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1740	# else
1741	const unsigned offPTSrc = 0;
1742	# endif
1743	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1744	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1745	iPTDst = 0;
1746	else
1747	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1748	for (; iPTDst < iPTDstEnd; iPTDst++)
1749	{
1750	if (!pPTDst->a[iPTDst].n.u1Present)
1751	{
1752	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1753	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1754	NOREF(GCPtrCurPage);
1755	#ifndef IN_RING0
1756	/*
1757	* Assuming kernel code will be marked as supervisor - and not as user level
1758	* and executed using a conforming code selector - And marked as readonly.
1759	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1760	*/
1761	PPGMPAGE pPage;
1762	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1763	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1764	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1765	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1766	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1767	)
1768	#endif /* else: CSAM not active */
1769	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1770	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1771	GCPtrCurPage, PteSrc.n.u1Present,
1772	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1773	PteSrc.n.u1User & PdeSrc.n.u1User,
1774	(uint64_t)PteSrc.u,
1775	(uint64_t)pPTDst->a[iPTDst].u,
1776	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1777	}
1778	}
1779	}
1780	else
1781	# endif /* PGM_SYNC_N_PAGES */
1782	{
1783	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1784	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1785	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1786	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1787	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1788	GCPtrPage, PteSrc.n.u1Present,
1789	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1790	PteSrc.n.u1User & PdeSrc.n.u1User,
1791	(uint64_t)PteSrc.u,
1792	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1793	}
1794	}
1795	else /* MMIO or invalid page: emulated in #PF handler. */
1796	{
1797	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1798	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1799	}
1800	}
1801	else
1802	{
1803	/*
1804	* 4/2MB page - lazy syncing shadow 4K pages.
1805	* (There are many causes of getting here, it's no longer only CSAM.)
1806	*/
1807	/* Calculate the GC physical address of this 4KB shadow page. */
1808	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1809	/* Find ram range. */
1810	PPGMPAGE pPage;
1811	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1812	if (RT_SUCCESS(rc))
1813	{
1814	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1815	/* Try make the page writable if necessary. */
1816	if ( PdeSrc.n.u1Write
1817	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1818	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1819	{
1820	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1821	AssertRC(rc);
1822	}
1823	# endif
1824
1825	/*
1826	* Make shadow PTE entry.
1827	*/
1828	SHWPTE PteDst;
1829	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1830	\| PGM_PAGE_GET_HCPHYS(pPage);
1831	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1832	{
1833	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1834	PteDst.n.u1Write = 0;
1835	else
1836	PteDst.u = 0;
1837	}
1838	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1839	# ifdef PGMPOOL_WITH_USER_TRACKING
1840	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1841	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1842	# endif
1843	/* Make sure only allocated pages are mapped writable. */
1844	if ( PteDst.n.u1Write
1845	&& PteDst.n.u1Present
1846	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1847	{
1848	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1849	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1850	}
1851
1852	pPTDst->a[iPTDst] = PteDst;
1853
1854
1855	/*
1856	* If the page is not flagged as dirty and is writable, then make it read-only
1857	* at PD level, so we can set the dirty bit when the page is modified.
1858	*
1859	* ASSUMES that page access handlers are implemented on page table entry level.
1860	* Thus we will first catch the dirty access and set PDE.D and restart. If
1861	* there is an access handler, we'll trap again and let it work on the problem.
1862	*/
1863	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1864	* As for invlpg, it simply frees the whole shadow PT.
1865	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1866	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1867	{
1868	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1869	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1870	PdeDst.n.u1Write = 0;
1871	}
1872	else
1873	{
1874	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1875	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1876	}
1877	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1878	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1879	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1880	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1881	}
1882	else
1883	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1884	}
1885	# if defined(IN_RC)
1886	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1887	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1888	# endif
1889	return VINF_SUCCESS;
1890	}
1891	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1892	}
1893	else
1894	{
1895	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1896	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1897	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1898	}
1899
1900	/*
1901	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1902	* Yea, I'm lazy.
1903	*/
1904	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1905	ASMAtomicWriteSize(pPdeDst, 0);
1906
1907	# if defined(IN_RC)
1908	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1909	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1910	# endif
1911	PGM_INVL_GUEST_TLBS();
1912	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1913
1914	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1915	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1916	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1917	&& !defined(IN_RC)
1918
1919	# ifdef PGM_SYNC_N_PAGES
1920	/*
1921	* Get the shadow PDE, find the shadow page table in the pool.
1922	*/
1923	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1924	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1925
1926	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1927	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1928
1929	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1930	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1931	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1932	PX86PDPAE pPDDst;
1933	X86PDEPAE PdeDst;
1934	PX86PDPT pPdptDst;
1935
1936	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1937	AssertRCSuccessReturn(rc, rc);
1938	Assert(pPDDst && pPdptDst);
1939	PdeDst = pPDDst->a[iPDDst];
1940	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1941	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1942	PEPTPD pPDDst;
1943	EPTPDE PdeDst;
1944
1945	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1946	if (rc != VINF_SUCCESS)
1947	{
1948	AssertRC(rc);
1949	return rc;
1950	}
1951	Assert(pPDDst);
1952	PdeDst = pPDDst->a[iPDDst];
1953	# endif
1954	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1955	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1956	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1957
1958	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1959	if ( cPages > 1
1960	&& !(uErr & X86_TRAP_PF_P)
1961	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1962	{
1963	/*
1964	* This code path is currently only taken when the caller is PGMTrap0eHandler
1965	* for non-present pages!
1966	*
1967	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1968	* deal with locality.
1969	*/
1970	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1971	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1972	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1973	iPTDst = 0;
1974	else
1975	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1976	for (; iPTDst < iPTDstEnd; iPTDst++)
1977	{
1978	if (!pPTDst->a[iPTDst].n.u1Present)
1979	{
1980	GSTPTE PteSrc;
1981
1982	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1983
1984	/* Fake the page table entry */
1985	PteSrc.u = GCPtrCurPage;
1986	PteSrc.n.u1Present = 1;
1987	PteSrc.n.u1Dirty = 1;
1988	PteSrc.n.u1Accessed = 1;
1989	PteSrc.n.u1Write = 1;
1990	PteSrc.n.u1User = 1;
1991
1992	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1993
1994	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1995	GCPtrCurPage, PteSrc.n.u1Present,
1996	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1997	PteSrc.n.u1User & PdeSrc.n.u1User,
1998	(uint64_t)PteSrc.u,
1999	(uint64_t)pPTDst->a[iPTDst].u,
2000	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2001
2002	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2003	break;
2004	}
2005	else
2006	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2007	}
2008	}
2009	else
2010	# endif /* PGM_SYNC_N_PAGES */
2011	{
2012	GSTPTE PteSrc;
2013	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2014	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2015
2016	/* Fake the page table entry */
2017	PteSrc.u = GCPtrCurPage;
2018	PteSrc.n.u1Present = 1;
2019	PteSrc.n.u1Dirty = 1;
2020	PteSrc.n.u1Accessed = 1;
2021	PteSrc.n.u1Write = 1;
2022	PteSrc.n.u1User = 1;
2023	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2024
2025	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2026	GCPtrPage, PteSrc.n.u1Present,
2027	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2028	PteSrc.n.u1User & PdeSrc.n.u1User,
2029	(uint64_t)PteSrc.u,
2030	(uint64_t)pPTDst->a[iPTDst].u,
2031	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2032	}
2033	return VINF_SUCCESS;
2034
2035	#else
2036	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2037	return VERR_INTERNAL_ERROR;
2038	#endif
2039	}
2040
2041
2042	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2043	/**
2044	* Investigate page fault and handle write protection page faults caused by
2045	* dirty bit tracking.
2046	*
2047	* @returns VBox status code.
2048	* @param pVCpu The VMCPU handle.
2049	* @param uErr Page fault error code.
2050	* @param pPdeDst Shadow page directory entry.
2051	* @param pPdeSrc Guest page directory entry.
2052	* @param GCPtrPage Guest context page address.
2053	*/
2054	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2055	{
2056	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2057	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2058	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2059	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2060	bool fBigPagesSupported = true;
2061	# else
2062	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2063	# endif
2064	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2065	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2066	# endif
2067	unsigned uPageFaultLevel;
2068	int rc;
2069	PVM pVM = pVCpu->CTX_SUFF(pVM);
2070	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2071
2072	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2073	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2074
2075	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2076	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2077
2078	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2079	PX86PML4E pPml4eSrc;
2080	PX86PDPE pPdpeSrc;
2081
2082	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2083	Assert(pPml4eSrc);
2084
2085	/*
2086	* Real page fault? (PML4E level)
2087	*/
2088	if ( (uErr & X86_TRAP_PF_RSVD)
2089	\|\| !pPml4eSrc->n.u1Present
2090	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2091	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2092	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2093	)
2094	{
2095	uPageFaultLevel = 0;
2096	goto l_UpperLevelPageFault;
2097	}
2098	Assert(pPdpeSrc);
2099
2100	# else /* PAE */
2101	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2102	# endif /* PAE */
2103
2104	/*
2105	* Real page fault? (PDPE level)
2106	*/
2107	if ( (uErr & X86_TRAP_PF_RSVD)
2108	\|\| !pPdpeSrc->n.u1Present
2109	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2110	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2111	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2112	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2113	# endif
2114	)
2115	{
2116	uPageFaultLevel = 1;
2117	goto l_UpperLevelPageFault;
2118	}
2119	# endif
2120
2121	/*
2122	* Real page fault? (PDE level)
2123	*/
2124	if ( (uErr & X86_TRAP_PF_RSVD)
2125	\|\| !pPdeSrc->n.u1Present
2126	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2127	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2128	# endif
2129	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2130	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2131	{
2132	uPageFaultLevel = 2;
2133	goto l_UpperLevelPageFault;
2134	}
2135
2136	/*
2137	* First check the easy case where the page directory has been marked read-only to track
2138	* the dirty bit of an emulated BIG page
2139	*/
2140	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2141	{
2142	/* Mark guest page directory as accessed */
2143	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2144	pPml4eSrc->n.u1Accessed = 1;
2145	pPdpeSrc->lm.u1Accessed = 1;
2146	# endif
2147	pPdeSrc->b.u1Accessed = 1;
2148
2149	/*
2150	* Only write protection page faults are relevant here.
2151	*/
2152	if (fWriteFault)
2153	{
2154	/* Mark guest page directory as dirty (BIG page only). */
2155	pPdeSrc->b.u1Dirty = 1;
2156
2157	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2158	{
2159	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2160
2161	Assert(pPdeSrc->b.u1Write);
2162
2163	pPdeDst->n.u1Write = 1;
2164	pPdeDst->n.u1Accessed = 1;
2165	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2166	PGM_INVL_BIG_PG(GCPtrPage);
2167	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2168	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2169	}
2170	}
2171	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2172	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2173	}
2174	/* else: 4KB page table */
2175
2176	/*
2177	* Map the guest page table.
2178	*/
2179	PGSTPT pPTSrc;
2180	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2181	if (RT_SUCCESS(rc))
2182	{
2183	/*
2184	* Real page fault?
2185	*/
2186	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2187	const GSTPTE PteSrc = *pPteSrc;
2188	if ( !PteSrc.n.u1Present
2189	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2190	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2191	# endif
2192	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2193	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2194	)
2195	{
2196	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2197	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2198	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2199
2200	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2201	* See the 2nd case above as well.
2202	*/
2203	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2204	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2205
2206	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2207	return VINF_EM_RAW_GUEST_TRAP;
2208	}
2209	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2210
2211	/*
2212	* Set the accessed bits in the page directory and the page table.
2213	*/
2214	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2215	pPml4eSrc->n.u1Accessed = 1;
2216	pPdpeSrc->lm.u1Accessed = 1;
2217	# endif
2218	pPdeSrc->n.u1Accessed = 1;
2219	pPteSrc->n.u1Accessed = 1;
2220
2221	/*
2222	* Only write protection page faults are relevant here.
2223	*/
2224	if (fWriteFault)
2225	{
2226	/* Write access, so mark guest entry as dirty. */
2227	# ifdef VBOX_WITH_STATISTICS
2228	if (!pPteSrc->n.u1Dirty)
2229	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2230	else
2231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2232	# endif
2233
2234	pPteSrc->n.u1Dirty = 1;
2235
2236	if (pPdeDst->n.u1Present)
2237	{
2238	#ifndef IN_RING0
2239	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2240	* Our individual shadow handlers will provide more information and force a fatal exit.
2241	*/
2242	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2243	{
2244	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2245	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2246	return VINF_SUCCESS;
2247	}
2248	#endif
2249	/*
2250	* Map shadow page table.
2251	*/
2252	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2253	if (pShwPage)
2254	{
2255	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2256	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2257	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
2258	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
2259	{
2260	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2261	# ifdef VBOX_STRICT
2262	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2263	if (pPage)
2264	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2265	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2266	# endif
2267	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2268
2269	Assert(pPteSrc->n.u1Write);
2270
2271	pPteDst->n.u1Write = 1;
2272	pPteDst->n.u1Dirty = 1;
2273	pPteDst->n.u1Accessed = 1;
2274	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2275	PGM_INVL_PG(GCPtrPage);
2276
2277	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2278	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2279	}
2280	}
2281	else
2282	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2283	}
2284	}
2285	/** @todo Optimize accessed bit emulation? */
2286	# ifdef VBOX_STRICT
2287	/*
2288	* Sanity check.
2289	*/
2290	else if ( !pPteSrc->n.u1Dirty
2291	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2292	&& pPdeDst->n.u1Present)
2293	{
2294	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2295	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2296	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2297	if ( pPteDst->n.u1Present
2298	&& pPteDst->n.u1Write)
2299	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2300	}
2301	# endif /* VBOX_STRICT */
2302	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2303	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2304	}
2305	AssertRC(rc);
2306	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2307	return rc;
2308
2309
2310	l_UpperLevelPageFault:
2311	/*
2312	* Pagefault detected while checking the PML4E, PDPE or PDE.
2313	* Single exit handler to get rid of duplicate code paths.
2314	*/
2315	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2316	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2317	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2318
2319	if (
2320	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2321	pPml4eSrc->n.u1Present &&
2322	# endif
2323	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2324	pPdpeSrc->n.u1Present &&
2325	# endif
2326	pPdeSrc->n.u1Present)
2327	{
2328	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2329	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2330	{
2331	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2332	}
2333	else
2334	{
2335	/*
2336	* Map the guest page table.
2337	*/
2338	PGSTPT pPTSrc;
2339	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2340	if (RT_SUCCESS(rc))
2341	{
2342	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2343	const GSTPTE PteSrc = *pPteSrc;
2344	if (pPteSrc->n.u1Present)
2345	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2346	}
2347	AssertRC(rc);
2348	}
2349	}
2350	return VINF_EM_RAW_GUEST_TRAP;
2351	}
2352	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2353
2354
2355	/**
2356	* Sync a shadow page table.
2357	*
2358	* The shadow page table is not present. This includes the case where
2359	* there is a conflict with a mapping.
2360	*
2361	* @returns VBox status code.
2362	* @param pVCpu The VMCPU handle.
2363	* @param iPD Page directory index.
2364	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2365	* Assume this is a temporary mapping.
2366	* @param GCPtrPage GC Pointer of the page that caused the fault
2367	*/
2368	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2369	{
2370	PVM pVM = pVCpu->CTX_SUFF(pVM);
2371	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2372
2373	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2374	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2375	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2376
2377	Assert(PGMIsLocked(pVM));
2378
2379	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2380	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2381	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2382	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2383	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2384
2385	int rc = VINF_SUCCESS;
2386
2387	/*
2388	* Validate input a little bit.
2389	*/
2390	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2391	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2392	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2393	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2394
2395	/* Fetch the pgm pool shadow descriptor. */
2396	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2397	Assert(pShwPde);
2398
2399	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2400	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2401	PPGMPOOLPAGE pShwPde = NULL;
2402	PX86PDPAE pPDDst;
2403	PSHWPDE pPdeDst;
2404
2405	/* Fetch the pgm pool shadow descriptor. */
2406	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2407	AssertRCSuccessReturn(rc, rc);
2408	Assert(pShwPde);
2409
2410	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2411	pPdeDst = &pPDDst->a[iPDDst];
2412
2413	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2414	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2415	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2416	PX86PDPAE pPDDst;
2417	PX86PDPT pPdptDst;
2418	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2419	AssertRCSuccessReturn(rc, rc);
2420	Assert(pPDDst);
2421	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2422	# endif
2423	SHWPDE PdeDst = *pPdeDst;
2424
2425	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2426	/* Fetch the pgm pool shadow descriptor. */
2427	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2428	Assert(pShwPde);
2429	# endif
2430
2431	# ifndef PGM_WITHOUT_MAPPINGS
2432	/*
2433	* Check for conflicts.
2434	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2435	* HC: Simply resolve the conflict.
2436	*/
2437	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2438	{
2439	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2440	# ifndef IN_RING3
2441	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2442	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2443	return VERR_ADDRESS_CONFLICT;
2444	# else
2445	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2446	Assert(pMapping);
2447	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2448	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2449	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2450	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2451	# else
2452	AssertFailed(); /* can't happen for amd64 */
2453	# endif
2454	if (RT_FAILURE(rc))
2455	{
2456	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2457	return rc;
2458	}
2459	PdeDst = *pPdeDst;
2460	# endif
2461	}
2462	# else /* PGM_WITHOUT_MAPPINGS */
2463	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2464	# endif /* PGM_WITHOUT_MAPPINGS */
2465	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2466
2467	# if defined(IN_RC)
2468	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2469	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2470	# endif
2471
2472	/*
2473	* Sync page directory entry.
2474	*/
2475	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2476	if (PdeSrc.n.u1Present)
2477	{
2478	/*
2479	* Allocate & map the page table.
2480	*/
2481	PSHWPT pPTDst;
2482	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2483	const bool fPageTable = !PdeSrc.b.u1Size;
2484	# else
2485	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2486	# endif
2487	PPGMPOOLPAGE pShwPage;
2488	RTGCPHYS GCPhys;
2489	if (fPageTable)
2490	{
2491	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2492	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2493	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2494	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2495	# endif
2496	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2497	}
2498	else
2499	{
2500	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2501	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2502	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2503	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2504	# endif
2505	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2506	}
2507	if (rc == VINF_SUCCESS)
2508	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2509	else if (rc == VINF_PGM_CACHED_PAGE)
2510	{
2511	/*
2512	* The PT was cached, just hook it up.
2513	*/
2514	if (fPageTable)
2515	PdeDst.u = pShwPage->Core.Key
2516	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2517	else
2518	{
2519	PdeDst.u = pShwPage->Core.Key
2520	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2521	/* (see explanation and assumptions further down.) */
2522	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2523	{
2524	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2525	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2526	PdeDst.b.u1Write = 0;
2527	}
2528	}
2529	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2530	# if defined(IN_RC)
2531	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2532	# endif
2533	return VINF_SUCCESS;
2534	}
2535	else if (rc == VERR_PGM_POOL_FLUSHED)
2536	{
2537	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2538	# if defined(IN_RC)
2539	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2540	# endif
2541	return VINF_PGM_SYNC_CR3;
2542	}
2543	else
2544	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2545	PdeDst.u &= X86_PDE_AVL_MASK;
2546	PdeDst.u \|= pShwPage->Core.Key;
2547
2548	/*
2549	* Page directory has been accessed (this is a fault situation, remember).
2550	*/
2551	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2552	if (fPageTable)
2553	{
2554	/*
2555	* Page table - 4KB.
2556	*
2557	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2558	*/
2559	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2560	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2561	PGSTPT pPTSrc;
2562	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2563	if (RT_SUCCESS(rc))
2564	{
2565	/*
2566	* Start by syncing the page directory entry so CSAM's TLB trick works.
2567	*/
2568	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2569	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2570	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2571	# if defined(IN_RC)
2572	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2573	# endif
2574
2575	/*
2576	* Directory/page user or supervisor privilege: (same goes for read/write)
2577	*
2578	* Directory Page Combined
2579	* U/S U/S U/S
2580	* 0 0 0
2581	* 0 1 0
2582	* 1 0 0
2583	* 1 1 1
2584	*
2585	* Simple AND operation. Table listed for completeness.
2586	*
2587	*/
2588	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2589	# ifdef PGM_SYNC_N_PAGES
2590	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2591	unsigned iPTDst = iPTBase;
2592	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2593	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2594	iPTDst = 0;
2595	else
2596	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2597	# else /* !PGM_SYNC_N_PAGES */
2598	unsigned iPTDst = 0;
2599	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2600	# endif /* !PGM_SYNC_N_PAGES */
2601	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2602	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2603	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2604	# else
2605	const unsigned offPTSrc = 0;
2606	# endif
2607	for (; iPTDst < iPTDstEnd; iPTDst++)
2608	{
2609	const unsigned iPTSrc = iPTDst + offPTSrc;
2610	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2611
2612	if (PteSrc.n.u1Present) /* we've already cleared it above */
2613	{
2614	# ifndef IN_RING0
2615	/*
2616	* Assuming kernel code will be marked as supervisor - and not as user level
2617	* and executed using a conforming code selector - And marked as readonly.
2618	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2619	*/
2620	PPGMPAGE pPage;
2621	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2622	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2623	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2624	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2625	)
2626	# endif
2627	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2628	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2629	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2630	PteSrc.n.u1Present,
2631	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2632	PteSrc.n.u1User & PdeSrc.n.u1User,
2633	(uint64_t)PteSrc.u,
2634	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2635	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2636	}
2637	} /* for PTEs */
2638	}
2639	}
2640	else
2641	{
2642	/*
2643	* Big page - 2/4MB.
2644	*
2645	* We'll walk the ram range list in parallel and optimize lookups.
2646	* We will only sync on shadow page table at a time.
2647	*/
2648	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2649
2650	/**
2651	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2652	*/
2653
2654	/*
2655	* Start by syncing the page directory entry.
2656	*/
2657	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2658	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2659
2660	/*
2661	* If the page is not flagged as dirty and is writable, then make it read-only
2662	* at PD level, so we can set the dirty bit when the page is modified.
2663	*
2664	* ASSUMES that page access handlers are implemented on page table entry level.
2665	* Thus we will first catch the dirty access and set PDE.D and restart. If
2666	* there is an access handler, we'll trap again and let it work on the problem.
2667	*/
2668	/** @todo move the above stuff to a section in the PGM documentation. */
2669	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2670	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2671	{
2672	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2673	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2674	PdeDst.b.u1Write = 0;
2675	}
2676	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2677	# if defined(IN_RC)
2678	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2679	# endif
2680
2681	/*
2682	* Fill the shadow page table.
2683	*/
2684	/* Get address and flags from the source PDE. */
2685	SHWPTE PteDstBase;
2686	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2687
2688	/* Loop thru the entries in the shadow PT. */
2689	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2690	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2691	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2692	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2693	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2694	unsigned iPTDst = 0;
2695	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2696	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2697	{
2698	/* Advance ram range list. */
2699	while (pRam && GCPhys > pRam->GCPhysLast)
2700	pRam = pRam->CTX_SUFF(pNext);
2701	if (pRam && GCPhys >= pRam->GCPhys)
2702	{
2703	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2704	do
2705	{
2706	/* Make shadow PTE. */
2707	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2708	SHWPTE PteDst;
2709
2710	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2711	/* Try make the page writable if necessary. */
2712	if ( PteDstBase.n.u1Write
2713	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2714	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2715	{
2716	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2717	AssertRCReturn(rc, rc);
2718	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2719	break;
2720	}
2721	# endif
2722
2723	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2724	{
2725	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2726	{
2727	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2728	PteDst.n.u1Write = 0;
2729	}
2730	else
2731	PteDst.u = 0;
2732	}
2733	# ifndef IN_RING0
2734	/*
2735	* Assuming kernel code will be marked as supervisor and not as user level and executed
2736	* using a conforming code selector. Don't check for readonly, as that implies the whole
2737	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2738	*/
2739	else if ( !PdeSrc.n.u1User
2740	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2741	PteDst.u = 0;
2742	# endif
2743	else
2744	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2745
2746	/* Only map writable pages writable. */
2747	if ( PteDst.n.u1Write
2748	&& PteDst.n.u1Present
2749	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2750	{
2751	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2752	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2753	}
2754
2755	# ifdef PGMPOOL_WITH_USER_TRACKING
2756	if (PteDst.n.u1Present)
2757	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2758	# endif
2759	/* commit it */
2760	pPTDst->a[iPTDst] = PteDst;
2761	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2762	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2763	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2764
2765	/* advance */
2766	GCPhys += PAGE_SIZE;
2767	iHCPage++;
2768	iPTDst++;
2769	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2770	&& GCPhys <= pRam->GCPhysLast);
2771	}
2772	else if (pRam)
2773	{
2774	Log(("Invalid pages at %RGp\n", GCPhys));
2775	do
2776	{
2777	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2778	GCPhys += PAGE_SIZE;
2779	iPTDst++;
2780	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2781	&& GCPhys < pRam->GCPhys);
2782	}
2783	else
2784	{
2785	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2786	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2787	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2788	}
2789	} /* while more PTEs */
2790	} /* 4KB / 4MB */
2791	}
2792	else
2793	AssertRelease(!PdeDst.n.u1Present);
2794
2795	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2796	if (RT_FAILURE(rc))
2797	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2798	return rc;
2799
2800	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2801	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2802	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2803	&& !defined(IN_RC)
2804
2805	/*
2806	* Validate input a little bit.
2807	*/
2808	int rc = VINF_SUCCESS;
2809	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2810	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2811	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2812
2813	/* Fetch the pgm pool shadow descriptor. */
2814	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2815	Assert(pShwPde);
2816
2817	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2818	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2819	PPGMPOOLPAGE pShwPde;
2820	PX86PDPAE pPDDst;
2821	PSHWPDE pPdeDst;
2822
2823	/* Fetch the pgm pool shadow descriptor. */
2824	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2825	AssertRCSuccessReturn(rc, rc);
2826	Assert(pShwPde);
2827
2828	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2829	pPdeDst = &pPDDst->a[iPDDst];
2830
2831	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2832	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2833	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2834	PX86PDPAE pPDDst;
2835	PX86PDPT pPdptDst;
2836	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2837	AssertRCSuccessReturn(rc, rc);
2838	Assert(pPDDst);
2839	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2840
2841	/* Fetch the pgm pool shadow descriptor. */
2842	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2843	Assert(pShwPde);
2844
2845	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2846	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2847	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2848	PEPTPD pPDDst;
2849	PEPTPDPT pPdptDst;
2850
2851	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2852	if (rc != VINF_SUCCESS)
2853	{
2854	AssertRC(rc);
2855	return rc;
2856	}
2857	Assert(pPDDst);
2858	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2859
2860	/* Fetch the pgm pool shadow descriptor. */
2861	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2862	Assert(pShwPde);
2863	# endif
2864	SHWPDE PdeDst = *pPdeDst;
2865
2866	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2867	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2868
2869	GSTPDE PdeSrc;
2870	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2871	PdeSrc.n.u1Present = 1;
2872	PdeSrc.n.u1Write = 1;
2873	PdeSrc.n.u1Accessed = 1;
2874	PdeSrc.n.u1User = 1;
2875
2876	/*
2877	* Allocate & map the page table.
2878	*/
2879	PSHWPT pPTDst;
2880	PPGMPOOLPAGE pShwPage;
2881	RTGCPHYS GCPhys;
2882
2883	/* Virtual address = physical address */
2884	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2885	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2886
2887	if ( rc == VINF_SUCCESS
2888	\|\| rc == VINF_PGM_CACHED_PAGE)
2889	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2890	else
2891	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2892
2893	PdeDst.u &= X86_PDE_AVL_MASK;
2894	PdeDst.u \|= pShwPage->Core.Key;
2895	PdeDst.n.u1Present = 1;
2896	PdeDst.n.u1Write = 1;
2897	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2898	PdeDst.n.u1Execute = 1;
2899	# else
2900	PdeDst.n.u1User = 1;
2901	PdeDst.n.u1Accessed = 1;
2902	# endif
2903	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2904
2905	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2906	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2907	return rc;
2908
2909	#else
2910	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2911	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2912	return VERR_INTERNAL_ERROR;
2913	#endif
2914	}
2915
2916
2917
2918	/**
2919	* Prefetch a page/set of pages.
2920	*
2921	* Typically used to sync commonly used pages before entering raw mode
2922	* after a CR3 reload.
2923	*
2924	* @returns VBox status code.
2925	* @param pVCpu The VMCPU handle.
2926	* @param GCPtrPage Page to invalidate.
2927	*/
2928	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
2929	{
2930	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2931	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2932	/*
2933	* Check that all Guest levels thru the PDE are present, getting the
2934	* PD and PDE in the processes.
2935	*/
2936	int rc = VINF_SUCCESS;
2937	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2938	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2939	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2940	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2941	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2942	unsigned iPDSrc;
2943	X86PDPE PdpeSrc;
2944	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
2945	if (!pPDSrc)
2946	return VINF_SUCCESS; /* not present */
2947	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
2948	unsigned iPDSrc;
2949	PX86PML4E pPml4eSrc;
2950	X86PDPE PdpeSrc;
2951	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
2952	if (!pPDSrc)
2953	return VINF_SUCCESS; /* not present */
2954	# endif
2955	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2956	# else
2957	PGSTPD pPDSrc = NULL;
2958	const unsigned iPDSrc = 0;
2959	GSTPDE PdeSrc;
2960
2961	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2962	PdeSrc.n.u1Present = 1;
2963	PdeSrc.n.u1Write = 1;
2964	PdeSrc.n.u1Accessed = 1;
2965	PdeSrc.n.u1User = 1;
2966	# endif
2967
2968	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2969	{
2970	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2971	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
2972	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2973	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2974	PX86PDPAE pPDDst;
2975	X86PDEPAE PdeDst;
2976	# if PGM_GST_TYPE != PGM_TYPE_PAE
2977	X86PDPE PdpeSrc;
2978
2979	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
2980	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
2981	# endif
2982	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
2983	if (rc != VINF_SUCCESS)
2984	{
2985	AssertRC(rc);
2986	return rc;
2987	}
2988	Assert(pPDDst);
2989	PdeDst = pPDDst->a[iPDDst];
2990
2991	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2992	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2993	PX86PDPAE pPDDst;
2994	X86PDEPAE PdeDst;
2995
2996	# if PGM_GST_TYPE == PGM_TYPE_PROT
2997	/* AMD-V nested paging */
2998	X86PML4E Pml4eSrc;
2999	X86PDPE PdpeSrc;
3000	PX86PML4E pPml4eSrc = &Pml4eSrc;
3001
3002	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3003	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3004	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3005	# endif
3006
3007	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3008	if (rc != VINF_SUCCESS)
3009	{
3010	AssertRC(rc);
3011	return rc;
3012	}
3013	Assert(pPDDst);
3014	PdeDst = pPDDst->a[iPDDst];
3015	# endif
3016	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3017	{
3018	if (!PdeDst.n.u1Present)
3019	{
3020	PVM pVM = pVCpu->CTX_SUFF(pVM);
3021	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3022	pgmLock(pVM);
3023	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3024	pgmUnlock(pVM);
3025	}
3026	else
3027	{
3028	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3029	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3030	* makes no sense to prefetch more than one page.
3031	*/
3032	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3033	if (RT_SUCCESS(rc))
3034	rc = VINF_SUCCESS;
3035	}
3036	}
3037	}
3038	return rc;
3039
3040	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3041	return VINF_SUCCESS; /* ignore */
3042	#endif
3043	}
3044
3045
3046
3047
3048	/**
3049	* Syncs a page during a PGMVerifyAccess() call.
3050	*
3051	* @returns VBox status code (informational included).
3052	* @param pVCpu The VMCPU handle.
3053	* @param GCPtrPage The address of the page to sync.
3054	* @param fPage The effective guest page flags.
3055	* @param uErr The trap error code.
3056	*/
3057	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3058	{
3059	PVM pVM = pVCpu->CTX_SUFF(pVM);
3060
3061	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3062
3063	Assert(!HWACCMIsNestedPagingActive(pVM));
3064	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3065	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3066
3067	# ifndef IN_RING0
3068	if (!(fPage & X86_PTE_US))
3069	{
3070	/*
3071	* Mark this page as safe.
3072	*/
3073	/** @todo not correct for pages that contain both code and data!! */
3074	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3075	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3076	}
3077	# endif
3078
3079	/*
3080	* Get guest PD and index.
3081	*/
3082	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3083	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3084	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3085	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3086	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3087	unsigned iPDSrc = 0;
3088	X86PDPE PdpeSrc;
3089	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3090
3091	if (pPDSrc)
3092	{
3093	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3094	return VINF_EM_RAW_GUEST_TRAP;
3095	}
3096	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3097	unsigned iPDSrc;
3098	PX86PML4E pPml4eSrc;
3099	X86PDPE PdpeSrc;
3100	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3101	if (!pPDSrc)
3102	{
3103	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3104	return VINF_EM_RAW_GUEST_TRAP;
3105	}
3106	# endif
3107	# else
3108	PGSTPD pPDSrc = NULL;
3109	const unsigned iPDSrc = 0;
3110	# endif
3111	int rc = VINF_SUCCESS;
3112
3113	/*
3114	* First check if the shadow pd is present.
3115	*/
3116	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3117	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3118	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3119	PX86PDEPAE pPdeDst;
3120	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3121	PX86PDPAE pPDDst;
3122	# if PGM_GST_TYPE != PGM_TYPE_PAE
3123	X86PDPE PdpeSrc;
3124
3125	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3126	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3127	# endif
3128	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3129	if (rc != VINF_SUCCESS)
3130	{
3131	AssertRC(rc);
3132	return rc;
3133	}
3134	Assert(pPDDst);
3135	pPdeDst = &pPDDst->a[iPDDst];
3136
3137	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3138	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3139	PX86PDPAE pPDDst;
3140	PX86PDEPAE pPdeDst;
3141
3142	# if PGM_GST_TYPE == PGM_TYPE_PROT
3143	/* AMD-V nested paging */
3144	X86PML4E Pml4eSrc;
3145	X86PDPE PdpeSrc;
3146	PX86PML4E pPml4eSrc = &Pml4eSrc;
3147
3148	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3149	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3150	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3151	# endif
3152
3153	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3154	if (rc != VINF_SUCCESS)
3155	{
3156	AssertRC(rc);
3157	return rc;
3158	}
3159	Assert(pPDDst);
3160	pPdeDst = &pPDDst->a[iPDDst];
3161	# endif
3162
3163	# if defined(IN_RC)
3164	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3165	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3166	# endif
3167
3168	if (!pPdeDst->n.u1Present)
3169	{
3170	pgmLock(pVM);
3171	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3172	pgmUnlock(pVM);
3173	AssertRC(rc);
3174	if (rc != VINF_SUCCESS)
3175	{
3176	# if defined(IN_RC)
3177	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3178	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3179	# endif
3180	return rc;
3181	}
3182	}
3183
3184	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3185	/* Check for dirty bit fault */
3186	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3187	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3188	Log(("PGMVerifyAccess: success (dirty)\n"));
3189	else
3190	{
3191	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3192	#else
3193	{
3194	GSTPDE PdeSrc;
3195	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3196	PdeSrc.n.u1Present = 1;
3197	PdeSrc.n.u1Write = 1;
3198	PdeSrc.n.u1Accessed = 1;
3199	PdeSrc.n.u1User = 1;
3200
3201	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3202	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3203	if (uErr & X86_TRAP_PF_US)
3204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3205	else /* supervisor */
3206	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3207
3208	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3209	if (RT_SUCCESS(rc))
3210	{
3211	/* Page was successfully synced */
3212	Log2(("PGMVerifyAccess: success (sync)\n"));
3213	rc = VINF_SUCCESS;
3214	}
3215	else
3216	{
3217	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3218	rc = VINF_EM_RAW_GUEST_TRAP;
3219	}
3220	}
3221	# if defined(IN_RC)
3222	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3223	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3224	# endif
3225	return rc;
3226
3227	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3228
3229	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3230	return VERR_INTERNAL_ERROR;
3231	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3232	}
3233
3234
3235	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3236	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3237	/**
3238	* Figures out which kind of shadow page this guest PDE warrants.
3239	*
3240	* @returns Shadow page kind.
3241	* @param pPdeSrc The guest PDE in question.
3242	* @param cr4 The current guest cr4 value.
3243	*/
3244	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3245	{
3246	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3247	if (!pPdeSrc->n.u1Size)
3248	# else
3249	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3250	# endif
3251	return BTH_PGMPOOLKIND_PT_FOR_PT;
3252	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3253	//{
3254	// case 0:
3255	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3256	// case X86_PDE4M_RW:
3257	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3258	// case X86_PDE4M_US:
3259	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3260	// case X86_PDE4M_RW \| X86_PDE4M_US:
3261	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3262	# if 0
3263	// case X86_PDE4M_PAE_NX:
3264	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3265	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3266	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3267	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3268	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3269	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3270	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3271	# endif
3272	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3273	//}
3274	}
3275	# endif
3276	#endif
3277
3278	#undef MY_STAM_COUNTER_INC
3279	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3280
3281
3282	/**
3283	* Syncs the paging hierarchy starting at CR3.
3284	*
3285	* @returns VBox status code, no specials.
3286	* @param pVCpu The VMCPU handle.
3287	* @param cr0 Guest context CR0 register
3288	* @param cr3 Guest context CR3 register
3289	* @param cr4 Guest context CR4 register
3290	* @param fGlobal Including global page directories or not
3291	*/
3292	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3293	{
3294	PVM pVM = pVCpu->CTX_SUFF(pVM);
3295
3296	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3297	fGlobal = true; /* Change this CR3 reload to be a global one. */
3298
3299	LogFlow(("SyncCR3 %d\n", fGlobal));
3300
3301	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3302	/*
3303	* Update page access handlers.
3304	* The virtual are always flushed, while the physical are only on demand.
3305	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3306	* have to look into that later because it will have a bad influence on the performance.
3307	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3308	* bird: Yes, but that won't work for aliases.
3309	*/
3310	/** @todo this MUST go away. See #1557. */
3311	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3312	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3313	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3314	#endif
3315
3316	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3317	/*
3318	* Nested / EPT - almost no work.
3319	*/
3320	/** @todo check if this is really necessary; the call does it as well... */
3321	HWACCMFlushTLB(pVM);
3322	return VINF_SUCCESS;
3323
3324	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3325	/*
3326	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3327	* out the shadow parts when the guest modifies its tables.
3328	*/
3329	return VINF_SUCCESS;
3330
3331	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3332
3333	# ifdef PGM_WITHOUT_MAPPINGS
3334	Assert(pVM->pgm.s.fMappingsFixed);
3335	return VINF_SUCCESS;
3336	# else
3337	/* Nothing to do when mappings are fixed. */
3338	if (pVM->pgm.s.fMappingsFixed)
3339	return VINF_SUCCESS;
3340
3341	int rc = PGMMapResolveConflicts(pVM);
3342	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3343	if (rc == VINF_PGM_SYNC_CR3)
3344	{
3345	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3346	return VINF_PGM_SYNC_CR3;
3347	}
3348	# endif
3349	return VINF_SUCCESS;
3350	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3351	}
3352
3353
3354
3355
3356	#ifdef VBOX_STRICT
3357	#ifdef IN_RC
3358	# undef AssertMsgFailed
3359	# define AssertMsgFailed Log
3360	#endif
3361	#ifdef IN_RING3
3362	# include <VBox/dbgf.h>
3363
3364	/**
3365	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3366	*
3367	* @returns VBox status code (VINF_SUCCESS).
3368	* @param cr3 The root of the hierarchy.
3369	* @param crr The cr4, only PAE and PSE is currently used.
3370	* @param fLongMode Set if long mode, false if not long mode.
3371	* @param cMaxDepth Number of levels to dump.
3372	* @param pHlp Pointer to the output functions.
3373	*/
3374	__BEGIN_DECLS
3375	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3376	__END_DECLS
3377
3378	#endif
3379
3380	/**
3381	* Checks that the shadow page table is in sync with the guest one.
3382	*
3383	* @returns The number of errors.
3384	* @param pVM The virtual machine.
3385	* @param pVCpu The VMCPU handle.
3386	* @param cr3 Guest context CR3 register
3387	* @param cr4 Guest context CR4 register
3388	* @param GCPtr Where to start. Defaults to 0.
3389	* @param cb How much to check. Defaults to everything.
3390	*/
3391	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3392	{
3393	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3394	return 0;
3395	#else
3396	unsigned cErrors = 0;
3397	PVM pVM = pVCpu->CTX_SUFF(pVM);
3398	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3399
3400	#if PGM_GST_TYPE == PGM_TYPE_PAE
3401	/** @todo currently broken; crashes below somewhere */
3402	AssertFailed();
3403	#endif
3404
3405	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3406	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3407	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3408
3409	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3410	bool fBigPagesSupported = true;
3411	# else
3412	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3413	# endif
3414	PPGMCPU pPGM = &pVCpu->pgm.s;
3415	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3416	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3417	# ifndef IN_RING0
3418	RTHCPHYS HCPhys; /* general usage. */
3419	# endif
3420	int rc;
3421
3422	/*
3423	* Check that the Guest CR3 and all its mappings are correct.
3424	*/
3425	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3426	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3427	false);
3428	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3429	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3430	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3431	# else
3432	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3433	# endif
3434	AssertRCReturn(rc, 1);
3435	HCPhys = NIL_RTHCPHYS;
3436	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3437	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3438	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3439	pgmGstGet32bitPDPtr(pPGM);
3440	RTGCPHYS GCPhys;
3441	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3442	AssertRCReturn(rc, 1);
3443	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3444	# endif
3445	# endif /* !IN_RING0 */
3446
3447	/*
3448	* Get and check the Shadow CR3.
3449	*/
3450	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3451	unsigned cPDEs = X86_PG_ENTRIES;
3452	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3453	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3454	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3455	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3456	# else
3457	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3458	# endif
3459	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3460	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3461	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3462	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3463	# endif
3464	if (cb != ~(RTGCPTR)0)
3465	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3466
3467	/** @todo call the other two PGMAssert() functions. /
3468
3469	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3470	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3471
3472	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3473	{
3474	PPGMPOOLPAGE pShwPdpt = NULL;
3475	PX86PML4E pPml4eSrc;
3476	PX86PML4E pPml4eDst;
3477	RTGCPHYS GCPhysPdptSrc;
3478
3479	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3480	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3481
3482	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3483	if (!pPml4eDst->n.u1Present)
3484	{
3485	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3486	continue;
3487	}
3488
3489	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3490	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3491
3492	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3493	{
3494	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3495	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3496	cErrors++;
3497	continue;
3498	}
3499
3500	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3501	{
3502	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3503	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3504	cErrors++;
3505	continue;
3506	}
3507
3508	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3509	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3510	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3511	{
3512	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3513	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3514	cErrors++;
3515	continue;
3516	}
3517	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3518	{
3519	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3520
3521	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3522	/*
3523	* Check the PDPTEs too.
3524	*/
3525	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3526
3527	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3528	{
3529	unsigned iPDSrc;
3530	PPGMPOOLPAGE pShwPde = NULL;
3531	PX86PDPE pPdpeDst;
3532	RTGCPHYS GCPhysPdeSrc;
3533	# if PGM_GST_TYPE == PGM_TYPE_PAE
3534	X86PDPE PdpeSrc;
3535	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3536	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3537	# else
3538	PX86PML4E pPml4eSrc;
3539	X86PDPE PdpeSrc;
3540	PX86PDPT pPdptDst;
3541	PX86PDPAE pPDDst;
3542	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3543
3544	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3545	if (rc != VINF_SUCCESS)
3546	{
3547	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3548	GCPtr += 512 * _2M;
3549	continue; /* next PDPTE */
3550	}
3551	Assert(pPDDst);
3552	# endif
3553	Assert(iPDSrc == 0);
3554
3555	pPdpeDst = &pPdptDst->a[iPdpt];
3556
3557	if (!pPdpeDst->n.u1Present)
3558	{
3559	GCPtr += 512 * _2M;
3560	continue; /* next PDPTE */
3561	}
3562
3563	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3564	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3565
3566	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3567	{
3568	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3569	GCPtr += 512 * _2M;
3570	cErrors++;
3571	continue;
3572	}
3573
3574	if (GCPhysPdeSrc != pShwPde->GCPhys)
3575	{
3576	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3577	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3578	# else
3579	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3580	# endif
3581	GCPtr += 512 * _2M;
3582	cErrors++;
3583	continue;
3584	}
3585
3586	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3587	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3588	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3589	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3590	{
3591	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3592	GCPtr += 512 * _2M;
3593	cErrors++;
3594	continue;
3595	}
3596	# endif
3597
3598	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3599	{
3600	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3601	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3602	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3603	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3604	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3605	# endif
3606	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3607	/*
3608	* Iterate the shadow page directory.
3609	*/
3610	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3611	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3612
3613	for (;
3614	iPDDst < cPDEs;
3615	iPDDst++, GCPtr += cIncrement)
3616	{
3617	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3618	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3619	# else
3620	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3621	# endif
3622	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3623	{
3624	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3625	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3626	{
3627	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3628	cErrors++;
3629	continue;
3630	}
3631	}
3632	else if ( (PdeDst.u & X86_PDE_P)
3633	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3634	)
3635	{
3636	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3637	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3638	if (!pPoolPage)
3639	{
3640	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3641	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3642	cErrors++;
3643	continue;
3644	}
3645	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3646
3647	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3648	{
3649	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3650	GCPtr, (uint64_t)PdeDst.u));
3651	cErrors++;
3652	}
3653
3654	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3655	{
3656	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3657	GCPtr, (uint64_t)PdeDst.u));
3658	cErrors++;
3659	}
3660
3661	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3662	if (!PdeSrc.n.u1Present)
3663	{
3664	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3665	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3666	cErrors++;
3667	continue;
3668	}
3669
3670	if ( !PdeSrc.b.u1Size
3671	\|\| !fBigPagesSupported)
3672	{
3673	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3674	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3675	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3676	# endif
3677	}
3678	else
3679	{
3680	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3681	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3682	{
3683	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3684	GCPtr, (uint64_t)PdeSrc.u));
3685	cErrors++;
3686	continue;
3687	}
3688	# endif
3689	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3690	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3691	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3692	# endif
3693	}
3694
3695	if ( pPoolPage->enmKind
3696	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3697	{
3698	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3699	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3700	cErrors++;
3701	}
3702
3703	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3704	if (!pPhysPage)
3705	{
3706	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3707	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3708	cErrors++;
3709	continue;
3710	}
3711
3712	if (GCPhysGst != pPoolPage->GCPhys)
3713	{
3714	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3715	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3716	cErrors++;
3717	continue;
3718	}
3719
3720	if ( !PdeSrc.b.u1Size
3721	\|\| !fBigPagesSupported)
3722	{
3723	/*
3724	* Page Table.
3725	*/
3726	const GSTPT *pPTSrc;
3727	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3728	if (RT_FAILURE(rc))
3729	{
3730	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3731	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3732	cErrors++;
3733	continue;
3734	}
3735	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3736	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3737	{
3738	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3739	// (This problem will go away when/if we shadow multiple CR3s.)
3740	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3741	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3742	cErrors++;
3743	continue;
3744	}
3745	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3746	{
3747	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3748	GCPtr, (uint64_t)PdeDst.u));
3749	cErrors++;
3750	continue;
3751	}
3752
3753	/* iterate the page table. */
3754	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3755	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3756	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3757	# else
3758	const unsigned offPTSrc = 0;
3759	# endif
3760	for (unsigned iPT = 0, off = 0;
3761	iPT < RT_ELEMENTS(pPTDst->a);
3762	iPT++, off += PAGE_SIZE)
3763	{
3764	const SHWPTE PteDst = pPTDst->a[iPT];
3765
3766	/* skip not-present entries. */
3767	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3768	continue;
3769	Assert(PteDst.n.u1Present);
3770
3771	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3772	if (!PteSrc.n.u1Present)
3773	{
3774	# ifdef IN_RING3
3775	PGMAssertHandlerAndFlagsInSync(pVM);
3776	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3777	# endif
3778	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3779	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3780	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3781	cErrors++;
3782	continue;
3783	}
3784
3785	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3786	# if 1 /** @todo sync accessed bit properly... */
3787	fIgnoreFlags \|= X86_PTE_A;
3788	# endif
3789
3790	/* match the physical addresses */
3791	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3792	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3793
3794	# ifdef IN_RING3
3795	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3796	if (RT_FAILURE(rc))
3797	{
3798	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3799	{
3800	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3801	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3802	cErrors++;
3803	continue;
3804	}
3805	}
3806	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3807	{
3808	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3809	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3810	cErrors++;
3811	continue;
3812	}
3813	# endif
3814
3815	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3816	if (!pPhysPage)
3817	{
3818	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3819	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3820	{
3821	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3822	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3823	cErrors++;
3824	continue;
3825	}
3826	# endif
3827	if (PteDst.n.u1Write)
3828	{
3829	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3830	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3831	cErrors++;
3832	}
3833	fIgnoreFlags \|= X86_PTE_RW;
3834	}
3835	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3836	{
3837	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3838	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3839	cErrors++;
3840	continue;
3841	}
3842
3843	/* flags */
3844	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3845	{
3846	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3847	{
3848	if (PteDst.n.u1Write)
3849	{
3850	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3851	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3852	cErrors++;
3853	continue;
3854	}
3855	fIgnoreFlags \|= X86_PTE_RW;
3856	}
3857	else
3858	{
3859	if (PteDst.n.u1Present)
3860	{
3861	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3862	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3863	cErrors++;
3864	continue;
3865	}
3866	fIgnoreFlags \|= X86_PTE_P;
3867	}
3868	}
3869	else
3870	{
3871	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3872	{
3873	if (PteDst.n.u1Write)
3874	{
3875	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3876	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3877	cErrors++;
3878	continue;
3879	}
3880	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3881	{
3882	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3883	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3884	cErrors++;
3885	continue;
3886	}
3887	if (PteDst.n.u1Dirty)
3888	{
3889	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3890	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3891	cErrors++;
3892	}
3893	# if 0 /** @todo sync access bit properly... */
3894	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3895	{
3896	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3897	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3898	cErrors++;
3899	}
3900	fIgnoreFlags \|= X86_PTE_RW;
3901	# else
3902	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3903	# endif
3904	}
3905	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3906	{
3907	/* access bit emulation (not implemented). */
3908	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3909	{
3910	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3911	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3912	cErrors++;
3913	continue;
3914	}
3915	if (!PteDst.n.u1Accessed)
3916	{
3917	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3918	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3919	cErrors++;
3920	}
3921	fIgnoreFlags \|= X86_PTE_P;
3922	}
3923	# ifdef DEBUG_sandervl
3924	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3925	# endif
3926	}
3927
3928	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3929	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3930	)
3931	{
3932	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3933	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3934	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3935	cErrors++;
3936	continue;
3937	}
3938	} /* foreach PTE */
3939	}
3940	else
3941	{
3942	/*
3943	* Big Page.
3944	*/
3945	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3946	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3947	{
3948	if (PdeDst.n.u1Write)
3949	{
3950	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3951	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3952	cErrors++;
3953	continue;
3954	}
3955	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3956	{
3957	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3958	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3959	cErrors++;
3960	continue;
3961	}
3962	# if 0 /** @todo sync access bit properly... */
3963	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3964	{
3965	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3966	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3967	cErrors++;
3968	}
3969	fIgnoreFlags \|= X86_PTE_RW;
3970	# else
3971	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3972	# endif
3973	}
3974	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3975	{
3976	/* access bit emulation (not implemented). */
3977	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3978	{
3979	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3980	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3981	cErrors++;
3982	continue;
3983	}
3984	if (!PdeDst.n.u1Accessed)
3985	{
3986	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3987	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3988	cErrors++;
3989	}
3990	fIgnoreFlags \|= X86_PTE_P;
3991	}
3992
3993	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3994	{
3995	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3996	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3997	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3998	cErrors++;
3999	}
4000
4001	/* iterate the page table. */
4002	for (unsigned iPT = 0, off = 0;
4003	iPT < RT_ELEMENTS(pPTDst->a);
4004	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4005	{
4006	const SHWPTE PteDst = pPTDst->a[iPT];
4007
4008	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4009	{
4010	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4011	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4012	cErrors++;
4013	}
4014
4015	/* skip not-present entries. */
4016	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4017	continue;
4018
4019	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4020
4021	/* match the physical addresses */
4022	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4023
4024	# ifdef IN_RING3
4025	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4026	if (RT_FAILURE(rc))
4027	{
4028	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4029	{
4030	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4031	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4032	cErrors++;
4033	}
4034	}
4035	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4036	{
4037	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4038	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4039	cErrors++;
4040	continue;
4041	}
4042	# endif
4043	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4044	if (!pPhysPage)
4045	{
4046	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4047	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4048	{
4049	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4050	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4051	cErrors++;
4052	continue;
4053	}
4054	# endif
4055	if (PteDst.n.u1Write)
4056	{
4057	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4058	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4059	cErrors++;
4060	}
4061	fIgnoreFlags \|= X86_PTE_RW;
4062	}
4063	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4064	{
4065	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4066	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4067	cErrors++;
4068	continue;
4069	}
4070
4071	/* flags */
4072	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4073	{
4074	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4075	{
4076	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4077	{
4078	if (PteDst.n.u1Write)
4079	{
4080	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4081	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4082	cErrors++;
4083	continue;
4084	}
4085	fIgnoreFlags \|= X86_PTE_RW;
4086	}
4087	}
4088	else
4089	{
4090	if (PteDst.n.u1Present)
4091	{
4092	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4093	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4094	cErrors++;
4095	continue;
4096	}
4097	fIgnoreFlags \|= X86_PTE_P;
4098	}
4099	}
4100
4101	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4102	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4103	)
4104	{
4105	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4106	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4107	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4108	cErrors++;
4109	continue;
4110	}
4111	} /* for each PTE */
4112	}
4113	}
4114	/* not present */
4115
4116	} /* for each PDE */
4117
4118	} /* for each PDPTE */
4119
4120	} /* for each PML4E */
4121
4122	# ifdef DEBUG
4123	if (cErrors)
4124	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4125	# endif
4126
4127	#endif /* GST == 32BIT, PAE or AMD64 */
4128	return cErrors;
4129
4130	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4131	}
4132	#endif /* VBOX_STRICT */
4133
4134
4135	/**
4136	* Sets up the CR3 for shadow paging
4137	*
4138	* @returns Strict VBox status code.
4139	* @retval VINF_SUCCESS.
4140	*
4141	* @param pVCpu The VMCPU handle.
4142	* @param GCPhysCR3 The physical address in the CR3 register.
4143	*/
4144	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4145	{
4146	PVM pVM = pVCpu->CTX_SUFF(pVM);
4147
4148	/* Update guest paging info. */
4149	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4150	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4151	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4152
4153	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4154
4155	/*
4156	* Map the page CR3 points at.
4157	*/
4158	RTHCPTR HCPtrGuestCR3;
4159	RTHCPHYS HCPhysGuestCR3;
4160	pgmLock(pVM);
4161	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4162	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4163	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4164	/** @todo this needs some reworking wrt. locking. */
4165	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4166	HCPtrGuestCR3 = NIL_RTHCPTR;
4167	int rc = VINF_SUCCESS;
4168	# else
4169	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4170	# endif
4171	pgmUnlock(pVM);
4172	if (RT_SUCCESS(rc))
4173	{
4174	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4175	if (RT_SUCCESS(rc))
4176	{
4177	# ifdef IN_RC
4178	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4179	# endif
4180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4181	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4182	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4183	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4184	# endif
4185	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4186
4187	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4188	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4189	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4190	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4191	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4192	# endif
4193	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4194	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4195
4196	/*
4197	* Map the 4 PDs too.
4198	*/
4199	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4200	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4201	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4202	{
4203	if (pGuestPDPT->a[i].n.u1Present)
4204	{
4205	RTHCPTR HCPtr;
4206	RTHCPHYS HCPhys;
4207	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4208	pgmLock(pVM);
4209	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4210	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4211	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4212	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4213	HCPtr = NIL_RTHCPTR;
4214	int rc2 = VINF_SUCCESS;
4215	# else
4216	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4217	# endif
4218	pgmUnlock(pVM);
4219	if (RT_SUCCESS(rc2))
4220	{
4221	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4222	AssertRCReturn(rc, rc);
4223
4224	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4225	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4226	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4227	# endif
4228	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4229	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4230	PGM_INVL_PG(GCPtr); /** @todo This ends up calling HWACCMInvalidatePage, is that correct? */
4231	continue;
4232	}
4233	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4234	}
4235
4236	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4237	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4238	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4239	# endif
4240	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4241	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4242	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4243	}
4244
4245	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4246	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4247	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4248	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4249	# endif
4250	# endif
4251	}
4252	else
4253	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4254	}
4255	else
4256	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4257
4258	#else /* prot/real stub */
4259	int rc = VINF_SUCCESS;
4260	#endif
4261
4262	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4263	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4264	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4265	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4266	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4267	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4268
4269	Assert(!HWACCMIsNestedPagingActive(pVM));
4270
4271	/*
4272	* Update the shadow root page as well since that's not fixed.
4273	*/
4274	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4275	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4276	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4277	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4278	PPGMPOOLPAGE pNewShwPageCR3;
4279
4280	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4281	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4282	AssertFatalRC(rc);
4283	rc = VINF_SUCCESS;
4284
4285	/* Mark the page as locked; disallow flushing. */
4286	pgmPoolLockPage(pPool, pNewShwPageCR3);
4287
4288	# ifdef IN_RC
4289	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4290	bool fLog = VMMGCLogDisable(pVM);
4291	pgmLock(pVM);
4292	# endif
4293
4294	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4295	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4296	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4297	# ifdef IN_RING0
4298	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4299	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4300	# elif defined(IN_RC)
4301	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4302	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4303	# else
4304	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4305	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4306	# endif
4307
4308	# ifndef PGM_WITHOUT_MAPPINGS
4309	/*
4310	* Apply all hypervisor mappings to the new CR3.
4311	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4312	* make sure we check for conflicts in the new CR3 root.
4313	*/
4314	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4315	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4316	# endif
4317	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4318	AssertRCReturn(rc, rc);
4319	# endif
4320
4321	/* Set the current hypervisor CR3. */
4322	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4323	SELMShadowCR3Changed(pVM, pVCpu);
4324
4325	# ifdef IN_RC
4326	pgmUnlock(pVM);
4327	VMMGCLogRestore(pVM, fLog);
4328	# endif
4329
4330	/* Clean up the old CR3 root. */
4331	if (pOldShwPageCR3)
4332	{
4333	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4334	# ifndef PGM_WITHOUT_MAPPINGS
4335	/* Remove the hypervisor mappings from the shadow page table. */
4336	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4337	# endif
4338	/* Mark the page as unlocked; allow flushing again. */
4339	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4340
4341	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4342	}
4343
4344	# endif
4345
4346	return rc;
4347	}
4348
4349	/**
4350	* Unmaps the shadow CR3.
4351	*
4352	* @returns VBox status, no specials.
4353	* @param pVCpu The VMCPU handle.
4354	*/
4355	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4356	{
4357	LogFlow(("UnmapCR3\n"));
4358
4359	int rc = VINF_SUCCESS;
4360	PVM pVM = pVCpu->CTX_SUFF(pVM);
4361
4362	/*
4363	* Update guest paging info.
4364	*/
4365	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4366	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4367	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4368	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4369	# endif
4370	pVCpu->pgm.s.pGst32BitPdRC = 0;
4371
4372	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4373	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4374	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4375	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4376	# endif
4377	pVCpu->pgm.s.pGstPaePdptRC = 0;
4378	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4379	{
4380	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4381	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4382	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4383	# endif
4384	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4385	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4386	}
4387
4388	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4389	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4390	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4391	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4392	# endif
4393
4394	#else /* prot/real mode stub */
4395	/* nothing to do */
4396	#endif
4397
4398	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4399	/*
4400	* Update shadow paging info.
4401	*/
4402	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4403	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4404	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4405
4406	# if PGM_GST_TYPE != PGM_TYPE_REAL
4407	Assert(!HWACCMIsNestedPagingActive(pVM));
4408	# endif
4409
4410	# ifndef PGM_WITHOUT_MAPPINGS
4411	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4412	/* Remove the hypervisor mappings from the shadow page table. */
4413	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4414	# endif
4415
4416	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4417	{
4418	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4419
4420	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4421
4422	/* Mark the page as unlocked; allow flushing again. */
4423	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4424
4425	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4426	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4427	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4428	pVCpu->pgm.s.pShwPageCR3RC = 0;
4429	pVCpu->pgm.s.iShwUser = 0;
4430	pVCpu->pgm.s.iShwUserTable = 0;
4431	}
4432	# endif
4433	#endif /* !IN_RC*/
4434
4435	return rc;
4436	}
4437

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 19775

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