VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 19789

Last change on this file since 19789 was 19789, checked in by vboxsync, 16 years ago

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1/* $Id: PGMAllBth.h 19789 2009-05-18 14:04:07Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4 *
5 * This file is a big challenge!
6 */
7
8/*
9 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20 * Clara, CA 95054 USA or visit http://www.sun.com if you need
21 * additional information or have any questions.
22 */
23
24/*******************************************************************************
25* Internal Functions *
26*******************************************************************************/
27__BEGIN_DECLS
28PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36#ifdef VBOX_STRICT
37PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38#endif
39#ifdef PGMPOOL_WITH_USER_TRACKING
40DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41#endif
42PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44__END_DECLS
45
46
47/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49# error "Invalid combination; PAE guest implies PAE shadow"
50#endif
51
52#if (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
53 && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
54# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55#endif
56
57#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE) \
58 && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT)
59# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60#endif
61
62#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63 || (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65#endif
66
67#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68# define PGM_WITHOUT_MAPPINGS
69#endif
70
71
72#ifndef IN_RING3
73/**
74 * #PF Handler for raw-mode guest execution.
75 *
76 * @returns VBox status code (appropriate for trap handling and GC return).
77 *
78 * @param pVCpu VMCPU Handle.
79 * @param uErr The trap error code.
80 * @param pRegFrame Trap register frame.
81 * @param pvFault The fault address.
82 */
83PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84{
85 PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87# if defined(IN_RC) && defined(VBOX_STRICT)
88 PGMDynCheckLocks(pVM);
89# endif
90
91# if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64) \
92 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
93 && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT)
94
95# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96 /*
97 * Hide the instruction fetch trap indicator for now.
98 */
99 /** @todo NXE will change this and we must fix NXE in the switcher too! */
100 if (uErr & X86_TRAP_PF_ID)
101 {
102 uErr &= ~X86_TRAP_PF_ID;
103 TRPMSetErrorCode(pVCpu, uErr);
104 }
105# endif
106
107 /*
108 * Get PDs.
109 */
110 int rc;
111# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112# if PGM_GST_TYPE == PGM_TYPE_32BIT
113 const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116# elif PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
117
118# if PGM_GST_TYPE == PGM_TYPE_PAE
119 unsigned iPDSrc;
120 X86PDPE PdpeSrc;
121 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124 unsigned iPDSrc;
125 PX86PML4E pPml4eSrc;
126 X86PDPE PdpeSrc;
127 PGSTPD pPDSrc;
128
129 pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130 Assert(pPml4eSrc);
131# endif
132
133 /* Quick check for a valid guest trap. (PAE & AMD64) */
134 if (!pPDSrc)
135 {
136# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137 LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138# else
139 LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140# endif
141 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142 TRPMSetErrorCode(pVCpu, uErr);
143 return VINF_EM_RAW_GUEST_TRAP;
144 }
145# endif
146
147# else /* !PGM_WITH_PAGING */
148 PGSTPD pPDSrc = NULL;
149 const unsigned iPDSrc = 0;
150# endif /* !PGM_WITH_PAGING */
151
152 /* Fetch the guest PDE */
153# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155# else
156 GSTPDE PdeSrc;
157 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158 PdeSrc.n.u1Present = 1;
159 PdeSrc.n.u1Write = 1;
160 PdeSrc.n.u1Accessed = 1;
161 PdeSrc.n.u1User = 1;
162# endif
163
164 pgmLock(pVM);
165 { /* Force the shadow pointers to go out of scope after releasing the lock. */
166# if PGM_SHW_TYPE == PGM_TYPE_32BIT
167 const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
168 PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
169
170# elif PGM_SHW_TYPE == PGM_TYPE_PAE
171 const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
172
173 PX86PDPAE pPDDst;
174# if PGM_GST_TYPE != PGM_TYPE_PAE
175 X86PDPE PdpeSrc;
176
177 /* Fake PDPT entry; access control handled on the page table level, so allow everything. */
178 PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
179# endif
180 rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
181 if (rc != VINF_SUCCESS)
182 {
183 pgmUnlock(pVM);
184 AssertRC(rc);
185 return rc;
186 }
187 Assert(pPDDst);
188
189# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
190 const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
191 PX86PDPAE pPDDst;
192# if PGM_GST_TYPE == PGM_TYPE_PROT
193 /* AMD-V nested paging */
194 X86PML4E Pml4eSrc;
195 X86PDPE PdpeSrc;
196 PX86PML4E pPml4eSrc = &Pml4eSrc;
197
198 /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
199 Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A;
200 PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A;
201# endif
202
203 rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
204 if (rc != VINF_SUCCESS)
205 {
206 pgmUnlock(pVM);
207 AssertRC(rc);
208 return rc;
209 }
210 Assert(pPDDst);
211
212# elif PGM_SHW_TYPE == PGM_TYPE_EPT
213 const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
214 PEPTPD pPDDst;
215
216 rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
217 if (rc != VINF_SUCCESS)
218 {
219 pgmUnlock(pVM);
220 AssertRC(rc);
221 return rc;
222 }
223 Assert(pPDDst);
224# endif
225
226# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
227 /*
228 * If we successfully correct the write protection fault due to dirty bit
229 * tracking, or this page fault is a genuine one, then return immediately.
230 */
231 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
232 rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
233 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
234 if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
235 || rc == VINF_EM_RAW_GUEST_TRAP)
236 {
237 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
238 = rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
239 LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
240 pgmUnlock(pVM);
241 return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
242 }
243
244 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
245# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
246
247 /*
248 * A common case is the not-present error caused by lazy page table syncing.
249 *
250 * It is IMPORTANT that we weed out any access to non-present shadow PDEs here
251 * so we can safely assume that the shadow PT is present when calling SyncPage later.
252 *
253 * On failure, we ASSUME that SyncPT is out of memory or detected some kind
254 * of mapping conflict and defer to SyncCR3 in R3.
255 * (Again, we do NOT support access handlers for non-present guest pages.)
256 *
257 */
258 if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
259 && !pPDDst->a[iPDDst].n.u1Present
260 && PdeSrc.n.u1Present
261 )
262 {
263 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
264 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
265 LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
266 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
267 pgmUnlock(pVM);
268 if (RT_SUCCESS(rc))
269 {
270 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271 return rc;
272 }
273 Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
274 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
275 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
276 return VINF_PGM_SYNC_CR3;
277 }
278 pgmUnlock(pVM);
279 }
280
281# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
282 /*
283 * Check if this address is within any of our mappings.
284 *
285 * This is *very* fast and it's gonna save us a bit of effort below and prevent
286 * us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
287 * (BTW, it's impossible to have physical access handlers in a mapping.)
288 */
289 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
290 {
291 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
292 PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
293 for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
294 {
295 if (pvFault < pMapping->GCPtr)
296 break;
297 if (pvFault - pMapping->GCPtr < pMapping->cb)
298 {
299 /*
300 * The first thing we check is if we've got an undetected conflict.
301 */
302 if (!pVM->pgm.s.fMappingsFixed)
303 {
304 unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
305 while (iPT-- > 0)
306 if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
307 {
308 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
309 Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
310 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
311 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
312 return VINF_PGM_SYNC_CR3;
313 }
314 }
315
316 /*
317 * Check if the fault address is in a virtual page access handler range.
318 */
319 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
320 if ( pCur
321 && pvFault - pCur->Core.Key < pCur->cb
322 && uErr & X86_TRAP_PF_RW)
323 {
324# ifdef IN_RC
325 STAM_PROFILE_START(&pCur->Stat, h);
326 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
327 STAM_PROFILE_STOP(&pCur->Stat, h);
328# else
329 AssertFailed();
330 rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
331# endif
332 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
333 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
334 return rc;
335 }
336
337 /*
338 * Pretend we're not here and let the guest handle the trap.
339 */
340 TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
341 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
342 LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
343 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
344 return VINF_EM_RAW_GUEST_TRAP;
345 }
346 }
347 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
348 } /* pgmAreMappingsEnabled(&pVM->pgm.s) */
349# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
350
351 /*
352 * Check if this fault address is flagged for special treatment,
353 * which means we'll have to figure out the physical address and
354 * check flags associated with it.
355 *
356 * ASSUME that we can limit any special access handling to pages
357 * in page tables which the guest believes to be present.
358 */
359 if (PdeSrc.n.u1Present)
360 {
361 RTGCPHYS GCPhys = NIL_RTGCPHYS;
362
363# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
364# if PGM_GST_TYPE == PGM_TYPE_AMD64
365 bool fBigPagesSupported = true;
366# else
367 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
368# endif
369 if ( PdeSrc.b.u1Size
370 && fBigPagesSupported)
371 GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
372 | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
373 else
374 {
375 PGSTPT pPTSrc;
376 rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
377 if (RT_SUCCESS(rc))
378 {
379 unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
380 if (pPTSrc->a[iPTESrc].n.u1Present)
381 GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
382 }
383 }
384# else
385 /* No paging so the fault address is the physical address */
386 GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
387# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
388
389 /*
390 * If we have a GC address we'll check if it has any flags set.
391 */
392 if (GCPhys != NIL_RTGCPHYS)
393 {
394 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
395
396 PPGMPAGE pPage;
397 rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
398 if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
399 {
400 if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
401 || PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
402 {
403 if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
404 {
405 /*
406 * Physical page access handler.
407 */
408 const RTGCPHYS GCPhysFault = GCPhys | (pvFault & PAGE_OFFSET_MASK);
409 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
410 if (pCur)
411 {
412# ifdef PGM_SYNC_N_PAGES
413 /*
414 * If the region is write protected and we got a page not present fault, then sync
415 * the pages. If the fault was caused by a read, then restart the instruction.
416 * In case of write access continue to the GC write handler.
417 *
418 * ASSUMES that there is only one handler per page or that they have similar write properties.
419 */
420 if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
421 && !(uErr & X86_TRAP_PF_P))
422 {
423 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
424 if ( RT_FAILURE(rc)
425 || !(uErr & X86_TRAP_PF_RW)
426 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
427 {
428 AssertRC(rc);
429 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
430 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
431 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
432 return rc;
433 }
434 }
435# endif
436
437 AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
438 || (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
439 ("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
440
441# if defined(IN_RC) || defined(IN_RING0)
442 if (pCur->CTX_SUFF(pfnHandler))
443 {
444 STAM_PROFILE_START(&pCur->Stat, h);
445 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
446 STAM_PROFILE_STOP(&pCur->Stat, h);
447 }
448 else
449# endif
450 rc = VINF_EM_RAW_EMULATE_INSTR;
451 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
452 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
453 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
454 return rc;
455 }
456 }
457# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
458 else
459 {
460# ifdef PGM_SYNC_N_PAGES
461 /*
462 * If the region is write protected and we got a page not present fault, then sync
463 * the pages. If the fault was caused by a read, then restart the instruction.
464 * In case of write access continue to the GC write handler.
465 */
466 if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
467 && !(uErr & X86_TRAP_PF_P))
468 {
469 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
470 if ( RT_FAILURE(rc)
471 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
472 || !(uErr & X86_TRAP_PF_RW))
473 {
474 AssertRC(rc);
475 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
476 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
477 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
478 return rc;
479 }
480 }
481# endif
482 /*
483 * Ok, it's an virtual page access handler.
484 *
485 * Since it's faster to search by address, we'll do that first
486 * and then retry by GCPhys if that fails.
487 */
488 /** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
489 /** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
490 * page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
491 */
492 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
493 if (pCur)
494 {
495 AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
496 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
497 || !(uErr & X86_TRAP_PF_P)
498 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
499 ("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
500
501 if ( pvFault - pCur->Core.Key < pCur->cb
502 && ( uErr & X86_TRAP_PF_RW
503 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
504 {
505# ifdef IN_RC
506 STAM_PROFILE_START(&pCur->Stat, h);
507 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
508 STAM_PROFILE_STOP(&pCur->Stat, h);
509# else
510 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
511# endif
512 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
513 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
514 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
515 return rc;
516 }
517 /* Unhandled part of a monitored page */
518 }
519 else
520 {
521 /* Check by physical address. */
522 PPGMVIRTHANDLER pCur;
523 unsigned iPage;
524 rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
525 &pCur, &iPage);
526 Assert(RT_SUCCESS(rc) || !pCur);
527 if ( pCur
528 && ( uErr & X86_TRAP_PF_RW
529 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
530 {
531 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
532# ifdef IN_RC
533 RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
534 Assert(off < pCur->cb);
535 STAM_PROFILE_START(&pCur->Stat, h);
536 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
537 STAM_PROFILE_STOP(&pCur->Stat, h);
538# else
539 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
540# endif
541 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
542 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
543 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
544 return rc;
545 }
546 }
547 }
548# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
549
550 /*
551 * There is a handled area of the page, but this fault doesn't belong to it.
552 * We must emulate the instruction.
553 *
554 * To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
555 * we first check if this was a page-not-present fault for a page with only
556 * write access handlers. Restart the instruction if it wasn't a write access.
557 */
558 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
559
560 if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
561 && !(uErr & X86_TRAP_PF_P))
562 {
563 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
564 if ( RT_FAILURE(rc)
565 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
566 || !(uErr & X86_TRAP_PF_RW))
567 {
568 AssertRC(rc);
569 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
570 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
571 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
572 return rc;
573 }
574 }
575
576 /** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
577 * It's writing to an unhandled part of the LDT page several million times.
578 */
579 rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
580 LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
581 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
582 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
583 return rc;
584 } /* if any kind of handler */
585
586# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
587 if (uErr & X86_TRAP_PF_P)
588 {
589 /*
590 * The page isn't marked, but it might still be monitored by a virtual page access handler.
591 * (ASSUMES no temporary disabling of virtual handlers.)
592 */
593 /** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
594 * we should correct both the shadow page table and physical memory flags, and not only check for
595 * accesses within the handler region but for access to pages with virtual handlers. */
596 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
597 if (pCur)
598 {
599 AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
600 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
601 || !(uErr & X86_TRAP_PF_P)
602 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
603 ("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
604
605 if ( pvFault - pCur->Core.Key < pCur->cb
606 && ( uErr & X86_TRAP_PF_RW
607 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
608 {
609# ifdef IN_RC
610 STAM_PROFILE_START(&pCur->Stat, h);
611 rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
612 STAM_PROFILE_STOP(&pCur->Stat, h);
613# else
614 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
615# endif
616 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
617 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
618 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
619 return rc;
620 }
621 }
622 }
623# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
624 }
625 else
626 {
627 /*
628 * When the guest accesses invalid physical memory (e.g. probing
629 * of RAM or accessing a remapped MMIO range), then we'll fall
630 * back to the recompiler to emulate the instruction.
631 */
632 LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
633 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
634 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
635 return VINF_EM_RAW_EMULATE_INSTR;
636 }
637
638 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
639
640# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
641 /*
642 * We are here only if page is present in Guest page tables and
643 * trap is not handled by our handlers.
644 *
645 * Check it for page out-of-sync situation.
646 */
647 STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
648
649 if (!(uErr & X86_TRAP_PF_P))
650 {
651 /*
652 * Page is not present in our page tables.
653 * Try to sync it!
654 * BTW, fPageShw is invalid in this branch!
655 */
656 if (uErr & X86_TRAP_PF_US)
657 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
658 else /* supervisor */
659 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
660
661# if defined(LOG_ENABLED) && !defined(IN_RING0)
662 RTGCPHYS GCPhys;
663 uint64_t fPageGst;
664 PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
665 Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
666 pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
667# endif /* LOG_ENABLED */
668
669# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
670 if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
671 {
672 uint64_t fPageGst;
673 rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
674 if ( RT_SUCCESS(rc)
675 && !(fPageGst & X86_PTE_US))
676 {
677 /* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
678 if ( pvFault == (RTGCPTR)pRegFrame->eip
679 || pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
680# ifdef CSAM_DETECT_NEW_CODE_PAGES
681 || ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
682 && CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
683# endif /* CSAM_DETECT_NEW_CODE_PAGES */
684 )
685 {
686 LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
687 rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
688 if (rc != VINF_SUCCESS)
689 {
690 /*
691 * CSAM needs to perform a job in ring 3.
692 *
693 * Sync the page before going to the host context; otherwise we'll end up in a loop if
694 * CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
695 */
696 LogFlow(("CSAM ring 3 job\n"));
697 int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
698 AssertRC(rc2);
699
700 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
701 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
702 return rc;
703 }
704 }
705# ifdef CSAM_DETECT_NEW_CODE_PAGES
706 else if ( uErr == X86_TRAP_PF_RW
707 && pRegFrame->ecx >= 0x100 /* early check for movswd count */
708 && pRegFrame->ecx < 0x10000)
709 {
710 /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
711 * to detect loading of new code pages.
712 */
713
714 /*
715 * Decode the instruction.
716 */
717 RTGCPTR PC;
718 rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
719 if (rc == VINF_SUCCESS)
720 {
721 DISCPUSTATE Cpu;
722 uint32_t cbOp;
723 rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
724
725 /* For now we'll restrict this to rep movsw/d instructions */
726 if ( rc == VINF_SUCCESS
727 && Cpu.pCurInstr->opcode == OP_MOVSWD
728 && (Cpu.prefix & PREFIX_REP))
729 {
730 CSAMMarkPossibleCodePage(pVM, pvFault);
731 }
732 }
733 }
734# endif /* CSAM_DETECT_NEW_CODE_PAGES */
735
736 /*
737 * Mark this page as safe.
738 */
739 /** @todo not correct for pages that contain both code and data!! */
740 Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
741 CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
742 }
743 }
744# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
745 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
746 if (RT_SUCCESS(rc))
747 {
748 /* The page was successfully synced, return to the guest. */
749 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
750 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
751 return VINF_SUCCESS;
752 }
753 }
754 else /* uErr & X86_TRAP_PF_P: */
755 {
756 /*
757 * Write protected pages are make writable when the guest makes the first
758 * write to it. This happens for pages that are shared, write monitored
759 * and not yet allocated.
760 *
761 * Also, a side effect of not flushing global PDEs are out of sync pages due
762 * to physical monitored regions, that are no longer valid.
763 * Assume for now it only applies to the read/write flag.
764 */
765 if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
766 {
767 if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
768 {
769 Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
770 GCPhys, pPage, pvFault, uErr));
771 rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
772 if (rc != VINF_SUCCESS)
773 {
774 AssertMsg(rc == VINF_PGM_SYNC_CR3 || RT_FAILURE(rc), ("%Rrc\n", rc));
775 return rc;
776 }
777 if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
778 return VINF_EM_NO_MEMORY;
779 }
780 /// @todo count the above case; else
781 if (uErr & X86_TRAP_PF_US)
782 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
783 else /* supervisor */
784 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
785
786 /*
787 * Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
788 * page is not present, which is not true in this case.
789 */
790 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
791 if (RT_SUCCESS(rc))
792 {
793 /*
794 * Page was successfully synced, return to guest.
795 */
796# ifdef VBOX_STRICT
797 RTGCPHYS GCPhys;
798 uint64_t fPageGst;
799 rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
800 Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
801 LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
802
803 uint64_t fPageShw;
804 rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
805 AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
806# endif /* VBOX_STRICT */
807 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
808 STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
809 return VINF_SUCCESS;
810 }
811
812 /* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
813 if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
814 && ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP | X86_CR0_PG)) == X86_CR0_PG)
815 && (uErr & (X86_TRAP_PF_RW | X86_TRAP_PF_P)) == (X86_TRAP_PF_RW | X86_TRAP_PF_P))
816 {
817 uint64_t fPageGst;
818 rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
819 if ( RT_SUCCESS(rc)
820 && !(fPageGst & X86_PTE_RW))
821 {
822 rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
823 if (RT_SUCCESS(rc))
824 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
825 else
826 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
827 return rc;
828 }
829 AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
830 }
831 }
832
833# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
834# ifdef VBOX_STRICT
835 /*
836 * Check for VMM page flags vs. Guest page flags consistency.
837 * Currently only for debug purposes.
838 */
839 if (RT_SUCCESS(rc))
840 {
841 /* Get guest page flags. */
842 uint64_t fPageGst;
843 rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
844 if (RT_SUCCESS(rc))
845 {
846 uint64_t fPageShw;
847 rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
848
849 /*
850 * Compare page flags.
851 * Note: we have AVL, A, D bits desynched.
852 */
853 AssertMsg((fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)),
854 ("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
855 }
856 else
857 AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
858 }
859 else
860 AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
861# endif /* VBOX_STRICT */
862# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
863 }
864 STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
865# endif /* PGM_OUT_OF_SYNC_IN_GC */
866 }
867 else /* GCPhys == NIL_RTGCPHYS */
868 {
869 /*
870 * Page not present in Guest OS or invalid page table address.
871 * This is potential virtual page access handler food.
872 *
873 * For the present we'll say that our access handlers don't
874 * work for this case - we've already discarded the page table
875 * not present case which is identical to this.
876 *
877 * When we perchance find we need this, we will probably have AVL
878 * trees (offset based) to operate on and we can measure their speed
879 * agains mapping a page table and probably rearrange this handling
880 * a bit. (Like, searching virtual ranges before checking the
881 * physical address.)
882 */
883 }
884 }
885 /* else: !present (guest) */
886
887
888# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
889 /*
890 * Conclusion, this is a guest trap.
891 */
892 LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
893 STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
894 return VINF_EM_RAW_GUEST_TRAP;
895# else
896 /* present, but not a monitored page; perhaps the guest is probing physical memory */
897 return VINF_EM_RAW_EMULATE_INSTR;
898# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
899
900
901# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
902
903 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
904 return VERR_INTERNAL_ERROR;
905# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
906}
907#endif /* !IN_RING3 */
908
909
910/**
911 * Emulation of the invlpg instruction.
912 *
913 *
914 * @returns VBox status code.
915 *
916 * @param pVCpu The VMCPU handle.
917 * @param GCPtrPage Page to invalidate.
918 *
919 * @remark ASSUMES that the guest is updating before invalidating. This order
920 * isn't required by the CPU, so this is speculative and could cause
921 * trouble.
922 *
923 * @todo Flush page or page directory only if necessary!
924 * @todo Add a #define for simply invalidating the page.
925 */
926PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
927{
928#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
929 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
930 && PGM_SHW_TYPE != PGM_TYPE_EPT
931 int rc;
932 PVM pVM = pVCpu->CTX_SUFF(pVM);
933 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
934
935 LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
936 /*
937 * Get the shadow PD entry and skip out if this PD isn't present.
938 * (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
939 */
940# if PGM_SHW_TYPE == PGM_TYPE_32BIT
941 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
942 PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
943
944 /* Fetch the pgm pool shadow descriptor. */
945 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
946 Assert(pShwPde);
947
948# elif PGM_SHW_TYPE == PGM_TYPE_PAE
949 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
950 PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
951
952 /* If the shadow PDPE isn't present, then skip the invalidate. */
953 if (!pPdptDst->a[iPdpt].n.u1Present)
954 {
955 Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
956 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
957 return VINF_SUCCESS;
958 }
959
960 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
961 PPGMPOOLPAGE pShwPde = NULL;
962 PX86PDPAE pPDDst;
963
964 /* Fetch the pgm pool shadow descriptor. */
965 rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
966 AssertRCSuccessReturn(rc, rc);
967 Assert(pShwPde);
968
969 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
970 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
971
972# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
973 /* PML4 */
974 const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
975 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
976 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
977 PX86PDPAE pPDDst;
978 PX86PDPT pPdptDst;
979 PX86PML4E pPml4eDst;
980 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
981 if (rc != VINF_SUCCESS)
982 {
983 AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT || rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
984 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
985 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
986 PGM_INVL_GUEST_TLBS();
987 return VINF_SUCCESS;
988 }
989 Assert(pPDDst);
990
991 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
992 PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
993
994 if (!pPdpeDst->n.u1Present)
995 {
996 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
997 if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
998 PGM_INVL_GUEST_TLBS();
999 return VINF_SUCCESS;
1000 }
1001
1002# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1003
1004 const SHWPDE PdeDst = *pPdeDst;
1005 if (!PdeDst.n.u1Present)
1006 {
1007 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1008 return VINF_SUCCESS;
1009 }
1010
1011# if defined(IN_RC)
1012 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1013 PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1014# endif
1015
1016 /*
1017 * Get the guest PD entry and calc big page.
1018 */
1019# if PGM_GST_TYPE == PGM_TYPE_32BIT
1020 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1021 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1022 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1023# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1024 unsigned iPDSrc = 0;
1025# if PGM_GST_TYPE == PGM_TYPE_PAE
1026 X86PDPE PdpeSrc;
1027 PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1028# else /* AMD64 */
1029 PX86PML4E pPml4eSrc;
1030 X86PDPE PdpeSrc;
1031 PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1032# endif
1033 GSTPDE PdeSrc;
1034
1035 if (pPDSrc)
1036 PdeSrc = pPDSrc->a[iPDSrc];
1037 else
1038 PdeSrc.u = 0;
1039# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1040
1041# if PGM_GST_TYPE == PGM_TYPE_AMD64
1042 const bool fIsBigPage = PdeSrc.b.u1Size;
1043# else
1044 const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1045# endif
1046
1047# ifdef IN_RING3
1048 /*
1049 * If a CR3 Sync is pending we may ignore the invalidate page operation
1050 * depending on the kind of sync and if it's a global page or not.
1051 * This doesn't make sense in GC/R0 so we'll skip it entirely there.
1052 */
1053# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1054 if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1055 || ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1056 && fIsBigPage
1057 && PdeSrc.b.u1Global
1058 )
1059 )
1060# else
1061 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1062# endif
1063 {
1064 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1065 return VINF_SUCCESS;
1066 }
1067# endif /* IN_RING3 */
1068
1069# if PGM_GST_TYPE == PGM_TYPE_AMD64
1070 /* Fetch the pgm pool shadow descriptor. */
1071 PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1072 Assert(pShwPdpt);
1073
1074 /* Fetch the pgm pool shadow descriptor. */
1075 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1076 Assert(pShwPde);
1077
1078 Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1079 RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1080
1081 if ( !pPml4eSrc->n.u1Present
1082 || pShwPdpt->GCPhys != GCPhysPdpt)
1083 {
1084 LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1085 GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1086 pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1087 ASMAtomicWriteSize(pPml4eDst, 0);
1088 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1089 PGM_INVL_GUEST_TLBS();
1090 return VINF_SUCCESS;
1091 }
1092 if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1093 || (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1094 {
1095 /*
1096 * Mark not present so we can resync the PML4E when it's used.
1097 */
1098 LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1099 GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1100 pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1101 ASMAtomicWriteSize(pPml4eDst, 0);
1102 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1103 PGM_INVL_GUEST_TLBS();
1104 }
1105 else if (!pPml4eSrc->n.u1Accessed)
1106 {
1107 /*
1108 * Mark not present so we can set the accessed bit.
1109 */
1110 LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1111 GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1112 pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1113 ASMAtomicWriteSize(pPml4eDst, 0);
1114 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1115 PGM_INVL_GUEST_TLBS();
1116 }
1117
1118 /* Check if the PDPT entry has changed. */
1119 Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1120 RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1121 if ( !PdpeSrc.n.u1Present
1122 || pShwPde->GCPhys != GCPhysPd)
1123 {
1124 LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1125 GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1126 pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1127 ASMAtomicWriteSize(pPdpeDst, 0);
1128 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1129 PGM_INVL_GUEST_TLBS();
1130 return VINF_SUCCESS;
1131 }
1132 if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1133 || (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1134 {
1135 /*
1136 * Mark not present so we can resync the PDPTE when it's used.
1137 */
1138 LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1139 GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1140 pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1141 ASMAtomicWriteSize(pPdpeDst, 0);
1142 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1143 PGM_INVL_GUEST_TLBS();
1144 }
1145 else if (!PdpeSrc.lm.u1Accessed)
1146 {
1147 /*
1148 * Mark not present so we can set the accessed bit.
1149 */
1150 LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1151 GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1152 pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1153 ASMAtomicWriteSize(pPdpeDst, 0);
1154 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1155 PGM_INVL_GUEST_TLBS();
1156 }
1157# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1158
1159 /*
1160 * Deal with the Guest PDE.
1161 */
1162 rc = VINF_SUCCESS;
1163 if (PdeSrc.n.u1Present)
1164 {
1165 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1166 {
1167 /*
1168 * Conflict - Let SyncPT deal with it to avoid duplicate code.
1169 */
1170 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1171 Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1172 pgmLock(pVM);
1173 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1174 pgmUnlock(pVM);
1175 }
1176 else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1177 || (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1178 {
1179 /*
1180 * Mark not present so we can resync the PDE when it's used.
1181 */
1182 LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1183 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1184 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1185 ASMAtomicWriteSize(pPdeDst, 0);
1186 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1187 PGM_INVL_GUEST_TLBS();
1188 }
1189 else if (!PdeSrc.n.u1Accessed)
1190 {
1191 /*
1192 * Mark not present so we can set the accessed bit.
1193 */
1194 LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1195 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1196 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1197 ASMAtomicWriteSize(pPdeDst, 0);
1198 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1199 PGM_INVL_GUEST_TLBS();
1200 }
1201 else if (!fIsBigPage)
1202 {
1203 /*
1204 * 4KB - page.
1205 */
1206 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1207 RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1208# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1209 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1210 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
1211# endif
1212 if (pShwPage->GCPhys == GCPhys)
1213 {
1214# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1215 const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1216 PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1217 if (pPT->a[iPTEDst].n.u1Present)
1218 {
1219# ifdef PGMPOOL_WITH_USER_TRACKING
1220 /* This is very unlikely with caching/monitoring enabled. */
1221 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1222# endif
1223 ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1224 }
1225# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1226 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1227 if (RT_SUCCESS(rc))
1228 rc = VINF_SUCCESS;
1229# endif
1230 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1231 PGM_INVL_PG(GCPtrPage);
1232 }
1233 else
1234 {
1235 /*
1236 * The page table address changed.
1237 */
1238 LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1239 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1240 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1241 ASMAtomicWriteSize(pPdeDst, 0);
1242 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1243 PGM_INVL_GUEST_TLBS();
1244 }
1245 }
1246 else
1247 {
1248 /*
1249 * 2/4MB - page.
1250 */
1251 /* Before freeing the page, check if anything really changed. */
1252 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1253 RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1254# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1255 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1256 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1257# endif
1258 if ( pShwPage->GCPhys == GCPhys
1259 && pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1260 {
1261 /* ASSUMES a the given bits are identical for 4M and normal PDEs */
1262 /** @todo PAT */
1263 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
1264 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
1265 && ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1266 || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1267 {
1268 LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1269 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1270# if defined(IN_RC)
1271 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1272 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1273# endif
1274 return VINF_SUCCESS;
1275 }
1276 }
1277
1278 /*
1279 * Ok, the page table is present and it's been changed in the guest.
1280 * If we're in host context, we'll just mark it as not present taking the lazy approach.
1281 * We could do this for some flushes in GC too, but we need an algorithm for
1282 * deciding which 4MB pages containing code likely to be executed very soon.
1283 */
1284 LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1285 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1286 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1287 ASMAtomicWriteSize(pPdeDst, 0);
1288 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1289 PGM_INVL_BIG_PG(GCPtrPage);
1290 }
1291 }
1292 else
1293 {
1294 /*
1295 * Page directory is not present, mark shadow PDE not present.
1296 */
1297 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1298 {
1299 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1300 ASMAtomicWriteSize(pPdeDst, 0);
1301 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1302 PGM_INVL_PG(GCPtrPage);
1303 }
1304 else
1305 {
1306 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1307 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1308 }
1309 }
1310# if defined(IN_RC)
1311 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1312 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1313# endif
1314 return rc;
1315
1316#else /* guest real and protected mode */
1317 /* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1318 return VINF_SUCCESS;
1319#endif
1320}
1321
1322
1323#ifdef PGMPOOL_WITH_USER_TRACKING
1324/**
1325 * Update the tracking of shadowed pages.
1326 *
1327 * @param pVCpu The VMCPU handle.
1328 * @param pShwPage The shadow page.
1329 * @param HCPhys The physical page we is being dereferenced.
1330 */
1331DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1332{
1333# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1334 PVM pVM = pVCpu->CTX_SUFF(pVM);
1335
1336 STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1337 LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1338
1339 /** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
1340 * 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1341 * 2. write protect all shadowed pages. I.e. implement caching.
1342 */
1343 /*
1344 * Find the guest address.
1345 */
1346 for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1347 pRam;
1348 pRam = pRam->CTX_SUFF(pNext))
1349 {
1350 unsigned iPage = pRam->cb >> PAGE_SHIFT;
1351 while (iPage-- > 0)
1352 {
1353 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1354 {
1355 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1356 pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1357 pShwPage->cPresent--;
1358 pPool->cPresent--;
1359 STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1360 return;
1361 }
1362 }
1363 }
1364
1365 for (;;)
1366 AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1367# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1368 pShwPage->cPresent--;
1369 pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1370# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1371}
1372
1373
1374/**
1375 * Update the tracking of shadowed pages.
1376 *
1377 * @param pVCpu The VMCPU handle.
1378 * @param pShwPage The shadow page.
1379 * @param u16 The top 16-bit of the pPage->HCPhys.
1380 * @param pPage Pointer to the guest page. this will be modified.
1381 * @param iPTDst The index into the shadow table.
1382 */
1383DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1384{
1385 PVM pVM = pVCpu->CTX_SUFF(pVM);
1386# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1387 /*
1388 * Just deal with the simple first time here.
1389 */
1390 if (!u16)
1391 {
1392 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1393 u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1394 }
1395 else
1396 u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1397
1398 /* write back */
1399 Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1400 PGM_PAGE_SET_TRACKING(pPage, u16);
1401
1402# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1403
1404 /* update statistics. */
1405 pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1406 pShwPage->cPresent++;
1407 if (pShwPage->iFirstPresent > iPTDst)
1408 pShwPage->iFirstPresent = iPTDst;
1409}
1410#endif /* PGMPOOL_WITH_USER_TRACKING */
1411
1412
1413/**
1414 * Creates a 4K shadow page for a guest page.
1415 *
1416 * For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1417 * physical address. The PdeSrc argument only the flags are used. No page structured
1418 * will be mapped in this function.
1419 *
1420 * @param pVCpu The VMCPU handle.
1421 * @param pPteDst Destination page table entry.
1422 * @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1423 * Can safely assume that only the flags are being used.
1424 * @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1425 * @param pShwPage Pointer to the shadow page.
1426 * @param iPTDst The index into the shadow table.
1427 *
1428 * @remark Not used for 2/4MB pages!
1429 */
1430DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1431{
1432 if (PteSrc.n.u1Present)
1433 {
1434 PVM pVM = pVCpu->CTX_SUFF(pVM);
1435
1436 /*
1437 * Find the ram range.
1438 */
1439 PPGMPAGE pPage;
1440 int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1441 if (RT_SUCCESS(rc))
1442 {
1443#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1444 /* Try make the page writable if necessary. */
1445 if ( PteSrc.n.u1Write
1446 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1447 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1448 {
1449 rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1450 AssertRC(rc);
1451 }
1452#endif
1453
1454 /** @todo investiage PWT, PCD and PAT. */
1455 /*
1456 * Make page table entry.
1457 */
1458 SHWPTE PteDst;
1459 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1460 {
1461 /** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1462 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1463 {
1464#if PGM_SHW_TYPE == PGM_TYPE_EPT
1465 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1466 PteDst.n.u1Present = 1;
1467 PteDst.n.u1Execute = 1;
1468 PteDst.n.u1IgnorePAT = 1;
1469 PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1470 /* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1471#else
1472 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1473 | PGM_PAGE_GET_HCPHYS(pPage);
1474#endif
1475 }
1476 else
1477 {
1478 LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1479 PteDst.u = 0;
1480 }
1481 /** @todo count these two kinds. */
1482 }
1483 else
1484 {
1485#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1486 /*
1487 * If the page or page directory entry is not marked accessed,
1488 * we mark the page not present.
1489 */
1490 if (!PteSrc.n.u1Accessed || !PdeSrc.n.u1Accessed)
1491 {
1492 LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1493 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1494 PteDst.u = 0;
1495 }
1496 else
1497 /*
1498 * If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1499 * when the page is modified.
1500 */
1501 if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1502 {
1503 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1504 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1505 | PGM_PAGE_GET_HCPHYS(pPage)
1506 | PGM_PTFLAGS_TRACK_DIRTY;
1507 }
1508 else
1509#endif
1510 {
1511 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1512#if PGM_SHW_TYPE == PGM_TYPE_EPT
1513 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1514 PteDst.n.u1Present = 1;
1515 PteDst.n.u1Write = 1;
1516 PteDst.n.u1Execute = 1;
1517 PteDst.n.u1IgnorePAT = 1;
1518 PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1519 /* PteDst.n.u1Size = 0 */
1520#else
1521 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1522 | PGM_PAGE_GET_HCPHYS(pPage);
1523#endif
1524 }
1525 }
1526
1527 /*
1528 * Make sure only allocated pages are mapped writable.
1529 */
1530 if ( PteDst.n.u1Write
1531 && PteDst.n.u1Present
1532 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1533 {
1534 PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1535 Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1536 }
1537
1538#ifdef PGMPOOL_WITH_USER_TRACKING
1539 /*
1540 * Keep user track up to date.
1541 */
1542 if (PteDst.n.u1Present)
1543 {
1544 if (!pPteDst->n.u1Present)
1545 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1546 else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1547 {
1548 Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1549 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1550 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1551 }
1552 }
1553 else if (pPteDst->n.u1Present)
1554 {
1555 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1556 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1557 }
1558#endif /* PGMPOOL_WITH_USER_TRACKING */
1559
1560 /*
1561 * Update statistics and commit the entry.
1562 */
1563#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1564 if (!PteSrc.n.u1Global)
1565 pShwPage->fSeenNonGlobal = true;
1566#endif
1567 ASMAtomicWriteSize(pPteDst, PteDst.u);
1568 }
1569 /* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1570 /** @todo count these. */
1571 }
1572 else
1573 {
1574 /*
1575 * Page not-present.
1576 */
1577 LogFlow(("SyncPageWorker: page not present in Pte\n"));
1578#ifdef PGMPOOL_WITH_USER_TRACKING
1579 /* Keep user track up to date. */
1580 if (pPteDst->n.u1Present)
1581 {
1582 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1583 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1584 }
1585#endif /* PGMPOOL_WITH_USER_TRACKING */
1586 ASMAtomicWriteSize(pPteDst, 0);
1587 /** @todo count these. */
1588 }
1589}
1590
1591
1592/**
1593 * Syncs a guest OS page.
1594 *
1595 * There are no conflicts at this point, neither is there any need for
1596 * page table allocations.
1597 *
1598 * @returns VBox status code.
1599 * @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1600 * @param pVCpu The VMCPU handle.
1601 * @param PdeSrc Page directory entry of the guest.
1602 * @param GCPtrPage Guest context page address.
1603 * @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1604 * @param uErr Fault error (X86_TRAP_PF_*).
1605 */
1606PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1607{
1608 PVM pVM = pVCpu->CTX_SUFF(pVM);
1609 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1610 LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1611
1612#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1613 || PGM_GST_TYPE == PGM_TYPE_PAE \
1614 || PGM_GST_TYPE == PGM_TYPE_AMD64) \
1615 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
1616 && PGM_SHW_TYPE != PGM_TYPE_EPT
1617
1618# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1619 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1620# endif
1621
1622 /*
1623 * Assert preconditions.
1624 */
1625 Assert(PdeSrc.n.u1Present);
1626 Assert(cPages);
1627 STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1628
1629 /*
1630 * Get the shadow PDE, find the shadow page table in the pool.
1631 */
1632# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1633 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1634 PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1635
1636 /* Fetch the pgm pool shadow descriptor. */
1637 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1638 Assert(pShwPde);
1639
1640# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1641 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1642 PPGMPOOLPAGE pShwPde = NULL;
1643 PX86PDPAE pPDDst;
1644
1645 /* Fetch the pgm pool shadow descriptor. */
1646 int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1647 AssertRCSuccessReturn(rc, rc);
1648 Assert(pShwPde);
1649
1650 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1651 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1652
1653# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1654 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1655 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1656 PX86PDPAE pPDDst;
1657 PX86PDPT pPdptDst;
1658
1659 int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1660 AssertRCSuccessReturn(rc, rc);
1661 Assert(pPDDst && pPdptDst);
1662 PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1663# endif
1664 SHWPDE PdeDst = *pPdeDst;
1665 AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1666 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1667
1668# if PGM_GST_TYPE == PGM_TYPE_AMD64
1669 /* Fetch the pgm pool shadow descriptor. */
1670 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1671 Assert(pShwPde);
1672# endif
1673
1674# if defined(IN_RC)
1675 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1676 PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1677# endif
1678
1679 /*
1680 * Check that the page is present and that the shadow PDE isn't out of sync.
1681 */
1682# if PGM_GST_TYPE == PGM_TYPE_AMD64
1683 const bool fBigPage = PdeSrc.b.u1Size;
1684# else
1685 const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1686# endif
1687 RTGCPHYS GCPhys;
1688 if (!fBigPage)
1689 {
1690 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1691# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1692 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1693 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
1694# endif
1695 }
1696 else
1697 {
1698 GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1699# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1700 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1701 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1702# endif
1703 }
1704 if ( pShwPage->GCPhys == GCPhys
1705 && PdeSrc.n.u1Present
1706 && (PdeSrc.n.u1User == PdeDst.n.u1User)
1707 && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
1708# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1709 && (!fNoExecuteBitValid || PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1710# endif
1711 )
1712 {
1713 /*
1714 * Check that the PDE is marked accessed already.
1715 * Since we set the accessed bit *before* getting here on a #PF, this
1716 * check is only meant for dealing with non-#PF'ing paths.
1717 */
1718 if (PdeSrc.n.u1Accessed)
1719 {
1720 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1721 if (!fBigPage)
1722 {
1723 /*
1724 * 4KB Page - Map the guest page table.
1725 */
1726 PGSTPT pPTSrc;
1727 int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1728 if (RT_SUCCESS(rc))
1729 {
1730# ifdef PGM_SYNC_N_PAGES
1731 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1732 if ( cPages > 1
1733 && !(uErr & X86_TRAP_PF_P)
1734 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1735 {
1736 /*
1737 * This code path is currently only taken when the caller is PGMTrap0eHandler
1738 * for non-present pages!
1739 *
1740 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1741 * deal with locality.
1742 */
1743 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1744# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1745 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1746 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1747# else
1748 const unsigned offPTSrc = 0;
1749# endif
1750 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1751 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1752 iPTDst = 0;
1753 else
1754 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1755 for (; iPTDst < iPTDstEnd; iPTDst++)
1756 {
1757 if (!pPTDst->a[iPTDst].n.u1Present)
1758 {
1759 GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1760 RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1761 NOREF(GCPtrCurPage);
1762#ifndef IN_RING0
1763 /*
1764 * Assuming kernel code will be marked as supervisor - and not as user level
1765 * and executed using a conforming code selector - And marked as readonly.
1766 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
1767 */
1768 PPGMPAGE pPage;
1769 if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW | X86_PTE_US))
1770 || iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1771 || !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1772 || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1773 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1774 )
1775#endif /* else: CSAM not active */
1776 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1777 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1778 GCPtrCurPage, PteSrc.n.u1Present,
1779 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1780 PteSrc.n.u1User & PdeSrc.n.u1User,
1781 (uint64_t)PteSrc.u,
1782 (uint64_t)pPTDst->a[iPTDst].u,
1783 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1784 }
1785 }
1786 }
1787 else
1788# endif /* PGM_SYNC_N_PAGES */
1789 {
1790 const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1791 GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1792 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1793 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1794 Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1795 GCPtrPage, PteSrc.n.u1Present,
1796 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1797 PteSrc.n.u1User & PdeSrc.n.u1User,
1798 (uint64_t)PteSrc.u,
1799 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1800 }
1801 }
1802 else /* MMIO or invalid page: emulated in #PF handler. */
1803 {
1804 LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1805 Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1806 }
1807 }
1808 else
1809 {
1810 /*
1811 * 4/2MB page - lazy syncing shadow 4K pages.
1812 * (There are many causes of getting here, it's no longer only CSAM.)
1813 */
1814 /* Calculate the GC physical address of this 4KB shadow page. */
1815 RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) | (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1816 /* Find ram range. */
1817 PPGMPAGE pPage;
1818 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1819 if (RT_SUCCESS(rc))
1820 {
1821# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1822 /* Try make the page writable if necessary. */
1823 if ( PdeSrc.n.u1Write
1824 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1825 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1826 {
1827 rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1828 AssertRC(rc);
1829 }
1830# endif
1831
1832 /*
1833 * Make shadow PTE entry.
1834 */
1835 SHWPTE PteDst;
1836 PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1837 | PGM_PAGE_GET_HCPHYS(pPage);
1838 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1839 {
1840 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1841 PteDst.n.u1Write = 0;
1842 else
1843 PteDst.u = 0;
1844 }
1845 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1846# ifdef PGMPOOL_WITH_USER_TRACKING
1847 if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1848 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1849# endif
1850 /* Make sure only allocated pages are mapped writable. */
1851 if ( PteDst.n.u1Write
1852 && PteDst.n.u1Present
1853 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1854 {
1855 PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1856 Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1857 }
1858
1859 ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1860
1861 /*
1862 * If the page is not flagged as dirty and is writable, then make it read-only
1863 * at PD level, so we can set the dirty bit when the page is modified.
1864 *
1865 * ASSUMES that page access handlers are implemented on page table entry level.
1866 * Thus we will first catch the dirty access and set PDE.D and restart. If
1867 * there is an access handler, we'll trap again and let it work on the problem.
1868 */
1869 /** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1870 * As for invlpg, it simply frees the whole shadow PT.
1871 * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1872 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1873 {
1874 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1875 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1876 PdeDst.n.u1Write = 0;
1877 }
1878 else
1879 {
1880 PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1881 PdeDst.n.u1Write = PdeSrc.n.u1Write;
1882 }
1883 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1884 Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1885 GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1886 PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1887 }
1888 else
1889 LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1890 }
1891# if defined(IN_RC)
1892 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1893 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1894# endif
1895 return VINF_SUCCESS;
1896 }
1897 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1898 }
1899 else
1900 {
1901 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1902 Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1903 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1904 }
1905
1906 /*
1907 * Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1908 * Yea, I'm lazy.
1909 */
1910 pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1911 ASMAtomicWriteSize(pPdeDst, 0);
1912
1913# if defined(IN_RC)
1914 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1915 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1916# endif
1917 PGM_INVL_GUEST_TLBS();
1918 return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1919
1920#elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
1921 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
1922 && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
1923 && !defined(IN_RC)
1924
1925# ifdef PGM_SYNC_N_PAGES
1926 /*
1927 * Get the shadow PDE, find the shadow page table in the pool.
1928 */
1929# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1930 X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1931
1932# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1933 X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1934
1935# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1936 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1937 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1938 PX86PDPAE pPDDst;
1939 X86PDEPAE PdeDst;
1940 PX86PDPT pPdptDst;
1941
1942 int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1943 AssertRCSuccessReturn(rc, rc);
1944 Assert(pPDDst && pPdptDst);
1945 PdeDst = pPDDst->a[iPDDst];
1946# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1947 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1948 PEPTPD pPDDst;
1949 EPTPDE PdeDst;
1950
1951 int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1952 if (rc != VINF_SUCCESS)
1953 {
1954 AssertRC(rc);
1955 return rc;
1956 }
1957 Assert(pPDDst);
1958 PdeDst = pPDDst->a[iPDDst];
1959# endif
1960 AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1961 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1962 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1963
1964 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1965 if ( cPages > 1
1966 && !(uErr & X86_TRAP_PF_P)
1967 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1968 {
1969 /*
1970 * This code path is currently only taken when the caller is PGMTrap0eHandler
1971 * for non-present pages!
1972 *
1973 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1974 * deal with locality.
1975 */
1976 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1977 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1978 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1979 iPTDst = 0;
1980 else
1981 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1982 for (; iPTDst < iPTDstEnd; iPTDst++)
1983 {
1984 if (!pPTDst->a[iPTDst].n.u1Present)
1985 {
1986 GSTPTE PteSrc;
1987
1988 RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT);
1989
1990 /* Fake the page table entry */
1991 PteSrc.u = GCPtrCurPage;
1992 PteSrc.n.u1Present = 1;
1993 PteSrc.n.u1Dirty = 1;
1994 PteSrc.n.u1Accessed = 1;
1995 PteSrc.n.u1Write = 1;
1996 PteSrc.n.u1User = 1;
1997
1998 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1999
2000 Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2001 GCPtrCurPage, PteSrc.n.u1Present,
2002 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2003 PteSrc.n.u1User & PdeSrc.n.u1User,
2004 (uint64_t)PteSrc.u,
2005 (uint64_t)pPTDst->a[iPTDst].u,
2006 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2007
2008 if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2009 break;
2010 }
2011 else
2012 Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2013 }
2014 }
2015 else
2016# endif /* PGM_SYNC_N_PAGES */
2017 {
2018 GSTPTE PteSrc;
2019 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2020 RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) | (iPTDst << PAGE_SHIFT);
2021
2022 /* Fake the page table entry */
2023 PteSrc.u = GCPtrCurPage;
2024 PteSrc.n.u1Present = 1;
2025 PteSrc.n.u1Dirty = 1;
2026 PteSrc.n.u1Accessed = 1;
2027 PteSrc.n.u1Write = 1;
2028 PteSrc.n.u1User = 1;
2029 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2030
2031 Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2032 GCPtrPage, PteSrc.n.u1Present,
2033 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2034 PteSrc.n.u1User & PdeSrc.n.u1User,
2035 (uint64_t)PteSrc.u,
2036 (uint64_t)pPTDst->a[iPTDst].u,
2037 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2038 }
2039 return VINF_SUCCESS;
2040
2041#else
2042 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2043 return VERR_INTERNAL_ERROR;
2044#endif
2045}
2046
2047
2048#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2049/**
2050 * Investigate page fault and handle write protection page faults caused by
2051 * dirty bit tracking.
2052 *
2053 * @returns VBox status code.
2054 * @param pVCpu The VMCPU handle.
2055 * @param uErr Page fault error code.
2056 * @param pPdeDst Shadow page directory entry.
2057 * @param pPdeSrc Guest page directory entry.
2058 * @param GCPtrPage Guest context page address.
2059 */
2060PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2061{
2062 bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2063 bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2064 bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2065# if PGM_GST_TYPE == PGM_TYPE_AMD64
2066 bool fBigPagesSupported = true;
2067# else
2068 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2069# endif
2070# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2071 bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2072# endif
2073 unsigned uPageFaultLevel;
2074 int rc;
2075 PVM pVM = pVCpu->CTX_SUFF(pVM);
2076 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2077
2078 Assert(PGMIsLockOwner(pVM));
2079
2080 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2081 LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2082
2083# if PGM_GST_TYPE == PGM_TYPE_PAE \
2084 || PGM_GST_TYPE == PGM_TYPE_AMD64
2085
2086# if PGM_GST_TYPE == PGM_TYPE_AMD64
2087 PX86PML4E pPml4eSrc;
2088 PX86PDPE pPdpeSrc;
2089
2090 pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2091 Assert(pPml4eSrc);
2092
2093 /*
2094 * Real page fault? (PML4E level)
2095 */
2096 if ( (uErr & X86_TRAP_PF_RSVD)
2097 || !pPml4eSrc->n.u1Present
2098 || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2099 || (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
2100 || (fUserLevelFault && !pPml4eSrc->n.u1User)
2101 )
2102 {
2103 uPageFaultLevel = 0;
2104 goto l_UpperLevelPageFault;
2105 }
2106 Assert(pPdpeSrc);
2107
2108# else /* PAE */
2109 PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2110# endif /* PAE */
2111
2112 /*
2113 * Real page fault? (PDPE level)
2114 */
2115 if ( (uErr & X86_TRAP_PF_RSVD)
2116 || !pPdpeSrc->n.u1Present
2117# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2118 || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2119 || (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault || fWriteProtect))
2120 || (fUserLevelFault && !pPdpeSrc->lm.u1User)
2121# endif
2122 )
2123 {
2124 uPageFaultLevel = 1;
2125 goto l_UpperLevelPageFault;
2126 }
2127# endif
2128
2129 /*
2130 * Real page fault? (PDE level)
2131 */
2132 if ( (uErr & X86_TRAP_PF_RSVD)
2133 || !pPdeSrc->n.u1Present
2134# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2135 || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2136# endif
2137 || (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault || fWriteProtect))
2138 || (fUserLevelFault && !pPdeSrc->n.u1User) )
2139 {
2140 uPageFaultLevel = 2;
2141 goto l_UpperLevelPageFault;
2142 }
2143
2144 /*
2145 * First check the easy case where the page directory has been marked read-only to track
2146 * the dirty bit of an emulated BIG page
2147 */
2148 if (pPdeSrc->b.u1Size && fBigPagesSupported)
2149 {
2150 /* Mark guest page directory as accessed */
2151# if PGM_GST_TYPE == PGM_TYPE_AMD64
2152 pPml4eSrc->n.u1Accessed = 1;
2153 pPdpeSrc->lm.u1Accessed = 1;
2154# endif
2155 pPdeSrc->b.u1Accessed = 1;
2156
2157 /*
2158 * Only write protection page faults are relevant here.
2159 */
2160 if (fWriteFault)
2161 {
2162 /* Mark guest page directory as dirty (BIG page only). */
2163 pPdeSrc->b.u1Dirty = 1;
2164
2165 if (pPdeDst->n.u1Present)
2166 {
2167 if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2168 {
2169 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2170 Assert(pPdeSrc->b.u1Write);
2171
2172 /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2173 * fault again and take this path to only invalidate the entry.
2174 */
2175 pPdeDst->n.u1Write = 1;
2176 pPdeDst->n.u1Accessed = 1;
2177 pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2178 PGM_INVL_BIG_PG(GCPtrPage);
2179 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2180 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2181 }
2182# ifdef IN_RING0
2183 else
2184 /* Check for stale TLB entry; only applies to the SMP guest case. */
2185 if ( pVM->cCPUs > 1
2186 && pPdeDst->n.u1Write
2187 && pPdeDst->n.u1Accessed)
2188 {
2189 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2190 if (pShwPage)
2191 {
2192 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2193 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2194 if ( pPteDst->n.u1Present
2195 && pPteDst->n.u1Write)
2196 {
2197 /* Stale TLB entry. */
2198 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2199 PGM_INVL_PG(GCPtrPage);
2200
2201 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2202 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2203 }
2204 }
2205 }
2206# endif /* IN_RING0 */
2207 }
2208 }
2209 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2210 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2211 }
2212 /* else: 4KB page table */
2213
2214 /*
2215 * Map the guest page table.
2216 */
2217 PGSTPT pPTSrc;
2218 rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2219 if (RT_SUCCESS(rc))
2220 {
2221 /*
2222 * Real page fault?
2223 */
2224 PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2225 const GSTPTE PteSrc = *pPteSrc;
2226 if ( !PteSrc.n.u1Present
2227# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2228 || (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2229# endif
2230 || (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault || fWriteProtect))
2231 || (fUserLevelFault && !PteSrc.n.u1User)
2232 )
2233 {
2234 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2235 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2236 LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2237
2238 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2239 * See the 2nd case above as well.
2240 */
2241 if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2242 TRPMSetErrorCode(pVCpu, uErr | X86_TRAP_PF_P); /* page-level protection violation */
2243
2244 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2245 return VINF_EM_RAW_GUEST_TRAP;
2246 }
2247 LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2248
2249 /*
2250 * Set the accessed bits in the page directory and the page table.
2251 */
2252# if PGM_GST_TYPE == PGM_TYPE_AMD64
2253 pPml4eSrc->n.u1Accessed = 1;
2254 pPdpeSrc->lm.u1Accessed = 1;
2255# endif
2256 pPdeSrc->n.u1Accessed = 1;
2257 pPteSrc->n.u1Accessed = 1;
2258
2259 /*
2260 * Only write protection page faults are relevant here.
2261 */
2262 if (fWriteFault)
2263 {
2264 /* Write access, so mark guest entry as dirty. */
2265# ifdef VBOX_WITH_STATISTICS
2266 if (!pPteSrc->n.u1Dirty)
2267 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2268 else
2269 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2270# endif
2271
2272 pPteSrc->n.u1Dirty = 1;
2273
2274 if (pPdeDst->n.u1Present)
2275 {
2276#ifndef IN_RING0
2277 /* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2278 * Our individual shadow handlers will provide more information and force a fatal exit.
2279 */
2280 if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2281 {
2282 LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2283 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2284 return VINF_SUCCESS;
2285 }
2286#endif
2287 /*
2288 * Map shadow page table.
2289 */
2290 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2291 if (pShwPage)
2292 {
2293 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2294 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2295 if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2296 {
2297 if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2298 {
2299 LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2300# ifdef VBOX_STRICT
2301 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2302 if (pPage)
2303 AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2304 ("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2305# endif
2306 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2307
2308 Assert(pPteSrc->n.u1Write);
2309
2310 /* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2311 * fault again and take this path to only invalidate the entry.
2312 */
2313 pPteDst->n.u1Write = 1;
2314 pPteDst->n.u1Dirty = 1;
2315 pPteDst->n.u1Accessed = 1;
2316 pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2317 PGM_INVL_PG(GCPtrPage);
2318
2319 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2320 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2321 }
2322# ifdef IN_RING0
2323 else
2324 /* Check for stale TLB entry; only applies to the SMP guest case. */
2325 if ( pVM->cCPUs > 1
2326 && pPteDst->n.u1Write == 1
2327 && pPteDst->n.u1Accessed == 1)
2328 {
2329 /* Stale TLB entry. */
2330 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2331 PGM_INVL_PG(GCPtrPage);
2332
2333 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2334 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2335 }
2336# endif
2337 }
2338 }
2339 else
2340 AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2341 }
2342 }
2343/** @todo Optimize accessed bit emulation? */
2344# ifdef VBOX_STRICT
2345 /*
2346 * Sanity check.
2347 */
2348 else if ( !pPteSrc->n.u1Dirty
2349 && (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2350 && pPdeDst->n.u1Present)
2351 {
2352 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2353 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2354 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2355 if ( pPteDst->n.u1Present
2356 && pPteDst->n.u1Write)
2357 LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2358 }
2359# endif /* VBOX_STRICT */
2360 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2361 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2362 }
2363 AssertRC(rc);
2364 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2365 return rc;
2366
2367
2368l_UpperLevelPageFault:
2369 /*
2370 * Pagefault detected while checking the PML4E, PDPE or PDE.
2371 * Single exit handler to get rid of duplicate code paths.
2372 */
2373 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2374 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2375 Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2376
2377 if (
2378# if PGM_GST_TYPE == PGM_TYPE_AMD64
2379 pPml4eSrc->n.u1Present &&
2380# endif
2381# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
2382 pPdpeSrc->n.u1Present &&
2383# endif
2384 pPdeSrc->n.u1Present)
2385 {
2386 /* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2387 if (pPdeSrc->b.u1Size && fBigPagesSupported)
2388 {
2389 TRPMSetErrorCode(pVCpu, uErr | X86_TRAP_PF_P); /* page-level protection violation */
2390 }
2391 else
2392 {
2393 /*
2394 * Map the guest page table.
2395 */
2396 PGSTPT pPTSrc;
2397 rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2398 if (RT_SUCCESS(rc))
2399 {
2400 PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2401 const GSTPTE PteSrc = *pPteSrc;
2402 if (pPteSrc->n.u1Present)
2403 TRPMSetErrorCode(pVCpu, uErr | X86_TRAP_PF_P); /* page-level protection violation */
2404 }
2405 AssertRC(rc);
2406 }
2407 }
2408 return VINF_EM_RAW_GUEST_TRAP;
2409}
2410#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2411
2412
2413/**
2414 * Sync a shadow page table.
2415 *
2416 * The shadow page table is not present. This includes the case where
2417 * there is a conflict with a mapping.
2418 *
2419 * @returns VBox status code.
2420 * @param pVCpu The VMCPU handle.
2421 * @param iPD Page directory index.
2422 * @param pPDSrc Source page directory (i.e. Guest OS page directory).
2423 * Assume this is a temporary mapping.
2424 * @param GCPtrPage GC Pointer of the page that caused the fault
2425 */
2426PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2427{
2428 PVM pVM = pVCpu->CTX_SUFF(pVM);
2429 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2430
2431 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2432 STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2433 LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2434
2435 Assert(PGMIsLocked(pVM));
2436
2437#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2438 || PGM_GST_TYPE == PGM_TYPE_PAE \
2439 || PGM_GST_TYPE == PGM_TYPE_AMD64) \
2440 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
2441 && PGM_SHW_TYPE != PGM_TYPE_EPT
2442
2443 int rc = VINF_SUCCESS;
2444
2445 /*
2446 * Validate input a little bit.
2447 */
2448 AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2449# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2450 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2451 PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2452
2453 /* Fetch the pgm pool shadow descriptor. */
2454 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2455 Assert(pShwPde);
2456
2457# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2458 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2459 PPGMPOOLPAGE pShwPde = NULL;
2460 PX86PDPAE pPDDst;
2461 PSHWPDE pPdeDst;
2462
2463 /* Fetch the pgm pool shadow descriptor. */
2464 rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2465 AssertRCSuccessReturn(rc, rc);
2466 Assert(pShwPde);
2467
2468 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2469 pPdeDst = &pPDDst->a[iPDDst];
2470
2471# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2472 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2473 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2474 PX86PDPAE pPDDst;
2475 PX86PDPT pPdptDst;
2476 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2477 AssertRCSuccessReturn(rc, rc);
2478 Assert(pPDDst);
2479 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2480# endif
2481 SHWPDE PdeDst = *pPdeDst;
2482
2483# if PGM_GST_TYPE == PGM_TYPE_AMD64
2484 /* Fetch the pgm pool shadow descriptor. */
2485 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2486 Assert(pShwPde);
2487# endif
2488
2489# ifndef PGM_WITHOUT_MAPPINGS
2490 /*
2491 * Check for conflicts.
2492 * GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2493 * HC: Simply resolve the conflict.
2494 */
2495 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2496 {
2497 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2498# ifndef IN_RING3
2499 Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2500 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2501 return VERR_ADDRESS_CONFLICT;
2502# else
2503 PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2504 Assert(pMapping);
2505# if PGM_GST_TYPE == PGM_TYPE_32BIT
2506 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2507# elif PGM_GST_TYPE == PGM_TYPE_PAE
2508 int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2509# else
2510 AssertFailed(); /* can't happen for amd64 */
2511# endif
2512 if (RT_FAILURE(rc))
2513 {
2514 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2515 return rc;
2516 }
2517 PdeDst = *pPdeDst;
2518# endif
2519 }
2520# else /* PGM_WITHOUT_MAPPINGS */
2521 Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2522# endif /* PGM_WITHOUT_MAPPINGS */
2523 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2524
2525# if defined(IN_RC)
2526 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2527 PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2528# endif
2529
2530 /*
2531 * Sync page directory entry.
2532 */
2533 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2534 if (PdeSrc.n.u1Present)
2535 {
2536 /*
2537 * Allocate & map the page table.
2538 */
2539 PSHWPT pPTDst;
2540# if PGM_GST_TYPE == PGM_TYPE_AMD64
2541 const bool fPageTable = !PdeSrc.b.u1Size;
2542# else
2543 const bool fPageTable = !PdeSrc.b.u1Size || !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2544# endif
2545 PPGMPOOLPAGE pShwPage;
2546 RTGCPHYS GCPhys;
2547 if (fPageTable)
2548 {
2549 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2550# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2551 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2552 GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
2553# endif
2554 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2555 }
2556 else
2557 {
2558 GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2559# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2560 /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2561 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2562# endif
2563 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2564 }
2565 if (rc == VINF_SUCCESS)
2566 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2567 else if (rc == VINF_PGM_CACHED_PAGE)
2568 {
2569 /*
2570 * The PT was cached, just hook it up.
2571 */
2572 if (fPageTable)
2573 PdeDst.u = pShwPage->Core.Key
2574 | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2575 else
2576 {
2577 PdeDst.u = pShwPage->Core.Key
2578 | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2579 /* (see explanation and assumptions further down.) */
2580 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2581 {
2582 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2583 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2584 PdeDst.b.u1Write = 0;
2585 }
2586 }
2587 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2588# if defined(IN_RC)
2589 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2590# endif
2591 return VINF_SUCCESS;
2592 }
2593 else if (rc == VERR_PGM_POOL_FLUSHED)
2594 {
2595 VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2596# if defined(IN_RC)
2597 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2598# endif
2599 return VINF_PGM_SYNC_CR3;
2600 }
2601 else
2602 AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2603 PdeDst.u &= X86_PDE_AVL_MASK;
2604 PdeDst.u |= pShwPage->Core.Key;
2605
2606 /*
2607 * Page directory has been accessed (this is a fault situation, remember).
2608 */
2609 pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2610 if (fPageTable)
2611 {
2612 /*
2613 * Page table - 4KB.
2614 *
2615 * Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2616 */
2617 Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2618 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2619 PGSTPT pPTSrc;
2620 rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2621 if (RT_SUCCESS(rc))
2622 {
2623 /*
2624 * Start by syncing the page directory entry so CSAM's TLB trick works.
2625 */
2626 PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | X86_PDE_AVL_MASK))
2627 | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2628 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2629# if defined(IN_RC)
2630 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2631# endif
2632
2633 /*
2634 * Directory/page user or supervisor privilege: (same goes for read/write)
2635 *
2636 * Directory Page Combined
2637 * U/S U/S U/S
2638 * 0 0 0
2639 * 0 1 0
2640 * 1 0 0
2641 * 1 1 1
2642 *
2643 * Simple AND operation. Table listed for completeness.
2644 *
2645 */
2646 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2647# ifdef PGM_SYNC_N_PAGES
2648 unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2649 unsigned iPTDst = iPTBase;
2650 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2651 if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2652 iPTDst = 0;
2653 else
2654 iPTDst -= PGM_SYNC_NR_PAGES / 2;
2655# else /* !PGM_SYNC_N_PAGES */
2656 unsigned iPTDst = 0;
2657 const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2658# endif /* !PGM_SYNC_N_PAGES */
2659# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2660 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2661 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2662# else
2663 const unsigned offPTSrc = 0;
2664# endif
2665 for (; iPTDst < iPTDstEnd; iPTDst++)
2666 {
2667 const unsigned iPTSrc = iPTDst + offPTSrc;
2668 const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2669
2670 if (PteSrc.n.u1Present) /* we've already cleared it above */
2671 {
2672# ifndef IN_RING0
2673 /*
2674 * Assuming kernel code will be marked as supervisor - and not as user level
2675 * and executed using a conforming code selector - And marked as readonly.
2676 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
2677 */
2678 PPGMPAGE pPage;
2679 if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW | X86_PTE_US))
2680 || !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)))
2681 || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2682 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2683 )
2684# endif
2685 PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2686 Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2687 (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)),
2688 PteSrc.n.u1Present,
2689 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2690 PteSrc.n.u1User & PdeSrc.n.u1User,
2691 (uint64_t)PteSrc.u,
2692 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2693 (RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2694 }
2695 } /* for PTEs */
2696 }
2697 }
2698 else
2699 {
2700 /*
2701 * Big page - 2/4MB.
2702 *
2703 * We'll walk the ram range list in parallel and optimize lookups.
2704 * We will only sync on shadow page table at a time.
2705 */
2706 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2707
2708 /**
2709 * @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2710 */
2711
2712 /*
2713 * Start by syncing the page directory entry.
2714 */
2715 PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK | (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2716 | (PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2717
2718 /*
2719 * If the page is not flagged as dirty and is writable, then make it read-only
2720 * at PD level, so we can set the dirty bit when the page is modified.
2721 *
2722 * ASSUMES that page access handlers are implemented on page table entry level.
2723 * Thus we will first catch the dirty access and set PDE.D and restart. If
2724 * there is an access handler, we'll trap again and let it work on the problem.
2725 */
2726 /** @todo move the above stuff to a section in the PGM documentation. */
2727 Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2728 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2729 {
2730 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2731 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2732 PdeDst.b.u1Write = 0;
2733 }
2734 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2735# if defined(IN_RC)
2736 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2737# endif
2738
2739 /*
2740 * Fill the shadow page table.
2741 */
2742 /* Get address and flags from the source PDE. */
2743 SHWPTE PteDstBase;
2744 PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
2745
2746 /* Loop thru the entries in the shadow PT. */
2747 const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2748 Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2749 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2750 GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2751 PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2752 unsigned iPTDst = 0;
2753 while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2754 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2755 {
2756 /* Advance ram range list. */
2757 while (pRam && GCPhys > pRam->GCPhysLast)
2758 pRam = pRam->CTX_SUFF(pNext);
2759 if (pRam && GCPhys >= pRam->GCPhys)
2760 {
2761 unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2762 do
2763 {
2764 /* Make shadow PTE. */
2765 PPGMPAGE pPage = &pRam->aPages[iHCPage];
2766 SHWPTE PteDst;
2767
2768# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2769 /* Try make the page writable if necessary. */
2770 if ( PteDstBase.n.u1Write
2771 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2772 && PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2773 {
2774 rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2775 AssertRCReturn(rc, rc);
2776 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2777 break;
2778 }
2779# endif
2780
2781 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2782 {
2783 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2784 {
2785 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
2786 PteDst.n.u1Write = 0;
2787 }
2788 else
2789 PteDst.u = 0;
2790 }
2791# ifndef IN_RING0
2792 /*
2793 * Assuming kernel code will be marked as supervisor and not as user level and executed
2794 * using a conforming code selector. Don't check for readonly, as that implies the whole
2795 * 4MB can be code or readonly data. Linux enables write access for its large pages.
2796 */
2797 else if ( !PdeSrc.n.u1User
2798 && CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))))
2799 PteDst.u = 0;
2800# endif
2801 else
2802 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
2803
2804 /* Only map writable pages writable. */
2805 if ( PteDst.n.u1Write
2806 && PteDst.n.u1Present
2807 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2808 {
2809 PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2810 Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))));
2811 }
2812
2813# ifdef PGMPOOL_WITH_USER_TRACKING
2814 if (PteDst.n.u1Present)
2815 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2816# endif
2817 /* commit it */
2818 pPTDst->a[iPTDst] = PteDst;
2819 Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2820 (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2821 PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2822
2823 /* advance */
2824 GCPhys += PAGE_SIZE;
2825 iHCPage++;
2826 iPTDst++;
2827 } while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2828 && GCPhys <= pRam->GCPhysLast);
2829 }
2830 else if (pRam)
2831 {
2832 Log(("Invalid pages at %RGp\n", GCPhys));
2833 do
2834 {
2835 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2836 GCPhys += PAGE_SIZE;
2837 iPTDst++;
2838 } while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2839 && GCPhys < pRam->GCPhys);
2840 }
2841 else
2842 {
2843 Log(("Invalid pages at %RGp (2)\n", GCPhys));
2844 for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2845 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2846 }
2847 } /* while more PTEs */
2848 } /* 4KB / 4MB */
2849 }
2850 else
2851 AssertRelease(!PdeDst.n.u1Present);
2852
2853 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2854 if (RT_FAILURE(rc))
2855 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2856 return rc;
2857
2858#elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
2859 && PGM_SHW_TYPE != PGM_TYPE_NESTED \
2860 && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
2861 && !defined(IN_RC)
2862
2863 /*
2864 * Validate input a little bit.
2865 */
2866 int rc = VINF_SUCCESS;
2867# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2868 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2869 PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2870
2871 /* Fetch the pgm pool shadow descriptor. */
2872 PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2873 Assert(pShwPde);
2874
2875# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2876 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2877 PPGMPOOLPAGE pShwPde;
2878 PX86PDPAE pPDDst;
2879 PSHWPDE pPdeDst;
2880
2881 /* Fetch the pgm pool shadow descriptor. */
2882 rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2883 AssertRCSuccessReturn(rc, rc);
2884 Assert(pShwPde);
2885
2886 pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2887 pPdeDst = &pPDDst->a[iPDDst];
2888
2889# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2890 const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2891 const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2892 PX86PDPAE pPDDst;
2893 PX86PDPT pPdptDst;
2894 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2895 AssertRCSuccessReturn(rc, rc);
2896 Assert(pPDDst);
2897 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2898
2899 /* Fetch the pgm pool shadow descriptor. */
2900 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2901 Assert(pShwPde);
2902
2903# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2904 const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2905 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2906 PEPTPD pPDDst;
2907 PEPTPDPT pPdptDst;
2908
2909 rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2910 if (rc != VINF_SUCCESS)
2911 {
2912 AssertRC(rc);
2913 return rc;
2914 }
2915 Assert(pPDDst);
2916 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2917
2918 /* Fetch the pgm pool shadow descriptor. */
2919 PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2920 Assert(pShwPde);
2921# endif
2922 SHWPDE PdeDst = *pPdeDst;
2923
2924 Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2925 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2926
2927 GSTPDE PdeSrc;
2928 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2929 PdeSrc.n.u1Present = 1;
2930 PdeSrc.n.u1Write = 1;
2931 PdeSrc.n.u1Accessed = 1;
2932 PdeSrc.n.u1User = 1;
2933
2934 /*
2935 * Allocate & map the page table.
2936 */
2937 PSHWPT pPTDst;
2938 PPGMPOOLPAGE pShwPage;
2939 RTGCPHYS GCPhys;
2940
2941 /* Virtual address = physical address */
2942 GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2943 rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2944
2945 if ( rc == VINF_SUCCESS
2946 || rc == VINF_PGM_CACHED_PAGE)
2947 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2948 else
2949 AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2950
2951 PdeDst.u &= X86_PDE_AVL_MASK;
2952 PdeDst.u |= pShwPage->Core.Key;
2953 PdeDst.n.u1Present = 1;
2954 PdeDst.n.u1Write = 1;
2955# if PGM_SHW_TYPE == PGM_TYPE_EPT
2956 PdeDst.n.u1Execute = 1;
2957# else
2958 PdeDst.n.u1User = 1;
2959 PdeDst.n.u1Accessed = 1;
2960# endif
2961 ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2962
2963 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2964 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2965 return rc;
2966
2967#else
2968 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2969 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2970 return VERR_INTERNAL_ERROR;
2971#endif
2972}
2973
2974
2975
2976/**
2977 * Prefetch a page/set of pages.
2978 *
2979 * Typically used to sync commonly used pages before entering raw mode
2980 * after a CR3 reload.
2981 *
2982 * @returns VBox status code.
2983 * @param pVCpu The VMCPU handle.
2984 * @param GCPtrPage Page to invalidate.
2985 */
2986PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
2987{
2988#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64) \
2989 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2990 /*
2991 * Check that all Guest levels thru the PDE are present, getting the
2992 * PD and PDE in the processes.
2993 */
2994 int rc = VINF_SUCCESS;
2995# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2996# if PGM_GST_TYPE == PGM_TYPE_32BIT
2997 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2998 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
2999# elif PGM_GST_TYPE == PGM_TYPE_PAE
3000 unsigned iPDSrc;
3001 X86PDPE PdpeSrc;
3002 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3003 if (!pPDSrc)
3004 return VINF_SUCCESS; /* not present */
3005# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3006 unsigned iPDSrc;
3007 PX86PML4E pPml4eSrc;
3008 X86PDPE PdpeSrc;
3009 PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3010 if (!pPDSrc)
3011 return VINF_SUCCESS; /* not present */
3012# endif
3013 const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3014# else
3015 PGSTPD pPDSrc = NULL;
3016 const unsigned iPDSrc = 0;
3017 GSTPDE PdeSrc;
3018
3019 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3020 PdeSrc.n.u1Present = 1;
3021 PdeSrc.n.u1Write = 1;
3022 PdeSrc.n.u1Accessed = 1;
3023 PdeSrc.n.u1User = 1;
3024# endif
3025
3026 if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3027 {
3028 PVM pVM = pVCpu->CTX_SUFF(pVM);
3029 pgmLock(pVM);
3030
3031# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3032 const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3033# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3034 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3035 PX86PDPAE pPDDst;
3036 X86PDEPAE PdeDst;
3037# if PGM_GST_TYPE != PGM_TYPE_PAE
3038 X86PDPE PdpeSrc;
3039
3040 /* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3041 PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3042# endif
3043 int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3044 if (rc != VINF_SUCCESS)
3045 {
3046 pgmUnlock(pVM);
3047 AssertRC(rc);
3048 return rc;
3049 }
3050 Assert(pPDDst);
3051 PdeDst = pPDDst->a[iPDDst];
3052
3053# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3054 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3055 PX86PDPAE pPDDst;
3056 X86PDEPAE PdeDst;
3057
3058# if PGM_GST_TYPE == PGM_TYPE_PROT
3059 /* AMD-V nested paging */
3060 X86PML4E Pml4eSrc;
3061 X86PDPE PdpeSrc;
3062 PX86PML4E pPml4eSrc = &Pml4eSrc;
3063
3064 /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3065 Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
3066 PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
3067# endif
3068
3069 int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3070 if (rc != VINF_SUCCESS)
3071 {
3072 pgmUnlock(pVM);
3073 AssertRC(rc);
3074 return rc;
3075 }
3076 Assert(pPDDst);
3077 PdeDst = pPDDst->a[iPDDst];
3078# endif
3079 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3080 {
3081 if (!PdeDst.n.u1Present)
3082 {
3083 /** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3084 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3085 }
3086 else
3087 {
3088 /** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3089 * R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3090 * makes no sense to prefetch more than one page.
3091 */
3092 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3093 if (RT_SUCCESS(rc))
3094 rc = VINF_SUCCESS;
3095 }
3096 }
3097 pgmUnlock(pVM);
3098 }
3099 return rc;
3100
3101#elif PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
3102 return VINF_SUCCESS; /* ignore */
3103#endif
3104}
3105
3106
3107
3108
3109/**
3110 * Syncs a page during a PGMVerifyAccess() call.
3111 *
3112 * @returns VBox status code (informational included).
3113 * @param pVCpu The VMCPU handle.
3114 * @param GCPtrPage The address of the page to sync.
3115 * @param fPage The effective guest page flags.
3116 * @param uErr The trap error code.
3117 */
3118PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3119{
3120 PVM pVM = pVCpu->CTX_SUFF(pVM);
3121
3122 LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3123
3124 Assert(!HWACCMIsNestedPagingActive(pVM));
3125#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_TYPE_AMD64) \
3126 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3127
3128# ifndef IN_RING0
3129 if (!(fPage & X86_PTE_US))
3130 {
3131 /*
3132 * Mark this page as safe.
3133 */
3134 /** @todo not correct for pages that contain both code and data!! */
3135 Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3136 CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3137 }
3138# endif
3139
3140 /*
3141 * Get guest PD and index.
3142 */
3143# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3144# if PGM_GST_TYPE == PGM_TYPE_32BIT
3145 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3146 PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3147# elif PGM_GST_TYPE == PGM_TYPE_PAE
3148 unsigned iPDSrc = 0;
3149 X86PDPE PdpeSrc;
3150 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3151
3152 if (pPDSrc)
3153 {
3154 Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3155 return VINF_EM_RAW_GUEST_TRAP;
3156 }
3157# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3158 unsigned iPDSrc;
3159 PX86PML4E pPml4eSrc;
3160 X86PDPE PdpeSrc;
3161 PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3162 if (!pPDSrc)
3163 {
3164 Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3165 return VINF_EM_RAW_GUEST_TRAP;
3166 }
3167# endif
3168# else
3169 PGSTPD pPDSrc = NULL;
3170 const unsigned iPDSrc = 0;
3171# endif
3172 int rc = VINF_SUCCESS;
3173
3174 pgmLock(pVM);
3175
3176 /*
3177 * First check if the shadow pd is present.
3178 */
3179# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3180 PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3181# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3182 PX86PDEPAE pPdeDst;
3183 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3184 PX86PDPAE pPDDst;
3185# if PGM_GST_TYPE != PGM_TYPE_PAE
3186 X86PDPE PdpeSrc;
3187
3188 /* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3189 PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3190# endif
3191 rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3192 if (rc != VINF_SUCCESS)
3193 {
3194 pgmUnlock(pVM);
3195 AssertRC(rc);
3196 return rc;
3197 }
3198 Assert(pPDDst);
3199 pPdeDst = &pPDDst->a[iPDDst];
3200
3201# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3202 const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3203 PX86PDPAE pPDDst;
3204 PX86PDEPAE pPdeDst;
3205
3206# if PGM_GST_TYPE == PGM_TYPE_PROT
3207 /* AMD-V nested paging */
3208 X86PML4E Pml4eSrc;
3209 X86PDPE PdpeSrc;
3210 PX86PML4E pPml4eSrc = &Pml4eSrc;
3211
3212 /* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3213 Pml4eSrc.u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_NX | X86_PML4E_A;
3214 PdpeSrc.u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_NX | X86_PDPE_A;
3215# endif
3216
3217 rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3218 if (rc != VINF_SUCCESS)
3219 {
3220 pgmUnlock(pVM);
3221 AssertRC(rc);
3222 return rc;
3223 }
3224 Assert(pPDDst);
3225 pPdeDst = &pPDDst->a[iPDDst];
3226# endif
3227
3228# if defined(IN_RC)
3229 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3230 PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3231# endif
3232
3233 if (!pPdeDst->n.u1Present)
3234 {
3235 rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3236 if (rc != VINF_SUCCESS)
3237 {
3238# if defined(IN_RC)
3239 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3240 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3241# endif
3242 pgmUnlock(pVM);
3243 AssertRC(rc);
3244 return rc;
3245 }
3246 }
3247
3248# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3249 /* Check for dirty bit fault */
3250 rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3251 if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3252 Log(("PGMVerifyAccess: success (dirty)\n"));
3253 else
3254 {
3255 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3256# else
3257 {
3258 GSTPDE PdeSrc;
3259 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3260 PdeSrc.n.u1Present = 1;
3261 PdeSrc.n.u1Write = 1;
3262 PdeSrc.n.u1Accessed = 1;
3263 PdeSrc.n.u1User = 1;
3264
3265# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3266 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3267 if (uErr & X86_TRAP_PF_US)
3268 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3269 else /* supervisor */
3270 STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3271
3272 rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3273 if (RT_SUCCESS(rc))
3274 {
3275 /* Page was successfully synced */
3276 Log2(("PGMVerifyAccess: success (sync)\n"));
3277 rc = VINF_SUCCESS;
3278 }
3279 else
3280 {
3281 Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3282 rc = VINF_EM_RAW_GUEST_TRAP;
3283 }
3284 }
3285# if defined(IN_RC)
3286 /* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3287 PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3288# endif
3289 pgmUnlock(pVM);
3290 return rc;
3291
3292#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3293
3294 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3295 return VERR_INTERNAL_ERROR;
3296#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3297}
3298
3299
3300#if PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
3301# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
3302/**
3303 * Figures out which kind of shadow page this guest PDE warrants.
3304 *
3305 * @returns Shadow page kind.
3306 * @param pPdeSrc The guest PDE in question.
3307 * @param cr4 The current guest cr4 value.
3308 */
3309DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3310{
3311# if PMG_GST_TYPE == PGM_TYPE_AMD64
3312 if (!pPdeSrc->n.u1Size)
3313# else
3314 if (!pPdeSrc->n.u1Size || !(cr4 & X86_CR4_PSE))
3315# endif
3316 return BTH_PGMPOOLKIND_PT_FOR_PT;
3317 //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/))
3318 //{
3319 // case 0:
3320 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3321 // case X86_PDE4M_RW:
3322 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3323 // case X86_PDE4M_US:
3324 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3325 // case X86_PDE4M_RW | X86_PDE4M_US:
3326 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3327# if 0
3328 // case X86_PDE4M_PAE_NX:
3329 // return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3330 // case X86_PDE4M_RW | X86_PDE4M_PAE_NX:
3331 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3332 // case X86_PDE4M_US | X86_PDE4M_PAE_NX:
3333 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3334 // case X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PAE_NX:
3335 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3336# endif
3337 return BTH_PGMPOOLKIND_PT_FOR_BIG;
3338 //}
3339}
3340# endif
3341#endif
3342
3343#undef MY_STAM_COUNTER_INC
3344#define MY_STAM_COUNTER_INC(a) do { } while (0)
3345
3346
3347/**
3348 * Syncs the paging hierarchy starting at CR3.
3349 *
3350 * @returns VBox status code, no specials.
3351 * @param pVCpu The VMCPU handle.
3352 * @param cr0 Guest context CR0 register
3353 * @param cr3 Guest context CR3 register
3354 * @param cr4 Guest context CR4 register
3355 * @param fGlobal Including global page directories or not
3356 */
3357PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3358{
3359 PVM pVM = pVCpu->CTX_SUFF(pVM);
3360
3361 if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3362 fGlobal = true; /* Change this CR3 reload to be a global one. */
3363
3364 LogFlow(("SyncCR3 %d\n", fGlobal));
3365
3366#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3367 /*
3368 * Update page access handlers.
3369 * The virtual are always flushed, while the physical are only on demand.
3370 * WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3371 * have to look into that later because it will have a bad influence on the performance.
3372 * @note SvL: There's no need for that. Just invalidate the virtual range(s).
3373 * bird: Yes, but that won't work for aliases.
3374 */
3375 /** @todo this MUST go away. See #1557. */
3376 STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3377 PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3378 STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3379#endif
3380
3381#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
3382 /*
3383 * Nested / EPT - almost no work.
3384 */
3385 /** @todo check if this is really necessary; the call does it as well... */
3386 HWACCMFlushTLB(pVM);
3387 return VINF_SUCCESS;
3388
3389#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3390 /*
3391 * AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3392 * out the shadow parts when the guest modifies its tables.
3393 */
3394 return VINF_SUCCESS;
3395
3396#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3397
3398# ifdef PGM_WITHOUT_MAPPINGS
3399 Assert(pVM->pgm.s.fMappingsFixed);
3400 return VINF_SUCCESS;
3401# else
3402 /* Nothing to do when mappings are fixed. */
3403 if (pVM->pgm.s.fMappingsFixed)
3404 return VINF_SUCCESS;
3405
3406 int rc = PGMMapResolveConflicts(pVM);
3407 Assert(rc == VINF_SUCCESS || rc == VINF_PGM_SYNC_CR3);
3408 if (rc == VINF_PGM_SYNC_CR3)
3409 {
3410 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3411 return VINF_PGM_SYNC_CR3;
3412 }
3413# endif
3414 return VINF_SUCCESS;
3415#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3416}
3417
3418
3419
3420
3421#ifdef VBOX_STRICT
3422#ifdef IN_RC
3423# undef AssertMsgFailed
3424# define AssertMsgFailed Log
3425#endif
3426#ifdef IN_RING3
3427# include <VBox/dbgf.h>
3428
3429/**
3430 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3431 *
3432 * @returns VBox status code (VINF_SUCCESS).
3433 * @param cr3 The root of the hierarchy.
3434 * @param crr The cr4, only PAE and PSE is currently used.
3435 * @param fLongMode Set if long mode, false if not long mode.
3436 * @param cMaxDepth Number of levels to dump.
3437 * @param pHlp Pointer to the output functions.
3438 */
3439__BEGIN_DECLS
3440VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3441__END_DECLS
3442
3443#endif
3444
3445/**
3446 * Checks that the shadow page table is in sync with the guest one.
3447 *
3448 * @returns The number of errors.
3449 * @param pVM The virtual machine.
3450 * @param pVCpu The VMCPU handle.
3451 * @param cr3 Guest context CR3 register
3452 * @param cr4 Guest context CR4 register
3453 * @param GCPtr Where to start. Defaults to 0.
3454 * @param cb How much to check. Defaults to everything.
3455 */
3456PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3457{
3458#if PGM_SHW_TYPE == PGM_TYPE_NESTED || PGM_SHW_TYPE == PGM_TYPE_EPT
3459 return 0;
3460#else
3461 unsigned cErrors = 0;
3462 PVM pVM = pVCpu->CTX_SUFF(pVM);
3463 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3464
3465#if PGM_GST_TYPE == PGM_TYPE_PAE
3466 /** @todo currently broken; crashes below somewhere */
3467 AssertFailed();
3468#endif
3469
3470#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3471 || PGM_GST_TYPE == PGM_TYPE_PAE \
3472 || PGM_GST_TYPE == PGM_TYPE_AMD64
3473
3474# if PGM_GST_TYPE == PGM_TYPE_AMD64
3475 bool fBigPagesSupported = true;
3476# else
3477 bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3478# endif
3479 PPGMCPU pPGM = &pVCpu->pgm.s;
3480 RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3481 RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3482# ifndef IN_RING0
3483 RTHCPHYS HCPhys; /* general usage. */
3484# endif
3485 int rc;
3486
3487 /*
3488 * Check that the Guest CR3 and all its mappings are correct.
3489 */
3490 AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3491 ("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3492 false);
3493# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3494# if PGM_GST_TYPE == PGM_TYPE_32BIT
3495 rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3496# else
3497 rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3498# endif
3499 AssertRCReturn(rc, 1);
3500 HCPhys = NIL_RTHCPHYS;
3501 rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3502 AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3503# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3504 pgmGstGet32bitPDPtr(pPGM);
3505 RTGCPHYS GCPhys;
3506 rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3507 AssertRCReturn(rc, 1);
3508 AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3509# endif
3510# endif /* !IN_RING0 */
3511
3512 /*
3513 * Get and check the Shadow CR3.
3514 */
3515# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3516 unsigned cPDEs = X86_PG_ENTRIES;
3517 unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3518# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3519# if PGM_GST_TYPE == PGM_TYPE_32BIT
3520 unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3521# else
3522 unsigned cPDEs = X86_PG_PAE_ENTRIES;
3523# endif
3524 unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3525# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3526 unsigned cPDEs = X86_PG_PAE_ENTRIES;
3527 unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3528# endif
3529 if (cb != ~(RTGCPTR)0)
3530 cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3531
3532/** @todo call the other two PGMAssert*() functions. */
3533
3534# if PGM_GST_TYPE == PGM_TYPE_AMD64
3535 unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3536
3537 for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3538 {
3539 PPGMPOOLPAGE pShwPdpt = NULL;
3540 PX86PML4E pPml4eSrc;
3541 PX86PML4E pPml4eDst;
3542 RTGCPHYS GCPhysPdptSrc;
3543
3544 pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3545 pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3546
3547 /* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3548 if (!pPml4eDst->n.u1Present)
3549 {
3550 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3551 continue;
3552 }
3553
3554 pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3555 GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3556
3557 if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3558 {
3559 AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3560 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3561 cErrors++;
3562 continue;
3563 }
3564
3565 if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3566 {
3567 AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3568 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3569 cErrors++;
3570 continue;
3571 }
3572
3573 if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3574 || pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3575 || pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3576 {
3577 AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3578 GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3579 cErrors++;
3580 continue;
3581 }
3582# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3583 {
3584# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3585
3586# if PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_GST_TYPE == PGM_TYPE_PAE
3587 /*
3588 * Check the PDPTEs too.
3589 */
3590 unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3591
3592 for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3593 {
3594 unsigned iPDSrc;
3595 PPGMPOOLPAGE pShwPde = NULL;
3596 PX86PDPE pPdpeDst;
3597 RTGCPHYS GCPhysPdeSrc;
3598# if PGM_GST_TYPE == PGM_TYPE_PAE
3599 X86PDPE PdpeSrc;
3600 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3601 PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3602# else
3603 PX86PML4E pPml4eSrc;
3604 X86PDPE PdpeSrc;
3605 PX86PDPT pPdptDst;
3606 PX86PDPAE pPDDst;
3607 PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3608
3609 rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3610 if (rc != VINF_SUCCESS)
3611 {
3612 AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3613 GCPtr += 512 * _2M;
3614 continue; /* next PDPTE */
3615 }
3616 Assert(pPDDst);
3617# endif
3618 Assert(iPDSrc == 0);
3619
3620 pPdpeDst = &pPdptDst->a[iPdpt];
3621
3622 if (!pPdpeDst->n.u1Present)
3623 {
3624 GCPtr += 512 * _2M;
3625 continue; /* next PDPTE */
3626 }
3627
3628 pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3629 GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3630
3631 if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3632 {
3633 AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3634 GCPtr += 512 * _2M;
3635 cErrors++;
3636 continue;
3637 }
3638
3639 if (GCPhysPdeSrc != pShwPde->GCPhys)
3640 {
3641# if PGM_GST_TYPE == PGM_TYPE_AMD64
3642 AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3643# else
3644 AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3645# endif
3646 GCPtr += 512 * _2M;
3647 cErrors++;
3648 continue;
3649 }
3650
3651# if PGM_GST_TYPE == PGM_TYPE_AMD64
3652 if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3653 || pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3654 || pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3655 {
3656 AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3657 GCPtr += 512 * _2M;
3658 cErrors++;
3659 continue;
3660 }
3661# endif
3662
3663# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3664 {
3665# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3666# if PGM_GST_TYPE == PGM_TYPE_32BIT
3667 GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3668# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3669 PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3670# endif
3671# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3672 /*
3673 * Iterate the shadow page directory.
3674 */
3675 GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3676 unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3677
3678 for (;
3679 iPDDst < cPDEs;
3680 iPDDst++, GCPtr += cIncrement)
3681 {
3682# if PGM_SHW_TYPE == PGM_TYPE_PAE
3683 const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3684# else
3685 const SHWPDE PdeDst = pPDDst->a[iPDDst];
3686# endif
3687 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3688 {
3689 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3690 if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3691 {
3692 AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3693 cErrors++;
3694 continue;
3695 }
3696 }
3697 else if ( (PdeDst.u & X86_PDE_P)
3698 || ((PdeDst.u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
3699 )
3700 {
3701 HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3702 PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3703 if (!pPoolPage)
3704 {
3705 AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3706 HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3707 cErrors++;
3708 continue;
3709 }
3710 const SHWPT *pPTDst = (const SHWPT *)PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3711
3712 if (PdeDst.u & (X86_PDE4M_PWT | X86_PDE4M_PCD))
3713 {
3714 AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3715 GCPtr, (uint64_t)PdeDst.u));
3716 cErrors++;
3717 }
3718
3719 if (PdeDst.u & (X86_PDE4M_G | X86_PDE4M_D))
3720 {
3721 AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3722 GCPtr, (uint64_t)PdeDst.u));
3723 cErrors++;
3724 }
3725
3726 const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3727 if (!PdeSrc.n.u1Present)
3728 {
3729 AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3730 GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3731 cErrors++;
3732 continue;
3733 }
3734
3735 if ( !PdeSrc.b.u1Size
3736 || !fBigPagesSupported)
3737 {
3738 GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3739# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3740 GCPhysGst |= (iPDDst & 1) * (PAGE_SIZE / 2);
3741# endif
3742 }
3743 else
3744 {
3745# if PGM_GST_TYPE == PGM_TYPE_32BIT
3746 if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3747 {
3748 AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3749 GCPtr, (uint64_t)PdeSrc.u));
3750 cErrors++;
3751 continue;
3752 }
3753# endif
3754 GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3755# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3756 GCPhysGst |= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3757# endif
3758 }
3759
3760 if ( pPoolPage->enmKind
3761 != (!PdeSrc.b.u1Size || !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3762 {
3763 AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3764 pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3765 cErrors++;
3766 }
3767
3768 PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3769 if (!pPhysPage)
3770 {
3771 AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3772 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3773 cErrors++;
3774 continue;
3775 }
3776
3777 if (GCPhysGst != pPoolPage->GCPhys)
3778 {
3779 AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3780 GCPhysGst, pPoolPage->GCPhys, GCPtr));
3781 cErrors++;
3782 continue;
3783 }
3784
3785 if ( !PdeSrc.b.u1Size
3786 || !fBigPagesSupported)
3787 {
3788 /*
3789 * Page Table.
3790 */
3791 const GSTPT *pPTSrc;
3792 rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3793 if (RT_FAILURE(rc))
3794 {
3795 AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3796 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3797 cErrors++;
3798 continue;
3799 }
3800 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/))
3801 != (PdeDst.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/)))
3802 {
3803 /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3804 // (This problem will go away when/if we shadow multiple CR3s.)
3805 AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3806 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3807 cErrors++;
3808 continue;
3809 }
3810 if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3811 {
3812 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3813 GCPtr, (uint64_t)PdeDst.u));
3814 cErrors++;
3815 continue;
3816 }
3817
3818 /* iterate the page table. */
3819# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3820 /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3821 const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3822# else
3823 const unsigned offPTSrc = 0;
3824# endif
3825 for (unsigned iPT = 0, off = 0;
3826 iPT < RT_ELEMENTS(pPTDst->a);
3827 iPT++, off += PAGE_SIZE)
3828 {
3829 const SHWPTE PteDst = pPTDst->a[iPT];
3830
3831 /* skip not-present entries. */
3832 if (!(PteDst.u & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3833 continue;
3834 Assert(PteDst.n.u1Present);
3835
3836 const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3837 if (!PteSrc.n.u1Present)
3838 {
3839# ifdef IN_RING3
3840 PGMAssertHandlerAndFlagsInSync(pVM);
3841 PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3842# endif
3843 AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3844 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3845 (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3846 cErrors++;
3847 continue;
3848 }
3849
3850 uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3851# if 1 /** @todo sync accessed bit properly... */
3852 fIgnoreFlags |= X86_PTE_A;
3853# endif
3854
3855 /* match the physical addresses */
3856 HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3857 GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3858
3859# ifdef IN_RING3
3860 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3861 if (RT_FAILURE(rc))
3862 {
3863 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3864 {
3865 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3866 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3867 cErrors++;
3868 continue;
3869 }
3870 }
3871 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3872 {
3873 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3874 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3875 cErrors++;
3876 continue;
3877 }
3878# endif
3879
3880 pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3881 if (!pPhysPage)
3882 {
3883# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3884 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3885 {
3886 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3887 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3888 cErrors++;
3889 continue;
3890 }
3891# endif
3892 if (PteDst.n.u1Write)
3893 {
3894 AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3895 GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3896 cErrors++;
3897 }
3898 fIgnoreFlags |= X86_PTE_RW;
3899 }
3900 else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3901 {
3902 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3903 GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3904 cErrors++;
3905 continue;
3906 }
3907
3908 /* flags */
3909 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3910 {
3911 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3912 {
3913 if (PteDst.n.u1Write)
3914 {
3915 AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3916 GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3917 cErrors++;
3918 continue;
3919 }
3920 fIgnoreFlags |= X86_PTE_RW;
3921 }
3922 else
3923 {
3924 if (PteDst.n.u1Present)
3925 {
3926 AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3927 GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3928 cErrors++;
3929 continue;
3930 }
3931 fIgnoreFlags |= X86_PTE_P;
3932 }
3933 }
3934 else
3935 {
3936 if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3937 {
3938 if (PteDst.n.u1Write)
3939 {
3940 AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3941 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3942 cErrors++;
3943 continue;
3944 }
3945 if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3946 {
3947 AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3948 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3949 cErrors++;
3950 continue;
3951 }
3952 if (PteDst.n.u1Dirty)
3953 {
3954 AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3955 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3956 cErrors++;
3957 }
3958# if 0 /** @todo sync access bit properly... */
3959 if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3960 {
3961 AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3962 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3963 cErrors++;
3964 }
3965 fIgnoreFlags |= X86_PTE_RW;
3966# else
3967 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3968# endif
3969 }
3970 else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3971 {
3972 /* access bit emulation (not implemented). */
3973 if (PteSrc.n.u1Accessed || PteDst.n.u1Present)
3974 {
3975 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3976 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3977 cErrors++;
3978 continue;
3979 }
3980 if (!PteDst.n.u1Accessed)
3981 {
3982 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3983 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3984 cErrors++;
3985 }
3986 fIgnoreFlags |= X86_PTE_P;
3987 }
3988# ifdef DEBUG_sandervl
3989 fIgnoreFlags |= X86_PTE_D | X86_PTE_A;
3990# endif
3991 }
3992
3993 if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3994 && (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3995 )
3996 {
3997 AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3998 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3999 fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4000 cErrors++;
4001 continue;
4002 }
4003 } /* foreach PTE */
4004 }
4005 else
4006 {
4007 /*
4008 * Big Page.
4009 */
4010 uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | GST_PDE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
4011 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4012 {
4013 if (PdeDst.n.u1Write)
4014 {
4015 AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4016 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4017 cErrors++;
4018 continue;
4019 }
4020 if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4021 {
4022 AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4023 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4024 cErrors++;
4025 continue;
4026 }
4027# if 0 /** @todo sync access bit properly... */
4028 if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4029 {
4030 AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4031 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4032 cErrors++;
4033 }
4034 fIgnoreFlags |= X86_PTE_RW;
4035# else
4036 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
4037# endif
4038 }
4039 else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4040 {
4041 /* access bit emulation (not implemented). */
4042 if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present)
4043 {
4044 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4045 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4046 cErrors++;
4047 continue;
4048 }
4049 if (!PdeDst.n.u1Accessed)
4050 {
4051 AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4052 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4053 cErrors++;
4054 }
4055 fIgnoreFlags |= X86_PTE_P;
4056 }
4057
4058 if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4059 {
4060 AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4061 GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4062 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4063 cErrors++;
4064 }
4065
4066 /* iterate the page table. */
4067 for (unsigned iPT = 0, off = 0;
4068 iPT < RT_ELEMENTS(pPTDst->a);
4069 iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4070 {
4071 const SHWPTE PteDst = pPTDst->a[iPT];
4072
4073 if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4074 {
4075 AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4076 GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4077 cErrors++;
4078 }
4079
4080 /* skip not-present entries. */
4081 if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4082 continue;
4083
4084 fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT | X86_PTE_D | X86_PTE_A | X86_PTE_G | X86_PTE_PAE_NX;
4085
4086 /* match the physical addresses */
4087 HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4088
4089# ifdef IN_RING3
4090 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4091 if (RT_FAILURE(rc))
4092 {
4093 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4094 {
4095 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4096 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4097 cErrors++;
4098 }
4099 }
4100 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4101 {
4102 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4103 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4104 cErrors++;
4105 continue;
4106 }
4107# endif
4108 pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4109 if (!pPhysPage)
4110 {
4111# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4112 if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4113 {
4114 AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4115 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4116 cErrors++;
4117 continue;
4118 }
4119# endif
4120 if (PteDst.n.u1Write)
4121 {
4122 AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4123 GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4124 cErrors++;
4125 }
4126 fIgnoreFlags |= X86_PTE_RW;
4127 }
4128 else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4129 {
4130 AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4131 GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4132 cErrors++;
4133 continue;
4134 }
4135
4136 /* flags */
4137 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4138 {
4139 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4140 {
4141 if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4142 {
4143 if (PteDst.n.u1Write)
4144 {
4145 AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4146 GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4147 cErrors++;
4148 continue;
4149 }
4150 fIgnoreFlags |= X86_PTE_RW;
4151 }
4152 }
4153 else
4154 {
4155 if (PteDst.n.u1Present)
4156 {
4157 AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4158 GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4159 cErrors++;
4160 continue;
4161 }
4162 fIgnoreFlags |= X86_PTE_P;
4163 }
4164 }
4165
4166 if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4167 && (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4168 )
4169 {
4170 AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4171 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4172 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4173 cErrors++;
4174 continue;
4175 }
4176 } /* for each PTE */
4177 }
4178 }
4179 /* not present */
4180
4181 } /* for each PDE */
4182
4183 } /* for each PDPTE */
4184
4185 } /* for each PML4E */
4186
4187# ifdef DEBUG
4188 if (cErrors)
4189 LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4190# endif
4191
4192#endif /* GST == 32BIT, PAE or AMD64 */
4193 return cErrors;
4194
4195#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4196}
4197#endif /* VBOX_STRICT */
4198
4199
4200/**
4201 * Sets up the CR3 for shadow paging
4202 *
4203 * @returns Strict VBox status code.
4204 * @retval VINF_SUCCESS.
4205 *
4206 * @param pVCpu The VMCPU handle.
4207 * @param GCPhysCR3 The physical address in the CR3 register.
4208 */
4209PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4210{
4211 PVM pVM = pVCpu->CTX_SUFF(pVM);
4212
4213 /* Update guest paging info. */
4214#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4215 || PGM_GST_TYPE == PGM_TYPE_PAE \
4216 || PGM_GST_TYPE == PGM_TYPE_AMD64
4217
4218 LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4219
4220 /*
4221 * Map the page CR3 points at.
4222 */
4223 RTHCPTR HCPtrGuestCR3;
4224 RTHCPHYS HCPhysGuestCR3;
4225 pgmLock(pVM);
4226 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4227 AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4228 HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4229 /** @todo this needs some reworking wrt. locking. */
4230# if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4231 HCPtrGuestCR3 = NIL_RTHCPTR;
4232 int rc = VINF_SUCCESS;
4233# else
4234 int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4235# endif
4236 pgmUnlock(pVM);
4237 if (RT_SUCCESS(rc))
4238 {
4239 rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4240 if (RT_SUCCESS(rc))
4241 {
4242# ifdef IN_RC
4243 PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4244# endif
4245# if PGM_GST_TYPE == PGM_TYPE_32BIT
4246 pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4247# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4248 pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4249# endif
4250 pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4251
4252# elif PGM_GST_TYPE == PGM_TYPE_PAE
4253 unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4254 pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4255# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4256 pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4257# endif
4258 pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4259 Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4260
4261 /*
4262 * Map the 4 PDs too.
4263 */
4264 PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4265 RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4266 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4267 {
4268 if (pGuestPDPT->a[i].n.u1Present)
4269 {
4270 RTHCPTR HCPtr;
4271 RTHCPHYS HCPhys;
4272 RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4273 pgmLock(pVM);
4274 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4275 AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4276 HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4277# if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4278 HCPtr = NIL_RTHCPTR;
4279 int rc2 = VINF_SUCCESS;
4280# else
4281 int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4282# endif
4283 pgmUnlock(pVM);
4284 if (RT_SUCCESS(rc2))
4285 {
4286 rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4287 AssertRCReturn(rc, rc);
4288
4289 pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4290# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4291 pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4292# endif
4293 pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4294 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4295# ifdef IN_RC
4296 PGM_INVL_PG(GCPtr);
4297# endif
4298 continue;
4299 }
4300 AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4301 }
4302
4303 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4304# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4305 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4306# endif
4307 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4308 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4309# ifdef IN_RC
4310 PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4311# endif
4312 }
4313
4314# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4315 pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4316# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4317 pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4318# endif
4319# endif
4320 }
4321 else
4322 AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4323 }
4324 else
4325 AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4326
4327#else /* prot/real stub */
4328 int rc = VINF_SUCCESS;
4329#endif
4330
4331 /* Update shadow paging info for guest modes with paging (32, pae, 64). */
4332# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4333 || PGM_SHW_TYPE == PGM_TYPE_PAE \
4334 || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4335 && ( PGM_GST_TYPE != PGM_TYPE_REAL \
4336 && PGM_GST_TYPE != PGM_TYPE_PROT))
4337
4338 Assert(!HWACCMIsNestedPagingActive(pVM));
4339
4340 /*
4341 * Update the shadow root page as well since that's not fixed.
4342 */
4343 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4344 PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4345 uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4346 uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4347 PPGMPOOLPAGE pNewShwPageCR3;
4348
4349 Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4350 rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4351 AssertFatalRC(rc);
4352 rc = VINF_SUCCESS;
4353
4354 /* Mark the page as locked; disallow flushing. */
4355 pgmPoolLockPage(pPool, pNewShwPageCR3);
4356
4357# ifdef IN_RC
4358 /* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4359 bool fLog = VMMGCLogDisable(pVM);
4360 pgmLock(pVM);
4361# endif
4362
4363 pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4364 pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4365 pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4366# ifdef IN_RING0
4367 pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4368 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4369# elif defined(IN_RC)
4370 pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4371 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4372# else
4373 pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4374 pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4375# endif
4376
4377# ifndef PGM_WITHOUT_MAPPINGS
4378 /*
4379 * Apply all hypervisor mappings to the new CR3.
4380 * Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4381 * make sure we check for conflicts in the new CR3 root.
4382 */
4383# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4384 Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) || VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4385# endif
4386 rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4387 AssertRCReturn(rc, rc);
4388# endif
4389
4390 /* Set the current hypervisor CR3. */
4391 CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4392 SELMShadowCR3Changed(pVM, pVCpu);
4393
4394# ifdef IN_RC
4395 pgmUnlock(pVM);
4396 VMMGCLogRestore(pVM, fLog);
4397# endif
4398
4399 /* Clean up the old CR3 root. */
4400 if (pOldShwPageCR3)
4401 {
4402 Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4403# ifndef PGM_WITHOUT_MAPPINGS
4404 /* Remove the hypervisor mappings from the shadow page table. */
4405 pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4406# endif
4407 /* Mark the page as unlocked; allow flushing again. */
4408 pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4409
4410 pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4411 }
4412
4413# endif
4414
4415 return rc;
4416}
4417
4418/**
4419 * Unmaps the shadow CR3.
4420 *
4421 * @returns VBox status, no specials.
4422 * @param pVCpu The VMCPU handle.
4423 */
4424PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4425{
4426 LogFlow(("UnmapCR3\n"));
4427
4428 int rc = VINF_SUCCESS;
4429 PVM pVM = pVCpu->CTX_SUFF(pVM);
4430
4431 /*
4432 * Update guest paging info.
4433 */
4434#if PGM_GST_TYPE == PGM_TYPE_32BIT
4435 pVCpu->pgm.s.pGst32BitPdR3 = 0;
4436# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4437 pVCpu->pgm.s.pGst32BitPdR0 = 0;
4438# endif
4439 pVCpu->pgm.s.pGst32BitPdRC = 0;
4440
4441#elif PGM_GST_TYPE == PGM_TYPE_PAE
4442 pVCpu->pgm.s.pGstPaePdptR3 = 0;
4443# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4444 pVCpu->pgm.s.pGstPaePdptR0 = 0;
4445# endif
4446 pVCpu->pgm.s.pGstPaePdptRC = 0;
4447 for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4448 {
4449 pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4450# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4451 pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4452# endif
4453 pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4454 pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4455 }
4456
4457#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4458 pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4459# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4460 pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4461# endif
4462
4463#else /* prot/real mode stub */
4464 /* nothing to do */
4465#endif
4466
4467#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4468 /*
4469 * Update shadow paging info.
4470 */
4471# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4472 || PGM_SHW_TYPE == PGM_TYPE_PAE \
4473 || PGM_SHW_TYPE == PGM_TYPE_AMD64))
4474
4475# if PGM_GST_TYPE != PGM_TYPE_REAL
4476 Assert(!HWACCMIsNestedPagingActive(pVM));
4477# endif
4478
4479# ifndef PGM_WITHOUT_MAPPINGS
4480 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4481 /* Remove the hypervisor mappings from the shadow page table. */
4482 pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4483# endif
4484
4485 if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4486 {
4487 PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4488
4489 Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4490
4491 /* Mark the page as unlocked; allow flushing again. */
4492 pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4493
4494 pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4495 pVCpu->pgm.s.pShwPageCR3R3 = 0;
4496 pVCpu->pgm.s.pShwPageCR3R0 = 0;
4497 pVCpu->pgm.s.pShwPageCR3RC = 0;
4498 pVCpu->pgm.s.iShwUser = 0;
4499 pVCpu->pgm.s.iShwUserTable = 0;
4500 }
4501# endif
4502#endif /* !IN_RC*/
4503
4504 return rc;
4505}
4506
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