PGMAllBth.h@ 19791

Last change on this file since 19791 was 19791, checked in by vboxsync, 16 years ago
Added remark to InvalidatePage about TLB shootdowns.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 193.9 KB

Line
1	/* $Id: PGMAllBth.h 19791 2009-05-18 14:17:26Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc;
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc;
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	pgmLock(pVM);
165	{ /* Force the shadow pointers to go out of scope after releasing the lock. */
166	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
167	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
168	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
169
170	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
171	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
172
173	PX86PDPAE pPDDst;
174	# if PGM_GST_TYPE != PGM_TYPE_PAE
175	X86PDPE PdpeSrc;
176
177	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
178	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
179	# endif
180	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
181	if (rc != VINF_SUCCESS)
182	{
183	pgmUnlock(pVM);
184	AssertRC(rc);
185	return rc;
186	}
187	Assert(pPDDst);
188
189	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
190	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
191	PX86PDPAE pPDDst;
192	# if PGM_GST_TYPE == PGM_TYPE_PROT
193	/* AMD-V nested paging */
194	X86PML4E Pml4eSrc;
195	X86PDPE PdpeSrc;
196	PX86PML4E pPml4eSrc = &Pml4eSrc;
197
198	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
199	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
200	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
201	# endif
202
203	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
204	if (rc != VINF_SUCCESS)
205	{
206	pgmUnlock(pVM);
207	AssertRC(rc);
208	return rc;
209	}
210	Assert(pPDDst);
211
212	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
213	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
214	PEPTPD pPDDst;
215
216	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
217	if (rc != VINF_SUCCESS)
218	{
219	pgmUnlock(pVM);
220	AssertRC(rc);
221	return rc;
222	}
223	Assert(pPDDst);
224	# endif
225
226	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
227	/*
228	* If we successfully correct the write protection fault due to dirty bit
229	* tracking, or this page fault is a genuine one, then return immediately.
230	*/
231	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
232	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
233	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
234	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
235	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
236	{
237	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
238	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
239	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
240	pgmUnlock(pVM);
241	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
242	}
243
244	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
245	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
246
247	/*
248	* A common case is the not-present error caused by lazy page table syncing.
249	*
250	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
251	* so we can safely assume that the shadow PT is present when calling SyncPage later.
252	*
253	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
254	* of mapping conflict and defer to SyncCR3 in R3.
255	* (Again, we do NOT support access handlers for non-present guest pages.)
256	*
257	*/
258	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
259	&& !pPDDst->a[iPDDst].n.u1Present
260	&& PdeSrc.n.u1Present
261	)
262	{
263	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
264	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
265	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
267	pgmUnlock(pVM);
268	if (RT_SUCCESS(rc))
269	{
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return rc;
272	}
273	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
274	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
275	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
276	return VINF_PGM_SYNC_CR3;
277	}
278	pgmUnlock(pVM);
279	}
280
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
282	/*
283	* Check if this address is within any of our mappings.
284	*
285	* This is very fast and it's gonna save us a bit of effort below and prevent
286	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
287	* (BTW, it's impossible to have physical access handlers in a mapping.)
288	*/
289	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
290	{
291	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
292	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
293	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
294	{
295	if (pvFault < pMapping->GCPtr)
296	break;
297	if (pvFault - pMapping->GCPtr < pMapping->cb)
298	{
299	/*
300	* The first thing we check is if we've got an undetected conflict.
301	*/
302	if (!pVM->pgm.s.fMappingsFixed)
303	{
304	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
305	while (iPT-- > 0)
306	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
307	{
308	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
309	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
310	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
311	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
312	return VINF_PGM_SYNC_CR3;
313	}
314	}
315
316	/*
317	* Check if the fault address is in a virtual page access handler range.
318	*/
319	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
320	if ( pCur
321	&& pvFault - pCur->Core.Key < pCur->cb
322	&& uErr & X86_TRAP_PF_RW)
323	{
324	# ifdef IN_RC
325	STAM_PROFILE_START(&pCur->Stat, h);
326	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
327	STAM_PROFILE_STOP(&pCur->Stat, h);
328	# else
329	AssertFailed();
330	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
331	# endif
332	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
333	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
334	return rc;
335	}
336
337	/*
338	* Pretend we're not here and let the guest handle the trap.
339	*/
340	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
341	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
342	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
343	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
344	return VINF_EM_RAW_GUEST_TRAP;
345	}
346	}
347	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
348	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
349	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
350
351	/*
352	* Check if this fault address is flagged for special treatment,
353	* which means we'll have to figure out the physical address and
354	* check flags associated with it.
355	*
356	* ASSUME that we can limit any special access handling to pages
357	* in page tables which the guest believes to be present.
358	*/
359	if (PdeSrc.n.u1Present)
360	{
361	RTGCPHYS GCPhys = NIL_RTGCPHYS;
362
363	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
364	# if PGM_GST_TYPE == PGM_TYPE_AMD64
365	bool fBigPagesSupported = true;
366	# else
367	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
368	# endif
369	if ( PdeSrc.b.u1Size
370	&& fBigPagesSupported)
371	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
372	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
373	else
374	{
375	PGSTPT pPTSrc;
376	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
377	if (RT_SUCCESS(rc))
378	{
379	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
380	if (pPTSrc->a[iPTESrc].n.u1Present)
381	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
382	}
383	}
384	# else
385	/* No paging so the fault address is the physical address */
386	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
387	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
388
389	/*
390	* If we have a GC address we'll check if it has any flags set.
391	*/
392	if (GCPhys != NIL_RTGCPHYS)
393	{
394	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
395
396	PPGMPAGE pPage;
397	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
398	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
399	{
400	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
401	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
402	{
403	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
404	{
405	/*
406	* Physical page access handler.
407	*/
408	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
409	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
410	if (pCur)
411	{
412	# ifdef PGM_SYNC_N_PAGES
413	/*
414	* If the region is write protected and we got a page not present fault, then sync
415	* the pages. If the fault was caused by a read, then restart the instruction.
416	* In case of write access continue to the GC write handler.
417	*
418	* ASSUMES that there is only one handler per page or that they have similar write properties.
419	*/
420	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
421	&& !(uErr & X86_TRAP_PF_P))
422	{
423	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
424	if ( RT_FAILURE(rc)
425	\|\| !(uErr & X86_TRAP_PF_RW)
426	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
427	{
428	AssertRC(rc);
429	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
430	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
431	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
432	return rc;
433	}
434	}
435	# endif
436
437	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
438	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
439	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
440
441	# if defined(IN_RC) \|\| defined(IN_RING0)
442	if (pCur->CTX_SUFF(pfnHandler))
443	{
444	STAM_PROFILE_START(&pCur->Stat, h);
445	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
446	STAM_PROFILE_STOP(&pCur->Stat, h);
447	}
448	else
449	# endif
450	rc = VINF_EM_RAW_EMULATE_INSTR;
451	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
452	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
453	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
454	return rc;
455	}
456	}
457	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
458	else
459	{
460	# ifdef PGM_SYNC_N_PAGES
461	/*
462	* If the region is write protected and we got a page not present fault, then sync
463	* the pages. If the fault was caused by a read, then restart the instruction.
464	* In case of write access continue to the GC write handler.
465	*/
466	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
467	&& !(uErr & X86_TRAP_PF_P))
468	{
469	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
470	if ( RT_FAILURE(rc)
471	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
472	\|\| !(uErr & X86_TRAP_PF_RW))
473	{
474	AssertRC(rc);
475	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
476	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
477	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
478	return rc;
479	}
480	}
481	# endif
482	/*
483	* Ok, it's an virtual page access handler.
484	*
485	* Since it's faster to search by address, we'll do that first
486	* and then retry by GCPhys if that fails.
487	*/
488	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
489	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
490	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
491	*/
492	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
493	if (pCur)
494	{
495	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
496	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
497	\|\| !(uErr & X86_TRAP_PF_P)
498	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
499	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
500
501	if ( pvFault - pCur->Core.Key < pCur->cb
502	&& ( uErr & X86_TRAP_PF_RW
503	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
504	{
505	# ifdef IN_RC
506	STAM_PROFILE_START(&pCur->Stat, h);
507	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
508	STAM_PROFILE_STOP(&pCur->Stat, h);
509	# else
510	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
511	# endif
512	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
513	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
514	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
515	return rc;
516	}
517	/* Unhandled part of a monitored page */
518	}
519	else
520	{
521	/* Check by physical address. */
522	PPGMVIRTHANDLER pCur;
523	unsigned iPage;
524	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
525	&pCur, &iPage);
526	Assert(RT_SUCCESS(rc) \|\| !pCur);
527	if ( pCur
528	&& ( uErr & X86_TRAP_PF_RW
529	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
530	{
531	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
532	# ifdef IN_RC
533	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
534	Assert(off < pCur->cb);
535	STAM_PROFILE_START(&pCur->Stat, h);
536	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
537	STAM_PROFILE_STOP(&pCur->Stat, h);
538	# else
539	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
540	# endif
541	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
542	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
543	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
544	return rc;
545	}
546	}
547	}
548	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
549
550	/*
551	* There is a handled area of the page, but this fault doesn't belong to it.
552	* We must emulate the instruction.
553	*
554	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
555	* we first check if this was a page-not-present fault for a page with only
556	* write access handlers. Restart the instruction if it wasn't a write access.
557	*/
558	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
559
560	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
561	&& !(uErr & X86_TRAP_PF_P))
562	{
563	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
564	if ( RT_FAILURE(rc)
565	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
566	\|\| !(uErr & X86_TRAP_PF_RW))
567	{
568	AssertRC(rc);
569	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
570	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
571	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
572	return rc;
573	}
574	}
575
576	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
577	* It's writing to an unhandled part of the LDT page several million times.
578	*/
579	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
580	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
581	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
582	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
583	return rc;
584	} /* if any kind of handler */
585
586	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
587	if (uErr & X86_TRAP_PF_P)
588	{
589	/*
590	* The page isn't marked, but it might still be monitored by a virtual page access handler.
591	* (ASSUMES no temporary disabling of virtual handlers.)
592	*/
593	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
594	* we should correct both the shadow page table and physical memory flags, and not only check for
595	* accesses within the handler region but for access to pages with virtual handlers. */
596	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
597	if (pCur)
598	{
599	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
600	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
601	\|\| !(uErr & X86_TRAP_PF_P)
602	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
603	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
604
605	if ( pvFault - pCur->Core.Key < pCur->cb
606	&& ( uErr & X86_TRAP_PF_RW
607	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
608	{
609	# ifdef IN_RC
610	STAM_PROFILE_START(&pCur->Stat, h);
611	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
612	STAM_PROFILE_STOP(&pCur->Stat, h);
613	# else
614	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
615	# endif
616	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
617	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
618	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
619	return rc;
620	}
621	}
622	}
623	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
624	}
625	else
626	{
627	/*
628	* When the guest accesses invalid physical memory (e.g. probing
629	* of RAM or accessing a remapped MMIO range), then we'll fall
630	* back to the recompiler to emulate the instruction.
631	*/
632	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
633	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
634	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
635	return VINF_EM_RAW_EMULATE_INSTR;
636	}
637
638	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
639
640	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
641	/*
642	* We are here only if page is present in Guest page tables and
643	* trap is not handled by our handlers.
644	*
645	* Check it for page out-of-sync situation.
646	*/
647	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
648
649	if (!(uErr & X86_TRAP_PF_P))
650	{
651	/*
652	* Page is not present in our page tables.
653	* Try to sync it!
654	* BTW, fPageShw is invalid in this branch!
655	*/
656	if (uErr & X86_TRAP_PF_US)
657	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
658	else /* supervisor */
659	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
660
661	# if defined(LOG_ENABLED) && !defined(IN_RING0)
662	RTGCPHYS GCPhys;
663	uint64_t fPageGst;
664	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
665	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
666	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
667	# endif /* LOG_ENABLED */
668
669	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
670	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
671	{
672	uint64_t fPageGst;
673	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
674	if ( RT_SUCCESS(rc)
675	&& !(fPageGst & X86_PTE_US))
676	{
677	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
678	if ( pvFault == (RTGCPTR)pRegFrame->eip
679	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
680	# ifdef CSAM_DETECT_NEW_CODE_PAGES
681	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
682	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
683	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
684	)
685	{
686	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
687	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
688	if (rc != VINF_SUCCESS)
689	{
690	/*
691	* CSAM needs to perform a job in ring 3.
692	*
693	* Sync the page before going to the host context; otherwise we'll end up in a loop if
694	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
695	*/
696	LogFlow(("CSAM ring 3 job\n"));
697	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
698	AssertRC(rc2);
699
700	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
701	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
702	return rc;
703	}
704	}
705	# ifdef CSAM_DETECT_NEW_CODE_PAGES
706	else if ( uErr == X86_TRAP_PF_RW
707	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
708	&& pRegFrame->ecx < 0x10000)
709	{
710	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
711	* to detect loading of new code pages.
712	*/
713
714	/*
715	* Decode the instruction.
716	*/
717	RTGCPTR PC;
718	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
719	if (rc == VINF_SUCCESS)
720	{
721	DISCPUSTATE Cpu;
722	uint32_t cbOp;
723	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
724
725	/* For now we'll restrict this to rep movsw/d instructions */
726	if ( rc == VINF_SUCCESS
727	&& Cpu.pCurInstr->opcode == OP_MOVSWD
728	&& (Cpu.prefix & PREFIX_REP))
729	{
730	CSAMMarkPossibleCodePage(pVM, pvFault);
731	}
732	}
733	}
734	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
735
736	/*
737	* Mark this page as safe.
738	*/
739	/** @todo not correct for pages that contain both code and data!! */
740	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
741	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
742	}
743	}
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
745	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
746	if (RT_SUCCESS(rc))
747	{
748	/* The page was successfully synced, return to the guest. */
749	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
750	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
751	return VINF_SUCCESS;
752	}
753	}
754	else /* uErr & X86_TRAP_PF_P: */
755	{
756	/*
757	* Write protected pages are make writable when the guest makes the first
758	* write to it. This happens for pages that are shared, write monitored
759	* and not yet allocated.
760	*
761	* Also, a side effect of not flushing global PDEs are out of sync pages due
762	* to physical monitored regions, that are no longer valid.
763	* Assume for now it only applies to the read/write flag.
764	*/
765	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
766	{
767	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
768	{
769	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
770	GCPhys, pPage, pvFault, uErr));
771	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
772	if (rc != VINF_SUCCESS)
773	{
774	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
775	return rc;
776	}
777	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
778	return VINF_EM_NO_MEMORY;
779	}
780	/// @todo count the above case; else
781	if (uErr & X86_TRAP_PF_US)
782	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
783	else /* supervisor */
784	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
785
786	/*
787	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
788	* page is not present, which is not true in this case.
789	*/
790	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
791	if (RT_SUCCESS(rc))
792	{
793	/*
794	* Page was successfully synced, return to guest.
795	*/
796	# ifdef VBOX_STRICT
797	RTGCPHYS GCPhys;
798	uint64_t fPageGst;
799	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
800	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
801	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
802
803	uint64_t fPageShw;
804	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
805	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
806	# endif /* VBOX_STRICT */
807	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
808	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
809	return VINF_SUCCESS;
810	}
811
812	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
813	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
814	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
815	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
816	{
817	uint64_t fPageGst;
818	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
819	if ( RT_SUCCESS(rc)
820	&& !(fPageGst & X86_PTE_RW))
821	{
822	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
823	if (RT_SUCCESS(rc))
824	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
825	else
826	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
827	return rc;
828	}
829	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
830	}
831	}
832
833	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
834	# ifdef VBOX_STRICT
835	/*
836	* Check for VMM page flags vs. Guest page flags consistency.
837	* Currently only for debug purposes.
838	*/
839	if (RT_SUCCESS(rc))
840	{
841	/* Get guest page flags. */
842	uint64_t fPageGst;
843	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
844	if (RT_SUCCESS(rc))
845	{
846	uint64_t fPageShw;
847	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
848
849	/*
850	* Compare page flags.
851	* Note: we have AVL, A, D bits desynched.
852	*/
853	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
854	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
855	}
856	else
857	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
858	}
859	else
860	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
861	# endif /* VBOX_STRICT */
862	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
863	}
864	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
865	# endif /* PGM_OUT_OF_SYNC_IN_GC */
866	}
867	else /* GCPhys == NIL_RTGCPHYS */
868	{
869	/*
870	* Page not present in Guest OS or invalid page table address.
871	* This is potential virtual page access handler food.
872	*
873	* For the present we'll say that our access handlers don't
874	* work for this case - we've already discarded the page table
875	* not present case which is identical to this.
876	*
877	* When we perchance find we need this, we will probably have AVL
878	* trees (offset based) to operate on and we can measure their speed
879	* agains mapping a page table and probably rearrange this handling
880	* a bit. (Like, searching virtual ranges before checking the
881	* physical address.)
882	*/
883	}
884	}
885	/* else: !present (guest) */
886
887
888	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
889	/*
890	* Conclusion, this is a guest trap.
891	*/
892	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
893	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
894	return VINF_EM_RAW_GUEST_TRAP;
895	# else
896	/* present, but not a monitored page; perhaps the guest is probing physical memory */
897	return VINF_EM_RAW_EMULATE_INSTR;
898	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
899
900
901	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
902
903	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
904	return VERR_INTERNAL_ERROR;
905	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
906	}
907	#endif /* !IN_RING3 */
908
909
910	/**
911	* Emulation of the invlpg instruction.
912	*
913	*
914	* @returns VBox status code.
915	*
916	* @param pVCpu The VMCPU handle.
917	* @param GCPtrPage Page to invalidate.
918	*
919	* @remark ASSUMES that the guest is updating before invalidating. This order
920	* isn't required by the CPU, so this is speculative and could cause
921	* trouble.
922	* @remark No TLB shootdown is done on any other VCPU as we assume that
923	* invlpg emulation is the only reason for calling this function.
924	* Currently true, but keep in mind!
925	*
926	* @todo Flush page or page directory only if necessary!
927	* @todo Add a #define for simply invalidating the page.
928	*/
929	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
930	{
931	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
932	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
933	&& PGM_SHW_TYPE != PGM_TYPE_EPT
934	int rc;
935	PVM pVM = pVCpu->CTX_SUFF(pVM);
936	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
937
938	Assert(PGMIsLockOwner(pVM));
939
940	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
941	/*
942	* Get the shadow PD entry and skip out if this PD isn't present.
943	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
944	*/
945	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
946	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
947	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
948
949	/* Fetch the pgm pool shadow descriptor. */
950	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
951	Assert(pShwPde);
952
953	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
954	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
955	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
956
957	/* If the shadow PDPE isn't present, then skip the invalidate. */
958	if (!pPdptDst->a[iPdpt].n.u1Present)
959	{
960	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
961	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
962	return VINF_SUCCESS;
963	}
964
965	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
966	PPGMPOOLPAGE pShwPde = NULL;
967	PX86PDPAE pPDDst;
968
969	/* Fetch the pgm pool shadow descriptor. */
970	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
971	AssertRCSuccessReturn(rc, rc);
972	Assert(pShwPde);
973
974	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
975	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
976
977	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
978	/* PML4 */
979	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
980	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
981	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
982	PX86PDPAE pPDDst;
983	PX86PDPT pPdptDst;
984	PX86PML4E pPml4eDst;
985	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
986	if (rc != VINF_SUCCESS)
987	{
988	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
990	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
991	PGM_INVL_GUEST_TLBS();
992	return VINF_SUCCESS;
993	}
994	Assert(pPDDst);
995
996	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
997	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
998
999	if (!pPdpeDst->n.u1Present)
1000	{
1001	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1002	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1003	PGM_INVL_GUEST_TLBS();
1004	return VINF_SUCCESS;
1005	}
1006
1007	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1008
1009	const SHWPDE PdeDst = *pPdeDst;
1010	if (!PdeDst.n.u1Present)
1011	{
1012	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1013	return VINF_SUCCESS;
1014	}
1015
1016	# if defined(IN_RC)
1017	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1018	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1019	# endif
1020
1021	/*
1022	* Get the guest PD entry and calc big page.
1023	*/
1024	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1025	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1026	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1027	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1028	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1029	unsigned iPDSrc = 0;
1030	# if PGM_GST_TYPE == PGM_TYPE_PAE
1031	X86PDPE PdpeSrc;
1032	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1033	# else /* AMD64 */
1034	PX86PML4E pPml4eSrc;
1035	X86PDPE PdpeSrc;
1036	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1037	# endif
1038	GSTPDE PdeSrc;
1039
1040	if (pPDSrc)
1041	PdeSrc = pPDSrc->a[iPDSrc];
1042	else
1043	PdeSrc.u = 0;
1044	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1045
1046	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1047	const bool fIsBigPage = PdeSrc.b.u1Size;
1048	# else
1049	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1050	# endif
1051
1052	# ifdef IN_RING3
1053	/*
1054	* If a CR3 Sync is pending we may ignore the invalidate page operation
1055	* depending on the kind of sync and if it's a global page or not.
1056	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1057	*/
1058	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1059	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1060	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1061	&& fIsBigPage
1062	&& PdeSrc.b.u1Global
1063	)
1064	)
1065	# else
1066	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1067	# endif
1068	{
1069	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1070	return VINF_SUCCESS;
1071	}
1072	# endif /* IN_RING3 */
1073
1074	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1075	/* Fetch the pgm pool shadow descriptor. */
1076	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1077	Assert(pShwPdpt);
1078
1079	/* Fetch the pgm pool shadow descriptor. */
1080	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1081	Assert(pShwPde);
1082
1083	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1084	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1085
1086	if ( !pPml4eSrc->n.u1Present
1087	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1088	{
1089	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1090	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1091	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1092	ASMAtomicWriteSize(pPml4eDst, 0);
1093	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1094	PGM_INVL_GUEST_TLBS();
1095	return VINF_SUCCESS;
1096	}
1097	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1098	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1099	{
1100	/*
1101	* Mark not present so we can resync the PML4E when it's used.
1102	*/
1103	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1104	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1105	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1106	ASMAtomicWriteSize(pPml4eDst, 0);
1107	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1108	PGM_INVL_GUEST_TLBS();
1109	}
1110	else if (!pPml4eSrc->n.u1Accessed)
1111	{
1112	/*
1113	* Mark not present so we can set the accessed bit.
1114	*/
1115	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1116	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1117	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1118	ASMAtomicWriteSize(pPml4eDst, 0);
1119	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1120	PGM_INVL_GUEST_TLBS();
1121	}
1122
1123	/* Check if the PDPT entry has changed. */
1124	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1125	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1126	if ( !PdpeSrc.n.u1Present
1127	\|\| pShwPde->GCPhys != GCPhysPd)
1128	{
1129	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1130	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1131	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1132	ASMAtomicWriteSize(pPdpeDst, 0);
1133	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1134	PGM_INVL_GUEST_TLBS();
1135	return VINF_SUCCESS;
1136	}
1137	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1138	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1139	{
1140	/*
1141	* Mark not present so we can resync the PDPTE when it's used.
1142	*/
1143	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1144	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1145	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1146	ASMAtomicWriteSize(pPdpeDst, 0);
1147	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1148	PGM_INVL_GUEST_TLBS();
1149	}
1150	else if (!PdpeSrc.lm.u1Accessed)
1151	{
1152	/*
1153	* Mark not present so we can set the accessed bit.
1154	*/
1155	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1156	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1157	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1158	ASMAtomicWriteSize(pPdpeDst, 0);
1159	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1160	PGM_INVL_GUEST_TLBS();
1161	}
1162	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1163
1164	/*
1165	* Deal with the Guest PDE.
1166	*/
1167	rc = VINF_SUCCESS;
1168	if (PdeSrc.n.u1Present)
1169	{
1170	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1171	{
1172	/*
1173	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1174	*/
1175	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1176	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1177	pgmLock(pVM);
1178	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1179	pgmUnlock(pVM);
1180	}
1181	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1182	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1183	{
1184	/*
1185	* Mark not present so we can resync the PDE when it's used.
1186	*/
1187	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1188	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1189	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1190	ASMAtomicWriteSize(pPdeDst, 0);
1191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1192	PGM_INVL_GUEST_TLBS();
1193	}
1194	else if (!PdeSrc.n.u1Accessed)
1195	{
1196	/*
1197	* Mark not present so we can set the accessed bit.
1198	*/
1199	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1200	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1201	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1202	ASMAtomicWriteSize(pPdeDst, 0);
1203	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1204	PGM_INVL_GUEST_TLBS();
1205	}
1206	else if (!fIsBigPage)
1207	{
1208	/*
1209	* 4KB - page.
1210	*/
1211	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1212	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1213	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1214	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1215	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1216	# endif
1217	if (pShwPage->GCPhys == GCPhys)
1218	{
1219	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1220	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1221	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1222	if (pPT->a[iPTEDst].n.u1Present)
1223	{
1224	# ifdef PGMPOOL_WITH_USER_TRACKING
1225	/* This is very unlikely with caching/monitoring enabled. */
1226	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1227	# endif
1228	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1229	}
1230	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1231	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1232	if (RT_SUCCESS(rc))
1233	rc = VINF_SUCCESS;
1234	# endif
1235	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1236	PGM_INVL_PG(GCPtrPage);
1237	}
1238	else
1239	{
1240	/*
1241	* The page table address changed.
1242	*/
1243	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1244	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1245	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1246	ASMAtomicWriteSize(pPdeDst, 0);
1247	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1248	PGM_INVL_GUEST_TLBS();
1249	}
1250	}
1251	else
1252	{
1253	/*
1254	* 2/4MB - page.
1255	*/
1256	/* Before freeing the page, check if anything really changed. */
1257	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1258	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1259	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1260	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1261	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1262	# endif
1263	if ( pShwPage->GCPhys == GCPhys
1264	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1265	{
1266	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1267	/** @todo PAT */
1268	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1269	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1270	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1271	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1272	{
1273	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1274	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1275	# if defined(IN_RC)
1276	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1277	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1278	# endif
1279	return VINF_SUCCESS;
1280	}
1281	}
1282
1283	/*
1284	* Ok, the page table is present and it's been changed in the guest.
1285	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1286	* We could do this for some flushes in GC too, but we need an algorithm for
1287	* deciding which 4MB pages containing code likely to be executed very soon.
1288	*/
1289	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1290	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1291	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1292	ASMAtomicWriteSize(pPdeDst, 0);
1293	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1294	PGM_INVL_BIG_PG(GCPtrPage);
1295	}
1296	}
1297	else
1298	{
1299	/*
1300	* Page directory is not present, mark shadow PDE not present.
1301	*/
1302	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1303	{
1304	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1305	ASMAtomicWriteSize(pPdeDst, 0);
1306	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1307	PGM_INVL_PG(GCPtrPage);
1308	}
1309	else
1310	{
1311	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1313	}
1314	}
1315	# if defined(IN_RC)
1316	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1317	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1318	# endif
1319	return rc;
1320
1321	#else /* guest real and protected mode */
1322	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1323	return VINF_SUCCESS;
1324	#endif
1325	}
1326
1327
1328	#ifdef PGMPOOL_WITH_USER_TRACKING
1329	/**
1330	* Update the tracking of shadowed pages.
1331	*
1332	* @param pVCpu The VMCPU handle.
1333	* @param pShwPage The shadow page.
1334	* @param HCPhys The physical page we is being dereferenced.
1335	*/
1336	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1337	{
1338	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1339	PVM pVM = pVCpu->CTX_SUFF(pVM);
1340
1341	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1342	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1343
1344	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1345	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1346	* 2. write protect all shadowed pages. I.e. implement caching.
1347	*/
1348	/*
1349	* Find the guest address.
1350	*/
1351	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1352	pRam;
1353	pRam = pRam->CTX_SUFF(pNext))
1354	{
1355	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1356	while (iPage-- > 0)
1357	{
1358	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1359	{
1360	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1361	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1362	pShwPage->cPresent--;
1363	pPool->cPresent--;
1364	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1365	return;
1366	}
1367	}
1368	}
1369
1370	for (;;)
1371	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1372	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1373	pShwPage->cPresent--;
1374	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1375	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1376	}
1377
1378
1379	/**
1380	* Update the tracking of shadowed pages.
1381	*
1382	* @param pVCpu The VMCPU handle.
1383	* @param pShwPage The shadow page.
1384	* @param u16 The top 16-bit of the pPage->HCPhys.
1385	* @param pPage Pointer to the guest page. this will be modified.
1386	* @param iPTDst The index into the shadow table.
1387	*/
1388	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1389	{
1390	PVM pVM = pVCpu->CTX_SUFF(pVM);
1391	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1392	/*
1393	* Just deal with the simple first time here.
1394	*/
1395	if (!u16)
1396	{
1397	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1398	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1399	}
1400	else
1401	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1402
1403	/* write back */
1404	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1405	PGM_PAGE_SET_TRACKING(pPage, u16);
1406
1407	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1408
1409	/* update statistics. */
1410	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1411	pShwPage->cPresent++;
1412	if (pShwPage->iFirstPresent > iPTDst)
1413	pShwPage->iFirstPresent = iPTDst;
1414	}
1415	#endif /* PGMPOOL_WITH_USER_TRACKING */
1416
1417
1418	/**
1419	* Creates a 4K shadow page for a guest page.
1420	*
1421	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1422	* physical address. The PdeSrc argument only the flags are used. No page structured
1423	* will be mapped in this function.
1424	*
1425	* @param pVCpu The VMCPU handle.
1426	* @param pPteDst Destination page table entry.
1427	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1428	* Can safely assume that only the flags are being used.
1429	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1430	* @param pShwPage Pointer to the shadow page.
1431	* @param iPTDst The index into the shadow table.
1432	*
1433	* @remark Not used for 2/4MB pages!
1434	*/
1435	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1436	{
1437	if (PteSrc.n.u1Present)
1438	{
1439	PVM pVM = pVCpu->CTX_SUFF(pVM);
1440
1441	/*
1442	* Find the ram range.
1443	*/
1444	PPGMPAGE pPage;
1445	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1446	if (RT_SUCCESS(rc))
1447	{
1448	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1449	/* Try make the page writable if necessary. */
1450	if ( PteSrc.n.u1Write
1451	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1452	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1453	{
1454	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1455	AssertRC(rc);
1456	}
1457	#endif
1458
1459	/** @todo investiage PWT, PCD and PAT. */
1460	/*
1461	* Make page table entry.
1462	*/
1463	SHWPTE PteDst;
1464	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1465	{
1466	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1467	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1468	{
1469	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1470	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1471	PteDst.n.u1Present = 1;
1472	PteDst.n.u1Execute = 1;
1473	PteDst.n.u1IgnorePAT = 1;
1474	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1475	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1476	#else
1477	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1478	\| PGM_PAGE_GET_HCPHYS(pPage);
1479	#endif
1480	}
1481	else
1482	{
1483	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1484	PteDst.u = 0;
1485	}
1486	/** @todo count these two kinds. */
1487	}
1488	else
1489	{
1490	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1491	/*
1492	* If the page or page directory entry is not marked accessed,
1493	* we mark the page not present.
1494	*/
1495	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1496	{
1497	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1498	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1499	PteDst.u = 0;
1500	}
1501	else
1502	/*
1503	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1504	* when the page is modified.
1505	*/
1506	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1507	{
1508	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1509	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1510	\| PGM_PAGE_GET_HCPHYS(pPage)
1511	\| PGM_PTFLAGS_TRACK_DIRTY;
1512	}
1513	else
1514	#endif
1515	{
1516	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1517	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1518	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1519	PteDst.n.u1Present = 1;
1520	PteDst.n.u1Write = 1;
1521	PteDst.n.u1Execute = 1;
1522	PteDst.n.u1IgnorePAT = 1;
1523	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1524	/* PteDst.n.u1Size = 0 */
1525	#else
1526	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1527	\| PGM_PAGE_GET_HCPHYS(pPage);
1528	#endif
1529	}
1530	}
1531
1532	/*
1533	* Make sure only allocated pages are mapped writable.
1534	*/
1535	if ( PteDst.n.u1Write
1536	&& PteDst.n.u1Present
1537	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1538	{
1539	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1540	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1541	}
1542
1543	#ifdef PGMPOOL_WITH_USER_TRACKING
1544	/*
1545	* Keep user track up to date.
1546	*/
1547	if (PteDst.n.u1Present)
1548	{
1549	if (!pPteDst->n.u1Present)
1550	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1551	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1552	{
1553	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1554	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1555	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1556	}
1557	}
1558	else if (pPteDst->n.u1Present)
1559	{
1560	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1561	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1562	}
1563	#endif /* PGMPOOL_WITH_USER_TRACKING */
1564
1565	/*
1566	* Update statistics and commit the entry.
1567	*/
1568	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1569	if (!PteSrc.n.u1Global)
1570	pShwPage->fSeenNonGlobal = true;
1571	#endif
1572	ASMAtomicWriteSize(pPteDst, PteDst.u);
1573	}
1574	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1575	/** @todo count these. */
1576	}
1577	else
1578	{
1579	/*
1580	* Page not-present.
1581	*/
1582	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1583	#ifdef PGMPOOL_WITH_USER_TRACKING
1584	/* Keep user track up to date. */
1585	if (pPteDst->n.u1Present)
1586	{
1587	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1588	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1589	}
1590	#endif /* PGMPOOL_WITH_USER_TRACKING */
1591	ASMAtomicWriteSize(pPteDst, 0);
1592	/** @todo count these. */
1593	}
1594	}
1595
1596
1597	/**
1598	* Syncs a guest OS page.
1599	*
1600	* There are no conflicts at this point, neither is there any need for
1601	* page table allocations.
1602	*
1603	* @returns VBox status code.
1604	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1605	* @param pVCpu The VMCPU handle.
1606	* @param PdeSrc Page directory entry of the guest.
1607	* @param GCPtrPage Guest context page address.
1608	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1609	* @param uErr Fault error (X86_TRAP_PF_*).
1610	*/
1611	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1612	{
1613	PVM pVM = pVCpu->CTX_SUFF(pVM);
1614	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1615	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1616
1617	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1618	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1619	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1620	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1621	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1622
1623	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1624	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1625	# endif
1626
1627	/*
1628	* Assert preconditions.
1629	*/
1630	Assert(PdeSrc.n.u1Present);
1631	Assert(cPages);
1632	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1633
1634	/*
1635	* Get the shadow PDE, find the shadow page table in the pool.
1636	*/
1637	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1638	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1639	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1640
1641	/* Fetch the pgm pool shadow descriptor. */
1642	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1643	Assert(pShwPde);
1644
1645	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1646	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1647	PPGMPOOLPAGE pShwPde = NULL;
1648	PX86PDPAE pPDDst;
1649
1650	/* Fetch the pgm pool shadow descriptor. */
1651	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1652	AssertRCSuccessReturn(rc, rc);
1653	Assert(pShwPde);
1654
1655	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1656	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1657
1658	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1659	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1660	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1661	PX86PDPAE pPDDst;
1662	PX86PDPT pPdptDst;
1663
1664	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1665	AssertRCSuccessReturn(rc, rc);
1666	Assert(pPDDst && pPdptDst);
1667	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1668	# endif
1669	SHWPDE PdeDst = *pPdeDst;
1670	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1671	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1672
1673	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1674	/* Fetch the pgm pool shadow descriptor. */
1675	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1676	Assert(pShwPde);
1677	# endif
1678
1679	# if defined(IN_RC)
1680	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1681	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1682	# endif
1683
1684	/*
1685	* Check that the page is present and that the shadow PDE isn't out of sync.
1686	*/
1687	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1688	const bool fBigPage = PdeSrc.b.u1Size;
1689	# else
1690	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1691	# endif
1692	RTGCPHYS GCPhys;
1693	if (!fBigPage)
1694	{
1695	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1696	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1697	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1698	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1699	# endif
1700	}
1701	else
1702	{
1703	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1704	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1705	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1706	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1707	# endif
1708	}
1709	if ( pShwPage->GCPhys == GCPhys
1710	&& PdeSrc.n.u1Present
1711	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1712	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1713	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1714	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1715	# endif
1716	)
1717	{
1718	/*
1719	* Check that the PDE is marked accessed already.
1720	* Since we set the accessed bit before getting here on a #PF, this
1721	* check is only meant for dealing with non-#PF'ing paths.
1722	*/
1723	if (PdeSrc.n.u1Accessed)
1724	{
1725	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1726	if (!fBigPage)
1727	{
1728	/*
1729	* 4KB Page - Map the guest page table.
1730	*/
1731	PGSTPT pPTSrc;
1732	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1733	if (RT_SUCCESS(rc))
1734	{
1735	# ifdef PGM_SYNC_N_PAGES
1736	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1737	if ( cPages > 1
1738	&& !(uErr & X86_TRAP_PF_P)
1739	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1740	{
1741	/*
1742	* This code path is currently only taken when the caller is PGMTrap0eHandler
1743	* for non-present pages!
1744	*
1745	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1746	* deal with locality.
1747	*/
1748	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1749	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1750	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1751	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1752	# else
1753	const unsigned offPTSrc = 0;
1754	# endif
1755	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1756	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1757	iPTDst = 0;
1758	else
1759	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1760	for (; iPTDst < iPTDstEnd; iPTDst++)
1761	{
1762	if (!pPTDst->a[iPTDst].n.u1Present)
1763	{
1764	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1765	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1766	NOREF(GCPtrCurPage);
1767	#ifndef IN_RING0
1768	/*
1769	* Assuming kernel code will be marked as supervisor - and not as user level
1770	* and executed using a conforming code selector - And marked as readonly.
1771	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1772	*/
1773	PPGMPAGE pPage;
1774	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1775	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1776	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1777	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1778	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1779	)
1780	#endif /* else: CSAM not active */
1781	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1782	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1783	GCPtrCurPage, PteSrc.n.u1Present,
1784	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1785	PteSrc.n.u1User & PdeSrc.n.u1User,
1786	(uint64_t)PteSrc.u,
1787	(uint64_t)pPTDst->a[iPTDst].u,
1788	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1789	}
1790	}
1791	}
1792	else
1793	# endif /* PGM_SYNC_N_PAGES */
1794	{
1795	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1796	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1797	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1798	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1799	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1800	GCPtrPage, PteSrc.n.u1Present,
1801	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1802	PteSrc.n.u1User & PdeSrc.n.u1User,
1803	(uint64_t)PteSrc.u,
1804	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1805	}
1806	}
1807	else /* MMIO or invalid page: emulated in #PF handler. */
1808	{
1809	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1810	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1811	}
1812	}
1813	else
1814	{
1815	/*
1816	* 4/2MB page - lazy syncing shadow 4K pages.
1817	* (There are many causes of getting here, it's no longer only CSAM.)
1818	*/
1819	/* Calculate the GC physical address of this 4KB shadow page. */
1820	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1821	/* Find ram range. */
1822	PPGMPAGE pPage;
1823	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1824	if (RT_SUCCESS(rc))
1825	{
1826	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1827	/* Try make the page writable if necessary. */
1828	if ( PdeSrc.n.u1Write
1829	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1830	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1831	{
1832	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1833	AssertRC(rc);
1834	}
1835	# endif
1836
1837	/*
1838	* Make shadow PTE entry.
1839	*/
1840	SHWPTE PteDst;
1841	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1842	\| PGM_PAGE_GET_HCPHYS(pPage);
1843	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1844	{
1845	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1846	PteDst.n.u1Write = 0;
1847	else
1848	PteDst.u = 0;
1849	}
1850	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1851	# ifdef PGMPOOL_WITH_USER_TRACKING
1852	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1853	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1854	# endif
1855	/* Make sure only allocated pages are mapped writable. */
1856	if ( PteDst.n.u1Write
1857	&& PteDst.n.u1Present
1858	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1859	{
1860	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1861	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1862	}
1863
1864	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1865
1866	/*
1867	* If the page is not flagged as dirty and is writable, then make it read-only
1868	* at PD level, so we can set the dirty bit when the page is modified.
1869	*
1870	* ASSUMES that page access handlers are implemented on page table entry level.
1871	* Thus we will first catch the dirty access and set PDE.D and restart. If
1872	* there is an access handler, we'll trap again and let it work on the problem.
1873	*/
1874	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1875	* As for invlpg, it simply frees the whole shadow PT.
1876	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1877	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1878	{
1879	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1880	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1881	PdeDst.n.u1Write = 0;
1882	}
1883	else
1884	{
1885	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1886	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1887	}
1888	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1889	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1890	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1891	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1892	}
1893	else
1894	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1895	}
1896	# if defined(IN_RC)
1897	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1898	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1899	# endif
1900	return VINF_SUCCESS;
1901	}
1902	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1903	}
1904	else
1905	{
1906	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1907	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1908	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1909	}
1910
1911	/*
1912	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1913	* Yea, I'm lazy.
1914	*/
1915	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1916	ASMAtomicWriteSize(pPdeDst, 0);
1917
1918	# if defined(IN_RC)
1919	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1920	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1921	# endif
1922	PGM_INVL_GUEST_TLBS();
1923	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1924
1925	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1926	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1927	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1928	&& !defined(IN_RC)
1929
1930	# ifdef PGM_SYNC_N_PAGES
1931	/*
1932	* Get the shadow PDE, find the shadow page table in the pool.
1933	*/
1934	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1935	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1936
1937	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1938	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1939
1940	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1941	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1942	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1943	PX86PDPAE pPDDst;
1944	X86PDEPAE PdeDst;
1945	PX86PDPT pPdptDst;
1946
1947	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1948	AssertRCSuccessReturn(rc, rc);
1949	Assert(pPDDst && pPdptDst);
1950	PdeDst = pPDDst->a[iPDDst];
1951	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1952	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1953	PEPTPD pPDDst;
1954	EPTPDE PdeDst;
1955
1956	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1957	if (rc != VINF_SUCCESS)
1958	{
1959	AssertRC(rc);
1960	return rc;
1961	}
1962	Assert(pPDDst);
1963	PdeDst = pPDDst->a[iPDDst];
1964	# endif
1965	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1966	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1967	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1968
1969	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1970	if ( cPages > 1
1971	&& !(uErr & X86_TRAP_PF_P)
1972	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1973	{
1974	/*
1975	* This code path is currently only taken when the caller is PGMTrap0eHandler
1976	* for non-present pages!
1977	*
1978	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1979	* deal with locality.
1980	*/
1981	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1982	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1983	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1984	iPTDst = 0;
1985	else
1986	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1987	for (; iPTDst < iPTDstEnd; iPTDst++)
1988	{
1989	if (!pPTDst->a[iPTDst].n.u1Present)
1990	{
1991	GSTPTE PteSrc;
1992
1993	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1994
1995	/* Fake the page table entry */
1996	PteSrc.u = GCPtrCurPage;
1997	PteSrc.n.u1Present = 1;
1998	PteSrc.n.u1Dirty = 1;
1999	PteSrc.n.u1Accessed = 1;
2000	PteSrc.n.u1Write = 1;
2001	PteSrc.n.u1User = 1;
2002
2003	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2004
2005	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2006	GCPtrCurPage, PteSrc.n.u1Present,
2007	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2008	PteSrc.n.u1User & PdeSrc.n.u1User,
2009	(uint64_t)PteSrc.u,
2010	(uint64_t)pPTDst->a[iPTDst].u,
2011	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2012
2013	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2014	break;
2015	}
2016	else
2017	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2018	}
2019	}
2020	else
2021	# endif /* PGM_SYNC_N_PAGES */
2022	{
2023	GSTPTE PteSrc;
2024	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2025	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2026
2027	/* Fake the page table entry */
2028	PteSrc.u = GCPtrCurPage;
2029	PteSrc.n.u1Present = 1;
2030	PteSrc.n.u1Dirty = 1;
2031	PteSrc.n.u1Accessed = 1;
2032	PteSrc.n.u1Write = 1;
2033	PteSrc.n.u1User = 1;
2034	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2035
2036	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2037	GCPtrPage, PteSrc.n.u1Present,
2038	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2039	PteSrc.n.u1User & PdeSrc.n.u1User,
2040	(uint64_t)PteSrc.u,
2041	(uint64_t)pPTDst->a[iPTDst].u,
2042	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2043	}
2044	return VINF_SUCCESS;
2045
2046	#else
2047	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2048	return VERR_INTERNAL_ERROR;
2049	#endif
2050	}
2051
2052
2053	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2054	/**
2055	* Investigate page fault and handle write protection page faults caused by
2056	* dirty bit tracking.
2057	*
2058	* @returns VBox status code.
2059	* @param pVCpu The VMCPU handle.
2060	* @param uErr Page fault error code.
2061	* @param pPdeDst Shadow page directory entry.
2062	* @param pPdeSrc Guest page directory entry.
2063	* @param GCPtrPage Guest context page address.
2064	*/
2065	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2066	{
2067	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2068	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2069	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2070	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2071	bool fBigPagesSupported = true;
2072	# else
2073	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2074	# endif
2075	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2076	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2077	# endif
2078	unsigned uPageFaultLevel;
2079	int rc;
2080	PVM pVM = pVCpu->CTX_SUFF(pVM);
2081	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2082
2083	Assert(PGMIsLockOwner(pVM));
2084
2085	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2086	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2087
2088	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2089	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2090
2091	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2092	PX86PML4E pPml4eSrc;
2093	PX86PDPE pPdpeSrc;
2094
2095	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2096	Assert(pPml4eSrc);
2097
2098	/*
2099	* Real page fault? (PML4E level)
2100	*/
2101	if ( (uErr & X86_TRAP_PF_RSVD)
2102	\|\| !pPml4eSrc->n.u1Present
2103	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2104	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2105	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2106	)
2107	{
2108	uPageFaultLevel = 0;
2109	goto l_UpperLevelPageFault;
2110	}
2111	Assert(pPdpeSrc);
2112
2113	# else /* PAE */
2114	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2115	# endif /* PAE */
2116
2117	/*
2118	* Real page fault? (PDPE level)
2119	*/
2120	if ( (uErr & X86_TRAP_PF_RSVD)
2121	\|\| !pPdpeSrc->n.u1Present
2122	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2123	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2124	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2125	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2126	# endif
2127	)
2128	{
2129	uPageFaultLevel = 1;
2130	goto l_UpperLevelPageFault;
2131	}
2132	# endif
2133
2134	/*
2135	* Real page fault? (PDE level)
2136	*/
2137	if ( (uErr & X86_TRAP_PF_RSVD)
2138	\|\| !pPdeSrc->n.u1Present
2139	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2140	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2141	# endif
2142	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2143	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2144	{
2145	uPageFaultLevel = 2;
2146	goto l_UpperLevelPageFault;
2147	}
2148
2149	/*
2150	* First check the easy case where the page directory has been marked read-only to track
2151	* the dirty bit of an emulated BIG page
2152	*/
2153	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2154	{
2155	/* Mark guest page directory as accessed */
2156	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2157	pPml4eSrc->n.u1Accessed = 1;
2158	pPdpeSrc->lm.u1Accessed = 1;
2159	# endif
2160	pPdeSrc->b.u1Accessed = 1;
2161
2162	/*
2163	* Only write protection page faults are relevant here.
2164	*/
2165	if (fWriteFault)
2166	{
2167	/* Mark guest page directory as dirty (BIG page only). */
2168	pPdeSrc->b.u1Dirty = 1;
2169
2170	if (pPdeDst->n.u1Present)
2171	{
2172	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2173	{
2174	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2175	Assert(pPdeSrc->b.u1Write);
2176
2177	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2178	* fault again and take this path to only invalidate the entry.
2179	*/
2180	pPdeDst->n.u1Write = 1;
2181	pPdeDst->n.u1Accessed = 1;
2182	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2183	PGM_INVL_BIG_PG(GCPtrPage);
2184	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2185	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2186	}
2187	# ifdef IN_RING0
2188	else
2189	/* Check for stale TLB entry; only applies to the SMP guest case. */
2190	if ( pVM->cCPUs > 1
2191	&& pPdeDst->n.u1Write
2192	&& pPdeDst->n.u1Accessed)
2193	{
2194	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2195	if (pShwPage)
2196	{
2197	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2198	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2199	if ( pPteDst->n.u1Present
2200	&& pPteDst->n.u1Write)
2201	{
2202	/* Stale TLB entry. */
2203	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2204	PGM_INVL_PG(GCPtrPage);
2205
2206	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2207	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2208	}
2209	}
2210	}
2211	# endif /* IN_RING0 */
2212	}
2213	}
2214	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2215	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2216	}
2217	/* else: 4KB page table */
2218
2219	/*
2220	* Map the guest page table.
2221	*/
2222	PGSTPT pPTSrc;
2223	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2224	if (RT_SUCCESS(rc))
2225	{
2226	/*
2227	* Real page fault?
2228	*/
2229	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2230	const GSTPTE PteSrc = *pPteSrc;
2231	if ( !PteSrc.n.u1Present
2232	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2233	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2234	# endif
2235	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2236	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2237	)
2238	{
2239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2240	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2241	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2242
2243	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2244	* See the 2nd case above as well.
2245	*/
2246	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2247	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2248
2249	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2250	return VINF_EM_RAW_GUEST_TRAP;
2251	}
2252	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2253
2254	/*
2255	* Set the accessed bits in the page directory and the page table.
2256	*/
2257	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2258	pPml4eSrc->n.u1Accessed = 1;
2259	pPdpeSrc->lm.u1Accessed = 1;
2260	# endif
2261	pPdeSrc->n.u1Accessed = 1;
2262	pPteSrc->n.u1Accessed = 1;
2263
2264	/*
2265	* Only write protection page faults are relevant here.
2266	*/
2267	if (fWriteFault)
2268	{
2269	/* Write access, so mark guest entry as dirty. */
2270	# ifdef VBOX_WITH_STATISTICS
2271	if (!pPteSrc->n.u1Dirty)
2272	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2273	else
2274	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2275	# endif
2276
2277	pPteSrc->n.u1Dirty = 1;
2278
2279	if (pPdeDst->n.u1Present)
2280	{
2281	#ifndef IN_RING0
2282	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2283	* Our individual shadow handlers will provide more information and force a fatal exit.
2284	*/
2285	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2286	{
2287	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2288	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2289	return VINF_SUCCESS;
2290	}
2291	#endif
2292	/*
2293	* Map shadow page table.
2294	*/
2295	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2296	if (pShwPage)
2297	{
2298	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2299	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2300	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2301	{
2302	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2303	{
2304	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2305	# ifdef VBOX_STRICT
2306	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2307	if (pPage)
2308	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2309	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2310	# endif
2311	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2312
2313	Assert(pPteSrc->n.u1Write);
2314
2315	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2316	* fault again and take this path to only invalidate the entry.
2317	*/
2318	pPteDst->n.u1Write = 1;
2319	pPteDst->n.u1Dirty = 1;
2320	pPteDst->n.u1Accessed = 1;
2321	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2322	PGM_INVL_PG(GCPtrPage);
2323
2324	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2325	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2326	}
2327	# ifdef IN_RING0
2328	else
2329	/* Check for stale TLB entry; only applies to the SMP guest case. */
2330	if ( pVM->cCPUs > 1
2331	&& pPteDst->n.u1Write == 1
2332	&& pPteDst->n.u1Accessed == 1)
2333	{
2334	/* Stale TLB entry. */
2335	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2336	PGM_INVL_PG(GCPtrPage);
2337
2338	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2339	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2340	}
2341	# endif
2342	}
2343	}
2344	else
2345	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2346	}
2347	}
2348	/** @todo Optimize accessed bit emulation? */
2349	# ifdef VBOX_STRICT
2350	/*
2351	* Sanity check.
2352	*/
2353	else if ( !pPteSrc->n.u1Dirty
2354	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2355	&& pPdeDst->n.u1Present)
2356	{
2357	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2358	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2359	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2360	if ( pPteDst->n.u1Present
2361	&& pPteDst->n.u1Write)
2362	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2363	}
2364	# endif /* VBOX_STRICT */
2365	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2366	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2367	}
2368	AssertRC(rc);
2369	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2370	return rc;
2371
2372
2373	l_UpperLevelPageFault:
2374	/*
2375	* Pagefault detected while checking the PML4E, PDPE or PDE.
2376	* Single exit handler to get rid of duplicate code paths.
2377	*/
2378	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2379	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2380	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2381
2382	if (
2383	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2384	pPml4eSrc->n.u1Present &&
2385	# endif
2386	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2387	pPdpeSrc->n.u1Present &&
2388	# endif
2389	pPdeSrc->n.u1Present)
2390	{
2391	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2392	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2393	{
2394	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2395	}
2396	else
2397	{
2398	/*
2399	* Map the guest page table.
2400	*/
2401	PGSTPT pPTSrc;
2402	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2403	if (RT_SUCCESS(rc))
2404	{
2405	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2406	const GSTPTE PteSrc = *pPteSrc;
2407	if (pPteSrc->n.u1Present)
2408	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2409	}
2410	AssertRC(rc);
2411	}
2412	}
2413	return VINF_EM_RAW_GUEST_TRAP;
2414	}
2415	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2416
2417
2418	/**
2419	* Sync a shadow page table.
2420	*
2421	* The shadow page table is not present. This includes the case where
2422	* there is a conflict with a mapping.
2423	*
2424	* @returns VBox status code.
2425	* @param pVCpu The VMCPU handle.
2426	* @param iPD Page directory index.
2427	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2428	* Assume this is a temporary mapping.
2429	* @param GCPtrPage GC Pointer of the page that caused the fault
2430	*/
2431	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2432	{
2433	PVM pVM = pVCpu->CTX_SUFF(pVM);
2434	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2435
2436	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2437	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2438	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2439
2440	Assert(PGMIsLocked(pVM));
2441
2442	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2443	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2444	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2446	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2447
2448	int rc = VINF_SUCCESS;
2449
2450	/*
2451	* Validate input a little bit.
2452	*/
2453	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2454	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2455	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2456	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2457
2458	/* Fetch the pgm pool shadow descriptor. */
2459	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2460	Assert(pShwPde);
2461
2462	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2463	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2464	PPGMPOOLPAGE pShwPde = NULL;
2465	PX86PDPAE pPDDst;
2466	PSHWPDE pPdeDst;
2467
2468	/* Fetch the pgm pool shadow descriptor. */
2469	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2470	AssertRCSuccessReturn(rc, rc);
2471	Assert(pShwPde);
2472
2473	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2474	pPdeDst = &pPDDst->a[iPDDst];
2475
2476	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2477	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2478	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2479	PX86PDPAE pPDDst;
2480	PX86PDPT pPdptDst;
2481	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2482	AssertRCSuccessReturn(rc, rc);
2483	Assert(pPDDst);
2484	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2485	# endif
2486	SHWPDE PdeDst = *pPdeDst;
2487
2488	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2489	/* Fetch the pgm pool shadow descriptor. */
2490	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2491	Assert(pShwPde);
2492	# endif
2493
2494	# ifndef PGM_WITHOUT_MAPPINGS
2495	/*
2496	* Check for conflicts.
2497	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2498	* HC: Simply resolve the conflict.
2499	*/
2500	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2501	{
2502	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2503	# ifndef IN_RING3
2504	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2505	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2506	return VERR_ADDRESS_CONFLICT;
2507	# else
2508	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2509	Assert(pMapping);
2510	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2511	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2512	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2513	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2514	# else
2515	AssertFailed(); /* can't happen for amd64 */
2516	# endif
2517	if (RT_FAILURE(rc))
2518	{
2519	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2520	return rc;
2521	}
2522	PdeDst = *pPdeDst;
2523	# endif
2524	}
2525	# else /* PGM_WITHOUT_MAPPINGS */
2526	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2527	# endif /* PGM_WITHOUT_MAPPINGS */
2528	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2529
2530	# if defined(IN_RC)
2531	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2532	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2533	# endif
2534
2535	/*
2536	* Sync page directory entry.
2537	*/
2538	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2539	if (PdeSrc.n.u1Present)
2540	{
2541	/*
2542	* Allocate & map the page table.
2543	*/
2544	PSHWPT pPTDst;
2545	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2546	const bool fPageTable = !PdeSrc.b.u1Size;
2547	# else
2548	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2549	# endif
2550	PPGMPOOLPAGE pShwPage;
2551	RTGCPHYS GCPhys;
2552	if (fPageTable)
2553	{
2554	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2555	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2556	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2557	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2558	# endif
2559	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2560	}
2561	else
2562	{
2563	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2564	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2565	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2566	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2567	# endif
2568	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2569	}
2570	if (rc == VINF_SUCCESS)
2571	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2572	else if (rc == VINF_PGM_CACHED_PAGE)
2573	{
2574	/*
2575	* The PT was cached, just hook it up.
2576	*/
2577	if (fPageTable)
2578	PdeDst.u = pShwPage->Core.Key
2579	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2580	else
2581	{
2582	PdeDst.u = pShwPage->Core.Key
2583	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2584	/* (see explanation and assumptions further down.) */
2585	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2586	{
2587	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2588	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2589	PdeDst.b.u1Write = 0;
2590	}
2591	}
2592	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2593	# if defined(IN_RC)
2594	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2595	# endif
2596	return VINF_SUCCESS;
2597	}
2598	else if (rc == VERR_PGM_POOL_FLUSHED)
2599	{
2600	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2601	# if defined(IN_RC)
2602	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2603	# endif
2604	return VINF_PGM_SYNC_CR3;
2605	}
2606	else
2607	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2608	PdeDst.u &= X86_PDE_AVL_MASK;
2609	PdeDst.u \|= pShwPage->Core.Key;
2610
2611	/*
2612	* Page directory has been accessed (this is a fault situation, remember).
2613	*/
2614	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2615	if (fPageTable)
2616	{
2617	/*
2618	* Page table - 4KB.
2619	*
2620	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2621	*/
2622	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2623	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2624	PGSTPT pPTSrc;
2625	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2626	if (RT_SUCCESS(rc))
2627	{
2628	/*
2629	* Start by syncing the page directory entry so CSAM's TLB trick works.
2630	*/
2631	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2632	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2633	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2634	# if defined(IN_RC)
2635	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2636	# endif
2637
2638	/*
2639	* Directory/page user or supervisor privilege: (same goes for read/write)
2640	*
2641	* Directory Page Combined
2642	* U/S U/S U/S
2643	* 0 0 0
2644	* 0 1 0
2645	* 1 0 0
2646	* 1 1 1
2647	*
2648	* Simple AND operation. Table listed for completeness.
2649	*
2650	*/
2651	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2652	# ifdef PGM_SYNC_N_PAGES
2653	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2654	unsigned iPTDst = iPTBase;
2655	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2656	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2657	iPTDst = 0;
2658	else
2659	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2660	# else /* !PGM_SYNC_N_PAGES */
2661	unsigned iPTDst = 0;
2662	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2663	# endif /* !PGM_SYNC_N_PAGES */
2664	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2665	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2666	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2667	# else
2668	const unsigned offPTSrc = 0;
2669	# endif
2670	for (; iPTDst < iPTDstEnd; iPTDst++)
2671	{
2672	const unsigned iPTSrc = iPTDst + offPTSrc;
2673	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2674
2675	if (PteSrc.n.u1Present) /* we've already cleared it above */
2676	{
2677	# ifndef IN_RING0
2678	/*
2679	* Assuming kernel code will be marked as supervisor - and not as user level
2680	* and executed using a conforming code selector - And marked as readonly.
2681	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2682	*/
2683	PPGMPAGE pPage;
2684	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2685	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2686	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2687	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2688	)
2689	# endif
2690	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2691	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2692	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2693	PteSrc.n.u1Present,
2694	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2695	PteSrc.n.u1User & PdeSrc.n.u1User,
2696	(uint64_t)PteSrc.u,
2697	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2698	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2699	}
2700	} /* for PTEs */
2701	}
2702	}
2703	else
2704	{
2705	/*
2706	* Big page - 2/4MB.
2707	*
2708	* We'll walk the ram range list in parallel and optimize lookups.
2709	* We will only sync on shadow page table at a time.
2710	*/
2711	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2712
2713	/**
2714	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2715	*/
2716
2717	/*
2718	* Start by syncing the page directory entry.
2719	*/
2720	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2721	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2722
2723	/*
2724	* If the page is not flagged as dirty and is writable, then make it read-only
2725	* at PD level, so we can set the dirty bit when the page is modified.
2726	*
2727	* ASSUMES that page access handlers are implemented on page table entry level.
2728	* Thus we will first catch the dirty access and set PDE.D and restart. If
2729	* there is an access handler, we'll trap again and let it work on the problem.
2730	*/
2731	/** @todo move the above stuff to a section in the PGM documentation. */
2732	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2733	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2734	{
2735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2736	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2737	PdeDst.b.u1Write = 0;
2738	}
2739	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2740	# if defined(IN_RC)
2741	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2742	# endif
2743
2744	/*
2745	* Fill the shadow page table.
2746	*/
2747	/* Get address and flags from the source PDE. */
2748	SHWPTE PteDstBase;
2749	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2750
2751	/* Loop thru the entries in the shadow PT. */
2752	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2753	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2754	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2755	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2756	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2757	unsigned iPTDst = 0;
2758	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2759	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2760	{
2761	/* Advance ram range list. */
2762	while (pRam && GCPhys > pRam->GCPhysLast)
2763	pRam = pRam->CTX_SUFF(pNext);
2764	if (pRam && GCPhys >= pRam->GCPhys)
2765	{
2766	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2767	do
2768	{
2769	/* Make shadow PTE. */
2770	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2771	SHWPTE PteDst;
2772
2773	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2774	/* Try make the page writable if necessary. */
2775	if ( PteDstBase.n.u1Write
2776	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2777	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2778	{
2779	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2780	AssertRCReturn(rc, rc);
2781	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2782	break;
2783	}
2784	# endif
2785
2786	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2787	{
2788	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2789	{
2790	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2791	PteDst.n.u1Write = 0;
2792	}
2793	else
2794	PteDst.u = 0;
2795	}
2796	# ifndef IN_RING0
2797	/*
2798	* Assuming kernel code will be marked as supervisor and not as user level and executed
2799	* using a conforming code selector. Don't check for readonly, as that implies the whole
2800	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2801	*/
2802	else if ( !PdeSrc.n.u1User
2803	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2804	PteDst.u = 0;
2805	# endif
2806	else
2807	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2808
2809	/* Only map writable pages writable. */
2810	if ( PteDst.n.u1Write
2811	&& PteDst.n.u1Present
2812	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2813	{
2814	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2815	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2816	}
2817
2818	# ifdef PGMPOOL_WITH_USER_TRACKING
2819	if (PteDst.n.u1Present)
2820	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2821	# endif
2822	/* commit it */
2823	pPTDst->a[iPTDst] = PteDst;
2824	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2825	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2826	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2827
2828	/* advance */
2829	GCPhys += PAGE_SIZE;
2830	iHCPage++;
2831	iPTDst++;
2832	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2833	&& GCPhys <= pRam->GCPhysLast);
2834	}
2835	else if (pRam)
2836	{
2837	Log(("Invalid pages at %RGp\n", GCPhys));
2838	do
2839	{
2840	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2841	GCPhys += PAGE_SIZE;
2842	iPTDst++;
2843	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2844	&& GCPhys < pRam->GCPhys);
2845	}
2846	else
2847	{
2848	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2849	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2850	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2851	}
2852	} /* while more PTEs */
2853	} /* 4KB / 4MB */
2854	}
2855	else
2856	AssertRelease(!PdeDst.n.u1Present);
2857
2858	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2859	if (RT_FAILURE(rc))
2860	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2861	return rc;
2862
2863	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2864	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2865	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2866	&& !defined(IN_RC)
2867
2868	/*
2869	* Validate input a little bit.
2870	*/
2871	int rc = VINF_SUCCESS;
2872	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2873	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2874	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2875
2876	/* Fetch the pgm pool shadow descriptor. */
2877	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2878	Assert(pShwPde);
2879
2880	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2881	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2882	PPGMPOOLPAGE pShwPde;
2883	PX86PDPAE pPDDst;
2884	PSHWPDE pPdeDst;
2885
2886	/* Fetch the pgm pool shadow descriptor. */
2887	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2888	AssertRCSuccessReturn(rc, rc);
2889	Assert(pShwPde);
2890
2891	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2892	pPdeDst = &pPDDst->a[iPDDst];
2893
2894	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2895	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2896	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2897	PX86PDPAE pPDDst;
2898	PX86PDPT pPdptDst;
2899	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2900	AssertRCSuccessReturn(rc, rc);
2901	Assert(pPDDst);
2902	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2903
2904	/* Fetch the pgm pool shadow descriptor. */
2905	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2906	Assert(pShwPde);
2907
2908	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2909	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2910	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2911	PEPTPD pPDDst;
2912	PEPTPDPT pPdptDst;
2913
2914	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2915	if (rc != VINF_SUCCESS)
2916	{
2917	AssertRC(rc);
2918	return rc;
2919	}
2920	Assert(pPDDst);
2921	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2922
2923	/* Fetch the pgm pool shadow descriptor. */
2924	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2925	Assert(pShwPde);
2926	# endif
2927	SHWPDE PdeDst = *pPdeDst;
2928
2929	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2930	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2931
2932	GSTPDE PdeSrc;
2933	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2934	PdeSrc.n.u1Present = 1;
2935	PdeSrc.n.u1Write = 1;
2936	PdeSrc.n.u1Accessed = 1;
2937	PdeSrc.n.u1User = 1;
2938
2939	/*
2940	* Allocate & map the page table.
2941	*/
2942	PSHWPT pPTDst;
2943	PPGMPOOLPAGE pShwPage;
2944	RTGCPHYS GCPhys;
2945
2946	/* Virtual address = physical address */
2947	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2948	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2949
2950	if ( rc == VINF_SUCCESS
2951	\|\| rc == VINF_PGM_CACHED_PAGE)
2952	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2953	else
2954	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2955
2956	PdeDst.u &= X86_PDE_AVL_MASK;
2957	PdeDst.u \|= pShwPage->Core.Key;
2958	PdeDst.n.u1Present = 1;
2959	PdeDst.n.u1Write = 1;
2960	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2961	PdeDst.n.u1Execute = 1;
2962	# else
2963	PdeDst.n.u1User = 1;
2964	PdeDst.n.u1Accessed = 1;
2965	# endif
2966	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2967
2968	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2969	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2970	return rc;
2971
2972	#else
2973	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2974	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2975	return VERR_INTERNAL_ERROR;
2976	#endif
2977	}
2978
2979
2980
2981	/**
2982	* Prefetch a page/set of pages.
2983	*
2984	* Typically used to sync commonly used pages before entering raw mode
2985	* after a CR3 reload.
2986	*
2987	* @returns VBox status code.
2988	* @param pVCpu The VMCPU handle.
2989	* @param GCPtrPage Page to invalidate.
2990	*/
2991	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
2992	{
2993	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2994	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
2995	/*
2996	* Check that all Guest levels thru the PDE are present, getting the
2997	* PD and PDE in the processes.
2998	*/
2999	int rc = VINF_SUCCESS;
3000	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3001	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3002	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3003	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3004	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3005	unsigned iPDSrc;
3006	X86PDPE PdpeSrc;
3007	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3008	if (!pPDSrc)
3009	return VINF_SUCCESS; /* not present */
3010	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3011	unsigned iPDSrc;
3012	PX86PML4E pPml4eSrc;
3013	X86PDPE PdpeSrc;
3014	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3015	if (!pPDSrc)
3016	return VINF_SUCCESS; /* not present */
3017	# endif
3018	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3019	# else
3020	PGSTPD pPDSrc = NULL;
3021	const unsigned iPDSrc = 0;
3022	GSTPDE PdeSrc;
3023
3024	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3025	PdeSrc.n.u1Present = 1;
3026	PdeSrc.n.u1Write = 1;
3027	PdeSrc.n.u1Accessed = 1;
3028	PdeSrc.n.u1User = 1;
3029	# endif
3030
3031	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3032	{
3033	PVM pVM = pVCpu->CTX_SUFF(pVM);
3034	pgmLock(pVM);
3035
3036	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3037	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3038	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3039	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3040	PX86PDPAE pPDDst;
3041	X86PDEPAE PdeDst;
3042	# if PGM_GST_TYPE != PGM_TYPE_PAE
3043	X86PDPE PdpeSrc;
3044
3045	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3046	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3047	# endif
3048	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3049	if (rc != VINF_SUCCESS)
3050	{
3051	pgmUnlock(pVM);
3052	AssertRC(rc);
3053	return rc;
3054	}
3055	Assert(pPDDst);
3056	PdeDst = pPDDst->a[iPDDst];
3057
3058	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3059	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3060	PX86PDPAE pPDDst;
3061	X86PDEPAE PdeDst;
3062
3063	# if PGM_GST_TYPE == PGM_TYPE_PROT
3064	/* AMD-V nested paging */
3065	X86PML4E Pml4eSrc;
3066	X86PDPE PdpeSrc;
3067	PX86PML4E pPml4eSrc = &Pml4eSrc;
3068
3069	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3070	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3071	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3072	# endif
3073
3074	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3075	if (rc != VINF_SUCCESS)
3076	{
3077	pgmUnlock(pVM);
3078	AssertRC(rc);
3079	return rc;
3080	}
3081	Assert(pPDDst);
3082	PdeDst = pPDDst->a[iPDDst];
3083	# endif
3084	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3085	{
3086	if (!PdeDst.n.u1Present)
3087	{
3088	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3089	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3090	}
3091	else
3092	{
3093	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3094	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3095	* makes no sense to prefetch more than one page.
3096	*/
3097	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3098	if (RT_SUCCESS(rc))
3099	rc = VINF_SUCCESS;
3100	}
3101	}
3102	pgmUnlock(pVM);
3103	}
3104	return rc;
3105
3106	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3107	return VINF_SUCCESS; /* ignore */
3108	#endif
3109	}
3110
3111
3112
3113
3114	/**
3115	* Syncs a page during a PGMVerifyAccess() call.
3116	*
3117	* @returns VBox status code (informational included).
3118	* @param pVCpu The VMCPU handle.
3119	* @param GCPtrPage The address of the page to sync.
3120	* @param fPage The effective guest page flags.
3121	* @param uErr The trap error code.
3122	*/
3123	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3124	{
3125	PVM pVM = pVCpu->CTX_SUFF(pVM);
3126
3127	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3128
3129	Assert(!HWACCMIsNestedPagingActive(pVM));
3130	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3131	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3132
3133	# ifndef IN_RING0
3134	if (!(fPage & X86_PTE_US))
3135	{
3136	/*
3137	* Mark this page as safe.
3138	*/
3139	/** @todo not correct for pages that contain both code and data!! */
3140	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3141	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3142	}
3143	# endif
3144
3145	/*
3146	* Get guest PD and index.
3147	*/
3148	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3149	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3150	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3151	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3152	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3153	unsigned iPDSrc = 0;
3154	X86PDPE PdpeSrc;
3155	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3156
3157	if (pPDSrc)
3158	{
3159	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3160	return VINF_EM_RAW_GUEST_TRAP;
3161	}
3162	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3163	unsigned iPDSrc;
3164	PX86PML4E pPml4eSrc;
3165	X86PDPE PdpeSrc;
3166	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3167	if (!pPDSrc)
3168	{
3169	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3170	return VINF_EM_RAW_GUEST_TRAP;
3171	}
3172	# endif
3173	# else
3174	PGSTPD pPDSrc = NULL;
3175	const unsigned iPDSrc = 0;
3176	# endif
3177	int rc = VINF_SUCCESS;
3178
3179	pgmLock(pVM);
3180
3181	/*
3182	* First check if the shadow pd is present.
3183	*/
3184	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3185	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3186	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3187	PX86PDEPAE pPdeDst;
3188	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3189	PX86PDPAE pPDDst;
3190	# if PGM_GST_TYPE != PGM_TYPE_PAE
3191	X86PDPE PdpeSrc;
3192
3193	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3194	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3195	# endif
3196	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3197	if (rc != VINF_SUCCESS)
3198	{
3199	pgmUnlock(pVM);
3200	AssertRC(rc);
3201	return rc;
3202	}
3203	Assert(pPDDst);
3204	pPdeDst = &pPDDst->a[iPDDst];
3205
3206	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3207	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3208	PX86PDPAE pPDDst;
3209	PX86PDEPAE pPdeDst;
3210
3211	# if PGM_GST_TYPE == PGM_TYPE_PROT
3212	/* AMD-V nested paging */
3213	X86PML4E Pml4eSrc;
3214	X86PDPE PdpeSrc;
3215	PX86PML4E pPml4eSrc = &Pml4eSrc;
3216
3217	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3218	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3219	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3220	# endif
3221
3222	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3223	if (rc != VINF_SUCCESS)
3224	{
3225	pgmUnlock(pVM);
3226	AssertRC(rc);
3227	return rc;
3228	}
3229	Assert(pPDDst);
3230	pPdeDst = &pPDDst->a[iPDDst];
3231	# endif
3232
3233	# if defined(IN_RC)
3234	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3235	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3236	# endif
3237
3238	if (!pPdeDst->n.u1Present)
3239	{
3240	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3241	if (rc != VINF_SUCCESS)
3242	{
3243	# if defined(IN_RC)
3244	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3245	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3246	# endif
3247	pgmUnlock(pVM);
3248	AssertRC(rc);
3249	return rc;
3250	}
3251	}
3252
3253	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3254	/* Check for dirty bit fault */
3255	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3256	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3257	Log(("PGMVerifyAccess: success (dirty)\n"));
3258	else
3259	{
3260	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3261	# else
3262	{
3263	GSTPDE PdeSrc;
3264	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3265	PdeSrc.n.u1Present = 1;
3266	PdeSrc.n.u1Write = 1;
3267	PdeSrc.n.u1Accessed = 1;
3268	PdeSrc.n.u1User = 1;
3269
3270	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3271	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3272	if (uErr & X86_TRAP_PF_US)
3273	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3274	else /* supervisor */
3275	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3276
3277	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3278	if (RT_SUCCESS(rc))
3279	{
3280	/* Page was successfully synced */
3281	Log2(("PGMVerifyAccess: success (sync)\n"));
3282	rc = VINF_SUCCESS;
3283	}
3284	else
3285	{
3286	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3287	rc = VINF_EM_RAW_GUEST_TRAP;
3288	}
3289	}
3290	# if defined(IN_RC)
3291	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3292	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3293	# endif
3294	pgmUnlock(pVM);
3295	return rc;
3296
3297	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3298
3299	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3300	return VERR_INTERNAL_ERROR;
3301	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3302	}
3303
3304
3305	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3306	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3307	/**
3308	* Figures out which kind of shadow page this guest PDE warrants.
3309	*
3310	* @returns Shadow page kind.
3311	* @param pPdeSrc The guest PDE in question.
3312	* @param cr4 The current guest cr4 value.
3313	*/
3314	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3315	{
3316	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3317	if (!pPdeSrc->n.u1Size)
3318	# else
3319	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3320	# endif
3321	return BTH_PGMPOOLKIND_PT_FOR_PT;
3322	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3323	//{
3324	// case 0:
3325	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3326	// case X86_PDE4M_RW:
3327	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3328	// case X86_PDE4M_US:
3329	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3330	// case X86_PDE4M_RW \| X86_PDE4M_US:
3331	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3332	# if 0
3333	// case X86_PDE4M_PAE_NX:
3334	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3335	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3336	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3337	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3338	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3339	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3340	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3341	# endif
3342	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3343	//}
3344	}
3345	# endif
3346	#endif
3347
3348	#undef MY_STAM_COUNTER_INC
3349	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3350
3351
3352	/**
3353	* Syncs the paging hierarchy starting at CR3.
3354	*
3355	* @returns VBox status code, no specials.
3356	* @param pVCpu The VMCPU handle.
3357	* @param cr0 Guest context CR0 register
3358	* @param cr3 Guest context CR3 register
3359	* @param cr4 Guest context CR4 register
3360	* @param fGlobal Including global page directories or not
3361	*/
3362	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3363	{
3364	PVM pVM = pVCpu->CTX_SUFF(pVM);
3365
3366	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3367	fGlobal = true; /* Change this CR3 reload to be a global one. */
3368
3369	LogFlow(("SyncCR3 %d\n", fGlobal));
3370
3371	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3372	/*
3373	* Update page access handlers.
3374	* The virtual are always flushed, while the physical are only on demand.
3375	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3376	* have to look into that later because it will have a bad influence on the performance.
3377	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3378	* bird: Yes, but that won't work for aliases.
3379	*/
3380	/** @todo this MUST go away. See #1557. */
3381	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3382	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3383	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3384	#endif
3385
3386	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3387	/*
3388	* Nested / EPT - almost no work.
3389	*/
3390	/** @todo check if this is really necessary; the call does it as well... */
3391	HWACCMFlushTLB(pVM);
3392	return VINF_SUCCESS;
3393
3394	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3395	/*
3396	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3397	* out the shadow parts when the guest modifies its tables.
3398	*/
3399	return VINF_SUCCESS;
3400
3401	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3402
3403	# ifdef PGM_WITHOUT_MAPPINGS
3404	Assert(pVM->pgm.s.fMappingsFixed);
3405	return VINF_SUCCESS;
3406	# else
3407	/* Nothing to do when mappings are fixed. */
3408	if (pVM->pgm.s.fMappingsFixed)
3409	return VINF_SUCCESS;
3410
3411	int rc = PGMMapResolveConflicts(pVM);
3412	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3413	if (rc == VINF_PGM_SYNC_CR3)
3414	{
3415	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3416	return VINF_PGM_SYNC_CR3;
3417	}
3418	# endif
3419	return VINF_SUCCESS;
3420	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3421	}
3422
3423
3424
3425
3426	#ifdef VBOX_STRICT
3427	#ifdef IN_RC
3428	# undef AssertMsgFailed
3429	# define AssertMsgFailed Log
3430	#endif
3431	#ifdef IN_RING3
3432	# include <VBox/dbgf.h>
3433
3434	/**
3435	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3436	*
3437	* @returns VBox status code (VINF_SUCCESS).
3438	* @param cr3 The root of the hierarchy.
3439	* @param crr The cr4, only PAE and PSE is currently used.
3440	* @param fLongMode Set if long mode, false if not long mode.
3441	* @param cMaxDepth Number of levels to dump.
3442	* @param pHlp Pointer to the output functions.
3443	*/
3444	__BEGIN_DECLS
3445	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3446	__END_DECLS
3447
3448	#endif
3449
3450	/**
3451	* Checks that the shadow page table is in sync with the guest one.
3452	*
3453	* @returns The number of errors.
3454	* @param pVM The virtual machine.
3455	* @param pVCpu The VMCPU handle.
3456	* @param cr3 Guest context CR3 register
3457	* @param cr4 Guest context CR4 register
3458	* @param GCPtr Where to start. Defaults to 0.
3459	* @param cb How much to check. Defaults to everything.
3460	*/
3461	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3462	{
3463	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3464	return 0;
3465	#else
3466	unsigned cErrors = 0;
3467	PVM pVM = pVCpu->CTX_SUFF(pVM);
3468	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3469
3470	#if PGM_GST_TYPE == PGM_TYPE_PAE
3471	/** @todo currently broken; crashes below somewhere */
3472	AssertFailed();
3473	#endif
3474
3475	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3476	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3477	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3478
3479	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3480	bool fBigPagesSupported = true;
3481	# else
3482	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3483	# endif
3484	PPGMCPU pPGM = &pVCpu->pgm.s;
3485	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3486	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3487	# ifndef IN_RING0
3488	RTHCPHYS HCPhys; /* general usage. */
3489	# endif
3490	int rc;
3491
3492	/*
3493	* Check that the Guest CR3 and all its mappings are correct.
3494	*/
3495	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3496	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3497	false);
3498	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3499	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3500	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3501	# else
3502	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3503	# endif
3504	AssertRCReturn(rc, 1);
3505	HCPhys = NIL_RTHCPHYS;
3506	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3507	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3508	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3509	pgmGstGet32bitPDPtr(pPGM);
3510	RTGCPHYS GCPhys;
3511	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3512	AssertRCReturn(rc, 1);
3513	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3514	# endif
3515	# endif /* !IN_RING0 */
3516
3517	/*
3518	* Get and check the Shadow CR3.
3519	*/
3520	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3521	unsigned cPDEs = X86_PG_ENTRIES;
3522	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3523	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3524	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3525	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3526	# else
3527	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3528	# endif
3529	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3530	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3531	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3532	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3533	# endif
3534	if (cb != ~(RTGCPTR)0)
3535	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3536
3537	/** @todo call the other two PGMAssert() functions. /
3538
3539	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3540	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3541
3542	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3543	{
3544	PPGMPOOLPAGE pShwPdpt = NULL;
3545	PX86PML4E pPml4eSrc;
3546	PX86PML4E pPml4eDst;
3547	RTGCPHYS GCPhysPdptSrc;
3548
3549	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3550	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3551
3552	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3553	if (!pPml4eDst->n.u1Present)
3554	{
3555	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3556	continue;
3557	}
3558
3559	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3560	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3561
3562	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3563	{
3564	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3565	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3566	cErrors++;
3567	continue;
3568	}
3569
3570	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3571	{
3572	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3573	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3574	cErrors++;
3575	continue;
3576	}
3577
3578	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3579	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3580	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3581	{
3582	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3583	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3584	cErrors++;
3585	continue;
3586	}
3587	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3588	{
3589	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3590
3591	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3592	/*
3593	* Check the PDPTEs too.
3594	*/
3595	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3596
3597	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3598	{
3599	unsigned iPDSrc;
3600	PPGMPOOLPAGE pShwPde = NULL;
3601	PX86PDPE pPdpeDst;
3602	RTGCPHYS GCPhysPdeSrc;
3603	# if PGM_GST_TYPE == PGM_TYPE_PAE
3604	X86PDPE PdpeSrc;
3605	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3606	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3607	# else
3608	PX86PML4E pPml4eSrc;
3609	X86PDPE PdpeSrc;
3610	PX86PDPT pPdptDst;
3611	PX86PDPAE pPDDst;
3612	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3613
3614	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3615	if (rc != VINF_SUCCESS)
3616	{
3617	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3618	GCPtr += 512 * _2M;
3619	continue; /* next PDPTE */
3620	}
3621	Assert(pPDDst);
3622	# endif
3623	Assert(iPDSrc == 0);
3624
3625	pPdpeDst = &pPdptDst->a[iPdpt];
3626
3627	if (!pPdpeDst->n.u1Present)
3628	{
3629	GCPtr += 512 * _2M;
3630	continue; /* next PDPTE */
3631	}
3632
3633	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3634	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3635
3636	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3637	{
3638	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3639	GCPtr += 512 * _2M;
3640	cErrors++;
3641	continue;
3642	}
3643
3644	if (GCPhysPdeSrc != pShwPde->GCPhys)
3645	{
3646	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3647	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3648	# else
3649	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3650	# endif
3651	GCPtr += 512 * _2M;
3652	cErrors++;
3653	continue;
3654	}
3655
3656	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3657	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3658	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3659	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3660	{
3661	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3662	GCPtr += 512 * _2M;
3663	cErrors++;
3664	continue;
3665	}
3666	# endif
3667
3668	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3669	{
3670	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3671	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3672	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3673	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3674	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3675	# endif
3676	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3677	/*
3678	* Iterate the shadow page directory.
3679	*/
3680	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3681	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3682
3683	for (;
3684	iPDDst < cPDEs;
3685	iPDDst++, GCPtr += cIncrement)
3686	{
3687	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3688	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3689	# else
3690	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3691	# endif
3692	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3693	{
3694	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3695	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3696	{
3697	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3698	cErrors++;
3699	continue;
3700	}
3701	}
3702	else if ( (PdeDst.u & X86_PDE_P)
3703	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3704	)
3705	{
3706	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3707	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3708	if (!pPoolPage)
3709	{
3710	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3711	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3712	cErrors++;
3713	continue;
3714	}
3715	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3716
3717	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3718	{
3719	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3720	GCPtr, (uint64_t)PdeDst.u));
3721	cErrors++;
3722	}
3723
3724	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3725	{
3726	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3727	GCPtr, (uint64_t)PdeDst.u));
3728	cErrors++;
3729	}
3730
3731	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3732	if (!PdeSrc.n.u1Present)
3733	{
3734	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3735	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3736	cErrors++;
3737	continue;
3738	}
3739
3740	if ( !PdeSrc.b.u1Size
3741	\|\| !fBigPagesSupported)
3742	{
3743	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3744	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3745	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3746	# endif
3747	}
3748	else
3749	{
3750	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3751	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3752	{
3753	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3754	GCPtr, (uint64_t)PdeSrc.u));
3755	cErrors++;
3756	continue;
3757	}
3758	# endif
3759	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3760	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3761	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3762	# endif
3763	}
3764
3765	if ( pPoolPage->enmKind
3766	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3767	{
3768	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3769	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3770	cErrors++;
3771	}
3772
3773	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3774	if (!pPhysPage)
3775	{
3776	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3777	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3778	cErrors++;
3779	continue;
3780	}
3781
3782	if (GCPhysGst != pPoolPage->GCPhys)
3783	{
3784	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3785	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3786	cErrors++;
3787	continue;
3788	}
3789
3790	if ( !PdeSrc.b.u1Size
3791	\|\| !fBigPagesSupported)
3792	{
3793	/*
3794	* Page Table.
3795	*/
3796	const GSTPT *pPTSrc;
3797	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3798	if (RT_FAILURE(rc))
3799	{
3800	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3801	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3802	cErrors++;
3803	continue;
3804	}
3805	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3806	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3807	{
3808	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3809	// (This problem will go away when/if we shadow multiple CR3s.)
3810	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3811	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3812	cErrors++;
3813	continue;
3814	}
3815	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3816	{
3817	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3818	GCPtr, (uint64_t)PdeDst.u));
3819	cErrors++;
3820	continue;
3821	}
3822
3823	/* iterate the page table. */
3824	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3825	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3826	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3827	# else
3828	const unsigned offPTSrc = 0;
3829	# endif
3830	for (unsigned iPT = 0, off = 0;
3831	iPT < RT_ELEMENTS(pPTDst->a);
3832	iPT++, off += PAGE_SIZE)
3833	{
3834	const SHWPTE PteDst = pPTDst->a[iPT];
3835
3836	/* skip not-present entries. */
3837	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3838	continue;
3839	Assert(PteDst.n.u1Present);
3840
3841	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3842	if (!PteSrc.n.u1Present)
3843	{
3844	# ifdef IN_RING3
3845	PGMAssertHandlerAndFlagsInSync(pVM);
3846	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3847	# endif
3848	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3849	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3850	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3851	cErrors++;
3852	continue;
3853	}
3854
3855	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3856	# if 1 /** @todo sync accessed bit properly... */
3857	fIgnoreFlags \|= X86_PTE_A;
3858	# endif
3859
3860	/* match the physical addresses */
3861	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3862	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3863
3864	# ifdef IN_RING3
3865	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3866	if (RT_FAILURE(rc))
3867	{
3868	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3869	{
3870	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3871	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3872	cErrors++;
3873	continue;
3874	}
3875	}
3876	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3877	{
3878	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3879	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3880	cErrors++;
3881	continue;
3882	}
3883	# endif
3884
3885	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3886	if (!pPhysPage)
3887	{
3888	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3889	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3890	{
3891	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3892	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3893	cErrors++;
3894	continue;
3895	}
3896	# endif
3897	if (PteDst.n.u1Write)
3898	{
3899	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3900	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3901	cErrors++;
3902	}
3903	fIgnoreFlags \|= X86_PTE_RW;
3904	}
3905	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3906	{
3907	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3908	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3909	cErrors++;
3910	continue;
3911	}
3912
3913	/* flags */
3914	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3915	{
3916	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3917	{
3918	if (PteDst.n.u1Write)
3919	{
3920	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3921	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3922	cErrors++;
3923	continue;
3924	}
3925	fIgnoreFlags \|= X86_PTE_RW;
3926	}
3927	else
3928	{
3929	if (PteDst.n.u1Present)
3930	{
3931	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3932	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3933	cErrors++;
3934	continue;
3935	}
3936	fIgnoreFlags \|= X86_PTE_P;
3937	}
3938	}
3939	else
3940	{
3941	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3942	{
3943	if (PteDst.n.u1Write)
3944	{
3945	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3946	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3947	cErrors++;
3948	continue;
3949	}
3950	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3951	{
3952	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3953	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3954	cErrors++;
3955	continue;
3956	}
3957	if (PteDst.n.u1Dirty)
3958	{
3959	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3960	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3961	cErrors++;
3962	}
3963	# if 0 /** @todo sync access bit properly... */
3964	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3965	{
3966	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3967	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3968	cErrors++;
3969	}
3970	fIgnoreFlags \|= X86_PTE_RW;
3971	# else
3972	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3973	# endif
3974	}
3975	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3976	{
3977	/* access bit emulation (not implemented). */
3978	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3979	{
3980	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3981	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3982	cErrors++;
3983	continue;
3984	}
3985	if (!PteDst.n.u1Accessed)
3986	{
3987	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3988	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3989	cErrors++;
3990	}
3991	fIgnoreFlags \|= X86_PTE_P;
3992	}
3993	# ifdef DEBUG_sandervl
3994	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3995	# endif
3996	}
3997
3998	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3999	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4000	)
4001	{
4002	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4003	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4004	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4005	cErrors++;
4006	continue;
4007	}
4008	} /* foreach PTE */
4009	}
4010	else
4011	{
4012	/*
4013	* Big Page.
4014	*/
4015	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4016	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4017	{
4018	if (PdeDst.n.u1Write)
4019	{
4020	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4021	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4022	cErrors++;
4023	continue;
4024	}
4025	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4026	{
4027	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4029	cErrors++;
4030	continue;
4031	}
4032	# if 0 /** @todo sync access bit properly... */
4033	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4034	{
4035	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4036	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4037	cErrors++;
4038	}
4039	fIgnoreFlags \|= X86_PTE_RW;
4040	# else
4041	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4042	# endif
4043	}
4044	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4045	{
4046	/* access bit emulation (not implemented). */
4047	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4048	{
4049	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4050	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4051	cErrors++;
4052	continue;
4053	}
4054	if (!PdeDst.n.u1Accessed)
4055	{
4056	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4057	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4058	cErrors++;
4059	}
4060	fIgnoreFlags \|= X86_PTE_P;
4061	}
4062
4063	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4064	{
4065	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4066	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4067	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4068	cErrors++;
4069	}
4070
4071	/* iterate the page table. */
4072	for (unsigned iPT = 0, off = 0;
4073	iPT < RT_ELEMENTS(pPTDst->a);
4074	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4075	{
4076	const SHWPTE PteDst = pPTDst->a[iPT];
4077
4078	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4079	{
4080	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4081	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4082	cErrors++;
4083	}
4084
4085	/* skip not-present entries. */
4086	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4087	continue;
4088
4089	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4090
4091	/* match the physical addresses */
4092	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4093
4094	# ifdef IN_RING3
4095	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4096	if (RT_FAILURE(rc))
4097	{
4098	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4099	{
4100	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4101	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4102	cErrors++;
4103	}
4104	}
4105	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4106	{
4107	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4108	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4109	cErrors++;
4110	continue;
4111	}
4112	# endif
4113	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4114	if (!pPhysPage)
4115	{
4116	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4117	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4118	{
4119	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4120	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4121	cErrors++;
4122	continue;
4123	}
4124	# endif
4125	if (PteDst.n.u1Write)
4126	{
4127	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4128	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4129	cErrors++;
4130	}
4131	fIgnoreFlags \|= X86_PTE_RW;
4132	}
4133	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4134	{
4135	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4136	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4137	cErrors++;
4138	continue;
4139	}
4140
4141	/* flags */
4142	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4143	{
4144	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4145	{
4146	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4147	{
4148	if (PteDst.n.u1Write)
4149	{
4150	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4151	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4152	cErrors++;
4153	continue;
4154	}
4155	fIgnoreFlags \|= X86_PTE_RW;
4156	}
4157	}
4158	else
4159	{
4160	if (PteDst.n.u1Present)
4161	{
4162	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4163	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4164	cErrors++;
4165	continue;
4166	}
4167	fIgnoreFlags \|= X86_PTE_P;
4168	}
4169	}
4170
4171	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4172	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4173	)
4174	{
4175	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4176	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4177	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4178	cErrors++;
4179	continue;
4180	}
4181	} /* for each PTE */
4182	}
4183	}
4184	/* not present */
4185
4186	} /* for each PDE */
4187
4188	} /* for each PDPTE */
4189
4190	} /* for each PML4E */
4191
4192	# ifdef DEBUG
4193	if (cErrors)
4194	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4195	# endif
4196
4197	#endif /* GST == 32BIT, PAE or AMD64 */
4198	return cErrors;
4199
4200	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4201	}
4202	#endif /* VBOX_STRICT */
4203
4204
4205	/**
4206	* Sets up the CR3 for shadow paging
4207	*
4208	* @returns Strict VBox status code.
4209	* @retval VINF_SUCCESS.
4210	*
4211	* @param pVCpu The VMCPU handle.
4212	* @param GCPhysCR3 The physical address in the CR3 register.
4213	*/
4214	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4215	{
4216	PVM pVM = pVCpu->CTX_SUFF(pVM);
4217
4218	/* Update guest paging info. */
4219	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4220	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4221	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4222
4223	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4224
4225	/*
4226	* Map the page CR3 points at.
4227	*/
4228	RTHCPTR HCPtrGuestCR3;
4229	RTHCPHYS HCPhysGuestCR3;
4230	pgmLock(pVM);
4231	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4232	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4233	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4234	/** @todo this needs some reworking wrt. locking. */
4235	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4236	HCPtrGuestCR3 = NIL_RTHCPTR;
4237	int rc = VINF_SUCCESS;
4238	# else
4239	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4240	# endif
4241	pgmUnlock(pVM);
4242	if (RT_SUCCESS(rc))
4243	{
4244	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4245	if (RT_SUCCESS(rc))
4246	{
4247	# ifdef IN_RC
4248	PGM_INVL_PG(pVM->pgm.s.GCPtrCR3Mapping);
4249	# endif
4250	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4251	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4252	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4253	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4254	# endif
4255	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4256
4257	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4258	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4259	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4260	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4261	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4262	# endif
4263	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4264	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4265
4266	/*
4267	* Map the 4 PDs too.
4268	*/
4269	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4270	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4271	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4272	{
4273	if (pGuestPDPT->a[i].n.u1Present)
4274	{
4275	RTHCPTR HCPtr;
4276	RTHCPHYS HCPhys;
4277	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4278	pgmLock(pVM);
4279	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4280	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4281	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4282	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4283	HCPtr = NIL_RTHCPTR;
4284	int rc2 = VINF_SUCCESS;
4285	# else
4286	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4287	# endif
4288	pgmUnlock(pVM);
4289	if (RT_SUCCESS(rc2))
4290	{
4291	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4292	AssertRCReturn(rc, rc);
4293
4294	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4295	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4296	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4297	# endif
4298	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4299	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4300	# ifdef IN_RC
4301	PGM_INVL_PG(GCPtr);
4302	# endif
4303	continue;
4304	}
4305	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4306	}
4307
4308	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4309	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4310	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4311	# endif
4312	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4313	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4314	# ifdef IN_RC
4315	PGM_INVL_PG(GCPtr); /** @todo this shouldn't be necessary? */
4316	# endif
4317	}
4318
4319	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4320	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4321	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4322	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4323	# endif
4324	# endif
4325	}
4326	else
4327	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4328	}
4329	else
4330	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4331
4332	#else /* prot/real stub */
4333	int rc = VINF_SUCCESS;
4334	#endif
4335
4336	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4337	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4338	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4339	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4340	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4341	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4342
4343	Assert(!HWACCMIsNestedPagingActive(pVM));
4344
4345	/*
4346	* Update the shadow root page as well since that's not fixed.
4347	*/
4348	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4349	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4350	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4351	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4352	PPGMPOOLPAGE pNewShwPageCR3;
4353
4354	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4355	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4356	AssertFatalRC(rc);
4357	rc = VINF_SUCCESS;
4358
4359	/* Mark the page as locked; disallow flushing. */
4360	pgmPoolLockPage(pPool, pNewShwPageCR3);
4361
4362	# ifdef IN_RC
4363	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4364	bool fLog = VMMGCLogDisable(pVM);
4365	pgmLock(pVM);
4366	# endif
4367
4368	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4369	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4370	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4371	# ifdef IN_RING0
4372	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4373	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4374	# elif defined(IN_RC)
4375	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4376	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4377	# else
4378	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4379	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4380	# endif
4381
4382	# ifndef PGM_WITHOUT_MAPPINGS
4383	/*
4384	* Apply all hypervisor mappings to the new CR3.
4385	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4386	* make sure we check for conflicts in the new CR3 root.
4387	*/
4388	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4389	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4390	# endif
4391	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4392	AssertRCReturn(rc, rc);
4393	# endif
4394
4395	/* Set the current hypervisor CR3. */
4396	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4397	SELMShadowCR3Changed(pVM, pVCpu);
4398
4399	# ifdef IN_RC
4400	pgmUnlock(pVM);
4401	VMMGCLogRestore(pVM, fLog);
4402	# endif
4403
4404	/* Clean up the old CR3 root. */
4405	if (pOldShwPageCR3)
4406	{
4407	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4408	# ifndef PGM_WITHOUT_MAPPINGS
4409	/* Remove the hypervisor mappings from the shadow page table. */
4410	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4411	# endif
4412	/* Mark the page as unlocked; allow flushing again. */
4413	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4414
4415	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4416	}
4417
4418	# endif
4419
4420	return rc;
4421	}
4422
4423	/**
4424	* Unmaps the shadow CR3.
4425	*
4426	* @returns VBox status, no specials.
4427	* @param pVCpu The VMCPU handle.
4428	*/
4429	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4430	{
4431	LogFlow(("UnmapCR3\n"));
4432
4433	int rc = VINF_SUCCESS;
4434	PVM pVM = pVCpu->CTX_SUFF(pVM);
4435
4436	/*
4437	* Update guest paging info.
4438	*/
4439	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4440	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4441	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4442	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4443	# endif
4444	pVCpu->pgm.s.pGst32BitPdRC = 0;
4445
4446	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4447	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4448	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4449	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4450	# endif
4451	pVCpu->pgm.s.pGstPaePdptRC = 0;
4452	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4453	{
4454	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4455	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4456	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4457	# endif
4458	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4459	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4460	}
4461
4462	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4463	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4464	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4465	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4466	# endif
4467
4468	#else /* prot/real mode stub */
4469	/* nothing to do */
4470	#endif
4471
4472	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4473	/*
4474	* Update shadow paging info.
4475	*/
4476	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4477	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4478	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4479
4480	# if PGM_GST_TYPE != PGM_TYPE_REAL
4481	Assert(!HWACCMIsNestedPagingActive(pVM));
4482	# endif
4483
4484	# ifndef PGM_WITHOUT_MAPPINGS
4485	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4486	/* Remove the hypervisor mappings from the shadow page table. */
4487	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4488	# endif
4489
4490	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4491	{
4492	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4493
4494	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4495
4496	/* Mark the page as unlocked; allow flushing again. */
4497	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4498
4499	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4500	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4501	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4502	pVCpu->pgm.s.pShwPageCR3RC = 0;
4503	pVCpu->pgm.s.iShwUser = 0;
4504	pVCpu->pgm.s.iShwUserTable = 0;
4505	}
4506	# endif
4507	#endif /* !IN_RC*/
4508
4509	return rc;
4510	}
4511

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 19791

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