PGMAllBth.h@ 19979

Last change on this file since 19979 was 19871, checked in by vboxsync, 16 years ago
Protect SyncPage with a lock as well.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 194.6 KB

Line
1	/* $Id: PGMAllBth.h 19871 2009-05-20 14:51:20Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc;
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc;
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	pgmLock(pVM);
165	{ /* Force the shadow pointers to go out of scope after releasing the lock. */
166	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
167	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
168	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
169
170	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
171	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
172
173	PX86PDPAE pPDDst;
174	# if PGM_GST_TYPE != PGM_TYPE_PAE
175	X86PDPE PdpeSrc;
176
177	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
178	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
179	# endif
180	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
181	if (rc != VINF_SUCCESS)
182	{
183	pgmUnlock(pVM);
184	AssertRC(rc);
185	return rc;
186	}
187	Assert(pPDDst);
188
189	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
190	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
191	PX86PDPAE pPDDst;
192	# if PGM_GST_TYPE == PGM_TYPE_PROT
193	/* AMD-V nested paging */
194	X86PML4E Pml4eSrc;
195	X86PDPE PdpeSrc;
196	PX86PML4E pPml4eSrc = &Pml4eSrc;
197
198	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
199	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
200	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
201	# endif
202
203	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
204	if (rc != VINF_SUCCESS)
205	{
206	pgmUnlock(pVM);
207	AssertRC(rc);
208	return rc;
209	}
210	Assert(pPDDst);
211
212	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
213	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
214	PEPTPD pPDDst;
215
216	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
217	if (rc != VINF_SUCCESS)
218	{
219	pgmUnlock(pVM);
220	AssertRC(rc);
221	return rc;
222	}
223	Assert(pPDDst);
224	# endif
225
226	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
227	/*
228	* If we successfully correct the write protection fault due to dirty bit
229	* tracking, or this page fault is a genuine one, then return immediately.
230	*/
231	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
232	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
233	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
234	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
235	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
236	{
237	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
238	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
239	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
240	pgmUnlock(pVM);
241	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
242	}
243
244	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
245	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
246
247	/*
248	* A common case is the not-present error caused by lazy page table syncing.
249	*
250	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
251	* so we can safely assume that the shadow PT is present when calling SyncPage later.
252	*
253	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
254	* of mapping conflict and defer to SyncCR3 in R3.
255	* (Again, we do NOT support access handlers for non-present guest pages.)
256	*
257	*/
258	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
259	&& !pPDDst->a[iPDDst].n.u1Present
260	&& PdeSrc.n.u1Present
261	)
262	{
263	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
264	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
265	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
267	pgmUnlock(pVM);
268	if (RT_SUCCESS(rc))
269	{
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return rc;
272	}
273	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
274	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
275	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
276	return VINF_PGM_SYNC_CR3;
277	}
278	pgmUnlock(pVM);
279	}
280
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
282	/*
283	* Check if this address is within any of our mappings.
284	*
285	* This is very fast and it's gonna save us a bit of effort below and prevent
286	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
287	* (BTW, it's impossible to have physical access handlers in a mapping.)
288	*/
289	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
290	{
291	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
292	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
293	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
294	{
295	if (pvFault < pMapping->GCPtr)
296	break;
297	if (pvFault - pMapping->GCPtr < pMapping->cb)
298	{
299	/*
300	* The first thing we check is if we've got an undetected conflict.
301	*/
302	if (!pVM->pgm.s.fMappingsFixed)
303	{
304	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
305	while (iPT-- > 0)
306	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
307	{
308	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
309	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
310	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
311	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
312	return VINF_PGM_SYNC_CR3;
313	}
314	}
315
316	/*
317	* Check if the fault address is in a virtual page access handler range.
318	*/
319	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
320	if ( pCur
321	&& pvFault - pCur->Core.Key < pCur->cb
322	&& uErr & X86_TRAP_PF_RW)
323	{
324	# ifdef IN_RC
325	STAM_PROFILE_START(&pCur->Stat, h);
326	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
327	STAM_PROFILE_STOP(&pCur->Stat, h);
328	# else
329	AssertFailed();
330	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
331	# endif
332	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
333	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
334	return rc;
335	}
336
337	/*
338	* Pretend we're not here and let the guest handle the trap.
339	*/
340	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
341	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
342	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
343	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
344	return VINF_EM_RAW_GUEST_TRAP;
345	}
346	}
347	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
348	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
349	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
350
351	/*
352	* Check if this fault address is flagged for special treatment,
353	* which means we'll have to figure out the physical address and
354	* check flags associated with it.
355	*
356	* ASSUME that we can limit any special access handling to pages
357	* in page tables which the guest believes to be present.
358	*/
359	if (PdeSrc.n.u1Present)
360	{
361	RTGCPHYS GCPhys = NIL_RTGCPHYS;
362
363	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
364	# if PGM_GST_TYPE == PGM_TYPE_AMD64
365	bool fBigPagesSupported = true;
366	# else
367	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
368	# endif
369	if ( PdeSrc.b.u1Size
370	&& fBigPagesSupported)
371	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
372	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
373	else
374	{
375	PGSTPT pPTSrc;
376	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
377	if (RT_SUCCESS(rc))
378	{
379	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
380	if (pPTSrc->a[iPTESrc].n.u1Present)
381	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
382	}
383	}
384	# else
385	/* No paging so the fault address is the physical address */
386	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
387	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
388
389	/*
390	* If we have a GC address we'll check if it has any flags set.
391	*/
392	if (GCPhys != NIL_RTGCPHYS)
393	{
394	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
395
396	PPGMPAGE pPage;
397	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
398	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
399	{
400	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
401	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
402	{
403	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
404	{
405	/*
406	* Physical page access handler.
407	*/
408	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
409	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
410	if (pCur)
411	{
412	# ifdef PGM_SYNC_N_PAGES
413	/*
414	* If the region is write protected and we got a page not present fault, then sync
415	* the pages. If the fault was caused by a read, then restart the instruction.
416	* In case of write access continue to the GC write handler.
417	*
418	* ASSUMES that there is only one handler per page or that they have similar write properties.
419	*/
420	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
421	&& !(uErr & X86_TRAP_PF_P))
422	{
423	pgmLock(pVM);
424	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
425	pgmUnlock(pVM);
426	if ( RT_FAILURE(rc)
427	\|\| !(uErr & X86_TRAP_PF_RW)
428	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
429	{
430	AssertRC(rc);
431	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
432	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
433	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
434	return rc;
435	}
436	}
437	# endif
438
439	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
440	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
441	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
442
443	# if defined(IN_RC) \|\| defined(IN_RING0)
444	if (pCur->CTX_SUFF(pfnHandler))
445	{
446	STAM_PROFILE_START(&pCur->Stat, h);
447	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
448	STAM_PROFILE_STOP(&pCur->Stat, h);
449	}
450	else
451	# endif
452	rc = VINF_EM_RAW_EMULATE_INSTR;
453	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
454	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
455	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
456	return rc;
457	}
458	}
459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
460	else
461	{
462	# ifdef PGM_SYNC_N_PAGES
463	/*
464	* If the region is write protected and we got a page not present fault, then sync
465	* the pages. If the fault was caused by a read, then restart the instruction.
466	* In case of write access continue to the GC write handler.
467	*/
468	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
469	&& !(uErr & X86_TRAP_PF_P))
470	{
471	pgmLock(pVM);
472	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
473	pgmUnlock(pVM);
474	if ( RT_FAILURE(rc)
475	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
476	\|\| !(uErr & X86_TRAP_PF_RW))
477	{
478	AssertRC(rc);
479	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
480	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
481	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
482	return rc;
483	}
484	}
485	# endif
486	/*
487	* Ok, it's an virtual page access handler.
488	*
489	* Since it's faster to search by address, we'll do that first
490	* and then retry by GCPhys if that fails.
491	*/
492	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
493	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
494	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
495	*/
496	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
497	if (pCur)
498	{
499	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
500	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
501	\|\| !(uErr & X86_TRAP_PF_P)
502	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
503	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
504
505	if ( pvFault - pCur->Core.Key < pCur->cb
506	&& ( uErr & X86_TRAP_PF_RW
507	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
508	{
509	# ifdef IN_RC
510	STAM_PROFILE_START(&pCur->Stat, h);
511	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
512	STAM_PROFILE_STOP(&pCur->Stat, h);
513	# else
514	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
515	# endif
516	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
517	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
518	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
519	return rc;
520	}
521	/* Unhandled part of a monitored page */
522	}
523	else
524	{
525	/* Check by physical address. */
526	PPGMVIRTHANDLER pCur;
527	unsigned iPage;
528	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
529	&pCur, &iPage);
530	Assert(RT_SUCCESS(rc) \|\| !pCur);
531	if ( pCur
532	&& ( uErr & X86_TRAP_PF_RW
533	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
534	{
535	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
536	# ifdef IN_RC
537	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
538	Assert(off < pCur->cb);
539	STAM_PROFILE_START(&pCur->Stat, h);
540	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
541	STAM_PROFILE_STOP(&pCur->Stat, h);
542	# else
543	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
544	# endif
545	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
546	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
547	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
548	return rc;
549	}
550	}
551	}
552	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
553
554	/*
555	* There is a handled area of the page, but this fault doesn't belong to it.
556	* We must emulate the instruction.
557	*
558	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
559	* we first check if this was a page-not-present fault for a page with only
560	* write access handlers. Restart the instruction if it wasn't a write access.
561	*/
562	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
563
564	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
565	&& !(uErr & X86_TRAP_PF_P))
566	{
567	pgmLock(pVM);
568	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
569	pgmUnlock(pVM);
570	if ( RT_FAILURE(rc)
571	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
572	\|\| !(uErr & X86_TRAP_PF_RW))
573	{
574	AssertRC(rc);
575	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
576	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
577	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
578	return rc;
579	}
580	}
581
582	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
583	* It's writing to an unhandled part of the LDT page several million times.
584	*/
585	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
586	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
587	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
588	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
589	return rc;
590	} /* if any kind of handler */
591
592	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
593	if (uErr & X86_TRAP_PF_P)
594	{
595	/*
596	* The page isn't marked, but it might still be monitored by a virtual page access handler.
597	* (ASSUMES no temporary disabling of virtual handlers.)
598	*/
599	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
600	* we should correct both the shadow page table and physical memory flags, and not only check for
601	* accesses within the handler region but for access to pages with virtual handlers. */
602	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
603	if (pCur)
604	{
605	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
606	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
607	\|\| !(uErr & X86_TRAP_PF_P)
608	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
609	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
610
611	if ( pvFault - pCur->Core.Key < pCur->cb
612	&& ( uErr & X86_TRAP_PF_RW
613	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
614	{
615	# ifdef IN_RC
616	STAM_PROFILE_START(&pCur->Stat, h);
617	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
618	STAM_PROFILE_STOP(&pCur->Stat, h);
619	# else
620	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
621	# endif
622	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
623	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
624	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
625	return rc;
626	}
627	}
628	}
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630	}
631	else
632	{
633	/*
634	* When the guest accesses invalid physical memory (e.g. probing
635	* of RAM or accessing a remapped MMIO range), then we'll fall
636	* back to the recompiler to emulate the instruction.
637	*/
638	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
639	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
640	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
641	return VINF_EM_RAW_EMULATE_INSTR;
642	}
643
644	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
645
646	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
647	/*
648	* We are here only if page is present in Guest page tables and
649	* trap is not handled by our handlers.
650	*
651	* Check it for page out-of-sync situation.
652	*/
653	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
654
655	if (!(uErr & X86_TRAP_PF_P))
656	{
657	/*
658	* Page is not present in our page tables.
659	* Try to sync it!
660	* BTW, fPageShw is invalid in this branch!
661	*/
662	if (uErr & X86_TRAP_PF_US)
663	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
664	else /* supervisor */
665	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
666
667	# if defined(LOG_ENABLED) && !defined(IN_RING0)
668	RTGCPHYS GCPhys;
669	uint64_t fPageGst;
670	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
671	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
672	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
673	# endif /* LOG_ENABLED */
674
675	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
676	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
677	{
678	uint64_t fPageGst;
679	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
680	if ( RT_SUCCESS(rc)
681	&& !(fPageGst & X86_PTE_US))
682	{
683	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
684	if ( pvFault == (RTGCPTR)pRegFrame->eip
685	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
686	# ifdef CSAM_DETECT_NEW_CODE_PAGES
687	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
688	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
689	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
690	)
691	{
692	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
693	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
694	if (rc != VINF_SUCCESS)
695	{
696	/*
697	* CSAM needs to perform a job in ring 3.
698	*
699	* Sync the page before going to the host context; otherwise we'll end up in a loop if
700	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
701	*/
702	LogFlow(("CSAM ring 3 job\n"));
703	pgmLock(pVM);
704	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
705	pgmUnlock(pVM);
706	AssertRC(rc2);
707
708	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
709	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
710	return rc;
711	}
712	}
713	# ifdef CSAM_DETECT_NEW_CODE_PAGES
714	else if ( uErr == X86_TRAP_PF_RW
715	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
716	&& pRegFrame->ecx < 0x10000)
717	{
718	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
719	* to detect loading of new code pages.
720	*/
721
722	/*
723	* Decode the instruction.
724	*/
725	RTGCPTR PC;
726	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
727	if (rc == VINF_SUCCESS)
728	{
729	DISCPUSTATE Cpu;
730	uint32_t cbOp;
731	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
732
733	/* For now we'll restrict this to rep movsw/d instructions */
734	if ( rc == VINF_SUCCESS
735	&& Cpu.pCurInstr->opcode == OP_MOVSWD
736	&& (Cpu.prefix & PREFIX_REP))
737	{
738	CSAMMarkPossibleCodePage(pVM, pvFault);
739	}
740	}
741	}
742	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
743
744	/*
745	* Mark this page as safe.
746	*/
747	/** @todo not correct for pages that contain both code and data!! */
748	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
749	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
750	}
751	}
752	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
753	pgmLock(pVM);
754	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
755	pgmUnlock(pVM);
756	if (RT_SUCCESS(rc))
757	{
758	/* The page was successfully synced, return to the guest. */
759	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
760	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
761	return VINF_SUCCESS;
762	}
763	}
764	else /* uErr & X86_TRAP_PF_P: */
765	{
766	/*
767	* Write protected pages are make writable when the guest makes the first
768	* write to it. This happens for pages that are shared, write monitored
769	* and not yet allocated.
770	*
771	* Also, a side effect of not flushing global PDEs are out of sync pages due
772	* to physical monitored regions, that are no longer valid.
773	* Assume for now it only applies to the read/write flag.
774	*/
775	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
776	{
777	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
778	{
779	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
780	GCPhys, pPage, pvFault, uErr));
781	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
782	if (rc != VINF_SUCCESS)
783	{
784	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
785	return rc;
786	}
787	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
788	return VINF_EM_NO_MEMORY;
789	}
790	/// @todo count the above case; else
791	if (uErr & X86_TRAP_PF_US)
792	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
793	else /* supervisor */
794	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
795
796	/*
797	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
798	* page is not present, which is not true in this case.
799	*/
800	pgmLock(pVM);
801	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
802	pgmUnlock(pVM);
803	if (RT_SUCCESS(rc))
804	{
805	/*
806	* Page was successfully synced, return to guest.
807	*/
808	# ifdef VBOX_STRICT
809	RTGCPHYS GCPhys;
810	uint64_t fPageGst;
811	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
812	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
813	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
814
815	uint64_t fPageShw;
816	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
817	AssertMsg(RT_SUCCESS(rc) && fPageShw & X86_PTE_RW, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
818	# endif /* VBOX_STRICT */
819	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
820	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
821	return VINF_SUCCESS;
822	}
823
824	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
825	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
826	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
827	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
828	{
829	uint64_t fPageGst;
830	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
831	if ( RT_SUCCESS(rc)
832	&& !(fPageGst & X86_PTE_RW))
833	{
834	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
835	if (RT_SUCCESS(rc))
836	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
837	else
838	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
839	return rc;
840	}
841	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
842	}
843	}
844
845	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
846	# ifdef VBOX_STRICT
847	/*
848	* Check for VMM page flags vs. Guest page flags consistency.
849	* Currently only for debug purposes.
850	*/
851	if (RT_SUCCESS(rc))
852	{
853	/* Get guest page flags. */
854	uint64_t fPageGst;
855	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
856	if (RT_SUCCESS(rc))
857	{
858	uint64_t fPageShw;
859	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
860
861	/*
862	* Compare page flags.
863	* Note: we have AVL, A, D bits desynched.
864	*/
865	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
866	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
867	}
868	else
869	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
870	}
871	else
872	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
873	# endif /* VBOX_STRICT */
874	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
875	}
876	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
877	# endif /* PGM_OUT_OF_SYNC_IN_GC */
878	}
879	else /* GCPhys == NIL_RTGCPHYS */
880	{
881	/*
882	* Page not present in Guest OS or invalid page table address.
883	* This is potential virtual page access handler food.
884	*
885	* For the present we'll say that our access handlers don't
886	* work for this case - we've already discarded the page table
887	* not present case which is identical to this.
888	*
889	* When we perchance find we need this, we will probably have AVL
890	* trees (offset based) to operate on and we can measure their speed
891	* agains mapping a page table and probably rearrange this handling
892	* a bit. (Like, searching virtual ranges before checking the
893	* physical address.)
894	*/
895	}
896	}
897	/* else: !present (guest) */
898
899
900	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
901	/*
902	* Conclusion, this is a guest trap.
903	*/
904	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
905	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
906	return VINF_EM_RAW_GUEST_TRAP;
907	# else
908	/* present, but not a monitored page; perhaps the guest is probing physical memory */
909	return VINF_EM_RAW_EMULATE_INSTR;
910	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
911
912
913	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
914
915	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
916	return VERR_INTERNAL_ERROR;
917	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
918	}
919	#endif /* !IN_RING3 */
920
921
922	/**
923	* Emulation of the invlpg instruction.
924	*
925	*
926	* @returns VBox status code.
927	*
928	* @param pVCpu The VMCPU handle.
929	* @param GCPtrPage Page to invalidate.
930	*
931	* @remark ASSUMES that the guest is updating before invalidating. This order
932	* isn't required by the CPU, so this is speculative and could cause
933	* trouble.
934	* @remark No TLB shootdown is done on any other VCPU as we assume that
935	* invlpg emulation is the only reason for calling this function.
936	* (The guest has to shoot down TLB entries on other CPUs itself)
937	* Currently true, but keep in mind!
938	*
939	* @todo Flush page or page directory only if necessary!
940	* @todo Add a #define for simply invalidating the page.
941	*/
942	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
943	{
944	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
945	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
946	&& PGM_SHW_TYPE != PGM_TYPE_EPT
947	int rc;
948	PVM pVM = pVCpu->CTX_SUFF(pVM);
949	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
950
951	Assert(PGMIsLockOwner(pVM));
952
953	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
954	/*
955	* Get the shadow PD entry and skip out if this PD isn't present.
956	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
957	*/
958	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
959	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
960	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
961
962	/* Fetch the pgm pool shadow descriptor. */
963	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
964	Assert(pShwPde);
965
966	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
967	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
968	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
969
970	/* If the shadow PDPE isn't present, then skip the invalidate. */
971	if (!pPdptDst->a[iPdpt].n.u1Present)
972	{
973	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
974	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
975	return VINF_SUCCESS;
976	}
977
978	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
979	PPGMPOOLPAGE pShwPde = NULL;
980	PX86PDPAE pPDDst;
981
982	/* Fetch the pgm pool shadow descriptor. */
983	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
984	AssertRCSuccessReturn(rc, rc);
985	Assert(pShwPde);
986
987	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
988	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
989
990	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
991	/* PML4 */
992	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
993	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
994	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
995	PX86PDPAE pPDDst;
996	PX86PDPT pPdptDst;
997	PX86PML4E pPml4eDst;
998	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
999	if (rc != VINF_SUCCESS)
1000	{
1001	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1002	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1003	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1004	PGM_INVL_VCPU_TLBS(pVCpu);
1005	return VINF_SUCCESS;
1006	}
1007	Assert(pPDDst);
1008
1009	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1010	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1011
1012	if (!pPdpeDst->n.u1Present)
1013	{
1014	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1015	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1016	PGM_INVL_VCPU_TLBS(pVCpu);
1017	return VINF_SUCCESS;
1018	}
1019
1020	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1021
1022	const SHWPDE PdeDst = *pPdeDst;
1023	if (!PdeDst.n.u1Present)
1024	{
1025	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1026	return VINF_SUCCESS;
1027	}
1028
1029	# if defined(IN_RC)
1030	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1031	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1032	# endif
1033
1034	/*
1035	* Get the guest PD entry and calc big page.
1036	*/
1037	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1038	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1039	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1040	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1041	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1042	unsigned iPDSrc = 0;
1043	# if PGM_GST_TYPE == PGM_TYPE_PAE
1044	X86PDPE PdpeSrc;
1045	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1046	# else /* AMD64 */
1047	PX86PML4E pPml4eSrc;
1048	X86PDPE PdpeSrc;
1049	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1050	# endif
1051	GSTPDE PdeSrc;
1052
1053	if (pPDSrc)
1054	PdeSrc = pPDSrc->a[iPDSrc];
1055	else
1056	PdeSrc.u = 0;
1057	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1058
1059	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1060	const bool fIsBigPage = PdeSrc.b.u1Size;
1061	# else
1062	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1063	# endif
1064
1065	# ifdef IN_RING3
1066	/*
1067	* If a CR3 Sync is pending we may ignore the invalidate page operation
1068	* depending on the kind of sync and if it's a global page or not.
1069	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1070	*/
1071	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1072	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1073	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1074	&& fIsBigPage
1075	&& PdeSrc.b.u1Global
1076	)
1077	)
1078	# else
1079	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1080	# endif
1081	{
1082	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1083	return VINF_SUCCESS;
1084	}
1085	# endif /* IN_RING3 */
1086
1087	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1088	/* Fetch the pgm pool shadow descriptor. */
1089	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1090	Assert(pShwPdpt);
1091
1092	/* Fetch the pgm pool shadow descriptor. */
1093	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1094	Assert(pShwPde);
1095
1096	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1097	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1098
1099	if ( !pPml4eSrc->n.u1Present
1100	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1101	{
1102	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1103	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1104	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1105	ASMAtomicWriteSize(pPml4eDst, 0);
1106	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1107	PGM_INVL_VCPU_TLBS(pVCpu);
1108	return VINF_SUCCESS;
1109	}
1110	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1111	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1112	{
1113	/*
1114	* Mark not present so we can resync the PML4E when it's used.
1115	*/
1116	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1117	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1118	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1119	ASMAtomicWriteSize(pPml4eDst, 0);
1120	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1121	PGM_INVL_VCPU_TLBS(pVCpu);
1122	}
1123	else if (!pPml4eSrc->n.u1Accessed)
1124	{
1125	/*
1126	* Mark not present so we can set the accessed bit.
1127	*/
1128	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1129	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1130	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1131	ASMAtomicWriteSize(pPml4eDst, 0);
1132	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1133	PGM_INVL_VCPU_TLBS(pVCpu);
1134	}
1135
1136	/* Check if the PDPT entry has changed. */
1137	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1138	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1139	if ( !PdpeSrc.n.u1Present
1140	\|\| pShwPde->GCPhys != GCPhysPd)
1141	{
1142	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1143	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1144	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1145	ASMAtomicWriteSize(pPdpeDst, 0);
1146	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1147	PGM_INVL_VCPU_TLBS(pVCpu);
1148	return VINF_SUCCESS;
1149	}
1150	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1151	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1152	{
1153	/*
1154	* Mark not present so we can resync the PDPTE when it's used.
1155	*/
1156	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1157	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1158	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1159	ASMAtomicWriteSize(pPdpeDst, 0);
1160	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1161	PGM_INVL_VCPU_TLBS(pVCpu);
1162	}
1163	else if (!PdpeSrc.lm.u1Accessed)
1164	{
1165	/*
1166	* Mark not present so we can set the accessed bit.
1167	*/
1168	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1169	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1170	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1171	ASMAtomicWriteSize(pPdpeDst, 0);
1172	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1173	PGM_INVL_VCPU_TLBS(pVCpu);
1174	}
1175	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1176
1177	/*
1178	* Deal with the Guest PDE.
1179	*/
1180	rc = VINF_SUCCESS;
1181	if (PdeSrc.n.u1Present)
1182	{
1183	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1184	{
1185	/*
1186	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1187	*/
1188	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1189	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1190	pgmLock(pVM);
1191	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1192	pgmUnlock(pVM);
1193	}
1194	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
1195	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1196	{
1197	/*
1198	* Mark not present so we can resync the PDE when it's used.
1199	*/
1200	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1201	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1202	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1203	ASMAtomicWriteSize(pPdeDst, 0);
1204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1205	PGM_INVL_VCPU_TLBS(pVCpu);
1206	}
1207	else if (!PdeSrc.n.u1Accessed)
1208	{
1209	/*
1210	* Mark not present so we can set the accessed bit.
1211	*/
1212	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1213	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1214	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1215	ASMAtomicWriteSize(pPdeDst, 0);
1216	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1217	PGM_INVL_VCPU_TLBS(pVCpu);
1218	}
1219	else if (!fIsBigPage)
1220	{
1221	/*
1222	* 4KB - page.
1223	*/
1224	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1225	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1226	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1227	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1228	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1229	# endif
1230	if (pShwPage->GCPhys == GCPhys)
1231	{
1232	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1233	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1234	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1235	if (pPT->a[iPTEDst].n.u1Present)
1236	{
1237	# ifdef PGMPOOL_WITH_USER_TRACKING
1238	/* This is very unlikely with caching/monitoring enabled. */
1239	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1240	# endif
1241	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1242	}
1243	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1244	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1245	if (RT_SUCCESS(rc))
1246	rc = VINF_SUCCESS;
1247	# endif
1248	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1249	PGM_INVL_PG(pVCpu, GCPtrPage);
1250	}
1251	else
1252	{
1253	/*
1254	* The page table address changed.
1255	*/
1256	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1257	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1258	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1259	ASMAtomicWriteSize(pPdeDst, 0);
1260	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1261	PGM_INVL_VCPU_TLBS(pVCpu);
1262	}
1263	}
1264	else
1265	{
1266	/*
1267	* 2/4MB - page.
1268	*/
1269	/* Before freeing the page, check if anything really changed. */
1270	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1271	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1272	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1273	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1274	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1275	# endif
1276	if ( pShwPage->GCPhys == GCPhys
1277	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1278	{
1279	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1280	/** @todo PAT */
1281	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1282	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1283	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1284	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1285	{
1286	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1287	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1288	# if defined(IN_RC)
1289	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1290	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1291	# endif
1292	return VINF_SUCCESS;
1293	}
1294	}
1295
1296	/*
1297	* Ok, the page table is present and it's been changed in the guest.
1298	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1299	* We could do this for some flushes in GC too, but we need an algorithm for
1300	* deciding which 4MB pages containing code likely to be executed very soon.
1301	*/
1302	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1303	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1304	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1305	ASMAtomicWriteSize(pPdeDst, 0);
1306	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1307	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1308	}
1309	}
1310	else
1311	{
1312	/*
1313	* Page directory is not present, mark shadow PDE not present.
1314	*/
1315	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1316	{
1317	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1318	ASMAtomicWriteSize(pPdeDst, 0);
1319	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1320	PGM_INVL_PG(pVCpu, GCPtrPage);
1321	}
1322	else
1323	{
1324	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1325	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1326	}
1327	}
1328	# if defined(IN_RC)
1329	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1330	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1331	# endif
1332	return rc;
1333
1334	#else /* guest real and protected mode */
1335	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1336	return VINF_SUCCESS;
1337	#endif
1338	}
1339
1340
1341	#ifdef PGMPOOL_WITH_USER_TRACKING
1342	/**
1343	* Update the tracking of shadowed pages.
1344	*
1345	* @param pVCpu The VMCPU handle.
1346	* @param pShwPage The shadow page.
1347	* @param HCPhys The physical page we is being dereferenced.
1348	*/
1349	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1350	{
1351	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1352	PVM pVM = pVCpu->CTX_SUFF(pVM);
1353
1354	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1355	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1356
1357	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1358	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1359	* 2. write protect all shadowed pages. I.e. implement caching.
1360	*/
1361	/*
1362	* Find the guest address.
1363	*/
1364	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1365	pRam;
1366	pRam = pRam->CTX_SUFF(pNext))
1367	{
1368	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1369	while (iPage-- > 0)
1370	{
1371	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1372	{
1373	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1374	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1375	pShwPage->cPresent--;
1376	pPool->cPresent--;
1377	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1378	return;
1379	}
1380	}
1381	}
1382
1383	for (;;)
1384	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1385	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1386	pShwPage->cPresent--;
1387	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1388	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1389	}
1390
1391
1392	/**
1393	* Update the tracking of shadowed pages.
1394	*
1395	* @param pVCpu The VMCPU handle.
1396	* @param pShwPage The shadow page.
1397	* @param u16 The top 16-bit of the pPage->HCPhys.
1398	* @param pPage Pointer to the guest page. this will be modified.
1399	* @param iPTDst The index into the shadow table.
1400	*/
1401	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1402	{
1403	PVM pVM = pVCpu->CTX_SUFF(pVM);
1404	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1405	/*
1406	* Just deal with the simple first time here.
1407	*/
1408	if (!u16)
1409	{
1410	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1411	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1412	}
1413	else
1414	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1415
1416	/* write back */
1417	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1418	PGM_PAGE_SET_TRACKING(pPage, u16);
1419
1420	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1421
1422	/* update statistics. */
1423	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1424	pShwPage->cPresent++;
1425	if (pShwPage->iFirstPresent > iPTDst)
1426	pShwPage->iFirstPresent = iPTDst;
1427	}
1428	#endif /* PGMPOOL_WITH_USER_TRACKING */
1429
1430
1431	/**
1432	* Creates a 4K shadow page for a guest page.
1433	*
1434	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1435	* physical address. The PdeSrc argument only the flags are used. No page structured
1436	* will be mapped in this function.
1437	*
1438	* @param pVCpu The VMCPU handle.
1439	* @param pPteDst Destination page table entry.
1440	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1441	* Can safely assume that only the flags are being used.
1442	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1443	* @param pShwPage Pointer to the shadow page.
1444	* @param iPTDst The index into the shadow table.
1445	*
1446	* @remark Not used for 2/4MB pages!
1447	*/
1448	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1449	{
1450	if (PteSrc.n.u1Present)
1451	{
1452	PVM pVM = pVCpu->CTX_SUFF(pVM);
1453
1454	/*
1455	* Find the ram range.
1456	*/
1457	PPGMPAGE pPage;
1458	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1459	if (RT_SUCCESS(rc))
1460	{
1461	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1462	/* Try make the page writable if necessary. */
1463	if ( PteSrc.n.u1Write
1464	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1465	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1466	{
1467	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1468	AssertRC(rc);
1469	}
1470	#endif
1471
1472	/** @todo investiage PWT, PCD and PAT. */
1473	/*
1474	* Make page table entry.
1475	*/
1476	SHWPTE PteDst;
1477	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1478	{
1479	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1480	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1481	{
1482	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1483	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1484	PteDst.n.u1Present = 1;
1485	PteDst.n.u1Execute = 1;
1486	PteDst.n.u1IgnorePAT = 1;
1487	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1488	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1489	#else
1490	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1491	\| PGM_PAGE_GET_HCPHYS(pPage);
1492	#endif
1493	}
1494	else
1495	{
1496	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1497	PteDst.u = 0;
1498	}
1499	/** @todo count these two kinds. */
1500	}
1501	else
1502	{
1503	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1504	/*
1505	* If the page or page directory entry is not marked accessed,
1506	* we mark the page not present.
1507	*/
1508	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1509	{
1510	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1511	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1512	PteDst.u = 0;
1513	}
1514	else
1515	/*
1516	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1517	* when the page is modified.
1518	*/
1519	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1520	{
1521	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1522	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1523	\| PGM_PAGE_GET_HCPHYS(pPage)
1524	\| PGM_PTFLAGS_TRACK_DIRTY;
1525	}
1526	else
1527	#endif
1528	{
1529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1530	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1531	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1532	PteDst.n.u1Present = 1;
1533	PteDst.n.u1Write = 1;
1534	PteDst.n.u1Execute = 1;
1535	PteDst.n.u1IgnorePAT = 1;
1536	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1537	/* PteDst.n.u1Size = 0 */
1538	#else
1539	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1540	\| PGM_PAGE_GET_HCPHYS(pPage);
1541	#endif
1542	}
1543	}
1544
1545	/*
1546	* Make sure only allocated pages are mapped writable.
1547	*/
1548	if ( PteDst.n.u1Write
1549	&& PteDst.n.u1Present
1550	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1551	{
1552	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1553	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1554	}
1555
1556	#ifdef PGMPOOL_WITH_USER_TRACKING
1557	/*
1558	* Keep user track up to date.
1559	*/
1560	if (PteDst.n.u1Present)
1561	{
1562	if (!pPteDst->n.u1Present)
1563	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1564	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1565	{
1566	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1567	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1568	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1569	}
1570	}
1571	else if (pPteDst->n.u1Present)
1572	{
1573	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1574	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1575	}
1576	#endif /* PGMPOOL_WITH_USER_TRACKING */
1577
1578	/*
1579	* Update statistics and commit the entry.
1580	*/
1581	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1582	if (!PteSrc.n.u1Global)
1583	pShwPage->fSeenNonGlobal = true;
1584	#endif
1585	ASMAtomicWriteSize(pPteDst, PteDst.u);
1586	}
1587	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1588	/** @todo count these. */
1589	}
1590	else
1591	{
1592	/*
1593	* Page not-present.
1594	*/
1595	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1596	#ifdef PGMPOOL_WITH_USER_TRACKING
1597	/* Keep user track up to date. */
1598	if (pPteDst->n.u1Present)
1599	{
1600	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1601	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1602	}
1603	#endif /* PGMPOOL_WITH_USER_TRACKING */
1604	ASMAtomicWriteSize(pPteDst, 0);
1605	/** @todo count these. */
1606	}
1607	}
1608
1609
1610	/**
1611	* Syncs a guest OS page.
1612	*
1613	* There are no conflicts at this point, neither is there any need for
1614	* page table allocations.
1615	*
1616	* @returns VBox status code.
1617	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1618	* @param pVCpu The VMCPU handle.
1619	* @param PdeSrc Page directory entry of the guest.
1620	* @param GCPtrPage Guest context page address.
1621	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1622	* @param uErr Fault error (X86_TRAP_PF_*).
1623	*/
1624	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1625	{
1626	PVM pVM = pVCpu->CTX_SUFF(pVM);
1627	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1628	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1629
1630	Assert(PGMIsLockOwner(pVM));
1631
1632	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1633	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1634	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1635	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1636	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1637
1638	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1639	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1640	# endif
1641
1642	/*
1643	* Assert preconditions.
1644	*/
1645	Assert(PdeSrc.n.u1Present);
1646	Assert(cPages);
1647	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1648
1649	/*
1650	* Get the shadow PDE, find the shadow page table in the pool.
1651	*/
1652	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1653	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1654	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1655
1656	/* Fetch the pgm pool shadow descriptor. */
1657	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1658	Assert(pShwPde);
1659
1660	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1661	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1662	PPGMPOOLPAGE pShwPde = NULL;
1663	PX86PDPAE pPDDst;
1664
1665	/* Fetch the pgm pool shadow descriptor. */
1666	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1667	AssertRCSuccessReturn(rc, rc);
1668	Assert(pShwPde);
1669
1670	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1671	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1672
1673	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1674	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1675	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1676	PX86PDPAE pPDDst;
1677	PX86PDPT pPdptDst;
1678
1679	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1680	AssertRCSuccessReturn(rc, rc);
1681	Assert(pPDDst && pPdptDst);
1682	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1683	# endif
1684	SHWPDE PdeDst = *pPdeDst;
1685	AssertMsg(PdeDst.n.u1Present, ("%p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1686	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1687
1688	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1689	/* Fetch the pgm pool shadow descriptor. */
1690	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1691	Assert(pShwPde);
1692	# endif
1693
1694	# if defined(IN_RC)
1695	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1696	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1697	# endif
1698
1699	/*
1700	* Check that the page is present and that the shadow PDE isn't out of sync.
1701	*/
1702	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1703	const bool fBigPage = PdeSrc.b.u1Size;
1704	# else
1705	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1706	# endif
1707	RTGCPHYS GCPhys;
1708	if (!fBigPage)
1709	{
1710	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1711	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1712	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1713	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1714	# endif
1715	}
1716	else
1717	{
1718	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1719	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1720	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1721	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1722	# endif
1723	}
1724	if ( pShwPage->GCPhys == GCPhys
1725	&& PdeSrc.n.u1Present
1726	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1727	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1728	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1729	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1730	# endif
1731	)
1732	{
1733	/*
1734	* Check that the PDE is marked accessed already.
1735	* Since we set the accessed bit before getting here on a #PF, this
1736	* check is only meant for dealing with non-#PF'ing paths.
1737	*/
1738	if (PdeSrc.n.u1Accessed)
1739	{
1740	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1741	if (!fBigPage)
1742	{
1743	/*
1744	* 4KB Page - Map the guest page table.
1745	*/
1746	PGSTPT pPTSrc;
1747	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1748	if (RT_SUCCESS(rc))
1749	{
1750	# ifdef PGM_SYNC_N_PAGES
1751	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1752	if ( cPages > 1
1753	&& !(uErr & X86_TRAP_PF_P)
1754	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1755	{
1756	/*
1757	* This code path is currently only taken when the caller is PGMTrap0eHandler
1758	* for non-present pages!
1759	*
1760	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1761	* deal with locality.
1762	*/
1763	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1764	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1765	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1766	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1767	# else
1768	const unsigned offPTSrc = 0;
1769	# endif
1770	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1771	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1772	iPTDst = 0;
1773	else
1774	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1775	for (; iPTDst < iPTDstEnd; iPTDst++)
1776	{
1777	if (!pPTDst->a[iPTDst].n.u1Present)
1778	{
1779	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1780	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1781	NOREF(GCPtrCurPage);
1782	#ifndef IN_RING0
1783	/*
1784	* Assuming kernel code will be marked as supervisor - and not as user level
1785	* and executed using a conforming code selector - And marked as readonly.
1786	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1787	*/
1788	PPGMPAGE pPage;
1789	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1790	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1791	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1792	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1793	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1794	)
1795	#endif /* else: CSAM not active */
1796	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1797	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1798	GCPtrCurPage, PteSrc.n.u1Present,
1799	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1800	PteSrc.n.u1User & PdeSrc.n.u1User,
1801	(uint64_t)PteSrc.u,
1802	(uint64_t)pPTDst->a[iPTDst].u,
1803	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1804	}
1805	}
1806	}
1807	else
1808	# endif /* PGM_SYNC_N_PAGES */
1809	{
1810	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1811	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1812	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1813	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1814	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1815	GCPtrPage, PteSrc.n.u1Present,
1816	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1817	PteSrc.n.u1User & PdeSrc.n.u1User,
1818	(uint64_t)PteSrc.u,
1819	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1820	}
1821	}
1822	else /* MMIO or invalid page: emulated in #PF handler. */
1823	{
1824	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1825	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1826	}
1827	}
1828	else
1829	{
1830	/*
1831	* 4/2MB page - lazy syncing shadow 4K pages.
1832	* (There are many causes of getting here, it's no longer only CSAM.)
1833	*/
1834	/* Calculate the GC physical address of this 4KB shadow page. */
1835	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1836	/* Find ram range. */
1837	PPGMPAGE pPage;
1838	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1839	if (RT_SUCCESS(rc))
1840	{
1841	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1842	/* Try make the page writable if necessary. */
1843	if ( PdeSrc.n.u1Write
1844	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1845	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1846	{
1847	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1848	AssertRC(rc);
1849	}
1850	# endif
1851
1852	/*
1853	* Make shadow PTE entry.
1854	*/
1855	SHWPTE PteDst;
1856	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1857	\| PGM_PAGE_GET_HCPHYS(pPage);
1858	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1859	{
1860	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1861	PteDst.n.u1Write = 0;
1862	else
1863	PteDst.u = 0;
1864	}
1865	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1866	# ifdef PGMPOOL_WITH_USER_TRACKING
1867	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1868	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1869	# endif
1870	/* Make sure only allocated pages are mapped writable. */
1871	if ( PteDst.n.u1Write
1872	&& PteDst.n.u1Present
1873	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1874	{
1875	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1876	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1877	}
1878
1879	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1880
1881	/*
1882	* If the page is not flagged as dirty and is writable, then make it read-only
1883	* at PD level, so we can set the dirty bit when the page is modified.
1884	*
1885	* ASSUMES that page access handlers are implemented on page table entry level.
1886	* Thus we will first catch the dirty access and set PDE.D and restart. If
1887	* there is an access handler, we'll trap again and let it work on the problem.
1888	*/
1889	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1890	* As for invlpg, it simply frees the whole shadow PT.
1891	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1892	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1893	{
1894	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1895	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1896	PdeDst.n.u1Write = 0;
1897	}
1898	else
1899	{
1900	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1901	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1902	}
1903	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1904	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1905	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1906	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1907	}
1908	else
1909	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1910	}
1911	# if defined(IN_RC)
1912	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1913	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1914	# endif
1915	return VINF_SUCCESS;
1916	}
1917	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1918	}
1919	else
1920	{
1921	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1922	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1923	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1924	}
1925
1926	/*
1927	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1928	* Yea, I'm lazy.
1929	*/
1930	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1931	ASMAtomicWriteSize(pPdeDst, 0);
1932
1933	# if defined(IN_RC)
1934	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1935	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1936	# endif
1937	PGM_INVL_VCPU_TLBS(pVCpu);
1938	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1939
1940	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1941	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1942	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1943	&& !defined(IN_RC)
1944
1945	# ifdef PGM_SYNC_N_PAGES
1946	/*
1947	* Get the shadow PDE, find the shadow page table in the pool.
1948	*/
1949	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1950	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1951
1952	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1953	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1954
1955	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1956	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1957	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1958	PX86PDPAE pPDDst;
1959	X86PDEPAE PdeDst;
1960	PX86PDPT pPdptDst;
1961
1962	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1963	AssertRCSuccessReturn(rc, rc);
1964	Assert(pPDDst && pPdptDst);
1965	PdeDst = pPDDst->a[iPDDst];
1966	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1967	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1968	PEPTPD pPDDst;
1969	EPTPDE PdeDst;
1970
1971	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1972	if (rc != VINF_SUCCESS)
1973	{
1974	AssertRC(rc);
1975	return rc;
1976	}
1977	Assert(pPDDst);
1978	PdeDst = pPDDst->a[iPDDst];
1979	# endif
1980	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1981	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1982	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1983
1984	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1985	if ( cPages > 1
1986	&& !(uErr & X86_TRAP_PF_P)
1987	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1988	{
1989	/*
1990	* This code path is currently only taken when the caller is PGMTrap0eHandler
1991	* for non-present pages!
1992	*
1993	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1994	* deal with locality.
1995	*/
1996	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1997	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1998	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1999	iPTDst = 0;
2000	else
2001	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2002	for (; iPTDst < iPTDstEnd; iPTDst++)
2003	{
2004	if (!pPTDst->a[iPTDst].n.u1Present)
2005	{
2006	GSTPTE PteSrc;
2007
2008	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2009
2010	/* Fake the page table entry */
2011	PteSrc.u = GCPtrCurPage;
2012	PteSrc.n.u1Present = 1;
2013	PteSrc.n.u1Dirty = 1;
2014	PteSrc.n.u1Accessed = 1;
2015	PteSrc.n.u1Write = 1;
2016	PteSrc.n.u1User = 1;
2017
2018	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2019
2020	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2021	GCPtrCurPage, PteSrc.n.u1Present,
2022	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2023	PteSrc.n.u1User & PdeSrc.n.u1User,
2024	(uint64_t)PteSrc.u,
2025	(uint64_t)pPTDst->a[iPTDst].u,
2026	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2027
2028	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2029	break;
2030	}
2031	else
2032	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2033	}
2034	}
2035	else
2036	# endif /* PGM_SYNC_N_PAGES */
2037	{
2038	GSTPTE PteSrc;
2039	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2040	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2041
2042	/* Fake the page table entry */
2043	PteSrc.u = GCPtrCurPage;
2044	PteSrc.n.u1Present = 1;
2045	PteSrc.n.u1Dirty = 1;
2046	PteSrc.n.u1Accessed = 1;
2047	PteSrc.n.u1Write = 1;
2048	PteSrc.n.u1User = 1;
2049	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2050
2051	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2052	GCPtrPage, PteSrc.n.u1Present,
2053	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2054	PteSrc.n.u1User & PdeSrc.n.u1User,
2055	(uint64_t)PteSrc.u,
2056	(uint64_t)pPTDst->a[iPTDst].u,
2057	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2058	}
2059	return VINF_SUCCESS;
2060
2061	#else
2062	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2063	return VERR_INTERNAL_ERROR;
2064	#endif
2065	}
2066
2067
2068	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2069	/**
2070	* Investigate page fault and handle write protection page faults caused by
2071	* dirty bit tracking.
2072	*
2073	* @returns VBox status code.
2074	* @param pVCpu The VMCPU handle.
2075	* @param uErr Page fault error code.
2076	* @param pPdeDst Shadow page directory entry.
2077	* @param pPdeSrc Guest page directory entry.
2078	* @param GCPtrPage Guest context page address.
2079	*/
2080	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2081	{
2082	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2083	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2084	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2085	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2086	bool fBigPagesSupported = true;
2087	# else
2088	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2089	# endif
2090	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2091	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2092	# endif
2093	unsigned uPageFaultLevel;
2094	int rc;
2095	PVM pVM = pVCpu->CTX_SUFF(pVM);
2096	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2097
2098	Assert(PGMIsLockOwner(pVM));
2099
2100	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2101	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2102
2103	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2104	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2105
2106	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2107	PX86PML4E pPml4eSrc;
2108	PX86PDPE pPdpeSrc;
2109
2110	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2111	Assert(pPml4eSrc);
2112
2113	/*
2114	* Real page fault? (PML4E level)
2115	*/
2116	if ( (uErr & X86_TRAP_PF_RSVD)
2117	\|\| !pPml4eSrc->n.u1Present
2118	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2119	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2120	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2121	)
2122	{
2123	uPageFaultLevel = 0;
2124	goto l_UpperLevelPageFault;
2125	}
2126	Assert(pPdpeSrc);
2127
2128	# else /* PAE */
2129	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2130	# endif /* PAE */
2131
2132	/*
2133	* Real page fault? (PDPE level)
2134	*/
2135	if ( (uErr & X86_TRAP_PF_RSVD)
2136	\|\| !pPdpeSrc->n.u1Present
2137	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2138	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2139	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2140	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2141	# endif
2142	)
2143	{
2144	uPageFaultLevel = 1;
2145	goto l_UpperLevelPageFault;
2146	}
2147	# endif
2148
2149	/*
2150	* Real page fault? (PDE level)
2151	*/
2152	if ( (uErr & X86_TRAP_PF_RSVD)
2153	\|\| !pPdeSrc->n.u1Present
2154	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2155	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2156	# endif
2157	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2158	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2159	{
2160	uPageFaultLevel = 2;
2161	goto l_UpperLevelPageFault;
2162	}
2163
2164	/*
2165	* First check the easy case where the page directory has been marked read-only to track
2166	* the dirty bit of an emulated BIG page
2167	*/
2168	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2169	{
2170	/* Mark guest page directory as accessed */
2171	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2172	pPml4eSrc->n.u1Accessed = 1;
2173	pPdpeSrc->lm.u1Accessed = 1;
2174	# endif
2175	pPdeSrc->b.u1Accessed = 1;
2176
2177	/*
2178	* Only write protection page faults are relevant here.
2179	*/
2180	if (fWriteFault)
2181	{
2182	/* Mark guest page directory as dirty (BIG page only). */
2183	pPdeSrc->b.u1Dirty = 1;
2184
2185	if (pPdeDst->n.u1Present)
2186	{
2187	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2188	{
2189	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2190	Assert(pPdeSrc->b.u1Write);
2191
2192	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2193	* fault again and take this path to only invalidate the entry.
2194	*/
2195	pPdeDst->n.u1Write = 1;
2196	pPdeDst->n.u1Accessed = 1;
2197	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2198	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2199	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2200	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2201	}
2202	# ifdef IN_RING0
2203	else
2204	/* Check for stale TLB entry; only applies to the SMP guest case. */
2205	if ( pVM->cCPUs > 1
2206	&& pPdeDst->n.u1Write
2207	&& pPdeDst->n.u1Accessed)
2208	{
2209	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2210	if (pShwPage)
2211	{
2212	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2213	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2214	if ( pPteDst->n.u1Present
2215	&& pPteDst->n.u1Write)
2216	{
2217	/* Stale TLB entry. */
2218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2219	PGM_INVL_PG(pVCpu, GCPtrPage);
2220
2221	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2222	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2223	}
2224	}
2225	}
2226	# endif /* IN_RING0 */
2227	}
2228	}
2229	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2230	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2231	}
2232	/* else: 4KB page table */
2233
2234	/*
2235	* Map the guest page table.
2236	*/
2237	PGSTPT pPTSrc;
2238	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2239	if (RT_SUCCESS(rc))
2240	{
2241	/*
2242	* Real page fault?
2243	*/
2244	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2245	const GSTPTE PteSrc = *pPteSrc;
2246	if ( !PteSrc.n.u1Present
2247	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2248	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2249	# endif
2250	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2251	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2252	)
2253	{
2254	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2255	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2256	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2257
2258	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2259	* See the 2nd case above as well.
2260	*/
2261	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2262	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2263
2264	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2265	return VINF_EM_RAW_GUEST_TRAP;
2266	}
2267	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2268
2269	/*
2270	* Set the accessed bits in the page directory and the page table.
2271	*/
2272	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2273	pPml4eSrc->n.u1Accessed = 1;
2274	pPdpeSrc->lm.u1Accessed = 1;
2275	# endif
2276	pPdeSrc->n.u1Accessed = 1;
2277	pPteSrc->n.u1Accessed = 1;
2278
2279	/*
2280	* Only write protection page faults are relevant here.
2281	*/
2282	if (fWriteFault)
2283	{
2284	/* Write access, so mark guest entry as dirty. */
2285	# ifdef VBOX_WITH_STATISTICS
2286	if (!pPteSrc->n.u1Dirty)
2287	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2288	else
2289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2290	# endif
2291
2292	pPteSrc->n.u1Dirty = 1;
2293
2294	if (pPdeDst->n.u1Present)
2295	{
2296	#ifndef IN_RING0
2297	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2298	* Our individual shadow handlers will provide more information and force a fatal exit.
2299	*/
2300	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2301	{
2302	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2303	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2304	return VINF_SUCCESS;
2305	}
2306	#endif
2307	/*
2308	* Map shadow page table.
2309	*/
2310	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2311	if (pShwPage)
2312	{
2313	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2314	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2315	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2316	{
2317	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2318	{
2319	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2320	# ifdef VBOX_STRICT
2321	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2322	if (pPage)
2323	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2324	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2325	# endif
2326	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2327
2328	Assert(pPteSrc->n.u1Write);
2329
2330	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2331	* fault again and take this path to only invalidate the entry.
2332	*/
2333	pPteDst->n.u1Write = 1;
2334	pPteDst->n.u1Dirty = 1;
2335	pPteDst->n.u1Accessed = 1;
2336	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2337	PGM_INVL_PG(pVCpu, GCPtrPage);
2338
2339	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2340	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2341	}
2342	# ifdef IN_RING0
2343	else
2344	/* Check for stale TLB entry; only applies to the SMP guest case. */
2345	if ( pVM->cCPUs > 1
2346	&& pPteDst->n.u1Write == 1
2347	&& pPteDst->n.u1Accessed == 1)
2348	{
2349	/* Stale TLB entry. */
2350	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2351	PGM_INVL_PG(pVCpu, GCPtrPage);
2352
2353	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2354	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2355	}
2356	# endif
2357	}
2358	}
2359	else
2360	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2361	}
2362	}
2363	/** @todo Optimize accessed bit emulation? */
2364	# ifdef VBOX_STRICT
2365	/*
2366	* Sanity check.
2367	*/
2368	else if ( !pPteSrc->n.u1Dirty
2369	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2370	&& pPdeDst->n.u1Present)
2371	{
2372	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2373	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2374	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2375	if ( pPteDst->n.u1Present
2376	&& pPteDst->n.u1Write)
2377	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2378	}
2379	# endif /* VBOX_STRICT */
2380	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2381	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2382	}
2383	AssertRC(rc);
2384	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2385	return rc;
2386
2387
2388	l_UpperLevelPageFault:
2389	/*
2390	* Pagefault detected while checking the PML4E, PDPE or PDE.
2391	* Single exit handler to get rid of duplicate code paths.
2392	*/
2393	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2394	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2395	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2396
2397	if (
2398	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2399	pPml4eSrc->n.u1Present &&
2400	# endif
2401	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2402	pPdpeSrc->n.u1Present &&
2403	# endif
2404	pPdeSrc->n.u1Present)
2405	{
2406	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2407	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2408	{
2409	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2410	}
2411	else
2412	{
2413	/*
2414	* Map the guest page table.
2415	*/
2416	PGSTPT pPTSrc;
2417	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2418	if (RT_SUCCESS(rc))
2419	{
2420	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2421	const GSTPTE PteSrc = *pPteSrc;
2422	if (pPteSrc->n.u1Present)
2423	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2424	}
2425	AssertRC(rc);
2426	}
2427	}
2428	return VINF_EM_RAW_GUEST_TRAP;
2429	}
2430	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2431
2432
2433	/**
2434	* Sync a shadow page table.
2435	*
2436	* The shadow page table is not present. This includes the case where
2437	* there is a conflict with a mapping.
2438	*
2439	* @returns VBox status code.
2440	* @param pVCpu The VMCPU handle.
2441	* @param iPD Page directory index.
2442	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2443	* Assume this is a temporary mapping.
2444	* @param GCPtrPage GC Pointer of the page that caused the fault
2445	*/
2446	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2447	{
2448	PVM pVM = pVCpu->CTX_SUFF(pVM);
2449	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2450
2451	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2452	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2453	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2454
2455	Assert(PGMIsLocked(pVM));
2456
2457	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2458	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2459	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2460	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2461	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2462
2463	int rc = VINF_SUCCESS;
2464
2465	/*
2466	* Validate input a little bit.
2467	*/
2468	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2469	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2470	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2471	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2472
2473	/* Fetch the pgm pool shadow descriptor. */
2474	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2475	Assert(pShwPde);
2476
2477	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2478	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2479	PPGMPOOLPAGE pShwPde = NULL;
2480	PX86PDPAE pPDDst;
2481	PSHWPDE pPdeDst;
2482
2483	/* Fetch the pgm pool shadow descriptor. */
2484	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2485	AssertRCSuccessReturn(rc, rc);
2486	Assert(pShwPde);
2487
2488	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2489	pPdeDst = &pPDDst->a[iPDDst];
2490
2491	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2492	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2493	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2494	PX86PDPAE pPDDst;
2495	PX86PDPT pPdptDst;
2496	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2497	AssertRCSuccessReturn(rc, rc);
2498	Assert(pPDDst);
2499	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2500	# endif
2501	SHWPDE PdeDst = *pPdeDst;
2502
2503	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2504	/* Fetch the pgm pool shadow descriptor. */
2505	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2506	Assert(pShwPde);
2507	# endif
2508
2509	# ifndef PGM_WITHOUT_MAPPINGS
2510	/*
2511	* Check for conflicts.
2512	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2513	* HC: Simply resolve the conflict.
2514	*/
2515	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2516	{
2517	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2518	# ifndef IN_RING3
2519	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2520	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2521	return VERR_ADDRESS_CONFLICT;
2522	# else
2523	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2524	Assert(pMapping);
2525	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2526	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2527	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2528	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2529	# else
2530	AssertFailed(); /* can't happen for amd64 */
2531	# endif
2532	if (RT_FAILURE(rc))
2533	{
2534	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2535	return rc;
2536	}
2537	PdeDst = *pPdeDst;
2538	# endif
2539	}
2540	# else /* PGM_WITHOUT_MAPPINGS */
2541	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2542	# endif /* PGM_WITHOUT_MAPPINGS */
2543	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2544
2545	# if defined(IN_RC)
2546	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2547	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2548	# endif
2549
2550	/*
2551	* Sync page directory entry.
2552	*/
2553	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2554	if (PdeSrc.n.u1Present)
2555	{
2556	/*
2557	* Allocate & map the page table.
2558	*/
2559	PSHWPT pPTDst;
2560	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2561	const bool fPageTable = !PdeSrc.b.u1Size;
2562	# else
2563	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2564	# endif
2565	PPGMPOOLPAGE pShwPage;
2566	RTGCPHYS GCPhys;
2567	if (fPageTable)
2568	{
2569	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2570	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2571	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2572	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2573	# endif
2574	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2575	}
2576	else
2577	{
2578	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2579	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2580	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2581	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2582	# endif
2583	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2584	}
2585	if (rc == VINF_SUCCESS)
2586	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2587	else if (rc == VINF_PGM_CACHED_PAGE)
2588	{
2589	/*
2590	* The PT was cached, just hook it up.
2591	*/
2592	if (fPageTable)
2593	PdeDst.u = pShwPage->Core.Key
2594	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2595	else
2596	{
2597	PdeDst.u = pShwPage->Core.Key
2598	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2599	/* (see explanation and assumptions further down.) */
2600	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2601	{
2602	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2603	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2604	PdeDst.b.u1Write = 0;
2605	}
2606	}
2607	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2608	# if defined(IN_RC)
2609	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2610	# endif
2611	return VINF_SUCCESS;
2612	}
2613	else if (rc == VERR_PGM_POOL_FLUSHED)
2614	{
2615	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2616	# if defined(IN_RC)
2617	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2618	# endif
2619	return VINF_PGM_SYNC_CR3;
2620	}
2621	else
2622	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2623	PdeDst.u &= X86_PDE_AVL_MASK;
2624	PdeDst.u \|= pShwPage->Core.Key;
2625
2626	/*
2627	* Page directory has been accessed (this is a fault situation, remember).
2628	*/
2629	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2630	if (fPageTable)
2631	{
2632	/*
2633	* Page table - 4KB.
2634	*
2635	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2636	*/
2637	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2638	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2639	PGSTPT pPTSrc;
2640	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2641	if (RT_SUCCESS(rc))
2642	{
2643	/*
2644	* Start by syncing the page directory entry so CSAM's TLB trick works.
2645	*/
2646	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2647	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2648	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2649	# if defined(IN_RC)
2650	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2651	# endif
2652
2653	/*
2654	* Directory/page user or supervisor privilege: (same goes for read/write)
2655	*
2656	* Directory Page Combined
2657	* U/S U/S U/S
2658	* 0 0 0
2659	* 0 1 0
2660	* 1 0 0
2661	* 1 1 1
2662	*
2663	* Simple AND operation. Table listed for completeness.
2664	*
2665	*/
2666	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2667	# ifdef PGM_SYNC_N_PAGES
2668	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2669	unsigned iPTDst = iPTBase;
2670	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2671	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2672	iPTDst = 0;
2673	else
2674	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2675	# else /* !PGM_SYNC_N_PAGES */
2676	unsigned iPTDst = 0;
2677	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2678	# endif /* !PGM_SYNC_N_PAGES */
2679	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2680	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2681	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2682	# else
2683	const unsigned offPTSrc = 0;
2684	# endif
2685	for (; iPTDst < iPTDstEnd; iPTDst++)
2686	{
2687	const unsigned iPTSrc = iPTDst + offPTSrc;
2688	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2689
2690	if (PteSrc.n.u1Present) /* we've already cleared it above */
2691	{
2692	# ifndef IN_RING0
2693	/*
2694	* Assuming kernel code will be marked as supervisor - and not as user level
2695	* and executed using a conforming code selector - And marked as readonly.
2696	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2697	*/
2698	PPGMPAGE pPage;
2699	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2700	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2701	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2702	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2703	)
2704	# endif
2705	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2706	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2707	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2708	PteSrc.n.u1Present,
2709	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2710	PteSrc.n.u1User & PdeSrc.n.u1User,
2711	(uint64_t)PteSrc.u,
2712	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2713	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2714	}
2715	} /* for PTEs */
2716	}
2717	}
2718	else
2719	{
2720	/*
2721	* Big page - 2/4MB.
2722	*
2723	* We'll walk the ram range list in parallel and optimize lookups.
2724	* We will only sync on shadow page table at a time.
2725	*/
2726	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2727
2728	/**
2729	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2730	*/
2731
2732	/*
2733	* Start by syncing the page directory entry.
2734	*/
2735	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2736	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2737
2738	/*
2739	* If the page is not flagged as dirty and is writable, then make it read-only
2740	* at PD level, so we can set the dirty bit when the page is modified.
2741	*
2742	* ASSUMES that page access handlers are implemented on page table entry level.
2743	* Thus we will first catch the dirty access and set PDE.D and restart. If
2744	* there is an access handler, we'll trap again and let it work on the problem.
2745	*/
2746	/** @todo move the above stuff to a section in the PGM documentation. */
2747	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2748	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2749	{
2750	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2751	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2752	PdeDst.b.u1Write = 0;
2753	}
2754	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2755	# if defined(IN_RC)
2756	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2757	# endif
2758
2759	/*
2760	* Fill the shadow page table.
2761	*/
2762	/* Get address and flags from the source PDE. */
2763	SHWPTE PteDstBase;
2764	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2765
2766	/* Loop thru the entries in the shadow PT. */
2767	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2768	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2769	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2770	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2771	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2772	unsigned iPTDst = 0;
2773	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2774	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2775	{
2776	/* Advance ram range list. */
2777	while (pRam && GCPhys > pRam->GCPhysLast)
2778	pRam = pRam->CTX_SUFF(pNext);
2779	if (pRam && GCPhys >= pRam->GCPhys)
2780	{
2781	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2782	do
2783	{
2784	/* Make shadow PTE. */
2785	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2786	SHWPTE PteDst;
2787
2788	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2789	/* Try make the page writable if necessary. */
2790	if ( PteDstBase.n.u1Write
2791	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2792	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2793	{
2794	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2795	AssertRCReturn(rc, rc);
2796	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2797	break;
2798	}
2799	# endif
2800
2801	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2802	{
2803	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2804	{
2805	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2806	PteDst.n.u1Write = 0;
2807	}
2808	else
2809	PteDst.u = 0;
2810	}
2811	# ifndef IN_RING0
2812	/*
2813	* Assuming kernel code will be marked as supervisor and not as user level and executed
2814	* using a conforming code selector. Don't check for readonly, as that implies the whole
2815	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2816	*/
2817	else if ( !PdeSrc.n.u1User
2818	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2819	PteDst.u = 0;
2820	# endif
2821	else
2822	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2823
2824	/* Only map writable pages writable. */
2825	if ( PteDst.n.u1Write
2826	&& PteDst.n.u1Present
2827	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2828	{
2829	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2830	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2831	}
2832
2833	# ifdef PGMPOOL_WITH_USER_TRACKING
2834	if (PteDst.n.u1Present)
2835	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2836	# endif
2837	/* commit it */
2838	pPTDst->a[iPTDst] = PteDst;
2839	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2840	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2841	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2842
2843	/* advance */
2844	GCPhys += PAGE_SIZE;
2845	iHCPage++;
2846	iPTDst++;
2847	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2848	&& GCPhys <= pRam->GCPhysLast);
2849	}
2850	else if (pRam)
2851	{
2852	Log(("Invalid pages at %RGp\n", GCPhys));
2853	do
2854	{
2855	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2856	GCPhys += PAGE_SIZE;
2857	iPTDst++;
2858	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2859	&& GCPhys < pRam->GCPhys);
2860	}
2861	else
2862	{
2863	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2864	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2865	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2866	}
2867	} /* while more PTEs */
2868	} /* 4KB / 4MB */
2869	}
2870	else
2871	AssertRelease(!PdeDst.n.u1Present);
2872
2873	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2874	if (RT_FAILURE(rc))
2875	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2876	return rc;
2877
2878	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2879	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2880	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2881	&& !defined(IN_RC)
2882
2883	/*
2884	* Validate input a little bit.
2885	*/
2886	int rc = VINF_SUCCESS;
2887	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2888	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2889	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2890
2891	/* Fetch the pgm pool shadow descriptor. */
2892	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2893	Assert(pShwPde);
2894
2895	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2896	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2897	PPGMPOOLPAGE pShwPde;
2898	PX86PDPAE pPDDst;
2899	PSHWPDE pPdeDst;
2900
2901	/* Fetch the pgm pool shadow descriptor. */
2902	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2903	AssertRCSuccessReturn(rc, rc);
2904	Assert(pShwPde);
2905
2906	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2907	pPdeDst = &pPDDst->a[iPDDst];
2908
2909	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2910	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2911	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2912	PX86PDPAE pPDDst;
2913	PX86PDPT pPdptDst;
2914	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2915	AssertRCSuccessReturn(rc, rc);
2916	Assert(pPDDst);
2917	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2918
2919	/* Fetch the pgm pool shadow descriptor. */
2920	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2921	Assert(pShwPde);
2922
2923	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2924	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2925	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2926	PEPTPD pPDDst;
2927	PEPTPDPT pPdptDst;
2928
2929	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2930	if (rc != VINF_SUCCESS)
2931	{
2932	AssertRC(rc);
2933	return rc;
2934	}
2935	Assert(pPDDst);
2936	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2937
2938	/* Fetch the pgm pool shadow descriptor. */
2939	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2940	Assert(pShwPde);
2941	# endif
2942	SHWPDE PdeDst = *pPdeDst;
2943
2944	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2945	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2946
2947	GSTPDE PdeSrc;
2948	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2949	PdeSrc.n.u1Present = 1;
2950	PdeSrc.n.u1Write = 1;
2951	PdeSrc.n.u1Accessed = 1;
2952	PdeSrc.n.u1User = 1;
2953
2954	/*
2955	* Allocate & map the page table.
2956	*/
2957	PSHWPT pPTDst;
2958	PPGMPOOLPAGE pShwPage;
2959	RTGCPHYS GCPhys;
2960
2961	/* Virtual address = physical address */
2962	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2963	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2964
2965	if ( rc == VINF_SUCCESS
2966	\|\| rc == VINF_PGM_CACHED_PAGE)
2967	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2968	else
2969	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2970
2971	PdeDst.u &= X86_PDE_AVL_MASK;
2972	PdeDst.u \|= pShwPage->Core.Key;
2973	PdeDst.n.u1Present = 1;
2974	PdeDst.n.u1Write = 1;
2975	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2976	PdeDst.n.u1Execute = 1;
2977	# else
2978	PdeDst.n.u1User = 1;
2979	PdeDst.n.u1Accessed = 1;
2980	# endif
2981	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2982
2983	pgmLock(pVM);
2984	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2985	pgmUnlock(pVM);
2986	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2987	return rc;
2988
2989	#else
2990	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2991	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2992	return VERR_INTERNAL_ERROR;
2993	#endif
2994	}
2995
2996
2997
2998	/**
2999	* Prefetch a page/set of pages.
3000	*
3001	* Typically used to sync commonly used pages before entering raw mode
3002	* after a CR3 reload.
3003	*
3004	* @returns VBox status code.
3005	* @param pVCpu The VMCPU handle.
3006	* @param GCPtrPage Page to invalidate.
3007	*/
3008	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3009	{
3010	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3011	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3012	/*
3013	* Check that all Guest levels thru the PDE are present, getting the
3014	* PD and PDE in the processes.
3015	*/
3016	int rc = VINF_SUCCESS;
3017	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3018	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3019	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3020	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3021	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3022	unsigned iPDSrc;
3023	X86PDPE PdpeSrc;
3024	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3025	if (!pPDSrc)
3026	return VINF_SUCCESS; /* not present */
3027	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3028	unsigned iPDSrc;
3029	PX86PML4E pPml4eSrc;
3030	X86PDPE PdpeSrc;
3031	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3032	if (!pPDSrc)
3033	return VINF_SUCCESS; /* not present */
3034	# endif
3035	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3036	# else
3037	PGSTPD pPDSrc = NULL;
3038	const unsigned iPDSrc = 0;
3039	GSTPDE PdeSrc;
3040
3041	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3042	PdeSrc.n.u1Present = 1;
3043	PdeSrc.n.u1Write = 1;
3044	PdeSrc.n.u1Accessed = 1;
3045	PdeSrc.n.u1User = 1;
3046	# endif
3047
3048	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3049	{
3050	PVM pVM = pVCpu->CTX_SUFF(pVM);
3051	pgmLock(pVM);
3052
3053	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3054	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3055	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3056	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3057	PX86PDPAE pPDDst;
3058	X86PDEPAE PdeDst;
3059	# if PGM_GST_TYPE != PGM_TYPE_PAE
3060	X86PDPE PdpeSrc;
3061
3062	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3063	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3064	# endif
3065	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3066	if (rc != VINF_SUCCESS)
3067	{
3068	pgmUnlock(pVM);
3069	AssertRC(rc);
3070	return rc;
3071	}
3072	Assert(pPDDst);
3073	PdeDst = pPDDst->a[iPDDst];
3074
3075	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3076	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3077	PX86PDPAE pPDDst;
3078	X86PDEPAE PdeDst;
3079
3080	# if PGM_GST_TYPE == PGM_TYPE_PROT
3081	/* AMD-V nested paging */
3082	X86PML4E Pml4eSrc;
3083	X86PDPE PdpeSrc;
3084	PX86PML4E pPml4eSrc = &Pml4eSrc;
3085
3086	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3087	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3088	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3089	# endif
3090
3091	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3092	if (rc != VINF_SUCCESS)
3093	{
3094	pgmUnlock(pVM);
3095	AssertRC(rc);
3096	return rc;
3097	}
3098	Assert(pPDDst);
3099	PdeDst = pPDDst->a[iPDDst];
3100	# endif
3101	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3102	{
3103	if (!PdeDst.n.u1Present)
3104	{
3105	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3106	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3107	}
3108	else
3109	{
3110	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3111	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3112	* makes no sense to prefetch more than one page.
3113	*/
3114	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3115	if (RT_SUCCESS(rc))
3116	rc = VINF_SUCCESS;
3117	}
3118	}
3119	pgmUnlock(pVM);
3120	}
3121	return rc;
3122
3123	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3124	return VINF_SUCCESS; /* ignore */
3125	#endif
3126	}
3127
3128
3129
3130
3131	/**
3132	* Syncs a page during a PGMVerifyAccess() call.
3133	*
3134	* @returns VBox status code (informational included).
3135	* @param pVCpu The VMCPU handle.
3136	* @param GCPtrPage The address of the page to sync.
3137	* @param fPage The effective guest page flags.
3138	* @param uErr The trap error code.
3139	*/
3140	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3141	{
3142	PVM pVM = pVCpu->CTX_SUFF(pVM);
3143
3144	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3145
3146	Assert(!HWACCMIsNestedPagingActive(pVM));
3147	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3148	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3149
3150	# ifndef IN_RING0
3151	if (!(fPage & X86_PTE_US))
3152	{
3153	/*
3154	* Mark this page as safe.
3155	*/
3156	/** @todo not correct for pages that contain both code and data!! */
3157	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3158	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3159	}
3160	# endif
3161
3162	/*
3163	* Get guest PD and index.
3164	*/
3165	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3166	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3167	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3168	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3169	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3170	unsigned iPDSrc = 0;
3171	X86PDPE PdpeSrc;
3172	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3173
3174	if (pPDSrc)
3175	{
3176	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3177	return VINF_EM_RAW_GUEST_TRAP;
3178	}
3179	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3180	unsigned iPDSrc;
3181	PX86PML4E pPml4eSrc;
3182	X86PDPE PdpeSrc;
3183	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3184	if (!pPDSrc)
3185	{
3186	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3187	return VINF_EM_RAW_GUEST_TRAP;
3188	}
3189	# endif
3190	# else
3191	PGSTPD pPDSrc = NULL;
3192	const unsigned iPDSrc = 0;
3193	# endif
3194	int rc = VINF_SUCCESS;
3195
3196	pgmLock(pVM);
3197
3198	/*
3199	* First check if the shadow pd is present.
3200	*/
3201	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3202	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3203	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3204	PX86PDEPAE pPdeDst;
3205	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3206	PX86PDPAE pPDDst;
3207	# if PGM_GST_TYPE != PGM_TYPE_PAE
3208	X86PDPE PdpeSrc;
3209
3210	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3211	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3212	# endif
3213	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3214	if (rc != VINF_SUCCESS)
3215	{
3216	pgmUnlock(pVM);
3217	AssertRC(rc);
3218	return rc;
3219	}
3220	Assert(pPDDst);
3221	pPdeDst = &pPDDst->a[iPDDst];
3222
3223	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3224	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3225	PX86PDPAE pPDDst;
3226	PX86PDEPAE pPdeDst;
3227
3228	# if PGM_GST_TYPE == PGM_TYPE_PROT
3229	/* AMD-V nested paging */
3230	X86PML4E Pml4eSrc;
3231	X86PDPE PdpeSrc;
3232	PX86PML4E pPml4eSrc = &Pml4eSrc;
3233
3234	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3235	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3236	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3237	# endif
3238
3239	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3240	if (rc != VINF_SUCCESS)
3241	{
3242	pgmUnlock(pVM);
3243	AssertRC(rc);
3244	return rc;
3245	}
3246	Assert(pPDDst);
3247	pPdeDst = &pPDDst->a[iPDDst];
3248	# endif
3249
3250	# if defined(IN_RC)
3251	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3252	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3253	# endif
3254
3255	if (!pPdeDst->n.u1Present)
3256	{
3257	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3258	if (rc != VINF_SUCCESS)
3259	{
3260	# if defined(IN_RC)
3261	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3262	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3263	# endif
3264	pgmUnlock(pVM);
3265	AssertRC(rc);
3266	return rc;
3267	}
3268	}
3269
3270	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3271	/* Check for dirty bit fault */
3272	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3273	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3274	Log(("PGMVerifyAccess: success (dirty)\n"));
3275	else
3276	{
3277	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3278	# else
3279	{
3280	GSTPDE PdeSrc;
3281	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3282	PdeSrc.n.u1Present = 1;
3283	PdeSrc.n.u1Write = 1;
3284	PdeSrc.n.u1Accessed = 1;
3285	PdeSrc.n.u1User = 1;
3286
3287	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3288	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3289	if (uErr & X86_TRAP_PF_US)
3290	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3291	else /* supervisor */
3292	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3293
3294	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3295	if (RT_SUCCESS(rc))
3296	{
3297	/* Page was successfully synced */
3298	Log2(("PGMVerifyAccess: success (sync)\n"));
3299	rc = VINF_SUCCESS;
3300	}
3301	else
3302	{
3303	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3304	rc = VINF_EM_RAW_GUEST_TRAP;
3305	}
3306	}
3307	# if defined(IN_RC)
3308	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3309	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3310	# endif
3311	pgmUnlock(pVM);
3312	return rc;
3313
3314	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3315
3316	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3317	return VERR_INTERNAL_ERROR;
3318	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3319	}
3320
3321
3322	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3323	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
3324	/**
3325	* Figures out which kind of shadow page this guest PDE warrants.
3326	*
3327	* @returns Shadow page kind.
3328	* @param pPdeSrc The guest PDE in question.
3329	* @param cr4 The current guest cr4 value.
3330	*/
3331	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
3332	{
3333	# if PMG_GST_TYPE == PGM_TYPE_AMD64
3334	if (!pPdeSrc->n.u1Size)
3335	# else
3336	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
3337	# endif
3338	return BTH_PGMPOOLKIND_PT_FOR_PT;
3339	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
3340	//{
3341	// case 0:
3342	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
3343	// case X86_PDE4M_RW:
3344	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
3345	// case X86_PDE4M_US:
3346	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
3347	// case X86_PDE4M_RW \| X86_PDE4M_US:
3348	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
3349	# if 0
3350	// case X86_PDE4M_PAE_NX:
3351	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
3352	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
3353	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
3354	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3355	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
3356	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
3357	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
3358	# endif
3359	return BTH_PGMPOOLKIND_PT_FOR_BIG;
3360	//}
3361	}
3362	# endif
3363	#endif
3364
3365	#undef MY_STAM_COUNTER_INC
3366	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3367
3368
3369	/**
3370	* Syncs the paging hierarchy starting at CR3.
3371	*
3372	* @returns VBox status code, no specials.
3373	* @param pVCpu The VMCPU handle.
3374	* @param cr0 Guest context CR0 register
3375	* @param cr3 Guest context CR3 register
3376	* @param cr4 Guest context CR4 register
3377	* @param fGlobal Including global page directories or not
3378	*/
3379	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3380	{
3381	PVM pVM = pVCpu->CTX_SUFF(pVM);
3382
3383	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3384	fGlobal = true; /* Change this CR3 reload to be a global one. */
3385
3386	LogFlow(("SyncCR3 %d\n", fGlobal));
3387
3388	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3389	/*
3390	* Update page access handlers.
3391	* The virtual are always flushed, while the physical are only on demand.
3392	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3393	* have to look into that later because it will have a bad influence on the performance.
3394	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3395	* bird: Yes, but that won't work for aliases.
3396	*/
3397	/** @todo this MUST go away. See #1557. */
3398	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3399	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3400	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3401	#endif
3402
3403	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3404	/*
3405	* Nested / EPT - almost no work.
3406	*/
3407	/** @todo check if this is really necessary; the call does it as well... */
3408	HWACCMFlushTLB(pVCpu);
3409	return VINF_SUCCESS;
3410
3411	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3412	/*
3413	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3414	* out the shadow parts when the guest modifies its tables.
3415	*/
3416	return VINF_SUCCESS;
3417
3418	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3419
3420	# ifdef PGM_WITHOUT_MAPPINGS
3421	Assert(pVM->pgm.s.fMappingsFixed);
3422	return VINF_SUCCESS;
3423	# else
3424	/* Nothing to do when mappings are fixed. */
3425	if (pVM->pgm.s.fMappingsFixed)
3426	return VINF_SUCCESS;
3427
3428	int rc = PGMMapResolveConflicts(pVM);
3429	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3430	if (rc == VINF_PGM_SYNC_CR3)
3431	{
3432	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3433	return VINF_PGM_SYNC_CR3;
3434	}
3435	# endif
3436	return VINF_SUCCESS;
3437	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3438	}
3439
3440
3441
3442
3443	#ifdef VBOX_STRICT
3444	#ifdef IN_RC
3445	# undef AssertMsgFailed
3446	# define AssertMsgFailed Log
3447	#endif
3448	#ifdef IN_RING3
3449	# include <VBox/dbgf.h>
3450
3451	/**
3452	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3453	*
3454	* @returns VBox status code (VINF_SUCCESS).
3455	* @param cr3 The root of the hierarchy.
3456	* @param crr The cr4, only PAE and PSE is currently used.
3457	* @param fLongMode Set if long mode, false if not long mode.
3458	* @param cMaxDepth Number of levels to dump.
3459	* @param pHlp Pointer to the output functions.
3460	*/
3461	__BEGIN_DECLS
3462	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3463	__END_DECLS
3464
3465	#endif
3466
3467	/**
3468	* Checks that the shadow page table is in sync with the guest one.
3469	*
3470	* @returns The number of errors.
3471	* @param pVM The virtual machine.
3472	* @param pVCpu The VMCPU handle.
3473	* @param cr3 Guest context CR3 register
3474	* @param cr4 Guest context CR4 register
3475	* @param GCPtr Where to start. Defaults to 0.
3476	* @param cb How much to check. Defaults to everything.
3477	*/
3478	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3479	{
3480	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3481	return 0;
3482	#else
3483	unsigned cErrors = 0;
3484	PVM pVM = pVCpu->CTX_SUFF(pVM);
3485	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3486
3487	#if PGM_GST_TYPE == PGM_TYPE_PAE
3488	/** @todo currently broken; crashes below somewhere */
3489	AssertFailed();
3490	#endif
3491
3492	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3493	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3494	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3495
3496	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3497	bool fBigPagesSupported = true;
3498	# else
3499	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3500	# endif
3501	PPGMCPU pPGM = &pVCpu->pgm.s;
3502	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3503	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3504	# ifndef IN_RING0
3505	RTHCPHYS HCPhys; /* general usage. */
3506	# endif
3507	int rc;
3508
3509	/*
3510	* Check that the Guest CR3 and all its mappings are correct.
3511	*/
3512	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3513	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3514	false);
3515	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3516	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3517	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3518	# else
3519	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3520	# endif
3521	AssertRCReturn(rc, 1);
3522	HCPhys = NIL_RTHCPHYS;
3523	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3524	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3525	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3526	pgmGstGet32bitPDPtr(pPGM);
3527	RTGCPHYS GCPhys;
3528	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3529	AssertRCReturn(rc, 1);
3530	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3531	# endif
3532	# endif /* !IN_RING0 */
3533
3534	/*
3535	* Get and check the Shadow CR3.
3536	*/
3537	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3538	unsigned cPDEs = X86_PG_ENTRIES;
3539	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3540	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3541	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3542	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3543	# else
3544	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3545	# endif
3546	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3547	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3548	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3549	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3550	# endif
3551	if (cb != ~(RTGCPTR)0)
3552	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3553
3554	/** @todo call the other two PGMAssert() functions. /
3555
3556	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3557	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3558
3559	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3560	{
3561	PPGMPOOLPAGE pShwPdpt = NULL;
3562	PX86PML4E pPml4eSrc;
3563	PX86PML4E pPml4eDst;
3564	RTGCPHYS GCPhysPdptSrc;
3565
3566	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3567	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3568
3569	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3570	if (!pPml4eDst->n.u1Present)
3571	{
3572	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3573	continue;
3574	}
3575
3576	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3577	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3578
3579	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3580	{
3581	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3582	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3583	cErrors++;
3584	continue;
3585	}
3586
3587	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3588	{
3589	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3590	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3591	cErrors++;
3592	continue;
3593	}
3594
3595	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3596	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3597	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3598	{
3599	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3600	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3601	cErrors++;
3602	continue;
3603	}
3604	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3605	{
3606	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3607
3608	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3609	/*
3610	* Check the PDPTEs too.
3611	*/
3612	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3613
3614	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3615	{
3616	unsigned iPDSrc;
3617	PPGMPOOLPAGE pShwPde = NULL;
3618	PX86PDPE pPdpeDst;
3619	RTGCPHYS GCPhysPdeSrc;
3620	# if PGM_GST_TYPE == PGM_TYPE_PAE
3621	X86PDPE PdpeSrc;
3622	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3623	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3624	# else
3625	PX86PML4E pPml4eSrc;
3626	X86PDPE PdpeSrc;
3627	PX86PDPT pPdptDst;
3628	PX86PDPAE pPDDst;
3629	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3630
3631	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3632	if (rc != VINF_SUCCESS)
3633	{
3634	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3635	GCPtr += 512 * _2M;
3636	continue; /* next PDPTE */
3637	}
3638	Assert(pPDDst);
3639	# endif
3640	Assert(iPDSrc == 0);
3641
3642	pPdpeDst = &pPdptDst->a[iPdpt];
3643
3644	if (!pPdpeDst->n.u1Present)
3645	{
3646	GCPtr += 512 * _2M;
3647	continue; /* next PDPTE */
3648	}
3649
3650	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3651	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3652
3653	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3654	{
3655	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3656	GCPtr += 512 * _2M;
3657	cErrors++;
3658	continue;
3659	}
3660
3661	if (GCPhysPdeSrc != pShwPde->GCPhys)
3662	{
3663	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3664	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3665	# else
3666	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3667	# endif
3668	GCPtr += 512 * _2M;
3669	cErrors++;
3670	continue;
3671	}
3672
3673	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3674	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3675	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3676	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3677	{
3678	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3679	GCPtr += 512 * _2M;
3680	cErrors++;
3681	continue;
3682	}
3683	# endif
3684
3685	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3686	{
3687	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3688	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3689	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3690	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3691	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3692	# endif
3693	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3694	/*
3695	* Iterate the shadow page directory.
3696	*/
3697	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3698	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3699
3700	for (;
3701	iPDDst < cPDEs;
3702	iPDDst++, GCPtr += cIncrement)
3703	{
3704	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3705	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3706	# else
3707	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3708	# endif
3709	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3710	{
3711	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3712	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3713	{
3714	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3715	cErrors++;
3716	continue;
3717	}
3718	}
3719	else if ( (PdeDst.u & X86_PDE_P)
3720	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3721	)
3722	{
3723	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3724	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3725	if (!pPoolPage)
3726	{
3727	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3728	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3729	cErrors++;
3730	continue;
3731	}
3732	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3733
3734	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3735	{
3736	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3737	GCPtr, (uint64_t)PdeDst.u));
3738	cErrors++;
3739	}
3740
3741	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3742	{
3743	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3744	GCPtr, (uint64_t)PdeDst.u));
3745	cErrors++;
3746	}
3747
3748	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3749	if (!PdeSrc.n.u1Present)
3750	{
3751	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3752	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3753	cErrors++;
3754	continue;
3755	}
3756
3757	if ( !PdeSrc.b.u1Size
3758	\|\| !fBigPagesSupported)
3759	{
3760	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3761	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3762	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3763	# endif
3764	}
3765	else
3766	{
3767	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3768	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3769	{
3770	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3771	GCPtr, (uint64_t)PdeSrc.u));
3772	cErrors++;
3773	continue;
3774	}
3775	# endif
3776	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3777	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3778	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3779	# endif
3780	}
3781
3782	if ( pPoolPage->enmKind
3783	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3784	{
3785	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3786	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3787	cErrors++;
3788	}
3789
3790	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3791	if (!pPhysPage)
3792	{
3793	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3794	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3795	cErrors++;
3796	continue;
3797	}
3798
3799	if (GCPhysGst != pPoolPage->GCPhys)
3800	{
3801	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3802	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3803	cErrors++;
3804	continue;
3805	}
3806
3807	if ( !PdeSrc.b.u1Size
3808	\|\| !fBigPagesSupported)
3809	{
3810	/*
3811	* Page Table.
3812	*/
3813	const GSTPT *pPTSrc;
3814	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3815	if (RT_FAILURE(rc))
3816	{
3817	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3818	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3819	cErrors++;
3820	continue;
3821	}
3822	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3823	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3824	{
3825	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3826	// (This problem will go away when/if we shadow multiple CR3s.)
3827	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3828	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3829	cErrors++;
3830	continue;
3831	}
3832	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3833	{
3834	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3835	GCPtr, (uint64_t)PdeDst.u));
3836	cErrors++;
3837	continue;
3838	}
3839
3840	/* iterate the page table. */
3841	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3842	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3843	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3844	# else
3845	const unsigned offPTSrc = 0;
3846	# endif
3847	for (unsigned iPT = 0, off = 0;
3848	iPT < RT_ELEMENTS(pPTDst->a);
3849	iPT++, off += PAGE_SIZE)
3850	{
3851	const SHWPTE PteDst = pPTDst->a[iPT];
3852
3853	/* skip not-present entries. */
3854	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3855	continue;
3856	Assert(PteDst.n.u1Present);
3857
3858	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3859	if (!PteSrc.n.u1Present)
3860	{
3861	# ifdef IN_RING3
3862	PGMAssertHandlerAndFlagsInSync(pVM);
3863	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3864	# endif
3865	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3866	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3867	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3868	cErrors++;
3869	continue;
3870	}
3871
3872	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3873	# if 1 /** @todo sync accessed bit properly... */
3874	fIgnoreFlags \|= X86_PTE_A;
3875	# endif
3876
3877	/* match the physical addresses */
3878	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3879	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3880
3881	# ifdef IN_RING3
3882	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3883	if (RT_FAILURE(rc))
3884	{
3885	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3886	{
3887	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3888	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3889	cErrors++;
3890	continue;
3891	}
3892	}
3893	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3894	{
3895	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3896	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3897	cErrors++;
3898	continue;
3899	}
3900	# endif
3901
3902	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3903	if (!pPhysPage)
3904	{
3905	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3906	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3907	{
3908	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3909	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3910	cErrors++;
3911	continue;
3912	}
3913	# endif
3914	if (PteDst.n.u1Write)
3915	{
3916	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3917	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3918	cErrors++;
3919	}
3920	fIgnoreFlags \|= X86_PTE_RW;
3921	}
3922	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3923	{
3924	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3925	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3926	cErrors++;
3927	continue;
3928	}
3929
3930	/* flags */
3931	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3932	{
3933	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3934	{
3935	if (PteDst.n.u1Write)
3936	{
3937	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3938	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3939	cErrors++;
3940	continue;
3941	}
3942	fIgnoreFlags \|= X86_PTE_RW;
3943	}
3944	else
3945	{
3946	if (PteDst.n.u1Present)
3947	{
3948	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3949	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3950	cErrors++;
3951	continue;
3952	}
3953	fIgnoreFlags \|= X86_PTE_P;
3954	}
3955	}
3956	else
3957	{
3958	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3959	{
3960	if (PteDst.n.u1Write)
3961	{
3962	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3963	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3964	cErrors++;
3965	continue;
3966	}
3967	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3968	{
3969	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3970	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3971	cErrors++;
3972	continue;
3973	}
3974	if (PteDst.n.u1Dirty)
3975	{
3976	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3977	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3978	cErrors++;
3979	}
3980	# if 0 /** @todo sync access bit properly... */
3981	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3982	{
3983	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3984	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3985	cErrors++;
3986	}
3987	fIgnoreFlags \|= X86_PTE_RW;
3988	# else
3989	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3990	# endif
3991	}
3992	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3993	{
3994	/* access bit emulation (not implemented). */
3995	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3996	{
3997	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3998	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3999	cErrors++;
4000	continue;
4001	}
4002	if (!PteDst.n.u1Accessed)
4003	{
4004	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4005	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4006	cErrors++;
4007	}
4008	fIgnoreFlags \|= X86_PTE_P;
4009	}
4010	# ifdef DEBUG_sandervl
4011	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4012	# endif
4013	}
4014
4015	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4016	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4017	)
4018	{
4019	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4020	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4021	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4022	cErrors++;
4023	continue;
4024	}
4025	} /* foreach PTE */
4026	}
4027	else
4028	{
4029	/*
4030	* Big Page.
4031	*/
4032	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4033	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4034	{
4035	if (PdeDst.n.u1Write)
4036	{
4037	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4038	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4039	cErrors++;
4040	continue;
4041	}
4042	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4043	{
4044	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4045	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4046	cErrors++;
4047	continue;
4048	}
4049	# if 0 /** @todo sync access bit properly... */
4050	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4051	{
4052	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4053	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4054	cErrors++;
4055	}
4056	fIgnoreFlags \|= X86_PTE_RW;
4057	# else
4058	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4059	# endif
4060	}
4061	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4062	{
4063	/* access bit emulation (not implemented). */
4064	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4065	{
4066	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4067	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4068	cErrors++;
4069	continue;
4070	}
4071	if (!PdeDst.n.u1Accessed)
4072	{
4073	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4074	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4075	cErrors++;
4076	}
4077	fIgnoreFlags \|= X86_PTE_P;
4078	}
4079
4080	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4081	{
4082	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4083	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4084	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4085	cErrors++;
4086	}
4087
4088	/* iterate the page table. */
4089	for (unsigned iPT = 0, off = 0;
4090	iPT < RT_ELEMENTS(pPTDst->a);
4091	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4092	{
4093	const SHWPTE PteDst = pPTDst->a[iPT];
4094
4095	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4096	{
4097	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4098	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4099	cErrors++;
4100	}
4101
4102	/* skip not-present entries. */
4103	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4104	continue;
4105
4106	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4107
4108	/* match the physical addresses */
4109	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4110
4111	# ifdef IN_RING3
4112	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4113	if (RT_FAILURE(rc))
4114	{
4115	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4116	{
4117	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4118	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4119	cErrors++;
4120	}
4121	}
4122	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4123	{
4124	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4125	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4126	cErrors++;
4127	continue;
4128	}
4129	# endif
4130	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4131	if (!pPhysPage)
4132	{
4133	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4134	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4135	{
4136	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4137	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4138	cErrors++;
4139	continue;
4140	}
4141	# endif
4142	if (PteDst.n.u1Write)
4143	{
4144	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4145	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4146	cErrors++;
4147	}
4148	fIgnoreFlags \|= X86_PTE_RW;
4149	}
4150	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4151	{
4152	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4153	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4154	cErrors++;
4155	continue;
4156	}
4157
4158	/* flags */
4159	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4160	{
4161	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4162	{
4163	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4164	{
4165	if (PteDst.n.u1Write)
4166	{
4167	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4168	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4169	cErrors++;
4170	continue;
4171	}
4172	fIgnoreFlags \|= X86_PTE_RW;
4173	}
4174	}
4175	else
4176	{
4177	if (PteDst.n.u1Present)
4178	{
4179	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4180	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4181	cErrors++;
4182	continue;
4183	}
4184	fIgnoreFlags \|= X86_PTE_P;
4185	}
4186	}
4187
4188	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4189	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4190	)
4191	{
4192	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4193	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4194	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4195	cErrors++;
4196	continue;
4197	}
4198	} /* for each PTE */
4199	}
4200	}
4201	/* not present */
4202
4203	} /* for each PDE */
4204
4205	} /* for each PDPTE */
4206
4207	} /* for each PML4E */
4208
4209	# ifdef DEBUG
4210	if (cErrors)
4211	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4212	# endif
4213
4214	#endif /* GST == 32BIT, PAE or AMD64 */
4215	return cErrors;
4216
4217	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4218	}
4219	#endif /* VBOX_STRICT */
4220
4221
4222	/**
4223	* Sets up the CR3 for shadow paging
4224	*
4225	* @returns Strict VBox status code.
4226	* @retval VINF_SUCCESS.
4227	*
4228	* @param pVCpu The VMCPU handle.
4229	* @param GCPhysCR3 The physical address in the CR3 register.
4230	*/
4231	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4232	{
4233	PVM pVM = pVCpu->CTX_SUFF(pVM);
4234
4235	/* Update guest paging info. */
4236	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4237	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4238	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4239
4240	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4241
4242	/*
4243	* Map the page CR3 points at.
4244	*/
4245	RTHCPTR HCPtrGuestCR3;
4246	RTHCPHYS HCPhysGuestCR3;
4247	pgmLock(pVM);
4248	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4249	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4250	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4251	/** @todo this needs some reworking wrt. locking. */
4252	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4253	HCPtrGuestCR3 = NIL_RTHCPTR;
4254	int rc = VINF_SUCCESS;
4255	# else
4256	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4257	# endif
4258	pgmUnlock(pVM);
4259	if (RT_SUCCESS(rc))
4260	{
4261	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4262	if (RT_SUCCESS(rc))
4263	{
4264	# ifdef IN_RC
4265	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4266	# endif
4267	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4268	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4269	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4270	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4271	# endif
4272	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4273
4274	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4275	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4276	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4277	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4278	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4279	# endif
4280	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4281	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4282
4283	/*
4284	* Map the 4 PDs too.
4285	*/
4286	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4287	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4288	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4289	{
4290	if (pGuestPDPT->a[i].n.u1Present)
4291	{
4292	RTHCPTR HCPtr;
4293	RTHCPHYS HCPhys;
4294	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4295	pgmLock(pVM);
4296	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4297	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4298	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4299	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4300	HCPtr = NIL_RTHCPTR;
4301	int rc2 = VINF_SUCCESS;
4302	# else
4303	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4304	# endif
4305	pgmUnlock(pVM);
4306	if (RT_SUCCESS(rc2))
4307	{
4308	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4309	AssertRCReturn(rc, rc);
4310
4311	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4312	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4313	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4314	# endif
4315	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4316	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4317	# ifdef IN_RC
4318	PGM_INVL_PG(pVCpu, GCPtr);
4319	# endif
4320	continue;
4321	}
4322	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4323	}
4324
4325	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4326	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4327	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4328	# endif
4329	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4330	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4331	# ifdef IN_RC
4332	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4333	# endif
4334	}
4335
4336	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4337	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4338	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4339	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4340	# endif
4341	# endif
4342	}
4343	else
4344	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4345	}
4346	else
4347	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4348
4349	#else /* prot/real stub */
4350	int rc = VINF_SUCCESS;
4351	#endif
4352
4353	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4354	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4355	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4356	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4357	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4358	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4359
4360	Assert(!HWACCMIsNestedPagingActive(pVM));
4361
4362	/*
4363	* Update the shadow root page as well since that's not fixed.
4364	*/
4365	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4366	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4367	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4368	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4369	PPGMPOOLPAGE pNewShwPageCR3;
4370
4371	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4372	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4373	AssertFatalRC(rc);
4374	rc = VINF_SUCCESS;
4375
4376	/* Mark the page as locked; disallow flushing. */
4377	pgmPoolLockPage(pPool, pNewShwPageCR3);
4378
4379	# ifdef IN_RC
4380	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4381	bool fLog = VMMGCLogDisable(pVM);
4382	pgmLock(pVM);
4383	# endif
4384
4385	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4386	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4387	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4388	# ifdef IN_RING0
4389	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4390	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4391	# elif defined(IN_RC)
4392	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4393	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4394	# else
4395	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4396	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4397	# endif
4398
4399	# ifndef PGM_WITHOUT_MAPPINGS
4400	/*
4401	* Apply all hypervisor mappings to the new CR3.
4402	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4403	* make sure we check for conflicts in the new CR3 root.
4404	*/
4405	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4406	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4407	# endif
4408	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4409	AssertRCReturn(rc, rc);
4410	# endif
4411
4412	/* Set the current hypervisor CR3. */
4413	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4414	SELMShadowCR3Changed(pVM, pVCpu);
4415
4416	# ifdef IN_RC
4417	pgmUnlock(pVM);
4418	VMMGCLogRestore(pVM, fLog);
4419	# endif
4420
4421	/* Clean up the old CR3 root. */
4422	if (pOldShwPageCR3)
4423	{
4424	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4425	# ifndef PGM_WITHOUT_MAPPINGS
4426	/* Remove the hypervisor mappings from the shadow page table. */
4427	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4428	# endif
4429	/* Mark the page as unlocked; allow flushing again. */
4430	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4431
4432	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4433	}
4434
4435	# endif
4436
4437	return rc;
4438	}
4439
4440	/**
4441	* Unmaps the shadow CR3.
4442	*
4443	* @returns VBox status, no specials.
4444	* @param pVCpu The VMCPU handle.
4445	*/
4446	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4447	{
4448	LogFlow(("UnmapCR3\n"));
4449
4450	int rc = VINF_SUCCESS;
4451	PVM pVM = pVCpu->CTX_SUFF(pVM);
4452
4453	/*
4454	* Update guest paging info.
4455	*/
4456	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4457	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4458	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4459	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4460	# endif
4461	pVCpu->pgm.s.pGst32BitPdRC = 0;
4462
4463	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4464	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4465	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4466	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4467	# endif
4468	pVCpu->pgm.s.pGstPaePdptRC = 0;
4469	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4470	{
4471	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4472	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4473	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4474	# endif
4475	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4476	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4477	}
4478
4479	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4480	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4481	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4482	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4483	# endif
4484
4485	#else /* prot/real mode stub */
4486	/* nothing to do */
4487	#endif
4488
4489	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4490	/*
4491	* Update shadow paging info.
4492	*/
4493	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4494	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4495	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4496
4497	# if PGM_GST_TYPE != PGM_TYPE_REAL
4498	Assert(!HWACCMIsNestedPagingActive(pVM));
4499	# endif
4500
4501	# ifndef PGM_WITHOUT_MAPPINGS
4502	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4503	/* Remove the hypervisor mappings from the shadow page table. */
4504	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4505	# endif
4506
4507	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4508	{
4509	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4510
4511	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4512
4513	/* Mark the page as unlocked; allow flushing again. */
4514	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4515
4516	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4517	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4518	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4519	pVCpu->pgm.s.pShwPageCR3RC = 0;
4520	pVCpu->pgm.s.iShwUser = 0;
4521	pVCpu->pgm.s.iShwUserTable = 0;
4522	}
4523	# endif
4524	#endif /* !IN_RC*/
4525
4526	return rc;
4527	}
4528

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 19979

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