PGMAllBth.h@ 20127

Last change on this file since 20127 was 20127, checked in by vboxsync, 16 years ago
Cleaned up
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File size: 194.0 KB

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1	/* $Id: PGMAllBth.h 20127 2009-05-28 15:48:56Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	__END_DECLS
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc;
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc;
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	pgmLock(pVM);
165	{ /* Force the shadow pointers to go out of scope after releasing the lock. */
166	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
167	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
168	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
169
170	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
171	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
172
173	PX86PDPAE pPDDst;
174	# if PGM_GST_TYPE != PGM_TYPE_PAE
175	X86PDPE PdpeSrc;
176
177	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
178	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
179	# endif
180	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
181	if (rc != VINF_SUCCESS)
182	{
183	pgmUnlock(pVM);
184	AssertRC(rc);
185	return rc;
186	}
187	Assert(pPDDst);
188
189	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
190	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
191	PX86PDPAE pPDDst;
192	# if PGM_GST_TYPE == PGM_TYPE_PROT
193	/* AMD-V nested paging */
194	X86PML4E Pml4eSrc;
195	X86PDPE PdpeSrc;
196	PX86PML4E pPml4eSrc = &Pml4eSrc;
197
198	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
199	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
200	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
201	# endif
202
203	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
204	if (rc != VINF_SUCCESS)
205	{
206	pgmUnlock(pVM);
207	AssertRC(rc);
208	return rc;
209	}
210	Assert(pPDDst);
211
212	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
213	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
214	PEPTPD pPDDst;
215
216	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
217	if (rc != VINF_SUCCESS)
218	{
219	pgmUnlock(pVM);
220	AssertRC(rc);
221	return rc;
222	}
223	Assert(pPDDst);
224	# endif
225
226	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
227	/*
228	* If we successfully correct the write protection fault due to dirty bit
229	* tracking, or this page fault is a genuine one, then return immediately.
230	*/
231	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
232	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
233	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
234	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
235	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
236	{
237	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
238	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
239	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
240	pgmUnlock(pVM);
241	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
242	}
243
244	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
245	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
246
247	/*
248	* A common case is the not-present error caused by lazy page table syncing.
249	*
250	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
251	* so we can safely assume that the shadow PT is present when calling SyncPage later.
252	*
253	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
254	* of mapping conflict and defer to SyncCR3 in R3.
255	* (Again, we do NOT support access handlers for non-present guest pages.)
256	*
257	*/
258	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
259	&& !pPDDst->a[iPDDst].n.u1Present
260	&& PdeSrc.n.u1Present
261	)
262	{
263	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
264	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
265	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
267	pgmUnlock(pVM);
268	if (RT_SUCCESS(rc))
269	{
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return rc;
272	}
273	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
274	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
275	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
276	return VINF_PGM_SYNC_CR3;
277	}
278	pgmUnlock(pVM);
279	}
280
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
282	/*
283	* Check if this address is within any of our mappings.
284	*
285	* This is very fast and it's gonna save us a bit of effort below and prevent
286	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
287	* (BTW, it's impossible to have physical access handlers in a mapping.)
288	*/
289	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
290	{
291	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
292	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
293	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
294	{
295	if (pvFault < pMapping->GCPtr)
296	break;
297	if (pvFault - pMapping->GCPtr < pMapping->cb)
298	{
299	/*
300	* The first thing we check is if we've got an undetected conflict.
301	*/
302	if (!pVM->pgm.s.fMappingsFixed)
303	{
304	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
305	while (iPT-- > 0)
306	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
307	{
308	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
309	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
310	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
311	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
312	return VINF_PGM_SYNC_CR3;
313	}
314	}
315
316	/*
317	* Check if the fault address is in a virtual page access handler range.
318	*/
319	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
320	if ( pCur
321	&& pvFault - pCur->Core.Key < pCur->cb
322	&& uErr & X86_TRAP_PF_RW)
323	{
324	# ifdef IN_RC
325	STAM_PROFILE_START(&pCur->Stat, h);
326	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
327	STAM_PROFILE_STOP(&pCur->Stat, h);
328	# else
329	AssertFailed();
330	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
331	# endif
332	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
333	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
334	return rc;
335	}
336
337	/*
338	* Pretend we're not here and let the guest handle the trap.
339	*/
340	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
341	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
342	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
343	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
344	return VINF_EM_RAW_GUEST_TRAP;
345	}
346	}
347	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
348	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
349	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
350
351	/*
352	* Check if this fault address is flagged for special treatment,
353	* which means we'll have to figure out the physical address and
354	* check flags associated with it.
355	*
356	* ASSUME that we can limit any special access handling to pages
357	* in page tables which the guest believes to be present.
358	*/
359	if (PdeSrc.n.u1Present)
360	{
361	RTGCPHYS GCPhys = NIL_RTGCPHYS;
362
363	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
364	# if PGM_GST_TYPE == PGM_TYPE_AMD64
365	bool fBigPagesSupported = true;
366	# else
367	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
368	# endif
369	if ( PdeSrc.b.u1Size
370	&& fBigPagesSupported)
371	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
372	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
373	else
374	{
375	PGSTPT pPTSrc;
376	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
377	if (RT_SUCCESS(rc))
378	{
379	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
380	if (pPTSrc->a[iPTESrc].n.u1Present)
381	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
382	}
383	}
384	# else
385	/* No paging so the fault address is the physical address */
386	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
387	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
388
389	/*
390	* If we have a GC address we'll check if it has any flags set.
391	*/
392	if (GCPhys != NIL_RTGCPHYS)
393	{
394	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
395
396	PPGMPAGE pPage;
397	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
398	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
399	{
400	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
401	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
402	{
403	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
404	{
405	/*
406	* Physical page access handler.
407	*/
408	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
409	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
410	if (pCur)
411	{
412	# ifdef PGM_SYNC_N_PAGES
413	/*
414	* If the region is write protected and we got a page not present fault, then sync
415	* the pages. If the fault was caused by a read, then restart the instruction.
416	* In case of write access continue to the GC write handler.
417	*
418	* ASSUMES that there is only one handler per page or that they have similar write properties.
419	*/
420	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
421	&& !(uErr & X86_TRAP_PF_P))
422	{
423	pgmLock(pVM);
424	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
425	pgmUnlock(pVM);
426	if ( RT_FAILURE(rc)
427	\|\| !(uErr & X86_TRAP_PF_RW)
428	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
429	{
430	AssertRC(rc);
431	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
432	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
433	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
434	return rc;
435	}
436	}
437	# endif
438
439	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
440	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
441	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
442
443	# if defined(IN_RC) \|\| defined(IN_RING0)
444	if (pCur->CTX_SUFF(pfnHandler))
445	{
446	STAM_PROFILE_START(&pCur->Stat, h);
447	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pCur->CTX_SUFF(pvUser));
448	STAM_PROFILE_STOP(&pCur->Stat, h);
449	}
450	else
451	# endif
452	rc = VINF_EM_RAW_EMULATE_INSTR;
453	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
454	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
455	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
456	return rc;
457	}
458	}
459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
460	else
461	{
462	# ifdef PGM_SYNC_N_PAGES
463	/*
464	* If the region is write protected and we got a page not present fault, then sync
465	* the pages. If the fault was caused by a read, then restart the instruction.
466	* In case of write access continue to the GC write handler.
467	*/
468	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
469	&& !(uErr & X86_TRAP_PF_P))
470	{
471	pgmLock(pVM);
472	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
473	pgmUnlock(pVM);
474	if ( RT_FAILURE(rc)
475	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
476	\|\| !(uErr & X86_TRAP_PF_RW))
477	{
478	AssertRC(rc);
479	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
480	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
481	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
482	return rc;
483	}
484	}
485	# endif
486	/*
487	* Ok, it's an virtual page access handler.
488	*
489	* Since it's faster to search by address, we'll do that first
490	* and then retry by GCPhys if that fails.
491	*/
492	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
493	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
494	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
495	*/
496	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
497	if (pCur)
498	{
499	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
500	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
501	\|\| !(uErr & X86_TRAP_PF_P)
502	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
503	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
504
505	if ( pvFault - pCur->Core.Key < pCur->cb
506	&& ( uErr & X86_TRAP_PF_RW
507	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
508	{
509	# ifdef IN_RC
510	STAM_PROFILE_START(&pCur->Stat, h);
511	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
512	STAM_PROFILE_STOP(&pCur->Stat, h);
513	# else
514	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
515	# endif
516	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
517	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
518	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
519	return rc;
520	}
521	/* Unhandled part of a monitored page */
522	}
523	else
524	{
525	/* Check by physical address. */
526	PPGMVIRTHANDLER pCur;
527	unsigned iPage;
528	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
529	&pCur, &iPage);
530	Assert(RT_SUCCESS(rc) \|\| !pCur);
531	if ( pCur
532	&& ( uErr & X86_TRAP_PF_RW
533	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
534	{
535	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
536	# ifdef IN_RC
537	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
538	Assert(off < pCur->cb);
539	STAM_PROFILE_START(&pCur->Stat, h);
540	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
541	STAM_PROFILE_STOP(&pCur->Stat, h);
542	# else
543	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
544	# endif
545	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
546	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
547	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
548	return rc;
549	}
550	}
551	}
552	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
553
554	/*
555	* There is a handled area of the page, but this fault doesn't belong to it.
556	* We must emulate the instruction.
557	*
558	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
559	* we first check if this was a page-not-present fault for a page with only
560	* write access handlers. Restart the instruction if it wasn't a write access.
561	*/
562	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
563
564	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
565	&& !(uErr & X86_TRAP_PF_P))
566	{
567	pgmLock(pVM);
568	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
569	pgmUnlock(pVM);
570	if ( RT_FAILURE(rc)
571	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
572	\|\| !(uErr & X86_TRAP_PF_RW))
573	{
574	AssertRC(rc);
575	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
576	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
577	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
578	return rc;
579	}
580	}
581
582	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
583	* It's writing to an unhandled part of the LDT page several million times.
584	*/
585	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
586	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
587	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
588	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
589	return rc;
590	} /* if any kind of handler */
591
592	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
593	if (uErr & X86_TRAP_PF_P)
594	{
595	/*
596	* The page isn't marked, but it might still be monitored by a virtual page access handler.
597	* (ASSUMES no temporary disabling of virtual handlers.)
598	*/
599	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
600	* we should correct both the shadow page table and physical memory flags, and not only check for
601	* accesses within the handler region but for access to pages with virtual handlers. */
602	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
603	if (pCur)
604	{
605	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
606	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
607	\|\| !(uErr & X86_TRAP_PF_P)
608	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
609	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
610
611	if ( pvFault - pCur->Core.Key < pCur->cb
612	&& ( uErr & X86_TRAP_PF_RW
613	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
614	{
615	# ifdef IN_RC
616	STAM_PROFILE_START(&pCur->Stat, h);
617	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
618	STAM_PROFILE_STOP(&pCur->Stat, h);
619	# else
620	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
621	# endif
622	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
623	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
624	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
625	return rc;
626	}
627	}
628	}
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630	}
631	else
632	{
633	/*
634	* When the guest accesses invalid physical memory (e.g. probing
635	* of RAM or accessing a remapped MMIO range), then we'll fall
636	* back to the recompiler to emulate the instruction.
637	*/
638	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
639	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
640	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
641	return VINF_EM_RAW_EMULATE_INSTR;
642	}
643
644	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
645
646	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
647	/*
648	* We are here only if page is present in Guest page tables and
649	* trap is not handled by our handlers.
650	*
651	* Check it for page out-of-sync situation.
652	*/
653	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
654
655	if (!(uErr & X86_TRAP_PF_P))
656	{
657	/*
658	* Page is not present in our page tables.
659	* Try to sync it!
660	* BTW, fPageShw is invalid in this branch!
661	*/
662	if (uErr & X86_TRAP_PF_US)
663	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
664	else /* supervisor */
665	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
666
667	# if defined(LOG_ENABLED) && !defined(IN_RING0)
668	RTGCPHYS GCPhys;
669	uint64_t fPageGst;
670	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
671	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
672	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
673	# endif /* LOG_ENABLED */
674
675	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
676	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
677	{
678	uint64_t fPageGst;
679	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
680	if ( RT_SUCCESS(rc)
681	&& !(fPageGst & X86_PTE_US))
682	{
683	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
684	if ( pvFault == (RTGCPTR)pRegFrame->eip
685	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
686	# ifdef CSAM_DETECT_NEW_CODE_PAGES
687	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
688	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
689	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
690	)
691	{
692	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
693	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
694	if (rc != VINF_SUCCESS)
695	{
696	/*
697	* CSAM needs to perform a job in ring 3.
698	*
699	* Sync the page before going to the host context; otherwise we'll end up in a loop if
700	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
701	*/
702	LogFlow(("CSAM ring 3 job\n"));
703	pgmLock(pVM);
704	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
705	pgmUnlock(pVM);
706	AssertRC(rc2);
707
708	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
709	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
710	return rc;
711	}
712	}
713	# ifdef CSAM_DETECT_NEW_CODE_PAGES
714	else if ( uErr == X86_TRAP_PF_RW
715	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
716	&& pRegFrame->ecx < 0x10000)
717	{
718	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
719	* to detect loading of new code pages.
720	*/
721
722	/*
723	* Decode the instruction.
724	*/
725	RTGCPTR PC;
726	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
727	if (rc == VINF_SUCCESS)
728	{
729	DISCPUSTATE Cpu;
730	uint32_t cbOp;
731	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, &Cpu, &cbOp);
732
733	/* For now we'll restrict this to rep movsw/d instructions */
734	if ( rc == VINF_SUCCESS
735	&& Cpu.pCurInstr->opcode == OP_MOVSWD
736	&& (Cpu.prefix & PREFIX_REP))
737	{
738	CSAMMarkPossibleCodePage(pVM, pvFault);
739	}
740	}
741	}
742	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
743
744	/*
745	* Mark this page as safe.
746	*/
747	/** @todo not correct for pages that contain both code and data!! */
748	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
749	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
750	}
751	}
752	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
753	pgmLock(pVM);
754	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
755	pgmUnlock(pVM);
756	if (RT_SUCCESS(rc))
757	{
758	/* The page was successfully synced, return to the guest. */
759	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
760	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
761	return VINF_SUCCESS;
762	}
763	}
764	else /* uErr & X86_TRAP_PF_P: */
765	{
766	/*
767	* Write protected pages are make writable when the guest makes the first
768	* write to it. This happens for pages that are shared, write monitored
769	* and not yet allocated.
770	*
771	* Also, a side effect of not flushing global PDEs are out of sync pages due
772	* to physical monitored regions, that are no longer valid.
773	* Assume for now it only applies to the read/write flag.
774	*/
775	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
776	{
777	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
778	{
779	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
780	GCPhys, pPage, pvFault, uErr));
781	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
782	if (rc != VINF_SUCCESS)
783	{
784	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
785	return rc;
786	}
787	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
788	return VINF_EM_NO_MEMORY;
789	}
790	/// @todo count the above case; else
791	if (uErr & X86_TRAP_PF_US)
792	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
793	else /* supervisor */
794	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
795
796	/*
797	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
798	* page is not present, which is not true in this case.
799	*/
800	pgmLock(pVM);
801	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
802	# ifndef VBOX_STRICT
803	/* Keep it locked in VBOX_STRICT mode so the next checks won't trigger without reason with guest SMP. */
804	pgmUnlock(pVM);
805	# endif
806	if (RT_SUCCESS(rc))
807	{
808	/*
809	* Page was successfully synced, return to guest.
810	*/
811	# ifdef VBOX_STRICT
812	RTGCPHYS GCPhys;
813	uint64_t fPageGst;
814	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
815	Assert(RT_SUCCESS(rc) && fPageGst & X86_PTE_RW);
816	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
817
818	uint64_t fPageShw;
819	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
820	AssertMsg((RT_SUCCESS(rc) && ((fPageShw & X86_PTE_RW) \|\| pVM->cCPUs > 1 /* new monitor can be installed during trap e execution */)), ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
821	pgmUnlock(pVM);
822	# endif /* VBOX_STRICT */
823	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
824	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
825	return VINF_SUCCESS;
826	}
827	# ifdef VBOX_STRICT
828	pgmUnlock(pVM);
829	# endif
830
831	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
832	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
833	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG)
834	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
835	{
836	uint64_t fPageGst;
837	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
838	if ( RT_SUCCESS(rc)
839	&& !(fPageGst & X86_PTE_RW))
840	{
841	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
842	if (RT_SUCCESS(rc))
843	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
844	else
845	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
846	return rc;
847	}
848	AssertMsgFailed(("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
849	}
850	}
851
852	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
853	# ifdef VBOX_STRICT
854	/*
855	* Check for VMM page flags vs. Guest page flags consistency.
856	* Currently only for debug purposes.
857	*/
858	if (RT_SUCCESS(rc))
859	{
860	/* Get guest page flags. */
861	uint64_t fPageGst;
862	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
863	if (RT_SUCCESS(rc))
864	{
865	uint64_t fPageShw;
866	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
867
868	/*
869	* Compare page flags.
870	* Note: we have AVL, A, D bits desynched.
871	*/
872	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
873	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
874	}
875	else
876	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
877	}
878	else
879	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
880	# endif /* VBOX_STRICT */
881	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
882	}
883	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
884	# endif /* PGM_OUT_OF_SYNC_IN_GC */
885	}
886	else /* GCPhys == NIL_RTGCPHYS */
887	{
888	/*
889	* Page not present in Guest OS or invalid page table address.
890	* This is potential virtual page access handler food.
891	*
892	* For the present we'll say that our access handlers don't
893	* work for this case - we've already discarded the page table
894	* not present case which is identical to this.
895	*
896	* When we perchance find we need this, we will probably have AVL
897	* trees (offset based) to operate on and we can measure their speed
898	* agains mapping a page table and probably rearrange this handling
899	* a bit. (Like, searching virtual ranges before checking the
900	* physical address.)
901	*/
902	}
903	}
904	/* else: !present (guest) */
905
906
907	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
908	/*
909	* Conclusion, this is a guest trap.
910	*/
911	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
912	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
913	return VINF_EM_RAW_GUEST_TRAP;
914	# else
915	/* present, but not a monitored page; perhaps the guest is probing physical memory */
916	return VINF_EM_RAW_EMULATE_INSTR;
917	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
918
919
920	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
921
922	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
923	return VERR_INTERNAL_ERROR;
924	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
925	}
926	#endif /* !IN_RING3 */
927
928
929	/**
930	* Emulation of the invlpg instruction.
931	*
932	*
933	* @returns VBox status code.
934	*
935	* @param pVCpu The VMCPU handle.
936	* @param GCPtrPage Page to invalidate.
937	*
938	* @remark ASSUMES that the guest is updating before invalidating. This order
939	* isn't required by the CPU, so this is speculative and could cause
940	* trouble.
941	* @remark No TLB shootdown is done on any other VCPU as we assume that
942	* invlpg emulation is the only reason for calling this function.
943	* (The guest has to shoot down TLB entries on other CPUs itself)
944	* Currently true, but keep in mind!
945	*
946	* @todo Flush page or page directory only if necessary!
947	* @todo Add a #define for simply invalidating the page.
948	*/
949	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
950	{
951	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
952	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
953	&& PGM_SHW_TYPE != PGM_TYPE_EPT
954	int rc;
955	PVM pVM = pVCpu->CTX_SUFF(pVM);
956	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
957
958	Assert(PGMIsLockOwner(pVM));
959
960	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
961	/*
962	* Get the shadow PD entry and skip out if this PD isn't present.
963	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
964	*/
965	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
966	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
967	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
968
969	/* Fetch the pgm pool shadow descriptor. */
970	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
971	Assert(pShwPde);
972
973	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
974	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
975	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
976
977	/* If the shadow PDPE isn't present, then skip the invalidate. */
978	if (!pPdptDst->a[iPdpt].n.u1Present)
979	{
980	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
981	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
982	return VINF_SUCCESS;
983	}
984
985	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
986	PPGMPOOLPAGE pShwPde = NULL;
987	PX86PDPAE pPDDst;
988
989	/* Fetch the pgm pool shadow descriptor. */
990	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
991	AssertRCSuccessReturn(rc, rc);
992	Assert(pShwPde);
993
994	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
995	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
996
997	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
998	/* PML4 */
999	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1000	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1001	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1002	PX86PDPAE pPDDst;
1003	PX86PDPT pPdptDst;
1004	PX86PML4E pPml4eDst;
1005	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1006	if (rc != VINF_SUCCESS)
1007	{
1008	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1009	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1010	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1011	PGM_INVL_VCPU_TLBS(pVCpu);
1012	return VINF_SUCCESS;
1013	}
1014	Assert(pPDDst);
1015
1016	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1017	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1018
1019	if (!pPdpeDst->n.u1Present)
1020	{
1021	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1022	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1023	PGM_INVL_VCPU_TLBS(pVCpu);
1024	return VINF_SUCCESS;
1025	}
1026
1027	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1028
1029	const SHWPDE PdeDst = *pPdeDst;
1030	if (!PdeDst.n.u1Present)
1031	{
1032	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1033	return VINF_SUCCESS;
1034	}
1035
1036	# if defined(IN_RC)
1037	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1038	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1039	# endif
1040
1041	/*
1042	* Get the guest PD entry and calc big page.
1043	*/
1044	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1045	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1046	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1047	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1048	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1049	unsigned iPDSrc = 0;
1050	# if PGM_GST_TYPE == PGM_TYPE_PAE
1051	X86PDPE PdpeSrc;
1052	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1053	# else /* AMD64 */
1054	PX86PML4E pPml4eSrc;
1055	X86PDPE PdpeSrc;
1056	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1057	# endif
1058	GSTPDE PdeSrc;
1059
1060	if (pPDSrc)
1061	PdeSrc = pPDSrc->a[iPDSrc];
1062	else
1063	PdeSrc.u = 0;
1064	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1065
1066	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1067	const bool fIsBigPage = PdeSrc.b.u1Size;
1068	# else
1069	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1070	# endif
1071
1072	# ifdef IN_RING3
1073	/*
1074	* If a CR3 Sync is pending we may ignore the invalidate page operation
1075	* depending on the kind of sync and if it's a global page or not.
1076	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1077	*/
1078	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1079	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1080	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1081	&& fIsBigPage
1082	&& PdeSrc.b.u1Global
1083	)
1084	)
1085	# else
1086	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1087	# endif
1088	{
1089	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1090	return VINF_SUCCESS;
1091	}
1092	# endif /* IN_RING3 */
1093
1094	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1095	/* Fetch the pgm pool shadow descriptor. */
1096	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1097	Assert(pShwPdpt);
1098
1099	/* Fetch the pgm pool shadow descriptor. */
1100	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1101	Assert(pShwPde);
1102
1103	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1104	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1105
1106	if ( !pPml4eSrc->n.u1Present
1107	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1108	{
1109	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1110	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1111	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1112	ASMAtomicWriteSize(pPml4eDst, 0);
1113	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1114	PGM_INVL_VCPU_TLBS(pVCpu);
1115	return VINF_SUCCESS;
1116	}
1117	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1118	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1119	{
1120	/*
1121	* Mark not present so we can resync the PML4E when it's used.
1122	*/
1123	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1124	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1125	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1126	ASMAtomicWriteSize(pPml4eDst, 0);
1127	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1128	PGM_INVL_VCPU_TLBS(pVCpu);
1129	}
1130	else if (!pPml4eSrc->n.u1Accessed)
1131	{
1132	/*
1133	* Mark not present so we can set the accessed bit.
1134	*/
1135	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1136	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1137	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1138	ASMAtomicWriteSize(pPml4eDst, 0);
1139	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1140	PGM_INVL_VCPU_TLBS(pVCpu);
1141	}
1142
1143	/* Check if the PDPT entry has changed. */
1144	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1145	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1146	if ( !PdpeSrc.n.u1Present
1147	\|\| pShwPde->GCPhys != GCPhysPd)
1148	{
1149	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1150	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1151	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1152	ASMAtomicWriteSize(pPdpeDst, 0);
1153	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1154	PGM_INVL_VCPU_TLBS(pVCpu);
1155	return VINF_SUCCESS;
1156	}
1157	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1158	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1159	{
1160	/*
1161	* Mark not present so we can resync the PDPTE when it's used.
1162	*/
1163	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1164	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1165	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1166	ASMAtomicWriteSize(pPdpeDst, 0);
1167	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1168	PGM_INVL_VCPU_TLBS(pVCpu);
1169	}
1170	else if (!PdpeSrc.lm.u1Accessed)
1171	{
1172	/*
1173	* Mark not present so we can set the accessed bit.
1174	*/
1175	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1176	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1177	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1178	ASMAtomicWriteSize(pPdpeDst, 0);
1179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1180	PGM_INVL_VCPU_TLBS(pVCpu);
1181	}
1182	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1183
1184	/*
1185	* Deal with the Guest PDE.
1186	*/
1187	rc = VINF_SUCCESS;
1188	if (PdeSrc.n.u1Present)
1189	{
1190	# ifndef PGM_WITHOUT_MAPPING
1191	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1192	{
1193	/*
1194	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1195	*/
1196	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1197	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1198	pgmLock(pVM);
1199	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1200	pgmUnlock(pVM);
1201	}
1202	else
1203	# endif /* !PGM_WITHOUT_MAPPING */
1204	if ( PdeSrc.n.u1User != PdeDst.n.u1User
1205	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1206	{
1207	/*
1208	* Mark not present so we can resync the PDE when it's used.
1209	*/
1210	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1211	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1212	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1213	ASMAtomicWriteSize(pPdeDst, 0);
1214	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1215	PGM_INVL_VCPU_TLBS(pVCpu);
1216	}
1217	else if (!PdeSrc.n.u1Accessed)
1218	{
1219	/*
1220	* Mark not present so we can set the accessed bit.
1221	*/
1222	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1223	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1224	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1225	ASMAtomicWriteSize(pPdeDst, 0);
1226	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1227	PGM_INVL_VCPU_TLBS(pVCpu);
1228	}
1229	else if (!fIsBigPage)
1230	{
1231	/*
1232	* 4KB - page.
1233	*/
1234	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1235	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1236	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1237	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1238	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1239	# endif
1240	if (pShwPage->GCPhys == GCPhys)
1241	{
1242	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1243	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1244	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1245	if (pPT->a[iPTEDst].n.u1Present)
1246	{
1247	# ifdef PGMPOOL_WITH_USER_TRACKING
1248	/* This is very unlikely with caching/monitoring enabled. */
1249	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1250	# endif
1251	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1252	}
1253	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1254	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1255	if (RT_SUCCESS(rc))
1256	rc = VINF_SUCCESS;
1257	# endif
1258	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1259	PGM_INVL_PG(pVCpu, GCPtrPage);
1260	}
1261	else
1262	{
1263	/*
1264	* The page table address changed.
1265	*/
1266	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1267	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1268	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1269	ASMAtomicWriteSize(pPdeDst, 0);
1270	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1271	PGM_INVL_VCPU_TLBS(pVCpu);
1272	}
1273	}
1274	else
1275	{
1276	/*
1277	* 2/4MB - page.
1278	*/
1279	/* Before freeing the page, check if anything really changed. */
1280	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1281	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1282	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1283	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1284	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1285	# endif
1286	if ( pShwPage->GCPhys == GCPhys
1287	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1288	{
1289	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1290	/** @todo PAT */
1291	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1292	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1293	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1294	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1295	{
1296	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1298	# if defined(IN_RC)
1299	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1300	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1301	# endif
1302	return VINF_SUCCESS;
1303	}
1304	}
1305
1306	/*
1307	* Ok, the page table is present and it's been changed in the guest.
1308	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1309	* We could do this for some flushes in GC too, but we need an algorithm for
1310	* deciding which 4MB pages containing code likely to be executed very soon.
1311	*/
1312	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1313	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1314	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1315	ASMAtomicWriteSize(pPdeDst, 0);
1316	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1317	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1318	}
1319	}
1320	else
1321	{
1322	/*
1323	* Page directory is not present, mark shadow PDE not present.
1324	*/
1325	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1326	{
1327	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1328	ASMAtomicWriteSize(pPdeDst, 0);
1329	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1330	PGM_INVL_PG(pVCpu, GCPtrPage);
1331	}
1332	else
1333	{
1334	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1335	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1336	}
1337	}
1338	# if defined(IN_RC)
1339	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1340	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1341	# endif
1342	return rc;
1343
1344	#else /* guest real and protected mode */
1345	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1346	return VINF_SUCCESS;
1347	#endif
1348	}
1349
1350
1351	#ifdef PGMPOOL_WITH_USER_TRACKING
1352	/**
1353	* Update the tracking of shadowed pages.
1354	*
1355	* @param pVCpu The VMCPU handle.
1356	* @param pShwPage The shadow page.
1357	* @param HCPhys The physical page we is being dereferenced.
1358	*/
1359	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1360	{
1361	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1362	PVM pVM = pVCpu->CTX_SUFF(pVM);
1363
1364	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1365	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1366
1367	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1368	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1369	* 2. write protect all shadowed pages. I.e. implement caching.
1370	*/
1371	/*
1372	* Find the guest address.
1373	*/
1374	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1375	pRam;
1376	pRam = pRam->CTX_SUFF(pNext))
1377	{
1378	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1379	while (iPage-- > 0)
1380	{
1381	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1382	{
1383	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1384	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1385	pShwPage->cPresent--;
1386	pPool->cPresent--;
1387	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1388	return;
1389	}
1390	}
1391	}
1392
1393	for (;;)
1394	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1395	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1396	pShwPage->cPresent--;
1397	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1398	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1399	}
1400
1401
1402	/**
1403	* Update the tracking of shadowed pages.
1404	*
1405	* @param pVCpu The VMCPU handle.
1406	* @param pShwPage The shadow page.
1407	* @param u16 The top 16-bit of the pPage->HCPhys.
1408	* @param pPage Pointer to the guest page. this will be modified.
1409	* @param iPTDst The index into the shadow table.
1410	*/
1411	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1412	{
1413	PVM pVM = pVCpu->CTX_SUFF(pVM);
1414	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1415	/*
1416	* Just deal with the simple first time here.
1417	*/
1418	if (!u16)
1419	{
1420	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1421	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1422	}
1423	else
1424	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1425
1426	/* write back */
1427	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1428	PGM_PAGE_SET_TRACKING(pPage, u16);
1429
1430	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1431
1432	/* update statistics. */
1433	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1434	pShwPage->cPresent++;
1435	if (pShwPage->iFirstPresent > iPTDst)
1436	pShwPage->iFirstPresent = iPTDst;
1437	}
1438	#endif /* PGMPOOL_WITH_USER_TRACKING */
1439
1440
1441	/**
1442	* Creates a 4K shadow page for a guest page.
1443	*
1444	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1445	* physical address. The PdeSrc argument only the flags are used. No page structured
1446	* will be mapped in this function.
1447	*
1448	* @param pVCpu The VMCPU handle.
1449	* @param pPteDst Destination page table entry.
1450	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1451	* Can safely assume that only the flags are being used.
1452	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1453	* @param pShwPage Pointer to the shadow page.
1454	* @param iPTDst The index into the shadow table.
1455	*
1456	* @remark Not used for 2/4MB pages!
1457	*/
1458	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1459	{
1460	if (PteSrc.n.u1Present)
1461	{
1462	PVM pVM = pVCpu->CTX_SUFF(pVM);
1463
1464	/*
1465	* Find the ram range.
1466	*/
1467	PPGMPAGE pPage;
1468	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1469	if (RT_SUCCESS(rc))
1470	{
1471	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1472	/* Try make the page writable if necessary. */
1473	if ( PteSrc.n.u1Write
1474	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1475	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1476	{
1477	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1478	AssertRC(rc);
1479	}
1480	#endif
1481
1482	/** @todo investiage PWT, PCD and PAT. */
1483	/*
1484	* Make page table entry.
1485	*/
1486	SHWPTE PteDst;
1487	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1488	{
1489	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1490	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1491	{
1492	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1493	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1494	PteDst.n.u1Present = 1;
1495	PteDst.n.u1Execute = 1;
1496	PteDst.n.u1IgnorePAT = 1;
1497	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1498	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1499	#else
1500	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1501	\| PGM_PAGE_GET_HCPHYS(pPage);
1502	#endif
1503	}
1504	else
1505	{
1506	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1507	PteDst.u = 0;
1508	}
1509	/** @todo count these two kinds. */
1510	}
1511	else
1512	{
1513	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1514	/*
1515	* If the page or page directory entry is not marked accessed,
1516	* we mark the page not present.
1517	*/
1518	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1519	{
1520	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1521	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1522	PteDst.u = 0;
1523	}
1524	else
1525	/*
1526	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1527	* when the page is modified.
1528	*/
1529	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1530	{
1531	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1532	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1533	\| PGM_PAGE_GET_HCPHYS(pPage)
1534	\| PGM_PTFLAGS_TRACK_DIRTY;
1535	}
1536	else
1537	#endif
1538	{
1539	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1540	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1541	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1542	PteDst.n.u1Present = 1;
1543	PteDst.n.u1Write = 1;
1544	PteDst.n.u1Execute = 1;
1545	PteDst.n.u1IgnorePAT = 1;
1546	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1547	/* PteDst.n.u1Size = 0 */
1548	#else
1549	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1550	\| PGM_PAGE_GET_HCPHYS(pPage);
1551	#endif
1552	}
1553	}
1554
1555	/*
1556	* Make sure only allocated pages are mapped writable.
1557	*/
1558	if ( PteDst.n.u1Write
1559	&& PteDst.n.u1Present
1560	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1561	{
1562	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1563	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1564	}
1565
1566	#ifdef PGMPOOL_WITH_USER_TRACKING
1567	/*
1568	* Keep user track up to date.
1569	*/
1570	if (PteDst.n.u1Present)
1571	{
1572	if (!pPteDst->n.u1Present)
1573	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1574	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1575	{
1576	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1577	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1578	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1579	}
1580	}
1581	else if (pPteDst->n.u1Present)
1582	{
1583	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1584	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1585	}
1586	#endif /* PGMPOOL_WITH_USER_TRACKING */
1587
1588	/*
1589	* Update statistics and commit the entry.
1590	*/
1591	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1592	if (!PteSrc.n.u1Global)
1593	pShwPage->fSeenNonGlobal = true;
1594	#endif
1595	ASMAtomicWriteSize(pPteDst, PteDst.u);
1596	}
1597	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1598	/** @todo count these. */
1599	}
1600	else
1601	{
1602	/*
1603	* Page not-present.
1604	*/
1605	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1606	#ifdef PGMPOOL_WITH_USER_TRACKING
1607	/* Keep user track up to date. */
1608	if (pPteDst->n.u1Present)
1609	{
1610	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1611	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1612	}
1613	#endif /* PGMPOOL_WITH_USER_TRACKING */
1614	ASMAtomicWriteSize(pPteDst, 0);
1615	/** @todo count these. */
1616	}
1617	}
1618
1619
1620	/**
1621	* Syncs a guest OS page.
1622	*
1623	* There are no conflicts at this point, neither is there any need for
1624	* page table allocations.
1625	*
1626	* @returns VBox status code.
1627	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1628	* @param pVCpu The VMCPU handle.
1629	* @param PdeSrc Page directory entry of the guest.
1630	* @param GCPtrPage Guest context page address.
1631	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1632	* @param uErr Fault error (X86_TRAP_PF_*).
1633	*/
1634	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1635	{
1636	PVM pVM = pVCpu->CTX_SUFF(pVM);
1637	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1638	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1639
1640	Assert(PGMIsLockOwner(pVM));
1641
1642	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1643	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1644	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1645	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1646	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1647
1648	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1649	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1650	# endif
1651
1652	/*
1653	* Assert preconditions.
1654	*/
1655	Assert(PdeSrc.n.u1Present);
1656	Assert(cPages);
1657	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1658
1659	/*
1660	* Get the shadow PDE, find the shadow page table in the pool.
1661	*/
1662	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1663	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1664	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1665
1666	/* Fetch the pgm pool shadow descriptor. */
1667	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1668	Assert(pShwPde);
1669
1670	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1671	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1672	PPGMPOOLPAGE pShwPde = NULL;
1673	PX86PDPAE pPDDst;
1674
1675	/* Fetch the pgm pool shadow descriptor. */
1676	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1677	AssertRCSuccessReturn(rc, rc);
1678	Assert(pShwPde);
1679
1680	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1681	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1682
1683	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1684	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1685	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1686	PX86PDPAE pPDDst;
1687	PX86PDPT pPdptDst;
1688
1689	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1690	AssertRCSuccessReturn(rc, rc);
1691	Assert(pPDDst && pPdptDst);
1692	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1693	# endif
1694	SHWPDE PdeDst = *pPdeDst;
1695	if (!PdeDst.n.u1Present)
1696	{
1697	AssertMsg(pVM->cCPUs > 1, ("%Unexpected missing PDE p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1698	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1699	return VINF_SUCCESS; /* force the instruction to be executed again. */
1700	}
1701
1702	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1703
1704	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1705	/* Fetch the pgm pool shadow descriptor. */
1706	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1707	Assert(pShwPde);
1708	# endif
1709
1710	# if defined(IN_RC)
1711	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1712	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1713	# endif
1714
1715	/*
1716	* Check that the page is present and that the shadow PDE isn't out of sync.
1717	*/
1718	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1719	const bool fBigPage = PdeSrc.b.u1Size;
1720	# else
1721	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1722	# endif
1723	RTGCPHYS GCPhys;
1724	if (!fBigPage)
1725	{
1726	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1727	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1728	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1729	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1730	# endif
1731	}
1732	else
1733	{
1734	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1735	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1736	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1737	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1738	# endif
1739	}
1740	if ( pShwPage->GCPhys == GCPhys
1741	&& PdeSrc.n.u1Present
1742	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1743	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1744	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1745	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1746	# endif
1747	)
1748	{
1749	/*
1750	* Check that the PDE is marked accessed already.
1751	* Since we set the accessed bit before getting here on a #PF, this
1752	* check is only meant for dealing with non-#PF'ing paths.
1753	*/
1754	if (PdeSrc.n.u1Accessed)
1755	{
1756	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1757	if (!fBigPage)
1758	{
1759	/*
1760	* 4KB Page - Map the guest page table.
1761	*/
1762	PGSTPT pPTSrc;
1763	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1764	if (RT_SUCCESS(rc))
1765	{
1766	# ifdef PGM_SYNC_N_PAGES
1767	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1768	if ( cPages > 1
1769	&& !(uErr & X86_TRAP_PF_P)
1770	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1771	{
1772	/*
1773	* This code path is currently only taken when the caller is PGMTrap0eHandler
1774	* for non-present pages!
1775	*
1776	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1777	* deal with locality.
1778	*/
1779	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1780	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1781	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1782	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1783	# else
1784	const unsigned offPTSrc = 0;
1785	# endif
1786	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1787	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1788	iPTDst = 0;
1789	else
1790	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1791	for (; iPTDst < iPTDstEnd; iPTDst++)
1792	{
1793	if (!pPTDst->a[iPTDst].n.u1Present)
1794	{
1795	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1796	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1797	NOREF(GCPtrCurPage);
1798	#ifndef IN_RING0
1799	/*
1800	* Assuming kernel code will be marked as supervisor - and not as user level
1801	* and executed using a conforming code selector - And marked as readonly.
1802	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1803	*/
1804	PPGMPAGE pPage;
1805	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1806	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1807	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1808	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1809	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1810	)
1811	#endif /* else: CSAM not active */
1812	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1813	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1814	GCPtrCurPage, PteSrc.n.u1Present,
1815	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1816	PteSrc.n.u1User & PdeSrc.n.u1User,
1817	(uint64_t)PteSrc.u,
1818	(uint64_t)pPTDst->a[iPTDst].u,
1819	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1820	}
1821	}
1822	}
1823	else
1824	# endif /* PGM_SYNC_N_PAGES */
1825	{
1826	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1827	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1828	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1829	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1830	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1831	GCPtrPage, PteSrc.n.u1Present,
1832	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1833	PteSrc.n.u1User & PdeSrc.n.u1User,
1834	(uint64_t)PteSrc.u,
1835	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1836	}
1837	}
1838	else /* MMIO or invalid page: emulated in #PF handler. */
1839	{
1840	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1841	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1842	}
1843	}
1844	else
1845	{
1846	/*
1847	* 4/2MB page - lazy syncing shadow 4K pages.
1848	* (There are many causes of getting here, it's no longer only CSAM.)
1849	*/
1850	/* Calculate the GC physical address of this 4KB shadow page. */
1851	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1852	/* Find ram range. */
1853	PPGMPAGE pPage;
1854	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1855	if (RT_SUCCESS(rc))
1856	{
1857	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1858	/* Try make the page writable if necessary. */
1859	if ( PdeSrc.n.u1Write
1860	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1861	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1862	{
1863	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1864	AssertRC(rc);
1865	}
1866	# endif
1867
1868	/*
1869	* Make shadow PTE entry.
1870	*/
1871	SHWPTE PteDst;
1872	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1873	\| PGM_PAGE_GET_HCPHYS(pPage);
1874	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1875	{
1876	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1877	PteDst.n.u1Write = 0;
1878	else
1879	PteDst.u = 0;
1880	}
1881	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1882	# ifdef PGMPOOL_WITH_USER_TRACKING
1883	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1884	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1885	# endif
1886	/* Make sure only allocated pages are mapped writable. */
1887	if ( PteDst.n.u1Write
1888	&& PteDst.n.u1Present
1889	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1890	{
1891	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1892	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1893	}
1894
1895	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1896
1897	/*
1898	* If the page is not flagged as dirty and is writable, then make it read-only
1899	* at PD level, so we can set the dirty bit when the page is modified.
1900	*
1901	* ASSUMES that page access handlers are implemented on page table entry level.
1902	* Thus we will first catch the dirty access and set PDE.D and restart. If
1903	* there is an access handler, we'll trap again and let it work on the problem.
1904	*/
1905	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1906	* As for invlpg, it simply frees the whole shadow PT.
1907	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1908	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1909	{
1910	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1911	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1912	PdeDst.n.u1Write = 0;
1913	}
1914	else
1915	{
1916	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1917	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1918	}
1919	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1920	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1921	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1922	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1923	}
1924	else
1925	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1926	}
1927	# if defined(IN_RC)
1928	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1929	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1930	# endif
1931	return VINF_SUCCESS;
1932	}
1933	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1934	}
1935	else
1936	{
1937	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1938	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1939	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1940	}
1941
1942	/*
1943	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1944	* Yea, I'm lazy.
1945	*/
1946	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1947	ASMAtomicWriteSize(pPdeDst, 0);
1948
1949	# if defined(IN_RC)
1950	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1951	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1952	# endif
1953	PGM_INVL_VCPU_TLBS(pVCpu);
1954	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1955
1956	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1957	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1958	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1959	&& !defined(IN_RC)
1960
1961	# ifdef PGM_SYNC_N_PAGES
1962	/*
1963	* Get the shadow PDE, find the shadow page table in the pool.
1964	*/
1965	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1966	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1967
1968	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1969	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1970
1971	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1972	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1973	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1974	PX86PDPAE pPDDst;
1975	X86PDEPAE PdeDst;
1976	PX86PDPT pPdptDst;
1977
1978	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1979	AssertRCSuccessReturn(rc, rc);
1980	Assert(pPDDst && pPdptDst);
1981	PdeDst = pPDDst->a[iPDDst];
1982	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1983	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1984	PEPTPD pPDDst;
1985	EPTPDE PdeDst;
1986
1987	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1988	if (rc != VINF_SUCCESS)
1989	{
1990	AssertRC(rc);
1991	return rc;
1992	}
1993	Assert(pPDDst);
1994	PdeDst = pPDDst->a[iPDDst];
1995	# endif
1996	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
1997	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1998	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1999
2000	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2001	if ( cPages > 1
2002	&& !(uErr & X86_TRAP_PF_P)
2003	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2004	{
2005	/*
2006	* This code path is currently only taken when the caller is PGMTrap0eHandler
2007	* for non-present pages!
2008	*
2009	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2010	* deal with locality.
2011	*/
2012	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2013	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2014	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2015	iPTDst = 0;
2016	else
2017	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2018	for (; iPTDst < iPTDstEnd; iPTDst++)
2019	{
2020	if (!pPTDst->a[iPTDst].n.u1Present)
2021	{
2022	GSTPTE PteSrc;
2023
2024	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2025
2026	/* Fake the page table entry */
2027	PteSrc.u = GCPtrCurPage;
2028	PteSrc.n.u1Present = 1;
2029	PteSrc.n.u1Dirty = 1;
2030	PteSrc.n.u1Accessed = 1;
2031	PteSrc.n.u1Write = 1;
2032	PteSrc.n.u1User = 1;
2033
2034	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2035
2036	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2037	GCPtrCurPage, PteSrc.n.u1Present,
2038	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2039	PteSrc.n.u1User & PdeSrc.n.u1User,
2040	(uint64_t)PteSrc.u,
2041	(uint64_t)pPTDst->a[iPTDst].u,
2042	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2043
2044	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2045	break;
2046	}
2047	else
2048	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2049	}
2050	}
2051	else
2052	# endif /* PGM_SYNC_N_PAGES */
2053	{
2054	GSTPTE PteSrc;
2055	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2056	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2057
2058	/* Fake the page table entry */
2059	PteSrc.u = GCPtrCurPage;
2060	PteSrc.n.u1Present = 1;
2061	PteSrc.n.u1Dirty = 1;
2062	PteSrc.n.u1Accessed = 1;
2063	PteSrc.n.u1Write = 1;
2064	PteSrc.n.u1User = 1;
2065	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2066
2067	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2068	GCPtrPage, PteSrc.n.u1Present,
2069	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2070	PteSrc.n.u1User & PdeSrc.n.u1User,
2071	(uint64_t)PteSrc.u,
2072	(uint64_t)pPTDst->a[iPTDst].u,
2073	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2074	}
2075	return VINF_SUCCESS;
2076
2077	#else
2078	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2079	return VERR_INTERNAL_ERROR;
2080	#endif
2081	}
2082
2083
2084	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2085	/**
2086	* Investigate page fault and handle write protection page faults caused by
2087	* dirty bit tracking.
2088	*
2089	* @returns VBox status code.
2090	* @param pVCpu The VMCPU handle.
2091	* @param uErr Page fault error code.
2092	* @param pPdeDst Shadow page directory entry.
2093	* @param pPdeSrc Guest page directory entry.
2094	* @param GCPtrPage Guest context page address.
2095	*/
2096	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2097	{
2098	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2099	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2100	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2101	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2102	bool fBigPagesSupported = true;
2103	# else
2104	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2105	# endif
2106	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2107	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2108	# endif
2109	unsigned uPageFaultLevel;
2110	int rc;
2111	PVM pVM = pVCpu->CTX_SUFF(pVM);
2112	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2113
2114	Assert(PGMIsLockOwner(pVM));
2115
2116	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2117	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2118
2119	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2120	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2121
2122	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2123	PX86PML4E pPml4eSrc;
2124	PX86PDPE pPdpeSrc;
2125
2126	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2127	Assert(pPml4eSrc);
2128
2129	/*
2130	* Real page fault? (PML4E level)
2131	*/
2132	if ( (uErr & X86_TRAP_PF_RSVD)
2133	\|\| !pPml4eSrc->n.u1Present
2134	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2135	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2136	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2137	)
2138	{
2139	uPageFaultLevel = 0;
2140	goto l_UpperLevelPageFault;
2141	}
2142	Assert(pPdpeSrc);
2143
2144	# else /* PAE */
2145	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2146	# endif /* PAE */
2147
2148	/*
2149	* Real page fault? (PDPE level)
2150	*/
2151	if ( (uErr & X86_TRAP_PF_RSVD)
2152	\|\| !pPdpeSrc->n.u1Present
2153	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2154	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2155	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2156	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2157	# endif
2158	)
2159	{
2160	uPageFaultLevel = 1;
2161	goto l_UpperLevelPageFault;
2162	}
2163	# endif
2164
2165	/*
2166	* Real page fault? (PDE level)
2167	*/
2168	if ( (uErr & X86_TRAP_PF_RSVD)
2169	\|\| !pPdeSrc->n.u1Present
2170	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2171	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2172	# endif
2173	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2174	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2175	{
2176	uPageFaultLevel = 2;
2177	goto l_UpperLevelPageFault;
2178	}
2179
2180	/*
2181	* First check the easy case where the page directory has been marked read-only to track
2182	* the dirty bit of an emulated BIG page
2183	*/
2184	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2185	{
2186	/* Mark guest page directory as accessed */
2187	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2188	pPml4eSrc->n.u1Accessed = 1;
2189	pPdpeSrc->lm.u1Accessed = 1;
2190	# endif
2191	pPdeSrc->b.u1Accessed = 1;
2192
2193	/*
2194	* Only write protection page faults are relevant here.
2195	*/
2196	if (fWriteFault)
2197	{
2198	/* Mark guest page directory as dirty (BIG page only). */
2199	pPdeSrc->b.u1Dirty = 1;
2200
2201	if (pPdeDst->n.u1Present)
2202	{
2203	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2204	{
2205	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2206	Assert(pPdeSrc->b.u1Write);
2207
2208	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2209	* fault again and take this path to only invalidate the entry.
2210	*/
2211	pPdeDst->n.u1Write = 1;
2212	pPdeDst->n.u1Accessed = 1;
2213	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2214	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2215	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2216	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2217	}
2218	# ifdef IN_RING0
2219	else
2220	/* Check for stale TLB entry; only applies to the SMP guest case. */
2221	if ( pVM->cCPUs > 1
2222	&& pPdeDst->n.u1Write
2223	&& pPdeDst->n.u1Accessed)
2224	{
2225	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2226	if (pShwPage)
2227	{
2228	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2229	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2230	if ( pPteDst->n.u1Present
2231	&& pPteDst->n.u1Write)
2232	{
2233	/* Stale TLB entry. */
2234	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2235	PGM_INVL_PG(pVCpu, GCPtrPage);
2236
2237	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2238	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2239	}
2240	}
2241	}
2242	# endif /* IN_RING0 */
2243	}
2244	}
2245	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2246	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2247	}
2248	/* else: 4KB page table */
2249
2250	/*
2251	* Map the guest page table.
2252	*/
2253	PGSTPT pPTSrc;
2254	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2255	if (RT_SUCCESS(rc))
2256	{
2257	/*
2258	* Real page fault?
2259	*/
2260	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2261	const GSTPTE PteSrc = *pPteSrc;
2262	if ( !PteSrc.n.u1Present
2263	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2264	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2265	# endif
2266	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2267	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2268	)
2269	{
2270	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2271	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2272	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2273
2274	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2275	* See the 2nd case above as well.
2276	*/
2277	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2278	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2279
2280	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2281	return VINF_EM_RAW_GUEST_TRAP;
2282	}
2283	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2284
2285	/*
2286	* Set the accessed bits in the page directory and the page table.
2287	*/
2288	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2289	pPml4eSrc->n.u1Accessed = 1;
2290	pPdpeSrc->lm.u1Accessed = 1;
2291	# endif
2292	pPdeSrc->n.u1Accessed = 1;
2293	pPteSrc->n.u1Accessed = 1;
2294
2295	/*
2296	* Only write protection page faults are relevant here.
2297	*/
2298	if (fWriteFault)
2299	{
2300	/* Write access, so mark guest entry as dirty. */
2301	# ifdef VBOX_WITH_STATISTICS
2302	if (!pPteSrc->n.u1Dirty)
2303	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2304	else
2305	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2306	# endif
2307
2308	pPteSrc->n.u1Dirty = 1;
2309
2310	if (pPdeDst->n.u1Present)
2311	{
2312	#ifndef IN_RING0
2313	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2314	* Our individual shadow handlers will provide more information and force a fatal exit.
2315	*/
2316	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2317	{
2318	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2319	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2320	return VINF_SUCCESS;
2321	}
2322	#endif
2323	/*
2324	* Map shadow page table.
2325	*/
2326	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2327	if (pShwPage)
2328	{
2329	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2330	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2331	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2332	{
2333	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2334	{
2335	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2336	# ifdef VBOX_STRICT
2337	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2338	if (pPage)
2339	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2340	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2341	# endif
2342	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2343
2344	Assert(pPteSrc->n.u1Write);
2345
2346	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2347	* fault again and take this path to only invalidate the entry.
2348	*/
2349	pPteDst->n.u1Write = 1;
2350	pPteDst->n.u1Dirty = 1;
2351	pPteDst->n.u1Accessed = 1;
2352	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2353	PGM_INVL_PG(pVCpu, GCPtrPage);
2354
2355	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2356	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2357	}
2358	# ifdef IN_RING0
2359	else
2360	/* Check for stale TLB entry; only applies to the SMP guest case. */
2361	if ( pVM->cCPUs > 1
2362	&& pPteDst->n.u1Write == 1
2363	&& pPteDst->n.u1Accessed == 1)
2364	{
2365	/* Stale TLB entry. */
2366	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2367	PGM_INVL_PG(pVCpu, GCPtrPage);
2368
2369	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2370	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2371	}
2372	# endif
2373	}
2374	}
2375	else
2376	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2377	}
2378	}
2379	/** @todo Optimize accessed bit emulation? */
2380	# ifdef VBOX_STRICT
2381	/*
2382	* Sanity check.
2383	*/
2384	else if ( !pPteSrc->n.u1Dirty
2385	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2386	&& pPdeDst->n.u1Present)
2387	{
2388	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2389	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2390	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2391	if ( pPteDst->n.u1Present
2392	&& pPteDst->n.u1Write)
2393	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2394	}
2395	# endif /* VBOX_STRICT */
2396	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2397	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2398	}
2399	AssertRC(rc);
2400	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2401	return rc;
2402
2403
2404	l_UpperLevelPageFault:
2405	/*
2406	* Pagefault detected while checking the PML4E, PDPE or PDE.
2407	* Single exit handler to get rid of duplicate code paths.
2408	*/
2409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2410	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2411	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2412
2413	if (
2414	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2415	pPml4eSrc->n.u1Present &&
2416	# endif
2417	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2418	pPdpeSrc->n.u1Present &&
2419	# endif
2420	pPdeSrc->n.u1Present)
2421	{
2422	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2423	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2424	{
2425	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2426	}
2427	else
2428	{
2429	/*
2430	* Map the guest page table.
2431	*/
2432	PGSTPT pPTSrc;
2433	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2434	if (RT_SUCCESS(rc))
2435	{
2436	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2437	const GSTPTE PteSrc = *pPteSrc;
2438	if (pPteSrc->n.u1Present)
2439	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2440	}
2441	AssertRC(rc);
2442	}
2443	}
2444	return VINF_EM_RAW_GUEST_TRAP;
2445	}
2446	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2447
2448
2449	/**
2450	* Sync a shadow page table.
2451	*
2452	* The shadow page table is not present. This includes the case where
2453	* there is a conflict with a mapping.
2454	*
2455	* @returns VBox status code.
2456	* @param pVCpu The VMCPU handle.
2457	* @param iPD Page directory index.
2458	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2459	* Assume this is a temporary mapping.
2460	* @param GCPtrPage GC Pointer of the page that caused the fault
2461	*/
2462	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2463	{
2464	PVM pVM = pVCpu->CTX_SUFF(pVM);
2465	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2466
2467	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2468	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2469	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2470
2471	Assert(PGMIsLocked(pVM));
2472
2473	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2474	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2475	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2476	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2477	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2478
2479	int rc = VINF_SUCCESS;
2480
2481	/*
2482	* Validate input a little bit.
2483	*/
2484	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2485	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2486	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2487	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2488
2489	/* Fetch the pgm pool shadow descriptor. */
2490	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2491	Assert(pShwPde);
2492
2493	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2494	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2495	PPGMPOOLPAGE pShwPde = NULL;
2496	PX86PDPAE pPDDst;
2497	PSHWPDE pPdeDst;
2498
2499	/* Fetch the pgm pool shadow descriptor. */
2500	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2501	AssertRCSuccessReturn(rc, rc);
2502	Assert(pShwPde);
2503
2504	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2505	pPdeDst = &pPDDst->a[iPDDst];
2506
2507	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2508	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2509	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2510	PX86PDPAE pPDDst;
2511	PX86PDPT pPdptDst;
2512	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2513	AssertRCSuccessReturn(rc, rc);
2514	Assert(pPDDst);
2515	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2516	# endif
2517	SHWPDE PdeDst = *pPdeDst;
2518
2519	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2520	/* Fetch the pgm pool shadow descriptor. */
2521	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2522	Assert(pShwPde);
2523	# endif
2524
2525	# ifndef PGM_WITHOUT_MAPPINGS
2526	/*
2527	* Check for conflicts.
2528	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2529	* HC: Simply resolve the conflict.
2530	*/
2531	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2532	{
2533	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2534	# ifndef IN_RING3
2535	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2536	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2537	return VERR_ADDRESS_CONFLICT;
2538	# else
2539	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2540	Assert(pMapping);
2541	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2542	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2543	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2544	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2545	# else
2546	AssertFailed(); /* can't happen for amd64 */
2547	# endif
2548	if (RT_FAILURE(rc))
2549	{
2550	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2551	return rc;
2552	}
2553	PdeDst = *pPdeDst;
2554	# endif
2555	}
2556	# else /* PGM_WITHOUT_MAPPINGS */
2557	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2558	# endif /* PGM_WITHOUT_MAPPINGS */
2559	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2560
2561	# if defined(IN_RC)
2562	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2563	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2564	# endif
2565
2566	/*
2567	* Sync page directory entry.
2568	*/
2569	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2570	if (PdeSrc.n.u1Present)
2571	{
2572	/*
2573	* Allocate & map the page table.
2574	*/
2575	PSHWPT pPTDst;
2576	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2577	const bool fPageTable = !PdeSrc.b.u1Size;
2578	# else
2579	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2580	# endif
2581	PPGMPOOLPAGE pShwPage;
2582	RTGCPHYS GCPhys;
2583	if (fPageTable)
2584	{
2585	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2586	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2587	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2588	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2589	# endif
2590	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2591	}
2592	else
2593	{
2594	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2595	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2596	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2597	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2598	# endif
2599	/* Modify the physical address to distinguish between different access types to prevent incorrect reuse of cached entries. */
2600	if (PdeSrc.n.u1Write)
2601	GCPhys \|= PGMPOOL_PHYS_ACCESS_RW;
2602	if (PdeSrc.n.u1User)
2603	GCPhys \|= PGMPOOL_PHYS_ACCESS_USER;
2604
2605	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, pShwPde->idx, iPDDst, &pShwPage);
2606	}
2607	if (rc == VINF_SUCCESS)
2608	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2609	else if (rc == VINF_PGM_CACHED_PAGE)
2610	{
2611	/*
2612	* The PT was cached, just hook it up.
2613	*/
2614	if (fPageTable)
2615	PdeDst.u = pShwPage->Core.Key
2616	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2617	else
2618	{
2619	PdeDst.u = pShwPage->Core.Key
2620	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2621	/* (see explanation and assumptions further down.) */
2622	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2623	{
2624	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2625	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2626	PdeDst.b.u1Write = 0;
2627	}
2628	}
2629	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2630	# if defined(IN_RC)
2631	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2632	# endif
2633	return VINF_SUCCESS;
2634	}
2635	else if (rc == VERR_PGM_POOL_FLUSHED)
2636	{
2637	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2638	# if defined(IN_RC)
2639	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2640	# endif
2641	return VINF_PGM_SYNC_CR3;
2642	}
2643	else
2644	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2645	PdeDst.u &= X86_PDE_AVL_MASK;
2646	PdeDst.u \|= pShwPage->Core.Key;
2647
2648	/*
2649	* Page directory has been accessed (this is a fault situation, remember).
2650	*/
2651	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2652	if (fPageTable)
2653	{
2654	/*
2655	* Page table - 4KB.
2656	*
2657	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2658	*/
2659	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2660	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2661	PGSTPT pPTSrc;
2662	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2663	if (RT_SUCCESS(rc))
2664	{
2665	/*
2666	* Start by syncing the page directory entry so CSAM's TLB trick works.
2667	*/
2668	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2669	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2670	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2671	# if defined(IN_RC)
2672	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2673	# endif
2674
2675	/*
2676	* Directory/page user or supervisor privilege: (same goes for read/write)
2677	*
2678	* Directory Page Combined
2679	* U/S U/S U/S
2680	* 0 0 0
2681	* 0 1 0
2682	* 1 0 0
2683	* 1 1 1
2684	*
2685	* Simple AND operation. Table listed for completeness.
2686	*
2687	*/
2688	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2689	# ifdef PGM_SYNC_N_PAGES
2690	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2691	unsigned iPTDst = iPTBase;
2692	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2693	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2694	iPTDst = 0;
2695	else
2696	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2697	# else /* !PGM_SYNC_N_PAGES */
2698	unsigned iPTDst = 0;
2699	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2700	# endif /* !PGM_SYNC_N_PAGES */
2701	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2702	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2703	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2704	# else
2705	const unsigned offPTSrc = 0;
2706	# endif
2707	for (; iPTDst < iPTDstEnd; iPTDst++)
2708	{
2709	const unsigned iPTSrc = iPTDst + offPTSrc;
2710	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2711
2712	if (PteSrc.n.u1Present) /* we've already cleared it above */
2713	{
2714	# ifndef IN_RING0
2715	/*
2716	* Assuming kernel code will be marked as supervisor - and not as user level
2717	* and executed using a conforming code selector - And marked as readonly.
2718	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2719	*/
2720	PPGMPAGE pPage;
2721	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2722	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2723	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2724	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2725	)
2726	# endif
2727	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2728	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2729	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2730	PteSrc.n.u1Present,
2731	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2732	PteSrc.n.u1User & PdeSrc.n.u1User,
2733	(uint64_t)PteSrc.u,
2734	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2735	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2736	}
2737	} /* for PTEs */
2738	}
2739	}
2740	else
2741	{
2742	/*
2743	* Big page - 2/4MB.
2744	*
2745	* We'll walk the ram range list in parallel and optimize lookups.
2746	* We will only sync on shadow page table at a time.
2747	*/
2748	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2749
2750	/**
2751	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2752	*/
2753
2754	/*
2755	* Start by syncing the page directory entry.
2756	*/
2757	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2758	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2759
2760	/*
2761	* If the page is not flagged as dirty and is writable, then make it read-only
2762	* at PD level, so we can set the dirty bit when the page is modified.
2763	*
2764	* ASSUMES that page access handlers are implemented on page table entry level.
2765	* Thus we will first catch the dirty access and set PDE.D and restart. If
2766	* there is an access handler, we'll trap again and let it work on the problem.
2767	*/
2768	/** @todo move the above stuff to a section in the PGM documentation. */
2769	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2770	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2771	{
2772	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2773	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2774	PdeDst.b.u1Write = 0;
2775	}
2776	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2777	# if defined(IN_RC)
2778	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2779	# endif
2780
2781	/*
2782	* Fill the shadow page table.
2783	*/
2784	/* Get address and flags from the source PDE. */
2785	SHWPTE PteDstBase;
2786	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2787
2788	/* Loop thru the entries in the shadow PT. */
2789	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2790	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2791	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2792	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2793	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2794	unsigned iPTDst = 0;
2795	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2796	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2797	{
2798	/* Advance ram range list. */
2799	while (pRam && GCPhys > pRam->GCPhysLast)
2800	pRam = pRam->CTX_SUFF(pNext);
2801	if (pRam && GCPhys >= pRam->GCPhys)
2802	{
2803	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2804	do
2805	{
2806	/* Make shadow PTE. */
2807	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2808	SHWPTE PteDst;
2809
2810	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2811	/* Try make the page writable if necessary. */
2812	if ( PteDstBase.n.u1Write
2813	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2814	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2815	{
2816	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2817	AssertRCReturn(rc, rc);
2818	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2819	break;
2820	}
2821	# endif
2822
2823	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2824	{
2825	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2826	{
2827	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2828	PteDst.n.u1Write = 0;
2829	}
2830	else
2831	PteDst.u = 0;
2832	}
2833	# ifndef IN_RING0
2834	/*
2835	* Assuming kernel code will be marked as supervisor and not as user level and executed
2836	* using a conforming code selector. Don't check for readonly, as that implies the whole
2837	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2838	*/
2839	else if ( !PdeSrc.n.u1User
2840	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2841	PteDst.u = 0;
2842	# endif
2843	else
2844	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2845
2846	/* Only map writable pages writable. */
2847	if ( PteDst.n.u1Write
2848	&& PteDst.n.u1Present
2849	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2850	{
2851	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2852	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2853	}
2854
2855	# ifdef PGMPOOL_WITH_USER_TRACKING
2856	if (PteDst.n.u1Present)
2857	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2858	# endif
2859	/* commit it */
2860	pPTDst->a[iPTDst] = PteDst;
2861	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2862	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2863	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2864
2865	/* advance */
2866	GCPhys += PAGE_SIZE;
2867	iHCPage++;
2868	iPTDst++;
2869	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2870	&& GCPhys <= pRam->GCPhysLast);
2871	}
2872	else if (pRam)
2873	{
2874	Log(("Invalid pages at %RGp\n", GCPhys));
2875	do
2876	{
2877	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2878	GCPhys += PAGE_SIZE;
2879	iPTDst++;
2880	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2881	&& GCPhys < pRam->GCPhys);
2882	}
2883	else
2884	{
2885	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2886	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2887	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2888	}
2889	} /* while more PTEs */
2890	} /* 4KB / 4MB */
2891	}
2892	else
2893	AssertRelease(!PdeDst.n.u1Present);
2894
2895	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2896	if (RT_FAILURE(rc))
2897	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2898	return rc;
2899
2900	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2901	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2902	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2903	&& !defined(IN_RC)
2904
2905	/*
2906	* Validate input a little bit.
2907	*/
2908	int rc = VINF_SUCCESS;
2909	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2910	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2911	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2912
2913	/* Fetch the pgm pool shadow descriptor. */
2914	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2915	Assert(pShwPde);
2916
2917	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2918	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2919	PPGMPOOLPAGE pShwPde;
2920	PX86PDPAE pPDDst;
2921	PSHWPDE pPdeDst;
2922
2923	/* Fetch the pgm pool shadow descriptor. */
2924	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2925	AssertRCSuccessReturn(rc, rc);
2926	Assert(pShwPde);
2927
2928	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2929	pPdeDst = &pPDDst->a[iPDDst];
2930
2931	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2932	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2933	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2934	PX86PDPAE pPDDst;
2935	PX86PDPT pPdptDst;
2936	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2937	AssertRCSuccessReturn(rc, rc);
2938	Assert(pPDDst);
2939	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2940
2941	/* Fetch the pgm pool shadow descriptor. */
2942	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2943	Assert(pShwPde);
2944
2945	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2946	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2947	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2948	PEPTPD pPDDst;
2949	PEPTPDPT pPdptDst;
2950
2951	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2952	if (rc != VINF_SUCCESS)
2953	{
2954	AssertRC(rc);
2955	return rc;
2956	}
2957	Assert(pPDDst);
2958	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2959
2960	/* Fetch the pgm pool shadow descriptor. */
2961	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2962	Assert(pShwPde);
2963	# endif
2964	SHWPDE PdeDst = *pPdeDst;
2965
2966	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2967	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2968
2969	GSTPDE PdeSrc;
2970	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2971	PdeSrc.n.u1Present = 1;
2972	PdeSrc.n.u1Write = 1;
2973	PdeSrc.n.u1Accessed = 1;
2974	PdeSrc.n.u1User = 1;
2975
2976	/*
2977	* Allocate & map the page table.
2978	*/
2979	PSHWPT pPTDst;
2980	PPGMPOOLPAGE pShwPage;
2981	RTGCPHYS GCPhys;
2982
2983	/* Virtual address = physical address */
2984	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2985	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2986
2987	if ( rc == VINF_SUCCESS
2988	\|\| rc == VINF_PGM_CACHED_PAGE)
2989	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2990	else
2991	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2992
2993	PdeDst.u &= X86_PDE_AVL_MASK;
2994	PdeDst.u \|= pShwPage->Core.Key;
2995	PdeDst.n.u1Present = 1;
2996	PdeDst.n.u1Write = 1;
2997	# if PGM_SHW_TYPE == PGM_TYPE_EPT
2998	PdeDst.n.u1Execute = 1;
2999	# else
3000	PdeDst.n.u1User = 1;
3001	PdeDst.n.u1Accessed = 1;
3002	# endif
3003	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3004
3005	pgmLock(pVM);
3006	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3007	pgmUnlock(pVM);
3008	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3009	return rc;
3010
3011	#else
3012	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3013	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3014	return VERR_INTERNAL_ERROR;
3015	#endif
3016	}
3017
3018
3019
3020	/**
3021	* Prefetch a page/set of pages.
3022	*
3023	* Typically used to sync commonly used pages before entering raw mode
3024	* after a CR3 reload.
3025	*
3026	* @returns VBox status code.
3027	* @param pVCpu The VMCPU handle.
3028	* @param GCPtrPage Page to invalidate.
3029	*/
3030	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3031	{
3032	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3033	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3034	/*
3035	* Check that all Guest levels thru the PDE are present, getting the
3036	* PD and PDE in the processes.
3037	*/
3038	int rc = VINF_SUCCESS;
3039	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3040	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3041	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3042	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3043	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3044	unsigned iPDSrc;
3045	X86PDPE PdpeSrc;
3046	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3047	if (!pPDSrc)
3048	return VINF_SUCCESS; /* not present */
3049	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3050	unsigned iPDSrc;
3051	PX86PML4E pPml4eSrc;
3052	X86PDPE PdpeSrc;
3053	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3054	if (!pPDSrc)
3055	return VINF_SUCCESS; /* not present */
3056	# endif
3057	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3058	# else
3059	PGSTPD pPDSrc = NULL;
3060	const unsigned iPDSrc = 0;
3061	GSTPDE PdeSrc;
3062
3063	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3064	PdeSrc.n.u1Present = 1;
3065	PdeSrc.n.u1Write = 1;
3066	PdeSrc.n.u1Accessed = 1;
3067	PdeSrc.n.u1User = 1;
3068	# endif
3069
3070	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3071	{
3072	PVM pVM = pVCpu->CTX_SUFF(pVM);
3073	pgmLock(pVM);
3074
3075	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3076	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3077	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3078	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3079	PX86PDPAE pPDDst;
3080	X86PDEPAE PdeDst;
3081	# if PGM_GST_TYPE != PGM_TYPE_PAE
3082	X86PDPE PdpeSrc;
3083
3084	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3085	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3086	# endif
3087	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3088	if (rc != VINF_SUCCESS)
3089	{
3090	pgmUnlock(pVM);
3091	AssertRC(rc);
3092	return rc;
3093	}
3094	Assert(pPDDst);
3095	PdeDst = pPDDst->a[iPDDst];
3096
3097	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3098	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3099	PX86PDPAE pPDDst;
3100	X86PDEPAE PdeDst;
3101
3102	# if PGM_GST_TYPE == PGM_TYPE_PROT
3103	/* AMD-V nested paging */
3104	X86PML4E Pml4eSrc;
3105	X86PDPE PdpeSrc;
3106	PX86PML4E pPml4eSrc = &Pml4eSrc;
3107
3108	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3109	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3110	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3111	# endif
3112
3113	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3114	if (rc != VINF_SUCCESS)
3115	{
3116	pgmUnlock(pVM);
3117	AssertRC(rc);
3118	return rc;
3119	}
3120	Assert(pPDDst);
3121	PdeDst = pPDDst->a[iPDDst];
3122	# endif
3123	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3124	{
3125	if (!PdeDst.n.u1Present)
3126	{
3127	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3128	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3129	}
3130	else
3131	{
3132	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3133	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3134	* makes no sense to prefetch more than one page.
3135	*/
3136	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3137	if (RT_SUCCESS(rc))
3138	rc = VINF_SUCCESS;
3139	}
3140	}
3141	pgmUnlock(pVM);
3142	}
3143	return rc;
3144
3145	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3146	return VINF_SUCCESS; /* ignore */
3147	#endif
3148	}
3149
3150
3151
3152
3153	/**
3154	* Syncs a page during a PGMVerifyAccess() call.
3155	*
3156	* @returns VBox status code (informational included).
3157	* @param pVCpu The VMCPU handle.
3158	* @param GCPtrPage The address of the page to sync.
3159	* @param fPage The effective guest page flags.
3160	* @param uErr The trap error code.
3161	*/
3162	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3163	{
3164	PVM pVM = pVCpu->CTX_SUFF(pVM);
3165
3166	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3167
3168	Assert(!HWACCMIsNestedPagingActive(pVM));
3169	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3170	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3171
3172	# ifndef IN_RING0
3173	if (!(fPage & X86_PTE_US))
3174	{
3175	/*
3176	* Mark this page as safe.
3177	*/
3178	/** @todo not correct for pages that contain both code and data!! */
3179	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3180	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3181	}
3182	# endif
3183
3184	/*
3185	* Get guest PD and index.
3186	*/
3187	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3188	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3189	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3190	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3191	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3192	unsigned iPDSrc = 0;
3193	X86PDPE PdpeSrc;
3194	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3195
3196	if (pPDSrc)
3197	{
3198	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3199	return VINF_EM_RAW_GUEST_TRAP;
3200	}
3201	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3202	unsigned iPDSrc;
3203	PX86PML4E pPml4eSrc;
3204	X86PDPE PdpeSrc;
3205	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3206	if (!pPDSrc)
3207	{
3208	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3209	return VINF_EM_RAW_GUEST_TRAP;
3210	}
3211	# endif
3212	# else
3213	PGSTPD pPDSrc = NULL;
3214	const unsigned iPDSrc = 0;
3215	# endif
3216	int rc = VINF_SUCCESS;
3217
3218	pgmLock(pVM);
3219
3220	/*
3221	* First check if the shadow pd is present.
3222	*/
3223	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3224	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3225	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3226	PX86PDEPAE pPdeDst;
3227	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3228	PX86PDPAE pPDDst;
3229	# if PGM_GST_TYPE != PGM_TYPE_PAE
3230	X86PDPE PdpeSrc;
3231
3232	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3233	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3234	# endif
3235	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3236	if (rc != VINF_SUCCESS)
3237	{
3238	pgmUnlock(pVM);
3239	AssertRC(rc);
3240	return rc;
3241	}
3242	Assert(pPDDst);
3243	pPdeDst = &pPDDst->a[iPDDst];
3244
3245	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3246	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3247	PX86PDPAE pPDDst;
3248	PX86PDEPAE pPdeDst;
3249
3250	# if PGM_GST_TYPE == PGM_TYPE_PROT
3251	/* AMD-V nested paging */
3252	X86PML4E Pml4eSrc;
3253	X86PDPE PdpeSrc;
3254	PX86PML4E pPml4eSrc = &Pml4eSrc;
3255
3256	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3257	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3258	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3259	# endif
3260
3261	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3262	if (rc != VINF_SUCCESS)
3263	{
3264	pgmUnlock(pVM);
3265	AssertRC(rc);
3266	return rc;
3267	}
3268	Assert(pPDDst);
3269	pPdeDst = &pPDDst->a[iPDDst];
3270	# endif
3271
3272	# if defined(IN_RC)
3273	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3274	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3275	# endif
3276
3277	if (!pPdeDst->n.u1Present)
3278	{
3279	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3280	if (rc != VINF_SUCCESS)
3281	{
3282	# if defined(IN_RC)
3283	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3284	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3285	# endif
3286	pgmUnlock(pVM);
3287	AssertRC(rc);
3288	return rc;
3289	}
3290	}
3291
3292	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3293	/* Check for dirty bit fault */
3294	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3295	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3296	Log(("PGMVerifyAccess: success (dirty)\n"));
3297	else
3298	{
3299	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3300	# else
3301	{
3302	GSTPDE PdeSrc;
3303	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3304	PdeSrc.n.u1Present = 1;
3305	PdeSrc.n.u1Write = 1;
3306	PdeSrc.n.u1Accessed = 1;
3307	PdeSrc.n.u1User = 1;
3308
3309	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3310	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3311	if (uErr & X86_TRAP_PF_US)
3312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3313	else /* supervisor */
3314	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3315
3316	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3317	if (RT_SUCCESS(rc))
3318	{
3319	/* Page was successfully synced */
3320	Log2(("PGMVerifyAccess: success (sync)\n"));
3321	rc = VINF_SUCCESS;
3322	}
3323	else
3324	{
3325	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3326	rc = VINF_EM_RAW_GUEST_TRAP;
3327	}
3328	}
3329	# if defined(IN_RC)
3330	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3331	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3332	# endif
3333	pgmUnlock(pVM);
3334	return rc;
3335
3336	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3337
3338	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3339	return VERR_INTERNAL_ERROR;
3340	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3341	}
3342
3343	#undef MY_STAM_COUNTER_INC
3344	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3345
3346
3347	/**
3348	* Syncs the paging hierarchy starting at CR3.
3349	*
3350	* @returns VBox status code, no specials.
3351	* @param pVCpu The VMCPU handle.
3352	* @param cr0 Guest context CR0 register
3353	* @param cr3 Guest context CR3 register
3354	* @param cr4 Guest context CR4 register
3355	* @param fGlobal Including global page directories or not
3356	*/
3357	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3358	{
3359	PVM pVM = pVCpu->CTX_SUFF(pVM);
3360
3361	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3362	fGlobal = true; /* Change this CR3 reload to be a global one. */
3363
3364	LogFlow(("SyncCR3 %d\n", fGlobal));
3365
3366	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3367	/*
3368	* Update page access handlers.
3369	* The virtual are always flushed, while the physical are only on demand.
3370	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3371	* have to look into that later because it will have a bad influence on the performance.
3372	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3373	* bird: Yes, but that won't work for aliases.
3374	*/
3375	/** @todo this MUST go away. See #1557. */
3376	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3377	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3378	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3379	#endif
3380
3381	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3382	/*
3383	* Nested / EPT - almost no work.
3384	*/
3385	/** @todo check if this is really necessary; the call does it as well... */
3386	HWACCMFlushTLB(pVCpu);
3387	return VINF_SUCCESS;
3388
3389	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3390	/*
3391	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3392	* out the shadow parts when the guest modifies its tables.
3393	*/
3394	return VINF_SUCCESS;
3395
3396	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3397
3398	# ifdef PGM_WITHOUT_MAPPINGS
3399	Assert(pVM->pgm.s.fMappingsFixed);
3400	return VINF_SUCCESS;
3401	# else
3402	/* Nothing to do when mappings are fixed. */
3403	if (pVM->pgm.s.fMappingsFixed)
3404	return VINF_SUCCESS;
3405
3406	int rc = PGMMapResolveConflicts(pVM);
3407	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3408	if (rc == VINF_PGM_SYNC_CR3)
3409	{
3410	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3411	return VINF_PGM_SYNC_CR3;
3412	}
3413	# endif
3414	return VINF_SUCCESS;
3415	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3416	}
3417
3418
3419
3420
3421	#ifdef VBOX_STRICT
3422	#ifdef IN_RC
3423	# undef AssertMsgFailed
3424	# define AssertMsgFailed Log
3425	#endif
3426	#ifdef IN_RING3
3427	# include <VBox/dbgf.h>
3428
3429	/**
3430	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3431	*
3432	* @returns VBox status code (VINF_SUCCESS).
3433	* @param cr3 The root of the hierarchy.
3434	* @param crr The cr4, only PAE and PSE is currently used.
3435	* @param fLongMode Set if long mode, false if not long mode.
3436	* @param cMaxDepth Number of levels to dump.
3437	* @param pHlp Pointer to the output functions.
3438	*/
3439	__BEGIN_DECLS
3440	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3441	__END_DECLS
3442
3443	#endif
3444
3445	/**
3446	* Checks that the shadow page table is in sync with the guest one.
3447	*
3448	* @returns The number of errors.
3449	* @param pVM The virtual machine.
3450	* @param pVCpu The VMCPU handle.
3451	* @param cr3 Guest context CR3 register
3452	* @param cr4 Guest context CR4 register
3453	* @param GCPtr Where to start. Defaults to 0.
3454	* @param cb How much to check. Defaults to everything.
3455	*/
3456	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3457	{
3458	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3459	return 0;
3460	#else
3461	unsigned cErrors = 0;
3462	PVM pVM = pVCpu->CTX_SUFF(pVM);
3463	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3464
3465	#if PGM_GST_TYPE == PGM_TYPE_PAE
3466	/** @todo currently broken; crashes below somewhere */
3467	AssertFailed();
3468	#endif
3469
3470	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3471	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3472	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3473
3474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3475	bool fBigPagesSupported = true;
3476	# else
3477	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3478	# endif
3479	PPGMCPU pPGM = &pVCpu->pgm.s;
3480	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3481	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3482	# ifndef IN_RING0
3483	RTHCPHYS HCPhys; /* general usage. */
3484	# endif
3485	int rc;
3486
3487	/*
3488	* Check that the Guest CR3 and all its mappings are correct.
3489	*/
3490	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3491	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3492	false);
3493	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3494	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3495	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3496	# else
3497	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3498	# endif
3499	AssertRCReturn(rc, 1);
3500	HCPhys = NIL_RTHCPHYS;
3501	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3502	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3503	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3504	pgmGstGet32bitPDPtr(pPGM);
3505	RTGCPHYS GCPhys;
3506	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3507	AssertRCReturn(rc, 1);
3508	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3509	# endif
3510	# endif /* !IN_RING0 */
3511
3512	/*
3513	* Get and check the Shadow CR3.
3514	*/
3515	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3516	unsigned cPDEs = X86_PG_ENTRIES;
3517	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3518	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3519	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3520	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3521	# else
3522	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3523	# endif
3524	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3525	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3526	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3527	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3528	# endif
3529	if (cb != ~(RTGCPTR)0)
3530	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3531
3532	/** @todo call the other two PGMAssert() functions. /
3533
3534	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3535	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3536
3537	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3538	{
3539	PPGMPOOLPAGE pShwPdpt = NULL;
3540	PX86PML4E pPml4eSrc;
3541	PX86PML4E pPml4eDst;
3542	RTGCPHYS GCPhysPdptSrc;
3543
3544	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3545	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3546
3547	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3548	if (!pPml4eDst->n.u1Present)
3549	{
3550	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3551	continue;
3552	}
3553
3554	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3555	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3556
3557	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3558	{
3559	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3560	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3561	cErrors++;
3562	continue;
3563	}
3564
3565	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3566	{
3567	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3568	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3569	cErrors++;
3570	continue;
3571	}
3572
3573	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3574	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3575	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3576	{
3577	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3578	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3579	cErrors++;
3580	continue;
3581	}
3582	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3583	{
3584	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3585
3586	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3587	/*
3588	* Check the PDPTEs too.
3589	*/
3590	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3591
3592	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3593	{
3594	unsigned iPDSrc;
3595	PPGMPOOLPAGE pShwPde = NULL;
3596	PX86PDPE pPdpeDst;
3597	RTGCPHYS GCPhysPdeSrc;
3598	# if PGM_GST_TYPE == PGM_TYPE_PAE
3599	X86PDPE PdpeSrc;
3600	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3601	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3602	# else
3603	PX86PML4E pPml4eSrc;
3604	X86PDPE PdpeSrc;
3605	PX86PDPT pPdptDst;
3606	PX86PDPAE pPDDst;
3607	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3608
3609	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3610	if (rc != VINF_SUCCESS)
3611	{
3612	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3613	GCPtr += 512 * _2M;
3614	continue; /* next PDPTE */
3615	}
3616	Assert(pPDDst);
3617	# endif
3618	Assert(iPDSrc == 0);
3619
3620	pPdpeDst = &pPdptDst->a[iPdpt];
3621
3622	if (!pPdpeDst->n.u1Present)
3623	{
3624	GCPtr += 512 * _2M;
3625	continue; /* next PDPTE */
3626	}
3627
3628	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3629	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3630
3631	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3632	{
3633	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3634	GCPtr += 512 * _2M;
3635	cErrors++;
3636	continue;
3637	}
3638
3639	if (GCPhysPdeSrc != pShwPde->GCPhys)
3640	{
3641	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3642	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3643	# else
3644	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3645	# endif
3646	GCPtr += 512 * _2M;
3647	cErrors++;
3648	continue;
3649	}
3650
3651	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3652	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3653	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3654	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3655	{
3656	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3657	GCPtr += 512 * _2M;
3658	cErrors++;
3659	continue;
3660	}
3661	# endif
3662
3663	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3664	{
3665	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3666	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3667	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3668	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3669	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3670	# endif
3671	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3672	/*
3673	* Iterate the shadow page directory.
3674	*/
3675	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3676	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3677
3678	for (;
3679	iPDDst < cPDEs;
3680	iPDDst++, GCPtr += cIncrement)
3681	{
3682	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3683	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3684	# else
3685	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3686	# endif
3687	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3688	{
3689	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3690	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3691	{
3692	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3693	cErrors++;
3694	continue;
3695	}
3696	}
3697	else if ( (PdeDst.u & X86_PDE_P)
3698	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3699	)
3700	{
3701	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3702	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3703	if (!pPoolPage)
3704	{
3705	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3706	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3707	cErrors++;
3708	continue;
3709	}
3710	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3711
3712	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3713	{
3714	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3715	GCPtr, (uint64_t)PdeDst.u));
3716	cErrors++;
3717	}
3718
3719	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3720	{
3721	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3722	GCPtr, (uint64_t)PdeDst.u));
3723	cErrors++;
3724	}
3725
3726	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3727	if (!PdeSrc.n.u1Present)
3728	{
3729	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3730	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3731	cErrors++;
3732	continue;
3733	}
3734
3735	if ( !PdeSrc.b.u1Size
3736	\|\| !fBigPagesSupported)
3737	{
3738	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3739	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3740	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3741	# endif
3742	}
3743	else
3744	{
3745	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3746	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3747	{
3748	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3749	GCPtr, (uint64_t)PdeSrc.u));
3750	cErrors++;
3751	continue;
3752	}
3753	# endif
3754	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3755	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3756	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3757	# endif
3758	}
3759
3760	if ( pPoolPage->enmKind
3761	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3762	{
3763	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3764	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3765	cErrors++;
3766	}
3767
3768	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3769	if (!pPhysPage)
3770	{
3771	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3772	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3773	cErrors++;
3774	continue;
3775	}
3776
3777	if (GCPhysGst != pPoolPage->GCPhys)
3778	{
3779	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3780	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3781	cErrors++;
3782	continue;
3783	}
3784
3785	if ( !PdeSrc.b.u1Size
3786	\|\| !fBigPagesSupported)
3787	{
3788	/*
3789	* Page Table.
3790	*/
3791	const GSTPT *pPTSrc;
3792	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3793	if (RT_FAILURE(rc))
3794	{
3795	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3796	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3797	cErrors++;
3798	continue;
3799	}
3800	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3801	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3802	{
3803	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3804	// (This problem will go away when/if we shadow multiple CR3s.)
3805	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3806	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3807	cErrors++;
3808	continue;
3809	}
3810	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3811	{
3812	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3813	GCPtr, (uint64_t)PdeDst.u));
3814	cErrors++;
3815	continue;
3816	}
3817
3818	/* iterate the page table. */
3819	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3820	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3821	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3822	# else
3823	const unsigned offPTSrc = 0;
3824	# endif
3825	for (unsigned iPT = 0, off = 0;
3826	iPT < RT_ELEMENTS(pPTDst->a);
3827	iPT++, off += PAGE_SIZE)
3828	{
3829	const SHWPTE PteDst = pPTDst->a[iPT];
3830
3831	/* skip not-present entries. */
3832	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3833	continue;
3834	Assert(PteDst.n.u1Present);
3835
3836	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3837	if (!PteSrc.n.u1Present)
3838	{
3839	# ifdef IN_RING3
3840	PGMAssertHandlerAndFlagsInSync(pVM);
3841	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3842	# endif
3843	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3844	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3845	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3846	cErrors++;
3847	continue;
3848	}
3849
3850	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3851	# if 1 /** @todo sync accessed bit properly... */
3852	fIgnoreFlags \|= X86_PTE_A;
3853	# endif
3854
3855	/* match the physical addresses */
3856	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3857	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3858
3859	# ifdef IN_RING3
3860	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3861	if (RT_FAILURE(rc))
3862	{
3863	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3864	{
3865	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3866	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3867	cErrors++;
3868	continue;
3869	}
3870	}
3871	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3872	{
3873	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3874	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3875	cErrors++;
3876	continue;
3877	}
3878	# endif
3879
3880	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3881	if (!pPhysPage)
3882	{
3883	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3884	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3885	{
3886	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3887	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3888	cErrors++;
3889	continue;
3890	}
3891	# endif
3892	if (PteDst.n.u1Write)
3893	{
3894	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3895	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3896	cErrors++;
3897	}
3898	fIgnoreFlags \|= X86_PTE_RW;
3899	}
3900	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3901	{
3902	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3903	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3904	cErrors++;
3905	continue;
3906	}
3907
3908	/* flags */
3909	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3910	{
3911	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3912	{
3913	if (PteDst.n.u1Write)
3914	{
3915	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3916	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3917	cErrors++;
3918	continue;
3919	}
3920	fIgnoreFlags \|= X86_PTE_RW;
3921	}
3922	else
3923	{
3924	if (PteDst.n.u1Present)
3925	{
3926	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3927	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3928	cErrors++;
3929	continue;
3930	}
3931	fIgnoreFlags \|= X86_PTE_P;
3932	}
3933	}
3934	else
3935	{
3936	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3937	{
3938	if (PteDst.n.u1Write)
3939	{
3940	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3941	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3942	cErrors++;
3943	continue;
3944	}
3945	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3946	{
3947	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3948	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3949	cErrors++;
3950	continue;
3951	}
3952	if (PteDst.n.u1Dirty)
3953	{
3954	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3955	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3956	cErrors++;
3957	}
3958	# if 0 /** @todo sync access bit properly... */
3959	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3960	{
3961	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3962	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3963	cErrors++;
3964	}
3965	fIgnoreFlags \|= X86_PTE_RW;
3966	# else
3967	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3968	# endif
3969	}
3970	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3971	{
3972	/* access bit emulation (not implemented). */
3973	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3974	{
3975	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3976	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3977	cErrors++;
3978	continue;
3979	}
3980	if (!PteDst.n.u1Accessed)
3981	{
3982	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3983	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3984	cErrors++;
3985	}
3986	fIgnoreFlags \|= X86_PTE_P;
3987	}
3988	# ifdef DEBUG_sandervl
3989	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3990	# endif
3991	}
3992
3993	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3994	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3995	)
3996	{
3997	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3998	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3999	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4000	cErrors++;
4001	continue;
4002	}
4003	} /* foreach PTE */
4004	}
4005	else
4006	{
4007	/*
4008	* Big Page.
4009	*/
4010	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4011	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4012	{
4013	if (PdeDst.n.u1Write)
4014	{
4015	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4016	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4017	cErrors++;
4018	continue;
4019	}
4020	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4021	{
4022	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4023	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4024	cErrors++;
4025	continue;
4026	}
4027	# if 0 /** @todo sync access bit properly... */
4028	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4029	{
4030	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4031	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4032	cErrors++;
4033	}
4034	fIgnoreFlags \|= X86_PTE_RW;
4035	# else
4036	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4037	# endif
4038	}
4039	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4040	{
4041	/* access bit emulation (not implemented). */
4042	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4043	{
4044	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4045	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4046	cErrors++;
4047	continue;
4048	}
4049	if (!PdeDst.n.u1Accessed)
4050	{
4051	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4052	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4053	cErrors++;
4054	}
4055	fIgnoreFlags \|= X86_PTE_P;
4056	}
4057
4058	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4059	{
4060	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4061	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4062	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4063	cErrors++;
4064	}
4065
4066	/* iterate the page table. */
4067	for (unsigned iPT = 0, off = 0;
4068	iPT < RT_ELEMENTS(pPTDst->a);
4069	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4070	{
4071	const SHWPTE PteDst = pPTDst->a[iPT];
4072
4073	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4074	{
4075	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4076	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4077	cErrors++;
4078	}
4079
4080	/* skip not-present entries. */
4081	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4082	continue;
4083
4084	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4085
4086	/* match the physical addresses */
4087	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4088
4089	# ifdef IN_RING3
4090	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4091	if (RT_FAILURE(rc))
4092	{
4093	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4094	{
4095	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4096	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4097	cErrors++;
4098	}
4099	}
4100	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4101	{
4102	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4103	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4104	cErrors++;
4105	continue;
4106	}
4107	# endif
4108	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4109	if (!pPhysPage)
4110	{
4111	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4112	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4113	{
4114	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4115	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4116	cErrors++;
4117	continue;
4118	}
4119	# endif
4120	if (PteDst.n.u1Write)
4121	{
4122	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4123	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4124	cErrors++;
4125	}
4126	fIgnoreFlags \|= X86_PTE_RW;
4127	}
4128	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4129	{
4130	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4131	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4132	cErrors++;
4133	continue;
4134	}
4135
4136	/* flags */
4137	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4138	{
4139	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4140	{
4141	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4142	{
4143	if (PteDst.n.u1Write)
4144	{
4145	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4146	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4147	cErrors++;
4148	continue;
4149	}
4150	fIgnoreFlags \|= X86_PTE_RW;
4151	}
4152	}
4153	else
4154	{
4155	if (PteDst.n.u1Present)
4156	{
4157	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4158	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4159	cErrors++;
4160	continue;
4161	}
4162	fIgnoreFlags \|= X86_PTE_P;
4163	}
4164	}
4165
4166	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4167	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4168	)
4169	{
4170	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4171	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4172	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4173	cErrors++;
4174	continue;
4175	}
4176	} /* for each PTE */
4177	}
4178	}
4179	/* not present */
4180
4181	} /* for each PDE */
4182
4183	} /* for each PDPTE */
4184
4185	} /* for each PML4E */
4186
4187	# ifdef DEBUG
4188	if (cErrors)
4189	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4190	# endif
4191
4192	#endif /* GST == 32BIT, PAE or AMD64 */
4193	return cErrors;
4194
4195	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4196	}
4197	#endif /* VBOX_STRICT */
4198
4199
4200	/**
4201	* Sets up the CR3 for shadow paging
4202	*
4203	* @returns Strict VBox status code.
4204	* @retval VINF_SUCCESS.
4205	*
4206	* @param pVCpu The VMCPU handle.
4207	* @param GCPhysCR3 The physical address in the CR3 register.
4208	*/
4209	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4210	{
4211	PVM pVM = pVCpu->CTX_SUFF(pVM);
4212
4213	/* Update guest paging info. */
4214	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4215	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4216	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4217
4218	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4219
4220	/*
4221	* Map the page CR3 points at.
4222	*/
4223	RTHCPTR HCPtrGuestCR3;
4224	RTHCPHYS HCPhysGuestCR3;
4225	pgmLock(pVM);
4226	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4227	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4228	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4229	/** @todo this needs some reworking wrt. locking. */
4230	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4231	HCPtrGuestCR3 = NIL_RTHCPTR;
4232	int rc = VINF_SUCCESS;
4233	# else
4234	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void **)&HCPtrGuestCR3);
4235	# endif
4236	pgmUnlock(pVM);
4237	if (RT_SUCCESS(rc))
4238	{
4239	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4240	if (RT_SUCCESS(rc))
4241	{
4242	# ifdef IN_RC
4243	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4244	# endif
4245	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4246	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4247	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4248	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4249	# endif
4250	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4251
4252	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4253	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4254	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4255	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4256	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4257	# endif
4258	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4259	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4260
4261	/*
4262	* Map the 4 PDs too.
4263	*/
4264	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4265	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4266	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4267	{
4268	if (pGuestPDPT->a[i].n.u1Present)
4269	{
4270	RTHCPTR HCPtr;
4271	RTHCPHYS HCPhys;
4272	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4273	pgmLock(pVM);
4274	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4275	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4276	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4277	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4278	HCPtr = NIL_RTHCPTR;
4279	int rc2 = VINF_SUCCESS;
4280	# else
4281	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4282	# endif
4283	pgmUnlock(pVM);
4284	if (RT_SUCCESS(rc2))
4285	{
4286	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4287	AssertRCReturn(rc, rc);
4288
4289	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4290	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4291	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4292	# endif
4293	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4294	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4295	# ifdef IN_RC
4296	PGM_INVL_PG(pVCpu, GCPtr);
4297	# endif
4298	continue;
4299	}
4300	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4301	}
4302
4303	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4304	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4305	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4306	# endif
4307	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4308	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4309	# ifdef IN_RC
4310	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4311	# endif
4312	}
4313
4314	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4315	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4316	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4317	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4318	# endif
4319	# endif
4320	}
4321	else
4322	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4323	}
4324	else
4325	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4326
4327	#else /* prot/real stub */
4328	int rc = VINF_SUCCESS;
4329	#endif
4330
4331	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4332	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4333	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4334	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4335	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4336	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4337
4338	Assert(!HWACCMIsNestedPagingActive(pVM));
4339
4340	/*
4341	* Update the shadow root page as well since that's not fixed.
4342	*/
4343	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4344	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4345	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4346	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4347	PPGMPOOLPAGE pNewShwPageCR3;
4348
4349	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4350	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3);
4351	AssertFatalRC(rc);
4352	rc = VINF_SUCCESS;
4353
4354	/* Mark the page as locked; disallow flushing. */
4355	pgmPoolLockPage(pPool, pNewShwPageCR3);
4356
4357	# ifdef IN_RC
4358	/* NOTE: We can't deal with jumps to ring 3 here as we're now in an inconsistent state! */
4359	bool fLog = VMMGCLogDisable(pVM);
4360	pgmLock(pVM);
4361	# endif
4362
4363	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4364	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4365	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4366	# ifdef IN_RING0
4367	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4368	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4369	# elif defined(IN_RC)
4370	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4371	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4372	# else
4373	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4374	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4375	# endif
4376
4377	# ifndef PGM_WITHOUT_MAPPINGS
4378	/*
4379	* Apply all hypervisor mappings to the new CR3.
4380	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4381	* make sure we check for conflicts in the new CR3 root.
4382	*/
4383	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4384	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4385	# endif
4386	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4387	AssertRCReturn(rc, rc);
4388	# endif
4389
4390	/* Set the current hypervisor CR3. */
4391	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4392	SELMShadowCR3Changed(pVM, pVCpu);
4393
4394	# ifdef IN_RC
4395	pgmUnlock(pVM);
4396	VMMGCLogRestore(pVM, fLog);
4397	# endif
4398
4399	/* Clean up the old CR3 root. */
4400	if (pOldShwPageCR3)
4401	{
4402	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4403	# ifndef PGM_WITHOUT_MAPPINGS
4404	/* Remove the hypervisor mappings from the shadow page table. */
4405	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4406	# endif
4407	/* Mark the page as unlocked; allow flushing again. */
4408	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4409
4410	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4411	}
4412
4413	# endif
4414
4415	return rc;
4416	}
4417
4418	/**
4419	* Unmaps the shadow CR3.
4420	*
4421	* @returns VBox status, no specials.
4422	* @param pVCpu The VMCPU handle.
4423	*/
4424	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4425	{
4426	LogFlow(("UnmapCR3\n"));
4427
4428	int rc = VINF_SUCCESS;
4429	PVM pVM = pVCpu->CTX_SUFF(pVM);
4430
4431	/*
4432	* Update guest paging info.
4433	*/
4434	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4435	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4436	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4437	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4438	# endif
4439	pVCpu->pgm.s.pGst32BitPdRC = 0;
4440
4441	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4442	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4443	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4444	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4445	# endif
4446	pVCpu->pgm.s.pGstPaePdptRC = 0;
4447	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4448	{
4449	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4450	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4451	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4452	# endif
4453	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4454	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4455	}
4456
4457	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4458	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4459	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4460	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4461	# endif
4462
4463	#else /* prot/real mode stub */
4464	/* nothing to do */
4465	#endif
4466
4467	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4468	/*
4469	* Update shadow paging info.
4470	*/
4471	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4472	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4473	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4474
4475	# if PGM_GST_TYPE != PGM_TYPE_REAL
4476	Assert(!HWACCMIsNestedPagingActive(pVM));
4477	# endif
4478
4479	# ifndef PGM_WITHOUT_MAPPINGS
4480	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4481	/* Remove the hypervisor mappings from the shadow page table. */
4482	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4483	# endif
4484
4485	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4486	{
4487	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4488
4489	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4490
4491	/* Mark the page as unlocked; allow flushing again. */
4492	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4493
4494	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4495	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4496	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4497	pVCpu->pgm.s.pShwPageCR3RC = 0;
4498	pVCpu->pgm.s.iShwUser = 0;
4499	pVCpu->pgm.s.iShwUserTable = 0;
4500	}
4501	# endif
4502	#endif /* !IN_RC*/
4503
4504	return rc;
4505	}
4506

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 20127

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