PGMAllBth.h@ 2128

Last change on this file since 2128 was 2120, checked in by vboxsync, 18 years ago
Real and protected mode without paging changes. Currently not yet used.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 149.2 KB

Line
1	/* $Id: PGMAllBth.h 2120 2007-04-17 08:40:33Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006 InnoTek Systemberatung GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License as published by the Free Software Foundation,
15	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16	* distribution. VirtualBox OSE is distributed in the hope that it will
17	* be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* If you received this file as part of a commercial VirtualBox
20	* distribution, then only the terms of your commercial VirtualBox
21	* license agreement apply instead of the previous paragraph.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/**
46	* #PF Handler for raw-mode guest execution.
47	*
48	* @returns VBox status code (appropriate for trap handling and GC return).
49	* @param pVM VM Handle.
50	* @param uErr The trap error code.
51	* @param pRegFrame Trap register frame.
52	* @param pvFault The fault address.
53	*/
54	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
55	{
56	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
57
58	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
59	# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
60	# endif
61
62	# if PGM_SHW_TYPE == PGM_TYPE_PAE
63	/*
64	* Hide the instruction fetch trap indicator for now.
65	*/
66	/** @todo NXE will change this and we must fix NXE in the switcher too! */
67	if (uErr & X86_TRAP_PF_ID)
68	{
69	uErr &= ~X86_TRAP_PF_ID;
70	TRPMSetErrorCode(pVM, uErr);
71	}
72	# endif
73
74	/*
75	* Get PDs.
76	*/
77	int rc;
78	# if PGM_WITH_PAGING(PGM_GST_TYPE)
79	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
80	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
81	# else
82	PVBOXPD pPDSrc = NULL;
83	const unsigned iPDSrc = 0;
84	# endif
85
86	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
87	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
88	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
89	# else /* PAE */
90	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
91	# endif
92
93	/* Determine current privilege level */
94	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
95
96	# if PGM_WITH_PAGING(PGM_GST_TYPE)
97	# ifdef PGM_SYNC_DIRTY_BIT
98	/*
99	* If we successfully correct the write protection fault due to dirty bit
100	* tracking, or this page fault is a genuine one, then return immediately.
101	*/
102	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
103	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
104	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
105	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
106	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
107	{
108	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
109	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
110	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
111	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
112	}
113	# endif
114
115	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
116	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
117
118	/*
119	* A common case is the not-present error caused by lazy page table syncing.
120	*
121	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
122	* so we can safely assume that the shadow PT is present when calling SyncPage later.
123	*
124	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
125	* of mapping conflict and defer to SyncCR3 in R3.
126	* (Again, we do NOT support access handlers for non-present guest pages.)
127	*
128	*/
129	# if PGM_WITH_PAGING(PGM_GST_TYPE)
130	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
131	# else
132	VBOXPDE PdeSrc;
133	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
134	PdeSrc.n.u1Present = 1;
135	PdeSrc.n.u1Write = 1;
136	PdeSrc.n.u1Accessed = 1;
137	# endif
138	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
139	&& !pPDDst->a[iPDDst].n.u1Present
140	&& PdeSrc.n.u1Present
141	)
142
143	{
144	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
145	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
146	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
147	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
148	if (VBOX_SUCCESS(rc))
149	{
150	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
151	return rc;
152	}
153	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
154	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
155	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
156	return VINF_PGM_SYNC_CR3;
157	}
158
159	# if PGM_WITH_PAGING(PGM_GST_TYPE)
160	/*
161	* Check if this address is within any of our mappings.
162	*
163	* This is very fast and it's gonna save us a bit of effort below and prevent
164	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
165	* (BTW, it's impossible to have physical access handlers in a mapping.)
166	*/
167	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
168	{
169	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
170	PPGMMAPPING pMapping = CTXSUFF(pVM->pgm.s.pMappings);
171	for ( ; pMapping; pMapping = CTXSUFF(pMapping->pNext))
172	{
173	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
174	break;
175	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
176	{
177	/*
178	* The first thing we check is if we've got an undetected conflict.
179	*/
180	if (!pVM->pgm.s.fMappingsFixed)
181	{
182	unsigned iPT = pMapping->cPTs;
183	while (iPT-- > 0)
184	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
185	{
186	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
187	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
188	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
189	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
190	return VINF_PGM_SYNC_CR3;
191	}
192	}
193
194	/*
195	* Check if the fault address is in a virtual page access handler range.
196	*/
197	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
198	if ( pCur
199	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
200	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
201	&& ( uErr & X86_TRAP_PF_RW
202	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
203	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** r=bird: <- this is probably wrong. */
204	{
205	# ifdef IN_GC
206	STAM_PROFILE_START(&pCur->Stat, h);
207	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
208	STAM_PROFILE_STOP(&pCur->Stat, h);
209	# else
210	AssertFailed();
211	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
212	# endif
213	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
214	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
215	return rc;
216	}
217
218	/*
219	* Check if the EIP is in a virtual page access handler range.
220	*/
221	if (cpl == 0)
222	{
223	RTGCPTR pvEIP;
224	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
225	if (VBOX_SUCCESS(rc))
226	{
227	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
228	if ( pCur
229	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
230	&& (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
231	{
232	# ifdef IN_GC
233	STAM_PROFILE_START(&pCur->Stat, h);
234	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
235	STAM_PROFILE_STOP(&pCur->Stat, h);
236	# else
237	AssertFailed();
238	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
239	# endif
240	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
241	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
242	return rc;
243	}
244	}
245	}
246
247	/*
248	* Pretend we're not here and let the guest handle the trap.
249	*/
250	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
251	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
252	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
253	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
254	return VINF_EM_RAW_GUEST_TRAP;
255	}
256	}
257	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
258	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
259	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
260
261	/*
262	* Check if this fault address is flagged for special treatment,
263	* which means we'll have to figure out the physical address and
264	* check flags associated with it.
265	*
266	* ASSUME that we can limit any special access handling to pages
267	* in page tables which the guest believes to be present.
268	*/
269	if (PdeSrc.n.u1Present)
270	{
271	RTGCPHYS GCPhys = ~0U;
272
273	# if PGM_WITH_PAGING(PGM_GST_TYPE)
274	uint32_t cr4 = CPUMGetGuestCR4(pVM);
275	if ( PdeSrc.b.u1Size
276	&& (cr4 & X86_CR4_PSE))
277	GCPhys = (PdeSrc.u & X86_PDE4M_PG_MASK)
278	\| ((RTGCPHYS)pvFault & (PAGE_OFFSET_MASK_BIG ^ PAGE_OFFSET_MASK));
279	else
280	{
281	PVBOXPT pPTSrc;
282	# ifdef IN_GC
283	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & X86_PDE_PG_MASK, (void **)&pPTSrc);
284	# else
285	pPTSrc = (PVBOXPT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & X86_PDE_PG_MASK, sizeof(*pPTSrc));
286	if (pPTSrc == 0)
287	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
288	# endif
289	if (VBOX_SUCCESS(rc))
290	{
291	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & PTE_MASK;
292	if (pPTSrc->a[iPTESrc].n.u1Present)
293	GCPhys = pPTSrc->a[iPTESrc].u & X86_PTE_PG_MASK;
294	}
295	}
296	# else
297	/* No paging so the fault address is the physical address */
298	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
299	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
300
301	/*
302	* If we have a GC address we'll check if it has any flags set.
303	*/
304	if (GCPhys != ~0U)
305	{
306	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
307
308	RTHCPHYS HCPhys;
309	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPhys);
310	if (VBOX_SUCCESS(rc))
311	{
312	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_HANDLER))
313	{
314	if (HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER)
315	{
316	/*
317	* Physical page access handler.
318	*/
319	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
320	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
321	if (pCur)
322	{
323	# ifdef PGM_SYNC_N_PAGES
324	/*
325	* If the region is write protected and we got a page not present fault, then sync
326	* the pages. If the fault was caused by a read, then restart the instruction.
327	* In case of write access continue to the GC write handler.
328	*
329	* ASSUMES that there is only one handler per page or that they have similar write properties.
330	*/
331	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
332	&& !(uErr & X86_TRAP_PF_P))
333	{
334	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
335	if ( VBOX_FAILURE(rc)
336	\|\| !(uErr & X86_TRAP_PF_RW)
337	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
338	{
339	AssertRC(rc);
340	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
341	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
342	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
343	return rc;
344	}
345	}
346	# endif
347
348	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
349	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
350	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
351
352	#ifdef IN_GC
353	Assert(CTXSUFF(pCur->pfnHandler));
354	STAM_PROFILE_START(&pCur->Stat, h);
355	rc = pCur->CTXSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXSUFF(pCur->pvUser));
356	STAM_PROFILE_STOP(&pCur->Stat, h);
357	#elif IN_RING0
358	if (CTXALLSUFF(pCur->pfnHandler))
359	{
360	STAM_PROFILE_START(&pCur->Stat, h);
361	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
362	STAM_PROFILE_STOP(&pCur->Stat, h);
363	}
364	else
365	rc = VINF_EM_RAW_EMULATE_INSTR;
366	#else
367	rc = VINF_EM_RAW_EMULATE_INSTR;
368	#endif
369	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
370	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
371	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
372	return rc;
373	}
374	}
375	# if PGM_WITH_PAGING(PGM_GST_TYPE)
376	else
377	{
378	# ifdef PGM_SYNC_N_PAGES
379	/*
380	* If the region is write protected and we got a page not present fault, then sync
381	* the pages. If the fault was caused by a read, then restart the instruction.
382	* In case of write access continue to the GC write handler.
383	*/
384	if ( (HCPhys & (MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL)) == MM_RAM_FLAGS_VIRTUAL_WRITE
385	&& !(uErr & X86_TRAP_PF_P))
386	{
387	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
388	if ( VBOX_FAILURE(rc)
389	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
390	\|\| !(uErr & X86_TRAP_PF_RW))
391	{
392	AssertRC(rc);
393	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
394	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
395	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
396	return rc;
397	}
398	}
399	# endif
400	/*
401	* Ok, it's an virtual page access handler.
402	*
403	* Since it's faster to search by address, we'll do that first
404	* and then retry by GCPhys if that fails.
405	*/
406	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
407	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
408	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
409	*/
410	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
411	if (pCur)
412	{
413	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
414	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
415	\|\| !(uErr & X86_TRAP_PF_P)
416	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
417	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
418
419	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
420	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
421	&& ( uErr & X86_TRAP_PF_RW
422	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
423	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
424	{
425	# ifdef IN_GC
426	STAM_PROFILE_START(&pCur->Stat, h);
427	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
428	STAM_PROFILE_STOP(&pCur->Stat, h);
429	# else
430	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
431	# endif
432	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
433	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
434	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
435	return rc;
436	}
437	/* Unhandled part of a monitored page */
438	}
439	else
440	{
441	/* Check by physical address. */
442	PPGMVIRTHANDLER pCur;
443	unsigned iPage;
444	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
445	&pCur, &iPage);
446	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
447	if ( pCur
448	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
449	&& ( uErr & X86_TRAP_PF_RW
450	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
451	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) )
452	{
453	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
454	# ifdef IN_GC
455	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
456	Assert(off < pCur->cb);
457	STAM_PROFILE_START(&pCur->Stat, h);
458	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
459	STAM_PROFILE_STOP(&pCur->Stat, h);
460	# else
461	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
462	# endif
463	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
464	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
465	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
466	return rc;
467	}
468	}
469	}
470	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
471
472	/*
473	* There is a handled area of the page, but this fault doesn't belong to it.
474	* We must emulate the instruction.
475	*
476	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
477	* we first check if this was a page-not-present fault for a page with only
478	* write access handlers. Restart the instruction if it wasn't a write access.
479	*/
480	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
481
482	if ( !(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL))
483	&& !(uErr & X86_TRAP_PF_P))
484	{
485	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
486	if ( VBOX_FAILURE(rc)
487	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
488	\|\| !(uErr & X86_TRAP_PF_RW))
489	{
490	AssertRC(rc);
491	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
492	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
493	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
494	return rc;
495	}
496	}
497
498	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
499	* It's writing to an unhandled part of the LDT page several million times.
500	*/
501	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
502	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%VHp%s%s\n",
503	rc, HCPhys, HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER ? " phys" : "",
504	HCPhys & MM_RAM_FLAGS_VIRTUAL_HANDLER ? " virt" : ""));
505	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
506	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
507	return rc;
508	} /* if any kind of handler */
509
510	# if PGM_WITH_PAGING(PGM_GST_TYPE)
511	if (uErr & X86_TRAP_PF_P)
512	{
513	/*
514	* The page isn't marked, but it might still be monitored by a virtual page access handler.
515	* (ASSUMES no temporary disabling of virtual handlers.)
516	*/
517	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
518	* we should correct both the shadow page table and physical memory flags, and not only check for
519	* accesses within the handler region but for access to pages with virtual handlers. */
520	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
521	if (pCur)
522	{
523	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
524	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
525	\|\| !(uErr & X86_TRAP_PF_P)
526	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
527	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
528
529	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
530	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
531	&& ( uErr & X86_TRAP_PF_RW
532	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
533	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
534	{
535	# ifdef IN_GC
536	STAM_PROFILE_START(&pCur->Stat, h);
537	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
538	STAM_PROFILE_STOP(&pCur->Stat, h);
539	# else
540	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
541	# endif
542	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
543	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
544	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
545	return rc;
546	}
547	}
548	}
549	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
550	}
551	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
552
553	# ifdef PGM_OUT_OF_SYNC_IN_GC
554	/*
555	* We are here only if page is present in Guest page tables and trap is not handled
556	* by our handlers.
557	* Check it for page out-of-sync situation.
558	*/
559	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
560
561	if (!(uErr & X86_TRAP_PF_P))
562	{
563	/*
564	* Page is not present in our page tables.
565	* Try to sync it!
566	* BTW, fPageShw is invalid in this branch!
567	*/
568	if (uErr & X86_TRAP_PF_US)
569	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
570	else /* supervisor */
571	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
572
573	# if defined(LOG_ENABLED) && !defined(IN_RING0)
574	RTGCPHYS GCPhys;
575	uint64_t fPageGst;
576	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
577	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
578	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
579	# endif /* LOG_ENABLED */
580
581	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
582	if (cpl == 0)
583	{
584	uint64_t fPageGst;
585	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
586	if ( VBOX_SUCCESS(rc)
587	&& !(fPageGst & X86_PTE_US))
588	{
589	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
590	if ( pvFault == (RTGCPTR)pRegFrame->eip
591	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
592	# ifdef CSAM_DETECT_NEW_CODE_PAGES
593	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
594	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
595	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
596	)
597	{
598	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
599	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
600	if (rc != VINF_SUCCESS)
601	{
602	/*
603	* CSAM needs to perform a job in ring 3.
604	*
605	* Sync the page before going to the host context; otherwise we'll end up in a loop if
606	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
607	*/
608	LogFlow(("CSAM ring 3 job\n"));
609	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
610	AssertRC(rc2);
611
612	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
613	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
614	return rc;
615	}
616	}
617	# ifdef CSAM_DETECT_NEW_CODE_PAGES
618	else
619	if ( uErr == X86_TRAP_PF_RW
620	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
621	&& pRegFrame->ecx < 0x10000
622	)
623	{
624	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
625	* to detect loading of new code pages.
626	*/
627
628	/*
629	* Decode the instruction.
630	*/
631	RTGCPTR PC;
632	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
633	if (rc == VINF_SUCCESS)
634	{
635	DISCPUSTATE Cpu;
636	uint32_t cbOp;
637	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
638
639	/* For now we'll restrict this to rep movsw/d instructions */
640	if ( rc == VINF_SUCCESS
641	&& Cpu.pCurInstr->opcode == OP_MOVSWD
642	&& (Cpu.prefix & PREFIX_REP))
643	{
644	CSAMMarkPossibleCodePage(pVM, pvFault);
645	}
646	}
647	}
648	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
649
650	/*
651	* Mark this page as safe.
652	*/
653	/** @todo not correct for pages that contain both code and data!! */
654	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
655	CSAMMarkPage(pVM, pvFault, true);
656	}
657	}
658	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
659	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
660	if (VBOX_SUCCESS(rc))
661	{
662	/* The page was successfully synced, return to the guest. */
663	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
664	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
665	return VINF_SUCCESS;
666	}
667	}
668	else
669	{
670	/*
671	* A side effect of not flushing global PDEs are out of sync pages due
672	* to physical monitored regions, that are no longer valid.
673	* Assume for now it only applies to the read/write flag
674	*/
675	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
676	{
677	if (uErr & X86_TRAP_PF_US)
678	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
679	else /* supervisor */
680	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
681
682
683	/*
684	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
685	*/
686	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
687	if (VBOX_SUCCESS(rc))
688	{
689	/*
690	* Page was successfully synced, return to guest.
691	*/
692	# ifdef VBOX_STRICT
693	RTGCPHYS GCPhys;
694	uint64_t fPageGst;
695	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
696	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
697	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
698
699	uint64_t fPageShw;
700	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
701	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
702	# endif /* VBOX_STRICT */
703	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
704	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
705	return VINF_SUCCESS;
706	}
707	}
708
709	# ifdef VBOX_STRICT
710	/*
711	* Check for VMM page flags vs. Guest page flags consistency.
712	* Currently only for debug purposes.
713	*/
714	if (VBOX_SUCCESS(rc))
715	{
716	/* Get guest page flags. */
717	uint64_t fPageGst;
718	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
719	if (VBOX_SUCCESS(rc))
720	{
721	uint64_t fPageShw;
722	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
723
724	/*
725	* Compare page flags.
726	* Note: we have AVL, A, D bits desynched.
727	*/
728	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
729	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
730	}
731	else
732	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
733	}
734	else
735	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
736	# endif /* VBOX_STRICT */
737	}
738	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
739	# endif /* PGM_OUT_OF_SYNC_IN_GC */
740	}
741	else
742	{
743	/*
744	* Page not present in Guest OS or invalid page table address.
745	* This is potential virtual page access handler food.
746	*
747	* For the present we'll say that our access handlers don't
748	* work for this case - we've already discarded the page table
749	* not present case which is identical to this.
750	*
751	* When we perchance find we need this, we will probably have AVL
752	* trees (offset based) to operate on and we can measure their speed
753	* agains mapping a page table and probably rearrange this handling
754	* a bit. (Like, searching virtual ranges before checking the
755	* physical address.)
756	*/
757	}
758	}
759
760
761	# if PGM_WITH_PAGING(PGM_GST_TYPE)
762	/*
763	* Check if it's in a EIP based virtual page access handler range.
764	* This is only used for supervisor pages in flat mode.
765	*/
766	/** @todo this stuff is completely broken by the out-of-sync stuff. since we don't use this stuff, that's not really a problem yet. */
767	STAM_PROFILE_START(&pVM->pgm.s.StatEIPHandlers, d);
768	if (cpl == 0)
769	{
770	RTGCPTR pvEIP;
771	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
772	if ( VBOX_SUCCESS(rc)
773	&& pvEIP == (RTGCPTR)pRegFrame->eip)
774	{
775	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
776	if ( pCur
777	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
778	&& (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
779	{
780	LogFlow(("EIP handler\n"));
781	# ifdef IN_GC
782	STAM_PROFILE_START(&pCur->Stat, h);
783	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
784	STAM_PROFILE_STOP(&pCur->Stat, h);
785	# else
786	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
787	# endif
788	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
789	return rc;
790	}
791	}
792	}
793	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
794
795	/*
796	* Conclusion, this is a guest trap.
797	*/
798	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
799	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
800	return VINF_EM_RAW_GUEST_TRAP;
801	# else
802	/* present, but not a monitored page; perhaps the guest is probing physical memory */
803	return VINF_EM_RAW_EMULATE_INSTR;
804	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
805
806
807	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
808
809	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
810	return VERR_INTERNAL_ERROR;
811	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
812	}
813
814
815	/**
816	* Emulation of the invlpg instruction.
817	*
818	*
819	* @returns VBox status code.
820	*
821	* @param pVM VM handle.
822	* @param GCPtrPage Page to invalidate.
823	*
824	* @remark ASSUMES that the guest is updating before invalidating. This order
825	* isn't required by the CPU, so this is speculative and could cause
826	* trouble.
827	*
828	* @todo Flush page or page directory only if necessary!
829	* @todo Add a #define for simply invalidating the page.
830	*/
831	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
832	{
833	#if PGM_GST_TYPE == PGM_TYPE_32BIT
834
835	LogFlow(("InvalidatePage %x\n", GCPtrPage));
836	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
837	/*
838	* Get the shadow PD entry and skip out if this PD isn't present.
839	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
840	*/
841	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
842	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
843	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
844	# else
845	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
846	# endif
847	const SHWPDE PdeDst = *pPdeDst;
848	if (!PdeDst.n.u1Present)
849	{
850	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
851	return VINF_SUCCESS;
852	}
853
854	/*
855	* Get the guest PD entry and calc big page.
856	*/
857	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
858	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
859	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
860	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
861	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
862
863	# ifdef IN_RING3
864	/*
865	* If a CR3 Sync is pending we may ignore the invalidate page operation
866	* depending on the kind of sync and if it's a global page or not.
867	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
868	*/
869	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
870	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
871	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
872	&& fIsBigPage
873	&& PdeSrc.b.u1Global
874	&& (cr4 & X86_CR4_PGE)
875	)
876	)
877	# else
878	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
879	# endif
880	{
881	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
882	return VINF_SUCCESS;
883	}
884	# endif /* IN_RING3 */
885
886
887	/*
888	* Deal with the Guest PDE.
889	*/
890	int rc = VINF_SUCCESS;
891	if (PdeSrc.n.u1Present)
892	{
893	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
894	{
895	/*
896	* Conflict - Let SyncPT deal with it to avoid duplicate code.
897	*/
898	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
899	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
900	}
901	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
902	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
903	{
904	/*
905	* Mark not present so we can resync the PDE when it's used.
906	*/
907	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
908	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
909	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
910	pPdeDst->u = 0;
911	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
912	PGM_INVL_GUEST_TLBS();
913	}
914	# ifdef PGM_SYNC_ACCESSED_BIT
915	else if (!PdeSrc.n.u1Accessed)
916	{
917	/*
918	* Mark not present so we can set the accessed bit.
919	*/
920	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
921	pPdeDst->u = 0;
922	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
923	PGM_INVL_GUEST_TLBS();
924	}
925	# endif
926	else if (!fIsBigPage)
927	{
928	/*
929	* 4KB - page.
930	*/
931	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
932	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
933	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
934	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
935	# endif
936	if (pShwPage->GCPhys == GCPhys)
937	{
938	#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
939	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
940	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
941	if (pPT->a[iPTEDst].n.u1Present)
942	{
943	# ifdef PGMPOOL_WITH_USER_TRACKING
944	/* This is very unlikely with caching/monitoring enabled. */
945	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
946	# endif
947	pPT->a[iPTEDst].u = 0;
948	}
949	#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
950	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
951	if (VBOX_SUCCESS(rc))
952	rc = VINF_SUCCESS;
953	#endif
954	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
955	PGM_INVL_PG(GCPtrPage);
956	}
957	else
958	{
959	/*
960	* The page table address changed.
961	*/
962	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
963	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
964	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
965	pPdeDst->u = 0;
966	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
967	PGM_INVL_GUEST_TLBS();
968	}
969	}
970	else
971	{
972	/*
973	* 4MB - page.
974	*/
975	/* Before freeing the page, check if anything really changed. */
976	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
977	RTGCPHYS GCPhys = PdeSrc.u & X86_PDE4M_PG_MASK;
978	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
979	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
980	# endif
981	if ( pShwPage->GCPhys == GCPhys
982	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
983	{
984	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
985	/** @todo PAT */
986	# ifdef PGM_SYNC_DIRTY_BIT
987	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
988	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
989	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
990	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
991	# else
992	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
993	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
994	# endif
995	{
996	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
997	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
998	return VINF_SUCCESS;
999	}
1000	}
1001
1002	/*
1003	* Ok, the page table is present and it's been changed in the guest.
1004	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1005	* We could do this for some flushes in GC too, but we need an algorithm for
1006	* deciding which 4MB pages containing code likely to be executed very soon.
1007	*/
1008	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1009	pPdeDst->u = 0;
1010	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1011	DUMP_PDE_BIG("PGMInvalidatePage", iPDSrc, PdeSrc);
1012	PGM_INVL_BIG_PG(GCPtrPage);
1013	}
1014	}
1015	else
1016	{
1017	/*
1018	* Page directory is not present, mark shadow PDE not present.
1019	*/
1020	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1021	{
1022	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1023	pPdeDst->u = 0;
1024	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1025	PGM_INVL_PG(GCPtrPage);
1026	}
1027	else
1028	{
1029	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1030	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1031	}
1032	}
1033
1034	return rc;
1035
1036	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1037	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
1038	# endif
1039	return VINF_SUCCESS;
1040
1041	#elif PGM_GST_TYPE == PGM_TYPE_PAE
1042	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1043	//# error not implemented
1044	return VERR_INTERNAL_ERROR;
1045
1046	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1047	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
1048	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1049
1050	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1051	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1052	//# error not implemented
1053	return VERR_INTERNAL_ERROR;
1054
1055	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1056	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
1057	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1058
1059	#else /* guest real and protected mode */
1060	/* There's no such thing when paging is disabled. */
1061	return VINF_SUCCESS;
1062	#endif
1063	}
1064
1065
1066	#ifdef PGMPOOL_WITH_USER_TRACKING
1067	/**
1068	* Update the tracking of shadowed pages.
1069	*
1070	* @param pVM The VM handle.
1071	* @param pShwPage The shadow page.
1072	* @param HCPhys The physical page we is being dereferenced.
1073	*/
1074	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1075	{
1076	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1077	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1078	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1079
1080	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1081	* 1. have a medium sized HCPhys -> GCPhys cache (hash?)
1082	* 2. write protect all shadowed pages. I.e. implement caching.
1083	*/
1084	/*
1085	* Find the guest address.
1086	*/
1087	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTXSUFF(pRamRanges);
1088	pRam;
1089	pRam = pRam->CTXSUFF(pNext))
1090	{
1091	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1092	while (iPage-- > 0)
1093	{
1094	if ((pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) == HCPhys)
1095	{
1096	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1097	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aHCPhys[iPage]);
1098	pShwPage->cPresent--;
1099	pPool->cPresent--;
1100	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1101	return;
1102	}
1103	}
1104	}
1105
1106	for (;;)
1107	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1108	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1109	pShwPage->cPresent--;
1110	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1111	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1112	}
1113
1114
1115	/**
1116	* Update the tracking of shadowed pages.
1117	*
1118	* @param pVM The VM handle.
1119	* @param pShwPage The shadow page.
1120	* @param u16 The top 16-bit of the *pHCPhys.
1121	* @param pHCPhys Pointer to the ram range physical page entry.
1122	* @param iPTDst The index into the shadow table.
1123	*/
1124	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PRTHCPHYS pHCPhys, const unsigned iPTDst)
1125	{
1126	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1127	/*
1128	* We're making certain assumptions about the placement of cRef and idx.
1129	*/
1130	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1131	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1132
1133	/*
1134	* Just deal with the simple first time here.
1135	*/
1136	if (!u16)
1137	{
1138	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1139	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1140	}
1141	else
1142	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1143
1144	/* write back, trying to be clever... */
1145	Log2(("SyncPageWorkerTrackAddRef: u16=%#x *pHCPhys=%VHp->%VHp iPTDst=%#x\n",
1146	u16, pHCPhys, (pHCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1147	((uint16_t )pHCPhys + 3) = u16;
1148	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1149
1150	/* update statistics. */
1151	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1152	pShwPage->cPresent++;
1153	if (pShwPage->iFirstPresent > iPTDst)
1154	pShwPage->iFirstPresent = iPTDst;
1155	}
1156	#endif /* PGMPOOL_WITH_USER_TRACKING */
1157
1158
1159	/**
1160	* Creates a 4K shadow page for a guest page.
1161	*
1162	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1163	* physical address. The PdeSrc argument only the flags are used. No page structured
1164	* will be mapped in this function.
1165	*
1166	* @param pVM VM handle.
1167	* @param pPteDst Destination page table entry.
1168	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1169	* Can safely assume that only the flags are being used.
1170	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1171	* @param pShwPage Pointer to the shadow page.
1172	* @param iPTDst The index into the shadow table.
1173	*
1174	* @remark Not used for 2/4MB pages!
1175	*/
1176	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, VBOXPDE PdeSrc, VBOXPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1177	{
1178	if (PteSrc.n.u1Present)
1179	{
1180	/*
1181	* Find the ram range.
1182	*/
1183	PRTHCPHYS pHCPhys;
1184	int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, PteSrc.u & X86_PTE_PG_MASK, &pHCPhys);
1185	if (VBOX_SUCCESS(rc))
1186	{
1187	/** @todo investiage PWT, PCD and PAT. */
1188	/*
1189	* Make page table entry.
1190	*/
1191	const RTHCPHYS HCPhys = *pHCPhys;
1192	SHWPTE PteDst;
1193	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1194	{
1195	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1196	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1197	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1198	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1199	else
1200	PteDst.u = 0;
1201	/** @todo count these two kinds. */
1202	}
1203	else
1204	{
1205	#ifdef PGM_SYNC_DIRTY_BIT
1206	# ifdef PGM_SYNC_ACCESSED_BIT
1207	/*
1208	* If the page or page directory entry is not marked accessed,
1209	* we mark the page not present.
1210	*/
1211	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1212	{
1213	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1214	PteDst.u = 0;
1215	}
1216	else
1217	# endif
1218	/*
1219	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1220	* when the page is modified.
1221	*/
1222	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1223	{
1224	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1225	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1226	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1227	\| PGM_PTFLAGS_TRACK_DIRTY;
1228	}
1229	else
1230	{
1231	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1232	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1233	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1234	}
1235	#endif
1236	}
1237
1238	#ifdef PGMPOOL_WITH_USER_TRACKING
1239	/*
1240	* Keep user track up to date.
1241	*/
1242	if (PteDst.n.u1Present)
1243	{
1244	if (!pPteDst->n.u1Present)
1245	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1246	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1247	{
1248	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1249	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1250	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1251	}
1252	}
1253	else if (pPteDst->n.u1Present)
1254	{
1255	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1256	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1257	}
1258	#endif /* PGMPOOL_WITH_USER_TRACKING */
1259
1260	/*
1261	* Update statistics and commit the entry.
1262	*/
1263	if (!PteSrc.n.u1Global)
1264	pShwPage->fSeenNonGlobal = true;
1265	*pPteDst = PteDst;
1266	}
1267	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1268	/** @todo count these. */
1269	}
1270	else
1271	{
1272	/*
1273	* Page not-present.
1274	*/
1275	#ifdef PGMPOOL_WITH_USER_TRACKING
1276	/* Keep user track up to date. */
1277	if (pPteDst->n.u1Present)
1278	{
1279	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1280	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1281	}
1282	#endif /* PGMPOOL_WITH_USER_TRACKING */
1283	pPteDst->u = 0;
1284	/** @todo count these. */
1285	}
1286	}
1287
1288
1289	/**
1290	* Syncs a guest OS page.
1291	*
1292	* There are no conflicts at this point, neither is there any need for
1293	* page table allocations.
1294	*
1295	* @returns VBox status code.
1296	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1297	* @param pVM VM handle.
1298	* @param PdeSrc Page directory entry of the guest.
1299	* @param GCPtrPage Guest context page address.
1300	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1301	* @param uErr Fault error (X86_TRAP_PF_*).
1302	*/
1303	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1304	{
1305	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1306
1307	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1308
1309	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1310	# error "Invalid shadow mode for 32-bit guest mode!"
1311	# endif
1312
1313	/*
1314	* Assert preconditions.
1315	*/
1316	# if GC_ARCH_BITS != 32
1317	Assert(GCPtrPage < _4G); //???
1318	# endif
1319	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & X86_PD_MASK]);
1320	Assert(PdeSrc.n.u1Present);
1321	Assert(cPages);
1322
1323	/*
1324	* Get the shadow PDE, find the shadow page table in the pool.
1325	*/
1326	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1327	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1328	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1329	# else /* PAE */
1330	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1331	# endif
1332	Assert(PdeDst.n.u1Present);
1333	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1334
1335	/*
1336	* Check that the page is present and that the shadow PDE isn't out of sync.
1337	*/
1338	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1339	RTGCPHYS GCPhys;
1340	if (!fBigPage)
1341	{
1342	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1343	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1344	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1345	# endif
1346	}
1347	else
1348	{
1349	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1350	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1351	GCPhys \|= GCPtrPage & X86_PAGE_2M_SIZE;
1352	# endif
1353	}
1354	if ( pShwPage->GCPhys == GCPhys
1355	&& PdeSrc.n.u1Present
1356	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1357	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1358	)
1359	{
1360	# ifdef PGM_SYNC_ACCESSED_BIT
1361	/*
1362	* Check that the PDE is marked accessed already.
1363	* Since we set the accessed bit before getting here on a #PF, this
1364	* check is only meant for dealing with non-#PF'ing paths.
1365	*/
1366	if (PdeSrc.n.u1Accessed)
1367	# endif
1368	{
1369	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1370	if (!fBigPage)
1371	{
1372	/*
1373	* 4KB Page - Map the guest page table.
1374	*/
1375	PVBOXPT pPTSrc;
1376	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & X86_PDE_PG_MASK, &pPTSrc);
1377	if (VBOX_SUCCESS(rc))
1378	{
1379	# ifdef PGM_SYNC_N_PAGES
1380	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1381	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1382	{
1383	/*
1384	* This code path is currently only taken when the caller is PGMTrap0eHandler
1385	* for non-present pages!
1386	*
1387	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1388	* deal with locality.
1389	*/
1390	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1391	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1392	const unsigned offPTSrc = 0;
1393	# else
1394	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1395	# endif
1396	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1397	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1398	iPTDst = 0;
1399	else
1400	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1401	for (; iPTDst < iPTDstEnd; iPTDst++)
1402	{
1403	if (!pPTDst->a[iPTDst].n.u1Present)
1404	{
1405	VBOXPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1406	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1407	NOREF(GCPtrCurPage);
1408	#ifndef IN_RING0
1409	/*
1410	* Assuming kernel code will be marked as supervisor - and not as user level
1411	* and executed using a conforming code selector - And marked as readonly.
1412	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1413	*/
1414	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1415	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1416	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1417	\|\| PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
1418	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
1419	)
1420	#endif
1421	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1422	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1423	GCPtrCurPage, PteSrc.n.u1Present,
1424	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1425	PteSrc.n.u1User & PdeSrc.n.u1User,
1426	(uint64_t)PteSrc.u,
1427	(uint64_t)pPTDst->a[iPTDst].u,
1428	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1429	}
1430	}
1431	}
1432	else
1433	# endif /* PGM_SYNC_N_PAGES */
1434	{
1435	const unsigned iPTSrc = (GCPtrPage >> X86_PT_SHIFT) & X86_PT_MASK;
1436	VBOXPTE PteSrc = pPTSrc->a[iPTSrc];
1437	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1438	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1439	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1440	GCPtrPage, PteSrc.n.u1Present,
1441	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1442	PteSrc.n.u1User & PdeSrc.n.u1User,
1443	(uint64_t)PteSrc.u,
1444	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1445	}
1446	}
1447	else /* MMIO or invalid page: emulated in #PF handler. */
1448	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1449	}
1450	else
1451	{
1452	/*
1453	* 4/2MB page - lazy syncing shadow 4K pages.
1454	* (There are many causes of getting here, it's no longer only CSAM.)
1455	*/
1456	/* Calculate the GC physical address of this 4KB shadow page. */
1457	RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PAE_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & PAGE_OFFSET_MASK_BIG);
1458	/* Find ram range. */
1459	PRTHCPHYS pHCPhys;
1460	int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, GCPhys, &pHCPhys);
1461	if (VBOX_SUCCESS(rc))
1462	{
1463	/*
1464	* Make shadow PTE entry.
1465	*/
1466	RTHCPHYS HCPhys = *pHCPhys;
1467	SHWPTE PteDst;
1468	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1469	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1470	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1471	{
1472	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1473	PteDst.n.u1Write = 0;
1474	else
1475	PteDst.u = 0;
1476	}
1477	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1478	# ifdef PGMPOOL_WITH_USER_TRACKING
1479	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1480	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1481	# endif
1482	pPTDst->a[iPTDst] = PteDst;
1483
1484
1485	# ifdef PGM_SYNC_DIRTY_BIT
1486	/*
1487	* If the page is not flagged as dirty and is writable, then make it read-only
1488	* at PD level, so we can set the dirty bit when the page is modified.
1489	*
1490	* ASSUMES that page access handlers are implemented on page table entry level.
1491	* Thus we will first catch the dirty access and set PDE.D and restart. If
1492	* there is an access handler, we'll trap again and let it work on the problem.
1493	*/
1494	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1495	* As for invlpg, it simply frees the whole shadow PT.
1496	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1497	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1498	{
1499	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1500	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1501	PdeDst.n.u1Write = 0;
1502	}
1503	else
1504	{
1505	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1506	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1507	}
1508	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1509	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1510	# else /* PAE */
1511	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1512	# endif
1513	# endif /* PGM_SYNC_DIRTY_BIT */
1514	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1515	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1516	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1517	}
1518	}
1519	return VINF_SUCCESS;
1520	}
1521	# ifdef PGM_SYNC_ACCESSED_BIT
1522	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1523	#endif
1524	}
1525	else
1526	{
1527	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1528	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1529	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1530	}
1531
1532	/*
1533	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1534	* Yea, I'm lazy.
1535	*/
1536	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1537	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1538	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1539	# else /* PAE */
1540	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1541	# endif
1542	PGM_INVL_GUEST_TLBS();
1543	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1544
1545	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1546
1547	# ifdef PGM_SYNC_N_PAGES
1548	/*
1549	* Get the shadow PDE, find the shadow page table in the pool.
1550	*/
1551	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1552	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1553	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1554	# else /* PAE */
1555	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1556	# endif
1557	Assert(PdeDst.n.u1Present);
1558	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1559	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1560
1561	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1562	const unsigned offPTSrc = 0;
1563	# else
1564	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1565	# endif
1566
1567	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1568	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1569	{
1570	/*
1571	* This code path is currently only taken when the caller is PGMTrap0eHandler
1572	* for non-present pages!
1573	*
1574	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1575	* deal with locality.
1576	*/
1577	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1578	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1579	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1580	iPTDst = 0;
1581	else
1582	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1583	for (; iPTDst < iPTDstEnd; iPTDst++)
1584	{
1585	if (!pPTDst->a[iPTDst].n.u1Present)
1586	{
1587	VBOXPTE PteSrc;
1588
1589	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1590
1591	/* Fake the page table entry */
1592	PteSrc.u = GCPtrCurPage;
1593	PteSrc.n.u1Present = 1;
1594	PteSrc.n.u1Dirty = 1;
1595	PteSrc.n.u1Accessed = 1;
1596	PteSrc.n.u1Write = 1;
1597
1598	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1599
1600	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1601	GCPtrCurPage, PteSrc.n.u1Present,
1602	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1603	PteSrc.n.u1User & PdeSrc.n.u1User,
1604	(uint64_t)PteSrc.u,
1605	(uint64_t)pPTDst->a[iPTDst].u,
1606	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1607	}
1608	}
1609	}
1610	else
1611	# endif /* PGM_SYNC_N_PAGES */
1612	{
1613	VBOXPTE PteSrc;
1614	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1615	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1616
1617	/* Fake the page table entry */
1618	PteSrc.u = GCPtrCurPage;
1619	PteSrc.n.u1Present = 1;
1620	PteSrc.n.u1Dirty = 1;
1621	PteSrc.n.u1Accessed = 1;
1622	PteSrc.n.u1Write = 1;
1623	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1624
1625	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1626	GCPtrPage, PteSrc.n.u1Present,
1627	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1628	PteSrc.n.u1User & PdeSrc.n.u1User,
1629	(uint64_t)PteSrc.u,
1630	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1631	}
1632	return VINF_SUCCESS;
1633
1634	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1635	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1636	return VERR_INTERNAL_ERROR;
1637	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1638	}
1639
1640
1641
1642	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1643
1644	# ifdef PGM_SYNC_DIRTY_BIT
1645
1646	/**
1647	* Investigate page fault and handle write protection page faults caused by
1648	* dirty bit tracking.
1649	*
1650	* @returns VBox status code.
1651	* @param pVM VM handle.
1652	* @param uErr Page fault error code.
1653	* @param pPdeDst Shadow page directory entry.
1654	* @param pPdeSrc Guest page directory entry.
1655	* @param GCPtrPage Guest context page address.
1656	*/
1657	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1658	{
1659	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1660	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1661
1662	/*
1663	* Real page fault?
1664	*/
1665	if ( (uErr & X86_TRAP_PF_RSVD)
1666	\|\| !pPdeSrc->n.u1Present
1667	\|\| ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1668	\|\| ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1669	{
1670	# ifdef IN_GC
1671	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1672	# endif
1673	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1674	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1675
1676	if (pPdeSrc->n.u1Present)
1677	{
1678	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1679	* See the 2nd case below as well.
1680	*/
1681	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1682	{
1683	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1684	}
1685	else
1686	{
1687	/*
1688	* Map the guest page table.
1689	*/
1690	PVBOXPT pPTSrc;
1691	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1692	if (VBOX_SUCCESS(rc))
1693	{
1694	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1695	const VBOXPTE PteSrc = *pPteSrc;
1696	if (pPteSrc->n.u1Present)
1697	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1698	}
1699	AssertRC(rc);
1700	}
1701	}
1702	return VINF_EM_RAW_GUEST_TRAP;
1703	}
1704
1705	/*
1706	* First check the easy case where the page directory has been marked read-only to track
1707	* the dirty bit of an emulated BIG page
1708	*/
1709	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1710	{
1711	/* Mark guest page directory as accessed */
1712	pPdeSrc->b.u1Accessed = 1;
1713
1714	/*
1715	* Only write protection page faults are relevant here.
1716	*/
1717	if (uErr & X86_TRAP_PF_RW)
1718	{
1719	/* Mark guest page directory as dirty (BIG page only). */
1720	pPdeSrc->b.u1Dirty = 1;
1721
1722	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1723	{
1724	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1725
1726	Assert(pPdeSrc->b.u1Write);
1727
1728	pPdeDst->n.u1Write = 1;
1729	pPdeDst->n.u1Accessed = 1;
1730	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1731	PGM_INVL_BIG_PG(GCPtrPage);
1732	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1733	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1734	}
1735	}
1736	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1737	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1738	}
1739	/* else: 4KB page table */
1740
1741	/*
1742	* Map the guest page table.
1743	*/
1744	PVBOXPT pPTSrc;
1745	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1746	if (VBOX_SUCCESS(rc))
1747	{
1748	/*
1749	* Real page fault?
1750	*/
1751	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1752	const VBOXPTE PteSrc = *pPteSrc;
1753	if ( !PteSrc.n.u1Present
1754	\|\| ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1755	\|\| ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1756	)
1757	{
1758	# ifdef IN_GC
1759	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1760	# endif
1761	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1762	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1763
1764	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1765	* See the 2nd case above as well.
1766	*/
1767	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1768	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1769
1770	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1771	return VINF_EM_RAW_GUEST_TRAP;
1772	}
1773	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1774
1775	/*
1776	* Set the accessed bits in the page directory and the page table.
1777	*/
1778	pPdeSrc->n.u1Accessed = 1;
1779	pPteSrc->n.u1Accessed = 1;
1780
1781	/*
1782	* Only write protection page faults are relevant here.
1783	*/
1784	if (uErr & X86_TRAP_PF_RW)
1785	{
1786	/* Write access, so mark guest entry as dirty. */
1787	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1788	if (!pPteSrc->n.u1Dirty)
1789	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1790	else
1791	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1792	# endif
1793	pPteSrc->n.u1Dirty = 1;
1794
1795	if (pPdeDst->n.u1Present)
1796	{
1797	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1798	* Our individual shadow handlers will provide more information and force a fatal exit.
1799	*/
1800	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1801	{
1802	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1803	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1804	return VINF_SUCCESS;
1805	}
1806
1807	/*
1808	* Map shadow page table.
1809	*/
1810	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1811	if (pShwPage)
1812	{
1813	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1814	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1815	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1816	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1817	{
1818	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1819	# ifdef VBOX_STRICT
1820	RTHCPHYS HCPhys;
1821	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, pPteSrc->u & X86_PTE_PG_MASK, &HCPhys);
1822	if (VBOX_SUCCESS(rc))
1823	AssertMsg(!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)),
1824	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1825	# endif
1826	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1827
1828	Assert(pPteSrc->n.u1Write);
1829
1830	pPteDst->n.u1Write = 1;
1831	pPteDst->n.u1Dirty = 1;
1832	pPteDst->n.u1Accessed = 1;
1833	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1834	PGM_INVL_PG(GCPtrPage);
1835
1836	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1837	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1838	}
1839	}
1840	else
1841	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1842	}
1843	}
1844	/** @todo Optimize accessed bit emulation? */
1845	# ifdef VBOX_STRICT
1846	/*
1847	* Sanity check.
1848	*/
1849	else if ( !pPteSrc->n.u1Dirty
1850	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1851	&& pPdeDst->n.u1Present)
1852	{
1853	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1854	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1855	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1856	if ( pPteDst->n.u1Present
1857	&& pPteDst->n.u1Write)
1858	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1859	}
1860	# endif /* VBOX_STRICT */
1861	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1862	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1863	}
1864	AssertRC(rc);
1865	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1866	return rc;
1867	}
1868
1869	# endif
1870
1871	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1872
1873
1874	/**
1875	* Sync a shadow page table.
1876	*
1877	* The shadow page table is not present. This includes the case where
1878	* there is a conflict with a mapping.
1879	*
1880	* @returns VBox status code.
1881	* @param pVM VM handle.
1882	* @param iPD Page directory index.
1883	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1884	* Assume this is a temporary mapping.
1885	* @param GCPtrPage GC Pointer of the page that caused the fault
1886	*/
1887	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage)
1888	{
1889	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1890	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1891	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1892
1893	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1894
1895	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1896	# error "Invalid shadow mode for 32-bit guest mode!"
1897	# endif
1898
1899	/*
1900	* Validate input a little bit.
1901	*/
1902	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1903	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1904	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1905	# else
1906	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1907	# endif
1908	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1909	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1910	SHWPDE PdeDst = *pPdeDst;
1911
1912	/*
1913	* Check for conflicts.
1914	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1915	* HC: Simply resolve the conflict.
1916	*/
1917	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1918	{
1919	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1920	# ifndef IN_RING3
1921	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1922	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1923	return VERR_ADDRESS_CONFLICT;
1924	# else
1925	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1926	Assert(pMapping);
1927	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1928	if (VBOX_FAILURE(rc))
1929	{
1930	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1931	return rc;
1932	}
1933	PdeDst = *pPdeDst;
1934	# endif
1935	}
1936	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1937
1938	/*
1939	* Sync page directory entry.
1940	*/
1941	int rc = VINF_SUCCESS;
1942	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1943	if (PdeSrc.n.u1Present)
1944	{
1945	/*
1946	* Allocate & map the page table.
1947	*/
1948	PSHWPT pPTDst;
1949	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1950	PPGMPOOLPAGE pShwPage;
1951	RTGCPHYS GCPhys;
1952	if (fPageTable)
1953	{
1954	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1955	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1956	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1957	# endif
1958	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1959	}
1960	else
1961	{
1962	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1963	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1964	GCPhys \|= GCPtrPage & BIT(X86_PAGE_2M_SHIFT);
1965	# endif
1966	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1967	}
1968	if (rc == VINF_SUCCESS)
1969	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1970	else if (rc == VINF_PGM_CACHED_PAGE)
1971	{
1972	/*
1973	* The PT was cached, just hook it up.
1974	*/
1975	if (fPageTable)
1976	PdeDst.u = pShwPage->Core.Key
1977	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1978	else
1979	{
1980	PdeDst.u = pShwPage->Core.Key
1981	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1982	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1983	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1984	{
1985	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1986	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1987	PdeDst.b.u1Write = 0;
1988	}
1989	# endif
1990	}
1991	*pPdeDst = PdeDst;
1992	return VINF_SUCCESS;
1993	}
1994	else if (rc == VERR_PGM_POOL_FLUSHED)
1995	return VINF_PGM_SYNC_CR3;
1996	else
1997	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1998	PdeDst.u &= X86_PDE_AVL_MASK;
1999	PdeDst.u \|= pShwPage->Core.Key;
2000
2001	# ifdef PGM_SYNC_DIRTY_BIT
2002	/*
2003	* Page directory has been accessed (this is a fault situation, remember).
2004	*/
2005	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2006	# endif
2007	if (fPageTable)
2008	{
2009	/*
2010	* Page table - 4KB.
2011	*
2012	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2013	*/
2014	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2015	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2016	PGSTPT pPTSrc;
2017	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2018	if (VBOX_SUCCESS(rc))
2019	{
2020	/*
2021	* Start by syncing the page directory entry so CSAM's TLB trick works.
2022	*/
2023	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK))
2024	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2025	*pPdeDst = PdeDst;
2026
2027	/*
2028	* Directory/page user or supervisor privilege: (same goes for read/write)
2029	*
2030	* Directory Page Combined
2031	* U/S U/S U/S
2032	* 0 0 0
2033	* 0 1 0
2034	* 1 0 0
2035	* 1 1 1
2036	*
2037	* Simple AND operation. Table listed for completeness.
2038	*
2039	*/
2040	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2041	# ifdef PGM_SYNC_N_PAGES
2042	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2043	unsigned iPTDst = iPTBase;
2044	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2045	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2046	iPTDst = 0;
2047	else
2048	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2049	# else /* !PGM_SYNC_N_PAGES */
2050	unsigned iPTDst = 0;
2051	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2052	# endif /* !PGM_SYNC_N_PAGES */
2053	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2054	const unsigned offPTSrc = 0;
2055	# else
2056	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2057	# endif
2058	for (; iPTDst < iPTDstEnd; iPTDst++)
2059	{
2060	const unsigned iPTSrc = iPTDst + offPTSrc;
2061	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2062
2063	if (PteSrc.n.u1Present) /* we've already cleared it above */
2064	{
2065	#ifndef IN_RING0
2066	/*
2067	* Assuming kernel code will be marked as supervisor - and not as user level
2068	* and executed using a conforming code selector - And marked as readonly.
2069	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2070	*/
2071	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2072	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2073	\|\| PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
2074	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
2075	)
2076	#endif
2077	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2078	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2079	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2080	PteSrc.n.u1Present,
2081	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2082	PteSrc.n.u1User & PdeSrc.n.u1User,
2083	(uint64_t)PteSrc.u,
2084	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2085	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2086	}
2087	} /* for PTEs */
2088	}
2089	}
2090	else
2091	{
2092	/*
2093	* Big page - 2/4MB.
2094	*
2095	* We'll walk the ram range list in parallel and optimize lookups.
2096	* We will only sync on shadow page table at a time.
2097	*/
2098	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2099
2100	/**
2101	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2102	*/
2103
2104	/*
2105	* Start by syncing the page directory entry.
2106	*/
2107	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2108	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2109
2110	# ifdef PGM_SYNC_DIRTY_BIT
2111	/*
2112	* If the page is not flagged as dirty and is writable, then make it read-only
2113	* at PD level, so we can set the dirty bit when the page is modified.
2114	*
2115	* ASSUMES that page access handlers are implemented on page table entry level.
2116	* Thus we will first catch the dirty access and set PDE.D and restart. If
2117	* there is an access handler, we'll trap again and let it work on the problem.
2118	*/
2119	/** @todo move the above stuff to a section in the PGM documentation. */
2120	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2121	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2122	{
2123	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2124	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2125	PdeDst.b.u1Write = 0;
2126	}
2127	# endif /* PGM_SYNC_DIRTY_BIT */
2128	*pPdeDst = PdeDst;
2129
2130	/*
2131	* Fill the shadow page table.
2132	*/
2133	/* Get address and flags from the source PDE. */
2134	SHWPTE PteDstBase;
2135	PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2136
2137	/* Loop thru the entries in the shadow PT. */
2138	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2139	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2140	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2141	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2142	PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
2143	unsigned iPTDst = 0;
2144	while (iPTDst < ELEMENTS(pPTDst->a))
2145	{
2146	/* Advance ram range list. */
2147	while (pRam && GCPhys > pRam->GCPhysLast)
2148	pRam = CTXSUFF(pRam->pNext);
2149	if (pRam && GCPhys >= pRam->GCPhys)
2150	{
2151	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2152	do
2153	{
2154	/* Make shadow PTE. */
2155	RTHCPHYS HCPhys = pRam->aHCPhys[iHCPage];
2156	SHWPTE PteDst;
2157
2158	/* Make sure the RAM has already been allocated. */
2159	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2160	{
2161	if (RT_UNLIKELY(!(pRam->aHCPhys[iHCPage] & X86_PTE_PAE_PG_MASK)))
2162	{
2163	# ifdef IN_RING3
2164	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2165	# else
2166	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2167	# endif
2168	if (rc != VINF_SUCCESS)
2169	return rc;
2170
2171	HCPhys = pRam->aHCPhys[iHCPage];
2172	}
2173	}
2174
2175	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
2176	{
2177	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
2178	{
2179	PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) \| PteDstBase.u;
2180	PteDst.n.u1Write = 0;
2181	}
2182	else
2183	PteDst.u = 0;
2184	}
2185	# ifndef IN_RING0
2186	/*
2187	* Assuming kernel code will be marked as supervisor and not as user level and executed
2188	* using a conforming code selector. Don't check for readonly, as that implies the whole
2189	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2190	*/
2191	else if ( !PdeSrc.n.u1User
2192	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2193	PteDst.u = 0;
2194	# endif
2195	else
2196	PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) \| PteDstBase.u;
2197	# ifdef PGMPOOL_WITH_USER_TRACKING
2198	if (PteDst.n.u1Present)
2199	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, &pRam->aHCPhys[iHCPage], iPTDst);
2200	# endif
2201	/* commit it */
2202	pPTDst->a[iPTDst] = PteDst;
2203	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2204	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2205	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2206
2207	/* advance */
2208	GCPhys += PAGE_SIZE;
2209	iHCPage++;
2210	iPTDst++;
2211	} while ( iPTDst < ELEMENTS(pPTDst->a)
2212	&& GCPhys <= pRam->GCPhysLast);
2213	}
2214	else if (pRam)
2215	{
2216	Log(("Invalid pages at %VGp\n", GCPhys));
2217	do
2218	{
2219	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2220	GCPhys += PAGE_SIZE;
2221	iPTDst++;
2222	} while ( iPTDst < ELEMENTS(pPTDst->a)
2223	&& GCPhys < pRam->GCPhys);
2224	}
2225	else
2226	{
2227	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2228	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2229	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2230	}
2231	} /* while more PTEs */
2232	} /* 4KB / 4MB */
2233	}
2234	else
2235	AssertRelease(!PdeDst.n.u1Present);
2236
2237	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2238	# ifdef IN_GC
2239	if (VBOX_FAILURE(rc))
2240	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2241	# endif
2242	return rc;
2243
2244	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2245
2246	int rc = VINF_SUCCESS;
2247
2248	/*
2249	* Validate input a little bit.
2250	*/
2251	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2252	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2253	# else
2254	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2255	# endif
2256	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2257	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2258	SHWPDE PdeDst = *pPdeDst;
2259
2260	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2261	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2262
2263	VBOXPDE PdeSrc;
2264	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2265	PdeSrc.n.u1Present = 1;
2266	PdeSrc.n.u1Write = 1;
2267	PdeSrc.n.u1Accessed = 1;
2268
2269	/*
2270	* Allocate & map the page table.
2271	*/
2272	PSHWPT pPTDst;
2273	PPGMPOOLPAGE pShwPage;
2274	RTGCPHYS GCPhys;
2275
2276	/* Virtual address = physical address */
2277	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2278	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2279
2280	if ( rc == VINF_SUCCESS
2281	\|\| rc == VINF_PGM_CACHED_PAGE)
2282	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2283	else
2284	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2285
2286	PdeDst.u &= X86_PDE_AVL_MASK;
2287	PdeDst.u \|= pShwPage->Core.Key;
2288	PdeDst.n.u1Present = 1;
2289	*pPdeDst = PdeDst;
2290
2291	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2292	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2293	return rc;
2294
2295	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2296
2297	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2298	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2299	return VERR_INTERNAL_ERROR;
2300	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2301	}
2302
2303
2304
2305	/**
2306	* Prefetch a page/set of pages.
2307	*
2308	* Typically used to sync commonly used pages before entering raw mode
2309	* after a CR3 reload.
2310	*
2311	* @returns VBox status code.
2312	* @param pVM VM handle.
2313	* @param GCPtrPage Page to invalidate.
2314	*/
2315	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2316	{
2317	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2318
2319	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2320	# error "Invalid shadow mode for 32-bit guest mode!"
2321	# endif
2322
2323	/*
2324	* Check that all Guest levels thru the PDE are present, getting the
2325	* PD and PDE in the processes.
2326	*/
2327	int rc = VINF_SUCCESS;
2328	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2329	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2330	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2331	# else
2332	PVBOXPD pPDSrc = NULL;
2333	const unsigned iPDSrc = 0;
2334	# endif
2335
2336	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2337	const VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2338	# else
2339	VBOXPDE PdeSrc;
2340	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2341	PdeSrc.n.u1Present = 1;
2342	PdeSrc.n.u1Write = 1;
2343	PdeSrc.n.u1Accessed = 1;
2344	# endif
2345
2346	# ifdef PGM_SYNC_ACCESSED_BIT
2347	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2348	# else
2349	if (PdeSrc.n.u1Present)
2350	# endif
2351	{
2352	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2353	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2354	# else
2355	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2356	# endif
2357	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2358	{
2359	if (!PdeDst.n.u1Present)
2360	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2361	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2362	else
2363	{
2364	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2365	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2366	* makes no sense to prefetch more than one page.
2367	*/
2368	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2369	if (VBOX_SUCCESS(rc))
2370	rc = VINF_SUCCESS;
2371	}
2372	}
2373	}
2374	return rc;
2375
2376	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2377
2378	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2379	return VERR_INTERNAL_ERROR;
2380	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2381	}
2382
2383
2384
2385
2386	/**
2387	* Syncs a page during a PGMVerifyAccess() call.
2388	*
2389	* @returns VBox status code (informational included).
2390	* @param GCPtrPage The address of the page to sync.
2391	* @param fPage The effective guest page flags.
2392	* @param uErr The trap error code.
2393	*/
2394	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2395	{
2396	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2397
2398	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2399
2400	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2401	# error "Invalid shadow mode for 32-bit guest mode!"
2402	# endif
2403
2404	#ifndef IN_RING0
2405	if (!(fPage & X86_PTE_US))
2406	{
2407	/*
2408	* Mark this page as safe.
2409	*/
2410	/** @todo not correct for pages that contain both code and data!! */
2411	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2412	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2413	}
2414	#endif
2415	/*
2416	* Get guest PD and index.
2417	*/
2418	unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2419	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2420	int rc = VINF_SUCCESS;
2421
2422	# ifdef PGM_SYNC_DIRTY_BIT
2423	/*
2424	* First check if the page fault was caused by dirty bit tracking
2425	*/
2426	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2427	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2428	# else
2429	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2430	# endif
2431	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2432	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2433	Log(("PGMVerifyAccess: success (dirty)\n"));
2434	else
2435	# endif /* PGM_SYNC_DIRTY_BIT */
2436	{
2437	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2438	if (uErr & X86_TRAP_PF_US)
2439	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2440	else /* supervisor */
2441	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2442
2443	rc = PGM_BTH_NAME(SyncPage)(pVM, pPDSrc->a[iPDSrc], GCPtrPage, 1, 0);
2444	if (VBOX_SUCCESS(rc))
2445	{
2446	/* Page was successfully synced */
2447	Log(("PGMVerifyAccess: success (sync)\n"));
2448	rc = VINF_SUCCESS;
2449	}
2450	else
2451	{
2452	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2453	return VINF_EM_RAW_GUEST_TRAP;
2454	}
2455	}
2456	return rc;
2457
2458	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2459	/* Everything is allowed */
2460	return VINF_SUCCESS;
2461
2462	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2463
2464	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2465	return VERR_INTERNAL_ERROR;
2466	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2467	}
2468
2469
2470	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2471	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2472	/**
2473	* Figures out which kind of shadow page this guest PDE warrants.
2474	*
2475	* @returns Shadow page kind.
2476	* @param pPdeSrc The guest PDE in question.
2477	* @param cr4 The current guest cr4 value.
2478	*/
2479	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const VBOXPDE *pPdeSrc, uint32_t cr4)
2480	{
2481	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2482	return BTH_PGMPOOLKIND_PT_FOR_PT;
2483	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2484	//{
2485	// case 0:
2486	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2487	// case X86_PDE4M_RW:
2488	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2489	// case X86_PDE4M_US:
2490	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2491	// case X86_PDE4M_RW \| X86_PDE4M_US:
2492	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2493	# if 0
2494	// case X86_PDE4M_PAE_NX:
2495	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2496	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2497	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2498	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2499	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2500	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2501	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2502	# endif
2503	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2504	//}
2505	}
2506	# endif
2507	#endif
2508
2509	#undef MY_STAM_COUNTER_INC
2510	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2511
2512
2513	/**
2514	* Syncs the paging hierarchy starting at CR3.
2515	*
2516	* @returns VBox status code, no specials.
2517	* @param pVM The virtual machine.
2518	* @param cr0 Guest context CR0 register
2519	* @param cr3 Guest context CR3 register
2520	* @param cr4 Guest context CR4 register
2521	* @param fGlobal Including global page directories or not
2522	*/
2523	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2524	{
2525	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2526	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2527	/*
2528	* Inform the PGM PD Cache Manager about the pending sync.
2529	*/
2530	if (fGlobal \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2531	{
2532	# if 0 /** @todo what the heck is this about? */
2533	/* Don't cause an additional global CR3 reload the next time (the flag is cleared in PGMSyncCR3). */
2534	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2535	# endif
2536
2537	/* Change this CR3 reload to be a global one. */
2538	fGlobal = true;
2539	}
2540	# endif
2541	#endif
2542
2543	/*
2544	* Update page access handlers.
2545	* The virtual are always flushed, while the physical are only on demand.
2546	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2547	* have to look into that later because it will have a bad influence on the performance.
2548	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2549	* bird: Yes, but that won't work for aliases.
2550	*/
2551	/** @todo this MUST go away. See #1557. */
2552	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2553	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2554	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2555
2556	#ifdef PGMPOOL_WITH_MONITORING
2557	/*
2558	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2559	* Occationally we will have to clear all the shadow page tables because we wanted
2560	* to monitor a page which was mapped by too many shadowed page tables. This operation
2561	* sometimes refered to as a 'lightweight flush'.
2562	*/
2563	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2564	pgmPoolMonitorModifiedClearAll(pVM);
2565	else
2566	{
2567	# ifdef IN_RING3
2568	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2569	pgmPoolClearAll(pVM);
2570	# else
2571	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2572	return VINF_PGM_SYNC_CR3;
2573	# endif
2574	}
2575	#endif
2576
2577	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2578	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2579
2580	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2581	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2582	/*
2583	* Get page directory addresses.
2584	*/
2585	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2586	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2587	# else
2588	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2589	# endif
2590	PVBOXPD pPDSrc = pVM->pgm.s.CTXSUFF(pGuestPD);
2591
2592	Assert(pPDSrc);
2593	#ifndef IN_GC
2594	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2595	#endif
2596
2597	/*
2598	* Iterate the page directory.
2599	*/
2600	PPGMMAPPING pMapping;
2601	unsigned iPdNoMapping;
2602	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2603	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2604
2605	/* Only check mappings if they are supposed to be put into the shadow page table. */
2606	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2607	{
2608	pMapping = pVM->pgm.s.CTXSUFF(pMappings);
2609	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2610	}
2611	else
2612	{
2613	pMapping = 0;
2614	iPdNoMapping = ~0U;
2615	}
2616
2617	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2618	{
2619	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2620	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2621	# else
2622	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2623	# endif
2624	register VBOXPDE PdeSrc = pPDSrc->a[iPD];
2625	if ( PdeSrc.n.u1Present
2626	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2627	{
2628	/*
2629	* Check for conflicts with GC mappings.
2630	*/
2631	if (iPD == iPdNoMapping)
2632	{
2633	if (pVM->pgm.s.fMappingsFixed)
2634	{
2635	/* It's fixed, just skip the mapping. */
2636	const unsigned cPTs = pMapping->cPTs;
2637	iPD += cPTs - 1;
2638	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2639	pMapping = pMapping->CTXSUFF(pNext);
2640	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2641	continue;
2642	}
2643
2644	#ifdef IN_RING3
2645	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2646	if (VBOX_FAILURE(rc))
2647	return rc;
2648
2649	/*
2650	* Update iPdNoMapping and pMapping.
2651	*/
2652	pMapping = pVM->pgm.s.pMappingsHC;
2653	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2654	pMapping = pMapping->pNextHC;
2655	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2656	#else
2657	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2658	return VINF_PGM_SYNC_CR3;
2659	#endif
2660	}
2661
2662	/*
2663	* Sync page directory entry.
2664	*
2665	* The current approach is to allocated the page table but to set
2666	* the entry to not-present and postpone the page table synching till
2667	* it's actually used.
2668	*/
2669	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2670	const unsigned iPdShw = iPD; NOREF(iPdShw);
2671	# else
2672	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2673	# endif
2674	{
2675	SHWPDE PdeDst = *pPDEDst;
2676	if (PdeDst.n.u1Present)
2677	{
2678	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2679	RTGCPHYS GCPhys;
2680	if ( !PdeSrc.b.u1Size
2681	\|\| !(cr4 & X86_CR4_PSE))
2682	{
2683	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2684	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2685	GCPhys \|= i * (PAGE_SIZE / 2);
2686	# endif
2687	}
2688	else
2689	{
2690	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
2691	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2692	GCPhys \|= i * X86_PAGE_2M_SIZE;
2693	# endif
2694	}
2695
2696	if ( pShwPage->GCPhys == GCPhys
2697	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2698	&& ( pShwPage->fCached
2699	\|\| ( !fGlobal
2700	&& ( false
2701	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2702	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2703	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2704	\|\| ( !pShwPage->fSeenNonGlobal
2705	&& (cr4 & X86_CR4_PGE))
2706	# endif
2707	)
2708	)
2709	)
2710	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2711	\|\| ( (cr4 & X86_CR4_PSE)
2712	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2713	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2714	)
2715	)
2716	{
2717	# ifdef VBOX_WITH_STATISTICS
2718	if ( !fGlobal
2719	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2720	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2721	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2722	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2723	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2724	else
2725	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2726	# endif /* VBOX_WITH_STATISTICS */
2727	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2728	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2729	//# ifdef PGMPOOL_WITH_CACHE
2730	// pgmPoolCacheUsed(pPool, pShwPage);
2731	//# endif
2732	}
2733	else
2734	{
2735	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2736	pPDEDst->u = 0;
2737	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2738	}
2739	}
2740	else
2741	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2742	pPDEDst++;
2743	}
2744	}
2745	else if (iPD != iPdNoMapping)
2746	{
2747	/*
2748	* Check if there is any page directory to mark not present here.
2749	*/
2750	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2751	const unsigned iPdShw = iPD; NOREF(iPdShw);
2752	# else
2753	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2754	# endif
2755	{
2756	if (pPDEDst->n.u1Present)
2757	{
2758	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2759	pPDEDst->u = 0;
2760	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2761	}
2762	pPDEDst++;
2763	}
2764	}
2765	else
2766	{
2767	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2768	const unsigned cPTs = pMapping->cPTs;
2769	if (pVM->pgm.s.fMappingsFixed)
2770	{
2771	/* It's fixed, just skip the mapping. */
2772	pMapping = pMapping->CTXSUFF(pNext);
2773	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2774	}
2775	else
2776	{
2777	/*
2778	* Check for conflicts for subsequent pagetables
2779	* and advance to the next mapping.
2780	*/
2781	iPdNoMapping = ~0U;
2782	unsigned iPT = cPTs;
2783	while (iPT-- > 1)
2784	{
2785	if ( pPDSrc->a[iPD + iPT].n.u1Present
2786	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2787	{
2788	# ifdef IN_RING3
2789	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2790	if (VBOX_FAILURE(rc))
2791	return rc;
2792
2793	/*
2794	* Update iPdNoMapping and pMapping.
2795	*/
2796	pMapping = pVM->pgm.s.CTXSUFF(pMappings);
2797	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2798	pMapping = pMapping->CTXSUFF(pNext);
2799	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2800	break;
2801	# else
2802	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2803	return VINF_PGM_SYNC_CR3;
2804	# endif
2805	}
2806	}
2807	if (iPdNoMapping == ~0U && pMapping)
2808	{
2809	pMapping = pMapping->CTXSUFF(pNext);
2810	if (pMapping)
2811	iPdNoMapping = pMapping->GCPtr >> PGDIR_SHIFT;
2812	}
2813	}
2814	/* advance. */
2815	iPD += cPTs - 1;
2816	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2817	}
2818
2819	} /* for iPD */
2820	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2821	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2822	# endif
2823
2824	return VINF_SUCCESS;
2825
2826	#elif PGM_GST_TYPE == PGM_TYPE_PAE
2827	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2828	//# error not implemented
2829	return VERR_INTERNAL_ERROR;
2830
2831	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2832	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2833	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2834
2835	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2836	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2837	//# error not implemented
2838	return VERR_INTERNAL_ERROR;
2839
2840	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2841	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2842	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2843
2844	#else /* guest real and protected mode */
2845
2846	return VINF_SUCCESS;
2847	#endif
2848	}
2849
2850
2851
2852
2853	#ifdef VBOX_STRICT
2854	#ifdef IN_GC
2855	# undef AssertMsgFailed
2856	# define AssertMsgFailed Log
2857	#endif
2858	#ifdef IN_RING3
2859	# include <VBox/dbgf.h>
2860
2861	/**
2862	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2863	*
2864	* @returns VBox status code (VINF_SUCCESS).
2865	* @param pVM The VM handle.
2866	* @param cr3 The root of the hierarchy.
2867	* @param crr The cr4, only PAE and PSE is currently used.
2868	* @param fLongMode Set if long mode, false if not long mode.
2869	* @param cMaxDepth Number of levels to dump.
2870	* @param pHlp Pointer to the output functions.
2871	*/
2872	__BEGIN_DECLS
2873	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2874	__END_DECLS
2875
2876	#endif
2877
2878	/**
2879	* Checks that the shadow page table is in sync with the guest one.
2880	*
2881	* @returns The number of errors.
2882	* @param pVM The virtual machine.
2883	* @param cr3 Guest context CR3 register
2884	* @param cr4 Guest context CR4 register
2885	* @param GCPtr Where to start. Defaults to 0.
2886	* @param cb How much to check. Defaults to everything.
2887	*/
2888	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2889	{
2890	unsigned cErrors = 0;
2891
2892	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2893
2894	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2895	# error "Invalid shadow mode for 32-bit guest paging."
2896	# endif
2897
2898	PPGM pPGM = &pVM->pgm.s;
2899	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2900	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2901	RTHCPHYS HCPhys; /* general usage. */
2902	int rc;
2903
2904	/*
2905	* Check that the Guest CR3 and all it's mappings are correct.
2906	*/
2907	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & X86_CR3_PAGE_MASK),
2908	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2909	false);
2910	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2911	AssertRCReturn(rc, 1);
2912	rc = PGMRamGCPhys2HCPhys(pPGM, cr3 & X86_CR3_PAGE_MASK, &HCPhys);
2913	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2914	# ifndef IN_GC
2915	RTGCPHYS GCPhys;
2916	rc = PGMPhysHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2917	AssertRCReturn(rc, 1);
2918	AssertMsgReturn((cr3 & X86_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2919	# endif
2920	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2921
2922	/*
2923	* Get and check the Shadow CR3.
2924	*/
2925	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2926	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2927	unsigned cPDEs = ELEMENTS(pPDDst->a);
2928	# else
2929	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2930	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2931	# endif
2932	if (cb != ~(RTGCUINTPTR)0)
2933	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2934
2935	/** @todo call the other two PGMAssert() functions. /
2936
2937	/*
2938	* Iterate the shadow page directory.
2939	*/
2940	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2941	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2942	cPDEs += iPDDst;
2943	for (;
2944	iPDDst < cPDEs;
2945	iPDDst++, GCPtr += _4G / cPDEs)
2946	{
2947	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2948	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2949	{
2950	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2951	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2952	{
2953	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2954	cErrors++;
2955	continue;
2956	}
2957	}
2958	else if ( (PdeDst.u & X86_PDE_P)
2959	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2960	)
2961	{
2962	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2963	PPGMPOOLPAGE pPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2964	if (!pPage)
2965	{
2966	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2967	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2968	cErrors++;
2969	continue;
2970	}
2971	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPage);
2972
2973	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
2974	{
2975	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2976	GCPtr, (uint64_t)PdeDst.u));
2977	cErrors++;
2978	}
2979
2980	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
2981	{
2982	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2983	GCPtr, (uint64_t)PdeDst.u));
2984	cErrors++;
2985	}
2986
2987	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2988	if (!PdeSrc.n.u1Present)
2989	{
2990	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2991	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2992	cErrors++;
2993	continue;
2994	}
2995
2996	if ( !PdeSrc.b.u1Size
2997	\|\| !(cr4 & X86_CR4_PSE))
2998	{
2999	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3000	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3001	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3002	# endif
3003	}
3004	else
3005	{
3006	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3007	{
3008	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3009	GCPtr, (uint64_t)PdeSrc.u));
3010	cErrors++;
3011	continue;
3012	}
3013	GCPhysGst = PdeSrc.u & GST_PDE4M_PG_MASK;
3014	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3015	GCPhysGst \|= GCPtr & BIT(X86_PAGE_2M_SHIFT);
3016	# endif
3017	}
3018
3019	if ( pPage->enmKind
3020	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3021	{
3022	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3023	pPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3024	cErrors++;
3025	}
3026
3027	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3028	if (VBOX_FAILURE(rc))
3029	{
3030	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3031	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3032	cErrors++;
3033	continue;
3034	}
3035
3036	if (GCPhysGst != pPage->GCPhys)
3037	{
3038	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3039	GCPhysGst, pPage->GCPhys, GCPtr));
3040	cErrors++;
3041	continue;
3042	}
3043
3044	if ( !PdeSrc.b.u1Size
3045	\|\| !(cr4 & X86_CR4_PSE))
3046	{
3047	/*
3048	* Page Table.
3049	*/
3050	const GSTPT *pPTSrc;
3051	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3052	if (VBOX_FAILURE(rc))
3053	{
3054	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3055	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3056	cErrors++;
3057	continue;
3058	}
3059	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3060	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3061	{
3062	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3063	// (This problem will go away when/if we shadow multiple CR3s.)
3064	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3065	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3066	cErrors++;
3067	continue;
3068	}
3069	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3070	{
3071	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3072	GCPtr, (uint64_t)PdeDst.u));
3073	cErrors++;
3074	continue;
3075	}
3076
3077	/* iterate the page table. */
3078	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3079	const unsigned offPTSrc = 0;
3080	# else
3081	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3082	# endif
3083	for (unsigned iPT = 0, off = 0;
3084	iPT < ELEMENTS(pPTDst->a);
3085	iPT++, off += PAGE_SIZE)
3086	{
3087	const SHWPTE PteDst = pPTDst->a[iPT];
3088
3089	/* skip not-present entries. */
3090	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3091	continue;
3092	Assert(PteDst.n.u1Present);
3093
3094	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3095	if (!PteSrc.n.u1Present)
3096	{
3097	#ifdef IN_RING3
3098	PGMAssertHandlerAndFlagsInSync(pVM);
3099	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3100	#endif
3101	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3102	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3103	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3104	cErrors++;
3105	continue;
3106	}
3107
3108	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3109	# if 1 /** @todo sync accessed bit properly... */
3110	fIgnoreFlags \|= X86_PTE_A;
3111	# endif
3112
3113	/* match the physical addresses */
3114	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3115	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3116
3117	# ifdef IN_RING3
3118	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3119	if (VBOX_FAILURE(rc))
3120	{
3121	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3122	{
3123	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3124	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3125	cErrors++;
3126	continue;
3127	}
3128	}
3129	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3130	{
3131	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3132	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3133	cErrors++;
3134	continue;
3135	}
3136	# endif
3137
3138	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3139	if (VBOX_FAILURE(rc))
3140	{
3141	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3142	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3143	{
3144	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3145	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3146	cErrors++;
3147	continue;
3148	}
3149	# endif
3150	if (PteDst.n.u1Write)
3151	{
3152	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3153	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3154	cErrors++;
3155	}
3156	fIgnoreFlags \|= X86_PTE_RW;
3157	}
3158	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3159	{
3160	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3161	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3162	cErrors++;
3163	continue;
3164	}
3165
3166	/* flags */
3167	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3168	{
3169	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3170	{
3171	if (PteDst.n.u1Write)
3172	{
3173	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3174	GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3175	cErrors++;
3176	continue;
3177	}
3178	fIgnoreFlags \|= X86_PTE_RW;
3179	}
3180	else
3181	{
3182	if (PteDst.n.u1Present)
3183	{
3184	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3185	GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3186	cErrors++;
3187	continue;
3188	}
3189	fIgnoreFlags \|= X86_PTE_P;
3190	}
3191	}
3192	else
3193	{
3194	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3195	{
3196	if (PteDst.n.u1Write)
3197	{
3198	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3199	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3200	cErrors++;
3201	continue;
3202	}
3203	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3204	{
3205	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3206	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3207	cErrors++;
3208	continue;
3209	}
3210	if (PteDst.n.u1Dirty)
3211	{
3212	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3213	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3214	cErrors++;
3215	}
3216	# if 0 /** @todo sync access bit properly... */
3217	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3218	{
3219	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3220	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3221	cErrors++;
3222	}
3223	fIgnoreFlags \|= X86_PTE_RW;
3224	# else
3225	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3226	# endif
3227	}
3228	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3229	{
3230	/* access bit emulation (not implemented). */
3231	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3232	{
3233	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3234	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3235	cErrors++;
3236	continue;
3237	}
3238	if (!PteDst.n.u1Accessed)
3239	{
3240	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3241	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3242	cErrors++;
3243	}
3244	fIgnoreFlags \|= X86_PTE_P;
3245	}
3246	# ifdef DEBUG_sandervl
3247	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3248	# endif
3249	}
3250
3251	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3252	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3253	)
3254	{
3255	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3256	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3257	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3258	cErrors++;
3259	continue;
3260	}
3261	} /* foreach PTE */
3262	}
3263	else
3264	{
3265	/*
3266	* Big Page.
3267	*/
3268	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| X86_PDE_PAE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3269	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3270	{
3271	if (PdeDst.n.u1Write)
3272	{
3273	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3274	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3275	cErrors++;
3276	continue;
3277	}
3278	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3279	{
3280	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3281	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3282	cErrors++;
3283	continue;
3284	}
3285	# if 0 /** @todo sync access bit properly... */
3286	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3287	{
3288	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3289	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3290	cErrors++;
3291	}
3292	fIgnoreFlags \|= X86_PTE_RW;
3293	# else
3294	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3295	# endif
3296	}
3297	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3298	{
3299	/* access bit emulation (not implemented). */
3300	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3301	{
3302	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3303	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3304	cErrors++;
3305	continue;
3306	}
3307	if (!PdeDst.n.u1Accessed)
3308	{
3309	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3310	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3311	cErrors++;
3312	}
3313	fIgnoreFlags \|= X86_PTE_P;
3314	}
3315
3316	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3317	{
3318	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3319	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3320	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3321	cErrors++;
3322	}
3323
3324	/* iterate the page table. */
3325	for (unsigned iPT = 0, off = 0;
3326	iPT < ELEMENTS(pPTDst->a);
3327	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3328	{
3329	const SHWPTE PteDst = pPTDst->a[iPT];
3330
3331	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3332	{
3333	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3334	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3335	cErrors++;
3336	}
3337
3338	/* skip not-present entries. */
3339	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3340	continue;
3341
3342	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3343
3344	/* match the physical addresses */
3345	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3346
3347	# ifdef IN_RING3
3348	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3349	if (VBOX_FAILURE(rc))
3350	{
3351	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3352	{
3353	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3354	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3355	cErrors++;
3356	}
3357	}
3358	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3359	{
3360	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3361	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3362	cErrors++;
3363	continue;
3364	}
3365	# endif
3366
3367	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3368	if (VBOX_FAILURE(rc))
3369	{
3370	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3371	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3372	{
3373	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3374	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3375	cErrors++;
3376	continue;
3377	}
3378	# endif
3379	if (PteDst.n.u1Write)
3380	{
3381	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3382	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3383	cErrors++;
3384	}
3385	fIgnoreFlags \|= X86_PTE_RW;
3386	}
3387	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3388	{
3389	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3390	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3391	cErrors++;
3392	continue;
3393	}
3394
3395	/* flags */
3396	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3397	{
3398	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3399	{
3400	if (!(HCPhys & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF))
3401	{
3402	if (PteDst.n.u1Write)
3403	{
3404	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3405	GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3406	cErrors++;
3407	continue;
3408	}
3409	fIgnoreFlags \|= X86_PTE_RW;
3410	}
3411	}
3412	else
3413	{
3414	if (PteDst.n.u1Present)
3415	{
3416	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3417	GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3418	cErrors++;
3419	continue;
3420	}
3421	fIgnoreFlags \|= X86_PTE_P;
3422	}
3423	}
3424
3425	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3426	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3427	)
3428	{
3429	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3430	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3431	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3432	cErrors++;
3433	continue;
3434	}
3435	} /* foreach PTE */
3436	}
3437	}
3438	/* not present */
3439
3440	} /* forearch PDE */
3441
3442	# ifdef DEBUG
3443	if (cErrors)
3444	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3445	# endif
3446
3447	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3448	//# error not implemented
3449
3450
3451	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3452	//# error not implemented
3453
3454	/#else: guest real and protected mode /
3455	#endif
3456	return cErrors;
3457	}
3458	#endif /* VBOX_STRICT */
3459

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 2128

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