PGMAllBth.h@ 22337

Last change on this file since 22337 was 22327, checked in by vboxsync, 15 years ago
Disabled rarely useful statistics as they pollute the log
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 196.2 KB

Line
1	/* $Id: PGMAllBth.h 22327 2009-08-18 14:52:08Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	RT_C_DECLS_BEGIN
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	RT_C_DECLS_END
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc = 0; /* initialized to shut up gcc */
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc = 0; /* initialized to shut up gcc */
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
165	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
166	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
167
168	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
169	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
170
171	PX86PDPAE pPDDst;
172	# if PGM_GST_TYPE != PGM_TYPE_PAE
173	X86PDPE PdpeSrc;
174
175	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
176	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
177	# endif
178	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
179	if (rc != VINF_SUCCESS)
180	{
181	AssertRC(rc);
182	return rc;
183	}
184	Assert(pPDDst);
185
186	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
187	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
188	PX86PDPAE pPDDst;
189	# if PGM_GST_TYPE == PGM_TYPE_PROT
190	/* AMD-V nested paging */
191	X86PML4E Pml4eSrc;
192	X86PDPE PdpeSrc;
193	PX86PML4E pPml4eSrc = &Pml4eSrc;
194
195	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
196	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
197	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
198	# endif
199
200	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
201	if (rc != VINF_SUCCESS)
202	{
203	AssertRC(rc);
204	return rc;
205	}
206	Assert(pPDDst);
207
208	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
209	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
210	PEPTPD pPDDst;
211
212	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
213	if (rc != VINF_SUCCESS)
214	{
215	AssertRC(rc);
216	return rc;
217	}
218	Assert(pPDDst);
219	# endif
220
221	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
222	/*
223	* If we successfully correct the write protection fault due to dirty bit
224	* tracking, or this page fault is a genuine one, then return immediately.
225	*/
226	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
227	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
228	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
229	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
230	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
231	{
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
233	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
234	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
235	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
236	}
237
238	# if 0 /* rarely useful; leave for debugging. */
239	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
240	# endif
241	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
242
243	/*
244	* A common case is the not-present error caused by lazy page table syncing.
245	*
246	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
247	* so we can safely assume that the shadow PT is present when calling SyncPage later.
248	*
249	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
250	* of mapping conflict and defer to SyncCR3 in R3.
251	* (Again, we do NOT support access handlers for non-present guest pages.)
252	*
253	*/
254	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
255	&& !pPDDst->a[iPDDst].n.u1Present
256	&& PdeSrc.n.u1Present
257	)
258	{
259	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
260	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
261	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
263	if (RT_SUCCESS(rc))
264	{
265	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
266	return rc;
267	}
268	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
269	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return VINF_PGM_SYNC_CR3;
272	}
273
274	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
275	/*
276	* Check if this address is within any of our mappings.
277	*
278	* This is very fast and it's gonna save us a bit of effort below and prevent
279	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
280	* (BTW, it's impossible to have physical access handlers in a mapping.)
281	*/
282	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
283	{
284	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
285	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
286	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
287	{
288	if (pvFault < pMapping->GCPtr)
289	break;
290	if (pvFault - pMapping->GCPtr < pMapping->cb)
291	{
292	/*
293	* The first thing we check is if we've got an undetected conflict.
294	*/
295	if (!pVM->pgm.s.fMappingsFixed)
296	{
297	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
298	while (iPT-- > 0)
299	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
300	{
301	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
302	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
303	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
304	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
305	return VINF_PGM_SYNC_CR3;
306	}
307	}
308
309	/*
310	* Check if the fault address is in a virtual page access handler range.
311	*/
312	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
313	if ( pCur
314	&& pvFault - pCur->Core.Key < pCur->cb
315	&& uErr & X86_TRAP_PF_RW)
316	{
317	# ifdef IN_RC
318	STAM_PROFILE_START(&pCur->Stat, h);
319	pgmUnlock(pVM);
320	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
321	pgmLock(pVM);
322	STAM_PROFILE_STOP(&pCur->Stat, h);
323	# else
324	AssertFailed();
325	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
326	# endif
327	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
328	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
329	return rc;
330	}
331
332	/*
333	* Pretend we're not here and let the guest handle the trap.
334	*/
335	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
336	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
337	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
338	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
339	return VINF_EM_RAW_GUEST_TRAP;
340	}
341	}
342	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
343	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
344	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
345
346	/*
347	* Check if this fault address is flagged for special treatment,
348	* which means we'll have to figure out the physical address and
349	* check flags associated with it.
350	*
351	* ASSUME that we can limit any special access handling to pages
352	* in page tables which the guest believes to be present.
353	*/
354	if (PdeSrc.n.u1Present)
355	{
356	RTGCPHYS GCPhys = NIL_RTGCPHYS;
357
358	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
359	# if PGM_GST_TYPE == PGM_TYPE_AMD64
360	bool fBigPagesSupported = true;
361	# else
362	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
363	# endif
364	if ( PdeSrc.b.u1Size
365	&& fBigPagesSupported)
366	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
367	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
368	else
369	{
370	PGSTPT pPTSrc;
371	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
372	if (RT_SUCCESS(rc))
373	{
374	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
375	if (pPTSrc->a[iPTESrc].n.u1Present)
376	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
377	}
378	}
379	# else
380	/* No paging so the fault address is the physical address */
381	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
382	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
383
384	/*
385	* If we have a GC address we'll check if it has any flags set.
386	*/
387	if (GCPhys != NIL_RTGCPHYS)
388	{
389	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
390
391	PPGMPAGE pPage;
392	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
393	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
394	{
395	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
396	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
397	{
398	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
399	{
400	/*
401	* Physical page access handler.
402	*/
403	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
404	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
405	if (pCur)
406	{
407	# ifdef PGM_SYNC_N_PAGES
408	/*
409	* If the region is write protected and we got a page not present fault, then sync
410	* the pages. If the fault was caused by a read, then restart the instruction.
411	* In case of write access continue to the GC write handler.
412	*
413	* ASSUMES that there is only one handler per page or that they have similar write properties.
414	*/
415	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
416	&& !(uErr & X86_TRAP_PF_P))
417	{
418	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
419	if ( RT_FAILURE(rc)
420	\|\| !(uErr & X86_TRAP_PF_RW)
421	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
422	{
423	AssertRC(rc);
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
425	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
426	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
427	return rc;
428	}
429	}
430	# endif
431
432	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
433	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
434	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
435
436	# if defined(IN_RC) \|\| defined(IN_RING0)
437	if (pCur->CTX_SUFF(pfnHandler))
438	{
439	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
440	# ifdef IN_RING0
441	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
442	# else
443	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
444	# endif
445	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
446	void *pvUser = pCur->CTX_SUFF(pvUser);
447
448	STAM_PROFILE_START(&pCur->Stat, h);
449	if (fLeaveLock)
450	pgmUnlock(pVM); /* @todo: Not entirely safe. */
451
452	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
453	if (fLeaveLock)
454	pgmLock(pVM);
455	# ifdef VBOX_WITH_STATISTICS
456	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
457	if (pCur)
458	STAM_PROFILE_STOP(&pCur->Stat, h);
459	# else
460	pCur = NULL; /* might be invalid by now. */
461	# endif
462
463	}
464	else
465	# endif
466	rc = VINF_EM_RAW_EMULATE_INSTR;
467
468	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
469	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
470	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
471	return rc;
472	}
473	}
474	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
475	else
476	{
477	# ifdef PGM_SYNC_N_PAGES
478	/*
479	* If the region is write protected and we got a page not present fault, then sync
480	* the pages. If the fault was caused by a read, then restart the instruction.
481	* In case of write access continue to the GC write handler.
482	*/
483	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
484	&& !(uErr & X86_TRAP_PF_P))
485	{
486	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
487	if ( RT_FAILURE(rc)
488	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
489	\|\| !(uErr & X86_TRAP_PF_RW))
490	{
491	AssertRC(rc);
492	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
493	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
494	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
495	return rc;
496	}
497	}
498	# endif
499	/*
500	* Ok, it's an virtual page access handler.
501	*
502	* Since it's faster to search by address, we'll do that first
503	* and then retry by GCPhys if that fails.
504	*/
505	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
506	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
507	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
508	*/
509	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
510	if (pCur)
511	{
512	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
513	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
514	\|\| !(uErr & X86_TRAP_PF_P)
515	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
516	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
517
518	if ( pvFault - pCur->Core.Key < pCur->cb
519	&& ( uErr & X86_TRAP_PF_RW
520	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
521	{
522	# ifdef IN_RC
523	STAM_PROFILE_START(&pCur->Stat, h);
524	pgmUnlock(pVM);
525	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
526	pgmLock(pVM);
527	STAM_PROFILE_STOP(&pCur->Stat, h);
528	# else
529	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
530	# endif
531	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
532	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
533	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
534	return rc;
535	}
536	/* Unhandled part of a monitored page */
537	}
538	else
539	{
540	/* Check by physical address. */
541	PPGMVIRTHANDLER pCur;
542	unsigned iPage;
543	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
544	&pCur, &iPage);
545	Assert(RT_SUCCESS(rc) \|\| !pCur);
546	if ( pCur
547	&& ( uErr & X86_TRAP_PF_RW
548	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
549	{
550	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
551	# ifdef IN_RC
552	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
553	Assert(off < pCur->cb);
554	STAM_PROFILE_START(&pCur->Stat, h);
555	pgmUnlock(pVM);
556	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
557	pgmLock(pVM);
558	STAM_PROFILE_STOP(&pCur->Stat, h);
559	# else
560	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
561	# endif
562	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
563	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
564	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
565	return rc;
566	}
567	}
568	}
569	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
570
571	/*
572	* There is a handled area of the page, but this fault doesn't belong to it.
573	* We must emulate the instruction.
574	*
575	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
576	* we first check if this was a page-not-present fault for a page with only
577	* write access handlers. Restart the instruction if it wasn't a write access.
578	*/
579	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
580
581	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
582	&& !(uErr & X86_TRAP_PF_P))
583	{
584	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
585	if ( RT_FAILURE(rc)
586	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
587	\|\| !(uErr & X86_TRAP_PF_RW))
588	{
589	AssertRC(rc);
590	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
591	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
592	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
593	return rc;
594	}
595	}
596
597	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
598	* It's writing to an unhandled part of the LDT page several million times.
599	*/
600	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
601	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
602	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
603	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
604	return rc;
605	} /* if any kind of handler */
606
607	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
608	if (uErr & X86_TRAP_PF_P)
609	{
610	/*
611	* The page isn't marked, but it might still be monitored by a virtual page access handler.
612	* (ASSUMES no temporary disabling of virtual handlers.)
613	*/
614	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
615	* we should correct both the shadow page table and physical memory flags, and not only check for
616	* accesses within the handler region but for access to pages with virtual handlers. */
617	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
618	if (pCur)
619	{
620	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
621	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
622	\|\| !(uErr & X86_TRAP_PF_P)
623	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
624	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
625
626	if ( pvFault - pCur->Core.Key < pCur->cb
627	&& ( uErr & X86_TRAP_PF_RW
628	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
629	{
630	# ifdef IN_RC
631	STAM_PROFILE_START(&pCur->Stat, h);
632	pgmUnlock(pVM);
633	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
634	pgmLock(pVM);
635	STAM_PROFILE_STOP(&pCur->Stat, h);
636	# else
637	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
638	# endif
639	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
640	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
641	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
642	return rc;
643	}
644	}
645	}
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647	}
648	else
649	{
650	/*
651	* When the guest accesses invalid physical memory (e.g. probing
652	* of RAM or accessing a remapped MMIO range), then we'll fall
653	* back to the recompiler to emulate the instruction.
654	*/
655	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
656	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
657	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
658	return VINF_EM_RAW_EMULATE_INSTR;
659	}
660
661	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
662
663	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
664	/*
665	* We are here only if page is present in Guest page tables and
666	* trap is not handled by our handlers.
667	*
668	* Check it for page out-of-sync situation.
669	*/
670	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
671
672	if (!(uErr & X86_TRAP_PF_P))
673	{
674	/*
675	* Page is not present in our page tables.
676	* Try to sync it!
677	* BTW, fPageShw is invalid in this branch!
678	*/
679	if (uErr & X86_TRAP_PF_US)
680	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
681	else /* supervisor */
682	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
683
684	# if defined(LOG_ENABLED) && !defined(IN_RING0)
685	RTGCPHYS GCPhys;
686	uint64_t fPageGst;
687	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
688	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
689	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
690	# endif /* LOG_ENABLED */
691
692	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
693	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
694	{
695	uint64_t fPageGst;
696	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
697	if ( RT_SUCCESS(rc)
698	&& !(fPageGst & X86_PTE_US))
699	{
700	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
701	if ( pvFault == (RTGCPTR)pRegFrame->eip
702	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
703	# ifdef CSAM_DETECT_NEW_CODE_PAGES
704	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
705	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
706	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
707	)
708	{
709	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
710	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
711	if (rc != VINF_SUCCESS)
712	{
713	/*
714	* CSAM needs to perform a job in ring 3.
715	*
716	* Sync the page before going to the host context; otherwise we'll end up in a loop if
717	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
718	*/
719	LogFlow(("CSAM ring 3 job\n"));
720	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
721	AssertRC(rc2);
722
723	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
724	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
725	return rc;
726	}
727	}
728	# ifdef CSAM_DETECT_NEW_CODE_PAGES
729	else if ( uErr == X86_TRAP_PF_RW
730	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
731	&& pRegFrame->ecx < 0x10000)
732	{
733	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
734	* to detect loading of new code pages.
735	*/
736
737	/*
738	* Decode the instruction.
739	*/
740	RTGCPTR PC;
741	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
742	if (rc == VINF_SUCCESS)
743	{
744	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
745	uint32_t cbOp;
746	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
747
748	/* For now we'll restrict this to rep movsw/d instructions */
749	if ( rc == VINF_SUCCESS
750	&& pDis->pCurInstr->opcode == OP_MOVSWD
751	&& (pDis->prefix & PREFIX_REP))
752	{
753	CSAMMarkPossibleCodePage(pVM, pvFault);
754	}
755	}
756	}
757	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
758
759	/*
760	* Mark this page as safe.
761	*/
762	/** @todo not correct for pages that contain both code and data!! */
763	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
764	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
765	}
766	}
767	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
768	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
769	if (RT_SUCCESS(rc))
770	{
771	/* The page was successfully synced, return to the guest. */
772	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
773	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
774	return VINF_SUCCESS;
775	}
776	}
777	else /* uErr & X86_TRAP_PF_P: */
778	{
779	/*
780	* Write protected pages are make writable when the guest makes the first
781	* write to it. This happens for pages that are shared, write monitored
782	* and not yet allocated.
783	*
784	* Also, a side effect of not flushing global PDEs are out of sync pages due
785	* to physical monitored regions, that are no longer valid.
786	* Assume for now it only applies to the read/write flag.
787	*/
788	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
789	{
790	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
791	{
792	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
793	GCPhys, pPage, pvFault, uErr));
794	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
795	if (rc != VINF_SUCCESS)
796	{
797	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
798	return rc;
799	}
800	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
801	return VINF_EM_NO_MEMORY;
802	}
803
804	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
805	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
806	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
807	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG))
808	{
809	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
810	uint64_t fPageGst;
811	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
812	if ( RT_SUCCESS(rc)
813	&& !(fPageGst & X86_PTE_RW))
814	{
815	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
816	if (RT_SUCCESS(rc))
817	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
818	else
819	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
820	return rc;
821	}
822	AssertMsg(RT_SUCCESS(rc), ("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
823	}
824	# endif
825	/// @todo count the above case; else
826	if (uErr & X86_TRAP_PF_US)
827	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
828	else /* supervisor */
829	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
830
831	/*
832	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
833	* page is not present, which is not true in this case.
834	*/
835	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
836	if (RT_SUCCESS(rc))
837	{
838	/*
839	* Page was successfully synced, return to guest.
840	*/
841	# ifdef VBOX_STRICT
842	RTGCPHYS GCPhys;
843	uint64_t fPageGst;
844	if (!HWACCMIsNestedPagingActive(pVM))
845	{
846	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
847	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
848	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
849	}
850	uint64_t fPageShw;
851	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
852	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCPUs > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
853	# endif /* VBOX_STRICT */
854	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
855	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
856	return VINF_SUCCESS;
857	}
858	}
859
860	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
861	# ifdef VBOX_STRICT
862	/*
863	* Check for VMM page flags vs. Guest page flags consistency.
864	* Currently only for debug purposes.
865	*/
866	if (RT_SUCCESS(rc))
867	{
868	/* Get guest page flags. */
869	uint64_t fPageGst;
870	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
871	if (RT_SUCCESS(rc))
872	{
873	uint64_t fPageShw;
874	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
875
876	/*
877	* Compare page flags.
878	* Note: we have AVL, A, D bits desynched.
879	*/
880	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
881	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
882	}
883	else
884	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
885	}
886	else
887	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
888	# endif /* VBOX_STRICT */
889	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
890	}
891	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
892	# endif /* PGM_OUT_OF_SYNC_IN_GC */
893	}
894	else /* GCPhys == NIL_RTGCPHYS */
895	{
896	/*
897	* Page not present in Guest OS or invalid page table address.
898	* This is potential virtual page access handler food.
899	*
900	* For the present we'll say that our access handlers don't
901	* work for this case - we've already discarded the page table
902	* not present case which is identical to this.
903	*
904	* When we perchance find we need this, we will probably have AVL
905	* trees (offset based) to operate on and we can measure their speed
906	* agains mapping a page table and probably rearrange this handling
907	* a bit. (Like, searching virtual ranges before checking the
908	* physical address.)
909	*/
910	}
911	}
912	/* else: !present (guest) */
913
914
915	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
916	/*
917	* Conclusion, this is a guest trap.
918	*/
919	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
920	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
921	return VINF_EM_RAW_GUEST_TRAP;
922	# else
923	/* present, but not a monitored page; perhaps the guest is probing physical memory */
924	return VINF_EM_RAW_EMULATE_INSTR;
925	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
926
927
928	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
929
930	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
931	return VERR_INTERNAL_ERROR;
932	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
933	}
934	#endif /* !IN_RING3 */
935
936
937	/**
938	* Emulation of the invlpg instruction.
939	*
940	*
941	* @returns VBox status code.
942	*
943	* @param pVCpu The VMCPU handle.
944	* @param GCPtrPage Page to invalidate.
945	*
946	* @remark ASSUMES that the guest is updating before invalidating. This order
947	* isn't required by the CPU, so this is speculative and could cause
948	* trouble.
949	* @remark No TLB shootdown is done on any other VCPU as we assume that
950	* invlpg emulation is the only reason for calling this function.
951	* (The guest has to shoot down TLB entries on other CPUs itself)
952	* Currently true, but keep in mind!
953	*
954	* @todo Flush page or page directory only if necessary!
955	* @todo Add a #define for simply invalidating the page.
956	*/
957	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
958	{
959	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
960	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
961	&& PGM_SHW_TYPE != PGM_TYPE_EPT
962	int rc;
963	PVM pVM = pVCpu->CTX_SUFF(pVM);
964	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
965
966	Assert(PGMIsLockOwner(pVM));
967
968	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
969	/*
970	* Get the shadow PD entry and skip out if this PD isn't present.
971	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
972	*/
973	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
974	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
975	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
976
977	/* Fetch the pgm pool shadow descriptor. */
978	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
979	Assert(pShwPde);
980
981	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
982	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
983	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
984
985	/* If the shadow PDPE isn't present, then skip the invalidate. */
986	if (!pPdptDst->a[iPdpt].n.u1Present)
987	{
988	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
990	return VINF_SUCCESS;
991	}
992
993	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
994	PPGMPOOLPAGE pShwPde = NULL;
995	PX86PDPAE pPDDst;
996
997	/* Fetch the pgm pool shadow descriptor. */
998	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
999	AssertRCSuccessReturn(rc, rc);
1000	Assert(pShwPde);
1001
1002	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1003	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1004
1005	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1006	/* PML4 */
1007	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1008	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1009	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1010	PX86PDPAE pPDDst;
1011	PX86PDPT pPdptDst;
1012	PX86PML4E pPml4eDst;
1013	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1014	if (rc != VINF_SUCCESS)
1015	{
1016	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1017	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1018	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1019	PGM_INVL_VCPU_TLBS(pVCpu);
1020	return VINF_SUCCESS;
1021	}
1022	Assert(pPDDst);
1023
1024	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1025	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1026
1027	if (!pPdpeDst->n.u1Present)
1028	{
1029	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1030	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1031	PGM_INVL_VCPU_TLBS(pVCpu);
1032	return VINF_SUCCESS;
1033	}
1034
1035	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1036
1037	const SHWPDE PdeDst = *pPdeDst;
1038	if (!PdeDst.n.u1Present)
1039	{
1040	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1041	return VINF_SUCCESS;
1042	}
1043
1044	# if defined(IN_RC)
1045	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1046	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1047	# endif
1048
1049	/*
1050	* Get the guest PD entry and calc big page.
1051	*/
1052	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1053	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1054	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1055	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1056	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1057	unsigned iPDSrc = 0;
1058	# if PGM_GST_TYPE == PGM_TYPE_PAE
1059	X86PDPE PdpeSrc;
1060	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1061	# else /* AMD64 */
1062	PX86PML4E pPml4eSrc;
1063	X86PDPE PdpeSrc;
1064	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1065	# endif
1066	GSTPDE PdeSrc;
1067
1068	if (pPDSrc)
1069	PdeSrc = pPDSrc->a[iPDSrc];
1070	else
1071	PdeSrc.u = 0;
1072	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1073
1074	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1075	const bool fIsBigPage = PdeSrc.b.u1Size;
1076	# else
1077	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1078	# endif
1079
1080	# ifdef IN_RING3
1081	/*
1082	* If a CR3 Sync is pending we may ignore the invalidate page operation
1083	* depending on the kind of sync and if it's a global page or not.
1084	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1085	*/
1086	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1087	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1088	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1089	&& fIsBigPage
1090	&& PdeSrc.b.u1Global
1091	)
1092	)
1093	# else
1094	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1095	# endif
1096	{
1097	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1098	return VINF_SUCCESS;
1099	}
1100	# endif /* IN_RING3 */
1101
1102	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1103	/* Fetch the pgm pool shadow descriptor. */
1104	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1105	Assert(pShwPdpt);
1106
1107	/* Fetch the pgm pool shadow descriptor. */
1108	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1109	Assert(pShwPde);
1110
1111	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1112	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1113
1114	if ( !pPml4eSrc->n.u1Present
1115	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1116	{
1117	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1118	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1119	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1120	ASMAtomicWriteSize(pPml4eDst, 0);
1121	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1122	PGM_INVL_VCPU_TLBS(pVCpu);
1123	return VINF_SUCCESS;
1124	}
1125	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1126	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1127	{
1128	/*
1129	* Mark not present so we can resync the PML4E when it's used.
1130	*/
1131	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1132	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1133	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1134	ASMAtomicWriteSize(pPml4eDst, 0);
1135	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1136	PGM_INVL_VCPU_TLBS(pVCpu);
1137	}
1138	else if (!pPml4eSrc->n.u1Accessed)
1139	{
1140	/*
1141	* Mark not present so we can set the accessed bit.
1142	*/
1143	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1144	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1145	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1146	ASMAtomicWriteSize(pPml4eDst, 0);
1147	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1148	PGM_INVL_VCPU_TLBS(pVCpu);
1149	}
1150
1151	/* Check if the PDPT entry has changed. */
1152	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1153	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1154	if ( !PdpeSrc.n.u1Present
1155	\|\| pShwPde->GCPhys != GCPhysPd)
1156	{
1157	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1158	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1159	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1160	ASMAtomicWriteSize(pPdpeDst, 0);
1161	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1162	PGM_INVL_VCPU_TLBS(pVCpu);
1163	return VINF_SUCCESS;
1164	}
1165	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1166	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1167	{
1168	/*
1169	* Mark not present so we can resync the PDPTE when it's used.
1170	*/
1171	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1172	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1173	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1174	ASMAtomicWriteSize(pPdpeDst, 0);
1175	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1176	PGM_INVL_VCPU_TLBS(pVCpu);
1177	}
1178	else if (!PdpeSrc.lm.u1Accessed)
1179	{
1180	/*
1181	* Mark not present so we can set the accessed bit.
1182	*/
1183	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1184	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1185	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1186	ASMAtomicWriteSize(pPdpeDst, 0);
1187	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1188	PGM_INVL_VCPU_TLBS(pVCpu);
1189	}
1190	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1191
1192	/*
1193	* Deal with the Guest PDE.
1194	*/
1195	rc = VINF_SUCCESS;
1196	if (PdeSrc.n.u1Present)
1197	{
1198	# ifndef PGM_WITHOUT_MAPPING
1199	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1200	{
1201	/*
1202	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1203	*/
1204	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1205	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1206	pgmLock(pVM);
1207	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1208	pgmUnlock(pVM);
1209	}
1210	else
1211	# endif /* !PGM_WITHOUT_MAPPING */
1212	if ( PdeSrc.n.u1User != PdeDst.n.u1User
1213	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1214	{
1215	/*
1216	* Mark not present so we can resync the PDE when it's used.
1217	*/
1218	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1219	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1220	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1221	ASMAtomicWriteSize(pPdeDst, 0);
1222	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1223	PGM_INVL_VCPU_TLBS(pVCpu);
1224	}
1225	else if (!PdeSrc.n.u1Accessed)
1226	{
1227	/*
1228	* Mark not present so we can set the accessed bit.
1229	*/
1230	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1231	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1232	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1233	ASMAtomicWriteSize(pPdeDst, 0);
1234	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1235	PGM_INVL_VCPU_TLBS(pVCpu);
1236	}
1237	else if (!fIsBigPage)
1238	{
1239	/*
1240	* 4KB - page.
1241	*/
1242	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1243	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1244	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1245	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1246	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1247	# endif
1248	if (pShwPage->GCPhys == GCPhys)
1249	{
1250	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1251	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1252	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1253	if (pPT->a[iPTEDst].n.u1Present)
1254	{
1255	# ifdef PGMPOOL_WITH_USER_TRACKING
1256	/* This is very unlikely with caching/monitoring enabled. */
1257	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1258	# endif
1259	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1260	}
1261	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1262	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1263	if (RT_SUCCESS(rc))
1264	rc = VINF_SUCCESS;
1265	# endif
1266	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1267	PGM_INVL_PG(pVCpu, GCPtrPage);
1268	}
1269	else
1270	{
1271	/*
1272	* The page table address changed.
1273	*/
1274	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1275	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1276	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1277	ASMAtomicWriteSize(pPdeDst, 0);
1278	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1279	PGM_INVL_VCPU_TLBS(pVCpu);
1280	}
1281	}
1282	else
1283	{
1284	/*
1285	* 2/4MB - page.
1286	*/
1287	/* Before freeing the page, check if anything really changed. */
1288	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1289	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1290	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1291	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1292	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1293	# endif
1294	if ( pShwPage->GCPhys == GCPhys
1295	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1296	{
1297	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1298	/** @todo PAT */
1299	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1300	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1301	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1302	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1303	{
1304	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1305	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1306	# if defined(IN_RC)
1307	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1308	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1309	# endif
1310	return VINF_SUCCESS;
1311	}
1312	}
1313
1314	/*
1315	* Ok, the page table is present and it's been changed in the guest.
1316	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1317	* We could do this for some flushes in GC too, but we need an algorithm for
1318	* deciding which 4MB pages containing code likely to be executed very soon.
1319	*/
1320	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1321	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1322	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1323	ASMAtomicWriteSize(pPdeDst, 0);
1324	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1325	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1326	}
1327	}
1328	else
1329	{
1330	/*
1331	* Page directory is not present, mark shadow PDE not present.
1332	*/
1333	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1334	{
1335	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1336	ASMAtomicWriteSize(pPdeDst, 0);
1337	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1338	PGM_INVL_PG(pVCpu, GCPtrPage);
1339	}
1340	else
1341	{
1342	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1343	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1344	}
1345	}
1346	# if defined(IN_RC)
1347	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1348	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1349	# endif
1350	return rc;
1351
1352	#else /* guest real and protected mode */
1353	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1354	return VINF_SUCCESS;
1355	#endif
1356	}
1357
1358
1359	#ifdef PGMPOOL_WITH_USER_TRACKING
1360	/**
1361	* Update the tracking of shadowed pages.
1362	*
1363	* @param pVCpu The VMCPU handle.
1364	* @param pShwPage The shadow page.
1365	* @param HCPhys The physical page we is being dereferenced.
1366	*/
1367	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1368	{
1369	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1370	PVM pVM = pVCpu->CTX_SUFF(pVM);
1371
1372	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1373	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1374
1375	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1376	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1377	* 2. write protect all shadowed pages. I.e. implement caching.
1378	*/
1379	/*
1380	* Find the guest address.
1381	*/
1382	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1383	pRam;
1384	pRam = pRam->CTX_SUFF(pNext))
1385	{
1386	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1387	while (iPage-- > 0)
1388	{
1389	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1390	{
1391	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1392	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1393	pShwPage->cPresent--;
1394	pPool->cPresent--;
1395	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1396	return;
1397	}
1398	}
1399	}
1400
1401	for (;;)
1402	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1403	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1404	pShwPage->cPresent--;
1405	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1406	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1407	}
1408
1409
1410	/**
1411	* Update the tracking of shadowed pages.
1412	*
1413	* @param pVCpu The VMCPU handle.
1414	* @param pShwPage The shadow page.
1415	* @param u16 The top 16-bit of the pPage->HCPhys.
1416	* @param pPage Pointer to the guest page. this will be modified.
1417	* @param iPTDst The index into the shadow table.
1418	*/
1419	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1420	{
1421	PVM pVM = pVCpu->CTX_SUFF(pVM);
1422	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1423	/*
1424	* Just deal with the simple first time here.
1425	*/
1426	if (!u16)
1427	{
1428	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1429	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1430	}
1431	else
1432	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1433
1434	/* write back */
1435	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1436	PGM_PAGE_SET_TRACKING(pPage, u16);
1437
1438	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1439
1440	/* update statistics. */
1441	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1442	pShwPage->cPresent++;
1443	if (pShwPage->iFirstPresent > iPTDst)
1444	pShwPage->iFirstPresent = iPTDst;
1445	}
1446	#endif /* PGMPOOL_WITH_USER_TRACKING */
1447
1448
1449	/**
1450	* Creates a 4K shadow page for a guest page.
1451	*
1452	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1453	* physical address. The PdeSrc argument only the flags are used. No page structured
1454	* will be mapped in this function.
1455	*
1456	* @param pVCpu The VMCPU handle.
1457	* @param pPteDst Destination page table entry.
1458	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1459	* Can safely assume that only the flags are being used.
1460	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1461	* @param pShwPage Pointer to the shadow page.
1462	* @param iPTDst The index into the shadow table.
1463	*
1464	* @remark Not used for 2/4MB pages!
1465	*/
1466	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1467	{
1468	if (PteSrc.n.u1Present)
1469	{
1470	PVM pVM = pVCpu->CTX_SUFF(pVM);
1471
1472	/*
1473	* Find the ram range.
1474	*/
1475	PPGMPAGE pPage;
1476	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1477	if (RT_SUCCESS(rc))
1478	{
1479	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1480	/* Try make the page writable if necessary. */
1481	if ( PteSrc.n.u1Write
1482	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1483	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1484	{
1485	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1486	AssertRC(rc);
1487	}
1488	#endif
1489
1490	/** @todo investiage PWT, PCD and PAT. */
1491	/*
1492	* Make page table entry.
1493	*/
1494	SHWPTE PteDst;
1495	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1496	{
1497	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1498	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1499	{
1500	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1501	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1502	PteDst.n.u1Present = 1;
1503	PteDst.n.u1Execute = 1;
1504	PteDst.n.u1IgnorePAT = 1;
1505	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1506	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1507	#else
1508	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1509	\| PGM_PAGE_GET_HCPHYS(pPage);
1510	#endif
1511	}
1512	else
1513	{
1514	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1515	PteDst.u = 0;
1516	}
1517	/** @todo count these two kinds. */
1518	}
1519	else
1520	{
1521	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1522	/*
1523	* If the page or page directory entry is not marked accessed,
1524	* we mark the page not present.
1525	*/
1526	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1527	{
1528	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1530	PteDst.u = 0;
1531	}
1532	else
1533	/*
1534	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1535	* when the page is modified.
1536	*/
1537	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1538	{
1539	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1540	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1541	\| PGM_PAGE_GET_HCPHYS(pPage)
1542	\| PGM_PTFLAGS_TRACK_DIRTY;
1543	}
1544	else
1545	#endif
1546	{
1547	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1548	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1549	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1550	PteDst.n.u1Present = 1;
1551	PteDst.n.u1Write = 1;
1552	PteDst.n.u1Execute = 1;
1553	PteDst.n.u1IgnorePAT = 1;
1554	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1555	/* PteDst.n.u1Size = 0 */
1556	#else
1557	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1558	\| PGM_PAGE_GET_HCPHYS(pPage);
1559	#endif
1560	}
1561	}
1562
1563	/*
1564	* Make sure only allocated pages are mapped writable.
1565	*/
1566	if ( PteDst.n.u1Write
1567	&& PteDst.n.u1Present
1568	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1569	{
1570	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1571	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1572	}
1573
1574	#ifdef PGMPOOL_WITH_USER_TRACKING
1575	/*
1576	* Keep user track up to date.
1577	*/
1578	if (PteDst.n.u1Present)
1579	{
1580	if (!pPteDst->n.u1Present)
1581	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1582	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1583	{
1584	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1585	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1586	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1587	}
1588	}
1589	else if (pPteDst->n.u1Present)
1590	{
1591	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1592	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1593	}
1594	#endif /* PGMPOOL_WITH_USER_TRACKING */
1595
1596	/*
1597	* Update statistics and commit the entry.
1598	*/
1599	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1600	if (!PteSrc.n.u1Global)
1601	pShwPage->fSeenNonGlobal = true;
1602	#endif
1603	ASMAtomicWriteSize(pPteDst, PteDst.u);
1604	}
1605	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1606	/** @todo count these. */
1607	}
1608	else
1609	{
1610	/*
1611	* Page not-present.
1612	*/
1613	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1614	#ifdef PGMPOOL_WITH_USER_TRACKING
1615	/* Keep user track up to date. */
1616	if (pPteDst->n.u1Present)
1617	{
1618	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1619	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1620	}
1621	#endif /* PGMPOOL_WITH_USER_TRACKING */
1622	ASMAtomicWriteSize(pPteDst, 0);
1623	/** @todo count these. */
1624	}
1625	}
1626
1627
1628	/**
1629	* Syncs a guest OS page.
1630	*
1631	* There are no conflicts at this point, neither is there any need for
1632	* page table allocations.
1633	*
1634	* @returns VBox status code.
1635	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1636	* @param pVCpu The VMCPU handle.
1637	* @param PdeSrc Page directory entry of the guest.
1638	* @param GCPtrPage Guest context page address.
1639	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1640	* @param uErr Fault error (X86_TRAP_PF_*).
1641	*/
1642	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1643	{
1644	PVM pVM = pVCpu->CTX_SUFF(pVM);
1645	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1646	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1647
1648	Assert(PGMIsLockOwner(pVM));
1649
1650	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1651	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1652	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1653	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1654	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1655
1656	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1657	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1658	# endif
1659
1660	/*
1661	* Assert preconditions.
1662	*/
1663	Assert(PdeSrc.n.u1Present);
1664	Assert(cPages);
1665	# if 0 /* rarely useful; leave for debugging. */
1666	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1667	# endif
1668
1669	/*
1670	* Get the shadow PDE, find the shadow page table in the pool.
1671	*/
1672	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1673	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1674	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1675
1676	/* Fetch the pgm pool shadow descriptor. */
1677	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1678	Assert(pShwPde);
1679
1680	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1681	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1682	PPGMPOOLPAGE pShwPde = NULL;
1683	PX86PDPAE pPDDst;
1684
1685	/* Fetch the pgm pool shadow descriptor. */
1686	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1687	AssertRCSuccessReturn(rc, rc);
1688	Assert(pShwPde);
1689
1690	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1691	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1692
1693	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1694	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1695	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1696	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1697	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1698
1699	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1700	AssertRCSuccessReturn(rc, rc);
1701	Assert(pPDDst && pPdptDst);
1702	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1703	# endif
1704	SHWPDE PdeDst = *pPdeDst;
1705	if (!PdeDst.n.u1Present)
1706	{
1707	AssertMsg(pVM->cCPUs > 1, ("%Unexpected missing PDE p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1708	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1709	return VINF_SUCCESS; /* force the instruction to be executed again. */
1710	}
1711
1712	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1713
1714	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1715	/* Fetch the pgm pool shadow descriptor. */
1716	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1717	Assert(pShwPde);
1718	# endif
1719
1720	# if defined(IN_RC)
1721	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1722	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1723	# endif
1724
1725	/*
1726	* Check that the page is present and that the shadow PDE isn't out of sync.
1727	*/
1728	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1729	const bool fBigPage = PdeSrc.b.u1Size;
1730	# else
1731	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1732	# endif
1733	RTGCPHYS GCPhys;
1734	if (!fBigPage)
1735	{
1736	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1737	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1738	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1739	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1740	# endif
1741	}
1742	else
1743	{
1744	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1745	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1746	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1747	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1748	# endif
1749	}
1750	if ( pShwPage->GCPhys == GCPhys
1751	&& PdeSrc.n.u1Present
1752	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1753	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1754	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1755	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1756	# endif
1757	)
1758	{
1759	/*
1760	* Check that the PDE is marked accessed already.
1761	* Since we set the accessed bit before getting here on a #PF, this
1762	* check is only meant for dealing with non-#PF'ing paths.
1763	*/
1764	if (PdeSrc.n.u1Accessed)
1765	{
1766	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1767	if (!fBigPage)
1768	{
1769	/*
1770	* 4KB Page - Map the guest page table.
1771	*/
1772	PGSTPT pPTSrc;
1773	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1774	if (RT_SUCCESS(rc))
1775	{
1776	# ifdef PGM_SYNC_N_PAGES
1777	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1778	if ( cPages > 1
1779	&& !(uErr & X86_TRAP_PF_P)
1780	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1781	{
1782	/*
1783	* This code path is currently only taken when the caller is PGMTrap0eHandler
1784	* for non-present pages!
1785	*
1786	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1787	* deal with locality.
1788	*/
1789	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1790	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1791	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1792	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1793	# else
1794	const unsigned offPTSrc = 0;
1795	# endif
1796	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1797	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1798	iPTDst = 0;
1799	else
1800	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1801	for (; iPTDst < iPTDstEnd; iPTDst++)
1802	{
1803	if (!pPTDst->a[iPTDst].n.u1Present)
1804	{
1805	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1806	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1807	NOREF(GCPtrCurPage);
1808	#ifndef IN_RING0
1809	/*
1810	* Assuming kernel code will be marked as supervisor - and not as user level
1811	* and executed using a conforming code selector - And marked as readonly.
1812	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1813	*/
1814	PPGMPAGE pPage;
1815	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1816	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1817	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1818	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1819	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1820	)
1821	#endif /* else: CSAM not active */
1822	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1823	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1824	GCPtrCurPage, PteSrc.n.u1Present,
1825	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1826	PteSrc.n.u1User & PdeSrc.n.u1User,
1827	(uint64_t)PteSrc.u,
1828	(uint64_t)pPTDst->a[iPTDst].u,
1829	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1830	}
1831	}
1832	}
1833	else
1834	# endif /* PGM_SYNC_N_PAGES */
1835	{
1836	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1837	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1838	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1839	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1840	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1841	GCPtrPage, PteSrc.n.u1Present,
1842	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1843	PteSrc.n.u1User & PdeSrc.n.u1User,
1844	(uint64_t)PteSrc.u,
1845	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1846	}
1847	}
1848	else /* MMIO or invalid page: emulated in #PF handler. */
1849	{
1850	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1851	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1852	}
1853	}
1854	else
1855	{
1856	/*
1857	* 4/2MB page - lazy syncing shadow 4K pages.
1858	* (There are many causes of getting here, it's no longer only CSAM.)
1859	*/
1860	/* Calculate the GC physical address of this 4KB shadow page. */
1861	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1862	/* Find ram range. */
1863	PPGMPAGE pPage;
1864	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1865	if (RT_SUCCESS(rc))
1866	{
1867	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1868	/* Try make the page writable if necessary. */
1869	if ( PdeSrc.n.u1Write
1870	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1871	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1872	{
1873	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1874	AssertRC(rc);
1875	}
1876	# endif
1877
1878	/*
1879	* Make shadow PTE entry.
1880	*/
1881	SHWPTE PteDst;
1882	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1883	\| PGM_PAGE_GET_HCPHYS(pPage);
1884	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1885	{
1886	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1887	PteDst.n.u1Write = 0;
1888	else
1889	PteDst.u = 0;
1890	}
1891	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1892	# ifdef PGMPOOL_WITH_USER_TRACKING
1893	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1894	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1895	# endif
1896	/* Make sure only allocated pages are mapped writable. */
1897	if ( PteDst.n.u1Write
1898	&& PteDst.n.u1Present
1899	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1900	{
1901	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1902	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1903	}
1904
1905	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1906
1907	/*
1908	* If the page is not flagged as dirty and is writable, then make it read-only
1909	* at PD level, so we can set the dirty bit when the page is modified.
1910	*
1911	* ASSUMES that page access handlers are implemented on page table entry level.
1912	* Thus we will first catch the dirty access and set PDE.D and restart. If
1913	* there is an access handler, we'll trap again and let it work on the problem.
1914	*/
1915	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1916	* As for invlpg, it simply frees the whole shadow PT.
1917	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1918	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1919	{
1920	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1921	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1922	PdeDst.n.u1Write = 0;
1923	}
1924	else
1925	{
1926	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1927	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1928	}
1929	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1930	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1931	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1932	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1933	}
1934	else
1935	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1936	}
1937	# if defined(IN_RC)
1938	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1939	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1940	# endif
1941	return VINF_SUCCESS;
1942	}
1943	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1944	}
1945	else
1946	{
1947	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1948	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1949	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1950	}
1951
1952	/*
1953	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1954	* Yea, I'm lazy.
1955	*/
1956	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1957	ASMAtomicWriteSize(pPdeDst, 0);
1958
1959	# if defined(IN_RC)
1960	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1961	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1962	# endif
1963	PGM_INVL_VCPU_TLBS(pVCpu);
1964	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1965
1966	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1967	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1968	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1969	&& !defined(IN_RC)
1970
1971	# ifdef PGM_SYNC_N_PAGES
1972	/*
1973	* Get the shadow PDE, find the shadow page table in the pool.
1974	*/
1975	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1976	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1977
1978	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1979	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1980
1981	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1982	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1983	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1984	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1985	X86PDEPAE PdeDst;
1986	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1987
1988	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1989	AssertRCSuccessReturn(rc, rc);
1990	Assert(pPDDst && pPdptDst);
1991	PdeDst = pPDDst->a[iPDDst];
1992	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1993	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1994	PEPTPD pPDDst;
1995	EPTPDE PdeDst;
1996
1997	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1998	if (rc != VINF_SUCCESS)
1999	{
2000	AssertRC(rc);
2001	return rc;
2002	}
2003	Assert(pPDDst);
2004	PdeDst = pPDDst->a[iPDDst];
2005	# endif
2006	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
2007	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2008	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2009
2010	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2011	if ( cPages > 1
2012	&& !(uErr & X86_TRAP_PF_P)
2013	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2014	{
2015	/*
2016	* This code path is currently only taken when the caller is PGMTrap0eHandler
2017	* for non-present pages!
2018	*
2019	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2020	* deal with locality.
2021	*/
2022	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2023	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2024	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2025	iPTDst = 0;
2026	else
2027	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2028	for (; iPTDst < iPTDstEnd; iPTDst++)
2029	{
2030	if (!pPTDst->a[iPTDst].n.u1Present)
2031	{
2032	GSTPTE PteSrc;
2033
2034	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2035
2036	/* Fake the page table entry */
2037	PteSrc.u = GCPtrCurPage;
2038	PteSrc.n.u1Present = 1;
2039	PteSrc.n.u1Dirty = 1;
2040	PteSrc.n.u1Accessed = 1;
2041	PteSrc.n.u1Write = 1;
2042	PteSrc.n.u1User = 1;
2043
2044	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2045
2046	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2047	GCPtrCurPage, PteSrc.n.u1Present,
2048	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2049	PteSrc.n.u1User & PdeSrc.n.u1User,
2050	(uint64_t)PteSrc.u,
2051	(uint64_t)pPTDst->a[iPTDst].u,
2052	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2053
2054	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2055	break;
2056	}
2057	else
2058	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2059	}
2060	}
2061	else
2062	# endif /* PGM_SYNC_N_PAGES */
2063	{
2064	GSTPTE PteSrc;
2065	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2066	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2067
2068	/* Fake the page table entry */
2069	PteSrc.u = GCPtrCurPage;
2070	PteSrc.n.u1Present = 1;
2071	PteSrc.n.u1Dirty = 1;
2072	PteSrc.n.u1Accessed = 1;
2073	PteSrc.n.u1Write = 1;
2074	PteSrc.n.u1User = 1;
2075	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2076
2077	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2078	GCPtrPage, PteSrc.n.u1Present,
2079	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2080	PteSrc.n.u1User & PdeSrc.n.u1User,
2081	(uint64_t)PteSrc.u,
2082	(uint64_t)pPTDst->a[iPTDst].u,
2083	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2084	}
2085	return VINF_SUCCESS;
2086
2087	#else
2088	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2089	return VERR_INTERNAL_ERROR;
2090	#endif
2091	}
2092
2093
2094	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2095	/**
2096	* Investigate page fault and handle write protection page faults caused by
2097	* dirty bit tracking.
2098	*
2099	* @returns VBox status code.
2100	* @param pVCpu The VMCPU handle.
2101	* @param uErr Page fault error code.
2102	* @param pPdeDst Shadow page directory entry.
2103	* @param pPdeSrc Guest page directory entry.
2104	* @param GCPtrPage Guest context page address.
2105	*/
2106	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2107	{
2108	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2109	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2110	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2111	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2112	bool fBigPagesSupported = true;
2113	# else
2114	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2115	# endif
2116	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2117	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2118	# endif
2119	unsigned uPageFaultLevel;
2120	int rc;
2121	PVM pVM = pVCpu->CTX_SUFF(pVM);
2122	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2123
2124	Assert(PGMIsLockOwner(pVM));
2125
2126	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2127	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2128
2129	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2130	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2131
2132	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2133	PX86PML4E pPml4eSrc;
2134	PX86PDPE pPdpeSrc;
2135
2136	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2137	Assert(pPml4eSrc);
2138
2139	/*
2140	* Real page fault? (PML4E level)
2141	*/
2142	if ( (uErr & X86_TRAP_PF_RSVD)
2143	\|\| !pPml4eSrc->n.u1Present
2144	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2145	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2146	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2147	)
2148	{
2149	uPageFaultLevel = 0;
2150	goto l_UpperLevelPageFault;
2151	}
2152	Assert(pPdpeSrc);
2153
2154	# else /* PAE */
2155	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2156	# endif /* PAE */
2157
2158	/*
2159	* Real page fault? (PDPE level)
2160	*/
2161	if ( (uErr & X86_TRAP_PF_RSVD)
2162	\|\| !pPdpeSrc->n.u1Present
2163	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2164	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2165	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2166	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2167	# endif
2168	)
2169	{
2170	uPageFaultLevel = 1;
2171	goto l_UpperLevelPageFault;
2172	}
2173	# endif
2174
2175	/*
2176	* Real page fault? (PDE level)
2177	*/
2178	if ( (uErr & X86_TRAP_PF_RSVD)
2179	\|\| !pPdeSrc->n.u1Present
2180	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2181	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2182	# endif
2183	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2184	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2185	{
2186	uPageFaultLevel = 2;
2187	goto l_UpperLevelPageFault;
2188	}
2189
2190	/*
2191	* First check the easy case where the page directory has been marked read-only to track
2192	* the dirty bit of an emulated BIG page
2193	*/
2194	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2195	{
2196	/* Mark guest page directory as accessed */
2197	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2198	pPml4eSrc->n.u1Accessed = 1;
2199	pPdpeSrc->lm.u1Accessed = 1;
2200	# endif
2201	pPdeSrc->b.u1Accessed = 1;
2202
2203	/*
2204	* Only write protection page faults are relevant here.
2205	*/
2206	if (fWriteFault)
2207	{
2208	/* Mark guest page directory as dirty (BIG page only). */
2209	pPdeSrc->b.u1Dirty = 1;
2210
2211	if (pPdeDst->n.u1Present)
2212	{
2213	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2214	{
2215	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2216	Assert(pPdeSrc->b.u1Write);
2217
2218	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2219	* fault again and take this path to only invalidate the entry.
2220	*/
2221	pPdeDst->n.u1Write = 1;
2222	pPdeDst->n.u1Accessed = 1;
2223	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2224	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2225	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2226	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2227	}
2228	# ifdef IN_RING0
2229	else
2230	/* Check for stale TLB entry; only applies to the SMP guest case. */
2231	if ( pVM->cCPUs > 1
2232	&& pPdeDst->n.u1Write
2233	&& pPdeDst->n.u1Accessed)
2234	{
2235	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2236	if (pShwPage)
2237	{
2238	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2239	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2240	if ( pPteDst->n.u1Present
2241	&& pPteDst->n.u1Write)
2242	{
2243	/* Stale TLB entry. */
2244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2245	PGM_INVL_PG(pVCpu, GCPtrPage);
2246
2247	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2248	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2249	}
2250	}
2251	}
2252	# endif /* IN_RING0 */
2253	}
2254	}
2255	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2256	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2257	}
2258	/* else: 4KB page table */
2259
2260	/*
2261	* Map the guest page table.
2262	*/
2263	PGSTPT pPTSrc;
2264	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2265	if (RT_SUCCESS(rc))
2266	{
2267	/*
2268	* Real page fault?
2269	*/
2270	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2271	const GSTPTE PteSrc = *pPteSrc;
2272	if ( !PteSrc.n.u1Present
2273	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2274	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2275	# endif
2276	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2277	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2278	)
2279	{
2280	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2281	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2282	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2283
2284	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2285	* See the 2nd case above as well.
2286	*/
2287	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2288	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2289
2290	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2291	return VINF_EM_RAW_GUEST_TRAP;
2292	}
2293	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2294
2295	/*
2296	* Set the accessed bits in the page directory and the page table.
2297	*/
2298	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2299	pPml4eSrc->n.u1Accessed = 1;
2300	pPdpeSrc->lm.u1Accessed = 1;
2301	# endif
2302	pPdeSrc->n.u1Accessed = 1;
2303	pPteSrc->n.u1Accessed = 1;
2304
2305	/*
2306	* Only write protection page faults are relevant here.
2307	*/
2308	if (fWriteFault)
2309	{
2310	/* Write access, so mark guest entry as dirty. */
2311	# ifdef VBOX_WITH_STATISTICS
2312	if (!pPteSrc->n.u1Dirty)
2313	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2314	else
2315	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2316	# endif
2317
2318	pPteSrc->n.u1Dirty = 1;
2319
2320	if (pPdeDst->n.u1Present)
2321	{
2322	#ifndef IN_RING0
2323	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2324	* Our individual shadow handlers will provide more information and force a fatal exit.
2325	*/
2326	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2327	{
2328	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2329	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2330	return VINF_SUCCESS;
2331	}
2332	#endif
2333	/*
2334	* Map shadow page table.
2335	*/
2336	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2337	if (pShwPage)
2338	{
2339	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2340	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2341	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2342	{
2343	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2344	{
2345	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2346	# ifdef VBOX_STRICT
2347	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2348	if (pPage)
2349	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2350	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2351	# endif
2352	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2353
2354	Assert(pPteSrc->n.u1Write);
2355
2356	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2357	* fault again and take this path to only invalidate the entry.
2358	*/
2359	pPteDst->n.u1Write = 1;
2360	pPteDst->n.u1Dirty = 1;
2361	pPteDst->n.u1Accessed = 1;
2362	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2363	PGM_INVL_PG(pVCpu, GCPtrPage);
2364
2365	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2366	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2367	}
2368	# ifdef IN_RING0
2369	else
2370	/* Check for stale TLB entry; only applies to the SMP guest case. */
2371	if ( pVM->cCPUs > 1
2372	&& pPteDst->n.u1Write == 1
2373	&& pPteDst->n.u1Accessed == 1)
2374	{
2375	/* Stale TLB entry. */
2376	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2377	PGM_INVL_PG(pVCpu, GCPtrPage);
2378
2379	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2380	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2381	}
2382	# endif
2383	}
2384	}
2385	else
2386	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2387	}
2388	}
2389	/** @todo Optimize accessed bit emulation? */
2390	# ifdef VBOX_STRICT
2391	/*
2392	* Sanity check.
2393	*/
2394	else if ( !pPteSrc->n.u1Dirty
2395	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2396	&& pPdeDst->n.u1Present)
2397	{
2398	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2399	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2400	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2401	if ( pPteDst->n.u1Present
2402	&& pPteDst->n.u1Write)
2403	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2404	}
2405	# endif /* VBOX_STRICT */
2406	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2407	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2408	}
2409	AssertRC(rc);
2410	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2411	return rc;
2412
2413
2414	l_UpperLevelPageFault:
2415	/*
2416	* Pagefault detected while checking the PML4E, PDPE or PDE.
2417	* Single exit handler to get rid of duplicate code paths.
2418	*/
2419	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2420	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2421	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2422
2423	if (
2424	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2425	pPml4eSrc->n.u1Present &&
2426	# endif
2427	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2428	pPdpeSrc->n.u1Present &&
2429	# endif
2430	pPdeSrc->n.u1Present)
2431	{
2432	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2433	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2434	{
2435	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2436	}
2437	else
2438	{
2439	/*
2440	* Map the guest page table.
2441	*/
2442	PGSTPT pPTSrc;
2443	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2444	if (RT_SUCCESS(rc))
2445	{
2446	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2447	const GSTPTE PteSrc = *pPteSrc;
2448	if (pPteSrc->n.u1Present)
2449	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2450	}
2451	AssertRC(rc);
2452	}
2453	}
2454	return VINF_EM_RAW_GUEST_TRAP;
2455	}
2456	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2457
2458
2459	/**
2460	* Sync a shadow page table.
2461	*
2462	* The shadow page table is not present. This includes the case where
2463	* there is a conflict with a mapping.
2464	*
2465	* @returns VBox status code.
2466	* @param pVCpu The VMCPU handle.
2467	* @param iPD Page directory index.
2468	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2469	* Assume this is a temporary mapping.
2470	* @param GCPtrPage GC Pointer of the page that caused the fault
2471	*/
2472	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2473	{
2474	PVM pVM = pVCpu->CTX_SUFF(pVM);
2475	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2476
2477	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2478	#if 0 /* rarely useful; leave for debugging. */
2479	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2480	#endif
2481	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2482
2483	Assert(PGMIsLocked(pVM));
2484
2485	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2486	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2487	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2488	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2489	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2490
2491	int rc = VINF_SUCCESS;
2492
2493	/*
2494	* Validate input a little bit.
2495	*/
2496	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2497	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2498	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2499	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2500
2501	/* Fetch the pgm pool shadow descriptor. */
2502	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2503	Assert(pShwPde);
2504
2505	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2506	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2507	PPGMPOOLPAGE pShwPde = NULL;
2508	PX86PDPAE pPDDst;
2509	PSHWPDE pPdeDst;
2510
2511	/* Fetch the pgm pool shadow descriptor. */
2512	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2513	AssertRCSuccessReturn(rc, rc);
2514	Assert(pShwPde);
2515
2516	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2517	pPdeDst = &pPDDst->a[iPDDst];
2518
2519	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2520	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2521	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2522	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2523	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2524	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2525	AssertRCSuccessReturn(rc, rc);
2526	Assert(pPDDst);
2527	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2528	# endif
2529	SHWPDE PdeDst = *pPdeDst;
2530
2531	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2532	/* Fetch the pgm pool shadow descriptor. */
2533	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2534	Assert(pShwPde);
2535	# endif
2536
2537	# ifndef PGM_WITHOUT_MAPPINGS
2538	/*
2539	* Check for conflicts.
2540	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2541	* HC: Simply resolve the conflict.
2542	*/
2543	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2544	{
2545	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2546	# ifndef IN_RING3
2547	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2548	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2549	return VERR_ADDRESS_CONFLICT;
2550	# else
2551	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2552	Assert(pMapping);
2553	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2554	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2555	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2556	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2557	# else
2558	AssertFailed(); /* can't happen for amd64 */
2559	# endif
2560	if (RT_FAILURE(rc))
2561	{
2562	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2563	return rc;
2564	}
2565	PdeDst = *pPdeDst;
2566	# endif
2567	}
2568	# else /* PGM_WITHOUT_MAPPINGS */
2569	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2570	# endif /* PGM_WITHOUT_MAPPINGS */
2571	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2572
2573	# if defined(IN_RC)
2574	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2575	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2576	# endif
2577
2578	/*
2579	* Sync page directory entry.
2580	*/
2581	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2582	if (PdeSrc.n.u1Present)
2583	{
2584	/*
2585	* Allocate & map the page table.
2586	*/
2587	PSHWPT pPTDst;
2588	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2589	const bool fPageTable = !PdeSrc.b.u1Size;
2590	# else
2591	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2592	# endif
2593	PPGMPOOLPAGE pShwPage;
2594	RTGCPHYS GCPhys;
2595	if (fPageTable)
2596	{
2597	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2598	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2599	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2600	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2601	# endif
2602	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2603	}
2604	else
2605	{
2606	PGMPOOLACCESS enmAccess;
2607
2608	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2609	const bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2610	const bool fNoExecute = fNoExecuteBitValid && PdeSrc.n.u1NoExecute;
2611	# else
2612	const bool fNoExecute = false;
2613	# endif
2614
2615	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2616	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2617	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2618	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2619	# endif
2620	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2621	if (PdeSrc.n.u1User)
2622	{
2623	if (PdeSrc.n.u1Write)
2624	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2625	else
2626	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2627	}
2628	else
2629	{
2630	if (PdeSrc.n.u1Write)
2631	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2632	else
2633	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2634	}
2635	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2636	}
2637	if (rc == VINF_SUCCESS)
2638	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2639	else if (rc == VINF_PGM_CACHED_PAGE)
2640	{
2641	/*
2642	* The PT was cached, just hook it up.
2643	*/
2644	if (fPageTable)
2645	PdeDst.u = pShwPage->Core.Key
2646	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2647	else
2648	{
2649	PdeDst.u = pShwPage->Core.Key
2650	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2651	/* (see explanation and assumptions further down.) */
2652	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2653	{
2654	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2655	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2656	PdeDst.b.u1Write = 0;
2657	}
2658	}
2659	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2660	# if defined(IN_RC)
2661	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2662	# endif
2663	return VINF_SUCCESS;
2664	}
2665	else if (rc == VERR_PGM_POOL_FLUSHED)
2666	{
2667	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2668	# if defined(IN_RC)
2669	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2670	# endif
2671	return VINF_PGM_SYNC_CR3;
2672	}
2673	else
2674	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2675	PdeDst.u &= X86_PDE_AVL_MASK;
2676	PdeDst.u \|= pShwPage->Core.Key;
2677
2678	/*
2679	* Page directory has been accessed (this is a fault situation, remember).
2680	*/
2681	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2682	if (fPageTable)
2683	{
2684	/*
2685	* Page table - 4KB.
2686	*
2687	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2688	*/
2689	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2690	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2691	PGSTPT pPTSrc;
2692	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2693	if (RT_SUCCESS(rc))
2694	{
2695	/*
2696	* Start by syncing the page directory entry so CSAM's TLB trick works.
2697	*/
2698	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2699	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2700	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2701	# if defined(IN_RC)
2702	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2703	# endif
2704
2705	/*
2706	* Directory/page user or supervisor privilege: (same goes for read/write)
2707	*
2708	* Directory Page Combined
2709	* U/S U/S U/S
2710	* 0 0 0
2711	* 0 1 0
2712	* 1 0 0
2713	* 1 1 1
2714	*
2715	* Simple AND operation. Table listed for completeness.
2716	*
2717	*/
2718	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2719	# ifdef PGM_SYNC_N_PAGES
2720	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2721	unsigned iPTDst = iPTBase;
2722	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2723	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2724	iPTDst = 0;
2725	else
2726	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2727	# else /* !PGM_SYNC_N_PAGES */
2728	unsigned iPTDst = 0;
2729	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2730	# endif /* !PGM_SYNC_N_PAGES */
2731	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2732	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2733	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2734	# else
2735	const unsigned offPTSrc = 0;
2736	# endif
2737	for (; iPTDst < iPTDstEnd; iPTDst++)
2738	{
2739	const unsigned iPTSrc = iPTDst + offPTSrc;
2740	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2741
2742	if (PteSrc.n.u1Present) /* we've already cleared it above */
2743	{
2744	# ifndef IN_RING0
2745	/*
2746	* Assuming kernel code will be marked as supervisor - and not as user level
2747	* and executed using a conforming code selector - And marked as readonly.
2748	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2749	*/
2750	PPGMPAGE pPage;
2751	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2752	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2753	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2754	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2755	)
2756	# endif
2757	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2758	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2759	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2760	PteSrc.n.u1Present,
2761	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2762	PteSrc.n.u1User & PdeSrc.n.u1User,
2763	(uint64_t)PteSrc.u,
2764	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2765	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2766	}
2767	} /* for PTEs */
2768	}
2769	}
2770	else
2771	{
2772	/*
2773	* Big page - 2/4MB.
2774	*
2775	* We'll walk the ram range list in parallel and optimize lookups.
2776	* We will only sync on shadow page table at a time.
2777	*/
2778	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2779
2780	/**
2781	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2782	*/
2783
2784	/*
2785	* Start by syncing the page directory entry.
2786	*/
2787	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2788	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2789
2790	/*
2791	* If the page is not flagged as dirty and is writable, then make it read-only
2792	* at PD level, so we can set the dirty bit when the page is modified.
2793	*
2794	* ASSUMES that page access handlers are implemented on page table entry level.
2795	* Thus we will first catch the dirty access and set PDE.D and restart. If
2796	* there is an access handler, we'll trap again and let it work on the problem.
2797	*/
2798	/** @todo move the above stuff to a section in the PGM documentation. */
2799	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2800	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2801	{
2802	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2803	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2804	PdeDst.b.u1Write = 0;
2805	}
2806	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2807	# if defined(IN_RC)
2808	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2809	# endif
2810
2811	/*
2812	* Fill the shadow page table.
2813	*/
2814	/* Get address and flags from the source PDE. */
2815	SHWPTE PteDstBase;
2816	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2817
2818	/* Loop thru the entries in the shadow PT. */
2819	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2820	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2821	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2822	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2823	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2824	unsigned iPTDst = 0;
2825	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2826	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2827	{
2828	/* Advance ram range list. */
2829	while (pRam && GCPhys > pRam->GCPhysLast)
2830	pRam = pRam->CTX_SUFF(pNext);
2831	if (pRam && GCPhys >= pRam->GCPhys)
2832	{
2833	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2834	do
2835	{
2836	/* Make shadow PTE. */
2837	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2838	SHWPTE PteDst;
2839
2840	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2841	/* Try make the page writable if necessary. */
2842	if ( PteDstBase.n.u1Write
2843	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2844	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2845	{
2846	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2847	AssertRCReturn(rc, rc);
2848	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2849	break;
2850	}
2851	# endif
2852
2853	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2854	{
2855	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2856	{
2857	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2858	PteDst.n.u1Write = 0;
2859	}
2860	else
2861	PteDst.u = 0;
2862	}
2863	# ifndef IN_RING0
2864	/*
2865	* Assuming kernel code will be marked as supervisor and not as user level and executed
2866	* using a conforming code selector. Don't check for readonly, as that implies the whole
2867	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2868	*/
2869	else if ( !PdeSrc.n.u1User
2870	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2871	PteDst.u = 0;
2872	# endif
2873	else
2874	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2875
2876	/* Only map writable pages writable. */
2877	if ( PteDst.n.u1Write
2878	&& PteDst.n.u1Present
2879	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2880	{
2881	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2882	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2883	}
2884
2885	# ifdef PGMPOOL_WITH_USER_TRACKING
2886	if (PteDst.n.u1Present)
2887	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2888	# endif
2889	/* commit it */
2890	pPTDst->a[iPTDst] = PteDst;
2891	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2892	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2893	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2894
2895	/* advance */
2896	GCPhys += PAGE_SIZE;
2897	iHCPage++;
2898	iPTDst++;
2899	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2900	&& GCPhys <= pRam->GCPhysLast);
2901	}
2902	else if (pRam)
2903	{
2904	Log(("Invalid pages at %RGp\n", GCPhys));
2905	do
2906	{
2907	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2908	GCPhys += PAGE_SIZE;
2909	iPTDst++;
2910	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2911	&& GCPhys < pRam->GCPhys);
2912	}
2913	else
2914	{
2915	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2916	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2917	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2918	}
2919	} /* while more PTEs */
2920	} /* 4KB / 4MB */
2921	}
2922	else
2923	AssertRelease(!PdeDst.n.u1Present);
2924
2925	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2926	if (RT_FAILURE(rc))
2927	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2928	return rc;
2929
2930	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2931	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2932	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2933	&& !defined(IN_RC)
2934
2935	/*
2936	* Validate input a little bit.
2937	*/
2938	int rc = VINF_SUCCESS;
2939	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2940	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2941	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2942
2943	/* Fetch the pgm pool shadow descriptor. */
2944	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2945	Assert(pShwPde);
2946
2947	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2948	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2949	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2950	PX86PDPAE pPDDst;
2951	PSHWPDE pPdeDst;
2952
2953	/* Fetch the pgm pool shadow descriptor. */
2954	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2955	AssertRCSuccessReturn(rc, rc);
2956	Assert(pShwPde);
2957
2958	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2959	pPdeDst = &pPDDst->a[iPDDst];
2960
2961	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2962	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2963	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2964	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2965	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2966	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2967	AssertRCSuccessReturn(rc, rc);
2968	Assert(pPDDst);
2969	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2970
2971	/* Fetch the pgm pool shadow descriptor. */
2972	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2973	Assert(pShwPde);
2974
2975	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2976	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2977	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2978	PEPTPD pPDDst;
2979	PEPTPDPT pPdptDst;
2980
2981	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2982	if (rc != VINF_SUCCESS)
2983	{
2984	AssertRC(rc);
2985	return rc;
2986	}
2987	Assert(pPDDst);
2988	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2989
2990	/* Fetch the pgm pool shadow descriptor. */
2991	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2992	Assert(pShwPde);
2993	# endif
2994	SHWPDE PdeDst = *pPdeDst;
2995
2996	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2997	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2998
2999	GSTPDE PdeSrc;
3000	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3001	PdeSrc.n.u1Present = 1;
3002	PdeSrc.n.u1Write = 1;
3003	PdeSrc.n.u1Accessed = 1;
3004	PdeSrc.n.u1User = 1;
3005
3006	/*
3007	* Allocate & map the page table.
3008	*/
3009	PSHWPT pPTDst;
3010	PPGMPOOLPAGE pShwPage;
3011	RTGCPHYS GCPhys;
3012
3013	/* Virtual address = physical address */
3014	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3015	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3016
3017	if ( rc == VINF_SUCCESS
3018	\|\| rc == VINF_PGM_CACHED_PAGE)
3019	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3020	else
3021	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3022
3023	PdeDst.u &= X86_PDE_AVL_MASK;
3024	PdeDst.u \|= pShwPage->Core.Key;
3025	PdeDst.n.u1Present = 1;
3026	PdeDst.n.u1Write = 1;
3027	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3028	PdeDst.n.u1Execute = 1;
3029	# else
3030	PdeDst.n.u1User = 1;
3031	PdeDst.n.u1Accessed = 1;
3032	# endif
3033	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3034
3035	pgmLock(pVM);
3036	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3037	pgmUnlock(pVM);
3038	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3039	return rc;
3040
3041	#else
3042	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3043	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3044	return VERR_INTERNAL_ERROR;
3045	#endif
3046	}
3047
3048
3049
3050	/**
3051	* Prefetch a page/set of pages.
3052	*
3053	* Typically used to sync commonly used pages before entering raw mode
3054	* after a CR3 reload.
3055	*
3056	* @returns VBox status code.
3057	* @param pVCpu The VMCPU handle.
3058	* @param GCPtrPage Page to invalidate.
3059	*/
3060	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3061	{
3062	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3063	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3064	/*
3065	* Check that all Guest levels thru the PDE are present, getting the
3066	* PD and PDE in the processes.
3067	*/
3068	int rc = VINF_SUCCESS;
3069	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3070	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3071	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3072	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3073	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3074	unsigned iPDSrc;
3075	X86PDPE PdpeSrc;
3076	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3077	if (!pPDSrc)
3078	return VINF_SUCCESS; /* not present */
3079	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3080	unsigned iPDSrc;
3081	PX86PML4E pPml4eSrc;
3082	X86PDPE PdpeSrc;
3083	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3084	if (!pPDSrc)
3085	return VINF_SUCCESS; /* not present */
3086	# endif
3087	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3088	# else
3089	PGSTPD pPDSrc = NULL;
3090	const unsigned iPDSrc = 0;
3091	GSTPDE PdeSrc;
3092
3093	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3094	PdeSrc.n.u1Present = 1;
3095	PdeSrc.n.u1Write = 1;
3096	PdeSrc.n.u1Accessed = 1;
3097	PdeSrc.n.u1User = 1;
3098	# endif
3099
3100	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3101	{
3102	PVM pVM = pVCpu->CTX_SUFF(pVM);
3103	pgmLock(pVM);
3104
3105	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3106	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3107	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3108	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3109	PX86PDPAE pPDDst;
3110	X86PDEPAE PdeDst;
3111	# if PGM_GST_TYPE != PGM_TYPE_PAE
3112	X86PDPE PdpeSrc;
3113
3114	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3115	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3116	# endif
3117	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3118	if (rc != VINF_SUCCESS)
3119	{
3120	pgmUnlock(pVM);
3121	AssertRC(rc);
3122	return rc;
3123	}
3124	Assert(pPDDst);
3125	PdeDst = pPDDst->a[iPDDst];
3126
3127	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3128	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3129	PX86PDPAE pPDDst;
3130	X86PDEPAE PdeDst;
3131
3132	# if PGM_GST_TYPE == PGM_TYPE_PROT
3133	/* AMD-V nested paging */
3134	X86PML4E Pml4eSrc;
3135	X86PDPE PdpeSrc;
3136	PX86PML4E pPml4eSrc = &Pml4eSrc;
3137
3138	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3139	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3140	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3141	# endif
3142
3143	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3144	if (rc != VINF_SUCCESS)
3145	{
3146	pgmUnlock(pVM);
3147	AssertRC(rc);
3148	return rc;
3149	}
3150	Assert(pPDDst);
3151	PdeDst = pPDDst->a[iPDDst];
3152	# endif
3153	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3154	{
3155	if (!PdeDst.n.u1Present)
3156	{
3157	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3158	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3159	}
3160	else
3161	{
3162	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3163	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3164	* makes no sense to prefetch more than one page.
3165	*/
3166	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3167	if (RT_SUCCESS(rc))
3168	rc = VINF_SUCCESS;
3169	}
3170	}
3171	pgmUnlock(pVM);
3172	}
3173	return rc;
3174
3175	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3176	return VINF_SUCCESS; /* ignore */
3177	#endif
3178	}
3179
3180
3181
3182
3183	/**
3184	* Syncs a page during a PGMVerifyAccess() call.
3185	*
3186	* @returns VBox status code (informational included).
3187	* @param pVCpu The VMCPU handle.
3188	* @param GCPtrPage The address of the page to sync.
3189	* @param fPage The effective guest page flags.
3190	* @param uErr The trap error code.
3191	*/
3192	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3193	{
3194	PVM pVM = pVCpu->CTX_SUFF(pVM);
3195
3196	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3197
3198	Assert(!HWACCMIsNestedPagingActive(pVM));
3199	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3200	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3201
3202	# ifndef IN_RING0
3203	if (!(fPage & X86_PTE_US))
3204	{
3205	/*
3206	* Mark this page as safe.
3207	*/
3208	/** @todo not correct for pages that contain both code and data!! */
3209	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3210	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3211	}
3212	# endif
3213
3214	/*
3215	* Get guest PD and index.
3216	*/
3217	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3218	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3219	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3220	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3221	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3222	unsigned iPDSrc = 0;
3223	X86PDPE PdpeSrc;
3224	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3225
3226	if (pPDSrc)
3227	{
3228	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3229	return VINF_EM_RAW_GUEST_TRAP;
3230	}
3231	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3232	unsigned iPDSrc;
3233	PX86PML4E pPml4eSrc;
3234	X86PDPE PdpeSrc;
3235	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3236	if (!pPDSrc)
3237	{
3238	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3239	return VINF_EM_RAW_GUEST_TRAP;
3240	}
3241	# endif
3242	# else
3243	PGSTPD pPDSrc = NULL;
3244	const unsigned iPDSrc = 0;
3245	# endif
3246	int rc = VINF_SUCCESS;
3247
3248	pgmLock(pVM);
3249
3250	/*
3251	* First check if the shadow pd is present.
3252	*/
3253	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3254	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3255	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3256	PX86PDEPAE pPdeDst;
3257	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3258	PX86PDPAE pPDDst;
3259	# if PGM_GST_TYPE != PGM_TYPE_PAE
3260	X86PDPE PdpeSrc;
3261
3262	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3263	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3264	# endif
3265	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3266	if (rc != VINF_SUCCESS)
3267	{
3268	pgmUnlock(pVM);
3269	AssertRC(rc);
3270	return rc;
3271	}
3272	Assert(pPDDst);
3273	pPdeDst = &pPDDst->a[iPDDst];
3274
3275	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3276	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3277	PX86PDPAE pPDDst;
3278	PX86PDEPAE pPdeDst;
3279
3280	# if PGM_GST_TYPE == PGM_TYPE_PROT
3281	/* AMD-V nested paging */
3282	X86PML4E Pml4eSrc;
3283	X86PDPE PdpeSrc;
3284	PX86PML4E pPml4eSrc = &Pml4eSrc;
3285
3286	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3287	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3288	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3289	# endif
3290
3291	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3292	if (rc != VINF_SUCCESS)
3293	{
3294	pgmUnlock(pVM);
3295	AssertRC(rc);
3296	return rc;
3297	}
3298	Assert(pPDDst);
3299	pPdeDst = &pPDDst->a[iPDDst];
3300	# endif
3301
3302	# if defined(IN_RC)
3303	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3304	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3305	# endif
3306
3307	if (!pPdeDst->n.u1Present)
3308	{
3309	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3310	if (rc != VINF_SUCCESS)
3311	{
3312	# if defined(IN_RC)
3313	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3314	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3315	# endif
3316	pgmUnlock(pVM);
3317	AssertRC(rc);
3318	return rc;
3319	}
3320	}
3321
3322	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3323	/* Check for dirty bit fault */
3324	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3325	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3326	Log(("PGMVerifyAccess: success (dirty)\n"));
3327	else
3328	{
3329	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3330	# else
3331	{
3332	GSTPDE PdeSrc;
3333	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3334	PdeSrc.n.u1Present = 1;
3335	PdeSrc.n.u1Write = 1;
3336	PdeSrc.n.u1Accessed = 1;
3337	PdeSrc.n.u1User = 1;
3338
3339	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3340	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3341	if (uErr & X86_TRAP_PF_US)
3342	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3343	else /* supervisor */
3344	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3345
3346	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3347	if (RT_SUCCESS(rc))
3348	{
3349	/* Page was successfully synced */
3350	Log2(("PGMVerifyAccess: success (sync)\n"));
3351	rc = VINF_SUCCESS;
3352	}
3353	else
3354	{
3355	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3356	rc = VINF_EM_RAW_GUEST_TRAP;
3357	}
3358	}
3359	# if defined(IN_RC)
3360	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3361	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3362	# endif
3363	pgmUnlock(pVM);
3364	return rc;
3365
3366	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3367
3368	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3369	return VERR_INTERNAL_ERROR;
3370	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3371	}
3372
3373	#undef MY_STAM_COUNTER_INC
3374	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3375
3376
3377	/**
3378	* Syncs the paging hierarchy starting at CR3.
3379	*
3380	* @returns VBox status code, no specials.
3381	* @param pVCpu The VMCPU handle.
3382	* @param cr0 Guest context CR0 register
3383	* @param cr3 Guest context CR3 register
3384	* @param cr4 Guest context CR4 register
3385	* @param fGlobal Including global page directories or not
3386	*/
3387	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3388	{
3389	PVM pVM = pVCpu->CTX_SUFF(pVM);
3390
3391	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3392	fGlobal = true; /* Change this CR3 reload to be a global one. */
3393
3394	LogFlow(("SyncCR3 %d\n", fGlobal));
3395
3396	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3397	/*
3398	* Update page access handlers.
3399	* The virtual are always flushed, while the physical are only on demand.
3400	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3401	* have to look into that later because it will have a bad influence on the performance.
3402	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3403	* bird: Yes, but that won't work for aliases.
3404	*/
3405	/** @todo this MUST go away. See #1557. */
3406	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3407	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3408	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3409	#endif
3410
3411	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3412	/*
3413	* Nested / EPT - almost no work.
3414	*/
3415	/** @todo check if this is really necessary; the call does it as well... */
3416	HWACCMFlushTLB(pVCpu);
3417	return VINF_SUCCESS;
3418
3419	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3420	/*
3421	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3422	* out the shadow parts when the guest modifies its tables.
3423	*/
3424	return VINF_SUCCESS;
3425
3426	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3427
3428	# ifdef PGM_WITHOUT_MAPPINGS
3429	Assert(pVM->pgm.s.fMappingsFixed);
3430	return VINF_SUCCESS;
3431	# else
3432	/* Nothing to do when mappings are fixed. */
3433	if (pVM->pgm.s.fMappingsFixed)
3434	return VINF_SUCCESS;
3435
3436	int rc = PGMMapResolveConflicts(pVM);
3437	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3438	if (rc == VINF_PGM_SYNC_CR3)
3439	{
3440	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3441	return VINF_PGM_SYNC_CR3;
3442	}
3443	# endif
3444	return VINF_SUCCESS;
3445	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3446	}
3447
3448
3449
3450
3451	#ifdef VBOX_STRICT
3452	#ifdef IN_RC
3453	# undef AssertMsgFailed
3454	# define AssertMsgFailed Log
3455	#endif
3456	#ifdef IN_RING3
3457	# include <VBox/dbgf.h>
3458
3459	/**
3460	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3461	*
3462	* @returns VBox status code (VINF_SUCCESS).
3463	* @param cr3 The root of the hierarchy.
3464	* @param crr The cr4, only PAE and PSE is currently used.
3465	* @param fLongMode Set if long mode, false if not long mode.
3466	* @param cMaxDepth Number of levels to dump.
3467	* @param pHlp Pointer to the output functions.
3468	*/
3469	RT_C_DECLS_BEGIN
3470	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3471	RT_C_DECLS_END
3472
3473	#endif
3474
3475	/**
3476	* Checks that the shadow page table is in sync with the guest one.
3477	*
3478	* @returns The number of errors.
3479	* @param pVM The virtual machine.
3480	* @param pVCpu The VMCPU handle.
3481	* @param cr3 Guest context CR3 register
3482	* @param cr4 Guest context CR4 register
3483	* @param GCPtr Where to start. Defaults to 0.
3484	* @param cb How much to check. Defaults to everything.
3485	*/
3486	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3487	{
3488	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3489	return 0;
3490	#else
3491	unsigned cErrors = 0;
3492	PVM pVM = pVCpu->CTX_SUFF(pVM);
3493	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3494
3495	#if PGM_GST_TYPE == PGM_TYPE_PAE
3496	/** @todo currently broken; crashes below somewhere */
3497	AssertFailed();
3498	#endif
3499
3500	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3501	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3502	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3503
3504	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3505	bool fBigPagesSupported = true;
3506	# else
3507	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3508	# endif
3509	PPGMCPU pPGM = &pVCpu->pgm.s;
3510	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3511	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3512	# ifndef IN_RING0
3513	RTHCPHYS HCPhys; /* general usage. */
3514	# endif
3515	int rc;
3516
3517	/*
3518	* Check that the Guest CR3 and all its mappings are correct.
3519	*/
3520	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3521	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3522	false);
3523	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3524	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3525	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3526	# else
3527	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3528	# endif
3529	AssertRCReturn(rc, 1);
3530	HCPhys = NIL_RTHCPHYS;
3531	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3532	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3533	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3534	pgmGstGet32bitPDPtr(pPGM);
3535	RTGCPHYS GCPhys;
3536	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3537	AssertRCReturn(rc, 1);
3538	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3539	# endif
3540	# endif /* !IN_RING0 */
3541
3542	/*
3543	* Get and check the Shadow CR3.
3544	*/
3545	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3546	unsigned cPDEs = X86_PG_ENTRIES;
3547	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3548	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3549	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3550	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3551	# else
3552	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3553	# endif
3554	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3555	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3556	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3557	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3558	# endif
3559	if (cb != ~(RTGCPTR)0)
3560	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3561
3562	/** @todo call the other two PGMAssert() functions. /
3563
3564	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3565	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3566
3567	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3568	{
3569	PPGMPOOLPAGE pShwPdpt = NULL;
3570	PX86PML4E pPml4eSrc;
3571	PX86PML4E pPml4eDst;
3572	RTGCPHYS GCPhysPdptSrc;
3573
3574	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3575	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3576
3577	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3578	if (!pPml4eDst->n.u1Present)
3579	{
3580	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3581	continue;
3582	}
3583
3584	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3585	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3586
3587	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3588	{
3589	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3590	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3591	cErrors++;
3592	continue;
3593	}
3594
3595	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3596	{
3597	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3598	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3599	cErrors++;
3600	continue;
3601	}
3602
3603	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3604	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3605	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3606	{
3607	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3608	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3609	cErrors++;
3610	continue;
3611	}
3612	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3613	{
3614	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3615
3616	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3617	/*
3618	* Check the PDPTEs too.
3619	*/
3620	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3621
3622	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3623	{
3624	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3625	PPGMPOOLPAGE pShwPde = NULL;
3626	PX86PDPE pPdpeDst;
3627	RTGCPHYS GCPhysPdeSrc;
3628	# if PGM_GST_TYPE == PGM_TYPE_PAE
3629	X86PDPE PdpeSrc;
3630	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3631	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3632	# else
3633	PX86PML4E pPml4eSrc;
3634	X86PDPE PdpeSrc;
3635	PX86PDPT pPdptDst;
3636	PX86PDPAE pPDDst;
3637	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3638
3639	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3640	if (rc != VINF_SUCCESS)
3641	{
3642	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3643	GCPtr += 512 * _2M;
3644	continue; /* next PDPTE */
3645	}
3646	Assert(pPDDst);
3647	# endif
3648	Assert(iPDSrc == 0);
3649
3650	pPdpeDst = &pPdptDst->a[iPdpt];
3651
3652	if (!pPdpeDst->n.u1Present)
3653	{
3654	GCPtr += 512 * _2M;
3655	continue; /* next PDPTE */
3656	}
3657
3658	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3659	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3660
3661	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3662	{
3663	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3664	GCPtr += 512 * _2M;
3665	cErrors++;
3666	continue;
3667	}
3668
3669	if (GCPhysPdeSrc != pShwPde->GCPhys)
3670	{
3671	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3672	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3673	# else
3674	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3675	# endif
3676	GCPtr += 512 * _2M;
3677	cErrors++;
3678	continue;
3679	}
3680
3681	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3682	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3683	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3684	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3685	{
3686	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3687	GCPtr += 512 * _2M;
3688	cErrors++;
3689	continue;
3690	}
3691	# endif
3692
3693	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3694	{
3695	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3696	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3697	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3698	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3699	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3700	# endif
3701	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3702	/*
3703	* Iterate the shadow page directory.
3704	*/
3705	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3706	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3707
3708	for (;
3709	iPDDst < cPDEs;
3710	iPDDst++, GCPtr += cIncrement)
3711	{
3712	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3713	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3714	# else
3715	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3716	# endif
3717	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3718	{
3719	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3720	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3721	{
3722	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3723	cErrors++;
3724	continue;
3725	}
3726	}
3727	else if ( (PdeDst.u & X86_PDE_P)
3728	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3729	)
3730	{
3731	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3732	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3733	if (!pPoolPage)
3734	{
3735	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3736	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3737	cErrors++;
3738	continue;
3739	}
3740	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3741
3742	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3743	{
3744	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3745	GCPtr, (uint64_t)PdeDst.u));
3746	cErrors++;
3747	}
3748
3749	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3750	{
3751	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3752	GCPtr, (uint64_t)PdeDst.u));
3753	cErrors++;
3754	}
3755
3756	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3757	if (!PdeSrc.n.u1Present)
3758	{
3759	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3760	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3761	cErrors++;
3762	continue;
3763	}
3764
3765	if ( !PdeSrc.b.u1Size
3766	\|\| !fBigPagesSupported)
3767	{
3768	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3769	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3770	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3771	# endif
3772	}
3773	else
3774	{
3775	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3776	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3777	{
3778	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3779	GCPtr, (uint64_t)PdeSrc.u));
3780	cErrors++;
3781	continue;
3782	}
3783	# endif
3784	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3785	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3786	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3787	# endif
3788	}
3789
3790	if ( pPoolPage->enmKind
3791	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3792	{
3793	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3794	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3795	cErrors++;
3796	}
3797
3798	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3799	if (!pPhysPage)
3800	{
3801	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3802	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3803	cErrors++;
3804	continue;
3805	}
3806
3807	if (GCPhysGst != pPoolPage->GCPhys)
3808	{
3809	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3810	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3811	cErrors++;
3812	continue;
3813	}
3814
3815	if ( !PdeSrc.b.u1Size
3816	\|\| !fBigPagesSupported)
3817	{
3818	/*
3819	* Page Table.
3820	*/
3821	const GSTPT *pPTSrc;
3822	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3823	if (RT_FAILURE(rc))
3824	{
3825	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3826	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3827	cErrors++;
3828	continue;
3829	}
3830	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3831	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3832	{
3833	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3834	// (This problem will go away when/if we shadow multiple CR3s.)
3835	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3836	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3837	cErrors++;
3838	continue;
3839	}
3840	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3841	{
3842	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3843	GCPtr, (uint64_t)PdeDst.u));
3844	cErrors++;
3845	continue;
3846	}
3847
3848	/* iterate the page table. */
3849	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3850	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3851	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3852	# else
3853	const unsigned offPTSrc = 0;
3854	# endif
3855	for (unsigned iPT = 0, off = 0;
3856	iPT < RT_ELEMENTS(pPTDst->a);
3857	iPT++, off += PAGE_SIZE)
3858	{
3859	const SHWPTE PteDst = pPTDst->a[iPT];
3860
3861	/* skip not-present entries. */
3862	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3863	continue;
3864	Assert(PteDst.n.u1Present);
3865
3866	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3867	if (!PteSrc.n.u1Present)
3868	{
3869	# ifdef IN_RING3
3870	PGMAssertHandlerAndFlagsInSync(pVM);
3871	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3872	# endif
3873	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3874	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3875	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3876	cErrors++;
3877	continue;
3878	}
3879
3880	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3881	# if 1 /** @todo sync accessed bit properly... */
3882	fIgnoreFlags \|= X86_PTE_A;
3883	# endif
3884
3885	/* match the physical addresses */
3886	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3887	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3888
3889	# ifdef IN_RING3
3890	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3891	if (RT_FAILURE(rc))
3892	{
3893	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3894	{
3895	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3896	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3897	cErrors++;
3898	continue;
3899	}
3900	}
3901	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3902	{
3903	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3904	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3905	cErrors++;
3906	continue;
3907	}
3908	# endif
3909
3910	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3911	if (!pPhysPage)
3912	{
3913	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3914	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3915	{
3916	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3917	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3918	cErrors++;
3919	continue;
3920	}
3921	# endif
3922	if (PteDst.n.u1Write)
3923	{
3924	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3925	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3926	cErrors++;
3927	}
3928	fIgnoreFlags \|= X86_PTE_RW;
3929	}
3930	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3931	{
3932	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3933	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3934	cErrors++;
3935	continue;
3936	}
3937
3938	/* flags */
3939	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3940	{
3941	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3942	{
3943	if (PteDst.n.u1Write)
3944	{
3945	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3946	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3947	cErrors++;
3948	continue;
3949	}
3950	fIgnoreFlags \|= X86_PTE_RW;
3951	}
3952	else
3953	{
3954	if (PteDst.n.u1Present)
3955	{
3956	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3957	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3958	cErrors++;
3959	continue;
3960	}
3961	fIgnoreFlags \|= X86_PTE_P;
3962	}
3963	}
3964	else
3965	{
3966	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3967	{
3968	if (PteDst.n.u1Write)
3969	{
3970	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3971	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3972	cErrors++;
3973	continue;
3974	}
3975	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3976	{
3977	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3978	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3979	cErrors++;
3980	continue;
3981	}
3982	if (PteDst.n.u1Dirty)
3983	{
3984	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3985	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3986	cErrors++;
3987	}
3988	# if 0 /** @todo sync access bit properly... */
3989	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3990	{
3991	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3992	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3993	cErrors++;
3994	}
3995	fIgnoreFlags \|= X86_PTE_RW;
3996	# else
3997	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3998	# endif
3999	}
4000	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4001	{
4002	/* access bit emulation (not implemented). */
4003	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4004	{
4005	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4006	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4007	cErrors++;
4008	continue;
4009	}
4010	if (!PteDst.n.u1Accessed)
4011	{
4012	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4013	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4014	cErrors++;
4015	}
4016	fIgnoreFlags \|= X86_PTE_P;
4017	}
4018	# ifdef DEBUG_sandervl
4019	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4020	# endif
4021	}
4022
4023	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4024	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4025	)
4026	{
4027	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4029	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4030	cErrors++;
4031	continue;
4032	}
4033	} /* foreach PTE */
4034	}
4035	else
4036	{
4037	/*
4038	* Big Page.
4039	*/
4040	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4041	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4042	{
4043	if (PdeDst.n.u1Write)
4044	{
4045	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4046	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4047	cErrors++;
4048	continue;
4049	}
4050	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4051	{
4052	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4053	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4054	cErrors++;
4055	continue;
4056	}
4057	# if 0 /** @todo sync access bit properly... */
4058	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4059	{
4060	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4061	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4062	cErrors++;
4063	}
4064	fIgnoreFlags \|= X86_PTE_RW;
4065	# else
4066	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4067	# endif
4068	}
4069	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4070	{
4071	/* access bit emulation (not implemented). */
4072	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4073	{
4074	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4075	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4076	cErrors++;
4077	continue;
4078	}
4079	if (!PdeDst.n.u1Accessed)
4080	{
4081	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4082	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4083	cErrors++;
4084	}
4085	fIgnoreFlags \|= X86_PTE_P;
4086	}
4087
4088	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4089	{
4090	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4091	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4092	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4093	cErrors++;
4094	}
4095
4096	/* iterate the page table. */
4097	for (unsigned iPT = 0, off = 0;
4098	iPT < RT_ELEMENTS(pPTDst->a);
4099	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4100	{
4101	const SHWPTE PteDst = pPTDst->a[iPT];
4102
4103	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4104	{
4105	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4106	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4107	cErrors++;
4108	}
4109
4110	/* skip not-present entries. */
4111	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4112	continue;
4113
4114	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4115
4116	/* match the physical addresses */
4117	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4118
4119	# ifdef IN_RING3
4120	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4121	if (RT_FAILURE(rc))
4122	{
4123	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4124	{
4125	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4126	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4127	cErrors++;
4128	}
4129	}
4130	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4131	{
4132	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4133	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4134	cErrors++;
4135	continue;
4136	}
4137	# endif
4138	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4139	if (!pPhysPage)
4140	{
4141	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4142	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4143	{
4144	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4145	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4146	cErrors++;
4147	continue;
4148	}
4149	# endif
4150	if (PteDst.n.u1Write)
4151	{
4152	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4153	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4154	cErrors++;
4155	}
4156	fIgnoreFlags \|= X86_PTE_RW;
4157	}
4158	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4159	{
4160	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4161	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4162	cErrors++;
4163	continue;
4164	}
4165
4166	/* flags */
4167	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4168	{
4169	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4170	{
4171	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4172	{
4173	if (PteDst.n.u1Write)
4174	{
4175	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4176	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4177	cErrors++;
4178	continue;
4179	}
4180	fIgnoreFlags \|= X86_PTE_RW;
4181	}
4182	}
4183	else
4184	{
4185	if (PteDst.n.u1Present)
4186	{
4187	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4188	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4189	cErrors++;
4190	continue;
4191	}
4192	fIgnoreFlags \|= X86_PTE_P;
4193	}
4194	}
4195
4196	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4197	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4198	)
4199	{
4200	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4201	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4202	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4203	cErrors++;
4204	continue;
4205	}
4206	} /* for each PTE */
4207	}
4208	}
4209	/* not present */
4210
4211	} /* for each PDE */
4212
4213	} /* for each PDPTE */
4214
4215	} /* for each PML4E */
4216
4217	# ifdef DEBUG
4218	if (cErrors)
4219	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4220	# endif
4221
4222	#endif /* GST == 32BIT, PAE or AMD64 */
4223	return cErrors;
4224
4225	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4226	}
4227	#endif /* VBOX_STRICT */
4228
4229
4230	/**
4231	* Sets up the CR3 for shadow paging
4232	*
4233	* @returns Strict VBox status code.
4234	* @retval VINF_SUCCESS.
4235	*
4236	* @param pVCpu The VMCPU handle.
4237	* @param GCPhysCR3 The physical address in the CR3 register.
4238	*/
4239	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4240	{
4241	PVM pVM = pVCpu->CTX_SUFF(pVM);
4242
4243	/* Update guest paging info. */
4244	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4245	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4246	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4247
4248	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4249
4250	/*
4251	* Map the page CR3 points at.
4252	*/
4253	RTHCPTR HCPtrGuestCR3;
4254	RTHCPHYS HCPhysGuestCR3;
4255	pgmLock(pVM);
4256	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4257	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4258	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4259	/** @todo this needs some reworking wrt. locking. */
4260	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4261	HCPtrGuestCR3 = NIL_RTHCPTR;
4262	int rc = VINF_SUCCESS;
4263	# else
4264	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4265	# endif
4266	pgmUnlock(pVM);
4267	if (RT_SUCCESS(rc))
4268	{
4269	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4270	if (RT_SUCCESS(rc))
4271	{
4272	# ifdef IN_RC
4273	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4274	# endif
4275	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4276	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4277	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4278	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4279	# endif
4280	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4281
4282	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4283	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4284	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4285	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4286	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4287	# endif
4288	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4289	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4290
4291	/*
4292	* Map the 4 PDs too.
4293	*/
4294	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4295	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4296	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4297	{
4298	if (pGuestPDPT->a[i].n.u1Present)
4299	{
4300	RTHCPTR HCPtr;
4301	RTHCPHYS HCPhys;
4302	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4303	pgmLock(pVM);
4304	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4305	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4306	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4307	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4308	HCPtr = NIL_RTHCPTR;
4309	int rc2 = VINF_SUCCESS;
4310	# else
4311	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4312	# endif
4313	pgmUnlock(pVM);
4314	if (RT_SUCCESS(rc2))
4315	{
4316	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4317	AssertRCReturn(rc, rc);
4318
4319	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4320	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4321	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4322	# endif
4323	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4324	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4325	# ifdef IN_RC
4326	PGM_INVL_PG(pVCpu, GCPtr);
4327	# endif
4328	continue;
4329	}
4330	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4331	}
4332
4333	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4334	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4335	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4336	# endif
4337	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4338	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4339	# ifdef IN_RC
4340	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4341	# endif
4342	}
4343
4344	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4345	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4346	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4347	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4348	# endif
4349	# endif
4350	}
4351	else
4352	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4353	}
4354	else
4355	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4356
4357	#else /* prot/real stub */
4358	int rc = VINF_SUCCESS;
4359	#endif
4360
4361	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4362	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4363	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4364	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4365	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4366	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4367
4368	Assert(!HWACCMIsNestedPagingActive(pVM));
4369
4370	/*
4371	* Update the shadow root page as well since that's not fixed.
4372	*/
4373	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4374	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4375	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4376	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4377	PPGMPOOLPAGE pNewShwPageCR3;
4378
4379	pgmLock(pVM);
4380
4381	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4382	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4383	AssertFatalRC(rc);
4384	rc = VINF_SUCCESS;
4385
4386	# ifdef IN_RC
4387	/*
4388	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4389	* state will be inconsistent! Flush important things now while
4390	* we still can and then make sure there are no ring-3 calls.
4391	*/
4392	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4393	VMMRZCallRing3Disable(pVCpu);
4394	# endif
4395
4396	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4397	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4398	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4399	# ifdef IN_RING0
4400	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4401	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4402	# elif defined(IN_RC)
4403	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4404	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4405	# else
4406	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4407	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4408	# endif
4409
4410	# ifndef PGM_WITHOUT_MAPPINGS
4411	/*
4412	* Apply all hypervisor mappings to the new CR3.
4413	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4414	* make sure we check for conflicts in the new CR3 root.
4415	*/
4416	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4417	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4418	# endif
4419	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4420	AssertRCReturn(rc, rc);
4421	# endif
4422
4423	/* Set the current hypervisor CR3. */
4424	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4425	SELMShadowCR3Changed(pVM, pVCpu);
4426
4427	# ifdef IN_RC
4428	/* NOTE: The state is consistent again. */
4429	VMMRZCallRing3Enable(pVCpu);
4430	# endif
4431
4432	/* Clean up the old CR3 root. */
4433	if ( pOldShwPageCR3
4434	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4435	{
4436	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4437	# ifndef PGM_WITHOUT_MAPPINGS
4438	/* Remove the hypervisor mappings from the shadow page table. */
4439	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4440	# endif
4441	/* Mark the page as unlocked; allow flushing again. */
4442	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4443
4444	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4445	}
4446	pgmUnlock(pVM);
4447	# endif
4448
4449	return rc;
4450	}
4451
4452	/**
4453	* Unmaps the shadow CR3.
4454	*
4455	* @returns VBox status, no specials.
4456	* @param pVCpu The VMCPU handle.
4457	*/
4458	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4459	{
4460	LogFlow(("UnmapCR3\n"));
4461
4462	int rc = VINF_SUCCESS;
4463	PVM pVM = pVCpu->CTX_SUFF(pVM);
4464
4465	/*
4466	* Update guest paging info.
4467	*/
4468	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4469	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4470	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4471	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4472	# endif
4473	pVCpu->pgm.s.pGst32BitPdRC = 0;
4474
4475	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4476	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4477	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4478	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4479	# endif
4480	pVCpu->pgm.s.pGstPaePdptRC = 0;
4481	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4482	{
4483	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4484	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4485	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4486	# endif
4487	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4488	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4489	}
4490
4491	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4492	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4493	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4494	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4495	# endif
4496
4497	#else /* prot/real mode stub */
4498	/* nothing to do */
4499	#endif
4500
4501	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4502	/*
4503	* Update shadow paging info.
4504	*/
4505	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4506	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4507	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4508
4509	# if PGM_GST_TYPE != PGM_TYPE_REAL
4510	Assert(!HWACCMIsNestedPagingActive(pVM));
4511	# endif
4512
4513	pgmLock(pVM);
4514
4515	# ifndef PGM_WITHOUT_MAPPINGS
4516	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4517	/* Remove the hypervisor mappings from the shadow page table. */
4518	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4519	# endif
4520
4521	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4522	{
4523	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4524
4525	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4526
4527	/* Mark the page as unlocked; allow flushing again. */
4528	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4529
4530	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4531	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4532	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4533	pVCpu->pgm.s.pShwPageCR3RC = 0;
4534	pVCpu->pgm.s.iShwUser = 0;
4535	pVCpu->pgm.s.iShwUserTable = 0;
4536	}
4537	pgmUnlock(pVM);
4538	# endif
4539	#endif /* !IN_RC*/
4540
4541	return rc;
4542	}
4543

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 22337

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