PGMAllBth.h@ 22512

Last change on this file since 22512 was 22473, checked in by vboxsync, 15 years ago
Disabled experiment with optimized dirty PTs.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 197.2 KB

Line
1	/* $Id: PGMAllBth.h 22473 2009-08-26 14:51:50Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	RT_C_DECLS_BEGIN
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
43	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
44	RT_C_DECLS_END
45
46
47	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
48	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
49	# error "Invalid combination; PAE guest implies PAE shadow"
50	#endif
51
52	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
53	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
54	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
55	#endif
56
57	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
58	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
59	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
60	#endif
61
62	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
63	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
64	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
65	#endif
66
67	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
68	# define PGM_WITHOUT_MAPPINGS
69	#endif
70
71
72	#ifndef IN_RING3
73	/**
74	* #PF Handler for raw-mode guest execution.
75	*
76	* @returns VBox status code (appropriate for trap handling and GC return).
77	*
78	* @param pVCpu VMCPU Handle.
79	* @param uErr The trap error code.
80	* @param pRegFrame Trap register frame.
81	* @param pvFault The fault address.
82	*/
83	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
84	{
85	PVM pVM = pVCpu->CTX_SUFF(pVM);
86
87	# if defined(IN_RC) && defined(VBOX_STRICT)
88	PGMDynCheckLocks(pVM);
89	# endif
90
91	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
92	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
93	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
94
95	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
96	/*
97	* Hide the instruction fetch trap indicator for now.
98	*/
99	/** @todo NXE will change this and we must fix NXE in the switcher too! */
100	if (uErr & X86_TRAP_PF_ID)
101	{
102	uErr &= ~X86_TRAP_PF_ID;
103	TRPMSetErrorCode(pVCpu, uErr);
104	}
105	# endif
106
107	/*
108	* Get PDs.
109	*/
110	int rc;
111	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
112	# if PGM_GST_TYPE == PGM_TYPE_32BIT
113	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
114	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
115
116	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
117
118	# if PGM_GST_TYPE == PGM_TYPE_PAE
119	unsigned iPDSrc = 0; /* initialized to shut up gcc */
120	X86PDPE PdpeSrc;
121	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
122
123	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
124	unsigned iPDSrc = 0; /* initialized to shut up gcc */
125	PX86PML4E pPml4eSrc;
126	X86PDPE PdpeSrc;
127	PGSTPD pPDSrc;
128
129	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
130	Assert(pPml4eSrc);
131	# endif
132
133	/* Quick check for a valid guest trap. (PAE & AMD64) */
134	if (!pPDSrc)
135	{
136	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
137	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# else
139	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
140	# endif
141	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
142	TRPMSetErrorCode(pVCpu, uErr);
143	return VINF_EM_RAW_GUEST_TRAP;
144	}
145	# endif
146
147	# else /* !PGM_WITH_PAGING */
148	PGSTPD pPDSrc = NULL;
149	const unsigned iPDSrc = 0;
150	# endif /* !PGM_WITH_PAGING */
151
152	/* Fetch the guest PDE */
153	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
154	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
155	# else
156	GSTPDE PdeSrc;
157	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
158	PdeSrc.n.u1Present = 1;
159	PdeSrc.n.u1Write = 1;
160	PdeSrc.n.u1Accessed = 1;
161	PdeSrc.n.u1User = 1;
162	# endif
163
164	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
165	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
166	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
167
168	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
169	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
170
171	PX86PDPAE pPDDst;
172	# if PGM_GST_TYPE != PGM_TYPE_PAE
173	X86PDPE PdpeSrc;
174
175	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
176	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
177	# endif
178	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
179	if (rc != VINF_SUCCESS)
180	{
181	AssertRC(rc);
182	return rc;
183	}
184	Assert(pPDDst);
185
186	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
187	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
188	PX86PDPAE pPDDst;
189	# if PGM_GST_TYPE == PGM_TYPE_PROT
190	/* AMD-V nested paging */
191	X86PML4E Pml4eSrc;
192	X86PDPE PdpeSrc;
193	PX86PML4E pPml4eSrc = &Pml4eSrc;
194
195	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
196	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
197	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
198	# endif
199
200	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
201	if (rc != VINF_SUCCESS)
202	{
203	AssertRC(rc);
204	return rc;
205	}
206	Assert(pPDDst);
207
208	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
209	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
210	PEPTPD pPDDst;
211
212	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
213	if (rc != VINF_SUCCESS)
214	{
215	AssertRC(rc);
216	return rc;
217	}
218	Assert(pPDDst);
219	# endif
220
221	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
222	/*
223	* If we successfully correct the write protection fault due to dirty bit
224	* tracking, or this page fault is a genuine one, then return immediately.
225	*/
226	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
227	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
228	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
229	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
230	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
231	{
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
233	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
234	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
235	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
236	}
237
238	# if 0 /* rarely useful; leave for debugging. */
239	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
240	# endif
241	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
242
243	/*
244	* A common case is the not-present error caused by lazy page table syncing.
245	*
246	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
247	* so we can safely assume that the shadow PT is present when calling SyncPage later.
248	*
249	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
250	* of mapping conflict and defer to SyncCR3 in R3.
251	* (Again, we do NOT support access handlers for non-present guest pages.)
252	*
253	*/
254	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
255	&& !pPDDst->a[iPDDst].n.u1Present
256	&& PdeSrc.n.u1Present
257	)
258	{
259	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
260	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
261	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
263	if (RT_SUCCESS(rc))
264	{
265	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
266	return rc;
267	}
268	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
269	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
270	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
271	return VINF_PGM_SYNC_CR3;
272	}
273
274	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
275	/*
276	* Check if this address is within any of our mappings.
277	*
278	* This is very fast and it's gonna save us a bit of effort below and prevent
279	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
280	* (BTW, it's impossible to have physical access handlers in a mapping.)
281	*/
282	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
283	{
284	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
285	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
286	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
287	{
288	if (pvFault < pMapping->GCPtr)
289	break;
290	if (pvFault - pMapping->GCPtr < pMapping->cb)
291	{
292	/*
293	* The first thing we check is if we've got an undetected conflict.
294	*/
295	if (!pVM->pgm.s.fMappingsFixed)
296	{
297	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
298	while (iPT-- > 0)
299	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
300	{
301	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
302	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
303	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
304	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
305	return VINF_PGM_SYNC_CR3;
306	}
307	}
308
309	/*
310	* Check if the fault address is in a virtual page access handler range.
311	*/
312	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
313	if ( pCur
314	&& pvFault - pCur->Core.Key < pCur->cb
315	&& uErr & X86_TRAP_PF_RW)
316	{
317	# ifdef IN_RC
318	STAM_PROFILE_START(&pCur->Stat, h);
319	pgmUnlock(pVM);
320	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
321	pgmLock(pVM);
322	STAM_PROFILE_STOP(&pCur->Stat, h);
323	# else
324	AssertFailed();
325	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
326	# endif
327	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
328	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
329	return rc;
330	}
331
332	/*
333	* Pretend we're not here and let the guest handle the trap.
334	*/
335	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
336	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
337	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
338	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
339	return VINF_EM_RAW_GUEST_TRAP;
340	}
341	}
342	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
343	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
344	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
345
346	/*
347	* Check if this fault address is flagged for special treatment,
348	* which means we'll have to figure out the physical address and
349	* check flags associated with it.
350	*
351	* ASSUME that we can limit any special access handling to pages
352	* in page tables which the guest believes to be present.
353	*/
354	if (PdeSrc.n.u1Present)
355	{
356	RTGCPHYS GCPhys = NIL_RTGCPHYS;
357
358	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
359	# if PGM_GST_TYPE == PGM_TYPE_AMD64
360	bool fBigPagesSupported = true;
361	# else
362	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
363	# endif
364	if ( PdeSrc.b.u1Size
365	&& fBigPagesSupported)
366	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
367	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
368	else
369	{
370	PGSTPT pPTSrc;
371	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
372	if (RT_SUCCESS(rc))
373	{
374	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
375	if (pPTSrc->a[iPTESrc].n.u1Present)
376	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
377	}
378	}
379	# else
380	/* No paging so the fault address is the physical address */
381	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
382	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
383
384	/*
385	* If we have a GC address we'll check if it has any flags set.
386	*/
387	if (GCPhys != NIL_RTGCPHYS)
388	{
389	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
390
391	PPGMPAGE pPage;
392	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
393	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
394	{
395	if ( PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage)
396	\|\| PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage))
397	{
398	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
399	{
400	/*
401	* Physical page access handler.
402	*/
403	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
404	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
405	if (pCur)
406	{
407	# ifdef PGM_SYNC_N_PAGES
408	/*
409	* If the region is write protected and we got a page not present fault, then sync
410	* the pages. If the fault was caused by a read, then restart the instruction.
411	* In case of write access continue to the GC write handler.
412	*
413	* ASSUMES that there is only one handler per page or that they have similar write properties.
414	*/
415	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
416	&& !(uErr & X86_TRAP_PF_P))
417	{
418	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
419	if ( RT_FAILURE(rc)
420	\|\| !(uErr & X86_TRAP_PF_RW)
421	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
422	{
423	AssertRC(rc);
424	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
425	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
426	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
427	return rc;
428	}
429	}
430	# endif
431
432	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
433	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
434	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
435
436	# if defined(IN_RC) \|\| defined(IN_RING0)
437	if (pCur->CTX_SUFF(pfnHandler))
438	{
439	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
440	# ifdef IN_RING0
441	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
442	# else
443	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
444	# endif
445	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
446	void *pvUser = pCur->CTX_SUFF(pvUser);
447
448	STAM_PROFILE_START(&pCur->Stat, h);
449	if (fLeaveLock)
450	pgmUnlock(pVM); /* @todo: Not entirely safe. */
451
452	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
453	if (fLeaveLock)
454	pgmLock(pVM);
455	# ifdef VBOX_WITH_STATISTICS
456	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
457	if (pCur)
458	STAM_PROFILE_STOP(&pCur->Stat, h);
459	# else
460	pCur = NULL; /* might be invalid by now. */
461	# endif
462
463	}
464	else
465	# endif
466	rc = VINF_EM_RAW_EMULATE_INSTR;
467
468	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
469	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
470	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
471	return rc;
472	}
473	}
474	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
475	else
476	{
477	# ifdef PGM_SYNC_N_PAGES
478	/*
479	* If the region is write protected and we got a page not present fault, then sync
480	* the pages. If the fault was caused by a read, then restart the instruction.
481	* In case of write access continue to the GC write handler.
482	*/
483	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
484	&& !(uErr & X86_TRAP_PF_P))
485	{
486	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
487	if ( RT_FAILURE(rc)
488	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
489	\|\| !(uErr & X86_TRAP_PF_RW))
490	{
491	AssertRC(rc);
492	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
493	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
494	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
495	return rc;
496	}
497	}
498	# endif
499	/*
500	* Ok, it's an virtual page access handler.
501	*
502	* Since it's faster to search by address, we'll do that first
503	* and then retry by GCPhys if that fails.
504	*/
505	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
506	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
507	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
508	*/
509	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
510	if (pCur)
511	{
512	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
513	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
514	\|\| !(uErr & X86_TRAP_PF_P)
515	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
516	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
517
518	if ( pvFault - pCur->Core.Key < pCur->cb
519	&& ( uErr & X86_TRAP_PF_RW
520	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
521	{
522	# ifdef IN_RC
523	STAM_PROFILE_START(&pCur->Stat, h);
524	pgmUnlock(pVM);
525	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
526	pgmLock(pVM);
527	STAM_PROFILE_STOP(&pCur->Stat, h);
528	# else
529	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
530	# endif
531	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
532	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
533	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
534	return rc;
535	}
536	/* Unhandled part of a monitored page */
537	}
538	else
539	{
540	/* Check by physical address. */
541	PPGMVIRTHANDLER pCur;
542	unsigned iPage;
543	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
544	&pCur, &iPage);
545	Assert(RT_SUCCESS(rc) \|\| !pCur);
546	if ( pCur
547	&& ( uErr & X86_TRAP_PF_RW
548	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
549	{
550	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
551	# ifdef IN_RC
552	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
553	Assert(off < pCur->cb);
554	STAM_PROFILE_START(&pCur->Stat, h);
555	pgmUnlock(pVM);
556	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
557	pgmLock(pVM);
558	STAM_PROFILE_STOP(&pCur->Stat, h);
559	# else
560	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
561	# endif
562	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
563	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
564	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
565	return rc;
566	}
567	}
568	}
569	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
570
571	/*
572	* There is a handled area of the page, but this fault doesn't belong to it.
573	* We must emulate the instruction.
574	*
575	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
576	* we first check if this was a page-not-present fault for a page with only
577	* write access handlers. Restart the instruction if it wasn't a write access.
578	*/
579	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
580
581	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
582	&& !(uErr & X86_TRAP_PF_P))
583	{
584	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
585	if ( RT_FAILURE(rc)
586	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
587	\|\| !(uErr & X86_TRAP_PF_RW))
588	{
589	AssertRC(rc);
590	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
591	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
592	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
593	return rc;
594	}
595	}
596
597	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
598	* It's writing to an unhandled part of the LDT page several million times.
599	*/
600	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
601	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
602	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
603	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
604	return rc;
605	} /* if any kind of handler */
606
607	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
608	if (uErr & X86_TRAP_PF_P)
609	{
610	/*
611	* The page isn't marked, but it might still be monitored by a virtual page access handler.
612	* (ASSUMES no temporary disabling of virtual handlers.)
613	*/
614	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
615	* we should correct both the shadow page table and physical memory flags, and not only check for
616	* accesses within the handler region but for access to pages with virtual handlers. */
617	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
618	if (pCur)
619	{
620	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
621	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
622	\|\| !(uErr & X86_TRAP_PF_P)
623	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
624	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
625
626	if ( pvFault - pCur->Core.Key < pCur->cb
627	&& ( uErr & X86_TRAP_PF_RW
628	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
629	{
630	# ifdef IN_RC
631	STAM_PROFILE_START(&pCur->Stat, h);
632	pgmUnlock(pVM);
633	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
634	pgmLock(pVM);
635	STAM_PROFILE_STOP(&pCur->Stat, h);
636	# else
637	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
638	# endif
639	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
640	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
641	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
642	return rc;
643	}
644	}
645	}
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647	}
648	else
649	{
650	/*
651	* When the guest accesses invalid physical memory (e.g. probing
652	* of RAM or accessing a remapped MMIO range), then we'll fall
653	* back to the recompiler to emulate the instruction.
654	*/
655	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
656	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
657	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
658	return VINF_EM_RAW_EMULATE_INSTR;
659	}
660
661	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
662
663	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
664	/*
665	* We are here only if page is present in Guest page tables and
666	* trap is not handled by our handlers.
667	*
668	* Check it for page out-of-sync situation.
669	*/
670	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
671
672	if (!(uErr & X86_TRAP_PF_P))
673	{
674	/*
675	* Page is not present in our page tables.
676	* Try to sync it!
677	* BTW, fPageShw is invalid in this branch!
678	*/
679	if (uErr & X86_TRAP_PF_US)
680	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
681	else /* supervisor */
682	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
683
684	# if defined(LOG_ENABLED) && !defined(IN_RING0)
685	RTGCPHYS GCPhys;
686	uint64_t fPageGst;
687	PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
688	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%RGp scan=%d\n",
689	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)));
690	# endif /* LOG_ENABLED */
691
692	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
693	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
694	{
695	uint64_t fPageGst;
696	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
697	if ( RT_SUCCESS(rc)
698	&& !(fPageGst & X86_PTE_US))
699	{
700	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
701	if ( pvFault == (RTGCPTR)pRegFrame->eip
702	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
703	# ifdef CSAM_DETECT_NEW_CODE_PAGES
704	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
705	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)pRegFrame->eip)) /* any new code we encounter here */
706	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
707	)
708	{
709	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
710	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
711	if (rc != VINF_SUCCESS)
712	{
713	/*
714	* CSAM needs to perform a job in ring 3.
715	*
716	* Sync the page before going to the host context; otherwise we'll end up in a loop if
717	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
718	*/
719	LogFlow(("CSAM ring 3 job\n"));
720	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
721	AssertRC(rc2);
722
723	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
724	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
725	return rc;
726	}
727	}
728	# ifdef CSAM_DETECT_NEW_CODE_PAGES
729	else if ( uErr == X86_TRAP_PF_RW
730	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
731	&& pRegFrame->ecx < 0x10000)
732	{
733	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
734	* to detect loading of new code pages.
735	*/
736
737	/*
738	* Decode the instruction.
739	*/
740	RTGCPTR PC;
741	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
742	if (rc == VINF_SUCCESS)
743	{
744	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
745	uint32_t cbOp;
746	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
747
748	/* For now we'll restrict this to rep movsw/d instructions */
749	if ( rc == VINF_SUCCESS
750	&& pDis->pCurInstr->opcode == OP_MOVSWD
751	&& (pDis->prefix & PREFIX_REP))
752	{
753	CSAMMarkPossibleCodePage(pVM, pvFault);
754	}
755	}
756	}
757	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
758
759	/*
760	* Mark this page as safe.
761	*/
762	/** @todo not correct for pages that contain both code and data!! */
763	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
764	CSAMMarkPage(pVM, (RTRCPTR)pvFault, true);
765	}
766	}
767	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
768	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
769	if (RT_SUCCESS(rc))
770	{
771	/* The page was successfully synced, return to the guest. */
772	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
773	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
774	return VINF_SUCCESS;
775	}
776	}
777	else /* uErr & X86_TRAP_PF_P: */
778	{
779	/*
780	* Write protected pages are make writable when the guest makes the first
781	* write to it. This happens for pages that are shared, write monitored
782	* and not yet allocated.
783	*
784	* Also, a side effect of not flushing global PDEs are out of sync pages due
785	* to physical monitored regions, that are no longer valid.
786	* Assume for now it only applies to the read/write flag.
787	*/
788	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
789	{
790	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
791	{
792	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
793	GCPhys, pPage, pvFault, uErr));
794	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
795	if (rc != VINF_SUCCESS)
796	{
797	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
798	return rc;
799	}
800	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
801	return VINF_EM_NO_MEMORY;
802	}
803
804	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
805	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
806	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
807	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG))
808	{
809	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
810	uint64_t fPageGst;
811	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
812	if ( RT_SUCCESS(rc)
813	&& !(fPageGst & X86_PTE_RW))
814	{
815	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
816	if (RT_SUCCESS(rc))
817	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
818	else
819	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
820	return rc;
821	}
822	AssertMsg(RT_SUCCESS(rc), ("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
823	}
824	# endif
825	/// @todo count the above case; else
826	if (uErr & X86_TRAP_PF_US)
827	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
828	else /* supervisor */
829	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
830
831	/*
832	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
833	* page is not present, which is not true in this case.
834	*/
835	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
836	if (RT_SUCCESS(rc))
837	{
838	/*
839	* Page was successfully synced, return to guest.
840	*/
841	# ifdef VBOX_STRICT
842	RTGCPHYS GCPhys;
843	uint64_t fPageGst;
844	if (!HWACCMIsNestedPagingActive(pVM))
845	{
846	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys);
847	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
848	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
849	}
850	uint64_t fPageShw;
851	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
852	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCPUs > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
853	# endif /* VBOX_STRICT */
854	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
855	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
856	return VINF_SUCCESS;
857	}
858	}
859
860	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
861	# ifdef VBOX_STRICT
862	/*
863	* Check for VMM page flags vs. Guest page flags consistency.
864	* Currently only for debug purposes.
865	*/
866	if (RT_SUCCESS(rc))
867	{
868	/* Get guest page flags. */
869	uint64_t fPageGst;
870	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
871	if (RT_SUCCESS(rc))
872	{
873	uint64_t fPageShw;
874	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
875
876	/*
877	* Compare page flags.
878	* Note: we have AVL, A, D bits desynched.
879	*/
880	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
881	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
882	}
883	else
884	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
885	}
886	else
887	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
888	# endif /* VBOX_STRICT */
889	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
890	}
891	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
892	# endif /* PGM_OUT_OF_SYNC_IN_GC */
893	}
894	else /* GCPhys == NIL_RTGCPHYS */
895	{
896	/*
897	* Page not present in Guest OS or invalid page table address.
898	* This is potential virtual page access handler food.
899	*
900	* For the present we'll say that our access handlers don't
901	* work for this case - we've already discarded the page table
902	* not present case which is identical to this.
903	*
904	* When we perchance find we need this, we will probably have AVL
905	* trees (offset based) to operate on and we can measure their speed
906	* agains mapping a page table and probably rearrange this handling
907	* a bit. (Like, searching virtual ranges before checking the
908	* physical address.)
909	*/
910	}
911	}
912	/* else: !present (guest) */
913
914
915	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
916	/*
917	* Conclusion, this is a guest trap.
918	*/
919	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
920	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
921	return VINF_EM_RAW_GUEST_TRAP;
922	# else
923	/* present, but not a monitored page; perhaps the guest is probing physical memory */
924	return VINF_EM_RAW_EMULATE_INSTR;
925	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
926
927
928	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
929
930	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
931	return VERR_INTERNAL_ERROR;
932	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
933	}
934	#endif /* !IN_RING3 */
935
936
937	/**
938	* Emulation of the invlpg instruction.
939	*
940	*
941	* @returns VBox status code.
942	*
943	* @param pVCpu The VMCPU handle.
944	* @param GCPtrPage Page to invalidate.
945	*
946	* @remark ASSUMES that the guest is updating before invalidating. This order
947	* isn't required by the CPU, so this is speculative and could cause
948	* trouble.
949	* @remark No TLB shootdown is done on any other VCPU as we assume that
950	* invlpg emulation is the only reason for calling this function.
951	* (The guest has to shoot down TLB entries on other CPUs itself)
952	* Currently true, but keep in mind!
953	*
954	* @todo Flush page or page directory only if necessary!
955	* @todo Add a #define for simply invalidating the page.
956	*/
957	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
958	{
959	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
960	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
961	&& PGM_SHW_TYPE != PGM_TYPE_EPT
962	int rc;
963	PVM pVM = pVCpu->CTX_SUFF(pVM);
964	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
965
966	Assert(PGMIsLockOwner(pVM));
967
968	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
969
970	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
971	if (pPool->cDirtyPages)
972	pgmPoolResetDirtyPages(pVM);
973	# endif
974
975	/*
976	* Get the shadow PD entry and skip out if this PD isn't present.
977	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
978	*/
979	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
980	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
981	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
982
983	/* Fetch the pgm pool shadow descriptor. */
984	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
985	Assert(pShwPde);
986
987	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
988	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
989	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
990
991	/* If the shadow PDPE isn't present, then skip the invalidate. */
992	if (!pPdptDst->a[iPdpt].n.u1Present)
993	{
994	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
995	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
996	return VINF_SUCCESS;
997	}
998
999	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1000	PPGMPOOLPAGE pShwPde = NULL;
1001	PX86PDPAE pPDDst;
1002
1003	/* Fetch the pgm pool shadow descriptor. */
1004	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1005	AssertRCSuccessReturn(rc, rc);
1006	Assert(pShwPde);
1007
1008	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1009	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1010
1011	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1012	/* PML4 */
1013	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1014	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1015	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1016	PX86PDPAE pPDDst;
1017	PX86PDPT pPdptDst;
1018	PX86PML4E pPml4eDst;
1019	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1020	if (rc != VINF_SUCCESS)
1021	{
1022	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1023	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1024	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1025	PGM_INVL_VCPU_TLBS(pVCpu);
1026	return VINF_SUCCESS;
1027	}
1028	Assert(pPDDst);
1029
1030	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1031	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1032
1033	if (!pPdpeDst->n.u1Present)
1034	{
1035	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1036	if (!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
1037	PGM_INVL_VCPU_TLBS(pVCpu);
1038	return VINF_SUCCESS;
1039	}
1040
1041	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1042
1043	const SHWPDE PdeDst = *pPdeDst;
1044	if (!PdeDst.n.u1Present)
1045	{
1046	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1047	return VINF_SUCCESS;
1048	}
1049
1050	# if defined(IN_RC)
1051	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1052	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1053	# endif
1054
1055	/*
1056	* Get the guest PD entry and calc big page.
1057	*/
1058	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1059	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1060	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1061	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1062	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1063	unsigned iPDSrc = 0;
1064	# if PGM_GST_TYPE == PGM_TYPE_PAE
1065	X86PDPE PdpeSrc;
1066	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1067	# else /* AMD64 */
1068	PX86PML4E pPml4eSrc;
1069	X86PDPE PdpeSrc;
1070	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1071	# endif
1072	GSTPDE PdeSrc;
1073
1074	if (pPDSrc)
1075	PdeSrc = pPDSrc->a[iPDSrc];
1076	else
1077	PdeSrc.u = 0;
1078	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1079
1080	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1081	const bool fIsBigPage = PdeSrc.b.u1Size;
1082	# else
1083	const bool fIsBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1084	# endif
1085
1086	# ifdef IN_RING3
1087	/*
1088	* If a CR3 Sync is pending we may ignore the invalidate page operation
1089	* depending on the kind of sync and if it's a global page or not.
1090	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1091	*/
1092	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1093	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1094	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1095	&& fIsBigPage
1096	&& PdeSrc.b.u1Global
1097	)
1098	)
1099	# else
1100	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1101	# endif
1102	{
1103	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1104	return VINF_SUCCESS;
1105	}
1106	# endif /* IN_RING3 */
1107
1108	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1109	/* Fetch the pgm pool shadow descriptor. */
1110	PPGMPOOLPAGE pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
1111	Assert(pShwPdpt);
1112
1113	/* Fetch the pgm pool shadow descriptor. */
1114	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1115	Assert(pShwPde);
1116
1117	Assert(pPml4eDst->n.u1Present && (pPml4eDst->u & SHW_PDPT_MASK));
1118	RTGCPHYS GCPhysPdpt = pPml4eSrc->u & X86_PML4E_PG_MASK;
1119
1120	if ( !pPml4eSrc->n.u1Present
1121	\|\| pShwPdpt->GCPhys != GCPhysPdpt)
1122	{
1123	LogFlow(("InvalidatePage: Out-of-sync PML4E (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1124	GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1125	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1126	ASMAtomicWriteSize(pPml4eDst, 0);
1127	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1128	PGM_INVL_VCPU_TLBS(pVCpu);
1129	return VINF_SUCCESS;
1130	}
1131	if ( pPml4eSrc->n.u1User != pPml4eDst->n.u1User
1132	\|\| (!pPml4eSrc->n.u1Write && pPml4eDst->n.u1Write))
1133	{
1134	/*
1135	* Mark not present so we can resync the PML4E when it's used.
1136	*/
1137	LogFlow(("InvalidatePage: Out-of-sync PML4E at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1138	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1139	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1140	ASMAtomicWriteSize(pPml4eDst, 0);
1141	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1142	PGM_INVL_VCPU_TLBS(pVCpu);
1143	}
1144	else if (!pPml4eSrc->n.u1Accessed)
1145	{
1146	/*
1147	* Mark not present so we can set the accessed bit.
1148	*/
1149	LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %RGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
1150	GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
1151	pgmPoolFreeByPage(pPool, pShwPdpt, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3)->idx, iPml4);
1152	ASMAtomicWriteSize(pPml4eDst, 0);
1153	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1154	PGM_INVL_VCPU_TLBS(pVCpu);
1155	}
1156
1157	/* Check if the PDPT entry has changed. */
1158	Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
1159	RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
1160	if ( !PdpeSrc.n.u1Present
1161	\|\| pShwPde->GCPhys != GCPhysPd)
1162	{
1163	LogFlow(("InvalidatePage: Out-of-sync PDPE (P/GCPhys) at %RGv GCPhys=%RGp vs %RGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
1164	GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1165	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1166	ASMAtomicWriteSize(pPdpeDst, 0);
1167	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1168	PGM_INVL_VCPU_TLBS(pVCpu);
1169	return VINF_SUCCESS;
1170	}
1171	if ( PdpeSrc.lm.u1User != pPdpeDst->lm.u1User
1172	\|\| (!PdpeSrc.lm.u1Write && pPdpeDst->lm.u1Write))
1173	{
1174	/*
1175	* Mark not present so we can resync the PDPTE when it's used.
1176	*/
1177	LogFlow(("InvalidatePage: Out-of-sync PDPE at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1178	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1179	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1180	ASMAtomicWriteSize(pPdpeDst, 0);
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1182	PGM_INVL_VCPU_TLBS(pVCpu);
1183	}
1184	else if (!PdpeSrc.lm.u1Accessed)
1185	{
1186	/*
1187	* Mark not present so we can set the accessed bit.
1188	*/
1189	LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %RGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
1190	GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
1191	pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdpt);
1192	ASMAtomicWriteSize(pPdpeDst, 0);
1193	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1194	PGM_INVL_VCPU_TLBS(pVCpu);
1195	}
1196	# endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1197
1198	/*
1199	* Deal with the Guest PDE.
1200	*/
1201	rc = VINF_SUCCESS;
1202	if (PdeSrc.n.u1Present)
1203	{
1204	# ifndef PGM_WITHOUT_MAPPING
1205	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1206	{
1207	/*
1208	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1209	*/
1210	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1211	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1212	pgmLock(pVM);
1213	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1214	pgmUnlock(pVM);
1215	}
1216	else
1217	# endif /* !PGM_WITHOUT_MAPPING */
1218	if ( PdeSrc.n.u1User != PdeDst.n.u1User
1219	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
1220	{
1221	/*
1222	* Mark not present so we can resync the PDE when it's used.
1223	*/
1224	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1225	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1226	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1227	ASMAtomicWriteSize(pPdeDst, 0);
1228	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1229	PGM_INVL_VCPU_TLBS(pVCpu);
1230	}
1231	else if (!PdeSrc.n.u1Accessed)
1232	{
1233	/*
1234	* Mark not present so we can set the accessed bit.
1235	*/
1236	LogFlow(("InvalidatePage: Out-of-sync (A) at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1237	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1238	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1239	ASMAtomicWriteSize(pPdeDst, 0);
1240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNAs));
1241	PGM_INVL_VCPU_TLBS(pVCpu);
1242	}
1243	else if (!fIsBigPage)
1244	{
1245	/*
1246	* 4KB - page.
1247	*/
1248	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1249	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1250	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1251	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1252	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1253	# endif
1254	if (pShwPage->GCPhys == GCPhys)
1255	{
1256	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1257	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1258	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1259	if (pPT->a[iPTEDst].n.u1Present)
1260	{
1261	# ifdef PGMPOOL_WITH_USER_TRACKING
1262	/* This is very unlikely with caching/monitoring enabled. */
1263	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1264	# endif
1265	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1266	}
1267	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1268	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1269	if (RT_SUCCESS(rc))
1270	rc = VINF_SUCCESS;
1271	# endif
1272	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1273	PGM_INVL_PG(pVCpu, GCPtrPage);
1274	}
1275	else
1276	{
1277	/*
1278	* The page table address changed.
1279	*/
1280	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1281	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1282	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1283	ASMAtomicWriteSize(pPdeDst, 0);
1284	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1285	PGM_INVL_VCPU_TLBS(pVCpu);
1286	}
1287	}
1288	else
1289	{
1290	/*
1291	* 2/4MB - page.
1292	*/
1293	/* Before freeing the page, check if anything really changed. */
1294	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1295	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1296	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1297	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1298	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1299	# endif
1300	if ( pShwPage->GCPhys == GCPhys
1301	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1302	{
1303	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1304	/** @todo PAT */
1305	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1306	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1307	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1308	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1309	{
1310	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1311	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1312	# if defined(IN_RC)
1313	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1314	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1315	# endif
1316	return VINF_SUCCESS;
1317	}
1318	}
1319
1320	/*
1321	* Ok, the page table is present and it's been changed in the guest.
1322	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1323	* We could do this for some flushes in GC too, but we need an algorithm for
1324	* deciding which 4MB pages containing code likely to be executed very soon.
1325	*/
1326	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1327	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1328	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1329	ASMAtomicWriteSize(pPdeDst, 0);
1330	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1331	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1332	}
1333	}
1334	else
1335	{
1336	/*
1337	* Page directory is not present, mark shadow PDE not present.
1338	*/
1339	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1340	{
1341	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1342	ASMAtomicWriteSize(pPdeDst, 0);
1343	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1344	PGM_INVL_PG(pVCpu, GCPtrPage);
1345	}
1346	else
1347	{
1348	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1350	}
1351	}
1352	# if defined(IN_RC)
1353	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1354	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1355	# endif
1356	return rc;
1357
1358	#else /* guest real and protected mode */
1359	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1360	return VINF_SUCCESS;
1361	#endif
1362	}
1363
1364
1365	#ifdef PGMPOOL_WITH_USER_TRACKING
1366	/**
1367	* Update the tracking of shadowed pages.
1368	*
1369	* @param pVCpu The VMCPU handle.
1370	* @param pShwPage The shadow page.
1371	* @param HCPhys The physical page we is being dereferenced.
1372	*/
1373	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1374	{
1375	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1376	PVM pVM = pVCpu->CTX_SUFF(pVM);
1377
1378	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1379	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1380
1381	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1382	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1383	* 2. write protect all shadowed pages. I.e. implement caching.
1384	*/
1385	/*
1386	* Find the guest address.
1387	*/
1388	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1389	pRam;
1390	pRam = pRam->CTX_SUFF(pNext))
1391	{
1392	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1393	while (iPage-- > 0)
1394	{
1395	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1396	{
1397	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1398	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1399	pShwPage->cPresent--;
1400	pPool->cPresent--;
1401	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1402	return;
1403	}
1404	}
1405	}
1406
1407	for (;;)
1408	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1409	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1410	pShwPage->cPresent--;
1411	pVM->pgm.s.CTX_SUFF(pPool)->cPresent--;
1412	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1413	}
1414
1415
1416	/**
1417	* Update the tracking of shadowed pages.
1418	*
1419	* @param pVCpu The VMCPU handle.
1420	* @param pShwPage The shadow page.
1421	* @param u16 The top 16-bit of the pPage->HCPhys.
1422	* @param pPage Pointer to the guest page. this will be modified.
1423	* @param iPTDst The index into the shadow table.
1424	*/
1425	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1426	{
1427	PVM pVM = pVCpu->CTX_SUFF(pVM);
1428	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1429	/*
1430	* Just deal with the simple first time here.
1431	*/
1432	if (!u16)
1433	{
1434	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1435	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1436	}
1437	else
1438	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1439
1440	/* write back */
1441	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1442	PGM_PAGE_SET_TRACKING(pPage, u16);
1443
1444	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1445
1446	/* update statistics. */
1447	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1448	pShwPage->cPresent++;
1449	if (pShwPage->iFirstPresent > iPTDst)
1450	pShwPage->iFirstPresent = iPTDst;
1451	}
1452	#endif /* PGMPOOL_WITH_USER_TRACKING */
1453
1454
1455	/**
1456	* Creates a 4K shadow page for a guest page.
1457	*
1458	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1459	* physical address. The PdeSrc argument only the flags are used. No page structured
1460	* will be mapped in this function.
1461	*
1462	* @param pVCpu The VMCPU handle.
1463	* @param pPteDst Destination page table entry.
1464	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1465	* Can safely assume that only the flags are being used.
1466	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1467	* @param pShwPage Pointer to the shadow page.
1468	* @param iPTDst The index into the shadow table.
1469	*
1470	* @remark Not used for 2/4MB pages!
1471	*/
1472	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1473	{
1474	if (PteSrc.n.u1Present)
1475	{
1476	PVM pVM = pVCpu->CTX_SUFF(pVM);
1477
1478	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1479	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1480	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1481	if (pShwPage->fDirty)
1482	{
1483	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1484	PX86PTPAE pGstPT;
1485
1486	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1487	pGstPT->a[iPTDst].u = PteSrc.u;
1488	}
1489	# endif
1490	/*
1491	* Find the ram range.
1492	*/
1493	PPGMPAGE pPage;
1494	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1495	if (RT_SUCCESS(rc))
1496	{
1497	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1498	/* Try make the page writable if necessary. */
1499	if ( PteSrc.n.u1Write
1500	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1501	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1502	{
1503	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1504	AssertRC(rc);
1505	}
1506	#endif
1507
1508	/** @todo investiage PWT, PCD and PAT. */
1509	/*
1510	* Make page table entry.
1511	*/
1512	SHWPTE PteDst;
1513	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1514	{
1515	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1516	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1517	{
1518	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1519	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1520	PteDst.n.u1Present = 1;
1521	PteDst.n.u1Execute = 1;
1522	PteDst.n.u1IgnorePAT = 1;
1523	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1524	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1525	#else
1526	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1527	\| PGM_PAGE_GET_HCPHYS(pPage);
1528	#endif
1529	}
1530	else
1531	{
1532	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1533	PteDst.u = 0;
1534	}
1535	/** @todo count these two kinds. */
1536	}
1537	else
1538	{
1539	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1540	/*
1541	* If the page or page directory entry is not marked accessed,
1542	* we mark the page not present.
1543	*/
1544	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1545	{
1546	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1547	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1548	PteDst.u = 0;
1549	}
1550	else
1551	/*
1552	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1553	* when the page is modified.
1554	*/
1555	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1556	{
1557	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1558	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1559	\| PGM_PAGE_GET_HCPHYS(pPage)
1560	\| PGM_PTFLAGS_TRACK_DIRTY;
1561	}
1562	else
1563	#endif
1564	{
1565	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1566	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1567	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1568	PteDst.n.u1Present = 1;
1569	PteDst.n.u1Write = 1;
1570	PteDst.n.u1Execute = 1;
1571	PteDst.n.u1IgnorePAT = 1;
1572	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1573	/* PteDst.n.u1Size = 0 */
1574	#else
1575	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1576	\| PGM_PAGE_GET_HCPHYS(pPage);
1577	#endif
1578	}
1579	}
1580
1581	/*
1582	* Make sure only allocated pages are mapped writable.
1583	*/
1584	if ( PteDst.n.u1Write
1585	&& PteDst.n.u1Present
1586	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1587	{
1588	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1589	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1590	}
1591
1592	#ifdef PGMPOOL_WITH_USER_TRACKING
1593	/*
1594	* Keep user track up to date.
1595	*/
1596	if (PteDst.n.u1Present)
1597	{
1598	if (!pPteDst->n.u1Present)
1599	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1600	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1601	{
1602	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1603	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1604	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1605	}
1606	}
1607	else if (pPteDst->n.u1Present)
1608	{
1609	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1610	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1611	}
1612	#endif /* PGMPOOL_WITH_USER_TRACKING */
1613
1614	/*
1615	* Update statistics and commit the entry.
1616	*/
1617	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1618	if (!PteSrc.n.u1Global)
1619	pShwPage->fSeenNonGlobal = true;
1620	#endif
1621	ASMAtomicWriteSize(pPteDst, PteDst.u);
1622	}
1623	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1624	/** @todo count these. */
1625	}
1626	else
1627	{
1628	/*
1629	* Page not-present.
1630	*/
1631	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1632	#ifdef PGMPOOL_WITH_USER_TRACKING
1633	/* Keep user track up to date. */
1634	if (pPteDst->n.u1Present)
1635	{
1636	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1637	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1638	}
1639	#endif /* PGMPOOL_WITH_USER_TRACKING */
1640	ASMAtomicWriteSize(pPteDst, 0);
1641	/** @todo count these. */
1642	}
1643	}
1644
1645
1646	/**
1647	* Syncs a guest OS page.
1648	*
1649	* There are no conflicts at this point, neither is there any need for
1650	* page table allocations.
1651	*
1652	* @returns VBox status code.
1653	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1654	* @param pVCpu The VMCPU handle.
1655	* @param PdeSrc Page directory entry of the guest.
1656	* @param GCPtrPage Guest context page address.
1657	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1658	* @param uErr Fault error (X86_TRAP_PF_*).
1659	*/
1660	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1661	{
1662	PVM pVM = pVCpu->CTX_SUFF(pVM);
1663	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1664	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1665
1666	Assert(PGMIsLockOwner(pVM));
1667
1668	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1669	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1670	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1671	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1672	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1673
1674	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1675	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
1676	# endif
1677
1678	/*
1679	* Assert preconditions.
1680	*/
1681	Assert(PdeSrc.n.u1Present);
1682	Assert(cPages);
1683	# if 0 /* rarely useful; leave for debugging. */
1684	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1685	# endif
1686
1687	/*
1688	* Get the shadow PDE, find the shadow page table in the pool.
1689	*/
1690	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1691	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1692	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1693
1694	/* Fetch the pgm pool shadow descriptor. */
1695	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1696	Assert(pShwPde);
1697
1698	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1699	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1700	PPGMPOOLPAGE pShwPde = NULL;
1701	PX86PDPAE pPDDst;
1702
1703	/* Fetch the pgm pool shadow descriptor. */
1704	int rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1705	AssertRCSuccessReturn(rc, rc);
1706	Assert(pShwPde);
1707
1708	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1709	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1710
1711	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1712	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1713	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1714	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1715	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1716
1717	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1718	AssertRCSuccessReturn(rc, rc);
1719	Assert(pPDDst && pPdptDst);
1720	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1721	# endif
1722	SHWPDE PdeDst = *pPdeDst;
1723	if (!PdeDst.n.u1Present)
1724	{
1725	AssertMsg(pVM->cCPUs > 1, ("%Unexpected missing PDE p=%llx\n", pPdeDst, (uint64_t)PdeDst.u));
1726	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1727	return VINF_SUCCESS; /* force the instruction to be executed again. */
1728	}
1729
1730	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1731	Assert(pShwPage);
1732
1733	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1734	/* Fetch the pgm pool shadow descriptor. */
1735	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1736	Assert(pShwPde);
1737	# endif
1738
1739	# if defined(IN_RC)
1740	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1741	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1742	# endif
1743
1744	/*
1745	* Check that the page is present and that the shadow PDE isn't out of sync.
1746	*/
1747	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1748	const bool fBigPage = PdeSrc.b.u1Size;
1749	# else
1750	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
1751	# endif
1752	RTGCPHYS GCPhys;
1753	if (!fBigPage)
1754	{
1755	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1756	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1757	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1758	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1759	# endif
1760	}
1761	else
1762	{
1763	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1764	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1765	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1766	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1767	# endif
1768	}
1769	if ( pShwPage->GCPhys == GCPhys
1770	&& PdeSrc.n.u1Present
1771	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1772	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1773	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1774	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1775	# endif
1776	)
1777	{
1778	/*
1779	* Check that the PDE is marked accessed already.
1780	* Since we set the accessed bit before getting here on a #PF, this
1781	* check is only meant for dealing with non-#PF'ing paths.
1782	*/
1783	if (PdeSrc.n.u1Accessed)
1784	{
1785	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1786	if (!fBigPage)
1787	{
1788	/*
1789	* 4KB Page - Map the guest page table.
1790	*/
1791	PGSTPT pPTSrc;
1792	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1793	if (RT_SUCCESS(rc))
1794	{
1795	# ifdef PGM_SYNC_N_PAGES
1796	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1797	if ( cPages > 1
1798	&& !(uErr & X86_TRAP_PF_P)
1799	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1800	{
1801	/*
1802	* This code path is currently only taken when the caller is PGMTrap0eHandler
1803	* for non-present pages!
1804	*
1805	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1806	* deal with locality.
1807	*/
1808	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1809	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1810	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1811	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1812	# else
1813	const unsigned offPTSrc = 0;
1814	# endif
1815	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1816	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1817	iPTDst = 0;
1818	else
1819	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1820	for (; iPTDst < iPTDstEnd; iPTDst++)
1821	{
1822	if (!pPTDst->a[iPTDst].n.u1Present)
1823	{
1824	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1825	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1826	NOREF(GCPtrCurPage);
1827	#ifndef IN_RING0
1828	/*
1829	* Assuming kernel code will be marked as supervisor - and not as user level
1830	* and executed using a conforming code selector - And marked as readonly.
1831	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1832	*/
1833	PPGMPAGE pPage;
1834	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1835	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1836	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)GCPtrCurPage)
1837	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1838	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1839	)
1840	#endif /* else: CSAM not active */
1841	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1842	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1843	GCPtrCurPage, PteSrc.n.u1Present,
1844	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1845	PteSrc.n.u1User & PdeSrc.n.u1User,
1846	(uint64_t)PteSrc.u,
1847	(uint64_t)pPTDst->a[iPTDst].u,
1848	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1849	}
1850	}
1851	}
1852	else
1853	# endif /* PGM_SYNC_N_PAGES */
1854	{
1855	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1856	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1857	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1858	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1859	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1860	GCPtrPage, PteSrc.n.u1Present,
1861	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1862	PteSrc.n.u1User & PdeSrc.n.u1User,
1863	(uint64_t)PteSrc.u,
1864	(uint64_t)pPTDst->a[iPTDst].u,
1865	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1866	}
1867	}
1868	else /* MMIO or invalid page: emulated in #PF handler. */
1869	{
1870	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1871	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1872	}
1873	}
1874	else
1875	{
1876	/*
1877	* 4/2MB page - lazy syncing shadow 4K pages.
1878	* (There are many causes of getting here, it's no longer only CSAM.)
1879	*/
1880	/* Calculate the GC physical address of this 4KB shadow page. */
1881	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1882	/* Find ram range. */
1883	PPGMPAGE pPage;
1884	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1885	if (RT_SUCCESS(rc))
1886	{
1887	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1888	/* Try make the page writable if necessary. */
1889	if ( PdeSrc.n.u1Write
1890	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1891	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1892	{
1893	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1894	AssertRC(rc);
1895	}
1896	# endif
1897
1898	/*
1899	* Make shadow PTE entry.
1900	*/
1901	SHWPTE PteDst;
1902	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1903	\| PGM_PAGE_GET_HCPHYS(pPage);
1904	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1905	{
1906	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1907	PteDst.n.u1Write = 0;
1908	else
1909	PteDst.u = 0;
1910	}
1911	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1912	# ifdef PGMPOOL_WITH_USER_TRACKING
1913	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1914	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1915	# endif
1916	/* Make sure only allocated pages are mapped writable. */
1917	if ( PteDst.n.u1Write
1918	&& PteDst.n.u1Present
1919	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1920	{
1921	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1922	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1923	}
1924
1925	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1926
1927	/*
1928	* If the page is not flagged as dirty and is writable, then make it read-only
1929	* at PD level, so we can set the dirty bit when the page is modified.
1930	*
1931	* ASSUMES that page access handlers are implemented on page table entry level.
1932	* Thus we will first catch the dirty access and set PDE.D and restart. If
1933	* there is an access handler, we'll trap again and let it work on the problem.
1934	*/
1935	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1936	* As for invlpg, it simply frees the whole shadow PT.
1937	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1938	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1939	{
1940	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1941	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1942	PdeDst.n.u1Write = 0;
1943	}
1944	else
1945	{
1946	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1947	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1948	}
1949	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1950	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1951	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1952	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1953	}
1954	else
1955	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1956	}
1957	# if defined(IN_RC)
1958	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1959	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1960	# endif
1961	return VINF_SUCCESS;
1962	}
1963	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1964	}
1965	else
1966	{
1967	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1968	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1969	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1970	}
1971
1972	/*
1973	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1974	* Yea, I'm lazy.
1975	*/
1976	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1977	ASMAtomicWriteSize(pPdeDst, 0);
1978
1979	# if defined(IN_RC)
1980	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1981	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1982	# endif
1983	PGM_INVL_VCPU_TLBS(pVCpu);
1984	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1985
1986	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1987	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1988	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1989	&& !defined(IN_RC)
1990
1991	# ifdef PGM_SYNC_N_PAGES
1992	/*
1993	* Get the shadow PDE, find the shadow page table in the pool.
1994	*/
1995	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1996	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1997
1998	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1999	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
2000
2001	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2002	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2003	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2004	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2005	X86PDEPAE PdeDst;
2006	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2007
2008	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2009	AssertRCSuccessReturn(rc, rc);
2010	Assert(pPDDst && pPdptDst);
2011	PdeDst = pPDDst->a[iPDDst];
2012	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2013	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2014	PEPTPD pPDDst;
2015	EPTPDE PdeDst;
2016
2017	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2018	if (rc != VINF_SUCCESS)
2019	{
2020	AssertRC(rc);
2021	return rc;
2022	}
2023	Assert(pPDDst);
2024	PdeDst = pPDDst->a[iPDDst];
2025	# endif
2026	AssertMsg(PdeDst.n.u1Present, ("%#llx\n", (uint64_t)PdeDst.u));
2027	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2028	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2029
2030	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2031	if ( cPages > 1
2032	&& !(uErr & X86_TRAP_PF_P)
2033	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2034	{
2035	/*
2036	* This code path is currently only taken when the caller is PGMTrap0eHandler
2037	* for non-present pages!
2038	*
2039	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2040	* deal with locality.
2041	*/
2042	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2043	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2044	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2045	iPTDst = 0;
2046	else
2047	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2048	for (; iPTDst < iPTDstEnd; iPTDst++)
2049	{
2050	if (!pPTDst->a[iPTDst].n.u1Present)
2051	{
2052	GSTPTE PteSrc;
2053
2054	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2055
2056	/* Fake the page table entry */
2057	PteSrc.u = GCPtrCurPage;
2058	PteSrc.n.u1Present = 1;
2059	PteSrc.n.u1Dirty = 1;
2060	PteSrc.n.u1Accessed = 1;
2061	PteSrc.n.u1Write = 1;
2062	PteSrc.n.u1User = 1;
2063
2064	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2065
2066	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2067	GCPtrCurPage, PteSrc.n.u1Present,
2068	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2069	PteSrc.n.u1User & PdeSrc.n.u1User,
2070	(uint64_t)PteSrc.u,
2071	(uint64_t)pPTDst->a[iPTDst].u,
2072	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2073
2074	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2075	break;
2076	}
2077	else
2078	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2079	}
2080	}
2081	else
2082	# endif /* PGM_SYNC_N_PAGES */
2083	{
2084	GSTPTE PteSrc;
2085	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2086	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2087
2088	/* Fake the page table entry */
2089	PteSrc.u = GCPtrCurPage;
2090	PteSrc.n.u1Present = 1;
2091	PteSrc.n.u1Dirty = 1;
2092	PteSrc.n.u1Accessed = 1;
2093	PteSrc.n.u1Write = 1;
2094	PteSrc.n.u1User = 1;
2095	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2096
2097	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2098	GCPtrPage, PteSrc.n.u1Present,
2099	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2100	PteSrc.n.u1User & PdeSrc.n.u1User,
2101	(uint64_t)PteSrc.u,
2102	(uint64_t)pPTDst->a[iPTDst].u,
2103	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2104	}
2105	return VINF_SUCCESS;
2106
2107	#else
2108	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2109	return VERR_INTERNAL_ERROR;
2110	#endif
2111	}
2112
2113
2114	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2115	/**
2116	* Investigate page fault and handle write protection page faults caused by
2117	* dirty bit tracking.
2118	*
2119	* @returns VBox status code.
2120	* @param pVCpu The VMCPU handle.
2121	* @param uErr Page fault error code.
2122	* @param pPdeDst Shadow page directory entry.
2123	* @param pPdeSrc Guest page directory entry.
2124	* @param GCPtrPage Guest context page address.
2125	*/
2126	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2127	{
2128	bool fWriteProtect = !!(CPUMGetGuestCR0(pVCpu) & X86_CR0_WP);
2129	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2130	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2131	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2132	bool fBigPagesSupported = true;
2133	# else
2134	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2135	# endif
2136	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2137	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2138	# endif
2139	unsigned uPageFaultLevel;
2140	int rc;
2141	PVM pVM = pVCpu->CTX_SUFF(pVM);
2142	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2143
2144	Assert(PGMIsLockOwner(pVM));
2145
2146	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2147	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2148
2149	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2150	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2151
2152	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2153	PX86PML4E pPml4eSrc;
2154	PX86PDPE pPdpeSrc;
2155
2156	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2157	Assert(pPml4eSrc);
2158
2159	/*
2160	* Real page fault? (PML4E level)
2161	*/
2162	if ( (uErr & X86_TRAP_PF_RSVD)
2163	\|\| !pPml4eSrc->n.u1Present
2164	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
2165	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2166	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2167	)
2168	{
2169	uPageFaultLevel = 0;
2170	goto l_UpperLevelPageFault;
2171	}
2172	Assert(pPdpeSrc);
2173
2174	# else /* PAE */
2175	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2176	# endif /* PAE */
2177
2178	/*
2179	* Real page fault? (PDPE level)
2180	*/
2181	if ( (uErr & X86_TRAP_PF_RSVD)
2182	\|\| !pPdpeSrc->n.u1Present
2183	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2184	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->lm.u1NoExecute)
2185	\|\| (fWriteFault && !pPdpeSrc->lm.u1Write && (fUserLevelFault \|\| fWriteProtect))
2186	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2187	# endif
2188	)
2189	{
2190	uPageFaultLevel = 1;
2191	goto l_UpperLevelPageFault;
2192	}
2193	# endif
2194
2195	/*
2196	* Real page fault? (PDE level)
2197	*/
2198	if ( (uErr & X86_TRAP_PF_RSVD)
2199	\|\| !pPdeSrc->n.u1Present
2200	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2201	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
2202	# endif
2203	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2204	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2205	{
2206	uPageFaultLevel = 2;
2207	goto l_UpperLevelPageFault;
2208	}
2209
2210	/*
2211	* First check the easy case where the page directory has been marked read-only to track
2212	* the dirty bit of an emulated BIG page
2213	*/
2214	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2215	{
2216	/* Mark guest page directory as accessed */
2217	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2218	pPml4eSrc->n.u1Accessed = 1;
2219	pPdpeSrc->lm.u1Accessed = 1;
2220	# endif
2221	pPdeSrc->b.u1Accessed = 1;
2222
2223	/*
2224	* Only write protection page faults are relevant here.
2225	*/
2226	if (fWriteFault)
2227	{
2228	/* Mark guest page directory as dirty (BIG page only). */
2229	pPdeSrc->b.u1Dirty = 1;
2230
2231	if (pPdeDst->n.u1Present)
2232	{
2233	if (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY)
2234	{
2235	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2236	Assert(pPdeSrc->b.u1Write);
2237
2238	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2239	* fault again and take this path to only invalidate the entry.
2240	*/
2241	pPdeDst->n.u1Write = 1;
2242	pPdeDst->n.u1Accessed = 1;
2243	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2244	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2245	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2246	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2247	}
2248	# ifdef IN_RING0
2249	else
2250	/* Check for stale TLB entry; only applies to the SMP guest case. */
2251	if ( pVM->cCPUs > 1
2252	&& pPdeDst->n.u1Write
2253	&& pPdeDst->n.u1Accessed)
2254	{
2255	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2256	if (pShwPage)
2257	{
2258	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2259	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2260	if ( pPteDst->n.u1Present
2261	&& pPteDst->n.u1Write)
2262	{
2263	/* Stale TLB entry. */
2264	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2265	PGM_INVL_PG(pVCpu, GCPtrPage);
2266
2267	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2268	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2269	}
2270	}
2271	}
2272	# endif /* IN_RING0 */
2273	}
2274	}
2275	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2276	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2277	}
2278	/* else: 4KB page table */
2279
2280	/*
2281	* Map the guest page table.
2282	*/
2283	PGSTPT pPTSrc;
2284	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2285	if (RT_SUCCESS(rc))
2286	{
2287	/*
2288	* Real page fault?
2289	*/
2290	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2291	const GSTPTE PteSrc = *pPteSrc;
2292	if ( !PteSrc.n.u1Present
2293	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2294	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
2295	# endif
2296	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
2297	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2298	)
2299	{
2300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2301	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2302	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2303
2304	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2305	* See the 2nd case above as well.
2306	*/
2307	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2308	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2309
2310	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2311	return VINF_EM_RAW_GUEST_TRAP;
2312	}
2313	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2314
2315	/*
2316	* Set the accessed bits in the page directory and the page table.
2317	*/
2318	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2319	pPml4eSrc->n.u1Accessed = 1;
2320	pPdpeSrc->lm.u1Accessed = 1;
2321	# endif
2322	pPdeSrc->n.u1Accessed = 1;
2323	pPteSrc->n.u1Accessed = 1;
2324
2325	/*
2326	* Only write protection page faults are relevant here.
2327	*/
2328	if (fWriteFault)
2329	{
2330	/* Write access, so mark guest entry as dirty. */
2331	# ifdef VBOX_WITH_STATISTICS
2332	if (!pPteSrc->n.u1Dirty)
2333	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2334	else
2335	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2336	# endif
2337
2338	pPteSrc->n.u1Dirty = 1;
2339
2340	if (pPdeDst->n.u1Present)
2341	{
2342	#ifndef IN_RING0
2343	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2344	* Our individual shadow handlers will provide more information and force a fatal exit.
2345	*/
2346	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2347	{
2348	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2349	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2350	return VINF_SUCCESS;
2351	}
2352	#endif
2353	/*
2354	* Map shadow page table.
2355	*/
2356	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2357	if (pShwPage)
2358	{
2359	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2360	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2361	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2362	{
2363	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2364	{
2365	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2366	# ifdef VBOX_STRICT
2367	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2368	if (pPage)
2369	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
2370	("Unexpected dirty bit tracking on monitored page %RGv (phys %RGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
2371	# endif
2372	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2373
2374	Assert(pPteSrc->n.u1Write);
2375
2376	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2377	* fault again and take this path to only invalidate the entry.
2378	*/
2379	pPteDst->n.u1Write = 1;
2380	pPteDst->n.u1Dirty = 1;
2381	pPteDst->n.u1Accessed = 1;
2382	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2383	PGM_INVL_PG(pVCpu, GCPtrPage);
2384
2385	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2386	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2387	}
2388	# ifdef IN_RING0
2389	else
2390	/* Check for stale TLB entry; only applies to the SMP guest case. */
2391	if ( pVM->cCPUs > 1
2392	&& pPteDst->n.u1Write == 1
2393	&& pPteDst->n.u1Accessed == 1)
2394	{
2395	/* Stale TLB entry. */
2396	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2397	PGM_INVL_PG(pVCpu, GCPtrPage);
2398
2399	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2400	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
2401	}
2402	# endif
2403	}
2404	}
2405	else
2406	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2407	}
2408	}
2409	/** @todo Optimize accessed bit emulation? */
2410	# ifdef VBOX_STRICT
2411	/*
2412	* Sanity check.
2413	*/
2414	else if ( !pPteSrc->n.u1Dirty
2415	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
2416	&& pPdeDst->n.u1Present)
2417	{
2418	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2419	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2420	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2421	if ( pPteDst->n.u1Present
2422	&& pPteDst->n.u1Write)
2423	LogFlow(("Writable present page %RGv not marked for dirty bit tracking!!!\n", GCPtrPage));
2424	}
2425	# endif /* VBOX_STRICT */
2426	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2427	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2428	}
2429	AssertRC(rc);
2430	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2431	return rc;
2432
2433
2434	l_UpperLevelPageFault:
2435	/*
2436	* Pagefault detected while checking the PML4E, PDPE or PDE.
2437	* Single exit handler to get rid of duplicate code paths.
2438	*/
2439	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2440	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
2441	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2442
2443	if (
2444	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2445	pPml4eSrc->n.u1Present &&
2446	# endif
2447	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2448	pPdpeSrc->n.u1Present &&
2449	# endif
2450	pPdeSrc->n.u1Present)
2451	{
2452	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2453	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2454	{
2455	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2456	}
2457	else
2458	{
2459	/*
2460	* Map the guest page table.
2461	*/
2462	PGSTPT pPTSrc;
2463	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2464	if (RT_SUCCESS(rc))
2465	{
2466	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2467	const GSTPTE PteSrc = *pPteSrc;
2468	if (pPteSrc->n.u1Present)
2469	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2470	}
2471	AssertRC(rc);
2472	}
2473	}
2474	return VINF_EM_RAW_GUEST_TRAP;
2475	}
2476	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2477
2478
2479	/**
2480	* Sync a shadow page table.
2481	*
2482	* The shadow page table is not present. This includes the case where
2483	* there is a conflict with a mapping.
2484	*
2485	* @returns VBox status code.
2486	* @param pVCpu The VMCPU handle.
2487	* @param iPD Page directory index.
2488	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2489	* Assume this is a temporary mapping.
2490	* @param GCPtrPage GC Pointer of the page that caused the fault
2491	*/
2492	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2493	{
2494	PVM pVM = pVCpu->CTX_SUFF(pVM);
2495	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2496
2497	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2498	#if 0 /* rarely useful; leave for debugging. */
2499	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2500	#endif
2501	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2502
2503	Assert(PGMIsLocked(pVM));
2504
2505	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2506	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2507	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2508	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2509	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2510
2511	int rc = VINF_SUCCESS;
2512
2513	/*
2514	* Validate input a little bit.
2515	*/
2516	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2517	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2518	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2519	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2520
2521	/* Fetch the pgm pool shadow descriptor. */
2522	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2523	Assert(pShwPde);
2524
2525	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2526	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2527	PPGMPOOLPAGE pShwPde = NULL;
2528	PX86PDPAE pPDDst;
2529	PSHWPDE pPdeDst;
2530
2531	/* Fetch the pgm pool shadow descriptor. */
2532	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2533	AssertRCSuccessReturn(rc, rc);
2534	Assert(pShwPde);
2535
2536	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2537	pPdeDst = &pPDDst->a[iPDDst];
2538
2539	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2540	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2541	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2542	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2543	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2544	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2545	AssertRCSuccessReturn(rc, rc);
2546	Assert(pPDDst);
2547	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2548	# endif
2549	SHWPDE PdeDst = *pPdeDst;
2550
2551	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2552	/* Fetch the pgm pool shadow descriptor. */
2553	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2554	Assert(pShwPde);
2555	# endif
2556
2557	# ifndef PGM_WITHOUT_MAPPINGS
2558	/*
2559	* Check for conflicts.
2560	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2561	* HC: Simply resolve the conflict.
2562	*/
2563	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2564	{
2565	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2566	# ifndef IN_RING3
2567	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2568	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2569	return VERR_ADDRESS_CONFLICT;
2570	# else
2571	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2572	Assert(pMapping);
2573	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2574	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2575	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2576	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2577	# else
2578	AssertFailed(); /* can't happen for amd64 */
2579	# endif
2580	if (RT_FAILURE(rc))
2581	{
2582	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2583	return rc;
2584	}
2585	PdeDst = *pPdeDst;
2586	# endif
2587	}
2588	# else /* PGM_WITHOUT_MAPPINGS */
2589	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2590	# endif /* PGM_WITHOUT_MAPPINGS */
2591	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2592
2593	# if defined(IN_RC)
2594	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2595	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2596	# endif
2597
2598	/*
2599	* Sync page directory entry.
2600	*/
2601	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2602	if (PdeSrc.n.u1Present)
2603	{
2604	/*
2605	* Allocate & map the page table.
2606	*/
2607	PSHWPT pPTDst;
2608	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2609	const bool fPageTable = !PdeSrc.b.u1Size;
2610	# else
2611	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2612	# endif
2613	PPGMPOOLPAGE pShwPage;
2614	RTGCPHYS GCPhys;
2615	if (fPageTable)
2616	{
2617	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2618	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2619	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2620	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2621	# endif
2622	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2623	}
2624	else
2625	{
2626	PGMPOOLACCESS enmAccess;
2627
2628	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2629	const bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVCpu) & MSR_K6_EFER_NXE);
2630	const bool fNoExecute = fNoExecuteBitValid && PdeSrc.n.u1NoExecute;
2631	# else
2632	const bool fNoExecute = false;
2633	# endif
2634
2635	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2636	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2637	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2638	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2639	# endif
2640	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2641	if (PdeSrc.n.u1User)
2642	{
2643	if (PdeSrc.n.u1Write)
2644	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2645	else
2646	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2647	}
2648	else
2649	{
2650	if (PdeSrc.n.u1Write)
2651	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2652	else
2653	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2654	}
2655	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2656	}
2657	if (rc == VINF_SUCCESS)
2658	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2659	else if (rc == VINF_PGM_CACHED_PAGE)
2660	{
2661	/*
2662	* The PT was cached, just hook it up.
2663	*/
2664	if (fPageTable)
2665	PdeDst.u = pShwPage->Core.Key
2666	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2667	else
2668	{
2669	PdeDst.u = pShwPage->Core.Key
2670	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2671	/* (see explanation and assumptions further down.) */
2672	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2673	{
2674	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2675	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2676	PdeDst.b.u1Write = 0;
2677	}
2678	}
2679	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2680	# if defined(IN_RC)
2681	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2682	# endif
2683	return VINF_SUCCESS;
2684	}
2685	else if (rc == VERR_PGM_POOL_FLUSHED)
2686	{
2687	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2688	# if defined(IN_RC)
2689	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2690	# endif
2691	return VINF_PGM_SYNC_CR3;
2692	}
2693	else
2694	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2695	PdeDst.u &= X86_PDE_AVL_MASK;
2696	PdeDst.u \|= pShwPage->Core.Key;
2697
2698	/*
2699	* Page directory has been accessed (this is a fault situation, remember).
2700	*/
2701	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2702	if (fPageTable)
2703	{
2704	/*
2705	* Page table - 4KB.
2706	*
2707	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2708	*/
2709	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2710	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2711	PGSTPT pPTSrc;
2712	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2713	if (RT_SUCCESS(rc))
2714	{
2715	/*
2716	* Start by syncing the page directory entry so CSAM's TLB trick works.
2717	*/
2718	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2719	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2720	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2721	# if defined(IN_RC)
2722	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2723	# endif
2724
2725	/*
2726	* Directory/page user or supervisor privilege: (same goes for read/write)
2727	*
2728	* Directory Page Combined
2729	* U/S U/S U/S
2730	* 0 0 0
2731	* 0 1 0
2732	* 1 0 0
2733	* 1 1 1
2734	*
2735	* Simple AND operation. Table listed for completeness.
2736	*
2737	*/
2738	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2739	# ifdef PGM_SYNC_N_PAGES
2740	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2741	unsigned iPTDst = iPTBase;
2742	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2743	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2744	iPTDst = 0;
2745	else
2746	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2747	# else /* !PGM_SYNC_N_PAGES */
2748	unsigned iPTDst = 0;
2749	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2750	# endif /* !PGM_SYNC_N_PAGES */
2751	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2752	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2753	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2754	# else
2755	const unsigned offPTSrc = 0;
2756	# endif
2757	for (; iPTDst < iPTDstEnd; iPTDst++)
2758	{
2759	const unsigned iPTSrc = iPTDst + offPTSrc;
2760	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2761
2762	if (PteSrc.n.u1Present) /* we've already cleared it above */
2763	{
2764	# ifndef IN_RING0
2765	/*
2766	* Assuming kernel code will be marked as supervisor - and not as user level
2767	* and executed using a conforming code selector - And marked as readonly.
2768	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2769	*/
2770	PPGMPAGE pPage;
2771	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2772	\|\| !CSAMDoesPageNeedScanning(pVM, (RTRCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2773	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2774	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2775	)
2776	# endif
2777	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2778	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2779	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2780	PteSrc.n.u1Present,
2781	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2782	PteSrc.n.u1User & PdeSrc.n.u1User,
2783	(uint64_t)PteSrc.u,
2784	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2785	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2786	}
2787	} /* for PTEs */
2788	}
2789	}
2790	else
2791	{
2792	/*
2793	* Big page - 2/4MB.
2794	*
2795	* We'll walk the ram range list in parallel and optimize lookups.
2796	* We will only sync on shadow page table at a time.
2797	*/
2798	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2799
2800	/**
2801	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2802	*/
2803
2804	/*
2805	* Start by syncing the page directory entry.
2806	*/
2807	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2808	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2809
2810	/*
2811	* If the page is not flagged as dirty and is writable, then make it read-only
2812	* at PD level, so we can set the dirty bit when the page is modified.
2813	*
2814	* ASSUMES that page access handlers are implemented on page table entry level.
2815	* Thus we will first catch the dirty access and set PDE.D and restart. If
2816	* there is an access handler, we'll trap again and let it work on the problem.
2817	*/
2818	/** @todo move the above stuff to a section in the PGM documentation. */
2819	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2820	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2821	{
2822	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2823	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2824	PdeDst.b.u1Write = 0;
2825	}
2826	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2827	# if defined(IN_RC)
2828	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2829	# endif
2830
2831	/*
2832	* Fill the shadow page table.
2833	*/
2834	/* Get address and flags from the source PDE. */
2835	SHWPTE PteDstBase;
2836	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2837
2838	/* Loop thru the entries in the shadow PT. */
2839	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2840	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2841	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2842	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2843	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2844	unsigned iPTDst = 0;
2845	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2846	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2847	{
2848	/* Advance ram range list. */
2849	while (pRam && GCPhys > pRam->GCPhysLast)
2850	pRam = pRam->CTX_SUFF(pNext);
2851	if (pRam && GCPhys >= pRam->GCPhys)
2852	{
2853	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2854	do
2855	{
2856	/* Make shadow PTE. */
2857	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2858	SHWPTE PteDst;
2859
2860	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2861	/* Try make the page writable if necessary. */
2862	if ( PteDstBase.n.u1Write
2863	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2864	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2865	{
2866	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2867	AssertRCReturn(rc, rc);
2868	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2869	break;
2870	}
2871	# endif
2872
2873	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2874	{
2875	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2876	{
2877	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2878	PteDst.n.u1Write = 0;
2879	}
2880	else
2881	PteDst.u = 0;
2882	}
2883	# ifndef IN_RING0
2884	/*
2885	* Assuming kernel code will be marked as supervisor and not as user level and executed
2886	* using a conforming code selector. Don't check for readonly, as that implies the whole
2887	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2888	*/
2889	else if ( !PdeSrc.n.u1User
2890	&& CSAMDoesPageNeedScanning(pVM, (RTRCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2891	PteDst.u = 0;
2892	# endif
2893	else
2894	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2895
2896	/* Only map writable pages writable. */
2897	if ( PteDst.n.u1Write
2898	&& PteDst.n.u1Present
2899	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2900	{
2901	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2902	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2903	}
2904
2905	# ifdef PGMPOOL_WITH_USER_TRACKING
2906	if (PteDst.n.u1Present)
2907	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2908	# endif
2909	/* commit it */
2910	pPTDst->a[iPTDst] = PteDst;
2911	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2912	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2913	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2914
2915	/* advance */
2916	GCPhys += PAGE_SIZE;
2917	iHCPage++;
2918	iPTDst++;
2919	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2920	&& GCPhys <= pRam->GCPhysLast);
2921	}
2922	else if (pRam)
2923	{
2924	Log(("Invalid pages at %RGp\n", GCPhys));
2925	do
2926	{
2927	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2928	GCPhys += PAGE_SIZE;
2929	iPTDst++;
2930	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2931	&& GCPhys < pRam->GCPhys);
2932	}
2933	else
2934	{
2935	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2936	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2937	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2938	}
2939	} /* while more PTEs */
2940	} /* 4KB / 4MB */
2941	}
2942	else
2943	AssertRelease(!PdeDst.n.u1Present);
2944
2945	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2946	if (RT_FAILURE(rc))
2947	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2948	return rc;
2949
2950	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2951	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2952	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2953	&& !defined(IN_RC)
2954
2955	/*
2956	* Validate input a little bit.
2957	*/
2958	int rc = VINF_SUCCESS;
2959	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2960	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2961	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2962
2963	/* Fetch the pgm pool shadow descriptor. */
2964	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2965	Assert(pShwPde);
2966
2967	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2968	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2969	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2970	PX86PDPAE pPDDst;
2971	PSHWPDE pPdeDst;
2972
2973	/* Fetch the pgm pool shadow descriptor. */
2974	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2975	AssertRCSuccessReturn(rc, rc);
2976	Assert(pShwPde);
2977
2978	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2979	pPdeDst = &pPDDst->a[iPDDst];
2980
2981	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2982	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2983	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2984	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2985	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2986	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2987	AssertRCSuccessReturn(rc, rc);
2988	Assert(pPDDst);
2989	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2990
2991	/* Fetch the pgm pool shadow descriptor. */
2992	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2993	Assert(pShwPde);
2994
2995	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2996	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2997	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2998	PEPTPD pPDDst;
2999	PEPTPDPT pPdptDst;
3000
3001	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3002	if (rc != VINF_SUCCESS)
3003	{
3004	AssertRC(rc);
3005	return rc;
3006	}
3007	Assert(pPDDst);
3008	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3009
3010	/* Fetch the pgm pool shadow descriptor. */
3011	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3012	Assert(pShwPde);
3013	# endif
3014	SHWPDE PdeDst = *pPdeDst;
3015
3016	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3017	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3018
3019	GSTPDE PdeSrc;
3020	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3021	PdeSrc.n.u1Present = 1;
3022	PdeSrc.n.u1Write = 1;
3023	PdeSrc.n.u1Accessed = 1;
3024	PdeSrc.n.u1User = 1;
3025
3026	/*
3027	* Allocate & map the page table.
3028	*/
3029	PSHWPT pPTDst;
3030	PPGMPOOLPAGE pShwPage;
3031	RTGCPHYS GCPhys;
3032
3033	/* Virtual address = physical address */
3034	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3035	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3036
3037	if ( rc == VINF_SUCCESS
3038	\|\| rc == VINF_PGM_CACHED_PAGE)
3039	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3040	else
3041	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3042
3043	PdeDst.u &= X86_PDE_AVL_MASK;
3044	PdeDst.u \|= pShwPage->Core.Key;
3045	PdeDst.n.u1Present = 1;
3046	PdeDst.n.u1Write = 1;
3047	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3048	PdeDst.n.u1Execute = 1;
3049	# else
3050	PdeDst.n.u1User = 1;
3051	PdeDst.n.u1Accessed = 1;
3052	# endif
3053	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3054
3055	pgmLock(pVM);
3056	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3057	pgmUnlock(pVM);
3058	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3059	return rc;
3060
3061	#else
3062	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3063	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3064	return VERR_INTERNAL_ERROR;
3065	#endif
3066	}
3067
3068
3069
3070	/**
3071	* Prefetch a page/set of pages.
3072	*
3073	* Typically used to sync commonly used pages before entering raw mode
3074	* after a CR3 reload.
3075	*
3076	* @returns VBox status code.
3077	* @param pVCpu The VMCPU handle.
3078	* @param GCPtrPage Page to invalidate.
3079	*/
3080	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3081	{
3082	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3083	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3084	/*
3085	* Check that all Guest levels thru the PDE are present, getting the
3086	* PD and PDE in the processes.
3087	*/
3088	int rc = VINF_SUCCESS;
3089	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3090	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3091	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3092	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3093	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3094	unsigned iPDSrc;
3095	X86PDPE PdpeSrc;
3096	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3097	if (!pPDSrc)
3098	return VINF_SUCCESS; /* not present */
3099	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3100	unsigned iPDSrc;
3101	PX86PML4E pPml4eSrc;
3102	X86PDPE PdpeSrc;
3103	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3104	if (!pPDSrc)
3105	return VINF_SUCCESS; /* not present */
3106	# endif
3107	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3108	# else
3109	PGSTPD pPDSrc = NULL;
3110	const unsigned iPDSrc = 0;
3111	GSTPDE PdeSrc;
3112
3113	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3114	PdeSrc.n.u1Present = 1;
3115	PdeSrc.n.u1Write = 1;
3116	PdeSrc.n.u1Accessed = 1;
3117	PdeSrc.n.u1User = 1;
3118	# endif
3119
3120	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3121	{
3122	PVM pVM = pVCpu->CTX_SUFF(pVM);
3123	pgmLock(pVM);
3124
3125	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3126	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3127	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3128	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3129	PX86PDPAE pPDDst;
3130	X86PDEPAE PdeDst;
3131	# if PGM_GST_TYPE != PGM_TYPE_PAE
3132	X86PDPE PdpeSrc;
3133
3134	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3135	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3136	# endif
3137	int rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3138	if (rc != VINF_SUCCESS)
3139	{
3140	pgmUnlock(pVM);
3141	AssertRC(rc);
3142	return rc;
3143	}
3144	Assert(pPDDst);
3145	PdeDst = pPDDst->a[iPDDst];
3146
3147	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3148	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3149	PX86PDPAE pPDDst;
3150	X86PDEPAE PdeDst;
3151
3152	# if PGM_GST_TYPE == PGM_TYPE_PROT
3153	/* AMD-V nested paging */
3154	X86PML4E Pml4eSrc;
3155	X86PDPE PdpeSrc;
3156	PX86PML4E pPml4eSrc = &Pml4eSrc;
3157
3158	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3159	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3160	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3161	# endif
3162
3163	int rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3164	if (rc != VINF_SUCCESS)
3165	{
3166	pgmUnlock(pVM);
3167	AssertRC(rc);
3168	return rc;
3169	}
3170	Assert(pPDDst);
3171	PdeDst = pPDDst->a[iPDDst];
3172	# endif
3173	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3174	{
3175	if (!PdeDst.n.u1Present)
3176	{
3177	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3178	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3179	}
3180	else
3181	{
3182	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3183	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3184	* makes no sense to prefetch more than one page.
3185	*/
3186	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3187	if (RT_SUCCESS(rc))
3188	rc = VINF_SUCCESS;
3189	}
3190	}
3191	pgmUnlock(pVM);
3192	}
3193	return rc;
3194
3195	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3196	return VINF_SUCCESS; /* ignore */
3197	#endif
3198	}
3199
3200
3201
3202
3203	/**
3204	* Syncs a page during a PGMVerifyAccess() call.
3205	*
3206	* @returns VBox status code (informational included).
3207	* @param pVCpu The VMCPU handle.
3208	* @param GCPtrPage The address of the page to sync.
3209	* @param fPage The effective guest page flags.
3210	* @param uErr The trap error code.
3211	*/
3212	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3213	{
3214	PVM pVM = pVCpu->CTX_SUFF(pVM);
3215
3216	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3217
3218	Assert(!HWACCMIsNestedPagingActive(pVM));
3219	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3220	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3221
3222	# ifndef IN_RING0
3223	if (!(fPage & X86_PTE_US))
3224	{
3225	/*
3226	* Mark this page as safe.
3227	*/
3228	/** @todo not correct for pages that contain both code and data!! */
3229	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3230	CSAMMarkPage(pVM, (RTRCPTR)GCPtrPage, true);
3231	}
3232	# endif
3233
3234	/*
3235	* Get guest PD and index.
3236	*/
3237	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3238	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3239	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3240	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3241	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3242	unsigned iPDSrc = 0;
3243	X86PDPE PdpeSrc;
3244	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3245
3246	if (pPDSrc)
3247	{
3248	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3249	return VINF_EM_RAW_GUEST_TRAP;
3250	}
3251	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3252	unsigned iPDSrc;
3253	PX86PML4E pPml4eSrc;
3254	X86PDPE PdpeSrc;
3255	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3256	if (!pPDSrc)
3257	{
3258	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3259	return VINF_EM_RAW_GUEST_TRAP;
3260	}
3261	# endif
3262	# else
3263	PGSTPD pPDSrc = NULL;
3264	const unsigned iPDSrc = 0;
3265	# endif
3266	int rc = VINF_SUCCESS;
3267
3268	pgmLock(pVM);
3269
3270	/*
3271	* First check if the shadow pd is present.
3272	*/
3273	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3274	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3275	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3276	PX86PDEPAE pPdeDst;
3277	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3278	PX86PDPAE pPDDst;
3279	# if PGM_GST_TYPE != PGM_TYPE_PAE
3280	X86PDPE PdpeSrc;
3281
3282	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3283	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3284	# endif
3285	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3286	if (rc != VINF_SUCCESS)
3287	{
3288	pgmUnlock(pVM);
3289	AssertRC(rc);
3290	return rc;
3291	}
3292	Assert(pPDDst);
3293	pPdeDst = &pPDDst->a[iPDDst];
3294
3295	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3296	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3297	PX86PDPAE pPDDst;
3298	PX86PDEPAE pPdeDst;
3299
3300	# if PGM_GST_TYPE == PGM_TYPE_PROT
3301	/* AMD-V nested paging */
3302	X86PML4E Pml4eSrc;
3303	X86PDPE PdpeSrc;
3304	PX86PML4E pPml4eSrc = &Pml4eSrc;
3305
3306	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3307	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3308	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3309	# endif
3310
3311	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3312	if (rc != VINF_SUCCESS)
3313	{
3314	pgmUnlock(pVM);
3315	AssertRC(rc);
3316	return rc;
3317	}
3318	Assert(pPDDst);
3319	pPdeDst = &pPDDst->a[iPDDst];
3320	# endif
3321
3322	# if defined(IN_RC)
3323	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3324	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3325	# endif
3326
3327	if (!pPdeDst->n.u1Present)
3328	{
3329	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3330	if (rc != VINF_SUCCESS)
3331	{
3332	# if defined(IN_RC)
3333	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3334	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3335	# endif
3336	pgmUnlock(pVM);
3337	AssertRC(rc);
3338	return rc;
3339	}
3340	}
3341
3342	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3343	/* Check for dirty bit fault */
3344	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3345	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3346	Log(("PGMVerifyAccess: success (dirty)\n"));
3347	else
3348	{
3349	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3350	# else
3351	{
3352	GSTPDE PdeSrc;
3353	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3354	PdeSrc.n.u1Present = 1;
3355	PdeSrc.n.u1Write = 1;
3356	PdeSrc.n.u1Accessed = 1;
3357	PdeSrc.n.u1User = 1;
3358
3359	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3360	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3361	if (uErr & X86_TRAP_PF_US)
3362	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3363	else /* supervisor */
3364	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3365
3366	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3367	if (RT_SUCCESS(rc))
3368	{
3369	/* Page was successfully synced */
3370	Log2(("PGMVerifyAccess: success (sync)\n"));
3371	rc = VINF_SUCCESS;
3372	}
3373	else
3374	{
3375	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3376	rc = VINF_EM_RAW_GUEST_TRAP;
3377	}
3378	}
3379	# if defined(IN_RC)
3380	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3381	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3382	# endif
3383	pgmUnlock(pVM);
3384	return rc;
3385
3386	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3387
3388	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3389	return VERR_INTERNAL_ERROR;
3390	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3391	}
3392
3393	#undef MY_STAM_COUNTER_INC
3394	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3395
3396
3397	/**
3398	* Syncs the paging hierarchy starting at CR3.
3399	*
3400	* @returns VBox status code, no specials.
3401	* @param pVCpu The VMCPU handle.
3402	* @param cr0 Guest context CR0 register
3403	* @param cr3 Guest context CR3 register
3404	* @param cr4 Guest context CR4 register
3405	* @param fGlobal Including global page directories or not
3406	*/
3407	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3408	{
3409	PVM pVM = pVCpu->CTX_SUFF(pVM);
3410
3411	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3412	fGlobal = true; /* Change this CR3 reload to be a global one. */
3413
3414	LogFlow(("SyncCR3 %d\n", fGlobal));
3415
3416	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3417
3418	pgmLock(pVM);
3419	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3420	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3421	if (pPool->cDirtyPages)
3422	pgmPoolResetDirtyPages(pVM);
3423	# endif
3424
3425	/*
3426	* Update page access handlers.
3427	* The virtual are always flushed, while the physical are only on demand.
3428	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3429	* have to look into that later because it will have a bad influence on the performance.
3430	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3431	* bird: Yes, but that won't work for aliases.
3432	*/
3433	/** @todo this MUST go away. See #1557. */
3434	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3435	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3436	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3437	pgmUnlock(pVM);
3438	#endif
3439
3440	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3441	/*
3442	* Nested / EPT - almost no work.
3443	*/
3444	/** @todo check if this is really necessary; the call does it as well... */
3445	HWACCMFlushTLB(pVCpu);
3446	return VINF_SUCCESS;
3447
3448	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3449	/*
3450	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3451	* out the shadow parts when the guest modifies its tables.
3452	*/
3453	return VINF_SUCCESS;
3454
3455	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3456
3457	# ifdef PGM_WITHOUT_MAPPINGS
3458	Assert(pVM->pgm.s.fMappingsFixed);
3459	return VINF_SUCCESS;
3460	# else
3461	/* Nothing to do when mappings are fixed. */
3462	if (pVM->pgm.s.fMappingsFixed)
3463	return VINF_SUCCESS;
3464
3465	int rc = PGMMapResolveConflicts(pVM);
3466	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3467	if (rc == VINF_PGM_SYNC_CR3)
3468	{
3469	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3470	return VINF_PGM_SYNC_CR3;
3471	}
3472	# endif
3473	return VINF_SUCCESS;
3474	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3475	}
3476
3477
3478
3479
3480	#ifdef VBOX_STRICT
3481	#ifdef IN_RC
3482	# undef AssertMsgFailed
3483	# define AssertMsgFailed Log
3484	#endif
3485	#ifdef IN_RING3
3486	# include <VBox/dbgf.h>
3487
3488	/**
3489	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3490	*
3491	* @returns VBox status code (VINF_SUCCESS).
3492	* @param cr3 The root of the hierarchy.
3493	* @param crr The cr4, only PAE and PSE is currently used.
3494	* @param fLongMode Set if long mode, false if not long mode.
3495	* @param cMaxDepth Number of levels to dump.
3496	* @param pHlp Pointer to the output functions.
3497	*/
3498	RT_C_DECLS_BEGIN
3499	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3500	RT_C_DECLS_END
3501
3502	#endif
3503
3504	/**
3505	* Checks that the shadow page table is in sync with the guest one.
3506	*
3507	* @returns The number of errors.
3508	* @param pVM The virtual machine.
3509	* @param pVCpu The VMCPU handle.
3510	* @param cr3 Guest context CR3 register
3511	* @param cr4 Guest context CR4 register
3512	* @param GCPtr Where to start. Defaults to 0.
3513	* @param cb How much to check. Defaults to everything.
3514	*/
3515	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3516	{
3517	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3518	return 0;
3519	#else
3520	unsigned cErrors = 0;
3521	PVM pVM = pVCpu->CTX_SUFF(pVM);
3522	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3523
3524	#if PGM_GST_TYPE == PGM_TYPE_PAE
3525	/** @todo currently broken; crashes below somewhere */
3526	AssertFailed();
3527	#endif
3528
3529	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3530	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3531	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3532
3533	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3534	bool fBigPagesSupported = true;
3535	# else
3536	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3537	# endif
3538	PPGMCPU pPGM = &pVCpu->pgm.s;
3539	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3540	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3541	# ifndef IN_RING0
3542	RTHCPHYS HCPhys; /* general usage. */
3543	# endif
3544	int rc;
3545
3546	/*
3547	* Check that the Guest CR3 and all its mappings are correct.
3548	*/
3549	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3550	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3551	false);
3552	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3553	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3554	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3555	# else
3556	rc = PGMShwGetPage(pVCpu, (RTGCPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3557	# endif
3558	AssertRCReturn(rc, 1);
3559	HCPhys = NIL_RTHCPHYS;
3560	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3561	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3562	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3563	pgmGstGet32bitPDPtr(pPGM);
3564	RTGCPHYS GCPhys;
3565	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3566	AssertRCReturn(rc, 1);
3567	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3568	# endif
3569	# endif /* !IN_RING0 */
3570
3571	/*
3572	* Get and check the Shadow CR3.
3573	*/
3574	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3575	unsigned cPDEs = X86_PG_ENTRIES;
3576	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3577	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3578	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3579	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3580	# else
3581	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3582	# endif
3583	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3584	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3585	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3586	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3587	# endif
3588	if (cb != ~(RTGCPTR)0)
3589	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3590
3591	/** @todo call the other two PGMAssert() functions. /
3592
3593	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3594	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3595
3596	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3597	{
3598	PPGMPOOLPAGE pShwPdpt = NULL;
3599	PX86PML4E pPml4eSrc;
3600	PX86PML4E pPml4eDst;
3601	RTGCPHYS GCPhysPdptSrc;
3602
3603	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3604	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3605
3606	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3607	if (!pPml4eDst->n.u1Present)
3608	{
3609	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3610	continue;
3611	}
3612
3613	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3614	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3615
3616	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3617	{
3618	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3619	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3620	cErrors++;
3621	continue;
3622	}
3623
3624	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3625	{
3626	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3627	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3628	cErrors++;
3629	continue;
3630	}
3631
3632	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3633	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3634	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3635	{
3636	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3637	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3638	cErrors++;
3639	continue;
3640	}
3641	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3642	{
3643	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3644
3645	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3646	/*
3647	* Check the PDPTEs too.
3648	*/
3649	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3650
3651	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3652	{
3653	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3654	PPGMPOOLPAGE pShwPde = NULL;
3655	PX86PDPE pPdpeDst;
3656	RTGCPHYS GCPhysPdeSrc;
3657	# if PGM_GST_TYPE == PGM_TYPE_PAE
3658	X86PDPE PdpeSrc;
3659	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3660	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3661	# else
3662	PX86PML4E pPml4eSrc;
3663	X86PDPE PdpeSrc;
3664	PX86PDPT pPdptDst;
3665	PX86PDPAE pPDDst;
3666	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3667
3668	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3669	if (rc != VINF_SUCCESS)
3670	{
3671	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3672	GCPtr += 512 * _2M;
3673	continue; /* next PDPTE */
3674	}
3675	Assert(pPDDst);
3676	# endif
3677	Assert(iPDSrc == 0);
3678
3679	pPdpeDst = &pPdptDst->a[iPdpt];
3680
3681	if (!pPdpeDst->n.u1Present)
3682	{
3683	GCPtr += 512 * _2M;
3684	continue; /* next PDPTE */
3685	}
3686
3687	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3688	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3689
3690	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3691	{
3692	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3693	GCPtr += 512 * _2M;
3694	cErrors++;
3695	continue;
3696	}
3697
3698	if (GCPhysPdeSrc != pShwPde->GCPhys)
3699	{
3700	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3701	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3702	# else
3703	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3704	# endif
3705	GCPtr += 512 * _2M;
3706	cErrors++;
3707	continue;
3708	}
3709
3710	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3711	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3712	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3713	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3714	{
3715	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3716	GCPtr += 512 * _2M;
3717	cErrors++;
3718	continue;
3719	}
3720	# endif
3721
3722	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3723	{
3724	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3725	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3726	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3727	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3728	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3729	# endif
3730	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3731	/*
3732	* Iterate the shadow page directory.
3733	*/
3734	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3735	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3736
3737	for (;
3738	iPDDst < cPDEs;
3739	iPDDst++, GCPtr += cIncrement)
3740	{
3741	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3742	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3743	# else
3744	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3745	# endif
3746	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3747	{
3748	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3749	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3750	{
3751	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3752	cErrors++;
3753	continue;
3754	}
3755	}
3756	else if ( (PdeDst.u & X86_PDE_P)
3757	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3758	)
3759	{
3760	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3761	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3762	if (!pPoolPage)
3763	{
3764	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3765	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3766	cErrors++;
3767	continue;
3768	}
3769	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3770
3771	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3772	{
3773	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3774	GCPtr, (uint64_t)PdeDst.u));
3775	cErrors++;
3776	}
3777
3778	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3779	{
3780	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3781	GCPtr, (uint64_t)PdeDst.u));
3782	cErrors++;
3783	}
3784
3785	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3786	if (!PdeSrc.n.u1Present)
3787	{
3788	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3789	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3790	cErrors++;
3791	continue;
3792	}
3793
3794	if ( !PdeSrc.b.u1Size
3795	\|\| !fBigPagesSupported)
3796	{
3797	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3798	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3799	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3800	# endif
3801	}
3802	else
3803	{
3804	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3805	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3806	{
3807	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3808	GCPtr, (uint64_t)PdeSrc.u));
3809	cErrors++;
3810	continue;
3811	}
3812	# endif
3813	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3814	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3815	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3816	# endif
3817	}
3818
3819	if ( pPoolPage->enmKind
3820	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3821	{
3822	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3823	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3824	cErrors++;
3825	}
3826
3827	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3828	if (!pPhysPage)
3829	{
3830	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3831	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3832	cErrors++;
3833	continue;
3834	}
3835
3836	if (GCPhysGst != pPoolPage->GCPhys)
3837	{
3838	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3839	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3840	cErrors++;
3841	continue;
3842	}
3843
3844	if ( !PdeSrc.b.u1Size
3845	\|\| !fBigPagesSupported)
3846	{
3847	/*
3848	* Page Table.
3849	*/
3850	const GSTPT *pPTSrc;
3851	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3852	if (RT_FAILURE(rc))
3853	{
3854	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3855	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3856	cErrors++;
3857	continue;
3858	}
3859	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3860	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3861	{
3862	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3863	// (This problem will go away when/if we shadow multiple CR3s.)
3864	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3865	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3866	cErrors++;
3867	continue;
3868	}
3869	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3870	{
3871	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3872	GCPtr, (uint64_t)PdeDst.u));
3873	cErrors++;
3874	continue;
3875	}
3876
3877	/* iterate the page table. */
3878	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3879	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3880	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3881	# else
3882	const unsigned offPTSrc = 0;
3883	# endif
3884	for (unsigned iPT = 0, off = 0;
3885	iPT < RT_ELEMENTS(pPTDst->a);
3886	iPT++, off += PAGE_SIZE)
3887	{
3888	const SHWPTE PteDst = pPTDst->a[iPT];
3889
3890	/* skip not-present entries. */
3891	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3892	continue;
3893	Assert(PteDst.n.u1Present);
3894
3895	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3896	if (!PteSrc.n.u1Present)
3897	{
3898	# ifdef IN_RING3
3899	PGMAssertHandlerAndFlagsInSync(pVM);
3900	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3901	# endif
3902	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3903	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3904	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3905	cErrors++;
3906	continue;
3907	}
3908
3909	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3910	# if 1 /** @todo sync accessed bit properly... */
3911	fIgnoreFlags \|= X86_PTE_A;
3912	# endif
3913
3914	/* match the physical addresses */
3915	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3916	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3917
3918	# ifdef IN_RING3
3919	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3920	if (RT_FAILURE(rc))
3921	{
3922	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3923	{
3924	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3925	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3926	cErrors++;
3927	continue;
3928	}
3929	}
3930	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3931	{
3932	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3933	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3934	cErrors++;
3935	continue;
3936	}
3937	# endif
3938
3939	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3940	if (!pPhysPage)
3941	{
3942	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3943	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3944	{
3945	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3946	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3947	cErrors++;
3948	continue;
3949	}
3950	# endif
3951	if (PteDst.n.u1Write)
3952	{
3953	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3954	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3955	cErrors++;
3956	}
3957	fIgnoreFlags \|= X86_PTE_RW;
3958	}
3959	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3960	{
3961	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3962	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3963	cErrors++;
3964	continue;
3965	}
3966
3967	/* flags */
3968	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3969	{
3970	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3971	{
3972	if (PteDst.n.u1Write)
3973	{
3974	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3975	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3976	cErrors++;
3977	continue;
3978	}
3979	fIgnoreFlags \|= X86_PTE_RW;
3980	}
3981	else
3982	{
3983	if (PteDst.n.u1Present)
3984	{
3985	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3986	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3987	cErrors++;
3988	continue;
3989	}
3990	fIgnoreFlags \|= X86_PTE_P;
3991	}
3992	}
3993	else
3994	{
3995	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3996	{
3997	if (PteDst.n.u1Write)
3998	{
3999	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4000	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4001	cErrors++;
4002	continue;
4003	}
4004	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4005	{
4006	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4007	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4008	cErrors++;
4009	continue;
4010	}
4011	if (PteDst.n.u1Dirty)
4012	{
4013	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4014	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4015	cErrors++;
4016	}
4017	# if 0 /** @todo sync access bit properly... */
4018	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4019	{
4020	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4021	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4022	cErrors++;
4023	}
4024	fIgnoreFlags \|= X86_PTE_RW;
4025	# else
4026	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4027	# endif
4028	}
4029	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4030	{
4031	/* access bit emulation (not implemented). */
4032	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4033	{
4034	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4035	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4036	cErrors++;
4037	continue;
4038	}
4039	if (!PteDst.n.u1Accessed)
4040	{
4041	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4042	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4043	cErrors++;
4044	}
4045	fIgnoreFlags \|= X86_PTE_P;
4046	}
4047	# ifdef DEBUG_sandervl
4048	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4049	# endif
4050	}
4051
4052	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4053	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4054	)
4055	{
4056	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4057	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4058	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4059	cErrors++;
4060	continue;
4061	}
4062	} /* foreach PTE */
4063	}
4064	else
4065	{
4066	/*
4067	* Big Page.
4068	*/
4069	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4070	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4071	{
4072	if (PdeDst.n.u1Write)
4073	{
4074	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4075	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4076	cErrors++;
4077	continue;
4078	}
4079	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4080	{
4081	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4082	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4083	cErrors++;
4084	continue;
4085	}
4086	# if 0 /** @todo sync access bit properly... */
4087	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4088	{
4089	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4090	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4091	cErrors++;
4092	}
4093	fIgnoreFlags \|= X86_PTE_RW;
4094	# else
4095	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4096	# endif
4097	}
4098	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4099	{
4100	/* access bit emulation (not implemented). */
4101	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4102	{
4103	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4104	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4105	cErrors++;
4106	continue;
4107	}
4108	if (!PdeDst.n.u1Accessed)
4109	{
4110	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4111	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4112	cErrors++;
4113	}
4114	fIgnoreFlags \|= X86_PTE_P;
4115	}
4116
4117	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4118	{
4119	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4120	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4121	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4122	cErrors++;
4123	}
4124
4125	/* iterate the page table. */
4126	for (unsigned iPT = 0, off = 0;
4127	iPT < RT_ELEMENTS(pPTDst->a);
4128	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4129	{
4130	const SHWPTE PteDst = pPTDst->a[iPT];
4131
4132	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4133	{
4134	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4135	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4136	cErrors++;
4137	}
4138
4139	/* skip not-present entries. */
4140	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4141	continue;
4142
4143	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4144
4145	/* match the physical addresses */
4146	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4147
4148	# ifdef IN_RING3
4149	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4150	if (RT_FAILURE(rc))
4151	{
4152	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4153	{
4154	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4155	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4156	cErrors++;
4157	}
4158	}
4159	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4160	{
4161	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4162	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4163	cErrors++;
4164	continue;
4165	}
4166	# endif
4167	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4168	if (!pPhysPage)
4169	{
4170	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4171	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4172	{
4173	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4174	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4175	cErrors++;
4176	continue;
4177	}
4178	# endif
4179	if (PteDst.n.u1Write)
4180	{
4181	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4182	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4183	cErrors++;
4184	}
4185	fIgnoreFlags \|= X86_PTE_RW;
4186	}
4187	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4188	{
4189	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4190	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4191	cErrors++;
4192	continue;
4193	}
4194
4195	/* flags */
4196	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4197	{
4198	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4199	{
4200	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4201	{
4202	if (PteDst.n.u1Write)
4203	{
4204	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4205	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4206	cErrors++;
4207	continue;
4208	}
4209	fIgnoreFlags \|= X86_PTE_RW;
4210	}
4211	}
4212	else
4213	{
4214	if (PteDst.n.u1Present)
4215	{
4216	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4217	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4218	cErrors++;
4219	continue;
4220	}
4221	fIgnoreFlags \|= X86_PTE_P;
4222	}
4223	}
4224
4225	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4226	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4227	)
4228	{
4229	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4230	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4231	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4232	cErrors++;
4233	continue;
4234	}
4235	} /* for each PTE */
4236	}
4237	}
4238	/* not present */
4239
4240	} /* for each PDE */
4241
4242	} /* for each PDPTE */
4243
4244	} /* for each PML4E */
4245
4246	# ifdef DEBUG
4247	if (cErrors)
4248	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4249	# endif
4250
4251	#endif /* GST == 32BIT, PAE or AMD64 */
4252	return cErrors;
4253
4254	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4255	}
4256	#endif /* VBOX_STRICT */
4257
4258
4259	/**
4260	* Sets up the CR3 for shadow paging
4261	*
4262	* @returns Strict VBox status code.
4263	* @retval VINF_SUCCESS.
4264	*
4265	* @param pVCpu The VMCPU handle.
4266	* @param GCPhysCR3 The physical address in the CR3 register.
4267	*/
4268	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4269	{
4270	PVM pVM = pVCpu->CTX_SUFF(pVM);
4271
4272	/* Update guest paging info. */
4273	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4274	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4275	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4276
4277	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4278
4279	/*
4280	* Map the page CR3 points at.
4281	*/
4282	RTHCPTR HCPtrGuestCR3;
4283	RTHCPHYS HCPhysGuestCR3;
4284	pgmLock(pVM);
4285	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4286	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4287	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPage);
4288	/** @todo this needs some reworking wrt. locking. */
4289	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4290	HCPtrGuestCR3 = NIL_RTHCPTR;
4291	int rc = VINF_SUCCESS;
4292	# else
4293	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4294	# endif
4295	pgmUnlock(pVM);
4296	if (RT_SUCCESS(rc))
4297	{
4298	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4299	if (RT_SUCCESS(rc))
4300	{
4301	# ifdef IN_RC
4302	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4303	# endif
4304	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4305	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4306	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4307	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4308	# endif
4309	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))pVM->pgm.s.GCPtrCR3Mapping;
4310
4311	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4312	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4313	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4314	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4315	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4316	# endif
4317	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RCPTRTYPE(uint8_t *))pVM->pgm.s.GCPtrCR3Mapping + off);
4318	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4319
4320	/*
4321	* Map the 4 PDs too.
4322	*/
4323	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4324	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4325	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4326	{
4327	if (pGuestPDPT->a[i].n.u1Present)
4328	{
4329	RTHCPTR HCPtr;
4330	RTHCPHYS HCPhys;
4331	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4332	pgmLock(pVM);
4333	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4334	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4335	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4336	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4337	HCPtr = NIL_RTHCPTR;
4338	int rc2 = VINF_SUCCESS;
4339	# else
4340	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4341	# endif
4342	pgmUnlock(pVM);
4343	if (RT_SUCCESS(rc2))
4344	{
4345	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4346	AssertRCReturn(rc, rc);
4347
4348	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4349	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4350	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4351	# endif
4352	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))GCPtr;
4353	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4354	# ifdef IN_RC
4355	PGM_INVL_PG(pVCpu, GCPtr);
4356	# endif
4357	continue;
4358	}
4359	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4360	}
4361
4362	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4363	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4364	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4365	# endif
4366	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4367	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4368	# ifdef IN_RC
4369	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4370	# endif
4371	}
4372
4373	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4374	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4375	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4376	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4377	# endif
4378	# endif
4379	}
4380	else
4381	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4382	}
4383	else
4384	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4385
4386	#else /* prot/real stub */
4387	int rc = VINF_SUCCESS;
4388	#endif
4389
4390	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4391	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4392	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4393	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4394	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4395	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4396
4397	Assert(!HWACCMIsNestedPagingActive(pVM));
4398
4399	/*
4400	* Update the shadow root page as well since that's not fixed.
4401	*/
4402	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4403	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4404	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4405	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4406	PPGMPOOLPAGE pNewShwPageCR3;
4407
4408	pgmLock(pVM);
4409
4410	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4411	if (pPool->cDirtyPages)
4412	pgmPoolResetDirtyPages(pVM);
4413	# endif
4414
4415	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4416	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4417	AssertFatalRC(rc);
4418	rc = VINF_SUCCESS;
4419
4420	# ifdef IN_RC
4421	/*
4422	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4423	* state will be inconsistent! Flush important things now while
4424	* we still can and then make sure there are no ring-3 calls.
4425	*/
4426	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4427	VMMRZCallRing3Disable(pVCpu);
4428	# endif
4429
4430	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4431	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4432	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4433	# ifdef IN_RING0
4434	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4435	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4436	# elif defined(IN_RC)
4437	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4438	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4439	# else
4440	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4441	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4442	# endif
4443
4444	# ifndef PGM_WITHOUT_MAPPINGS
4445	/*
4446	* Apply all hypervisor mappings to the new CR3.
4447	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4448	* make sure we check for conflicts in the new CR3 root.
4449	*/
4450	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4451	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4452	# endif
4453	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4454	AssertRCReturn(rc, rc);
4455	# endif
4456
4457	/* Set the current hypervisor CR3. */
4458	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4459	SELMShadowCR3Changed(pVM, pVCpu);
4460
4461	# ifdef IN_RC
4462	/* NOTE: The state is consistent again. */
4463	VMMRZCallRing3Enable(pVCpu);
4464	# endif
4465
4466	/* Clean up the old CR3 root. */
4467	if ( pOldShwPageCR3
4468	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4469	{
4470	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4471	# ifndef PGM_WITHOUT_MAPPINGS
4472	/* Remove the hypervisor mappings from the shadow page table. */
4473	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4474	# endif
4475	/* Mark the page as unlocked; allow flushing again. */
4476	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4477
4478	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4479	}
4480	pgmUnlock(pVM);
4481	# endif
4482
4483	return rc;
4484	}
4485
4486	/**
4487	* Unmaps the shadow CR3.
4488	*
4489	* @returns VBox status, no specials.
4490	* @param pVCpu The VMCPU handle.
4491	*/
4492	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4493	{
4494	LogFlow(("UnmapCR3\n"));
4495
4496	int rc = VINF_SUCCESS;
4497	PVM pVM = pVCpu->CTX_SUFF(pVM);
4498
4499	/*
4500	* Update guest paging info.
4501	*/
4502	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4503	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4504	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4505	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4506	# endif
4507	pVCpu->pgm.s.pGst32BitPdRC = 0;
4508
4509	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4510	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4511	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4512	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4513	# endif
4514	pVCpu->pgm.s.pGstPaePdptRC = 0;
4515	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4516	{
4517	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4518	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4519	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4520	# endif
4521	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4522	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4523	}
4524
4525	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4526	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4527	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4528	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4529	# endif
4530
4531	#else /* prot/real mode stub */
4532	/* nothing to do */
4533	#endif
4534
4535	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4536	/*
4537	* Update shadow paging info.
4538	*/
4539	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4540	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4541	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4542
4543	# if PGM_GST_TYPE != PGM_TYPE_REAL
4544	Assert(!HWACCMIsNestedPagingActive(pVM));
4545	# endif
4546
4547	pgmLock(pVM);
4548
4549	# ifndef PGM_WITHOUT_MAPPINGS
4550	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4551	/* Remove the hypervisor mappings from the shadow page table. */
4552	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4553	# endif
4554
4555	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4556	{
4557	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4558
4559	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4560
4561	/* Mark the page as unlocked; allow flushing again. */
4562	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4563
4564	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4565	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4566	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4567	pVCpu->pgm.s.pShwPageCR3RC = 0;
4568	pVCpu->pgm.s.iShwUser = 0;
4569	pVCpu->pgm.s.iShwUserTable = 0;
4570	}
4571	pgmUnlock(pVM);
4572	# endif
4573	#endif /* !IN_RC*/
4574
4575	return rc;
4576	}
4577

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 22512

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