PGMAllBth.h@ 26701

Last change on this file since 26701 was 26701, checked in by vboxsync, 15 years ago
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1	/* $Id: PGMAllBth.h 26701 2010-02-23 13:25:38Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	RT_C_DECLS_BEGIN
28	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
29	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
32	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
33	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
34	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
35	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
37	#ifdef VBOX_STRICT
38	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
39	#endif
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
42	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
43	RT_C_DECLS_END
44
45
46	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
47	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
48	# error "Invalid combination; PAE guest implies PAE shadow"
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
53	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
57	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
58	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
59	#endif
60
61	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
62	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
63	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
64	#endif
65
66
67	#ifndef IN_RING3
68	/**
69	* #PF Handler for raw-mode guest execution.
70	*
71	* @returns VBox status code (appropriate for trap handling and GC return).
72	*
73	* @param pVCpu VMCPU Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	* @param pfLockTaken PGM lock taken here or not (out)
78	*/
79	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
80	{
81	PVM pVM = pVCpu->CTX_SUFF(pVM);
82
83	*pfLockTaken = false;
84
85	# if defined(IN_RC) && defined(VBOX_STRICT)
86	PGMDynCheckLocks(pVM);
87	# endif
88
89	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
90	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
91	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
92
93	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
94	/*
95	* Hide the instruction fetch trap indicator for now.
96	*/
97	/** @todo NXE will change this and we must fix NXE in the switcher too! */
98	if (uErr & X86_TRAP_PF_ID)
99	{
100	uErr &= ~X86_TRAP_PF_ID;
101	TRPMSetErrorCode(pVCpu, uErr);
102	}
103	# endif
104
105	/*
106	* Get PDs.
107	*/
108	int rc;
109	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
110	# if PGM_GST_TYPE == PGM_TYPE_32BIT
111	const unsigned iPDSrc = pvFault >> GST_PD_SHIFT;
112	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
113
114	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
115
116	# if PGM_GST_TYPE == PGM_TYPE_PAE
117	unsigned iPDSrc = 0; /* initialized to shut up gcc */
118	X86PDPE PdpeSrc;
119	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, pvFault, &iPDSrc, &PdpeSrc);
120
121	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
122	unsigned iPDSrc = 0; /* initialized to shut up gcc */
123	PX86PML4E pPml4eSrc;
124	X86PDPE PdpeSrc;
125	PGSTPD pPDSrc;
126
127	pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, pvFault, &pPml4eSrc, &PdpeSrc, &iPDSrc);
128	Assert(pPml4eSrc);
129	# endif
130
131	/* Quick check for a valid guest trap. (PAE & AMD64) */
132	if (!pPDSrc)
133	{
134	# if PGM_GST_TYPE == PGM_TYPE_AMD64 && GC_ARCH_BITS == 64
135	LogFlow(("Trap0eHandler: guest PML4 %d not present CR3=%RGp\n", (int)((pvFault >> X86_PML4_SHIFT) & X86_PML4_MASK), CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
136	# else
137	LogFlow(("Trap0eHandler: guest iPDSrc=%u not present CR3=%RGp\n", iPDSrc, CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK));
138	# endif
139	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
140	TRPMSetErrorCode(pVCpu, uErr);
141	return VINF_EM_RAW_GUEST_TRAP;
142	}
143	# endif
144
145	# else /* !PGM_WITH_PAGING */
146	PGSTPD pPDSrc = NULL;
147	const unsigned iPDSrc = 0;
148	# endif /* !PGM_WITH_PAGING */
149
150	/* First check for a genuine guest page fault. */
151	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
153	rc = PGM_BTH_NAME(CheckPageFault)(pVCpu, uErr, &pPDSrc->a[iPDSrc], pvFault);
154	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeCheckPageFault, e);
155	if (rc == VINF_EM_RAW_GUEST_TRAP)
156	{
157	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
158	= &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
159	return rc;
160	}
161	# endif /* PGM_WITH_PAGING */
162
163	/* Take the big lock now. */
164	*pfLockTaken = true;
165	pgmLock(pVM);
166
167	/* Fetch the guest PDE */
168	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
169	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
170	# else
171	GSTPDE PdeSrc;
172	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
173	PdeSrc.n.u1Present = 1;
174	PdeSrc.n.u1Write = 1;
175	PdeSrc.n.u1Accessed = 1;
176	PdeSrc.n.u1User = 1;
177	# endif
178
179	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
180	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
181	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
182
183	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
184	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
185
186	PX86PDPAE pPDDst;
187	# if PGM_GST_TYPE != PGM_TYPE_PAE
188	X86PDPE PdpeSrc;
189
190	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
191	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
192	# endif
193	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, &PdpeSrc, &pPDDst);
194	if (rc != VINF_SUCCESS)
195	{
196	AssertRC(rc);
197	return rc;
198	}
199	Assert(pPDDst);
200
201	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
202	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
203	PX86PDPAE pPDDst;
204	# if PGM_GST_TYPE == PGM_TYPE_PROT
205	/* AMD-V nested paging */
206	X86PML4E Pml4eSrc;
207	X86PDPE PdpeSrc;
208	PX86PML4E pPml4eSrc = &Pml4eSrc;
209
210	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
211	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
212	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
213	# endif
214
215	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, pPml4eSrc, &PdpeSrc, &pPDDst);
216	if (rc != VINF_SUCCESS)
217	{
218	AssertRC(rc);
219	return rc;
220	}
221	Assert(pPDDst);
222
223	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
224	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
225	PEPTPD pPDDst;
226
227	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
228	if (rc != VINF_SUCCESS)
229	{
230	AssertRC(rc);
231	return rc;
232	}
233	Assert(pPDDst);
234	# endif
235
236	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
237	/* Dirty page handling. */
238	if (uErr & X86_TRAP_PF_RW) /* write fault? */
239	{
240	/*
241	* If we successfully correct the write protection fault due to dirty bit
242	* tracking, then return immediately.
243	*/
244	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
245	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], pvFault);
246	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
247	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
248	{
249	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
250	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
251	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
252	return VINF_SUCCESS;
253	}
254	}
255
256	# if 0 /* rarely useful; leave for debugging. */
257	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
258	# endif
259	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
260
261	/*
262	* A common case is the not-present error caused by lazy page table syncing.
263	*
264	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
265	* so we can safely assume that the shadow PT is present when calling SyncPage later.
266	*
267	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
268	* of mapping conflict and defer to SyncCR3 in R3.
269	* (Again, we do NOT support access handlers for non-present guest pages.)
270	*
271	*/
272	Assert(PdeSrc.n.u1Present);
273	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
274	&& !pPDDst->a[iPDDst].n.u1Present
275	)
276	{
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
278	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
279	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
280	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, pvFault);
281	if (RT_SUCCESS(rc))
282	{
283	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
284	return rc;
285	}
286	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
287	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
288	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
289	return VINF_PGM_SYNC_CR3;
290	}
291
292	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
293	/*
294	* Check if this address is within any of our mappings.
295	*
296	* This is very fast and it's gonna save us a bit of effort below and prevent
297	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
298	* (BTW, it's impossible to have physical access handlers in a mapping.)
299	*/
300	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
301	{
302	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
303	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
304	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
305	{
306	if (pvFault < pMapping->GCPtr)
307	break;
308	if (pvFault - pMapping->GCPtr < pMapping->cb)
309	{
310	/*
311	* The first thing we check is if we've got an undetected conflict.
312	*/
313	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
314	{
315	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
316	while (iPT-- > 0)
317	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
318	{
319	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
320	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
321	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
322	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
323	return VINF_PGM_SYNC_CR3;
324	}
325	}
326
327	/*
328	* Check if the fault address is in a virtual page access handler range.
329	*/
330	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
331	if ( pCur
332	&& pvFault - pCur->Core.Key < pCur->cb
333	&& uErr & X86_TRAP_PF_RW)
334	{
335	# ifdef IN_RC
336	STAM_PROFILE_START(&pCur->Stat, h);
337	pgmUnlock(pVM);
338	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
339	pgmLock(pVM);
340	STAM_PROFILE_STOP(&pCur->Stat, h);
341	# else
342	AssertFailed();
343	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
344	# endif
345	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
346	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
347	return rc;
348	}
349
350	/*
351	* Pretend we're not here and let the guest handle the trap.
352	*/
353	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
354	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
355	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
356	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
357	return VINF_EM_RAW_GUEST_TRAP;
358	}
359	}
360	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
361	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
362	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
363
364	/*
365	* Check if this fault address is flagged for special treatment,
366	* which means we'll have to figure out the physical address and
367	* check flags associated with it.
368	*
369	* ASSUME that we can limit any special access handling to pages
370	* in page tables which the guest believes to be present.
371	*/
372	Assert(PdeSrc.n.u1Present);
373	{
374	RTGCPHYS GCPhys = NIL_RTGCPHYS;
375
376	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
377	if ( PdeSrc.b.u1Size
378	# if PGM_GST_TYPE == PGM_TYPE_32BIT
379	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
380	# endif
381	)
382	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc)
383	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
384	else
385	{
386	PGSTPT pPTSrc;
387	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
388	if (RT_SUCCESS(rc))
389	{
390	unsigned iPTESrc = (pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
391	if (pPTSrc->a[iPTESrc].n.u1Present)
392	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
393	}
394	}
395	# else
396	/* No paging so the fault address is the physical address */
397	GCPhys = (RTGCPHYS)(pvFault & ~PAGE_OFFSET_MASK);
398	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
399
400	/*
401	* If we have a GC address we'll check if it has any flags set.
402	*/
403	if (GCPhys != NIL_RTGCPHYS)
404	{
405	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
406
407	PPGMPAGE pPage;
408	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
409	if (RT_SUCCESS(rc)) /** just handle the failure immediate (it returns) and make things easier to read. */
410	{
411	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
412	{
413	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
414	{
415	/*
416	* Physical page access handler.
417	*/
418	const RTGCPHYS GCPhysFault = GCPhys \| (pvFault & PAGE_OFFSET_MASK);
419	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
420	if (pCur)
421	{
422	# ifdef PGM_SYNC_N_PAGES
423	/*
424	* If the region is write protected and we got a page not present fault, then sync
425	* the pages. If the fault was caused by a read, then restart the instruction.
426	* In case of write access continue to the GC write handler.
427	*
428	* ASSUMES that there is only one handler per page or that they have similar write properties.
429	*/
430	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
431	&& !(uErr & X86_TRAP_PF_P))
432	{
433	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
434	if ( RT_FAILURE(rc)
435	\|\| !(uErr & X86_TRAP_PF_RW)
436	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
437	{
438	AssertRC(rc);
439	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
440	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
441	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
442	return rc;
443	}
444	}
445	# endif
446
447	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
448	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
449	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
450
451	# if defined(IN_RC) \|\| defined(IN_RING0)
452	if (pCur->CTX_SUFF(pfnHandler))
453	{
454	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
455	# ifdef IN_RING0
456	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
457	# else
458	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
459	# endif
460	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
461	void *pvUser = pCur->CTX_SUFF(pvUser);
462
463	STAM_PROFILE_START(&pCur->Stat, h);
464	if (fLeaveLock)
465	pgmUnlock(pVM); /* @todo: Not entirely safe. */
466
467	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
468	if (fLeaveLock)
469	pgmLock(pVM);
470	# ifdef VBOX_WITH_STATISTICS
471	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
472	if (pCur)
473	STAM_PROFILE_STOP(&pCur->Stat, h);
474	# else
475	pCur = NULL; /* might be invalid by now. */
476	# endif
477
478	}
479	else
480	# endif
481	rc = VINF_EM_RAW_EMULATE_INSTR;
482
483	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
484	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
485	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
486	return rc;
487	}
488	}
489	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
490	else
491	{
492	# ifdef PGM_SYNC_N_PAGES
493	/*
494	* If the region is write protected and we got a page not present fault, then sync
495	* the pages. If the fault was caused by a read, then restart the instruction.
496	* In case of write access continue to the GC write handler.
497	*/
498	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
499	&& !(uErr & X86_TRAP_PF_P))
500	{
501	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
502	if ( RT_FAILURE(rc)
503	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
504	\|\| !(uErr & X86_TRAP_PF_RW))
505	{
506	AssertRC(rc);
507	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
508	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
509	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
510	return rc;
511	}
512	}
513	# endif
514	/*
515	* Ok, it's an virtual page access handler.
516	*
517	* Since it's faster to search by address, we'll do that first
518	* and then retry by GCPhys if that fails.
519	*/
520	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
521	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
522	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
523	*/
524	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
525	if (pCur)
526	{
527	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
528	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
529	\|\| !(uErr & X86_TRAP_PF_P)
530	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
531	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
532
533	if ( pvFault - pCur->Core.Key < pCur->cb
534	&& ( uErr & X86_TRAP_PF_RW
535	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
536	{
537	# ifdef IN_RC
538	STAM_PROFILE_START(&pCur->Stat, h);
539	pgmUnlock(pVM);
540	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
541	pgmLock(pVM);
542	STAM_PROFILE_STOP(&pCur->Stat, h);
543	# else
544	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
545	# endif
546	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
547	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
548	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
549	return rc;
550	}
551	/* Unhandled part of a monitored page */
552	}
553	else
554	{
555	/* Check by physical address. */
556	unsigned iPage;
557	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + (pvFault & PAGE_OFFSET_MASK),
558	&pCur, &iPage);
559	Assert(RT_SUCCESS(rc) \|\| !pCur);
560	if ( pCur
561	&& ( uErr & X86_TRAP_PF_RW
562	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
563	{
564	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
565	# ifdef IN_RC
566	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
567	Assert(off < pCur->cb);
568	STAM_PROFILE_START(&pCur->Stat, h);
569	pgmUnlock(pVM);
570	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
571	pgmLock(pVM);
572	STAM_PROFILE_STOP(&pCur->Stat, h);
573	# else
574	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
575	# endif
576	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
577	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
578	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
579	return rc;
580	}
581	}
582	}
583	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
584
585	/*
586	* There is a handled area of the page, but this fault doesn't belong to it.
587	* We must emulate the instruction.
588	*
589	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
590	* we first check if this was a page-not-present fault for a page with only
591	* write access handlers. Restart the instruction if it wasn't a write access.
592	*/
593	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
594
595	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
596	&& !(uErr & X86_TRAP_PF_P))
597	{
598	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
599	if ( RT_FAILURE(rc)
600	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
601	\|\| !(uErr & X86_TRAP_PF_RW))
602	{
603	AssertRC(rc);
604	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
605	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
606	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
607	return rc;
608	}
609	}
610
611	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
612	* It's writing to an unhandled part of the LDT page several million times.
613	*/
614	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
615	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
616	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
617	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
618	return rc;
619	} /* if any kind of handler */
620
621	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
622	if (uErr & X86_TRAP_PF_P)
623	{
624	/*
625	* The page isn't marked, but it might still be monitored by a virtual page access handler.
626	* (ASSUMES no temporary disabling of virtual handlers.)
627	*/
628	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
629	* we should correct both the shadow page table and physical memory flags, and not only check for
630	* accesses within the handler region but for access to pages with virtual handlers. */
631	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
632	if (pCur)
633	{
634	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
635	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
636	\|\| !(uErr & X86_TRAP_PF_P)
637	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
638	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
639
640	if ( pvFault - pCur->Core.Key < pCur->cb
641	&& ( uErr & X86_TRAP_PF_RW
642	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
643	{
644	# ifdef IN_RC
645	STAM_PROFILE_START(&pCur->Stat, h);
646	pgmUnlock(pVM);
647	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
648	pgmLock(pVM);
649	STAM_PROFILE_STOP(&pCur->Stat, h);
650	# else
651	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
652	# endif
653	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
654	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
655	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
656	return rc;
657	}
658	}
659	}
660	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
661	}
662	else
663	{
664	/*
665	* When the guest accesses invalid physical memory (e.g. probing
666	* of RAM or accessing a remapped MMIO range), then we'll fall
667	* back to the recompiler to emulate the instruction.
668	*/
669	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
670	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
671	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
672	return VINF_EM_RAW_EMULATE_INSTR;
673	}
674
675	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
676
677	# ifdef PGM_OUT_OF_SYNC_IN_GC /** @todo remove this bugger. */
678	/*
679	* We are here only if page is present in Guest page tables and
680	* trap is not handled by our handlers.
681	*
682	* Check it for page out-of-sync situation.
683	*/
684	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
685
686	if (!(uErr & X86_TRAP_PF_P))
687	{
688	/*
689	* Page is not present in our page tables.
690	* Try to sync it!
691	* BTW, fPageShw is invalid in this branch!
692	*/
693	if (uErr & X86_TRAP_PF_US)
694	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
695	else /* supervisor */
696	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
697
698	# if defined(LOG_ENABLED) && !defined(IN_RING0)
699	RTGCPHYS GCPhys2;
700	uint64_t fPageGst2;
701	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
702	Log(("Page out of sync: %RGv eip=%08x PdeSrc.n.u1User=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
703	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
704	# endif /* LOG_ENABLED */
705
706	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
707	if (CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
708	{
709	uint64_t fPageGst;
710	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
711	if ( RT_SUCCESS(rc)
712	&& !(fPageGst & X86_PTE_US))
713	{
714	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
715	if ( pvFault == (RTGCPTR)pRegFrame->eip
716	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
717	# ifdef CSAM_DETECT_NEW_CODE_PAGES
718	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
719	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
720	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
721	)
722	{
723	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
724	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
725	if (rc != VINF_SUCCESS)
726	{
727	/*
728	* CSAM needs to perform a job in ring 3.
729	*
730	* Sync the page before going to the host context; otherwise we'll end up in a loop if
731	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
732	*/
733	LogFlow(("CSAM ring 3 job\n"));
734	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
735	AssertRC(rc2);
736
737	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
738	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
739	return rc;
740	}
741	}
742	# ifdef CSAM_DETECT_NEW_CODE_PAGES
743	else if ( uErr == X86_TRAP_PF_RW
744	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
745	&& pRegFrame->ecx < 0x10000)
746	{
747	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
748	* to detect loading of new code pages.
749	*/
750
751	/*
752	* Decode the instruction.
753	*/
754	RTGCPTR PC;
755	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
756	if (rc == VINF_SUCCESS)
757	{
758	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
759	uint32_t cbOp;
760	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
761
762	/* For now we'll restrict this to rep movsw/d instructions */
763	if ( rc == VINF_SUCCESS
764	&& pDis->pCurInstr->opcode == OP_MOVSWD
765	&& (pDis->prefix & PREFIX_REP))
766	{
767	CSAMMarkPossibleCodePage(pVM, pvFault);
768	}
769	}
770	}
771	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
772
773	/*
774	* Mark this page as safe.
775	*/
776	/** @todo not correct for pages that contain both code and data!! */
777	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
778	CSAMMarkPage(pVM, pvFault, true);
779	}
780	}
781	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
782	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, PGM_SYNC_NR_PAGES, uErr);
783	if (RT_SUCCESS(rc))
784	{
785	/* The page was successfully synced, return to the guest. */
786	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
787	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
788	return VINF_SUCCESS;
789	}
790	}
791	else /* uErr & X86_TRAP_PF_P: */
792	{
793	/*
794	* Write protected pages are make writable when the guest makes the first
795	* write to it. This happens for pages that are shared, write monitored
796	* and not yet allocated.
797	*
798	* Also, a side effect of not flushing global PDEs are out of sync pages due
799	* to physical monitored regions, that are no longer valid.
800	* Assume for now it only applies to the read/write flag.
801	*/
802	if (RT_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
803	{
804	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
805	{
806	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n",
807	GCPhys, pPage, pvFault, uErr));
808	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
809	if (rc != VINF_SUCCESS)
810	{
811	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
812	return rc;
813	}
814	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
815	return VINF_EM_NO_MEMORY;
816	}
817
818	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
819	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
820	if ( CPUMGetGuestCPL(pVCpu, pRegFrame) == 0
821	&& ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG))
822	{
823	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
824	uint64_t fPageGst;
825	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
826	if ( RT_SUCCESS(rc)
827	&& !(fPageGst & X86_PTE_RW))
828	{
829	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
830	if (RT_SUCCESS(rc))
831	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
832	else
833	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
834	return rc;
835	}
836	AssertMsg(RT_SUCCESS(rc), ("Unexpected r/w page %RGv flag=%x rc=%Rrc\n", pvFault, (uint32_t)fPageGst, rc));
837	}
838	# endif
839	/// @todo count the above case; else
840	if (uErr & X86_TRAP_PF_US)
841	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
842	else /* supervisor */
843	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
844
845	/*
846	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
847	* page is not present, which is not true in this case.
848	*/
849	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, pvFault, 1, uErr);
850	if (RT_SUCCESS(rc))
851	{
852	/*
853	* Page was successfully synced, return to guest.
854	* First invalidate the page as it might be in the TLB.
855	*/
856	# if PGM_SHW_TYPE == PGM_TYPE_EPT
857	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
858	# else
859	PGM_INVL_PG(pVCpu, pvFault);
860	# endif
861	# ifdef VBOX_STRICT
862	RTGCPHYS GCPhys2;
863	uint64_t fPageGst;
864	if (!HWACCMIsNestedPagingActive(pVM))
865	{
866	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
867	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%d fPageGst=%RX64\n"));
868	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
869	}
870	uint64_t fPageShw;
871	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
872	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
873	# endif /* VBOX_STRICT */
874	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
875	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
876	return VINF_SUCCESS;
877	}
878	}
879
880	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
881	# ifdef VBOX_STRICT
882	/*
883	* Check for VMM page flags vs. Guest page flags consistency.
884	* Currently only for debug purposes.
885	*/
886	if (RT_SUCCESS(rc))
887	{
888	/* Get guest page flags. */
889	uint64_t fPageGst;
890	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
891	if (RT_SUCCESS(rc))
892	{
893	uint64_t fPageShw;
894	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
895
896	/*
897	* Compare page flags.
898	* Note: we have AVL, A, D bits desynched.
899	*/
900	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
901	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
902	}
903	else
904	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
905	}
906	else
907	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
908	# endif /* VBOX_STRICT */
909	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
910	}
911	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
912	# endif /* PGM_OUT_OF_SYNC_IN_GC */
913	}
914	else /* GCPhys == NIL_RTGCPHYS */
915	{
916	/*
917	* Page not present in Guest OS or invalid page table address.
918	* This is potential virtual page access handler food.
919	*
920	* For the present we'll say that our access handlers don't
921	* work for this case - we've already discarded the page table
922	* not present case which is identical to this.
923	*
924	* When we perchance find we need this, we will probably have AVL
925	* trees (offset based) to operate on and we can measure their speed
926	* agains mapping a page table and probably rearrange this handling
927	* a bit. (Like, searching virtual ranges before checking the
928	* physical address.)
929	*/
930	}
931	}
932
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
934	/*
935	* Conclusion, this is a guest trap.
936	*/
937	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
938	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
939	return VINF_EM_RAW_GUEST_TRAP;
940	# else
941	/* present, but not a monitored page; perhaps the guest is probing physical memory */
942	return VINF_EM_RAW_EMULATE_INSTR;
943	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
944
945
946	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
947
948	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
949	return VERR_INTERNAL_ERROR;
950	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
951	}
952	#endif /* !IN_RING3 */
953
954
955	/**
956	* Emulation of the invlpg instruction.
957	*
958	*
959	* @returns VBox status code.
960	*
961	* @param pVCpu The VMCPU handle.
962	* @param GCPtrPage Page to invalidate.
963	*
964	* @remark ASSUMES that the guest is updating before invalidating. This order
965	* isn't required by the CPU, so this is speculative and could cause
966	* trouble.
967	* @remark No TLB shootdown is done on any other VCPU as we assume that
968	* invlpg emulation is the only reason for calling this function.
969	* (The guest has to shoot down TLB entries on other CPUs itself)
970	* Currently true, but keep in mind!
971	*
972	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
973	*/
974	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
975	{
976	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
977	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
978	&& PGM_SHW_TYPE != PGM_TYPE_EPT
979	int rc;
980	PVM pVM = pVCpu->CTX_SUFF(pVM);
981	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
982
983	Assert(PGMIsLockOwner(pVM));
984
985	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
986
987	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
988	if (pPool->cDirtyPages)
989	pgmPoolResetDirtyPages(pVM);
990	# endif
991
992	/*
993	* Get the shadow PD entry and skip out if this PD isn't present.
994	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
995	*/
996	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
997	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
998	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
999
1000	/* Fetch the pgm pool shadow descriptor. */
1001	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1002	Assert(pShwPde);
1003
1004	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1005	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1006	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
1007
1008	/* If the shadow PDPE isn't present, then skip the invalidate. */
1009	if (!pPdptDst->a[iPdpt].n.u1Present)
1010	{
1011	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1012	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1013	return VINF_SUCCESS;
1014	}
1015
1016	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1017	PPGMPOOLPAGE pShwPde = NULL;
1018	PX86PDPAE pPDDst;
1019
1020	/* Fetch the pgm pool shadow descriptor. */
1021	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1022	AssertRCSuccessReturn(rc, rc);
1023	Assert(pShwPde);
1024
1025	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1026	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1027
1028	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1029	/* PML4 */
1030	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1031	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1032	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1033	PX86PDPAE pPDDst;
1034	PX86PDPT pPdptDst;
1035	PX86PML4E pPml4eDst;
1036	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1037	if (rc != VINF_SUCCESS)
1038	{
1039	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1040	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1041	return VINF_SUCCESS;
1042	}
1043	Assert(pPDDst);
1044
1045	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1046	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1047
1048	if (!pPdpeDst->n.u1Present)
1049	{
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1051	return VINF_SUCCESS;
1052	}
1053
1054	/* Fetch the pgm pool shadow descriptor. */
1055	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1056	Assert(pShwPde);
1057
1058	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1059
1060	const SHWPDE PdeDst = *pPdeDst;
1061	if (!PdeDst.n.u1Present)
1062	{
1063	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1064	return VINF_SUCCESS;
1065	}
1066
1067	# if defined(IN_RC)
1068	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1069	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1070	# endif
1071
1072	/*
1073	* Get the guest PD entry and calc big page.
1074	*/
1075	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1076	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
1077	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1078	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1079	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1080	unsigned iPDSrc = 0;
1081	# if PGM_GST_TYPE == PGM_TYPE_PAE
1082	X86PDPE PdpeSrc;
1083	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
1084	# else /* AMD64 */
1085	PX86PML4E pPml4eSrc;
1086	X86PDPE PdpeSrc;
1087	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
1088	# endif
1089	GSTPDE PdeSrc;
1090
1091	if (pPDSrc)
1092	PdeSrc = pPDSrc->a[iPDSrc];
1093	else
1094	PdeSrc.u = 0;
1095	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1096
1097	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1098	const bool fIsBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu);
1099	# else
1100	const bool fIsBigPage = PdeSrc.b.u1Size;
1101	# endif
1102
1103	# ifdef IN_RING3
1104	/*
1105	* If a CR3 Sync is pending we may ignore the invalidate page operation
1106	* depending on the kind of sync and if it's a global page or not.
1107	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1108	*/
1109	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1110	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1111	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1112	&& fIsBigPage
1113	&& PdeSrc.b.u1Global
1114	)
1115	)
1116	# else
1117	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1118	# endif
1119	{
1120	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1121	return VINF_SUCCESS;
1122	}
1123	# endif /* IN_RING3 */
1124
1125	/*
1126	* Deal with the Guest PDE.
1127	*/
1128	rc = VINF_SUCCESS;
1129	if (PdeSrc.n.u1Present)
1130	{
1131	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1132	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1133	# ifndef PGM_WITHOUT_MAPPING
1134	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1135	{
1136	/*
1137	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1138	*/
1139	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1140	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1141	pgmLock(pVM);
1142	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1143	pgmUnlock(pVM);
1144	}
1145	else
1146	# endif /* !PGM_WITHOUT_MAPPING */
1147	if (!fIsBigPage)
1148	{
1149	/*
1150	* 4KB - page.
1151	*/
1152	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1153	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1154
1155	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1156	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1157	if (pShwPage->cModifications)
1158	pShwPage->cModifications = 1;
1159	# endif
1160
1161	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1162	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1163	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1164	# endif
1165	if (pShwPage->GCPhys == GCPhys)
1166	{
1167	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1168	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1169	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1170	if (pPT->a[iPTEDst].n.u1Present)
1171	{
1172	/* This is very unlikely with caching/monitoring enabled. */
1173	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
1174	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1175	}
1176	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1177	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1178	if (RT_SUCCESS(rc))
1179	rc = VINF_SUCCESS;
1180	# endif
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1182	PGM_INVL_PG(pVCpu, GCPtrPage);
1183	}
1184	else
1185	{
1186	/*
1187	* The page table address changed.
1188	*/
1189	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1190	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1191	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1192	ASMAtomicWriteSize(pPdeDst, 0);
1193	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1194	PGM_INVL_VCPU_TLBS(pVCpu);
1195	}
1196	}
1197	else
1198	{
1199	/*
1200	* 2/4MB - page.
1201	*/
1202	/* Before freeing the page, check if anything really changed. */
1203	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1204	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1205	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1206	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1207	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1208	# endif
1209	if ( pShwPage->GCPhys == GCPhys
1210	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1211	{
1212	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1213	/** @todo PAT */
1214	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1215	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1216	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1217	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1218	{
1219	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1220	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1221	# if defined(IN_RC)
1222	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1223	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1224	# endif
1225	return VINF_SUCCESS;
1226	}
1227	}
1228
1229	/*
1230	* Ok, the page table is present and it's been changed in the guest.
1231	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1232	* We could do this for some flushes in GC too, but we need an algorithm for
1233	* deciding which 4MB pages containing code likely to be executed very soon.
1234	*/
1235	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1236	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1237	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1238	ASMAtomicWriteSize(pPdeDst, 0);
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1240	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1241	}
1242	}
1243	else
1244	{
1245	/*
1246	* Page directory is not present, mark shadow PDE not present.
1247	*/
1248	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1249	{
1250	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1251	ASMAtomicWriteSize(pPdeDst, 0);
1252	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1253	PGM_INVL_PG(pVCpu, GCPtrPage);
1254	}
1255	else
1256	{
1257	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1258	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1259	}
1260	}
1261	# if defined(IN_RC)
1262	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1263	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1264	# endif
1265	return rc;
1266
1267	#else /* guest real and protected mode */
1268	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1269	return VINF_SUCCESS;
1270	#endif
1271	}
1272
1273
1274	/**
1275	* Update the tracking of shadowed pages.
1276	*
1277	* @param pVCpu The VMCPU handle.
1278	* @param pShwPage The shadow page.
1279	* @param HCPhys The physical page we is being dereferenced.
1280	*/
1281	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1282	{
1283	PVM pVM = pVCpu->CTX_SUFF(pVM);
1284
1285	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1286	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1287
1288	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1289	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1290	* 2. write protect all shadowed pages. I.e. implement caching.
1291	*/
1292	/*
1293	* Find the guest address.
1294	*/
1295	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1296	pRam;
1297	pRam = pRam->CTX_SUFF(pNext))
1298	{
1299	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1300	while (iPage-- > 0)
1301	{
1302	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1303	{
1304	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1305	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1306	pShwPage->cPresent--;
1307	pPool->cPresent--;
1308	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1309	return;
1310	}
1311	}
1312	}
1313
1314	for (;;)
1315	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1316	}
1317
1318
1319	/**
1320	* Update the tracking of shadowed pages.
1321	*
1322	* @param pVCpu The VMCPU handle.
1323	* @param pShwPage The shadow page.
1324	* @param u16 The top 16-bit of the pPage->HCPhys.
1325	* @param pPage Pointer to the guest page. this will be modified.
1326	* @param iPTDst The index into the shadow table.
1327	*/
1328	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1329	{
1330	PVM pVM = pVCpu->CTX_SUFF(pVM);
1331	/*
1332	* Just deal with the simple first time here.
1333	*/
1334	if (!u16)
1335	{
1336	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1337	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1338	}
1339	else
1340	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1341
1342	/* write back */
1343	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1344	PGM_PAGE_SET_TRACKING(pPage, u16);
1345
1346	/* update statistics. */
1347	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1348	pShwPage->cPresent++;
1349	if (pShwPage->iFirstPresent > iPTDst)
1350	pShwPage->iFirstPresent = iPTDst;
1351	}
1352
1353
1354	/**
1355	* Creates a 4K shadow page for a guest page.
1356	*
1357	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1358	* physical address. The PdeSrc argument only the flags are used. No page structured
1359	* will be mapped in this function.
1360	*
1361	* @param pVCpu The VMCPU handle.
1362	* @param pPteDst Destination page table entry.
1363	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1364	* Can safely assume that only the flags are being used.
1365	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1366	* @param pShwPage Pointer to the shadow page.
1367	* @param iPTDst The index into the shadow table.
1368	*
1369	* @remark Not used for 2/4MB pages!
1370	*/
1371	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1372	{
1373	if (PteSrc.n.u1Present)
1374	{
1375	PVM pVM = pVCpu->CTX_SUFF(pVM);
1376
1377	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1378	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1379	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1380	if (pShwPage->fDirty)
1381	{
1382	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1383	PX86PTPAE pGstPT;
1384
1385	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1386	pGstPT->a[iPTDst].u = PteSrc.u;
1387	}
1388	# endif
1389	/*
1390	* Find the ram range.
1391	*/
1392	PPGMPAGE pPage;
1393	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1394	if (RT_SUCCESS(rc))
1395	{
1396	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1397	/* Try make the page writable if necessary. */
1398	if ( PteSrc.n.u1Write
1399	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1400	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1401	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1402	# endif
1403	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1404	{
1405	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1406	AssertRC(rc);
1407	}
1408	#endif
1409
1410	/** @todo investiage PWT, PCD and PAT. */
1411	/*
1412	* Make page table entry.
1413	*/
1414	SHWPTE PteDst;
1415	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1416	{
1417	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1418	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1419	{
1420	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1421	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1422	PteDst.n.u1Present = 1;
1423	PteDst.n.u1Execute = 1;
1424	PteDst.n.u1IgnorePAT = 1;
1425	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1426	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1427	#else
1428	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1429	\| PGM_PAGE_GET_HCPHYS(pPage);
1430	#endif
1431	}
1432	else
1433	{
1434	LogFlow(("SyncPageWorker: monitored page (%RHp) -> mark not present\n", PGM_PAGE_GET_HCPHYS(pPage)));
1435	PteDst.u = 0;
1436	}
1437	/** @todo count these two kinds. */
1438	}
1439	else
1440	{
1441	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1442	/*
1443	* If the page or page directory entry is not marked accessed,
1444	* we mark the page not present.
1445	*/
1446	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1447	{
1448	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1449	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1450	PteDst.u = 0;
1451	}
1452	else
1453	/*
1454	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1455	* when the page is modified.
1456	*/
1457	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1458	{
1459	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1460	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1461	\| PGM_PAGE_GET_HCPHYS(pPage)
1462	\| PGM_PTFLAGS_TRACK_DIRTY;
1463	}
1464	else
1465	#endif
1466	{
1467	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1468	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1469	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1470	PteDst.n.u1Present = 1;
1471	PteDst.n.u1Write = 1;
1472	PteDst.n.u1Execute = 1;
1473	PteDst.n.u1IgnorePAT = 1;
1474	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1475	/* PteDst.n.u1Size = 0 */
1476	#else
1477	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1478	\| PGM_PAGE_GET_HCPHYS(pPage);
1479	#endif
1480	}
1481	}
1482
1483	/*
1484	* Make sure only allocated pages are mapped writable.
1485	*/
1486	if ( PteDst.n.u1Write
1487	&& PteDst.n.u1Present
1488	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1489	{
1490	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. */
1491	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1492	}
1493
1494	/*
1495	* Keep user track up to date.
1496	*/
1497	if (PteDst.n.u1Present)
1498	{
1499	if (!pPteDst->n.u1Present)
1500	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1501	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1502	{
1503	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1504	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1505	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1506	}
1507	}
1508	else if (pPteDst->n.u1Present)
1509	{
1510	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1511	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1512	}
1513
1514	/*
1515	* Update statistics and commit the entry.
1516	*/
1517	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1518	if (!PteSrc.n.u1Global)
1519	pShwPage->fSeenNonGlobal = true;
1520	#endif
1521	ASMAtomicWriteSize(pPteDst, PteDst.u);
1522	}
1523	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1524	/** @todo count these. */
1525	}
1526	else
1527	{
1528	/*
1529	* Page not-present.
1530	*/
1531	Log2(("SyncPageWorker: page not present in Pte\n"));
1532	/* Keep user track up to date. */
1533	if (pPteDst->n.u1Present)
1534	{
1535	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1536	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1537	}
1538	ASMAtomicWriteSize(pPteDst, 0);
1539	/** @todo count these. */
1540	}
1541	}
1542
1543
1544	/**
1545	* Syncs a guest OS page.
1546	*
1547	* There are no conflicts at this point, neither is there any need for
1548	* page table allocations.
1549	*
1550	* @returns VBox status code.
1551	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1552	* @param pVCpu The VMCPU handle.
1553	* @param PdeSrc Page directory entry of the guest.
1554	* @param GCPtrPage Guest context page address.
1555	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1556	* @param uErr Fault error (X86_TRAP_PF_*).
1557	*/
1558	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1559	{
1560	PVM pVM = pVCpu->CTX_SUFF(pVM);
1561	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1562	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1563
1564	Assert(PGMIsLockOwner(pVM));
1565
1566	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1567	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1568	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1569	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1570	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1571
1572	/*
1573	* Assert preconditions.
1574	*/
1575	Assert(PdeSrc.n.u1Present);
1576	Assert(cPages);
1577	# if 0 /* rarely useful; leave for debugging. */
1578	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1579	# endif
1580
1581	/*
1582	* Get the shadow PDE, find the shadow page table in the pool.
1583	*/
1584	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1585	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1586	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1587
1588	/* Fetch the pgm pool shadow descriptor. */
1589	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1590	Assert(pShwPde);
1591
1592	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1593	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1594	PPGMPOOLPAGE pShwPde = NULL;
1595	PX86PDPAE pPDDst;
1596
1597	/* Fetch the pgm pool shadow descriptor. */
1598	int rc2 = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1599	AssertRCSuccessReturn(rc2, rc2);
1600	Assert(pShwPde);
1601
1602	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1603	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1604
1605	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1606	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1607	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1608	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1609	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1610
1611	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1612	AssertRCSuccessReturn(rc2, rc2);
1613	Assert(pPDDst && pPdptDst);
1614	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1615	# endif
1616	SHWPDE PdeDst = *pPdeDst;
1617
1618	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1619	if (!PdeDst.n.u1Present)
1620	{
1621	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1622	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1623	return VINF_SUCCESS; /* force the instruction to be executed again. */
1624	}
1625
1626	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1627	Assert(pShwPage);
1628
1629	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1630	/* Fetch the pgm pool shadow descriptor. */
1631	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1632	Assert(pShwPde);
1633	# endif
1634
1635	# if defined(IN_RC)
1636	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1637	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1638	# endif
1639
1640	/*
1641	* Check that the page is present and that the shadow PDE isn't out of sync.
1642	*/
1643	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1644	const bool fBigPage = PdeSrc.b.u1Size && CPUMIsGuestPageSizeExtEnabled(pVCpu);
1645	# else
1646	const bool fBigPage = PdeSrc.b.u1Size;
1647	# endif
1648	RTGCPHYS GCPhys;
1649	if (!fBigPage)
1650	{
1651	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1652	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1653	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1654	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1655	# endif
1656	}
1657	else
1658	{
1659	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
1660	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1661	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1662	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1663	# endif
1664	}
1665	if ( pShwPage->GCPhys == GCPhys
1666	&& PdeSrc.n.u1Present
1667	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1668	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1669	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1670	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !CPUMIsGuestNXEnabled(pVCpu))
1671	# endif
1672	)
1673	{
1674	/*
1675	* Check that the PDE is marked accessed already.
1676	* Since we set the accessed bit before getting here on a #PF, this
1677	* check is only meant for dealing with non-#PF'ing paths.
1678	*/
1679	if (PdeSrc.n.u1Accessed)
1680	{
1681	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1682	if (!fBigPage)
1683	{
1684	/*
1685	* 4KB Page - Map the guest page table.
1686	*/
1687	PGSTPT pPTSrc;
1688	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1689	if (RT_SUCCESS(rc))
1690	{
1691	# ifdef PGM_SYNC_N_PAGES
1692	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1693	if ( cPages > 1
1694	&& !(uErr & X86_TRAP_PF_P)
1695	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1696	{
1697	/*
1698	* This code path is currently only taken when the caller is PGMTrap0eHandler
1699	* for non-present pages!
1700	*
1701	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1702	* deal with locality.
1703	*/
1704	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1705	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1706	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1707	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1708	# else
1709	const unsigned offPTSrc = 0;
1710	# endif
1711	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1712	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1713	iPTDst = 0;
1714	else
1715	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1716	for (; iPTDst < iPTDstEnd; iPTDst++)
1717	{
1718	if (!pPTDst->a[iPTDst].n.u1Present)
1719	{
1720	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1721	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1722	NOREF(GCPtrCurPage);
1723	#ifndef IN_RING0
1724	/*
1725	* Assuming kernel code will be marked as supervisor - and not as user level
1726	* and executed using a conforming code selector - And marked as readonly.
1727	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1728	*/
1729	PPGMPAGE pPage;
1730	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1731	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1732	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1733	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1734	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1735	)
1736	#endif /* else: CSAM not active */
1737	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1738	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1739	GCPtrCurPage, PteSrc.n.u1Present,
1740	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1741	PteSrc.n.u1User & PdeSrc.n.u1User,
1742	(uint64_t)PteSrc.u,
1743	(uint64_t)pPTDst->a[iPTDst].u,
1744	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1745	}
1746	}
1747	}
1748	else
1749	# endif /* PGM_SYNC_N_PAGES */
1750	{
1751	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1752	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1753	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1754	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1755	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1756	GCPtrPage, PteSrc.n.u1Present,
1757	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1758	PteSrc.n.u1User & PdeSrc.n.u1User,
1759	(uint64_t)PteSrc.u,
1760	(uint64_t)pPTDst->a[iPTDst].u,
1761	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1762	}
1763	}
1764	else /* MMIO or invalid page: emulated in #PF handler. */
1765	{
1766	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1767	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1768	}
1769	}
1770	else
1771	{
1772	/*
1773	* 4/2MB page - lazy syncing shadow 4K pages.
1774	* (There are many causes of getting here, it's no longer only CSAM.)
1775	*/
1776	/* Calculate the GC physical address of this 4KB shadow page. */
1777	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1778	/* Find ram range. */
1779	PPGMPAGE pPage;
1780	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1781	if (RT_SUCCESS(rc))
1782	{
1783	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1784	/* Try make the page writable if necessary. */
1785	if ( PdeSrc.n.u1Write
1786	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1787	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1788	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1789	# endif
1790	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
1791	{
1792	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
1793	AssertRC(rc);
1794	}
1795	# endif
1796
1797	/*
1798	* Make shadow PTE entry.
1799	*/
1800	SHWPTE PteDst;
1801	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1802	\| PGM_PAGE_GET_HCPHYS(pPage);
1803	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1804	{
1805	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1806	PteDst.n.u1Write = 0;
1807	else
1808	PteDst.u = 0;
1809	}
1810	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1811	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1812	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1813
1814	/* Make sure only allocated pages are mapped writable. */
1815	if ( PteDst.n.u1Write
1816	&& PteDst.n.u1Present
1817	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1818	{
1819	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
1820	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
1821	}
1822
1823	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
1824
1825	/*
1826	* If the page is not flagged as dirty and is writable, then make it read-only
1827	* at PD level, so we can set the dirty bit when the page is modified.
1828	*
1829	* ASSUMES that page access handlers are implemented on page table entry level.
1830	* Thus we will first catch the dirty access and set PDE.D and restart. If
1831	* there is an access handler, we'll trap again and let it work on the problem.
1832	*/
1833	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1834	* As for invlpg, it simply frees the whole shadow PT.
1835	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1836	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1837	{
1838	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
1839	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1840	PdeDst.n.u1Write = 0;
1841	}
1842	else
1843	{
1844	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1845	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1846	}
1847	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
1848	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
1849	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1850	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1851	}
1852	else
1853	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
1854	}
1855	# if defined(IN_RC)
1856	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1857	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1858	# endif
1859	return VINF_SUCCESS;
1860	}
1861	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
1862	}
1863	else
1864	{
1865	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
1866	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
1867	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
1868	}
1869
1870	/*
1871	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1872	* Yea, I'm lazy.
1873	*/
1874	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
1875	ASMAtomicWriteSize(pPdeDst, 0);
1876
1877	# if defined(IN_RC)
1878	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1879	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1880	# endif
1881	PGM_INVL_VCPU_TLBS(pVCpu);
1882	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1883
1884	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1885	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1886	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
1887	&& !defined(IN_RC)
1888
1889	# ifdef PGM_SYNC_N_PAGES
1890	/*
1891	* Get the shadow PDE, find the shadow page table in the pool.
1892	*/
1893	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1894	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
1895
1896	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1897	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
1898
1899	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1900	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1901	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
1902	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1903	X86PDEPAE PdeDst;
1904	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1905
1906	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1907	AssertRCSuccessReturn(rc, rc);
1908	Assert(pPDDst && pPdptDst);
1909	PdeDst = pPDDst->a[iPDDst];
1910	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
1911	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
1912	PEPTPD pPDDst;
1913	EPTPDE PdeDst;
1914
1915	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
1916	if (rc != VINF_SUCCESS)
1917	{
1918	AssertRC(rc);
1919	return rc;
1920	}
1921	Assert(pPDDst);
1922	PdeDst = pPDDst->a[iPDDst];
1923	# endif
1924	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1925	if (!PdeDst.n.u1Present)
1926	{
1927	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
1928	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", GCPtrPage));
1929	return VINF_SUCCESS; /* force the instruction to be executed again. */
1930	}
1931
1932	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1933	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1934
1935	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
1936	if (PdeDst.n.u1Size)
1937	{
1938	Assert(HWACCMIsNestedPagingActive(pVM));
1939	Log(("CPU%d: SyncPage: Pde (big) at %RGv changed behind our back!\n", GCPtrPage));
1940	return VINF_SUCCESS;
1941	}
1942
1943	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1944	if ( cPages > 1
1945	&& !(uErr & X86_TRAP_PF_P)
1946	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1947	{
1948	/*
1949	* This code path is currently only taken when the caller is PGMTrap0eHandler
1950	* for non-present pages!
1951	*
1952	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1953	* deal with locality.
1954	*/
1955	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1956	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1957	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1958	iPTDst = 0;
1959	else
1960	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1961	for (; iPTDst < iPTDstEnd; iPTDst++)
1962	{
1963	if (!pPTDst->a[iPTDst].n.u1Present)
1964	{
1965	GSTPTE PteSrc;
1966
1967	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
1968
1969	/* Fake the page table entry */
1970	PteSrc.u = GCPtrCurPage;
1971	PteSrc.n.u1Present = 1;
1972	PteSrc.n.u1Dirty = 1;
1973	PteSrc.n.u1Accessed = 1;
1974	PteSrc.n.u1Write = 1;
1975	PteSrc.n.u1User = 1;
1976
1977	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1978
1979	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1980	GCPtrCurPage, PteSrc.n.u1Present,
1981	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1982	PteSrc.n.u1User & PdeSrc.n.u1User,
1983	(uint64_t)PteSrc.u,
1984	(uint64_t)pPTDst->a[iPTDst].u,
1985	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1986
1987	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
1988	break;
1989	}
1990	else
1991	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
1992	}
1993	}
1994	else
1995	# endif /* PGM_SYNC_N_PAGES */
1996	{
1997	GSTPTE PteSrc;
1998	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1999	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2000
2001	/* Fake the page table entry */
2002	PteSrc.u = GCPtrCurPage;
2003	PteSrc.n.u1Present = 1;
2004	PteSrc.n.u1Dirty = 1;
2005	PteSrc.n.u1Accessed = 1;
2006	PteSrc.n.u1Write = 1;
2007	PteSrc.n.u1User = 1;
2008	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2009
2010	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2011	GCPtrPage, PteSrc.n.u1Present,
2012	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2013	PteSrc.n.u1User & PdeSrc.n.u1User,
2014	(uint64_t)PteSrc.u,
2015	(uint64_t)pPTDst->a[iPTDst].u,
2016	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2017	}
2018	return VINF_SUCCESS;
2019
2020	#else
2021	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2022	return VERR_INTERNAL_ERROR;
2023	#endif
2024	}
2025
2026
2027	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2028	/**
2029	* Investigate page fault and handle write protection page faults caused by
2030	* dirty bit tracking.
2031	*
2032	* @returns VBox status code.
2033	* @param pVCpu The VMCPU handle.
2034	* @param uErr Page fault error code.
2035	* @param pPdeSrc Guest page directory entry.
2036	* @param GCPtrPage Guest context page address.
2037	*/
2038	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2039	{
2040	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2041	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2042	bool fMaybeWriteProtFault = fWriteFault && (fUserLevelFault \|\| CPUMIsGuestR0WriteProtEnabled(pVCpu));
2043	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2044	bool fMaybeNXEFault = (uErr & X86_TRAP_PF_ID) && CPUMIsGuestNXEnabled(pVCpu);
2045	# endif
2046	unsigned uPageFaultLevel;
2047	int rc;
2048	PVM pVM = pVCpu->CTX_SUFF(pVM);
2049
2050	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2051
2052	# if PGM_GST_TYPE == PGM_TYPE_PAE \
2053	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2054
2055	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2056	PX86PML4E pPml4eSrc;
2057	PX86PDPE pPdpeSrc;
2058
2059	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc);
2060	Assert(pPml4eSrc);
2061
2062	/*
2063	* Real page fault? (PML4E level)
2064	*/
2065	if ( (uErr & X86_TRAP_PF_RSVD)
2066	\|\| !pPml4eSrc->n.u1Present
2067	\|\| (fMaybeWriteProtFault && !pPml4eSrc->n.u1Write)
2068	\|\| (fMaybeNXEFault && pPml4eSrc->n.u1NoExecute)
2069	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
2070	)
2071	{
2072	uPageFaultLevel = 0;
2073	goto l_UpperLevelPageFault;
2074	}
2075	Assert(pPdpeSrc);
2076
2077	# else /* PAE */
2078	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(&pVCpu->pgm.s, GCPtrPage);
2079	# endif /* PAE */
2080
2081	/*
2082	* Real page fault? (PDPE level)
2083	*/
2084	if ( (uErr & X86_TRAP_PF_RSVD)
2085	\|\| !pPdpeSrc->n.u1Present
2086	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
2087	\|\| (fMaybeWriteProtFault && !pPdpeSrc->lm.u1Write)
2088	\|\| (fMaybeNXEFault && pPdpeSrc->lm.u1NoExecute)
2089	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User)
2090	# endif
2091	)
2092	{
2093	uPageFaultLevel = 1;
2094	goto l_UpperLevelPageFault;
2095	}
2096	# endif
2097
2098	/*
2099	* Real page fault? (PDE level)
2100	*/
2101	if ( (uErr & X86_TRAP_PF_RSVD)
2102	\|\| !pPdeSrc->n.u1Present
2103	\|\| (fMaybeWriteProtFault && !pPdeSrc->n.u1Write)
2104	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2105	\|\| (fMaybeNXEFault && pPdeSrc->n.u1NoExecute)
2106	# endif
2107	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2108	{
2109	uPageFaultLevel = 2;
2110	goto l_UpperLevelPageFault;
2111	}
2112
2113	/*
2114	* First check the easy case where the page directory has been marked read-only to track
2115	* the dirty bit of an emulated BIG page
2116	*/
2117	if ( pPdeSrc->b.u1Size
2118	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2119	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
2120	# endif
2121	)
2122	{
2123	/* Mark guest page directory as accessed */
2124	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2125	pPml4eSrc->n.u1Accessed = 1;
2126	pPdpeSrc->lm.u1Accessed = 1;
2127	# endif
2128	pPdeSrc->b.u1Accessed = 1;
2129
2130	/*
2131	* Only write protection page faults are relevant here.
2132	*/
2133	if (fWriteFault)
2134	{
2135	/* Mark guest page directory as dirty (BIG page only). */
2136	pPdeSrc->b.u1Dirty = 1;
2137	}
2138	return VINF_SUCCESS;
2139	}
2140	/* else: 4KB page table */
2141
2142	/*
2143	* Map the guest page table.
2144	*/
2145	PGSTPT pPTSrc;
2146	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2147	if (RT_SUCCESS(rc))
2148	{
2149	/*
2150	* Real page fault?
2151	*/
2152	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2153	const GSTPTE PteSrc = *pPteSrc;
2154	if ( !PteSrc.n.u1Present
2155	\|\| (fMaybeWriteProtFault && !PteSrc.n.u1Write)
2156	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2157	\|\| (fMaybeNXEFault && PteSrc.n.u1NoExecute)
2158	# endif
2159	\|\| (fUserLevelFault && !PteSrc.n.u1User)
2160	)
2161	{
2162	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2163	LogFlow(("CheckPageFault: real page fault at %RGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
2164
2165	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
2166	* See the 2nd case above as well.
2167	*/
2168	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
2169	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2170
2171	return VINF_EM_RAW_GUEST_TRAP;
2172	}
2173	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2174
2175	/*
2176	* Set the accessed bits in the page directory and the page table.
2177	*/
2178	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2179	pPml4eSrc->n.u1Accessed = 1;
2180	pPdpeSrc->lm.u1Accessed = 1;
2181	# endif
2182	pPdeSrc->n.u1Accessed = 1;
2183	pPteSrc->n.u1Accessed = 1;
2184
2185	/*
2186	* Only write protection page faults are relevant here.
2187	*/
2188	if (fWriteFault)
2189	{
2190	/* Write access, so mark guest entry as dirty. */
2191	# ifdef VBOX_WITH_STATISTICS
2192	if (!pPteSrc->n.u1Dirty)
2193	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2194	else
2195	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2196	# endif
2197
2198	pPteSrc->n.u1Dirty = 1;
2199	}
2200	return VINF_SUCCESS;
2201	}
2202	AssertRC(rc);
2203	return rc;
2204
2205
2206	l_UpperLevelPageFault:
2207	/*
2208	* Pagefault detected while checking the PML4E, PDPE or PDE.
2209	* Single exit handler to get rid of duplicate code paths.
2210	*/
2211	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2212	Log(("CheckPageFault: real page fault at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2213
2214	if ( 1
2215	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2216	&& pPml4eSrc->n.u1Present
2217	# endif
2218	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2219	&& pPdpeSrc->n.u1Present
2220	# endif
2221	&& pPdeSrc->n.u1Present)
2222	{
2223	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
2224	if ( pPdeSrc->b.u1Size
2225	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2226	&& CPUMIsGuestPageSizeExtEnabled(pVCpu)
2227	# endif
2228	)
2229	{
2230	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2231	}
2232	else
2233	{
2234	/*
2235	* Map the guest page table.
2236	*/
2237	PGSTPT pPTSrc2;
2238	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc2);
2239	if (RT_SUCCESS(rc))
2240	{
2241	PGSTPTE pPteSrc = &pPTSrc2->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2242	if (pPteSrc->n.u1Present)
2243	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
2244	}
2245	AssertRC(rc);
2246	}
2247	}
2248	return VINF_EM_RAW_GUEST_TRAP;
2249	}
2250
2251	/**
2252	* Handle dirty bit tracking faults.
2253	*
2254	* @returns VBox status code.
2255	* @param pVCpu The VMCPU handle.
2256	* @param uErr Page fault error code.
2257	* @param pPdeSrc Guest page directory entry.
2258	* @param pPdeDst Shadow page directory entry.
2259	* @param GCPtrPage Guest context page address.
2260	*/
2261	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2262	{
2263	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2264	const bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu);
2265	# else
2266	const bool fBigPagesSupported = true;
2267	# endif
2268	PVM pVM = pVCpu->CTX_SUFF(pVM);
2269	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2270
2271	Assert(PGMIsLockOwner(pVM));
2272
2273	if (pPdeSrc->b.u1Size && fBigPagesSupported)
2274	{
2275	if ( pPdeDst->n.u1Present
2276	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2277	{
2278	SHWPDE PdeDst = *pPdeDst;
2279
2280	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2281	Assert(pPdeSrc->b.u1Write);
2282
2283	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2284	* fault again and take this path to only invalidate the entry.
2285	*/
2286	PdeDst.n.u1Write = 1;
2287	PdeDst.n.u1Accessed = 1;
2288	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2289	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2290	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2291	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2292	}
2293	# ifdef IN_RING0
2294	else
2295	/* Check for stale TLB entry; only applies to the SMP guest case. */
2296	if ( pVM->cCpus > 1
2297	&& pPdeDst->n.u1Write
2298	&& pPdeDst->n.u1Accessed)
2299	{
2300	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2301	if (pShwPage)
2302	{
2303	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2304	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2305	if ( pPteDst->n.u1Present
2306	&& pPteDst->n.u1Write)
2307	{
2308	/* Stale TLB entry. */
2309	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2310	PGM_INVL_PG(pVCpu, GCPtrPage);
2311	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2312	}
2313	}
2314	}
2315	# endif /* IN_RING0 */
2316	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2317	}
2318
2319	/*
2320	* Map the guest page table.
2321	*/
2322	PGSTPT pPTSrc;
2323	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2324	if (RT_SUCCESS(rc))
2325	{
2326	if (pPdeDst->n.u1Present)
2327	{
2328	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2329	const GSTPTE PteSrc = *pPteSrc;
2330	#ifndef IN_RING0
2331	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
2332	* Our individual shadow handlers will provide more information and force a fatal exit.
2333	*/
2334	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2335	{
2336	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2337	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2338	}
2339	#endif
2340	/*
2341	* Map shadow page table.
2342	*/
2343	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2344	if (pShwPage)
2345	{
2346	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2347	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2348	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2349	{
2350	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2351	{
2352	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2353	SHWPTE PteDst = *pPteDst;
2354
2355	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2356	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2357
2358	Assert(pPteSrc->n.u1Write);
2359
2360	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2361	* fault again and take this path to only invalidate the entry.
2362	*/
2363	if (RT_LIKELY(pPage))
2364	{
2365	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2366	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2367	PteDst.n.u1Write = 0;
2368	else
2369	{
2370	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2371	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2372	{
2373	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2374	AssertRC(rc);
2375	}
2376	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2377	PteDst.n.u1Write = 1;
2378	else
2379	PteDst.n.u1Write = 0;
2380	}
2381	}
2382	else
2383	PteDst.n.u1Write = 1;
2384
2385	PteDst.n.u1Dirty = 1;
2386	PteDst.n.u1Accessed = 1;
2387	PteDst.au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2388	ASMAtomicWriteSize(pPteDst, PteDst.u);
2389	PGM_INVL_PG(pVCpu, GCPtrPage);
2390	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2391	}
2392	# ifdef IN_RING0
2393	else
2394	/* Check for stale TLB entry; only applies to the SMP guest case. */
2395	if ( pVM->cCpus > 1
2396	&& pPteDst->n.u1Write == 1
2397	&& pPteDst->n.u1Accessed == 1)
2398	{
2399	/* Stale TLB entry. */
2400	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2401	PGM_INVL_PG(pVCpu, GCPtrPage);
2402	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2403	}
2404	# endif
2405	}
2406	}
2407	else
2408	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2409	}
2410	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2411	}
2412	AssertRC(rc);
2413	return rc;
2414	}
2415	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2416
2417
2418	/**
2419	* Sync a shadow page table.
2420	*
2421	* The shadow page table is not present. This includes the case where
2422	* there is a conflict with a mapping.
2423	*
2424	* @returns VBox status code.
2425	* @param pVCpu The VMCPU handle.
2426	* @param iPD Page directory index.
2427	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2428	* Assume this is a temporary mapping.
2429	* @param GCPtrPage GC Pointer of the page that caused the fault
2430	*/
2431	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2432	{
2433	PVM pVM = pVCpu->CTX_SUFF(pVM);
2434	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2435
2436	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2437	#if 0 /* rarely useful; leave for debugging. */
2438	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2439	#endif
2440	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2441
2442	Assert(PGMIsLocked(pVM));
2443
2444	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2445	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2446	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2447	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2448	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2449
2450	int rc = VINF_SUCCESS;
2451
2452	/*
2453	* Validate input a little bit.
2454	*/
2455	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2456	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2457	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2458	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2459
2460	/* Fetch the pgm pool shadow descriptor. */
2461	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2462	Assert(pShwPde);
2463
2464	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2465	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2466	PPGMPOOLPAGE pShwPde = NULL;
2467	PX86PDPAE pPDDst;
2468	PSHWPDE pPdeDst;
2469
2470	/* Fetch the pgm pool shadow descriptor. */
2471	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2472	AssertRCSuccessReturn(rc, rc);
2473	Assert(pShwPde);
2474
2475	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2476	pPdeDst = &pPDDst->a[iPDDst];
2477
2478	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2479	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2480	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2481	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2482	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2483	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2484	AssertRCSuccessReturn(rc, rc);
2485	Assert(pPDDst);
2486	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2487	# endif
2488	SHWPDE PdeDst = *pPdeDst;
2489
2490	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2491	/* Fetch the pgm pool shadow descriptor. */
2492	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2493	Assert(pShwPde);
2494	# endif
2495
2496	# ifndef PGM_WITHOUT_MAPPINGS
2497	/*
2498	* Check for conflicts.
2499	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2500	* HC: Simply resolve the conflict.
2501	*/
2502	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2503	{
2504	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2505	# ifndef IN_RING3
2506	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2507	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2508	return VERR_ADDRESS_CONFLICT;
2509	# else
2510	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2511	Assert(pMapping);
2512	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2513	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2514	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2515	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2516	# else
2517	AssertFailed(); /* can't happen for amd64 */
2518	# endif
2519	if (RT_FAILURE(rc))
2520	{
2521	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2522	return rc;
2523	}
2524	PdeDst = *pPdeDst;
2525	# endif
2526	}
2527	# endif /* !PGM_WITHOUT_MAPPINGS */
2528	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2529
2530	# if defined(IN_RC)
2531	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2532	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2533	# endif
2534
2535	/*
2536	* Sync page directory entry.
2537	*/
2538	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2539	if (PdeSrc.n.u1Present)
2540	{
2541	/*
2542	* Allocate & map the page table.
2543	*/
2544	PSHWPT pPTDst;
2545	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2546	const bool fPageTable = !PdeSrc.b.u1Size \|\| !CPUMIsGuestPageSizeExtEnabled(pVCpu);
2547	# else
2548	const bool fPageTable = !PdeSrc.b.u1Size;
2549	# endif
2550	PPGMPOOLPAGE pShwPage;
2551	RTGCPHYS GCPhys;
2552	if (fPageTable)
2553	{
2554	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2555	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2556	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2557	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2558	# endif
2559	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2560	}
2561	else
2562	{
2563	PGMPOOLACCESS enmAccess;
2564	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2565	const bool fNoExecute = PdeSrc.n.u1NoExecute && CPUMIsGuestNXEnabled(pVCpu);
2566	# else
2567	const bool fNoExecute = false;
2568	# endif
2569
2570	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
2571	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2572	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2573	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2574	# endif
2575	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2576	if (PdeSrc.n.u1User)
2577	{
2578	if (PdeSrc.n.u1Write)
2579	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2580	else
2581	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2582	}
2583	else
2584	{
2585	if (PdeSrc.n.u1Write)
2586	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2587	else
2588	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2589	}
2590	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2591	}
2592	if (rc == VINF_SUCCESS)
2593	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2594	else if (rc == VINF_PGM_CACHED_PAGE)
2595	{
2596	/*
2597	* The PT was cached, just hook it up.
2598	*/
2599	if (fPageTable)
2600	PdeDst.u = pShwPage->Core.Key
2601	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2602	else
2603	{
2604	PdeDst.u = pShwPage->Core.Key
2605	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2606	/* (see explanation and assumptions further down.) */
2607	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2608	{
2609	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2610	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2611	PdeDst.b.u1Write = 0;
2612	}
2613	}
2614	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2615	# if defined(IN_RC)
2616	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2617	# endif
2618	return VINF_SUCCESS;
2619	}
2620	else if (rc == VERR_PGM_POOL_FLUSHED)
2621	{
2622	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2623	# if defined(IN_RC)
2624	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2625	# endif
2626	return VINF_PGM_SYNC_CR3;
2627	}
2628	else
2629	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2630	PdeDst.u &= X86_PDE_AVL_MASK;
2631	PdeDst.u \|= pShwPage->Core.Key;
2632
2633	/*
2634	* Page directory has been accessed (this is a fault situation, remember).
2635	*/
2636	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2637	if (fPageTable)
2638	{
2639	/*
2640	* Page table - 4KB.
2641	*
2642	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2643	*/
2644	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2645	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2646	PGSTPT pPTSrc;
2647	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2648	if (RT_SUCCESS(rc))
2649	{
2650	/*
2651	* Start by syncing the page directory entry so CSAM's TLB trick works.
2652	*/
2653	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2654	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2655	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2656	# if defined(IN_RC)
2657	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2658	# endif
2659
2660	/*
2661	* Directory/page user or supervisor privilege: (same goes for read/write)
2662	*
2663	* Directory Page Combined
2664	* U/S U/S U/S
2665	* 0 0 0
2666	* 0 1 0
2667	* 1 0 0
2668	* 1 1 1
2669	*
2670	* Simple AND operation. Table listed for completeness.
2671	*
2672	*/
2673	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2674	# ifdef PGM_SYNC_N_PAGES
2675	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2676	unsigned iPTDst = iPTBase;
2677	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2678	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2679	iPTDst = 0;
2680	else
2681	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2682	# else /* !PGM_SYNC_N_PAGES */
2683	unsigned iPTDst = 0;
2684	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2685	# endif /* !PGM_SYNC_N_PAGES */
2686	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2687	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2688	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2689	# else
2690	const unsigned offPTSrc = 0;
2691	# endif
2692	for (; iPTDst < iPTDstEnd; iPTDst++)
2693	{
2694	const unsigned iPTSrc = iPTDst + offPTSrc;
2695	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2696
2697	if (PteSrc.n.u1Present) /* we've already cleared it above */
2698	{
2699	# ifndef IN_RING0
2700	/*
2701	* Assuming kernel code will be marked as supervisor - and not as user level
2702	* and executed using a conforming code selector - And marked as readonly.
2703	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2704	*/
2705	PPGMPAGE pPage;
2706	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2707	\|\| !CSAMDoesPageNeedScanning(pVM, (iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT))
2708	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2709	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2710	)
2711	# endif
2712	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2713	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2714	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2715	PteSrc.n.u1Present,
2716	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2717	PteSrc.n.u1User & PdeSrc.n.u1User,
2718	(uint64_t)PteSrc.u,
2719	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2720	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2721	}
2722	} /* for PTEs */
2723	}
2724	}
2725	else
2726	{
2727	/*
2728	* Big page - 2/4MB.
2729	*
2730	* We'll walk the ram range list in parallel and optimize lookups.
2731	* We will only sync on shadow page table at a time.
2732	*/
2733	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2734
2735	/**
2736	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2737	*/
2738
2739	/*
2740	* Start by syncing the page directory entry.
2741	*/
2742	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2743	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2744
2745	/*
2746	* If the page is not flagged as dirty and is writable, then make it read-only
2747	* at PD level, so we can set the dirty bit when the page is modified.
2748	*
2749	* ASSUMES that page access handlers are implemented on page table entry level.
2750	* Thus we will first catch the dirty access and set PDE.D and restart. If
2751	* there is an access handler, we'll trap again and let it work on the problem.
2752	*/
2753	/** @todo move the above stuff to a section in the PGM documentation. */
2754	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2755	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2756	{
2757	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2758	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2759	PdeDst.b.u1Write = 0;
2760	}
2761	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2762	# if defined(IN_RC)
2763	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2764	# endif
2765
2766	/*
2767	* Fill the shadow page table.
2768	*/
2769	/* Get address and flags from the source PDE. */
2770	SHWPTE PteDstBase;
2771	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2772
2773	/* Loop thru the entries in the shadow PT. */
2774	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2775	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2776	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2777	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2778	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2779	unsigned iPTDst = 0;
2780	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2781	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2782	{
2783	/* Advance ram range list. */
2784	while (pRam && GCPhys > pRam->GCPhysLast)
2785	pRam = pRam->CTX_SUFF(pNext);
2786	if (pRam && GCPhys >= pRam->GCPhys)
2787	{
2788	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2789	do
2790	{
2791	/* Make shadow PTE. */
2792	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2793	SHWPTE PteDst;
2794
2795	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2796	/* Try make the page writable if necessary. */
2797	if ( PteDstBase.n.u1Write
2798	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2799	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2800	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2801	# endif
2802	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2803	{
2804	rc = pgmPhysPageMakeWritableUnlocked(pVM, pPage, GCPhys);
2805	AssertRCReturn(rc, rc);
2806	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2807	break;
2808	}
2809	# endif
2810
2811	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2812	{
2813	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2814	{
2815	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2816	PteDst.n.u1Write = 0;
2817	}
2818	else
2819	PteDst.u = 0;
2820	}
2821	# ifndef IN_RING0
2822	/*
2823	* Assuming kernel code will be marked as supervisor and not as user level and executed
2824	* using a conforming code selector. Don't check for readonly, as that implies the whole
2825	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2826	*/
2827	else if ( !PdeSrc.n.u1User
2828	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2829	PteDst.u = 0;
2830	# endif
2831	else
2832	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2833
2834	/* Only map writable pages writable. */
2835	if ( PteDst.n.u1Write
2836	&& PteDst.n.u1Present
2837	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2838	{
2839	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2840	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2841	}
2842
2843	if (PteDst.n.u1Present)
2844	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2845
2846	/* commit it */
2847	pPTDst->a[iPTDst] = PteDst;
2848	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2849	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2850	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2851
2852	/* advance */
2853	GCPhys += PAGE_SIZE;
2854	iHCPage++;
2855	iPTDst++;
2856	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2857	&& GCPhys <= pRam->GCPhysLast);
2858	}
2859	else if (pRam)
2860	{
2861	Log(("Invalid pages at %RGp\n", GCPhys));
2862	do
2863	{
2864	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2865	GCPhys += PAGE_SIZE;
2866	iPTDst++;
2867	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2868	&& GCPhys < pRam->GCPhys);
2869	}
2870	else
2871	{
2872	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2873	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2874	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2875	}
2876	} /* while more PTEs */
2877	} /* 4KB / 4MB */
2878	}
2879	else
2880	AssertRelease(!PdeDst.n.u1Present);
2881
2882	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2883	if (RT_FAILURE(rc))
2884	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
2885	return rc;
2886
2887	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2888	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2889	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2890	&& !defined(IN_RC)
2891
2892	/*
2893	* Validate input a little bit.
2894	*/
2895	int rc = VINF_SUCCESS;
2896	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2897	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2898	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2899
2900	/* Fetch the pgm pool shadow descriptor. */
2901	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2902	Assert(pShwPde);
2903
2904	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2905	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2906	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2907	PX86PDPAE pPDDst;
2908	PSHWPDE pPdeDst;
2909
2910	/* Fetch the pgm pool shadow descriptor. */
2911	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2912	AssertRCSuccessReturn(rc, rc);
2913	Assert(pShwPde);
2914
2915	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2916	pPdeDst = &pPDDst->a[iPDDst];
2917
2918	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2919	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2920	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2921	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2922	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2923	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2924	AssertRCSuccessReturn(rc, rc);
2925	Assert(pPDDst);
2926	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2927
2928	/* Fetch the pgm pool shadow descriptor. */
2929	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2930	Assert(pShwPde);
2931
2932	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2933	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2934	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2935	PEPTPD pPDDst;
2936	PEPTPDPT pPdptDst;
2937
2938	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2939	if (rc != VINF_SUCCESS)
2940	{
2941	AssertRC(rc);
2942	return rc;
2943	}
2944	Assert(pPDDst);
2945	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2946
2947	/* Fetch the pgm pool shadow descriptor. */
2948	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2949	Assert(pShwPde);
2950	# endif
2951	SHWPDE PdeDst = *pPdeDst;
2952
2953	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2954	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2955
2956	# if (PGM_SHW_TYPE == PGM_TYPE_EPT) && (HC_ARCH_BITS == 64) && defined(RT_OS_WINDOWS)
2957	if (PGMIsUsingLargePages(pVM))
2958	{
2959	RTHCPHYS HCPhys;
2960	rc = pgmPhysAllocLargePage(pVM, GCPtrPage & SHW_PDE_PG_MASK, &HCPhys);
2961	if (RT_SUCCESS(rc))
2962	{
2963	PdeDst.u &= X86_PDE_AVL_MASK;
2964	PdeDst.u \|= HCPhys;
2965	PdeDst.n.u1Present = 1;
2966	PdeDst.n.u1Write = 1;
2967	PdeDst.n.u1Execute = 1;
2968	PdeDst.b.u1Size = 1;
2969	PdeDst.b.u1IgnorePAT = 1;
2970	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
2971	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2972
2973	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2974	return VINF_SUCCESS;
2975
2976	}
2977	else
2978	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
2979	}
2980	# endif
2981
2982	GSTPDE PdeSrc;
2983	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2984	PdeSrc.n.u1Present = 1;
2985	PdeSrc.n.u1Write = 1;
2986	PdeSrc.n.u1Accessed = 1;
2987	PdeSrc.n.u1User = 1;
2988
2989	/*
2990	* Allocate & map the page table.
2991	*/
2992	PSHWPT pPTDst;
2993	PPGMPOOLPAGE pShwPage;
2994	RTGCPHYS GCPhys;
2995
2996	/* Virtual address = physical address */
2997	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
2998	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2999
3000	if ( rc == VINF_SUCCESS
3001	\|\| rc == VINF_PGM_CACHED_PAGE)
3002	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3003	else
3004	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3005
3006	PdeDst.u &= X86_PDE_AVL_MASK;
3007	PdeDst.u \|= pShwPage->Core.Key;
3008	PdeDst.n.u1Present = 1;
3009	PdeDst.n.u1Write = 1;
3010	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3011	PdeDst.n.u1Execute = 1;
3012	# else
3013	PdeDst.n.u1User = 1;
3014	PdeDst.n.u1Accessed = 1;
3015	# endif
3016	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3017
3018	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3019	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3020	return rc;
3021
3022	#else
3023	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3024	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3025	return VERR_INTERNAL_ERROR;
3026	#endif
3027	}
3028
3029
3030
3031	/**
3032	* Prefetch a page/set of pages.
3033	*
3034	* Typically used to sync commonly used pages before entering raw mode
3035	* after a CR3 reload.
3036	*
3037	* @returns VBox status code.
3038	* @param pVCpu The VMCPU handle.
3039	* @param GCPtrPage Page to invalidate.
3040	*/
3041	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3042	{
3043	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
3044	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3045	/*
3046	* Check that all Guest levels thru the PDE are present, getting the
3047	* PD and PDE in the processes.
3048	*/
3049	int rc = VINF_SUCCESS;
3050	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3051	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3052	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3053	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3054	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3055	unsigned iPDSrc;
3056	X86PDPE PdpeSrc;
3057	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3058	if (!pPDSrc)
3059	return VINF_SUCCESS; /* not present */
3060	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3061	unsigned iPDSrc;
3062	PX86PML4E pPml4eSrc;
3063	X86PDPE PdpeSrc;
3064	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3065	if (!pPDSrc)
3066	return VINF_SUCCESS; /* not present */
3067	# endif
3068	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3069	# else
3070	PGSTPD pPDSrc = NULL;
3071	const unsigned iPDSrc = 0;
3072	GSTPDE PdeSrc;
3073
3074	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3075	PdeSrc.n.u1Present = 1;
3076	PdeSrc.n.u1Write = 1;
3077	PdeSrc.n.u1Accessed = 1;
3078	PdeSrc.n.u1User = 1;
3079	# endif
3080
3081	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3082	{
3083	PVM pVM = pVCpu->CTX_SUFF(pVM);
3084	pgmLock(pVM);
3085
3086	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3087	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3088	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3089	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3090	PX86PDPAE pPDDst;
3091	X86PDEPAE PdeDst;
3092	# if PGM_GST_TYPE != PGM_TYPE_PAE
3093	X86PDPE PdpeSrc;
3094
3095	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3096	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3097	# endif
3098	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3099	if (rc != VINF_SUCCESS)
3100	{
3101	pgmUnlock(pVM);
3102	AssertRC(rc);
3103	return rc;
3104	}
3105	Assert(pPDDst);
3106	PdeDst = pPDDst->a[iPDDst];
3107
3108	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3109	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3110	PX86PDPAE pPDDst;
3111	X86PDEPAE PdeDst;
3112
3113	# if PGM_GST_TYPE == PGM_TYPE_PROT
3114	/* AMD-V nested paging */
3115	X86PML4E Pml4eSrc;
3116	X86PDPE PdpeSrc;
3117	PX86PML4E pPml4eSrc = &Pml4eSrc;
3118
3119	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3120	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3121	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3122	# endif
3123
3124	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3125	if (rc != VINF_SUCCESS)
3126	{
3127	pgmUnlock(pVM);
3128	AssertRC(rc);
3129	return rc;
3130	}
3131	Assert(pPDDst);
3132	PdeDst = pPDDst->a[iPDDst];
3133	# endif
3134	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3135	{
3136	if (!PdeDst.n.u1Present)
3137	{
3138	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
3139	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3140	}
3141	else
3142	{
3143	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3144	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3145	* makes no sense to prefetch more than one page.
3146	*/
3147	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3148	if (RT_SUCCESS(rc))
3149	rc = VINF_SUCCESS;
3150	}
3151	}
3152	pgmUnlock(pVM);
3153	}
3154	return rc;
3155
3156	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3157	return VINF_SUCCESS; /* ignore */
3158	#endif
3159	}
3160
3161
3162
3163
3164	/**
3165	* Syncs a page during a PGMVerifyAccess() call.
3166	*
3167	* @returns VBox status code (informational included).
3168	* @param pVCpu The VMCPU handle.
3169	* @param GCPtrPage The address of the page to sync.
3170	* @param fPage The effective guest page flags.
3171	* @param uErr The trap error code.
3172	*/
3173	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3174	{
3175	PVM pVM = pVCpu->CTX_SUFF(pVM);
3176
3177	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3178
3179	Assert(!HWACCMIsNestedPagingActive(pVM));
3180	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_TYPE_AMD64) \
3181	&& PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3182
3183	# ifndef IN_RING0
3184	if (!(fPage & X86_PTE_US))
3185	{
3186	/*
3187	* Mark this page as safe.
3188	*/
3189	/** @todo not correct for pages that contain both code and data!! */
3190	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3191	CSAMMarkPage(pVM, GCPtrPage, true);
3192	}
3193	# endif
3194
3195	/*
3196	* Get guest PD and index.
3197	*/
3198	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3199	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3200	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3201	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3202	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3203	unsigned iPDSrc = 0;
3204	X86PDPE PdpeSrc;
3205	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtrPage, &iPDSrc, &PdpeSrc);
3206
3207	if (pPDSrc)
3208	{
3209	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3210	return VINF_EM_RAW_GUEST_TRAP;
3211	}
3212	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3213	unsigned iPDSrc;
3214	PX86PML4E pPml4eSrc;
3215	X86PDPE PdpeSrc;
3216	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3217	if (!pPDSrc)
3218	{
3219	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3220	return VINF_EM_RAW_GUEST_TRAP;
3221	}
3222	# endif
3223	# else
3224	PGSTPD pPDSrc = NULL;
3225	const unsigned iPDSrc = 0;
3226	# endif
3227	int rc = VINF_SUCCESS;
3228
3229	pgmLock(pVM);
3230
3231	/*
3232	* First check if the shadow pd is present.
3233	*/
3234	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3235	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3236	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3237	PX86PDEPAE pPdeDst;
3238	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3239	PX86PDPAE pPDDst;
3240	# if PGM_GST_TYPE != PGM_TYPE_PAE
3241	X86PDPE PdpeSrc;
3242
3243	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3244	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3245	# endif
3246	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, &PdpeSrc, &pPDDst);
3247	if (rc != VINF_SUCCESS)
3248	{
3249	pgmUnlock(pVM);
3250	AssertRC(rc);
3251	return rc;
3252	}
3253	Assert(pPDDst);
3254	pPdeDst = &pPDDst->a[iPDDst];
3255
3256	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3257	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3258	PX86PDPAE pPDDst;
3259	PX86PDEPAE pPdeDst;
3260
3261	# if PGM_GST_TYPE == PGM_TYPE_PROT
3262	/* AMD-V nested paging */
3263	X86PML4E Pml4eSrc;
3264	X86PDPE PdpeSrc;
3265	PX86PML4E pPml4eSrc = &Pml4eSrc;
3266
3267	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3268	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_NX \| X86_PML4E_A;
3269	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_NX \| X86_PDPE_A;
3270	# endif
3271
3272	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc, &PdpeSrc, &pPDDst);
3273	if (rc != VINF_SUCCESS)
3274	{
3275	pgmUnlock(pVM);
3276	AssertRC(rc);
3277	return rc;
3278	}
3279	Assert(pPDDst);
3280	pPdeDst = &pPDDst->a[iPDDst];
3281	# endif
3282
3283	# if defined(IN_RC)
3284	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3285	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3286	# endif
3287
3288	if (!pPdeDst->n.u1Present)
3289	{
3290	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3291	if (rc != VINF_SUCCESS)
3292	{
3293	# if defined(IN_RC)
3294	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3295	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3296	# endif
3297	pgmUnlock(pVM);
3298	AssertRC(rc);
3299	return rc;
3300	}
3301	}
3302
3303	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3304	/* Check for dirty bit fault */
3305	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3306	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3307	Log(("PGMVerifyAccess: success (dirty)\n"));
3308	else
3309	{
3310	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3311	# else
3312	{
3313	GSTPDE PdeSrc;
3314	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
3315	PdeSrc.n.u1Present = 1;
3316	PdeSrc.n.u1Write = 1;
3317	PdeSrc.n.u1Accessed = 1;
3318	PdeSrc.n.u1User = 1;
3319
3320	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
3321	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3322	if (uErr & X86_TRAP_PF_US)
3323	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3324	else /* supervisor */
3325	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3326
3327	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3328	if (RT_SUCCESS(rc))
3329	{
3330	/* Page was successfully synced */
3331	Log2(("PGMVerifyAccess: success (sync)\n"));
3332	rc = VINF_SUCCESS;
3333	}
3334	else
3335	{
3336	Log(("PGMVerifyAccess: access violation for %RGv rc=%d\n", GCPtrPage, rc));
3337	rc = VINF_EM_RAW_GUEST_TRAP;
3338	}
3339	}
3340	# if defined(IN_RC)
3341	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3342	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3343	# endif
3344	pgmUnlock(pVM);
3345	return rc;
3346
3347	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3348
3349	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3350	return VERR_INTERNAL_ERROR;
3351	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
3352	}
3353
3354	#undef MY_STAM_COUNTER_INC
3355	#define MY_STAM_COUNTER_INC(a) do { } while (0)
3356
3357
3358	/**
3359	* Syncs the paging hierarchy starting at CR3.
3360	*
3361	* @returns VBox status code, no specials.
3362	* @param pVCpu The VMCPU handle.
3363	* @param cr0 Guest context CR0 register
3364	* @param cr3 Guest context CR3 register
3365	* @param cr4 Guest context CR4 register
3366	* @param fGlobal Including global page directories or not
3367	*/
3368	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3369	{
3370	PVM pVM = pVCpu->CTX_SUFF(pVM);
3371
3372	if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3))
3373	fGlobal = true; /* Change this CR3 reload to be a global one. */
3374
3375	LogFlow(("SyncCR3 %d\n", fGlobal));
3376
3377	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3378
3379	pgmLock(pVM);
3380	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3381	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3382	if (pPool->cDirtyPages)
3383	pgmPoolResetDirtyPages(pVM);
3384	# endif
3385
3386	/*
3387	* Update page access handlers.
3388	* The virtual are always flushed, while the physical are only on demand.
3389	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3390	* have to look into that later because it will have a bad influence on the performance.
3391	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3392	* bird: Yes, but that won't work for aliases.
3393	*/
3394	/** @todo this MUST go away. See #1557. */
3395	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3396	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3397	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3398	pgmUnlock(pVM);
3399	#endif /* !NESTED && !EPT */
3400
3401	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3402	/*
3403	* Nested / EPT - almost no work.
3404	*/
3405	/** @todo check if this is really necessary; the call does it as well... */
3406	HWACCMFlushTLB(pVCpu);
3407	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3408	return VINF_SUCCESS;
3409
3410	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3411	/*
3412	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3413	* out the shadow parts when the guest modifies its tables.
3414	*/
3415	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3416	return VINF_SUCCESS;
3417
3418	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3419
3420	# ifndef PGM_WITHOUT_MAPPINGS
3421	/*
3422	* Check for and resolve conflicts with our guest mappings if they
3423	* are enabled and not fixed.
3424	*/
3425	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3426	{
3427	int rc = pgmMapResolveConflicts(pVM);
3428	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3429	if (rc == VINF_PGM_SYNC_CR3)
3430	{
3431	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3432	return VINF_PGM_SYNC_CR3;
3433	}
3434	}
3435	# else
3436	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3437	# endif
3438	return VINF_SUCCESS;
3439	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3440	}
3441
3442
3443
3444
3445	#ifdef VBOX_STRICT
3446	#ifdef IN_RC
3447	# undef AssertMsgFailed
3448	# define AssertMsgFailed Log
3449	#endif
3450	#ifdef IN_RING3
3451	# include <VBox/dbgf.h>
3452
3453	/**
3454	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3455	*
3456	* @returns VBox status code (VINF_SUCCESS).
3457	* @param cr3 The root of the hierarchy.
3458	* @param crr The cr4, only PAE and PSE is currently used.
3459	* @param fLongMode Set if long mode, false if not long mode.
3460	* @param cMaxDepth Number of levels to dump.
3461	* @param pHlp Pointer to the output functions.
3462	*/
3463	RT_C_DECLS_BEGIN
3464	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3465	RT_C_DECLS_END
3466
3467	#endif
3468
3469	/**
3470	* Checks that the shadow page table is in sync with the guest one.
3471	*
3472	* @returns The number of errors.
3473	* @param pVM The virtual machine.
3474	* @param pVCpu The VMCPU handle.
3475	* @param cr3 Guest context CR3 register
3476	* @param cr4 Guest context CR4 register
3477	* @param GCPtr Where to start. Defaults to 0.
3478	* @param cb How much to check. Defaults to everything.
3479	*/
3480	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3481	{
3482	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3483	return 0;
3484	#else
3485	unsigned cErrors = 0;
3486	PVM pVM = pVCpu->CTX_SUFF(pVM);
3487	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3488
3489	#if PGM_GST_TYPE == PGM_TYPE_PAE
3490	/** @todo currently broken; crashes below somewhere */
3491	AssertFailed();
3492	#endif
3493
3494	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3495	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3496	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3497
3498	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3499	bool fBigPagesSupported = CPUMIsGuestPageSizeExtEnabled(pVCpu);
3500	# else
3501	bool fBigPagesSupported = true;
3502	# endif
3503	PPGMCPU pPGM = &pVCpu->pgm.s;
3504	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3505	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3506	# ifndef IN_RING0
3507	RTHCPHYS HCPhys; /* general usage. */
3508	# endif
3509	int rc;
3510
3511	/*
3512	* Check that the Guest CR3 and all its mappings are correct.
3513	*/
3514	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3515	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3516	false);
3517	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3518	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3519	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3520	# else
3521	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3522	# endif
3523	AssertRCReturn(rc, 1);
3524	HCPhys = NIL_RTHCPHYS;
3525	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3526	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3527	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3528	pgmGstGet32bitPDPtr(pPGM);
3529	RTGCPHYS GCPhys;
3530	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3531	AssertRCReturn(rc, 1);
3532	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3533	# endif
3534	# endif /* !IN_RING0 */
3535
3536	/*
3537	* Get and check the Shadow CR3.
3538	*/
3539	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3540	unsigned cPDEs = X86_PG_ENTRIES;
3541	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3542	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3543	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3544	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3545	# else
3546	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3547	# endif
3548	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3549	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3550	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3551	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3552	# endif
3553	if (cb != ~(RTGCPTR)0)
3554	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3555
3556	/** @todo call the other two PGMAssert() functions. /
3557
3558	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3559	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3560
3561	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3562	{
3563	PPGMPOOLPAGE pShwPdpt = NULL;
3564	PX86PML4E pPml4eSrc;
3565	PX86PML4E pPml4eDst;
3566	RTGCPHYS GCPhysPdptSrc;
3567
3568	pPml4eSrc = pgmGstGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3569	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3570
3571	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3572	if (!pPml4eDst->n.u1Present)
3573	{
3574	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3575	continue;
3576	}
3577
3578	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3579	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3580
3581	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3582	{
3583	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3584	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3585	cErrors++;
3586	continue;
3587	}
3588
3589	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3590	{
3591	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3592	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3593	cErrors++;
3594	continue;
3595	}
3596
3597	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3598	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3599	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3600	{
3601	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3602	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3603	cErrors++;
3604	continue;
3605	}
3606	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3607	{
3608	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3609
3610	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3611	/*
3612	* Check the PDPTEs too.
3613	*/
3614	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3615
3616	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3617	{
3618	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3619	PPGMPOOLPAGE pShwPde = NULL;
3620	PX86PDPE pPdpeDst;
3621	RTGCPHYS GCPhysPdeSrc;
3622	# if PGM_GST_TYPE == PGM_TYPE_PAE
3623	X86PDPE PdpeSrc;
3624	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVCpu->pgm.s, GCPtr, &iPDSrc, &PdpeSrc);
3625	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3626	# else
3627	PX86PML4E pPml4eSrcIgn;
3628	X86PDPE PdpeSrc;
3629	PX86PDPT pPdptDst;
3630	PX86PDPAE pPDDst;
3631	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(&pVCpu->pgm.s, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3632
3633	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3634	if (rc != VINF_SUCCESS)
3635	{
3636	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3637	GCPtr += 512 * _2M;
3638	continue; /* next PDPTE */
3639	}
3640	Assert(pPDDst);
3641	# endif
3642	Assert(iPDSrc == 0);
3643
3644	pPdpeDst = &pPdptDst->a[iPdpt];
3645
3646	if (!pPdpeDst->n.u1Present)
3647	{
3648	GCPtr += 512 * _2M;
3649	continue; /* next PDPTE */
3650	}
3651
3652	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3653	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3654
3655	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3656	{
3657	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3658	GCPtr += 512 * _2M;
3659	cErrors++;
3660	continue;
3661	}
3662
3663	if (GCPhysPdeSrc != pShwPde->GCPhys)
3664	{
3665	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3666	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3667	# else
3668	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3669	# endif
3670	GCPtr += 512 * _2M;
3671	cErrors++;
3672	continue;
3673	}
3674
3675	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3676	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3677	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3678	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3679	{
3680	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3681	GCPtr += 512 * _2M;
3682	cErrors++;
3683	continue;
3684	}
3685	# endif
3686
3687	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3688	{
3689	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3690	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3691	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3692	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3693	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
3694	# endif
3695	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3696	/*
3697	* Iterate the shadow page directory.
3698	*/
3699	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3700	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3701
3702	for (;
3703	iPDDst < cPDEs;
3704	iPDDst++, GCPtr += cIncrement)
3705	{
3706	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3707	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
3708	# else
3709	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3710	# endif
3711	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3712	{
3713	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3714	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3715	{
3716	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3717	cErrors++;
3718	continue;
3719	}
3720	}
3721	else if ( (PdeDst.u & X86_PDE_P)
3722	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3723	)
3724	{
3725	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3726	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3727	if (!pPoolPage)
3728	{
3729	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3730	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3731	cErrors++;
3732	continue;
3733	}
3734	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3735
3736	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3737	{
3738	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3739	GCPtr, (uint64_t)PdeDst.u));
3740	cErrors++;
3741	}
3742
3743	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3744	{
3745	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3746	GCPtr, (uint64_t)PdeDst.u));
3747	cErrors++;
3748	}
3749
3750	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3751	if (!PdeSrc.n.u1Present)
3752	{
3753	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3754	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3755	cErrors++;
3756	continue;
3757	}
3758
3759	if ( !PdeSrc.b.u1Size
3760	\|\| !fBigPagesSupported)
3761	{
3762	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3763	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3764	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3765	# endif
3766	}
3767	else
3768	{
3769	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3770	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3771	{
3772	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3773	GCPtr, (uint64_t)PdeSrc.u));
3774	cErrors++;
3775	continue;
3776	}
3777	# endif
3778	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(PdeSrc);
3779	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3780	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3781	# endif
3782	}
3783
3784	if ( pPoolPage->enmKind
3785	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3786	{
3787	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3788	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3789	cErrors++;
3790	}
3791
3792	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3793	if (!pPhysPage)
3794	{
3795	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3796	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3797	cErrors++;
3798	continue;
3799	}
3800
3801	if (GCPhysGst != pPoolPage->GCPhys)
3802	{
3803	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3804	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3805	cErrors++;
3806	continue;
3807	}
3808
3809	if ( !PdeSrc.b.u1Size
3810	\|\| !fBigPagesSupported)
3811	{
3812	/*
3813	* Page Table.
3814	*/
3815	const GSTPT *pPTSrc;
3816	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3817	if (RT_FAILURE(rc))
3818	{
3819	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3820	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3821	cErrors++;
3822	continue;
3823	}
3824	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3825	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3826	{
3827	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3828	// (This problem will go away when/if we shadow multiple CR3s.)
3829	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3830	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3831	cErrors++;
3832	continue;
3833	}
3834	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3835	{
3836	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3837	GCPtr, (uint64_t)PdeDst.u));
3838	cErrors++;
3839	continue;
3840	}
3841
3842	/* iterate the page table. */
3843	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3844	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3845	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3846	# else
3847	const unsigned offPTSrc = 0;
3848	# endif
3849	for (unsigned iPT = 0, off = 0;
3850	iPT < RT_ELEMENTS(pPTDst->a);
3851	iPT++, off += PAGE_SIZE)
3852	{
3853	const SHWPTE PteDst = pPTDst->a[iPT];
3854
3855	/* skip not-present entries. */
3856	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3857	continue;
3858	Assert(PteDst.n.u1Present);
3859
3860	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3861	if (!PteSrc.n.u1Present)
3862	{
3863	# ifdef IN_RING3
3864	PGMAssertHandlerAndFlagsInSync(pVM);
3865	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3866	# endif
3867	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3868	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3869	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3870	cErrors++;
3871	continue;
3872	}
3873
3874	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3875	# if 1 /** @todo sync accessed bit properly... */
3876	fIgnoreFlags \|= X86_PTE_A;
3877	# endif
3878
3879	/* match the physical addresses */
3880	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3881	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3882
3883	# ifdef IN_RING3
3884	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3885	if (RT_FAILURE(rc))
3886	{
3887	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3888	{
3889	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3890	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3891	cErrors++;
3892	continue;
3893	}
3894	}
3895	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3896	{
3897	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3898	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3899	cErrors++;
3900	continue;
3901	}
3902	# endif
3903
3904	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3905	if (!pPhysPage)
3906	{
3907	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3908	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3909	{
3910	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3911	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3912	cErrors++;
3913	continue;
3914	}
3915	# endif
3916	if (PteDst.n.u1Write)
3917	{
3918	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3919	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3920	cErrors++;
3921	}
3922	fIgnoreFlags \|= X86_PTE_RW;
3923	}
3924	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
3925	{
3926	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3927	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3928	cErrors++;
3929	continue;
3930	}
3931
3932	/* flags */
3933	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3934	{
3935	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3936	{
3937	if (PteDst.n.u1Write)
3938	{
3939	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3940	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3941	cErrors++;
3942	continue;
3943	}
3944	fIgnoreFlags \|= X86_PTE_RW;
3945	}
3946	else
3947	{
3948	if (PteDst.n.u1Present)
3949	{
3950	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
3951	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3952	cErrors++;
3953	continue;
3954	}
3955	fIgnoreFlags \|= X86_PTE_P;
3956	}
3957	}
3958	else
3959	{
3960	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3961	{
3962	if (PteDst.n.u1Write)
3963	{
3964	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3965	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3966	cErrors++;
3967	continue;
3968	}
3969	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3970	{
3971	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3972	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3973	cErrors++;
3974	continue;
3975	}
3976	if (PteDst.n.u1Dirty)
3977	{
3978	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3979	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3980	cErrors++;
3981	}
3982	# if 0 /** @todo sync access bit properly... */
3983	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3984	{
3985	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3986	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3987	cErrors++;
3988	}
3989	fIgnoreFlags \|= X86_PTE_RW;
3990	# else
3991	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3992	# endif
3993	}
3994	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3995	{
3996	/* access bit emulation (not implemented). */
3997	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3998	{
3999	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4000	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4001	cErrors++;
4002	continue;
4003	}
4004	if (!PteDst.n.u1Accessed)
4005	{
4006	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4007	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4008	cErrors++;
4009	}
4010	fIgnoreFlags \|= X86_PTE_P;
4011	}
4012	# ifdef DEBUG_sandervl
4013	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4014	# endif
4015	}
4016
4017	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4018	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4019	)
4020	{
4021	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4022	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4023	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4024	cErrors++;
4025	continue;
4026	}
4027	} /* foreach PTE */
4028	}
4029	else
4030	{
4031	/*
4032	* Big Page.
4033	*/
4034	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4035	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4036	{
4037	if (PdeDst.n.u1Write)
4038	{
4039	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4040	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4041	cErrors++;
4042	continue;
4043	}
4044	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4045	{
4046	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4047	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4048	cErrors++;
4049	continue;
4050	}
4051	# if 0 /** @todo sync access bit properly... */
4052	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4053	{
4054	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4055	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4056	cErrors++;
4057	}
4058	fIgnoreFlags \|= X86_PTE_RW;
4059	# else
4060	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4061	# endif
4062	}
4063	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4064	{
4065	/* access bit emulation (not implemented). */
4066	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4067	{
4068	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4069	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4070	cErrors++;
4071	continue;
4072	}
4073	if (!PdeDst.n.u1Accessed)
4074	{
4075	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4076	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4077	cErrors++;
4078	}
4079	fIgnoreFlags \|= X86_PTE_P;
4080	}
4081
4082	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4083	{
4084	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4085	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4086	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4087	cErrors++;
4088	}
4089
4090	/* iterate the page table. */
4091	for (unsigned iPT = 0, off = 0;
4092	iPT < RT_ELEMENTS(pPTDst->a);
4093	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4094	{
4095	const SHWPTE PteDst = pPTDst->a[iPT];
4096
4097	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4098	{
4099	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4100	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4101	cErrors++;
4102	}
4103
4104	/* skip not-present entries. */
4105	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4106	continue;
4107
4108	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4109
4110	/* match the physical addresses */
4111	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4112
4113	# ifdef IN_RING3
4114	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4115	if (RT_FAILURE(rc))
4116	{
4117	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4118	{
4119	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4120	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4121	cErrors++;
4122	}
4123	}
4124	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4125	{
4126	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4127	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4128	cErrors++;
4129	continue;
4130	}
4131	# endif
4132	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4133	if (!pPhysPage)
4134	{
4135	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4136	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4137	{
4138	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4139	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4140	cErrors++;
4141	continue;
4142	}
4143	# endif
4144	if (PteDst.n.u1Write)
4145	{
4146	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4147	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4148	cErrors++;
4149	}
4150	fIgnoreFlags \|= X86_PTE_RW;
4151	}
4152	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4153	{
4154	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4155	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4156	cErrors++;
4157	continue;
4158	}
4159
4160	/* flags */
4161	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4162	{
4163	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4164	{
4165	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4166	{
4167	if (PteDst.n.u1Write)
4168	{
4169	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4170	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4171	cErrors++;
4172	continue;
4173	}
4174	fIgnoreFlags \|= X86_PTE_RW;
4175	}
4176	}
4177	else
4178	{
4179	if (PteDst.n.u1Present)
4180	{
4181	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4182	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4183	cErrors++;
4184	continue;
4185	}
4186	fIgnoreFlags \|= X86_PTE_P;
4187	}
4188	}
4189
4190	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4191	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4192	)
4193	{
4194	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4195	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4196	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4197	cErrors++;
4198	continue;
4199	}
4200	} /* for each PTE */
4201	}
4202	}
4203	/* not present */
4204
4205	} /* for each PDE */
4206
4207	} /* for each PDPTE */
4208
4209	} /* for each PML4E */
4210
4211	# ifdef DEBUG
4212	if (cErrors)
4213	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4214	# endif
4215
4216	#endif /* GST == 32BIT, PAE or AMD64 */
4217	return cErrors;
4218
4219	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4220	}
4221	#endif /* VBOX_STRICT */
4222
4223
4224	/**
4225	* Sets up the CR3 for shadow paging
4226	*
4227	* @returns Strict VBox status code.
4228	* @retval VINF_SUCCESS.
4229	*
4230	* @param pVCpu The VMCPU handle.
4231	* @param GCPhysCR3 The physical address in the CR3 register.
4232	*/
4233	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4234	{
4235	PVM pVM = pVCpu->CTX_SUFF(pVM);
4236
4237	/* Update guest paging info. */
4238	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4239	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4240	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4241
4242	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4243
4244	/*
4245	* Map the page CR3 points at.
4246	*/
4247	RTHCPTR HCPtrGuestCR3;
4248	RTHCPHYS HCPhysGuestCR3;
4249	pgmLock(pVM);
4250	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4251	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4252	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4253	/** @todo this needs some reworking wrt. locking. */
4254	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4255	HCPtrGuestCR3 = NIL_RTHCPTR;
4256	int rc = VINF_SUCCESS;
4257	# else
4258	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4259	# endif
4260	pgmUnlock(pVM);
4261	if (RT_SUCCESS(rc))
4262	{
4263	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4264	if (RT_SUCCESS(rc))
4265	{
4266	# ifdef IN_RC
4267	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4268	# endif
4269	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4270	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4271	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4272	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4273	# endif
4274	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4275
4276	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4277	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4278	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4279	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4280	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4281	# endif
4282	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4283	Log(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4284
4285	/*
4286	* Map the 4 PDs too.
4287	*/
4288	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(&pVCpu->pgm.s);
4289	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4290	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4291	{
4292	if (pGuestPDPT->a[i].n.u1Present)
4293	{
4294	RTHCPTR HCPtr;
4295	RTHCPHYS HCPhys;
4296	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4297	pgmLock(pVM);
4298	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4299	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4300	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4301	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4302	HCPtr = NIL_RTHCPTR;
4303	int rc2 = VINF_SUCCESS;
4304	# else
4305	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4306	# endif
4307	pgmUnlock(pVM);
4308	if (RT_SUCCESS(rc2))
4309	{
4310	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4311	AssertRCReturn(rc, rc);
4312
4313	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4314	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4315	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4316	# endif
4317	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4318	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4319	# ifdef IN_RC
4320	PGM_INVL_PG(pVCpu, GCPtr);
4321	# endif
4322	continue;
4323	}
4324	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4325	}
4326
4327	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4328	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4329	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4330	# endif
4331	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4332	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4333	# ifdef IN_RC
4334	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4335	# endif
4336	}
4337
4338	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4339	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4340	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4341	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4342	# endif
4343	# endif
4344	}
4345	else
4346	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4347	}
4348	else
4349	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4350
4351	#else /* prot/real stub */
4352	int rc = VINF_SUCCESS;
4353	#endif
4354
4355	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4356	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4357	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4358	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4359	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4360	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4361
4362	Assert(!HWACCMIsNestedPagingActive(pVM));
4363
4364	/*
4365	* Update the shadow root page as well since that's not fixed.
4366	*/
4367	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4368	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4369	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4370	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4371	PPGMPOOLPAGE pNewShwPageCR3;
4372
4373	pgmLock(pVM);
4374
4375	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4376	if (pPool->cDirtyPages)
4377	pgmPoolResetDirtyPages(pVM);
4378	# endif
4379
4380	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4381	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4382	AssertFatalRC(rc);
4383	rc = VINF_SUCCESS;
4384
4385	# ifdef IN_RC
4386	/*
4387	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4388	* state will be inconsistent! Flush important things now while
4389	* we still can and then make sure there are no ring-3 calls.
4390	*/
4391	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4392	VMMRZCallRing3Disable(pVCpu);
4393	# endif
4394
4395	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4396	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4397	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4398	# ifdef IN_RING0
4399	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4400	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4401	# elif defined(IN_RC)
4402	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4403	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4404	# else
4405	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4406	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4407	# endif
4408
4409	# ifndef PGM_WITHOUT_MAPPINGS
4410	/*
4411	* Apply all hypervisor mappings to the new CR3.
4412	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4413	* make sure we check for conflicts in the new CR3 root.
4414	*/
4415	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4416	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4417	# endif
4418	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4419	AssertRCReturn(rc, rc);
4420	# endif
4421
4422	/* Set the current hypervisor CR3. */
4423	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4424	SELMShadowCR3Changed(pVM, pVCpu);
4425
4426	# ifdef IN_RC
4427	/* NOTE: The state is consistent again. */
4428	VMMRZCallRing3Enable(pVCpu);
4429	# endif
4430
4431	/* Clean up the old CR3 root. */
4432	if ( pOldShwPageCR3
4433	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4434	{
4435	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4436	# ifndef PGM_WITHOUT_MAPPINGS
4437	/* Remove the hypervisor mappings from the shadow page table. */
4438	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4439	# endif
4440	/* Mark the page as unlocked; allow flushing again. */
4441	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4442
4443	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4444	}
4445	pgmUnlock(pVM);
4446	# endif
4447
4448	return rc;
4449	}
4450
4451	/**
4452	* Unmaps the shadow CR3.
4453	*
4454	* @returns VBox status, no specials.
4455	* @param pVCpu The VMCPU handle.
4456	*/
4457	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4458	{
4459	LogFlow(("UnmapCR3\n"));
4460
4461	int rc = VINF_SUCCESS;
4462	PVM pVM = pVCpu->CTX_SUFF(pVM);
4463
4464	/*
4465	* Update guest paging info.
4466	*/
4467	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4468	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4469	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4470	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4471	# endif
4472	pVCpu->pgm.s.pGst32BitPdRC = 0;
4473
4474	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4475	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4476	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4477	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4478	# endif
4479	pVCpu->pgm.s.pGstPaePdptRC = 0;
4480	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4481	{
4482	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4483	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4484	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4485	# endif
4486	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4487	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4488	}
4489
4490	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4491	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4492	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4493	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4494	# endif
4495
4496	#else /* prot/real mode stub */
4497	/* nothing to do */
4498	#endif
4499
4500	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4501	/*
4502	* Update shadow paging info.
4503	*/
4504	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4505	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4506	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4507
4508	# if PGM_GST_TYPE != PGM_TYPE_REAL
4509	Assert(!HWACCMIsNestedPagingActive(pVM));
4510	# endif
4511
4512	pgmLock(pVM);
4513
4514	# ifndef PGM_WITHOUT_MAPPINGS
4515	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4516	/* Remove the hypervisor mappings from the shadow page table. */
4517	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4518	# endif
4519
4520	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4521	{
4522	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4523
4524	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4525
4526	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4527	if (pPool->cDirtyPages)
4528	pgmPoolResetDirtyPages(pVM);
4529	# endif
4530
4531	/* Mark the page as unlocked; allow flushing again. */
4532	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4533
4534	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4535	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4536	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4537	pVCpu->pgm.s.pShwPageCR3RC = 0;
4538	pVCpu->pgm.s.iShwUser = 0;
4539	pVCpu->pgm.s.iShwUserTable = 0;
4540	}
4541	pgmUnlock(pVM);
4542	# endif
4543	#endif /* !IN_RC*/
4544
4545	return rc;
4546	}
4547

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 26701

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