PGMAllBth.h@ 2744

Last change on this file since 2744 was 2701, checked in by vboxsync, 18 years ago
Stupid typo
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1	/* $Id: PGMAllBth.h 2701 2007-05-17 16:22:43Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006 InnoTek Systemberatung GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License as published by the Free Software Foundation,
15	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
16	* distribution. VirtualBox OSE is distributed in the hope that it will
17	* be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* If you received this file as part of a commercial VirtualBox
20	* distribution, then only the terms of your commercial VirtualBox
21	* license agreement apply instead of the previous paragraph.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/**
46	* #PF Handler for raw-mode guest execution.
47	*
48	* @returns VBox status code (appropriate for trap handling and GC return).
49	* @param pVM VM Handle.
50	* @param uErr The trap error code.
51	* @param pRegFrame Trap register frame.
52	* @param pvFault The fault address.
53	*/
54	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
55	{
56	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
57
58	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
59	# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
60	# endif
61
62	# if PGM_SHW_TYPE == PGM_TYPE_PAE
63	/*
64	* Hide the instruction fetch trap indicator for now.
65	*/
66	/** @todo NXE will change this and we must fix NXE in the switcher too! */
67	if (uErr & X86_TRAP_PF_ID)
68	{
69	uErr &= ~X86_TRAP_PF_ID;
70	TRPMSetErrorCode(pVM, uErr);
71	}
72	# endif
73
74	/*
75	* Get PDs.
76	*/
77	int rc;
78	# if PGM_WITH_PAGING(PGM_GST_TYPE)
79	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
80	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
81	# else
82	PVBOXPD pPDSrc = NULL;
83	const unsigned iPDSrc = 0;
84	# endif
85
86	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
87	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
88	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
89	# else /* PAE */
90	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
91	# endif
92
93	# if PGM_WITH_PAGING(PGM_GST_TYPE)
94	/* Determine current privilege level */
95	uint32_t cpl = CPUMGetGuestCPL(pVM, pRegFrame);
96
97	# ifdef PGM_SYNC_DIRTY_BIT
98	/*
99	* If we successfully correct the write protection fault due to dirty bit
100	* tracking, or this page fault is a genuine one, then return immediately.
101	*/
102	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
103	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
104	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
105	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
106	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
107	{
108	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
109	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
110	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
111	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
112	}
113	# endif
114
115	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
116	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
117
118	/*
119	* A common case is the not-present error caused by lazy page table syncing.
120	*
121	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
122	* so we can safely assume that the shadow PT is present when calling SyncPage later.
123	*
124	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
125	* of mapping conflict and defer to SyncCR3 in R3.
126	* (Again, we do NOT support access handlers for non-present guest pages.)
127	*
128	*/
129	# if PGM_WITH_PAGING(PGM_GST_TYPE)
130	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
131	# else
132	VBOXPDE PdeSrc;
133	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
134	PdeSrc.n.u1Present = 1;
135	PdeSrc.n.u1Write = 1;
136	PdeSrc.n.u1Accessed = 1;
137	PdeSrc.n.u1User = 1;
138	# endif
139	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
140	&& !pPDDst->a[iPDDst].n.u1Present
141	&& PdeSrc.n.u1Present
142	)
143
144	{
145	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
146	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
147	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
148	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
149	if (VBOX_SUCCESS(rc))
150	{
151	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
152	return rc;
153	}
154	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
155	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
156	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
157	return VINF_PGM_SYNC_CR3;
158	}
159
160	# if PGM_WITH_PAGING(PGM_GST_TYPE)
161	/*
162	* Check if this address is within any of our mappings.
163	*
164	* This is very fast and it's gonna save us a bit of effort below and prevent
165	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
166	* (BTW, it's impossible to have physical access handlers in a mapping.)
167	*/
168	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
169	{
170	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
171	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
172	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
173	{
174	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
175	break;
176	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
177	{
178	/*
179	* The first thing we check is if we've got an undetected conflict.
180	*/
181	if (!pVM->pgm.s.fMappingsFixed)
182	{
183	unsigned iPT = pMapping->cPTs;
184	while (iPT-- > 0)
185	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
186	{
187	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
188	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
189	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
190	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
191	return VINF_PGM_SYNC_CR3;
192	}
193	}
194
195	/*
196	* Check if the fault address is in a virtual page access handler range.
197	*/
198	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
199	if ( pCur
200	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
201	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
202	&& ( uErr & X86_TRAP_PF_RW
203	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
204	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** r=bird: <- this is probably wrong. */
205	{
206	# ifdef IN_GC
207	STAM_PROFILE_START(&pCur->Stat, h);
208	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
209	STAM_PROFILE_STOP(&pCur->Stat, h);
210	# else
211	AssertFailed();
212	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
213	# endif
214	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
215	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
216	return rc;
217	}
218
219	/*
220	* Check if the EIP is in a virtual page access handler range.
221	*/
222	if (cpl == 0)
223	{
224	RTGCPTR pvEIP;
225	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
226	if (VBOX_SUCCESS(rc))
227	{
228	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
229	if ( pCur
230	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
231	&& (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
232	{
233	# ifdef IN_GC
234	STAM_PROFILE_START(&pCur->Stat, h);
235	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
236	STAM_PROFILE_STOP(&pCur->Stat, h);
237	# else
238	AssertFailed();
239	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
240	# endif
241	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
242	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
243	return rc;
244	}
245	}
246	}
247
248	/*
249	* Pretend we're not here and let the guest handle the trap.
250	*/
251	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
252	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
253	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
254	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
255	return VINF_EM_RAW_GUEST_TRAP;
256	}
257	}
258	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
259	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
260	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
261
262	/*
263	* Check if this fault address is flagged for special treatment,
264	* which means we'll have to figure out the physical address and
265	* check flags associated with it.
266	*
267	* ASSUME that we can limit any special access handling to pages
268	* in page tables which the guest believes to be present.
269	*/
270	if (PdeSrc.n.u1Present)
271	{
272	RTGCPHYS GCPhys = ~0U;
273
274	# if PGM_WITH_PAGING(PGM_GST_TYPE)
275	uint32_t cr4 = CPUMGetGuestCR4(pVM);
276	if ( PdeSrc.b.u1Size
277	&& (cr4 & X86_CR4_PSE))
278	GCPhys = (PdeSrc.u & X86_PDE4M_PG_MASK)
279	\| ((RTGCPHYS)pvFault & (PAGE_OFFSET_MASK_BIG ^ PAGE_OFFSET_MASK));
280	else
281	{
282	PVBOXPT pPTSrc;
283	# ifdef IN_GC
284	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & X86_PDE_PG_MASK, (void **)&pPTSrc);
285	# else
286	pPTSrc = (PVBOXPT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & X86_PDE_PG_MASK, sizeof(*pPTSrc));
287	if (pPTSrc == 0)
288	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
289	# endif
290	if (VBOX_SUCCESS(rc))
291	{
292	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & PTE_MASK;
293	if (pPTSrc->a[iPTESrc].n.u1Present)
294	GCPhys = pPTSrc->a[iPTESrc].u & X86_PTE_PG_MASK;
295	}
296	}
297	# else
298	/* No paging so the fault address is the physical address */
299	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
300	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
301
302	/*
303	* If we have a GC address we'll check if it has any flags set.
304	*/
305	if (GCPhys != ~0U)
306	{
307	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
308
309	RTHCPHYS HCPhys;
310	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPhys);
311	if (VBOX_SUCCESS(rc))
312	{
313	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_HANDLER))
314	{
315	if (HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER)
316	{
317	/*
318	* Physical page access handler.
319	*/
320	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
321	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
322	if (pCur)
323	{
324	# ifdef PGM_SYNC_N_PAGES
325	/*
326	* If the region is write protected and we got a page not present fault, then sync
327	* the pages. If the fault was caused by a read, then restart the instruction.
328	* In case of write access continue to the GC write handler.
329	*
330	* ASSUMES that there is only one handler per page or that they have similar write properties.
331	*/
332	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
333	&& !(uErr & X86_TRAP_PF_P))
334	{
335	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
336	if ( VBOX_FAILURE(rc)
337	\|\| !(uErr & X86_TRAP_PF_RW)
338	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
339	{
340	AssertRC(rc);
341	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
342	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
343	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
344	return rc;
345	}
346	}
347	# endif
348
349	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
350	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
351	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
352
353	#if defined(IN_GC) \|\| defined(IN_RING0)
354	if (CTXALLSUFF(pCur->pfnHandler))
355	{
356	STAM_PROFILE_START(&pCur->Stat, h);
357	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
358	STAM_PROFILE_STOP(&pCur->Stat, h);
359	}
360	else
361	#endif
362	rc = VINF_EM_RAW_EMULATE_INSTR;
363	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
364	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
365	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
366	return rc;
367	}
368	}
369	# if PGM_WITH_PAGING(PGM_GST_TYPE)
370	else
371	{
372	# ifdef PGM_SYNC_N_PAGES
373	/*
374	* If the region is write protected and we got a page not present fault, then sync
375	* the pages. If the fault was caused by a read, then restart the instruction.
376	* In case of write access continue to the GC write handler.
377	*/
378	if ( (HCPhys & (MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL)) == MM_RAM_FLAGS_VIRTUAL_WRITE
379	&& !(uErr & X86_TRAP_PF_P))
380	{
381	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
382	if ( VBOX_FAILURE(rc)
383	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
384	\|\| !(uErr & X86_TRAP_PF_RW))
385	{
386	AssertRC(rc);
387	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
388	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
389	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
390	return rc;
391	}
392	}
393	# endif
394	/*
395	* Ok, it's an virtual page access handler.
396	*
397	* Since it's faster to search by address, we'll do that first
398	* and then retry by GCPhys if that fails.
399	*/
400	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
401	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
402	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
403	*/
404	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
405	if (pCur)
406	{
407	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
408	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
409	\|\| !(uErr & X86_TRAP_PF_P)
410	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
411	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
412
413	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
414	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
415	&& ( uErr & X86_TRAP_PF_RW
416	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
417	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
418	{
419	# ifdef IN_GC
420	STAM_PROFILE_START(&pCur->Stat, h);
421	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
422	STAM_PROFILE_STOP(&pCur->Stat, h);
423	# else
424	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
425	# endif
426	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
427	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
428	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
429	return rc;
430	}
431	/* Unhandled part of a monitored page */
432	}
433	else
434	{
435	/* Check by physical address. */
436	PPGMVIRTHANDLER pCur;
437	unsigned iPage;
438	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
439	&pCur, &iPage);
440	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
441	if ( pCur
442	&& pCur->enmType != PGMVIRTHANDLERTYPE_EIP
443	&& ( uErr & X86_TRAP_PF_RW
444	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
445	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) )
446	{
447	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
448	# ifdef IN_GC
449	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
450	Assert(off < pCur->cb);
451	STAM_PROFILE_START(&pCur->Stat, h);
452	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
453	STAM_PROFILE_STOP(&pCur->Stat, h);
454	# else
455	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
456	# endif
457	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
458	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
459	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
460	return rc;
461	}
462	}
463	}
464	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
465
466	/*
467	* There is a handled area of the page, but this fault doesn't belong to it.
468	* We must emulate the instruction.
469	*
470	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
471	* we first check if this was a page-not-present fault for a page with only
472	* write access handlers. Restart the instruction if it wasn't a write access.
473	*/
474	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
475
476	if ( !(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL))
477	&& !(uErr & X86_TRAP_PF_P))
478	{
479	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
480	if ( VBOX_FAILURE(rc)
481	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
482	\|\| !(uErr & X86_TRAP_PF_RW))
483	{
484	AssertRC(rc);
485	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
486	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
487	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
488	return rc;
489	}
490	}
491
492	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
493	* It's writing to an unhandled part of the LDT page several million times.
494	*/
495	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
496	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%VHp%s%s\n",
497	rc, HCPhys, HCPhys & MM_RAM_FLAGS_PHYSICAL_HANDLER ? " phys" : "",
498	HCPhys & MM_RAM_FLAGS_VIRTUAL_HANDLER ? " virt" : ""));
499	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
500	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
501	return rc;
502	} /* if any kind of handler */
503
504	# if PGM_WITH_PAGING(PGM_GST_TYPE)
505	if (uErr & X86_TRAP_PF_P)
506	{
507	/*
508	* The page isn't marked, but it might still be monitored by a virtual page access handler.
509	* (ASSUMES no temporary disabling of virtual handlers.)
510	*/
511	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
512	* we should correct both the shadow page table and physical memory flags, and not only check for
513	* accesses within the handler region but for access to pages with virtual handlers. */
514	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
515	if (pCur)
516	{
517	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
518	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
519	\|\| !(uErr & X86_TRAP_PF_P)
520	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
521	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, HCPhys, uErr, pCur->enmType));
522
523	if ( pCur->enmType != PGMVIRTHANDLERTYPE_EIP
524	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
525	&& ( uErr & X86_TRAP_PF_RW
526	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
527	&& pCur->enmType != PGMVIRTHANDLERTYPE_HYPERVISOR) ) ) /** @todo r=bird: _HYPERVISOR is impossible here because of mapping check. */
528	{
529	# ifdef IN_GC
530	STAM_PROFILE_START(&pCur->Stat, h);
531	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
532	STAM_PROFILE_STOP(&pCur->Stat, h);
533	# else
534	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
535	# endif
536	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
537	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
538	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
539	return rc;
540	}
541	}
542	}
543	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
544	}
545	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
546
547	# ifdef PGM_OUT_OF_SYNC_IN_GC
548	/*
549	* We are here only if page is present in Guest page tables and trap is not handled
550	* by our handlers.
551	* Check it for page out-of-sync situation.
552	*/
553	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
554
555	if (!(uErr & X86_TRAP_PF_P))
556	{
557	/*
558	* Page is not present in our page tables.
559	* Try to sync it!
560	* BTW, fPageShw is invalid in this branch!
561	*/
562	if (uErr & X86_TRAP_PF_US)
563	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
564	else /* supervisor */
565	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
566
567	# if defined(LOG_ENABLED) && !defined(IN_RING0)
568	RTGCPHYS GCPhys;
569	uint64_t fPageGst;
570	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
571	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
572	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
573	# endif /* LOG_ENABLED */
574
575	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
576	if (cpl == 0)
577	{
578	uint64_t fPageGst;
579	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
580	if ( VBOX_SUCCESS(rc)
581	&& !(fPageGst & X86_PTE_US))
582	{
583	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
584	if ( pvFault == (RTGCPTR)pRegFrame->eip
585	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
586	# ifdef CSAM_DETECT_NEW_CODE_PAGES
587	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
588	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
589	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
590	)
591	{
592	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
593	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
594	if (rc != VINF_SUCCESS)
595	{
596	/*
597	* CSAM needs to perform a job in ring 3.
598	*
599	* Sync the page before going to the host context; otherwise we'll end up in a loop if
600	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
601	*/
602	LogFlow(("CSAM ring 3 job\n"));
603	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
604	AssertRC(rc2);
605
606	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
607	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
608	return rc;
609	}
610	}
611	# ifdef CSAM_DETECT_NEW_CODE_PAGES
612	else
613	if ( uErr == X86_TRAP_PF_RW
614	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
615	&& pRegFrame->ecx < 0x10000
616	)
617	{
618	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
619	* to detect loading of new code pages.
620	*/
621
622	/*
623	* Decode the instruction.
624	*/
625	RTGCPTR PC;
626	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
627	if (rc == VINF_SUCCESS)
628	{
629	DISCPUSTATE Cpu;
630	uint32_t cbOp;
631	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
632
633	/* For now we'll restrict this to rep movsw/d instructions */
634	if ( rc == VINF_SUCCESS
635	&& Cpu.pCurInstr->opcode == OP_MOVSWD
636	&& (Cpu.prefix & PREFIX_REP))
637	{
638	CSAMMarkPossibleCodePage(pVM, pvFault);
639	}
640	}
641	}
642	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
643
644	/*
645	* Mark this page as safe.
646	*/
647	/** @todo not correct for pages that contain both code and data!! */
648	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
649	CSAMMarkPage(pVM, pvFault, true);
650	}
651	}
652	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
653	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
654	if (VBOX_SUCCESS(rc))
655	{
656	/* The page was successfully synced, return to the guest. */
657	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
658	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
659	return VINF_SUCCESS;
660	}
661	}
662	else
663	{
664	/*
665	* A side effect of not flushing global PDEs are out of sync pages due
666	* to physical monitored regions, that are no longer valid.
667	* Assume for now it only applies to the read/write flag
668	*/
669	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
670	{
671	if (uErr & X86_TRAP_PF_US)
672	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
673	else /* supervisor */
674	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
675
676
677	/*
678	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
679	*/
680	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
681	if (VBOX_SUCCESS(rc))
682	{
683	/*
684	* Page was successfully synced, return to guest.
685	*/
686	# ifdef VBOX_STRICT
687	RTGCPHYS GCPhys;
688	uint64_t fPageGst;
689	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
690	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
691	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
692
693	uint64_t fPageShw;
694	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
695	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
696	# endif /* VBOX_STRICT */
697	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
698	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
699	return VINF_SUCCESS;
700	}
701	}
702
703	# if PGM_WITH_PAGING(PGM_GST_TYPE)
704	# ifdef VBOX_STRICT
705	/*
706	* Check for VMM page flags vs. Guest page flags consistency.
707	* Currently only for debug purposes.
708	*/
709	if (VBOX_SUCCESS(rc))
710	{
711	/* Get guest page flags. */
712	uint64_t fPageGst;
713	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
714	if (VBOX_SUCCESS(rc))
715	{
716	uint64_t fPageShw;
717	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
718
719	/*
720	* Compare page flags.
721	* Note: we have AVL, A, D bits desynched.
722	*/
723	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
724	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
725	}
726	else
727	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
728	}
729	else
730	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
731	# endif /* VBOX_STRICT */
732	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
733	}
734	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
735	# endif /* PGM_OUT_OF_SYNC_IN_GC */
736	}
737	else
738	{
739	/*
740	* Page not present in Guest OS or invalid page table address.
741	* This is potential virtual page access handler food.
742	*
743	* For the present we'll say that our access handlers don't
744	* work for this case - we've already discarded the page table
745	* not present case which is identical to this.
746	*
747	* When we perchance find we need this, we will probably have AVL
748	* trees (offset based) to operate on and we can measure their speed
749	* agains mapping a page table and probably rearrange this handling
750	* a bit. (Like, searching virtual ranges before checking the
751	* physical address.)
752	*/
753	}
754	}
755
756
757	# if PGM_WITH_PAGING(PGM_GST_TYPE)
758	/*
759	* Check if it's in a EIP based virtual page access handler range.
760	* This is only used for supervisor pages in flat mode.
761	*/
762	/** @todo this stuff is completely broken by the out-of-sync stuff. since we don't use this stuff, that's not really a problem yet. */
763	STAM_PROFILE_START(&pVM->pgm.s.StatEIPHandlers, d);
764	if (cpl == 0)
765	{
766	RTGCPTR pvEIP;
767	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pvEIP);
768	if ( VBOX_SUCCESS(rc)
769	&& pvEIP == (RTGCPTR)pRegFrame->eip)
770	{
771	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvEIP);
772	if ( pCur
773	&& pCur->enmType == PGMVIRTHANDLERTYPE_EIP
774	&& (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
775	{
776	LogFlow(("EIP handler\n"));
777	# ifdef IN_GC
778	STAM_PROFILE_START(&pCur->Stat, h);
779	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvEIP - (RTGCUINTPTR)pCur->GCPtr);
780	STAM_PROFILE_STOP(&pCur->Stat, h);
781	# else
782	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
783	# endif
784	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
785	return rc;
786	}
787	}
788	}
789	STAM_PROFILE_STOP(&pVM->pgm.s.StatEIPHandlers, d);
790
791	/*
792	* Conclusion, this is a guest trap.
793	*/
794	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
795	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
796	return VINF_EM_RAW_GUEST_TRAP;
797	# else
798	/* present, but not a monitored page; perhaps the guest is probing physical memory */
799	return VINF_EM_RAW_EMULATE_INSTR;
800	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
801
802
803	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
804
805	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
806	return VERR_INTERNAL_ERROR;
807	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
808	}
809
810
811	/**
812	* Emulation of the invlpg instruction.
813	*
814	*
815	* @returns VBox status code.
816	*
817	* @param pVM VM handle.
818	* @param GCPtrPage Page to invalidate.
819	*
820	* @remark ASSUMES that the guest is updating before invalidating. This order
821	* isn't required by the CPU, so this is speculative and could cause
822	* trouble.
823	*
824	* @todo Flush page or page directory only if necessary!
825	* @todo Add a #define for simply invalidating the page.
826	*/
827	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
828	{
829	#if PGM_GST_TYPE == PGM_TYPE_32BIT
830
831	LogFlow(("InvalidatePage %x\n", GCPtrPage));
832	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
833	/*
834	* Get the shadow PD entry and skip out if this PD isn't present.
835	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
836	*/
837	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
838	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
839	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
840	# else
841	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
842	# endif
843	const SHWPDE PdeDst = *pPdeDst;
844	if (!PdeDst.n.u1Present)
845	{
846	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
847	return VINF_SUCCESS;
848	}
849
850	/*
851	* Get the guest PD entry and calc big page.
852	*/
853	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
854	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
855	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
856	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
857	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
858
859	# ifdef IN_RING3
860	/*
861	* If a CR3 Sync is pending we may ignore the invalidate page operation
862	* depending on the kind of sync and if it's a global page or not.
863	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
864	*/
865	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
866	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
867	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
868	&& fIsBigPage
869	&& PdeSrc.b.u1Global
870	&& (cr4 & X86_CR4_PGE)
871	)
872	)
873	# else
874	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
875	# endif
876	{
877	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
878	return VINF_SUCCESS;
879	}
880	# endif /* IN_RING3 */
881
882
883	/*
884	* Deal with the Guest PDE.
885	*/
886	int rc = VINF_SUCCESS;
887	if (PdeSrc.n.u1Present)
888	{
889	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
890	{
891	/*
892	* Conflict - Let SyncPT deal with it to avoid duplicate code.
893	*/
894	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
895	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
896	}
897	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
898	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
899	{
900	/*
901	* Mark not present so we can resync the PDE when it's used.
902	*/
903	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
904	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
905	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
906	pPdeDst->u = 0;
907	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
908	PGM_INVL_GUEST_TLBS();
909	}
910	# ifdef PGM_SYNC_ACCESSED_BIT
911	else if (!PdeSrc.n.u1Accessed)
912	{
913	/*
914	* Mark not present so we can set the accessed bit.
915	*/
916	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
917	pPdeDst->u = 0;
918	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
919	PGM_INVL_GUEST_TLBS();
920	}
921	# endif
922	else if (!fIsBigPage)
923	{
924	/*
925	* 4KB - page.
926	*/
927	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
928	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
929	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
930	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
931	# endif
932	if (pShwPage->GCPhys == GCPhys)
933	{
934	#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
935	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
936	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
937	if (pPT->a[iPTEDst].n.u1Present)
938	{
939	# ifdef PGMPOOL_WITH_USER_TRACKING
940	/* This is very unlikely with caching/monitoring enabled. */
941	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
942	# endif
943	pPT->a[iPTEDst].u = 0;
944	}
945	#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
946	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
947	if (VBOX_SUCCESS(rc))
948	rc = VINF_SUCCESS;
949	#endif
950	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
951	PGM_INVL_PG(GCPtrPage);
952	}
953	else
954	{
955	/*
956	* The page table address changed.
957	*/
958	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
959	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
960	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
961	pPdeDst->u = 0;
962	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
963	PGM_INVL_GUEST_TLBS();
964	}
965	}
966	else
967	{
968	/*
969	* 4MB - page.
970	*/
971	/* Before freeing the page, check if anything really changed. */
972	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
973	RTGCPHYS GCPhys = PdeSrc.u & X86_PDE4M_PG_MASK;
974	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
975	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
976	# endif
977	if ( pShwPage->GCPhys == GCPhys
978	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
979	{
980	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
981	/** @todo PAT */
982	# ifdef PGM_SYNC_DIRTY_BIT
983	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
984	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
985	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
986	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
987	# else
988	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
989	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
990	# endif
991	{
992	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
993	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
994	return VINF_SUCCESS;
995	}
996	}
997
998	/*
999	* Ok, the page table is present and it's been changed in the guest.
1000	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1001	* We could do this for some flushes in GC too, but we need an algorithm for
1002	* deciding which 4MB pages containing code likely to be executed very soon.
1003	*/
1004	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1005	pPdeDst->u = 0;
1006	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1007	DUMP_PDE_BIG("PGMInvalidatePage", iPDSrc, PdeSrc);
1008	PGM_INVL_BIG_PG(GCPtrPage);
1009	}
1010	}
1011	else
1012	{
1013	/*
1014	* Page directory is not present, mark shadow PDE not present.
1015	*/
1016	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1017	{
1018	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1019	pPdeDst->u = 0;
1020	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1021	PGM_INVL_PG(GCPtrPage);
1022	}
1023	else
1024	{
1025	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1026	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1027	}
1028	}
1029
1030	return rc;
1031
1032	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1033	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
1034	# endif
1035	return VINF_SUCCESS;
1036
1037	#elif PGM_GST_TYPE == PGM_TYPE_PAE
1038	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1039	//# error not implemented
1040	return VERR_INTERNAL_ERROR;
1041
1042	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1043	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
1044	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1045
1046	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1047	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1048	//# error not implemented
1049	return VERR_INTERNAL_ERROR;
1050
1051	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1052	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
1053	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
1054
1055	#else /* guest real and protected mode */
1056	/* There's no such thing when paging is disabled. */
1057	return VINF_SUCCESS;
1058	#endif
1059	}
1060
1061
1062	#ifdef PGMPOOL_WITH_USER_TRACKING
1063	/**
1064	* Update the tracking of shadowed pages.
1065	*
1066	* @param pVM The VM handle.
1067	* @param pShwPage The shadow page.
1068	* @param HCPhys The physical page we is being dereferenced.
1069	*/
1070	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1071	{
1072	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1073	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1074	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1075
1076	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1077	* 1. have a medium sized HCPhys -> GCPhys cache (hash?)
1078	* 2. write protect all shadowed pages. I.e. implement caching.
1079	*/
1080	/*
1081	* Find the guest address.
1082	*/
1083	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTXSUFF(pRamRanges);
1084	pRam;
1085	pRam = pRam->CTXSUFF(pNext))
1086	{
1087	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1088	while (iPage-- > 0)
1089	{
1090	if ((pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) == HCPhys)
1091	{
1092	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1093	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aHCPhys[iPage]);
1094	pShwPage->cPresent--;
1095	pPool->cPresent--;
1096	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1097	return;
1098	}
1099	}
1100	}
1101
1102	for (;;)
1103	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1104	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1105	pShwPage->cPresent--;
1106	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1107	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1108	}
1109
1110
1111	/**
1112	* Update the tracking of shadowed pages.
1113	*
1114	* @param pVM The VM handle.
1115	* @param pShwPage The shadow page.
1116	* @param u16 The top 16-bit of the *pHCPhys.
1117	* @param pHCPhys Pointer to the ram range physical page entry.
1118	* @param iPTDst The index into the shadow table.
1119	*/
1120	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PRTHCPHYS pHCPhys, const unsigned iPTDst)
1121	{
1122	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1123	/*
1124	* We're making certain assumptions about the placement of cRef and idx.
1125	*/
1126	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1127	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1128
1129	/*
1130	* Just deal with the simple first time here.
1131	*/
1132	if (!u16)
1133	{
1134	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1135	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1136	}
1137	else
1138	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1139
1140	/* write back, trying to be clever... */
1141	Log2(("SyncPageWorkerTrackAddRef: u16=%#x *pHCPhys=%VHp->%VHp iPTDst=%#x\n",
1142	u16, pHCPhys, (pHCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1143	((uint16_t )pHCPhys + 3) = u16;
1144	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1145
1146	/* update statistics. */
1147	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1148	pShwPage->cPresent++;
1149	if (pShwPage->iFirstPresent > iPTDst)
1150	pShwPage->iFirstPresent = iPTDst;
1151	}
1152	#endif /* PGMPOOL_WITH_USER_TRACKING */
1153
1154
1155	/**
1156	* Creates a 4K shadow page for a guest page.
1157	*
1158	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1159	* physical address. The PdeSrc argument only the flags are used. No page structured
1160	* will be mapped in this function.
1161	*
1162	* @param pVM VM handle.
1163	* @param pPteDst Destination page table entry.
1164	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1165	* Can safely assume that only the flags are being used.
1166	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1167	* @param pShwPage Pointer to the shadow page.
1168	* @param iPTDst The index into the shadow table.
1169	*
1170	* @remark Not used for 2/4MB pages!
1171	*/
1172	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, VBOXPDE PdeSrc, VBOXPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1173	{
1174	if (PteSrc.n.u1Present)
1175	{
1176	/*
1177	* Find the ram range.
1178	*/
1179	PRTHCPHYS pHCPhys;
1180	int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, PteSrc.u & X86_PTE_PG_MASK, &pHCPhys);
1181	if (VBOX_SUCCESS(rc))
1182	{
1183	/** @todo investiage PWT, PCD and PAT. */
1184	/*
1185	* Make page table entry.
1186	*/
1187	const RTHCPHYS HCPhys = *pHCPhys;
1188	SHWPTE PteDst;
1189	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1190	{
1191	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1192	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1193	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1194	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1195	else
1196	PteDst.u = 0;
1197	/** @todo count these two kinds. */
1198	}
1199	else
1200	{
1201	#ifdef PGM_SYNC_DIRTY_BIT
1202	# ifdef PGM_SYNC_ACCESSED_BIT
1203	/*
1204	* If the page or page directory entry is not marked accessed,
1205	* we mark the page not present.
1206	*/
1207	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1208	{
1209	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1210	PteDst.u = 0;
1211	}
1212	else
1213	# endif
1214	/*
1215	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1216	* when the page is modified.
1217	*/
1218	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1219	{
1220	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1221	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1222	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1223	\| PGM_PTFLAGS_TRACK_DIRTY;
1224	}
1225	else
1226	{
1227	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1228	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1229	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1230	}
1231	#endif
1232	}
1233
1234	#ifdef PGMPOOL_WITH_USER_TRACKING
1235	/*
1236	* Keep user track up to date.
1237	*/
1238	if (PteDst.n.u1Present)
1239	{
1240	if (!pPteDst->n.u1Present)
1241	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1242	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1243	{
1244	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1245	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1246	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1247	}
1248	}
1249	else if (pPteDst->n.u1Present)
1250	{
1251	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1252	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1253	}
1254	#endif /* PGMPOOL_WITH_USER_TRACKING */
1255
1256	/*
1257	* Update statistics and commit the entry.
1258	*/
1259	if (!PteSrc.n.u1Global)
1260	pShwPage->fSeenNonGlobal = true;
1261	*pPteDst = PteDst;
1262	}
1263	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1264	/** @todo count these. */
1265	}
1266	else
1267	{
1268	/*
1269	* Page not-present.
1270	*/
1271	#ifdef PGMPOOL_WITH_USER_TRACKING
1272	/* Keep user track up to date. */
1273	if (pPteDst->n.u1Present)
1274	{
1275	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1276	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1277	}
1278	#endif /* PGMPOOL_WITH_USER_TRACKING */
1279	pPteDst->u = 0;
1280	/** @todo count these. */
1281	}
1282	}
1283
1284
1285	/**
1286	* Syncs a guest OS page.
1287	*
1288	* There are no conflicts at this point, neither is there any need for
1289	* page table allocations.
1290	*
1291	* @returns VBox status code.
1292	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1293	* @param pVM VM handle.
1294	* @param PdeSrc Page directory entry of the guest.
1295	* @param GCPtrPage Guest context page address.
1296	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1297	* @param uErr Fault error (X86_TRAP_PF_*).
1298	*/
1299	PGM_BTH_DECL(int, SyncPage)(PVM pVM, VBOXPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1300	{
1301	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1302
1303	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1304
1305	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1306	# error "Invalid shadow mode for 32-bit guest mode!"
1307	# endif
1308
1309	/*
1310	* Assert preconditions.
1311	*/
1312	# if GC_ARCH_BITS != 32
1313	Assert(GCPtrPage < _4G); //???
1314	# endif
1315	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & X86_PD_MASK]);
1316	Assert(PdeSrc.n.u1Present);
1317	Assert(cPages);
1318
1319	/*
1320	* Get the shadow PDE, find the shadow page table in the pool.
1321	*/
1322	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1323	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1324	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1325	# else /* PAE */
1326	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1327	# endif
1328	Assert(PdeDst.n.u1Present);
1329	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1330
1331	/*
1332	* Check that the page is present and that the shadow PDE isn't out of sync.
1333	*/
1334	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1335	RTGCPHYS GCPhys;
1336	if (!fBigPage)
1337	{
1338	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1339	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1340	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1341	# endif
1342	}
1343	else
1344	{
1345	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1346	# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1347	GCPhys \|= GCPtrPage & X86_PAGE_2M_SIZE;
1348	# endif
1349	}
1350	if ( pShwPage->GCPhys == GCPhys
1351	&& PdeSrc.n.u1Present
1352	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1353	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1354	)
1355	{
1356	# ifdef PGM_SYNC_ACCESSED_BIT
1357	/*
1358	* Check that the PDE is marked accessed already.
1359	* Since we set the accessed bit before getting here on a #PF, this
1360	* check is only meant for dealing with non-#PF'ing paths.
1361	*/
1362	if (PdeSrc.n.u1Accessed)
1363	# endif
1364	{
1365	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1366	if (!fBigPage)
1367	{
1368	/*
1369	* 4KB Page - Map the guest page table.
1370	*/
1371	PVBOXPT pPTSrc;
1372	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & X86_PDE_PG_MASK, &pPTSrc);
1373	if (VBOX_SUCCESS(rc))
1374	{
1375	# ifdef PGM_SYNC_N_PAGES
1376	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1377	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1378	{
1379	/*
1380	* This code path is currently only taken when the caller is PGMTrap0eHandler
1381	* for non-present pages!
1382	*
1383	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1384	* deal with locality.
1385	*/
1386	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1387	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1388	const unsigned offPTSrc = 0;
1389	# else
1390	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1391	# endif
1392	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1393	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1394	iPTDst = 0;
1395	else
1396	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1397	for (; iPTDst < iPTDstEnd; iPTDst++)
1398	{
1399	if (!pPTDst->a[iPTDst].n.u1Present)
1400	{
1401	VBOXPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1402	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1403	NOREF(GCPtrCurPage);
1404	#ifndef IN_RING0
1405	/*
1406	* Assuming kernel code will be marked as supervisor - and not as user level
1407	* and executed using a conforming code selector - And marked as readonly.
1408	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1409	*/
1410	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1411	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1412	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1413	\|\| PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
1414	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
1415	)
1416	#endif
1417	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1418	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1419	GCPtrCurPage, PteSrc.n.u1Present,
1420	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1421	PteSrc.n.u1User & PdeSrc.n.u1User,
1422	(uint64_t)PteSrc.u,
1423	(uint64_t)pPTDst->a[iPTDst].u,
1424	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1425	}
1426	}
1427	}
1428	else
1429	# endif /* PGM_SYNC_N_PAGES */
1430	{
1431	const unsigned iPTSrc = (GCPtrPage >> X86_PT_SHIFT) & X86_PT_MASK;
1432	VBOXPTE PteSrc = pPTSrc->a[iPTSrc];
1433	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1434	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1435	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1436	GCPtrPage, PteSrc.n.u1Present,
1437	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1438	PteSrc.n.u1User & PdeSrc.n.u1User,
1439	(uint64_t)PteSrc.u,
1440	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1441	}
1442	}
1443	else /* MMIO or invalid page: emulated in #PF handler. */
1444	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1445	}
1446	else
1447	{
1448	/*
1449	* 4/2MB page - lazy syncing shadow 4K pages.
1450	* (There are many causes of getting here, it's no longer only CSAM.)
1451	*/
1452	/* Calculate the GC physical address of this 4KB shadow page. */
1453	RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PAE_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & PAGE_OFFSET_MASK_BIG);
1454	/* Find ram range. */
1455	PRTHCPHYS pHCPhys;
1456	int rc = PGMRamGCPhys2PagePtr(&pVM->pgm.s, GCPhys, &pHCPhys);
1457	if (VBOX_SUCCESS(rc))
1458	{
1459	/*
1460	* Make shadow PTE entry.
1461	*/
1462	RTHCPHYS HCPhys = *pHCPhys;
1463	SHWPTE PteDst;
1464	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1465	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1466	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
1467	{
1468	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
1469	PteDst.n.u1Write = 0;
1470	else
1471	PteDst.u = 0;
1472	}
1473	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1474	# ifdef PGMPOOL_WITH_USER_TRACKING
1475	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1476	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pHCPhys, iPTDst);
1477	# endif
1478	pPTDst->a[iPTDst] = PteDst;
1479
1480
1481	# ifdef PGM_SYNC_DIRTY_BIT
1482	/*
1483	* If the page is not flagged as dirty and is writable, then make it read-only
1484	* at PD level, so we can set the dirty bit when the page is modified.
1485	*
1486	* ASSUMES that page access handlers are implemented on page table entry level.
1487	* Thus we will first catch the dirty access and set PDE.D and restart. If
1488	* there is an access handler, we'll trap again and let it work on the problem.
1489	*/
1490	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1491	* As for invlpg, it simply frees the whole shadow PT.
1492	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1493	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1494	{
1495	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1496	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1497	PdeDst.n.u1Write = 0;
1498	}
1499	else
1500	{
1501	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1502	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1503	}
1504	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1505	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1506	# else /* PAE */
1507	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1508	# endif
1509	# endif /* PGM_SYNC_DIRTY_BIT */
1510	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1511	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1512	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1513	}
1514	}
1515	return VINF_SUCCESS;
1516	}
1517	# ifdef PGM_SYNC_ACCESSED_BIT
1518	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1519	#endif
1520	}
1521	else
1522	{
1523	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1524	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1525	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1526	}
1527
1528	/*
1529	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1530	* Yea, I'm lazy.
1531	*/
1532	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1533	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1534	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1535	# else /* PAE */
1536	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1537	# endif
1538	PGM_INVL_GUEST_TLBS();
1539	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1540
1541	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1542
1543	# ifdef PGM_SYNC_N_PAGES
1544	/*
1545	* Get the shadow PDE, find the shadow page table in the pool.
1546	*/
1547	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1548	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1549	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1550	# else /* PAE */
1551	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1552	# endif
1553	Assert(PdeDst.n.u1Present);
1554	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1555	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1556
1557	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1558	const unsigned offPTSrc = 0;
1559	# else
1560	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1561	# endif
1562
1563	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1564	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1565	{
1566	/*
1567	* This code path is currently only taken when the caller is PGMTrap0eHandler
1568	* for non-present pages!
1569	*
1570	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1571	* deal with locality.
1572	*/
1573	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1574	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1575	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1576	iPTDst = 0;
1577	else
1578	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1579	for (; iPTDst < iPTDstEnd; iPTDst++)
1580	{
1581	if (!pPTDst->a[iPTDst].n.u1Present)
1582	{
1583	VBOXPTE PteSrc;
1584
1585	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1586
1587	/* Fake the page table entry */
1588	PteSrc.u = GCPtrCurPage;
1589	PteSrc.n.u1Present = 1;
1590	PteSrc.n.u1Dirty = 1;
1591	PteSrc.n.u1Accessed = 1;
1592	PteSrc.n.u1Write = 1;
1593	PteSrc.n.u1User = 1;
1594
1595	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1596
1597	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1598	GCPtrCurPage, PteSrc.n.u1Present,
1599	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1600	PteSrc.n.u1User & PdeSrc.n.u1User,
1601	(uint64_t)PteSrc.u,
1602	(uint64_t)pPTDst->a[iPTDst].u,
1603	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1604	}
1605	}
1606	}
1607	else
1608	# endif /* PGM_SYNC_N_PAGES */
1609	{
1610	VBOXPTE PteSrc;
1611	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1612	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(X86_PT_MASK << X86_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1613
1614	/* Fake the page table entry */
1615	PteSrc.u = GCPtrCurPage;
1616	PteSrc.n.u1Present = 1;
1617	PteSrc.n.u1Dirty = 1;
1618	PteSrc.n.u1Accessed = 1;
1619	PteSrc.n.u1Write = 1;
1620	PteSrc.n.u1User = 1;
1621	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1622
1623	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1624	GCPtrPage, PteSrc.n.u1Present,
1625	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1626	PteSrc.n.u1User & PdeSrc.n.u1User,
1627	(uint64_t)PteSrc.u,
1628	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1629	}
1630	return VINF_SUCCESS;
1631
1632	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1633	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1634	return VERR_INTERNAL_ERROR;
1635	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1636	}
1637
1638
1639
1640	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1641
1642	# ifdef PGM_SYNC_DIRTY_BIT
1643
1644	/**
1645	* Investigate page fault and handle write protection page faults caused by
1646	* dirty bit tracking.
1647	*
1648	* @returns VBox status code.
1649	* @param pVM VM handle.
1650	* @param uErr Page fault error code.
1651	* @param pPdeDst Shadow page directory entry.
1652	* @param pPdeSrc Guest page directory entry.
1653	* @param GCPtrPage Guest context page address.
1654	*/
1655	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PVBOXPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1656	{
1657	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1658	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1659
1660	/*
1661	* Real page fault?
1662	*/
1663	if ( (uErr & X86_TRAP_PF_RSVD)
1664	\|\| !pPdeSrc->n.u1Present
1665	\|\| ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1666	\|\| ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1667	{
1668	# ifdef IN_GC
1669	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1670	# endif
1671	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1672	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1673
1674	if (pPdeSrc->n.u1Present)
1675	{
1676	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1677	* See the 2nd case below as well.
1678	*/
1679	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1680	{
1681	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1682	}
1683	else
1684	{
1685	/*
1686	* Map the guest page table.
1687	*/
1688	PVBOXPT pPTSrc;
1689	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1690	if (VBOX_SUCCESS(rc))
1691	{
1692	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1693	const VBOXPTE PteSrc = *pPteSrc;
1694	if (pPteSrc->n.u1Present)
1695	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1696	}
1697	AssertRC(rc);
1698	}
1699	}
1700	return VINF_EM_RAW_GUEST_TRAP;
1701	}
1702
1703	/*
1704	* First check the easy case where the page directory has been marked read-only to track
1705	* the dirty bit of an emulated BIG page
1706	*/
1707	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1708	{
1709	/* Mark guest page directory as accessed */
1710	pPdeSrc->b.u1Accessed = 1;
1711
1712	/*
1713	* Only write protection page faults are relevant here.
1714	*/
1715	if (uErr & X86_TRAP_PF_RW)
1716	{
1717	/* Mark guest page directory as dirty (BIG page only). */
1718	pPdeSrc->b.u1Dirty = 1;
1719
1720	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1721	{
1722	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1723
1724	Assert(pPdeSrc->b.u1Write);
1725
1726	pPdeDst->n.u1Write = 1;
1727	pPdeDst->n.u1Accessed = 1;
1728	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1729	PGM_INVL_BIG_PG(GCPtrPage);
1730	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1731	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1732	}
1733	}
1734	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1735	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1736	}
1737	/* else: 4KB page table */
1738
1739	/*
1740	* Map the guest page table.
1741	*/
1742	PVBOXPT pPTSrc;
1743	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & X86_PDE_PG_MASK, &pPTSrc);
1744	if (VBOX_SUCCESS(rc))
1745	{
1746	/*
1747	* Real page fault?
1748	*/
1749	PVBOXPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & PTE_MASK];
1750	const VBOXPTE PteSrc = *pPteSrc;
1751	if ( !PteSrc.n.u1Present
1752	\|\| ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1753	\|\| ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1754	)
1755	{
1756	# ifdef IN_GC
1757	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1758	# endif
1759	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1760	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1761
1762	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1763	* See the 2nd case above as well.
1764	*/
1765	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1766	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1767
1768	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1769	return VINF_EM_RAW_GUEST_TRAP;
1770	}
1771	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1772
1773	/*
1774	* Set the accessed bits in the page directory and the page table.
1775	*/
1776	pPdeSrc->n.u1Accessed = 1;
1777	pPteSrc->n.u1Accessed = 1;
1778
1779	/*
1780	* Only write protection page faults are relevant here.
1781	*/
1782	if (uErr & X86_TRAP_PF_RW)
1783	{
1784	/* Write access, so mark guest entry as dirty. */
1785	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1786	if (!pPteSrc->n.u1Dirty)
1787	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1788	else
1789	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1790	# endif
1791	pPteSrc->n.u1Dirty = 1;
1792
1793	if (pPdeDst->n.u1Present)
1794	{
1795	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1796	* Our individual shadow handlers will provide more information and force a fatal exit.
1797	*/
1798	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1799	{
1800	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1801	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1802	return VINF_SUCCESS;
1803	}
1804
1805	/*
1806	* Map shadow page table.
1807	*/
1808	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1809	if (pShwPage)
1810	{
1811	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1812	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1813	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1814	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1815	{
1816	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1817	# ifdef VBOX_STRICT
1818	RTHCPHYS HCPhys;
1819	rc = PGMRamGCPhys2HCPhysWithFlags(&pVM->pgm.s, pPteSrc->u & X86_PTE_PG_MASK, &HCPhys);
1820	if (VBOX_SUCCESS(rc))
1821	AssertMsg(!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)),
1822	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1823	# endif
1824	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1825
1826	Assert(pPteSrc->n.u1Write);
1827
1828	pPteDst->n.u1Write = 1;
1829	pPteDst->n.u1Dirty = 1;
1830	pPteDst->n.u1Accessed = 1;
1831	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1832	PGM_INVL_PG(GCPtrPage);
1833
1834	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1835	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1836	}
1837	}
1838	else
1839	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1840	}
1841	}
1842	/** @todo Optimize accessed bit emulation? */
1843	# ifdef VBOX_STRICT
1844	/*
1845	* Sanity check.
1846	*/
1847	else if ( !pPteSrc->n.u1Dirty
1848	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1849	&& pPdeDst->n.u1Present)
1850	{
1851	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1852	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1853	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1854	if ( pPteDst->n.u1Present
1855	&& pPteDst->n.u1Write)
1856	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1857	}
1858	# endif /* VBOX_STRICT */
1859	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1860	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1861	}
1862	AssertRC(rc);
1863	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1864	return rc;
1865	}
1866
1867	# endif
1868
1869	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1870
1871
1872	/**
1873	* Sync a shadow page table.
1874	*
1875	* The shadow page table is not present. This includes the case where
1876	* there is a conflict with a mapping.
1877	*
1878	* @returns VBox status code.
1879	* @param pVM VM handle.
1880	* @param iPD Page directory index.
1881	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1882	* Assume this is a temporary mapping.
1883	* @param GCPtrPage GC Pointer of the page that caused the fault
1884	*/
1885	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PVBOXPD pPDSrc, RTGCUINTPTR GCPtrPage)
1886	{
1887	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1888	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1889	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1890
1891	#if PGM_GST_TYPE == PGM_TYPE_32BIT
1892
1893	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1894	# error "Invalid shadow mode for 32-bit guest mode!"
1895	# endif
1896
1897	/*
1898	* Validate input a little bit.
1899	*/
1900	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1901	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1902	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1903	# else
1904	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1905	# endif
1906	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1907	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1908	SHWPDE PdeDst = *pPdeDst;
1909
1910	/*
1911	* Check for conflicts.
1912	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1913	* HC: Simply resolve the conflict.
1914	*/
1915	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1916	{
1917	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1918	# ifndef IN_RING3
1919	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1920	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1921	return VERR_ADDRESS_CONFLICT;
1922	# else
1923	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1924	Assert(pMapping);
1925	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1926	if (VBOX_FAILURE(rc))
1927	{
1928	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1929	return rc;
1930	}
1931	PdeDst = *pPdeDst;
1932	# endif
1933	}
1934	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1935
1936	/*
1937	* Sync page directory entry.
1938	*/
1939	int rc = VINF_SUCCESS;
1940	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1941	if (PdeSrc.n.u1Present)
1942	{
1943	/*
1944	* Allocate & map the page table.
1945	*/
1946	PSHWPT pPTDst;
1947	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1948	PPGMPOOLPAGE pShwPage;
1949	RTGCPHYS GCPhys;
1950	if (fPageTable)
1951	{
1952	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1953	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1954	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1955	# endif
1956	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1957	}
1958	else
1959	{
1960	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
1961	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1962	GCPhys \|= GCPtrPage & BIT(X86_PAGE_2M_SHIFT);
1963	# endif
1964	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1965	}
1966	if (rc == VINF_SUCCESS)
1967	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1968	else if (rc == VINF_PGM_CACHED_PAGE)
1969	{
1970	/*
1971	* The PT was cached, just hook it up.
1972	*/
1973	if (fPageTable)
1974	PdeDst.u = pShwPage->Core.Key
1975	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1976	else
1977	{
1978	PdeDst.u = pShwPage->Core.Key
1979	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1980	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1981	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1982	{
1983	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1984	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1985	PdeDst.b.u1Write = 0;
1986	}
1987	# endif
1988	}
1989	*pPdeDst = PdeDst;
1990	return VINF_SUCCESS;
1991	}
1992	else if (rc == VERR_PGM_POOL_FLUSHED)
1993	return VINF_PGM_SYNC_CR3;
1994	else
1995	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1996	PdeDst.u &= X86_PDE_AVL_MASK;
1997	PdeDst.u \|= pShwPage->Core.Key;
1998
1999	# ifdef PGM_SYNC_DIRTY_BIT
2000	/*
2001	* Page directory has been accessed (this is a fault situation, remember).
2002	*/
2003	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2004	# endif
2005	if (fPageTable)
2006	{
2007	/*
2008	* Page table - 4KB.
2009	*
2010	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2011	*/
2012	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2013	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2014	PGSTPT pPTSrc;
2015	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2016	if (VBOX_SUCCESS(rc))
2017	{
2018	/*
2019	* Start by syncing the page directory entry so CSAM's TLB trick works.
2020	*/
2021	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK))
2022	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2023	*pPdeDst = PdeDst;
2024
2025	/*
2026	* Directory/page user or supervisor privilege: (same goes for read/write)
2027	*
2028	* Directory Page Combined
2029	* U/S U/S U/S
2030	* 0 0 0
2031	* 0 1 0
2032	* 1 0 0
2033	* 1 1 1
2034	*
2035	* Simple AND operation. Table listed for completeness.
2036	*
2037	*/
2038	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2039	# ifdef PGM_SYNC_N_PAGES
2040	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2041	unsigned iPTDst = iPTBase;
2042	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2043	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2044	iPTDst = 0;
2045	else
2046	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2047	# else /* !PGM_SYNC_N_PAGES */
2048	unsigned iPTDst = 0;
2049	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2050	# endif /* !PGM_SYNC_N_PAGES */
2051	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2052	const unsigned offPTSrc = 0;
2053	# else
2054	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2055	# endif
2056	for (; iPTDst < iPTDstEnd; iPTDst++)
2057	{
2058	const unsigned iPTSrc = iPTDst + offPTSrc;
2059	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2060
2061	if (PteSrc.n.u1Present) /* we've already cleared it above */
2062	{
2063	#ifndef IN_RING0
2064	/*
2065	* Assuming kernel code will be marked as supervisor - and not as user level
2066	* and executed using a conforming code selector - And marked as readonly.
2067	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2068	*/
2069	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2070	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2071	\|\| PGMRamTestFlags(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK,
2072	MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE)
2073	)
2074	#endif
2075	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2076	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2077	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2078	PteSrc.n.u1Present,
2079	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2080	PteSrc.n.u1User & PdeSrc.n.u1User,
2081	(uint64_t)PteSrc.u,
2082	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2083	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2084	}
2085	} /* for PTEs */
2086	}
2087	}
2088	else
2089	{
2090	/*
2091	* Big page - 2/4MB.
2092	*
2093	* We'll walk the ram range list in parallel and optimize lookups.
2094	* We will only sync on shadow page table at a time.
2095	*/
2096	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2097
2098	/**
2099	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2100	*/
2101
2102	/*
2103	* Start by syncing the page directory entry.
2104	*/
2105	PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2106	\| (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2107
2108	# ifdef PGM_SYNC_DIRTY_BIT
2109	/*
2110	* If the page is not flagged as dirty and is writable, then make it read-only
2111	* at PD level, so we can set the dirty bit when the page is modified.
2112	*
2113	* ASSUMES that page access handlers are implemented on page table entry level.
2114	* Thus we will first catch the dirty access and set PDE.D and restart. If
2115	* there is an access handler, we'll trap again and let it work on the problem.
2116	*/
2117	/** @todo move the above stuff to a section in the PGM documentation. */
2118	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2119	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2120	{
2121	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2122	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2123	PdeDst.b.u1Write = 0;
2124	}
2125	# endif /* PGM_SYNC_DIRTY_BIT */
2126	*pPdeDst = PdeDst;
2127
2128	/*
2129	* Fill the shadow page table.
2130	*/
2131	/* Get address and flags from the source PDE. */
2132	SHWPTE PteDstBase;
2133	PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2134
2135	/* Loop thru the entries in the shadow PT. */
2136	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2137	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2138	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2139	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2140	PPGMRAMRANGE pRam = CTXSUFF(pVM->pgm.s.pRamRanges);
2141	unsigned iPTDst = 0;
2142	while (iPTDst < ELEMENTS(pPTDst->a))
2143	{
2144	/* Advance ram range list. */
2145	while (pRam && GCPhys > pRam->GCPhysLast)
2146	pRam = CTXSUFF(pRam->pNext);
2147	if (pRam && GCPhys >= pRam->GCPhys)
2148	{
2149	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2150	do
2151	{
2152	/* Make shadow PTE. */
2153	RTHCPHYS HCPhys = pRam->aHCPhys[iHCPage];
2154	SHWPTE PteDst;
2155
2156	/* Make sure the RAM has already been allocated. */
2157	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2158	{
2159	if (RT_UNLIKELY(!(pRam->aHCPhys[iHCPage] & X86_PTE_PAE_PG_MASK)))
2160	{
2161	# ifdef IN_RING3
2162	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2163	# else
2164	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2165	# endif
2166	if (rc != VINF_SUCCESS)
2167	return rc;
2168
2169	HCPhys = pRam->aHCPhys[iHCPage];
2170	}
2171	}
2172
2173	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
2174	{
2175	if (!(HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL)))
2176	{
2177	PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) \| PteDstBase.u;
2178	PteDst.n.u1Write = 0;
2179	}
2180	else
2181	PteDst.u = 0;
2182	}
2183	# ifndef IN_RING0
2184	/*
2185	* Assuming kernel code will be marked as supervisor and not as user level and executed
2186	* using a conforming code selector. Don't check for readonly, as that implies the whole
2187	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2188	*/
2189	else if ( !PdeSrc.n.u1User
2190	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2191	PteDst.u = 0;
2192	# endif
2193	else
2194	PteDst.u = (HCPhys & X86_PTE_PAE_PG_MASK) \| PteDstBase.u;
2195	# ifdef PGMPOOL_WITH_USER_TRACKING
2196	if (PteDst.n.u1Present)
2197	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, &pRam->aHCPhys[iHCPage], iPTDst);
2198	# endif
2199	/* commit it */
2200	pPTDst->a[iPTDst] = PteDst;
2201	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2202	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2203	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2204
2205	/* advance */
2206	GCPhys += PAGE_SIZE;
2207	iHCPage++;
2208	iPTDst++;
2209	} while ( iPTDst < ELEMENTS(pPTDst->a)
2210	&& GCPhys <= pRam->GCPhysLast);
2211	}
2212	else if (pRam)
2213	{
2214	Log(("Invalid pages at %VGp\n", GCPhys));
2215	do
2216	{
2217	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2218	GCPhys += PAGE_SIZE;
2219	iPTDst++;
2220	} while ( iPTDst < ELEMENTS(pPTDst->a)
2221	&& GCPhys < pRam->GCPhys);
2222	}
2223	else
2224	{
2225	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2226	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2227	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2228	}
2229	} /* while more PTEs */
2230	} /* 4KB / 4MB */
2231	}
2232	else
2233	AssertRelease(!PdeDst.n.u1Present);
2234
2235	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2236	# ifdef IN_GC
2237	if (VBOX_FAILURE(rc))
2238	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2239	# endif
2240	return rc;
2241
2242	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2243
2244	int rc = VINF_SUCCESS;
2245
2246	/*
2247	* Validate input a little bit.
2248	*/
2249	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2250	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2251	# else
2252	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2253	# endif
2254	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2255	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2256	SHWPDE PdeDst = *pPdeDst;
2257
2258	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2259	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2260
2261	VBOXPDE PdeSrc;
2262	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2263	PdeSrc.n.u1Present = 1;
2264	PdeSrc.n.u1Write = 1;
2265	PdeSrc.n.u1Accessed = 1;
2266	PdeSrc.n.u1User = 1;
2267
2268	/*
2269	* Allocate & map the page table.
2270	*/
2271	PSHWPT pPTDst;
2272	PPGMPOOLPAGE pShwPage;
2273	RTGCPHYS GCPhys;
2274
2275	/* Virtual address = physical address */
2276	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2277	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2278
2279	if ( rc == VINF_SUCCESS
2280	\|\| rc == VINF_PGM_CACHED_PAGE)
2281	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2282	else
2283	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2284
2285	PdeDst.u &= X86_PDE_AVL_MASK;
2286	PdeDst.u \|= pShwPage->Core.Key;
2287	PdeDst.n.u1Present = 1;
2288	*pPdeDst = PdeDst;
2289
2290	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2291	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2292	return rc;
2293
2294	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2295
2296	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2297	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2298	return VERR_INTERNAL_ERROR;
2299	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2300	}
2301
2302
2303
2304	/**
2305	* Prefetch a page/set of pages.
2306	*
2307	* Typically used to sync commonly used pages before entering raw mode
2308	* after a CR3 reload.
2309	*
2310	* @returns VBox status code.
2311	* @param pVM VM handle.
2312	* @param GCPtrPage Page to invalidate.
2313	*/
2314	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2315	{
2316	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2317
2318	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2319	# error "Invalid shadow mode for 32-bit guest mode!"
2320	# endif
2321
2322	/*
2323	* Check that all Guest levels thru the PDE are present, getting the
2324	* PD and PDE in the processes.
2325	*/
2326	int rc = VINF_SUCCESS;
2327	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2328	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2329	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2330	# else
2331	PVBOXPD pPDSrc = NULL;
2332	const unsigned iPDSrc = 0;
2333	# endif
2334
2335	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2336	const VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2337	# else
2338	VBOXPDE PdeSrc;
2339	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2340	PdeSrc.n.u1Present = 1;
2341	PdeSrc.n.u1Write = 1;
2342	PdeSrc.n.u1Accessed = 1;
2343	PdeSrc.n.u1User = 1;
2344	# endif
2345
2346	# ifdef PGM_SYNC_ACCESSED_BIT
2347	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2348	# else
2349	if (PdeSrc.n.u1Present)
2350	# endif
2351	{
2352	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2353	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2354	# else
2355	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2356	# endif
2357	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2358	{
2359	if (!PdeDst.n.u1Present)
2360	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2361	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2362	else
2363	{
2364	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2365	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2366	* makes no sense to prefetch more than one page.
2367	*/
2368	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2369	if (VBOX_SUCCESS(rc))
2370	rc = VINF_SUCCESS;
2371	}
2372	}
2373	}
2374	return rc;
2375
2376	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2377
2378	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2379	return VERR_INTERNAL_ERROR;
2380	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2381	}
2382
2383
2384
2385
2386	/**
2387	* Syncs a page during a PGMVerifyAccess() call.
2388	*
2389	* @returns VBox status code (informational included).
2390	* @param GCPtrPage The address of the page to sync.
2391	* @param fPage The effective guest page flags.
2392	* @param uErr The trap error code.
2393	*/
2394	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2395	{
2396	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2397
2398	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2399
2400	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2401	# error "Invalid shadow mode for 32-bit guest mode!"
2402	# endif
2403
2404	#ifndef IN_RING0
2405	if (!(fPage & X86_PTE_US))
2406	{
2407	/*
2408	* Mark this page as safe.
2409	*/
2410	/** @todo not correct for pages that contain both code and data!! */
2411	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2412	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2413	}
2414	#endif
2415	/*
2416	* Get guest PD and index.
2417	*/
2418	unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
2419	PVBOXPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2420	int rc = VINF_SUCCESS;
2421
2422	/*
2423	* First check if the shadow pd is present.
2424	*/
2425	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2426	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> X86_PD_SHIFT];
2427	# else
2428	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> X86_PD_PAE_SHIFT];
2429	# endif
2430	if (!pPdeDst->n.u1Present)
2431	{
2432	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2433	AssertRC(rc);
2434	if (rc != VINF_SUCCESS)
2435	return rc;
2436	}
2437
2438	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2439	/* Check for dirty bit fault */
2440	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2441	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2442	Log(("PGMVerifyAccess: success (dirty)\n"));
2443	else
2444	{
2445	VBOXPDE PdeSrc = pPDSrc->a[iPDSrc];
2446	#else
2447	{
2448	VBOXPDE PdeSrc;
2449	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2450	PdeSrc.n.u1Present = 1;
2451	PdeSrc.n.u1Write = 1;
2452	PdeSrc.n.u1Accessed = 1;
2453	PdeSrc.n.u1User = 1;
2454
2455	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2456	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2457	if (uErr & X86_TRAP_PF_US)
2458	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2459	else /* supervisor */
2460	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2461
2462	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2463	if (VBOX_SUCCESS(rc))
2464	{
2465	/* Page was successfully synced */
2466	Log(("PGMVerifyAccess: success (sync)\n"));
2467	rc = VINF_SUCCESS;
2468	}
2469	else
2470	{
2471	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2472	return VINF_EM_RAW_GUEST_TRAP;
2473	}
2474	}
2475	return rc;
2476
2477	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2478
2479	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2480	return VERR_INTERNAL_ERROR;
2481	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2482	}
2483
2484
2485	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2486	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2487	/**
2488	* Figures out which kind of shadow page this guest PDE warrants.
2489	*
2490	* @returns Shadow page kind.
2491	* @param pPdeSrc The guest PDE in question.
2492	* @param cr4 The current guest cr4 value.
2493	*/
2494	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const VBOXPDE *pPdeSrc, uint32_t cr4)
2495	{
2496	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2497	return BTH_PGMPOOLKIND_PT_FOR_PT;
2498	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2499	//{
2500	// case 0:
2501	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2502	// case X86_PDE4M_RW:
2503	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2504	// case X86_PDE4M_US:
2505	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2506	// case X86_PDE4M_RW \| X86_PDE4M_US:
2507	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2508	# if 0
2509	// case X86_PDE4M_PAE_NX:
2510	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2511	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2512	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2513	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2514	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2515	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2516	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2517	# endif
2518	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2519	//}
2520	}
2521	# endif
2522	#endif
2523
2524	#undef MY_STAM_COUNTER_INC
2525	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2526
2527
2528	/**
2529	* Syncs the paging hierarchy starting at CR3.
2530	*
2531	* @returns VBox status code, no specials.
2532	* @param pVM The virtual machine.
2533	* @param cr0 Guest context CR0 register
2534	* @param cr3 Guest context CR3 register
2535	* @param cr4 Guest context CR4 register
2536	* @param fGlobal Including global page directories or not
2537	*/
2538	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2539	{
2540	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2541	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2542	/*
2543	* Inform the PGM PD Cache Manager about the pending sync.
2544	*/
2545	if (fGlobal \|\| VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2546	{
2547	# if 0 /** @todo what the heck is this about? */
2548	/* Don't cause an additional global CR3 reload the next time (the flag is cleared in PGMSyncCR3). */
2549	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2550	# endif
2551
2552	/* Change this CR3 reload to be a global one. */
2553	fGlobal = true;
2554	}
2555	# endif
2556	#endif
2557
2558	/*
2559	* Update page access handlers.
2560	* The virtual are always flushed, while the physical are only on demand.
2561	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2562	* have to look into that later because it will have a bad influence on the performance.
2563	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2564	* bird: Yes, but that won't work for aliases.
2565	*/
2566	/** @todo this MUST go away. See #1557. */
2567	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2568	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2569	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2570
2571	#ifdef PGMPOOL_WITH_MONITORING
2572	/*
2573	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2574	* Occationally we will have to clear all the shadow page tables because we wanted
2575	* to monitor a page which was mapped by too many shadowed page tables. This operation
2576	* sometimes refered to as a 'lightweight flush'.
2577	*/
2578	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2579	pgmPoolMonitorModifiedClearAll(pVM);
2580	else
2581	{
2582	# ifdef IN_RING3
2583	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2584	pgmPoolClearAll(pVM);
2585	# else
2586	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2587	return VINF_PGM_SYNC_CR3;
2588	# endif
2589	}
2590	#endif
2591
2592	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2593	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2594
2595	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2596	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2597	/*
2598	* Get page directory addresses.
2599	*/
2600	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2601	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2602	# else
2603	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2604	# endif
2605	PVBOXPD pPDSrc = pVM->pgm.s.CTXSUFF(pGuestPD);
2606
2607	Assert(pPDSrc);
2608	#ifndef IN_GC
2609	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2610	#endif
2611
2612	/*
2613	* Iterate the page directory.
2614	*/
2615	PPGMMAPPING pMapping;
2616	unsigned iPdNoMapping;
2617	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2618	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2619
2620	/* Only check mappings if they are supposed to be put into the shadow page table. */
2621	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2622	{
2623	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2624	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2625	}
2626	else
2627	{
2628	pMapping = 0;
2629	iPdNoMapping = ~0U;
2630	}
2631
2632	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2633	{
2634	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2635	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2636	# else
2637	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2638	# endif
2639	register VBOXPDE PdeSrc = pPDSrc->a[iPD];
2640	if ( PdeSrc.n.u1Present
2641	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2642	{
2643	/*
2644	* Check for conflicts with GC mappings.
2645	*/
2646	if (iPD == iPdNoMapping)
2647	{
2648	if (pVM->pgm.s.fMappingsFixed)
2649	{
2650	/* It's fixed, just skip the mapping. */
2651	const unsigned cPTs = pMapping->cPTs;
2652	iPD += cPTs - 1;
2653	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2654	pMapping = pMapping->CTXALLSUFF(pNext);
2655	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2656	continue;
2657	}
2658
2659	#ifdef IN_RING3
2660	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2661	if (VBOX_FAILURE(rc))
2662	return rc;
2663
2664	/*
2665	* Update iPdNoMapping and pMapping.
2666	*/
2667	pMapping = pVM->pgm.s.pMappingsR3;
2668	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2669	pMapping = pMapping->pNextR3;
2670	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2671	#else
2672	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2673	return VINF_PGM_SYNC_CR3;
2674	#endif
2675	}
2676
2677	/*
2678	* Sync page directory entry.
2679	*
2680	* The current approach is to allocated the page table but to set
2681	* the entry to not-present and postpone the page table synching till
2682	* it's actually used.
2683	*/
2684	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2685	const unsigned iPdShw = iPD; NOREF(iPdShw);
2686	# else
2687	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2688	# endif
2689	{
2690	SHWPDE PdeDst = *pPDEDst;
2691	if (PdeDst.n.u1Present)
2692	{
2693	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2694	RTGCPHYS GCPhys;
2695	if ( !PdeSrc.b.u1Size
2696	\|\| !(cr4 & X86_CR4_PSE))
2697	{
2698	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2699	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2700	GCPhys \|= i * (PAGE_SIZE / 2);
2701	# endif
2702	}
2703	else
2704	{
2705	GCPhys = PdeSrc.u & GST_PDE4M_PG_MASK;
2706	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2707	GCPhys \|= i * X86_PAGE_2M_SIZE;
2708	# endif
2709	}
2710
2711	if ( pShwPage->GCPhys == GCPhys
2712	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2713	&& ( pShwPage->fCached
2714	\|\| ( !fGlobal
2715	&& ( false
2716	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2717	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2718	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2719	\|\| ( !pShwPage->fSeenNonGlobal
2720	&& (cr4 & X86_CR4_PGE))
2721	# endif
2722	)
2723	)
2724	)
2725	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2726	\|\| ( (cr4 & X86_CR4_PSE)
2727	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2728	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2729	)
2730	)
2731	{
2732	# ifdef VBOX_WITH_STATISTICS
2733	if ( !fGlobal
2734	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2735	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2736	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2737	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2738	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2739	else
2740	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2741	# endif /* VBOX_WITH_STATISTICS */
2742	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2743	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2744	//# ifdef PGMPOOL_WITH_CACHE
2745	// pgmPoolCacheUsed(pPool, pShwPage);
2746	//# endif
2747	}
2748	else
2749	{
2750	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2751	pPDEDst->u = 0;
2752	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2753	}
2754	}
2755	else
2756	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2757	pPDEDst++;
2758	}
2759	}
2760	else if (iPD != iPdNoMapping)
2761	{
2762	/*
2763	* Check if there is any page directory to mark not present here.
2764	*/
2765	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2766	const unsigned iPdShw = iPD; NOREF(iPdShw);
2767	# else
2768	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2769	# endif
2770	{
2771	if (pPDEDst->n.u1Present)
2772	{
2773	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2774	pPDEDst->u = 0;
2775	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2776	}
2777	pPDEDst++;
2778	}
2779	}
2780	else
2781	{
2782	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2783	const unsigned cPTs = pMapping->cPTs;
2784	if (pVM->pgm.s.fMappingsFixed)
2785	{
2786	/* It's fixed, just skip the mapping. */
2787	pMapping = pMapping->CTXALLSUFF(pNext);
2788	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2789	}
2790	else
2791	{
2792	/*
2793	* Check for conflicts for subsequent pagetables
2794	* and advance to the next mapping.
2795	*/
2796	iPdNoMapping = ~0U;
2797	unsigned iPT = cPTs;
2798	while (iPT-- > 1)
2799	{
2800	if ( pPDSrc->a[iPD + iPT].n.u1Present
2801	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2802	{
2803	# ifdef IN_RING3
2804	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2805	if (VBOX_FAILURE(rc))
2806	return rc;
2807
2808	/*
2809	* Update iPdNoMapping and pMapping.
2810	*/
2811	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2812	while (pMapping && pMapping->GCPtr < (iPD << PGDIR_SHIFT))
2813	pMapping = pMapping->CTXALLSUFF(pNext);
2814	iPdNoMapping = pMapping ? pMapping->GCPtr >> PGDIR_SHIFT : ~0U;
2815	break;
2816	# else
2817	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2818	return VINF_PGM_SYNC_CR3;
2819	# endif
2820	}
2821	}
2822	if (iPdNoMapping == ~0U && pMapping)
2823	{
2824	pMapping = pMapping->CTXALLSUFF(pNext);
2825	if (pMapping)
2826	iPdNoMapping = pMapping->GCPtr >> PGDIR_SHIFT;
2827	}
2828	}
2829	/* advance. */
2830	iPD += cPTs - 1;
2831	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2832	}
2833
2834	} /* for iPD */
2835	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2836	# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2837	# endif
2838
2839	return VINF_SUCCESS;
2840
2841	#elif PGM_GST_TYPE == PGM_TYPE_PAE
2842	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2843	//# error not implemented
2844	return VERR_INTERNAL_ERROR;
2845
2846	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2847	# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2848	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2849
2850	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2851	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2852	//# error not implemented
2853	return VERR_INTERNAL_ERROR;
2854
2855	# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2856	# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2857	# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2858
2859	#else /* guest real and protected mode */
2860
2861	return VINF_SUCCESS;
2862	#endif
2863	}
2864
2865
2866
2867
2868	#ifdef VBOX_STRICT
2869	#ifdef IN_GC
2870	# undef AssertMsgFailed
2871	# define AssertMsgFailed Log
2872	#endif
2873	#ifdef IN_RING3
2874	# include <VBox/dbgf.h>
2875
2876	/**
2877	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2878	*
2879	* @returns VBox status code (VINF_SUCCESS).
2880	* @param pVM The VM handle.
2881	* @param cr3 The root of the hierarchy.
2882	* @param crr The cr4, only PAE and PSE is currently used.
2883	* @param fLongMode Set if long mode, false if not long mode.
2884	* @param cMaxDepth Number of levels to dump.
2885	* @param pHlp Pointer to the output functions.
2886	*/
2887	__BEGIN_DECLS
2888	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2889	__END_DECLS
2890
2891	#endif
2892
2893	/**
2894	* Checks that the shadow page table is in sync with the guest one.
2895	*
2896	* @returns The number of errors.
2897	* @param pVM The virtual machine.
2898	* @param cr3 Guest context CR3 register
2899	* @param cr4 Guest context CR4 register
2900	* @param GCPtr Where to start. Defaults to 0.
2901	* @param cb How much to check. Defaults to everything.
2902	*/
2903	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2904	{
2905	unsigned cErrors = 0;
2906
2907	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2908
2909	# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2910	# error "Invalid shadow mode for 32-bit guest paging."
2911	# endif
2912
2913	PPGM pPGM = &pVM->pgm.s;
2914	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2915	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2916	RTHCPHYS HCPhys; /* general usage. */
2917	int rc;
2918
2919	/*
2920	* Check that the Guest CR3 and all it's mappings are correct.
2921	*/
2922	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & X86_CR3_PAGE_MASK),
2923	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2924	false);
2925	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2926	AssertRCReturn(rc, 1);
2927	rc = PGMRamGCPhys2HCPhys(pPGM, cr3 & X86_CR3_PAGE_MASK, &HCPhys);
2928	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2929	# ifndef IN_GC
2930	RTGCPHYS GCPhys;
2931	rc = PGMPhysHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2932	AssertRCReturn(rc, 1);
2933	AssertMsgReturn((cr3 & X86_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2934	# endif
2935	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2936
2937	/*
2938	* Get and check the Shadow CR3.
2939	*/
2940	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2941	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2942	unsigned cPDEs = ELEMENTS(pPDDst->a);
2943	# else
2944	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2945	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2946	# endif
2947	if (cb != ~(RTGCUINTPTR)0)
2948	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2949
2950	/** @todo call the other two PGMAssert() functions. /
2951
2952	/*
2953	* Iterate the shadow page directory.
2954	*/
2955	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2956	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2957	cPDEs += iPDDst;
2958	for (;
2959	iPDDst < cPDEs;
2960	iPDDst++, GCPtr += _4G / cPDEs)
2961	{
2962	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2963	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2964	{
2965	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2966	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2967	{
2968	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2969	cErrors++;
2970	continue;
2971	}
2972	}
2973	else if ( (PdeDst.u & X86_PDE_P)
2974	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2975	)
2976	{
2977	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2978	PPGMPOOLPAGE pPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2979	if (!pPage)
2980	{
2981	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2982	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2983	cErrors++;
2984	continue;
2985	}
2986	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPage);
2987
2988	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
2989	{
2990	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2991	GCPtr, (uint64_t)PdeDst.u));
2992	cErrors++;
2993	}
2994
2995	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
2996	{
2997	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2998	GCPtr, (uint64_t)PdeDst.u));
2999	cErrors++;
3000	}
3001
3002	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
3003	if (!PdeSrc.n.u1Present)
3004	{
3005	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3006	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3007	cErrors++;
3008	continue;
3009	}
3010
3011	if ( !PdeSrc.b.u1Size
3012	\|\| !(cr4 & X86_CR4_PSE))
3013	{
3014	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3015	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3016	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3017	# endif
3018	}
3019	else
3020	{
3021	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3022	{
3023	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3024	GCPtr, (uint64_t)PdeSrc.u));
3025	cErrors++;
3026	continue;
3027	}
3028	GCPhysGst = PdeSrc.u & GST_PDE4M_PG_MASK;
3029	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3030	GCPhysGst \|= GCPtr & BIT(X86_PAGE_2M_SHIFT);
3031	# endif
3032	}
3033
3034	if ( pPage->enmKind
3035	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3036	{
3037	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3038	pPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3039	cErrors++;
3040	}
3041
3042	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3043	if (VBOX_FAILURE(rc))
3044	{
3045	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3046	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3047	cErrors++;
3048	continue;
3049	}
3050
3051	if (GCPhysGst != pPage->GCPhys)
3052	{
3053	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3054	GCPhysGst, pPage->GCPhys, GCPtr));
3055	cErrors++;
3056	continue;
3057	}
3058
3059	if ( !PdeSrc.b.u1Size
3060	\|\| !(cr4 & X86_CR4_PSE))
3061	{
3062	/*
3063	* Page Table.
3064	*/
3065	const GSTPT *pPTSrc;
3066	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3067	if (VBOX_FAILURE(rc))
3068	{
3069	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3070	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3071	cErrors++;
3072	continue;
3073	}
3074	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3075	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3076	{
3077	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3078	// (This problem will go away when/if we shadow multiple CR3s.)
3079	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3080	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3081	cErrors++;
3082	continue;
3083	}
3084	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3085	{
3086	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3087	GCPtr, (uint64_t)PdeDst.u));
3088	cErrors++;
3089	continue;
3090	}
3091
3092	/* iterate the page table. */
3093	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3094	const unsigned offPTSrc = 0;
3095	# else
3096	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3097	# endif
3098	for (unsigned iPT = 0, off = 0;
3099	iPT < ELEMENTS(pPTDst->a);
3100	iPT++, off += PAGE_SIZE)
3101	{
3102	const SHWPTE PteDst = pPTDst->a[iPT];
3103
3104	/* skip not-present entries. */
3105	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3106	continue;
3107	Assert(PteDst.n.u1Present);
3108
3109	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3110	if (!PteSrc.n.u1Present)
3111	{
3112	#ifdef IN_RING3
3113	PGMAssertHandlerAndFlagsInSync(pVM);
3114	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3115	#endif
3116	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3117	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3118	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3119	cErrors++;
3120	continue;
3121	}
3122
3123	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3124	# if 1 /** @todo sync accessed bit properly... */
3125	fIgnoreFlags \|= X86_PTE_A;
3126	# endif
3127
3128	/* match the physical addresses */
3129	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3130	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3131
3132	# ifdef IN_RING3
3133	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3134	if (VBOX_FAILURE(rc))
3135	{
3136	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3137	{
3138	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3139	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3140	cErrors++;
3141	continue;
3142	}
3143	}
3144	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3145	{
3146	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3147	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3148	cErrors++;
3149	continue;
3150	}
3151	# endif
3152
3153	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3154	if (VBOX_FAILURE(rc))
3155	{
3156	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3157	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3158	{
3159	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3160	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3161	cErrors++;
3162	continue;
3163	}
3164	# endif
3165	if (PteDst.n.u1Write)
3166	{
3167	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3168	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3169	cErrors++;
3170	}
3171	fIgnoreFlags \|= X86_PTE_RW;
3172	}
3173	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3174	{
3175	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3176	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3177	cErrors++;
3178	continue;
3179	}
3180
3181	/* flags */
3182	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3183	{
3184	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3185	{
3186	if (PteDst.n.u1Write)
3187	{
3188	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3189	GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3190	cErrors++;
3191	continue;
3192	}
3193	fIgnoreFlags \|= X86_PTE_RW;
3194	}
3195	else
3196	{
3197	if (PteDst.n.u1Present)
3198	{
3199	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3200	GCPtr + off, HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3201	cErrors++;
3202	continue;
3203	}
3204	fIgnoreFlags \|= X86_PTE_P;
3205	}
3206	}
3207	else
3208	{
3209	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3210	{
3211	if (PteDst.n.u1Write)
3212	{
3213	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3214	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3215	cErrors++;
3216	continue;
3217	}
3218	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3219	{
3220	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3221	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3222	cErrors++;
3223	continue;
3224	}
3225	if (PteDst.n.u1Dirty)
3226	{
3227	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3228	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3229	cErrors++;
3230	}
3231	# if 0 /** @todo sync access bit properly... */
3232	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3233	{
3234	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3235	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3236	cErrors++;
3237	}
3238	fIgnoreFlags \|= X86_PTE_RW;
3239	# else
3240	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3241	# endif
3242	}
3243	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3244	{
3245	/* access bit emulation (not implemented). */
3246	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3247	{
3248	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3249	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3250	cErrors++;
3251	continue;
3252	}
3253	if (!PteDst.n.u1Accessed)
3254	{
3255	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3256	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3257	cErrors++;
3258	}
3259	fIgnoreFlags \|= X86_PTE_P;
3260	}
3261	# ifdef DEBUG_sandervl
3262	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3263	# endif
3264	}
3265
3266	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3267	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3268	)
3269	{
3270	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3271	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3272	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3273	cErrors++;
3274	continue;
3275	}
3276	} /* foreach PTE */
3277	}
3278	else
3279	{
3280	/*
3281	* Big Page.
3282	*/
3283	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| X86_PDE_PAE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3284	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3285	{
3286	if (PdeDst.n.u1Write)
3287	{
3288	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3289	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3290	cErrors++;
3291	continue;
3292	}
3293	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3294	{
3295	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3296	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3297	cErrors++;
3298	continue;
3299	}
3300	# if 0 /** @todo sync access bit properly... */
3301	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3302	{
3303	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3304	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3305	cErrors++;
3306	}
3307	fIgnoreFlags \|= X86_PTE_RW;
3308	# else
3309	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3310	# endif
3311	}
3312	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3313	{
3314	/* access bit emulation (not implemented). */
3315	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3316	{
3317	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3318	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3319	cErrors++;
3320	continue;
3321	}
3322	if (!PdeDst.n.u1Accessed)
3323	{
3324	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3325	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3326	cErrors++;
3327	}
3328	fIgnoreFlags \|= X86_PTE_P;
3329	}
3330
3331	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3332	{
3333	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3334	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3335	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3336	cErrors++;
3337	}
3338
3339	/* iterate the page table. */
3340	for (unsigned iPT = 0, off = 0;
3341	iPT < ELEMENTS(pPTDst->a);
3342	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3343	{
3344	const SHWPTE PteDst = pPTDst->a[iPT];
3345
3346	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3347	{
3348	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3349	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3350	cErrors++;
3351	}
3352
3353	/* skip not-present entries. */
3354	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3355	continue;
3356
3357	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3358
3359	/* match the physical addresses */
3360	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3361
3362	# ifdef IN_RING3
3363	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3364	if (VBOX_FAILURE(rc))
3365	{
3366	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3367	{
3368	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3369	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3370	cErrors++;
3371	}
3372	}
3373	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3374	{
3375	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3376	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3377	cErrors++;
3378	continue;
3379	}
3380	# endif
3381
3382	rc = PGMRamGCPhys2HCPhysWithFlags(pPGM, GCPhysGst, &HCPhys);
3383	if (VBOX_FAILURE(rc))
3384	{
3385	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3386	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3387	{
3388	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3389	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3390	cErrors++;
3391	continue;
3392	}
3393	# endif
3394	if (PteDst.n.u1Write)
3395	{
3396	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3397	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3398	cErrors++;
3399	}
3400	fIgnoreFlags \|= X86_PTE_RW;
3401	}
3402	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3403	{
3404	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3405	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3406	cErrors++;
3407	continue;
3408	}
3409
3410	/* flags */
3411	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_ALL \| MM_RAM_FLAGS_VIRTUAL_ALL \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3412	{
3413	if (HCPhys & (MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_WRITE))
3414	{
3415	if (!(HCPhys & MM_RAM_FLAGS_PHYSICAL_TEMP_OFF))
3416	{
3417	if (PteDst.n.u1Write)
3418	{
3419	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3420	GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3421	cErrors++;
3422	continue;
3423	}
3424	fIgnoreFlags \|= X86_PTE_RW;
3425	}
3426	}
3427	else
3428	{
3429	if (PteDst.n.u1Present)
3430	{
3431	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3432	GCPtr + off, HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3433	cErrors++;
3434	continue;
3435	}
3436	fIgnoreFlags \|= X86_PTE_P;
3437	}
3438	}
3439
3440	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3441	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3442	)
3443	{
3444	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3445	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3446	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3447	cErrors++;
3448	continue;
3449	}
3450	} /* foreach PTE */
3451	}
3452	}
3453	/* not present */
3454
3455	} /* forearch PDE */
3456
3457	# ifdef DEBUG
3458	if (cErrors)
3459	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3460	# endif
3461
3462	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3463	//# error not implemented
3464
3465
3466	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3467	//# error not implemented
3468
3469	/#else: guest real and protected mode /
3470	#endif
3471	return cErrors;
3472	}
3473	#endif /* VBOX_STRICT */
3474

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 2744

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