PGMAllBth.h@ 31101

Last change on this file since 31101 was 31101, checked in by vboxsync, 14 years ago
PGM: Moved the code dealing with access handlers out of the #PF function.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 205.7 KB

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1	/* $Id: PGMAllBth.h 31101 2010-07-26 09:33:19Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage);
38	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
40	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
41	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
42	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
43	#ifdef VBOX_STRICT
44	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
45	#endif
46	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte);
47	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
48	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
49	RT_C_DECLS_END
50
51
52	/*
53	* Filter out some illegal combinations of guest and shadow paging, so we can
54	* remove redundant checks inside functions.
55	*/
56	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
57	# error "Invalid combination; PAE guest implies PAE shadow"
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
61	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
62	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
63	#endif
64
65	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
66	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
67	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
68	#endif
69
70	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
71	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
72	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
73	#endif
74
75	#ifndef IN_RING3
76
77	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
78	/**
79	* Deal with a guest page fault.
80	*
81	* @returns Strict VBox status code.
82	* @retval VINF_EM_RAW_GUEST_TRAP
83	* @retval VINF_EM_RAW_EMULATE_INSTR
84	*
85	* @param pVCpu The current CPU.
86	* @param pGstWalk The guest page table walk result.
87	* @param uErr The error code.
88	*/
89	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
90	{
91	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
92	/*
93	* Check for write conflicts with our hypervisor mapping.
94	*
95	* If the guest happens to access a non-present page, where our hypervisor
96	* is currently mapped, then we'll create a #PF storm in the guest.
97	*/
98	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
99	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
100	{
101	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
102	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
103	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
104	return VINF_EM_RAW_EMULATE_INSTR;
105	}
106	# endif
107
108	/*
109	* Calc the error code for the guest trap.
110	*/
111	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
112	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
113	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
114	if (pGstWalk->Core.fBadPhysAddr)
115	{
116	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
117	Assert(!pGstWalk->Core.fNotPresent);
118	}
119	else if (!pGstWalk->Core.fNotPresent)
120	uNewErr \|= X86_TRAP_PF_P;
121	TRPMSetErrorCode(pVCpu, uNewErr);
122
123	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
124	return VINF_EM_RAW_GUEST_TRAP;
125	}
126	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
127
128
129	/**
130	* Deal with a guest page fault.
131	*
132	* @returns Strict VBox status code.
133	* @retval VINF_EM_RAW_GUEST_TRAP
134	* @retval VINF_EM_RAW_EMULATE_INSTR
135	*
136	* @param pVCpu The current CPU.
137	*
138	* @param uErr The error code.
139	*
140	* @param pGstWalk The guest page table walk result.
141	*/
142	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
143	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
144	RTGCPTR pvFault, PPGMPAGE pPage, PGSTPTWALK pGstWalk)
145	# else
146	RTGCPTR pvFault, PPGMPAGE pPage)
147	# endif
148	{
149	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
150	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
151	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A};
152	#endif
153	PVM pVM = pVCpu->CTX_SUFF(pVM);
154	int rc;
155
156	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
157	{
158	/*
159	* Physical page access handler.
160	*/
161	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
162	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
163	# else
164	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
165	# endif
166	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
167	if (pCur)
168	{
169	# ifdef PGM_SYNC_N_PAGES
170	/*
171	* If the region is write protected and we got a page not present fault, then sync
172	* the pages. If the fault was caused by a read, then restart the instruction.
173	* In case of write access continue to the GC write handler.
174	*
175	* ASSUMES that there is only one handler per page or that they have similar write properties.
176	*/
177	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
178	&& !(uErr & X86_TRAP_PF_P))
179	{
180	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
181	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
182	# else
183	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
184	# endif
185	if ( RT_FAILURE(rc)
186	\|\| !(uErr & X86_TRAP_PF_RW)
187	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
188	{
189	AssertRC(rc);
190	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
191	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197
198	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
199	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
200	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
201	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
202
203	# if defined(IN_RC) \|\| defined(IN_RING0) /** @todo remove this */
204	if (pCur->CTX_SUFF(pfnHandler))
205	{
206	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
207	# ifdef IN_RING0
208	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
209	# else
210	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
211	# endif
212	bool fLeaveLock = (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler));
213	void *pvUser = pCur->CTX_SUFF(pvUser);
214
215	STAM_PROFILE_START(&pCur->Stat, h);
216	if (fLeaveLock)
217	pgmUnlock(pVM); /* @todo: Not entirely safe. */
218
219	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
220	if (fLeaveLock)
221	pgmLock(pVM);
222	# ifdef VBOX_WITH_STATISTICS
223	pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->PhysHandlers, GCPhysFault);
224	if (pCur)
225	STAM_PROFILE_STOP(&pCur->Stat, h);
226	# else
227	pCur = NULL; /* might be invalid by now. */
228	# endif
229
230	}
231	else
232	# endif /* IN_RC \|\| IN_RING0 */
233	rc = VINF_EM_RAW_EMULATE_INSTR;
234
235	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersPhysical);
236	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
237	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndPhys; });
238	return rc;
239	}
240	}
241	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
242	else
243	{
244	# ifdef PGM_SYNC_N_PAGES
245	/*
246	* If the region is write protected and we got a page not present fault, then sync
247	* the pages. If the fault was caused by a read, then restart the instruction.
248	* In case of write access continue to the GC write handler.
249	*/
250	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
251	&& !(uErr & X86_TRAP_PF_P))
252	{
253	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
254	if ( RT_FAILURE(rc)
255	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
256	\|\| !(uErr & X86_TRAP_PF_RW))
257	{
258	AssertRC(rc);
259	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
260	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
261	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndVirt; });
262	return rc;
263	}
264	}
265	# endif
266	/*
267	* Ok, it's an virtual page access handler.
268	*
269	* Since it's faster to search by address, we'll do that first
270	* and then retry by GCPhys if that fails.
271	*/
272	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
273	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
274	* out of sync, because the page was changed without us noticing it (not-present -> present
275	* without invlpg or mov cr3, xxx).
276	*/
277	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
278	if (pCur)
279	{
280	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
281	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
282	\|\| !(uErr & X86_TRAP_PF_P)
283	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
284	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
285	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
286
287	if ( pvFault - pCur->Core.Key < pCur->cb
288	&& ( uErr & X86_TRAP_PF_RW
289	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
290	{
291	# ifdef IN_RC
292	STAM_PROFILE_START(&pCur->Stat, h);
293	pgmUnlock(pVM);
294	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
295	pgmLock(pVM);
296	STAM_PROFILE_STOP(&pCur->Stat, h);
297	# else
298	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
299	# endif
300	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtual);
301	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
302	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
303	return rc;
304	}
305	/* Unhandled part of a monitored page */
306	}
307	else
308	{
309	/* Check by physical address. */
310	unsigned iPage;
311	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
312	Assert(RT_SUCCESS(rc) \|\| !pCur);
313	if ( pCur
314	&& ( uErr & X86_TRAP_PF_RW
315	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
316	{
317	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
318	# ifdef IN_RC
319	RTGCPTR off = (iPage << PAGE_SHIFT) + (pvFault & PAGE_OFFSET_MASK) - (pCur->Core.Key & PAGE_OFFSET_MASK);
320	Assert(off < pCur->cb);
321	STAM_PROFILE_START(&pCur->Stat, h);
322	pgmUnlock(pVM);
323	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, off);
324	pgmLock(pVM);
325	STAM_PROFILE_STOP(&pCur->Stat, h);
326	# else
327	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
328	# endif
329	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualByPhys);
330	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
331	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
332	return rc;
333	}
334	}
335	}
336	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
337
338	/*
339	* There is a handled area of the page, but this fault doesn't belong to it.
340	* We must emulate the instruction.
341	*
342	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
343	* we first check if this was a page-not-present fault for a page with only
344	* write access handlers. Restart the instruction if it wasn't a write access.
345	*/
346	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersUnhandled);
347
348	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
349	&& !(uErr & X86_TRAP_PF_P))
350	{
351	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
352	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
353	# else
354	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
355	# endif
356	if ( RT_FAILURE(rc)
357	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
358	\|\| !(uErr & X86_TRAP_PF_RW))
359	{
360	AssertRC(rc);
361	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersOutOfSync);
362	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
363	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndPhys; });
364	return rc;
365	}
366	}
367
368	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
369	* It's writing to an unhandled part of the LDT page several million times.
370	*/
371	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
372	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
373	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeHandlers, b);
374	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
375	return rc;
376	} /* if any kind of handler */
377
378
379	/**
380	* #PF Handler for raw-mode guest execution.
381	*
382	* @returns VBox status code (appropriate for trap handling and GC return).
383	*
384	* @param pVCpu VMCPU Handle.
385	* @param uErr The trap error code.
386	* @param pRegFrame Trap register frame.
387	* @param pvFault The fault address.
388	* @param pfLockTaken PGM lock taken here or not (out)
389	*/
390	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
391	{
392	PVM pVM = pVCpu->CTX_SUFF(pVM);
393
394	*pfLockTaken = false;
395
396	# if defined(IN_RC) && defined(VBOX_STRICT)
397	PGMDynCheckLocks(pVM);
398	# endif
399
400	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
401	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
402	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
403	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
404	int rc;
405
406	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
407	/*
408	* Walk the guest page translation tables and check if it's a guest fault.
409	*/
410	GSTPTWALK GstWalk;
411	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
412	if (RT_FAILURE_NP(rc))
413	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
414
415	/* assert some GstWalk sanity. */
416	# if PGM_GST_TYPE == PGM_TYPE_AMD64
417	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
418	# endif
419	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
420	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
421	# endif
422	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
423	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
424	Assert(GstWalk.Core.fSucceeded);
425
426	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
427	{
428	if ( ( (uErr & X86_TRAP_PF_RW)
429	&& !GstWalk.Core.fEffectiveRW
430	&& ( (uErr & X86_TRAP_PF_US)
431	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
432	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
433	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
434	)
435	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
436	}
437	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
438
439	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
440	/*
441	* If it is a reserved bit fault we know that it is an MMIO or access
442	* handler related fault and can skip the dirty page stuff below.
443	*/
444	if (uErr & X86_TRAP_PF_RSVD)
445	{
446	Assert(uErr & X86_TRAP_PF_P);
447	PPGMPAGE pPage;
448	/** @todo Only all physical access handlers here, so optimize further. */
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
451	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
452	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
453	&GstWalk));
454	# else
455	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
456	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
457	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage));
458	# endif
459	}
460	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
461
462	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
463	/*
464	* Set the accessed and dirty flags.
465	*/
466	# if PGM_GST_TYPE == PGM_TYPE_AMD64
467	GstWalk.Pml4e.u \|= X86_PML4E_A;
468	GstWalk.pPml4e->u \|= X86_PML4E_A;
469	GstWalk.Pdpe.u \|= X86_PDPE_A;
470	GstWalk.pPdpe->u \|= X86_PDPE_A;
471	# endif
472	if (GstWalk.Core.fBigPage)
473	{
474	Assert(GstWalk.Pde.b.u1Size);
475	if (uErr & X86_TRAP_PF_RW)
476	{
477	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
478	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
479	}
480	else
481	{
482	GstWalk.Pde.u \|= X86_PDE4M_A;
483	GstWalk.pPde->u \|= X86_PDE4M_A;
484	}
485	}
486	else
487	{
488	Assert(!GstWalk.Pde.b.u1Size);
489	GstWalk.Pde.u \|= X86_PDE_A;
490	GstWalk.pPde->u \|= X86_PDE_A;
491	if (uErr & X86_TRAP_PF_RW)
492	{
493	# ifdef VBOX_WITH_STATISTICS
494	if (!GstWalk.Pte.n.u1Dirty)
495	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
496	else
497	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
498	# endif
499	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
500	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
501	}
502	else
503	{
504	GstWalk.Pte.u \|= X86_PTE_A;
505	GstWalk.pPte->u \|= X86_PTE_A;
506	}
507	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
508	}
509	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
510	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
511	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
512	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
513	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
514
515	/* Take the big lock now. */
516	*pfLockTaken = true;
517	pgmLock(pVM);
518
519	/*
520	* Fetch the guest PDE, PDPE and PML4E.
521	*/
522	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
523	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
524	PX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
525
526	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
527	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
528	PX86PDPAE pPDDst;
529	# if PGM_GST_TYPE == PGM_TYPE_PAE
530	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
531	# else
532	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
533	# endif
534	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
535
536	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
537	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
538	PX86PDPAE pPDDst;
539	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
540	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
541	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
542	# else
543	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
544	# endif
545	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
546
547	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
548	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
549	PEPTPD pPDDst;
550	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
551	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
552	# endif
553	Assert(pPDDst);
554
555	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
556	/*
557	* Dirty page handling.
558	*
559	* If we successfully correct the write protection fault due to dirty bit
560	* tracking, then return immediately.
561	*/
562	if (uErr & X86_TRAP_PF_RW) /* write fault? */
563	{
564	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
565	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
566	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyBitTracking), a);
567	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
568	{
569	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
570	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVCpu->pgm.s.StatRZTrap0eTime2DirtyAndAccessed : &pVCpu->pgm.s.StatRZTrap0eTime2GuestTrap; });
571	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
572	return VINF_SUCCESS;
573	}
574	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
575	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
576	}
577
578	# if 0 /* rarely useful; leave for debugging. */
579	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
580	# endif
581	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
582
583	/*
584	* A common case is the not-present error caused by lazy page table syncing.
585	*
586	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
587	* here so we can safely assume that the shadow PT is present when calling
588	* SyncPage later.
589	*
590	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
591	* of mapping conflict and defer to SyncCR3 in R3.
592	* (Again, we do NOT support access handlers for non-present guest pages.)
593	*
594	*/
595	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
596	Assert(GstWalk.Pde.n.u1Present);
597	# endif
598	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
599	&& !pPDDst->a[iPDDst].n.u1Present)
600	{
601	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2SyncPT; });
602	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
603	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
604	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
605	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
606	# else
607	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
608	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
609	# endif
610	if (RT_SUCCESS(rc))
611	{
612	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
613	return rc;
614	}
615	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
616	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
617	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeSyncPT, f);
618	return VINF_PGM_SYNC_CR3;
619	}
620
621	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
622	/*
623	* Check if this address is within any of our mappings.
624	*
625	* This is very fast and it's gonna save us a bit of effort below and prevent
626	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
627	* (BTW, it's impossible to have physical access handlers in a mapping.)
628	*/
629	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
630	{
631	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
632	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
633	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
634	{
635	if (pvFault < pMapping->GCPtr)
636	break;
637	if (pvFault - pMapping->GCPtr < pMapping->cb)
638	{
639	/*
640	* The first thing we check is if we've got an undetected conflict.
641	*/
642	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
643	{
644	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
645	while (iPT-- > 0)
646	if (GstWalk.pPde[iPT].n.u1Present)
647	{
648	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eConflicts);
649	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
650	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
651	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
652	return VINF_PGM_SYNC_CR3;
653	}
654	}
655
656	/*
657	* Check if the fault address is in a virtual page access handler range.
658	*/
659	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
660	if ( pCur
661	&& pvFault - pCur->Core.Key < pCur->cb
662	&& uErr & X86_TRAP_PF_RW)
663	{
664	# ifdef IN_RC
665	STAM_PROFILE_START(&pCur->Stat, h);
666	pgmUnlock(pVM);
667	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
668	pgmLock(pVM);
669	STAM_PROFILE_STOP(&pCur->Stat, h);
670	# else
671	AssertFailed();
672	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
673	# endif
674	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersMapping);
675	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
676	return rc;
677	}
678
679	/*
680	* Pretend we're not here and let the guest handle the trap.
681	*/
682	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
683	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFMapping);
684	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
685	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
686	return VINF_EM_RAW_GUEST_TRAP;
687	}
688	}
689	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeMapping, a);
690	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
691	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
692
693	/*
694	* Check if this fault address is flagged for special treatment,
695	* which means we'll have to figure out the physical address and
696	* check flags associated with it.
697	*
698	* ASSUME that we can limit any special access handling to pages
699	* in page tables which the guest believes to be present.
700	*/
701	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
702	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
703	# else
704	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
705	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
706	PPGMPAGE pPage;
707	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
708	if (RT_FAILURE(rc))
709	{
710	/*
711	* When the guest accesses invalid physical memory (e.g. probing
712	* of RAM or accessing a remapped MMIO range), then we'll fall
713	* back to the recompiler to emulate the instruction.
714	*/
715	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
716	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersInvalid);
717	return VINF_EM_RAW_EMULATE_INSTR;
718	}
719
720	/*
721	* Any handlers for this page?
722	*/
723	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
724	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
725	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, &GstWalk));
726	# else
727	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage));
728	# endif
729
730	STAM_PROFILE_START(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
731
732	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
733	if (uErr & X86_TRAP_PF_P)
734	{
735	/*
736	* The page isn't marked, but it might still be monitored by a virtual page access handler.
737	* (ASSUMES no temporary disabling of virtual handlers.)
738	*/
739	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
740	* we should correct both the shadow page table and physical memory flags, and not only check for
741	* accesses within the handler region but for access to pages with virtual handlers. */
742	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
743	if (pCur)
744	{
745	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
746	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
747	\|\| !(uErr & X86_TRAP_PF_P)
748	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
749	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
750
751	if ( pvFault - pCur->Core.Key < pCur->cb
752	&& ( uErr & X86_TRAP_PF_RW
753	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
754	{
755	# ifdef IN_RC
756	STAM_PROFILE_START(&pCur->Stat, h);
757	pgmUnlock(pVM);
758	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
759	pgmLock(pVM);
760	STAM_PROFILE_STOP(&pCur->Stat, h);
761	# else
762	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
763	# endif
764	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eHandlersVirtualUnmarked);
765	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
766	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndVirt; });
767	return rc;
768	}
769	}
770	}
771	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
772
773	/*
774	* We are here only if page is present in Guest page tables and
775	* trap is not handled by our handlers.
776	*
777	* Check it for page out-of-sync situation.
778	*/
779	if (!(uErr & X86_TRAP_PF_P))
780	{
781	/*
782	* Page is not present in our page tables. Try to sync it!
783	*/
784	if (uErr & X86_TRAP_PF_US)
785	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
786	else /* supervisor */
787	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
788
789	if (PGM_PAGE_IS_BALLOONED(pPage))
790	{
791	/* Emulate reads from ballooned pages as they are not present in
792	our shadow page tables. (Required for e.g. Solaris guests; soft
793	ecc, random nr generator.) */
794	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
795	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
796	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncBallloon));
797	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
798	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2HndUnhandled; });
799	return rc;
800	}
801
802	# if defined(LOG_ENABLED) && !defined(IN_RING0)
803	RTGCPHYS GCPhys2;
804	uint64_t fPageGst2;
805	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
806	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
807	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
808	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
809	# else
810	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
811	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
812	# endif
813	# endif /* LOG_ENABLED */
814
815	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
816	if ( !GstWalk.Core.fEffectiveUS
817	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
818	{
819	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
820	if ( pvFault == (RTGCPTR)pRegFrame->eip
821	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
822	# ifdef CSAM_DETECT_NEW_CODE_PAGES
823	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
824	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
825	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
826	)
827	{
828	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
829	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
830	if (rc != VINF_SUCCESS)
831	{
832	/*
833	* CSAM needs to perform a job in ring 3.
834	*
835	* Sync the page before going to the host context; otherwise we'll end up in a loop if
836	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
837	*/
838	LogFlow(("CSAM ring 3 job\n"));
839	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
840	AssertRC(rc2);
841
842	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
843	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2CSAM; });
844	return rc;
845	}
846	}
847	# ifdef CSAM_DETECT_NEW_CODE_PAGES
848	else if ( uErr == X86_TRAP_PF_RW
849	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
850	&& pRegFrame->ecx < 0x10000)
851	{
852	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
853	* to detect loading of new code pages.
854	*/
855
856	/*
857	* Decode the instruction.
858	*/
859	RTGCPTR PC;
860	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
861	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
862	if (rc == VINF_SUCCESS)
863	{
864	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
865	uint32_t cbOp;
866	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
867
868	/* For now we'll restrict this to rep movsw/d instructions */
869	if ( rc == VINF_SUCCESS
870	&& pDis->pCurInstr->opcode == OP_MOVSWD
871	&& (pDis->prefix & PREFIX_REP))
872	{
873	CSAMMarkPossibleCodePage(pVM, pvFault);
874	}
875	}
876	}
877	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
878
879	/*
880	* Mark this page as safe.
881	*/
882	/** @todo not correct for pages that contain both code and data!! */
883	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
884	CSAMMarkPage(pVM, pvFault, true);
885	}
886	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
887	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
888	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
889	# else
890	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
891	# endif
892	if (RT_SUCCESS(rc))
893	{
894	/* The page was successfully synced, return to the guest. */
895	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
896	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSync; });
897	return VINF_SUCCESS;
898	}
899	}
900	else /* uErr & X86_TRAP_PF_P: */
901	{
902	/*
903	* Write protected pages are made writable when the guest makes the
904	* first write to it. This happens for pages that are shared, write
905	* monitored or not yet allocated.
906	*
907	* We may also end up here when CR0.WP=0 in the guest.
908	*
909	* Also, a side effect of not flushing global PDEs are out of sync
910	* pages due to physical monitored regions, that are no longer valid.
911	* Assume for now it only applies to the read/write flag.
912	*/
913	if (uErr & X86_TRAP_PF_RW)
914	{
915	/*
916	* Check if it is a read-only page.
917	*/
918	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
919	{
920	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
921	Assert(!PGM_PAGE_IS_ZERO(pPage));
922	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
923
924	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
925	if (rc != VINF_SUCCESS)
926	{
927	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
928	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
929	/// @todo STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2MakeWritable; });
930	return rc;
931	}
932	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
933	return VINF_EM_NO_MEMORY;
934	}
935
936	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
937	/*
938	* Check to see if we need to emulate the instruction if CR0.WP=0.
939	*/
940	if ( !GstWalk.Core.fEffectiveRW
941	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
942	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
943	{
944	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
945	rc = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
946	if (RT_SUCCESS(rc))
947	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulInRZ);
948	else
949	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eWPEmulToR3);
950	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
951	/// @todo STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2WPEmulation; });
952	return rc;
953	}
954	# endif
955	/// @todo count the above case; else
956	if (uErr & X86_TRAP_PF_US)
957	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
958	else /* supervisor */
959	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
960
961	/*
962	* Sync the page.
963	*
964	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
965	* page is not present, which is not true in this case.
966	*/
967	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
968	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
969	# else
970	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
971	# endif
972	if (RT_SUCCESS(rc))
973	{
974	/*
975	* Page was successfully synced, return to guest but invalidate
976	* the TLB first as the page is very likely to be in it.
977	*/
978	# if PGM_SHW_TYPE == PGM_TYPE_EPT
979	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
980	# else
981	PGM_INVL_PG(pVCpu, pvFault);
982	# endif
983	# ifdef VBOX_STRICT
984	RTGCPHYS GCPhys2;
985	uint64_t fPageGst;
986	if (!pVM->pgm.s.fNestedPaging)
987	{
988	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
989	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
990	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
991	}
992	uint64_t fPageShw;
993	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
994	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */, ("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
995	# endif /* VBOX_STRICT */
996	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
997	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.StatRZTrap0eTime2OutOfSyncHndObs; });
998	return VINF_SUCCESS;
999	}
1000	}
1001	/** @todo else: WTF are we here? */
1002
1003	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1004	/*
1005	* Check for VMM page flags vs. Guest page flags consistency.
1006	* Currently only for debug purposes.
1007	*/
1008	if (RT_SUCCESS(rc))
1009	{
1010	/* Get guest page flags. */
1011	uint64_t fPageGst;
1012	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1013	if (RT_SUCCESS(rc))
1014	{
1015	uint64_t fPageShw;
1016	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1017
1018	/*
1019	* Compare page flags.
1020	* Note: we have AVL, A, D bits desynched.
1021	*/
1022	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1023	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n", pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1024	}
1025	else
1026	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1027	}
1028	else
1029	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1030	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1031	}
1032	STAM_PROFILE_STOP(&pVCpu->pgm.s.StatRZTrap0eTimeOutOfSync, c);
1033
1034	/** @todo This point is only ever reached when something goes awry. The
1035	* conclusion here is wrong, it is not a guest trap! Will fix in
1036	* a bit... */
1037
1038	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1039	/*
1040	* Conclusion, this is a guest trap.
1041	*/
1042	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
1043	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0eGuestPFUnh);
1044	return VINF_EM_RAW_GUEST_TRAP;
1045	# else
1046	/* present, but not a monitored page; perhaps the guest is probing physical memory */
1047	return VINF_EM_RAW_EMULATE_INSTR;
1048	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
1049
1050
1051	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1052
1053	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1054	return VERR_INTERNAL_ERROR;
1055	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1056	}
1057	#endif /* !IN_RING3 */
1058
1059
1060	/**
1061	* Emulation of the invlpg instruction.
1062	*
1063	*
1064	* @returns VBox status code.
1065	*
1066	* @param pVCpu The VMCPU handle.
1067	* @param GCPtrPage Page to invalidate.
1068	*
1069	* @remark ASSUMES that the guest is updating before invalidating. This order
1070	* isn't required by the CPU, so this is speculative and could cause
1071	* trouble.
1072	* @remark No TLB shootdown is done on any other VCPU as we assume that
1073	* invlpg emulation is the only reason for calling this function.
1074	* (The guest has to shoot down TLB entries on other CPUs itself)
1075	* Currently true, but keep in mind!
1076	*
1077	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1078	*/
1079	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1080	{
1081	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1082	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1083	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1084	int rc;
1085	PVM pVM = pVCpu->CTX_SUFF(pVM);
1086	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1087
1088	Assert(PGMIsLockOwner(pVM));
1089
1090	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1091
1092	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1093	if (pPool->cDirtyPages)
1094	pgmPoolResetDirtyPages(pVM);
1095	# endif
1096
1097	/*
1098	* Get the shadow PD entry and skip out if this PD isn't present.
1099	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1100	*/
1101	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1102	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1103	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1104
1105	/* Fetch the pgm pool shadow descriptor. */
1106	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1107	Assert(pShwPde);
1108
1109	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1110	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1111	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
1112
1113	/* If the shadow PDPE isn't present, then skip the invalidate. */
1114	if (!pPdptDst->a[iPdpt].n.u1Present)
1115	{
1116	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1117	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1118	return VINF_SUCCESS;
1119	}
1120
1121	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1122	PPGMPOOLPAGE pShwPde = NULL;
1123	PX86PDPAE pPDDst;
1124
1125	/* Fetch the pgm pool shadow descriptor. */
1126	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1127	AssertRCSuccessReturn(rc, rc);
1128	Assert(pShwPde);
1129
1130	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1131	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1132
1133	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1134	/* PML4 */
1135	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1136	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1137	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1138	PX86PDPAE pPDDst;
1139	PX86PDPT pPdptDst;
1140	PX86PML4E pPml4eDst;
1141	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1142	if (rc != VINF_SUCCESS)
1143	{
1144	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1145	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1146	return VINF_SUCCESS;
1147	}
1148	Assert(pPDDst);
1149
1150	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1151	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1152
1153	if (!pPdpeDst->n.u1Present)
1154	{
1155	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1156	return VINF_SUCCESS;
1157	}
1158
1159	/* Fetch the pgm pool shadow descriptor. */
1160	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1161	Assert(pShwPde);
1162
1163	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1164
1165	const SHWPDE PdeDst = *pPdeDst;
1166	if (!PdeDst.n.u1Present)
1167	{
1168	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1169	return VINF_SUCCESS;
1170	}
1171
1172	# if defined(IN_RC)
1173	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1174	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1175	# endif
1176
1177	/*
1178	* Get the guest PD entry and calc big page.
1179	*/
1180	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1181	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1182	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1183	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1184	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1185	unsigned iPDSrc = 0;
1186	# if PGM_GST_TYPE == PGM_TYPE_PAE
1187	X86PDPE PdpeSrcIgn;
1188	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1189	# else /* AMD64 */
1190	PX86PML4E pPml4eSrcIgn;
1191	X86PDPE PdpeSrcIgn;
1192	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1193	# endif
1194	GSTPDE PdeSrc;
1195
1196	if (pPDSrc)
1197	PdeSrc = pPDSrc->a[iPDSrc];
1198	else
1199	PdeSrc.u = 0;
1200	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1201	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1202
1203	# ifdef IN_RING3
1204	/*
1205	* If a CR3 Sync is pending we may ignore the invalidate page operation
1206	* depending on the kind of sync and if it's a global page or not.
1207	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1208	*/
1209	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1210	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1211	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1212	&& fIsBigPage
1213	&& PdeSrc.b.u1Global
1214	)
1215	)
1216	# else
1217	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1218	# endif
1219	{
1220	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePageSkipped));
1221	return VINF_SUCCESS;
1222	}
1223	# endif /* IN_RING3 */
1224
1225	/*
1226	* Deal with the Guest PDE.
1227	*/
1228	rc = VINF_SUCCESS;
1229	if (PdeSrc.n.u1Present)
1230	{
1231	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1232	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1233	# ifndef PGM_WITHOUT_MAPPING
1234	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1235	{
1236	/*
1237	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1238	*/
1239	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1240	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1241	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1242	}
1243	else
1244	# endif /* !PGM_WITHOUT_MAPPING */
1245	if (!fIsBigPage)
1246	{
1247	/*
1248	* 4KB - page.
1249	*/
1250	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1251	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1252
1253	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1254	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1255	if (pShwPage->cModifications)
1256	pShwPage->cModifications = 1;
1257	# endif
1258
1259	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1260	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1261	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1262	# endif
1263	if (pShwPage->GCPhys == GCPhys)
1264	{
1265	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1266	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1267	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1268	if (pPT->a[iPTEDst].n.u1Present)
1269	{
1270	/* This is very unlikely with caching/monitoring enabled. */
1271	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1272	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1273	}
1274	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1275	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1276	if (RT_SUCCESS(rc))
1277	rc = VINF_SUCCESS;
1278	# endif
1279	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4KBPages));
1280	PGM_INVL_PG(pVCpu, GCPtrPage);
1281	}
1282	else
1283	{
1284	/*
1285	* The page table address changed.
1286	*/
1287	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1288	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1289	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1290	ASMAtomicWriteSize(pPdeDst, 0);
1291	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1292	PGM_INVL_VCPU_TLBS(pVCpu);
1293	}
1294	}
1295	else
1296	{
1297	/*
1298	* 2/4MB - page.
1299	*/
1300	/* Before freeing the page, check if anything really changed. */
1301	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1302	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
1303	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1304	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1305	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1306	# endif
1307	if ( pShwPage->GCPhys == GCPhys
1308	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1309	{
1310	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1311	/** @todo PAT */
1312	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1313	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1314	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1315	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1316	{
1317	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1318	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1319	# if defined(IN_RC)
1320	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1321	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1322	# endif
1323	return VINF_SUCCESS;
1324	}
1325	}
1326
1327	/*
1328	* Ok, the page table is present and it's been changed in the guest.
1329	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1330	* We could do this for some flushes in GC too, but we need an algorithm for
1331	* deciding which 4MB pages containing code likely to be executed very soon.
1332	*/
1333	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1334	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1335	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1336	ASMAtomicWriteSize(pPdeDst, 0);
1337	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePage4MBPages));
1338	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1339	}
1340	}
1341	else
1342	{
1343	/*
1344	* Page directory is not present, mark shadow PDE not present.
1345	*/
1346	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1347	{
1348	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1349	ASMAtomicWriteSize(pPdeDst, 0);
1350	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDNPs));
1351	PGM_INVL_PG(pVCpu, GCPtrPage);
1352	}
1353	else
1354	{
1355	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1356	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,InvalidatePagePDMappings));
1357	}
1358	}
1359	# if defined(IN_RC)
1360	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1361	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
1362	# endif
1363	return rc;
1364
1365	#else /* guest real and protected mode */
1366	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1367	return VINF_SUCCESS;
1368	#endif
1369	}
1370
1371
1372	/**
1373	* Update the tracking of shadowed pages.
1374	*
1375	* @param pVCpu The VMCPU handle.
1376	* @param pShwPage The shadow page.
1377	* @param HCPhys The physical page we is being dereferenced.
1378	* @param iPte Shadow PTE index
1379	*/
1380	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1381	{
1382	PVM pVM = pVCpu->CTX_SUFF(pVM);
1383
1384	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1385	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1386
1387	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1388	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1389	* 2. write protect all shadowed pages. I.e. implement caching.
1390	*/
1391	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1392
1393	/*
1394	* Find the guest address.
1395	*/
1396	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1397	pRam;
1398	pRam = pRam->CTX_SUFF(pNext))
1399	{
1400	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1401	while (iPage-- > 0)
1402	{
1403	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1404	{
1405	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1406
1407	Assert(pShwPage->cPresent);
1408	Assert(pPool->cPresent);
1409	pShwPage->cPresent--;
1410	pPool->cPresent--;
1411
1412	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1413	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1414	return;
1415	}
1416	}
1417	}
1418
1419	for (;;)
1420	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1421	}
1422
1423
1424	/**
1425	* Update the tracking of shadowed pages.
1426	*
1427	* @param pVCpu The VMCPU handle.
1428	* @param pShwPage The shadow page.
1429	* @param u16 The top 16-bit of the pPage->HCPhys.
1430	* @param pPage Pointer to the guest page. this will be modified.
1431	* @param iPTDst The index into the shadow table.
1432	*/
1433	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1434	{
1435	PVM pVM = pVCpu->CTX_SUFF(pVM);
1436	/*
1437	* Just deal with the simple first time here.
1438	*/
1439	if (!u16)
1440	{
1441	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1442	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1443	/* Save the page table index. */
1444	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1445	}
1446	else
1447	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1448
1449	/* write back */
1450	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1451	PGM_PAGE_SET_TRACKING(pPage, u16);
1452
1453	/* update statistics. */
1454	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1455	pShwPage->cPresent++;
1456	if (pShwPage->iFirstPresent > iPTDst)
1457	pShwPage->iFirstPresent = iPTDst;
1458	}
1459
1460
1461	/**
1462	* Modifies a shadow PTE to account for access handlers.
1463	*
1464	* @param pVM The VM handle.
1465	* @param pPage The page in question.
1466	* @param fPteSrc The flags of the source PTE.
1467	* @param pPteDst The shadow PTE (output).
1468	*/
1469	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint32_t fPteSrc, PSHWPTE pPteDst)
1470	{
1471	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1472	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1473	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1474	{
1475	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1476	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1477	pPteDst->n.u1Present = 1;
1478	pPteDst->n.u1Execute = 1;
1479	pPteDst->n.u1IgnorePAT = 1;
1480	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1481	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1482	#else
1483	pPteDst->u = (fPteSrc & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1484	\| PGM_PAGE_GET_HCPHYS(pPage);
1485	#endif
1486	}
1487	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1488	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1489	else if ( PGM_PAGE_IS_MMIO(pPage)
1490	# if PGM_SHW_TYPE != PGM_TYPE_EPT
1491	&& ( (fPteSrc & (X86_PTE_RW /\| X86_PTE_D \| X86_PTE_A/ \| X86_PTE_US )) /* #PF handles D & A first. */
1492	== (X86_PTE_RW /\| X86_PTE_D \| X86_PTE_A/)
1493	\|\| BTH_IS_NP_ACTIVE(pVM) )
1494	# endif
1495	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1496	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1497	# endif
1498	)
1499	{
1500	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1501	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1502	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1503	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1504	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1505	pPteDst->n.u1Present = 0;
1506	pPteDst->n.u1Write = 1;
1507	pPteDst->n.u1Execute = 0;
1508	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1509	pPteDst->n.u3EMT = 7;
1510	# else
1511	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1512	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P;
1513	# endif
1514	}
1515	# endif
1516	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1517	else
1518	{
1519	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1520	pPteDst->u = 0;
1521	}
1522	/** @todo count these kinds of entries. */
1523	}
1524
1525
1526	/**
1527	* Creates a 4K shadow page for a guest page.
1528	*
1529	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1530	* physical address. The PdeSrc argument only the flags are used. No page
1531	* structured will be mapped in this function.
1532	*
1533	* @param pVCpu The VMCPU handle.
1534	* @param pPteDst Destination page table entry.
1535	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1536	* Can safely assume that only the flags are being used.
1537	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1538	* @param pShwPage Pointer to the shadow page.
1539	* @param iPTDst The index into the shadow table.
1540	*
1541	* @remark Not used for 2/4MB pages!
1542	*/
1543	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1544	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1545	{
1546	if ( PteSrc.n.u1Present
1547	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1548	{
1549	PVM pVM = pVCpu->CTX_SUFF(pVM);
1550
1551	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1552	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1553	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1554	if (pShwPage->fDirty)
1555	{
1556	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1557	PX86PTPAE pGstPT;
1558
1559	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1560	pGstPT->a[iPTDst].u = PteSrc.u;
1561	}
1562	# endif
1563	/*
1564	* Find the ram range.
1565	*/
1566	PPGMPAGE pPage;
1567	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1568	if (RT_SUCCESS(rc))
1569	{
1570	/* Ignore ballooned pages.
1571	Don't return errors or use a fatal assert here as part of a
1572	shadow sync range might included ballooned pages. */
1573	if (PGM_PAGE_IS_BALLOONED(pPage))
1574	{
1575	Assert(!pPteDst->n.u1Present); /** @todo user tracking needs updating if this triggers. */
1576	return;
1577	}
1578
1579	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1580	/* Make the page writable if necessary. */
1581	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1582	&& ( PGM_PAGE_IS_ZERO(pPage)
1583	\|\| ( PteSrc.n.u1Write
1584	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1585	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1586	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1587	# endif
1588	# ifdef VBOX_WITH_PAGE_SHARING
1589	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1590	# endif
1591	)
1592	)
1593	)
1594	{
1595	rc = pgmPhysPageMakeWritable(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1596	AssertRC(rc);
1597	}
1598	#endif
1599
1600	/*
1601	* Make page table entry.
1602	*/
1603	SHWPTE PteDst;
1604	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1605	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage,
1606	PteSrc.u & ~( X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT
1607	\| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW),
1608	&PteDst);
1609	else
1610	{
1611	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1612	/*
1613	* If the page or page directory entry is not marked accessed,
1614	* we mark the page not present.
1615	*/
1616	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1617	{
1618	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1619	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,AccessedPage));
1620	PteDst.u = 0;
1621	}
1622	/*
1623	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1624	* when the page is modified.
1625	*/
1626	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1627	{
1628	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPage));
1629	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1630	\| PGM_PAGE_GET_HCPHYS(pPage)
1631	\| PGM_PTFLAGS_TRACK_DIRTY;
1632	}
1633	else
1634	#endif
1635	{
1636	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageSkipped));
1637	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1638	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1639	PteDst.n.u1Present = 1;
1640	PteDst.n.u1Write = 1;
1641	PteDst.n.u1Execute = 1;
1642	PteDst.n.u1IgnorePAT = 1;
1643	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1644	/* PteDst.n.u1Size = 0 */
1645	#else
1646	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1647	\| PGM_PAGE_GET_HCPHYS(pPage);
1648	#endif
1649	}
1650
1651	/*
1652	* Make sure only allocated pages are mapped writable.
1653	*/
1654	if ( PteDst.n.u1Write
1655	&& PteDst.n.u1Present
1656	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1657	{
1658	/* Still applies to shared pages. */
1659	Assert(!PGM_PAGE_IS_ZERO(pPage));
1660	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet. Why, isn't it? */
1661	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1662	}
1663	}
1664
1665	/*
1666	* Keep user track up to date.
1667	*/
1668	if (PteDst.n.u1Present)
1669	{
1670	if (!pPteDst->n.u1Present)
1671	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1672	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1673	{
1674	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1675	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK, iPTDst);
1676	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1677	}
1678	}
1679	else if (pPteDst->n.u1Present)
1680	{
1681	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1682	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK, iPTDst);
1683	}
1684
1685	/*
1686	* Update statistics and commit the entry.
1687	*/
1688	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1689	if (!PteSrc.n.u1Global)
1690	pShwPage->fSeenNonGlobal = true;
1691	#endif
1692	ASMAtomicWriteSize(pPteDst, PteDst.u);
1693	return;
1694	}
1695
1696	/** @todo count these three different kinds. */
1697	Log2(("SyncPageWorker: invalid address in Pte\n"));
1698	}
1699	else if (!PteSrc.n.u1Present)
1700	Log2(("SyncPageWorker: page not present in Pte\n"));
1701	else
1702	Log2(("SyncPageWorker: invalid Pte\n"));
1703
1704	/*
1705	* The page is not present or the PTE is bad. Replace the shadow PTE by
1706	* an empty entry, making sure to keep the user tracking up to date.
1707	*/
1708	if (pPteDst->n.u1Present)
1709	{
1710	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1711	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, pPteDst->u & SHW_PTE_PG_MASK, iPTDst);
1712	}
1713	ASMAtomicWriteSize(pPteDst, 0);
1714	}
1715
1716
1717	/**
1718	* Syncs a guest OS page.
1719	*
1720	* There are no conflicts at this point, neither is there any need for
1721	* page table allocations.
1722	*
1723	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1724	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1725	*
1726	* @returns VBox status code.
1727	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1728	* @param pVCpu The VMCPU handle.
1729	* @param PdeSrc Page directory entry of the guest.
1730	* @param GCPtrPage Guest context page address.
1731	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1732	* @param uErr Fault error (X86_TRAP_PF_*).
1733	*/
1734	PGM_BTH_DECL(int, SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1735	{
1736	PVM pVM = pVCpu->CTX_SUFF(pVM);
1737	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1738	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1739
1740	Assert(PGMIsLockOwner(pVM));
1741
1742	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1743	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1744	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1745	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1746	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1747
1748	/*
1749	* Assert preconditions.
1750	*/
1751	Assert(PdeSrc.n.u1Present);
1752	Assert(cPages);
1753	# if 0 /* rarely useful; leave for debugging. */
1754	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1755	# endif
1756
1757	/*
1758	* Get the shadow PDE, find the shadow page table in the pool.
1759	*/
1760	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1761	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1762	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
1763
1764	/* Fetch the pgm pool shadow descriptor. */
1765	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1766	Assert(pShwPde);
1767
1768	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1769	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1770	PPGMPOOLPAGE pShwPde = NULL;
1771	PX86PDPAE pPDDst;
1772
1773	/* Fetch the pgm pool shadow descriptor. */
1774	int rc2 = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
1775	AssertRCSuccessReturn(rc2, rc2);
1776	Assert(pShwPde);
1777
1778	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
1779	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1780
1781	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1782	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1783	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1784	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1785	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1786
1787	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1788	AssertRCSuccessReturn(rc2, rc2);
1789	Assert(pPDDst && pPdptDst);
1790	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1791	# endif
1792	SHWPDE PdeDst = *pPdeDst;
1793
1794	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1795	if (!PdeDst.n.u1Present)
1796	{
1797	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1798	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
1799	return VINF_SUCCESS; /* force the instruction to be executed again. */
1800	}
1801
1802	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1803	Assert(pShwPage);
1804
1805	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1806	/* Fetch the pgm pool shadow descriptor. */
1807	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1808	Assert(pShwPde);
1809	# endif
1810
1811	# if defined(IN_RC)
1812	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
1813	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
1814	# endif
1815
1816	/*
1817	* Check that the page is present and that the shadow PDE isn't out of sync.
1818	*/
1819	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1820	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1821	RTGCPHYS GCPhys;
1822	if (!fBigPage)
1823	{
1824	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1825	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1826	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1827	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1828	# endif
1829	}
1830	else
1831	{
1832	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
1833	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1834	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1835	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1836	# endif
1837	}
1838	if ( fPdeValid
1839	&& pShwPage->GCPhys == GCPhys
1840	&& PdeSrc.n.u1Present
1841	&& PdeSrc.n.u1User == PdeDst.n.u1User
1842	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1843	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1844	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1845	# endif
1846	)
1847	{
1848	/*
1849	* Check that the PDE is marked accessed already.
1850	* Since we set the accessed bit before getting here on a #PF, this
1851	* check is only meant for dealing with non-#PF'ing paths.
1852	*/
1853	if (PdeSrc.n.u1Accessed)
1854	{
1855	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1856	if (!fBigPage)
1857	{
1858	/*
1859	* 4KB Page - Map the guest page table.
1860	*/
1861	PGSTPT pPTSrc;
1862	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1863	if (RT_SUCCESS(rc))
1864	{
1865	# ifdef PGM_SYNC_N_PAGES
1866	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1867	if ( cPages > 1
1868	&& !(uErr & X86_TRAP_PF_P)
1869	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1870	{
1871	/*
1872	* This code path is currently only taken when the caller is PGMTrap0eHandler
1873	* for non-present pages!
1874	*
1875	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1876	* deal with locality.
1877	*/
1878	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1879	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1880	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1881	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1882	# else
1883	const unsigned offPTSrc = 0;
1884	# endif
1885	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1886	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1887	iPTDst = 0;
1888	else
1889	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1890	for (; iPTDst < iPTDstEnd; iPTDst++)
1891	{
1892	if (!pPTDst->a[iPTDst].n.u1Present)
1893	{
1894	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1895	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1896	NOREF(GCPtrCurPage);
1897	#ifndef IN_RING0
1898	/*
1899	* Assuming kernel code will be marked as supervisor - and not as user level
1900	* and executed using a conforming code selector - And marked as readonly.
1901	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1902	*/
1903	PPGMPAGE pPage;
1904	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1905	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1906	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1907	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1908	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1909	)
1910	#endif /* else: CSAM not active */
1911	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1912	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1913	GCPtrCurPage, PteSrc.n.u1Present,
1914	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1915	PteSrc.n.u1User & PdeSrc.n.u1User,
1916	(uint64_t)PteSrc.u,
1917	(uint64_t)pPTDst->a[iPTDst].u,
1918	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1919	}
1920	}
1921	}
1922	else
1923	# endif /* PGM_SYNC_N_PAGES */
1924	{
1925	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1926	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1927	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1928	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1929	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1930	GCPtrPage, PteSrc.n.u1Present,
1931	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1932	PteSrc.n.u1User & PdeSrc.n.u1User,
1933	(uint64_t)PteSrc.u,
1934	(uint64_t)pPTDst->a[iPTDst].u,
1935	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1936	}
1937	}
1938	else /* MMIO or invalid page: emulated in #PF handler. */
1939	{
1940	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1941	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1942	}
1943	}
1944	else
1945	{
1946	/*
1947	* 4/2MB page - lazy syncing shadow 4K pages.
1948	* (There are many causes of getting here, it's no longer only CSAM.)
1949	*/
1950	/* Calculate the GC physical address of this 4KB shadow page. */
1951	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1952	/* Find ram range. */
1953	PPGMPAGE pPage;
1954	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1955	if (RT_SUCCESS(rc))
1956	{
1957	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1958
1959	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1960	/* Try to make the page writable if necessary. */
1961	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1962	&& ( PGM_PAGE_IS_ZERO(pPage)
1963	\|\| ( PdeSrc.n.u1Write
1964	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1965	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1966	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1967	# endif
1968	# ifdef VBOX_WITH_PAGE_SHARING
1969	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1970	# endif
1971	)
1972	)
1973	)
1974	{
1975	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1976	AssertRC(rc);
1977	}
1978	# endif
1979
1980	/*
1981	* Make shadow PTE entry.
1982	*/
1983	SHWPTE PteDst;
1984	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1985	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage,
1986	PdeSrc.u & ~( X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK
1987	\| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT),
1988	&PteDst);
1989	else
1990	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1991	\| PGM_PAGE_GET_HCPHYS(pPage);
1992
1993	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1994	if ( PteDst.n.u1Present
1995	&& !pPTDst->a[iPTDst].n.u1Present)
1996	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1997
1998	/* Make sure only allocated pages are mapped writable. */
1999	if ( PteDst.n.u1Write
2000	&& PteDst.n.u1Present
2001	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2002	{
2003	/* Still applies to shared pages. */
2004	Assert(!PGM_PAGE_IS_ZERO(pPage));
2005	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
2006	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2007	}
2008
2009	ASMAtomicWriteSize(&pPTDst->a[iPTDst], PteDst.u);
2010
2011	/*
2012	* If the page is not flagged as dirty and is writable, then make it read-only
2013	* at PD level, so we can set the dirty bit when the page is modified.
2014	*
2015	* ASSUMES that page access handlers are implemented on page table entry level.
2016	* Thus we will first catch the dirty access and set PDE.D and restart. If
2017	* there is an access handler, we'll trap again and let it work on the problem.
2018	*/
2019	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2020	* As for invlpg, it simply frees the whole shadow PT.
2021	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2022	if ( !PdeSrc.b.u1Dirty
2023	&& PdeSrc.b.u1Write)
2024	{
2025	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2026	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2027	PdeDst.n.u1Write = 0;
2028	}
2029	else
2030	{
2031	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2032	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2033	}
2034	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2035	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2036	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2037	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2038	}
2039	else
2040	{
2041	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2042	/** @todo must wipe the shadow page table in this case. */
2043	}
2044	}
2045	# if defined(IN_RC)
2046	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2047	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2048	# endif
2049	return VINF_SUCCESS;
2050	}
2051
2052	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDNAs));
2053	}
2054	else if (fPdeValid)
2055	{
2056	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2057	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2058	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2059	}
2060	else
2061	{
2062	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2063	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2064	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2065	}
2066
2067	/*
2068	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2069	* Yea, I'm lazy.
2070	*/
2071	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2072	ASMAtomicWriteSize(pPdeDst, 0);
2073
2074	# if defined(IN_RC)
2075	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2076	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2077	# endif
2078	PGM_INVL_VCPU_TLBS(pVCpu);
2079	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2080
2081
2082	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2083	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2084	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2085	&& !defined(IN_RC)
2086
2087	# ifdef PGM_SYNC_N_PAGES
2088	/*
2089	* Get the shadow PDE, find the shadow page table in the pool.
2090	*/
2091	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2092	X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
2093
2094	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2095	X86PDEPAE PdeDst = pgmShwGetPaePDE(&pVCpu->pgm.s, GCPtrPage);
2096
2097	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2098	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2099	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2100	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2101	X86PDEPAE PdeDst;
2102	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2103
2104	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2105	AssertRCSuccessReturn(rc, rc);
2106	Assert(pPDDst && pPdptDst);
2107	PdeDst = pPDDst->a[iPDDst];
2108	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2109	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2110	PEPTPD pPDDst;
2111	EPTPDE PdeDst;
2112
2113	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2114	if (rc != VINF_SUCCESS)
2115	{
2116	AssertRC(rc);
2117	return rc;
2118	}
2119	Assert(pPDDst);
2120	PdeDst = pPDDst->a[iPDDst];
2121	# endif
2122	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2123	if (!PdeDst.n.u1Present)
2124	{
2125	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2126	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2127	return VINF_SUCCESS; /* force the instruction to be executed again. */
2128	}
2129
2130	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2131	if (PdeDst.n.u1Size)
2132	{
2133	Assert(pVM->pgm.s.fNestedPaging);
2134	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2135	return VINF_SUCCESS;
2136	}
2137
2138	/* Mask away the page offset. */
2139	GCPtrPage &= ~((RTGCPTR)0xfff);
2140
2141	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2142	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2143
2144	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2145	if ( cPages > 1
2146	&& !(uErr & X86_TRAP_PF_P)
2147	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2148	{
2149	/*
2150	* This code path is currently only taken when the caller is PGMTrap0eHandler
2151	* for non-present pages!
2152	*
2153	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2154	* deal with locality.
2155	*/
2156	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2157	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2158	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2159	iPTDst = 0;
2160	else
2161	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2162	for (; iPTDst < iPTDstEnd; iPTDst++)
2163	{
2164	if (!pPTDst->a[iPTDst].n.u1Present)
2165	{
2166	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2167	GSTPTE PteSrc;
2168
2169	/* Fake the page table entry */
2170	PteSrc.u = GCPtrCurPage;
2171	PteSrc.n.u1Present = 1;
2172	PteSrc.n.u1Dirty = 1;
2173	PteSrc.n.u1Accessed = 1;
2174	PteSrc.n.u1Write = 1;
2175	PteSrc.n.u1User = 1;
2176
2177	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2178
2179	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2180	GCPtrCurPage, PteSrc.n.u1Present,
2181	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2182	PteSrc.n.u1User & PdeSrc.n.u1User,
2183	(uint64_t)PteSrc.u,
2184	(uint64_t)pPTDst->a[iPTDst].u,
2185	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2186
2187	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2188	break;
2189	}
2190	else
2191	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, pPTDst->a[iPTDst].u));
2192	}
2193	}
2194	else
2195	# endif /* PGM_SYNC_N_PAGES */
2196	{
2197	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2198	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2199	GSTPTE PteSrc;
2200
2201	/* Fake the page table entry */
2202	PteSrc.u = GCPtrCurPage;
2203	PteSrc.n.u1Present = 1;
2204	PteSrc.n.u1Dirty = 1;
2205	PteSrc.n.u1Accessed = 1;
2206	PteSrc.n.u1Write = 1;
2207	PteSrc.n.u1User = 1;
2208	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2209
2210	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2211	GCPtrPage, PteSrc.n.u1Present,
2212	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2213	PteSrc.n.u1User & PdeSrc.n.u1User,
2214	(uint64_t)PteSrc.u,
2215	(uint64_t)pPTDst->a[iPTDst].u,
2216	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2217	}
2218	return VINF_SUCCESS;
2219
2220	#else
2221	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2222	return VERR_INTERNAL_ERROR;
2223	#endif
2224	}
2225
2226
2227	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2228
2229	/**
2230	* CheckPageFault helper for returning a page fault indicating a non-present
2231	* (NP) entry in the page translation structures.
2232	*
2233	* @returns VINF_EM_RAW_GUEST_TRAP.
2234	* @param pVCpu The virtual CPU to operate on.
2235	* @param uErr The error code of the shadow fault. Corrections to
2236	* TRPM's copy will be made if necessary.
2237	* @param GCPtrPage For logging.
2238	* @param uPageFaultLevel For logging.
2239	*/
2240	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2241	{
2242	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2243	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2244	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2245	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2246	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2247
2248	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2249	return VINF_EM_RAW_GUEST_TRAP;
2250	}
2251
2252
2253	/**
2254	* CheckPageFault helper for returning a page fault indicating a reserved bit
2255	* (RSVD) error in the page translation structures.
2256	*
2257	* @returns VINF_EM_RAW_GUEST_TRAP.
2258	* @param pVCpu The virtual CPU to operate on.
2259	* @param uErr The error code of the shadow fault. Corrections to
2260	* TRPM's copy will be made if necessary.
2261	* @param GCPtrPage For logging.
2262	* @param uPageFaultLevel For logging.
2263	*/
2264	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2265	{
2266	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2267	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2268	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2269
2270	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2271	return VINF_EM_RAW_GUEST_TRAP;
2272	}
2273
2274
2275	/**
2276	* CheckPageFault helper for returning a page protection fault (P).
2277	*
2278	* @returns VINF_EM_RAW_GUEST_TRAP.
2279	* @param pVCpu The virtual CPU to operate on.
2280	* @param uErr The error code of the shadow fault. Corrections to
2281	* TRPM's copy will be made if necessary.
2282	* @param GCPtrPage For logging.
2283	* @param uPageFaultLevel For logging.
2284	*/
2285	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2286	{
2287	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyTrackRealPF));
2288	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2289	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2290	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2291
2292	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2293	return VINF_EM_RAW_GUEST_TRAP;
2294	}
2295
2296
2297	/**
2298	* Investigate a page fault to identify ones targetted at the guest and to
2299	* handle write protection page faults caused by dirty bit tracking.
2300	*
2301	* This will do detect invalid entries and raise X86_TRAP_PF_RSVD.
2302	*
2303	* @returns VBox status code.
2304	* @param pVCpu The VMCPU handle.
2305	* @param uErr Page fault error code. The X86_TRAP_PF_RSVD flag
2306	* cannot be trusted as it is used for MMIO optimizations.
2307	* @param pPdeSrc Guest page directory entry.
2308	* @param GCPtrPage Guest context page address.
2309	*/
2310	PGM_BTH_DECL(int, CheckPageFault)(PVMCPU pVCpu, uint32_t uErr, PGSTPDE pPdeSrc, RTGCPTR GCPtrPage)
2311	{
2312	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
2313	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
2314	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2315	bool fMaybeNXEFault = (uErr & X86_TRAP_PF_ID) && GST_IS_NX_ACTIVE(pVCpu);
2316	# endif
2317	bool fMaybeWriteProtFault = fWriteFault && (fUserLevelFault \|\| CPUMIsGuestR0WriteProtEnabled(pVCpu));
2318	PVM pVM = pVCpu->CTX_SUFF(pVM);
2319	int rc;
2320
2321	LogFlow(("CheckPageFault: GCPtrPage=%RGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
2322
2323	/*
2324	* Note! For PAE it is safe to assume that bad guest physical addresses
2325	* (which returns all FFs) in the translation tables will cause
2326	* #PF(RSVD). The same will be the case for long mode provided the
2327	* physical address width is less than 52 bits - this we ASSUME.
2328	*
2329	* Note! No convenient shortcuts here, we have to validate everything!
2330	*/
2331
2332	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2333	/*
2334	* Real page fault? (PML4E level)
2335	*/
2336	PX86PML4 pPml4Src = pgmGstGetLongModePML4Ptr(pVCpu);
2337	if (RT_UNLIKELY(!pPml4Src))
2338	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 0);
2339
2340	PX86PML4E pPml4eSrc = &pPml4Src->a[(GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK];
2341	if (!pPml4eSrc->n.u1Present)
2342	return PGM_BTH_NAME(CheckPageFaultReturnNP)(pVCpu, uErr, GCPtrPage, 0);
2343	if (RT_UNLIKELY(!GST_IS_PML4E_VALID(pVCpu, *pPml4eSrc)))
2344	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 0);
2345	if ( (fMaybeWriteProtFault && !pPml4eSrc->n.u1Write)
2346	\|\| (fMaybeNXEFault && pPml4eSrc->n.u1NoExecute)
2347	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User) )
2348	return PGM_BTH_NAME(CheckPageFaultReturnProt)(pVCpu, uErr, GCPtrPage, 0);
2349
2350	/*
2351	* Real page fault? (PDPE level)
2352	*/
2353	PX86PDPT pPdptSrc;
2354	rc = PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK, &pPdptSrc);
2355	if (RT_FAILURE(rc))
2356	{
2357	AssertMsgReturn(rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS, ("%Rrc\n", rc), rc);
2358	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 1);
2359	}
2360
2361	PX86PDPE pPdpeSrc = &pPdptSrc->a[(GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64];
2362	if (!pPdpeSrc->n.u1Present)
2363	return PGM_BTH_NAME(CheckPageFaultReturnNP)(pVCpu, uErr, GCPtrPage, 1);
2364	if (!GST_IS_PDPE_VALID(pVCpu, *pPdpeSrc))
2365	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 1);
2366	if ( (fMaybeWriteProtFault && !pPdpeSrc->lm.u1Write)
2367	\|\| (fMaybeNXEFault && pPdpeSrc->lm.u1NoExecute)
2368	\|\| (fUserLevelFault && !pPdpeSrc->lm.u1User) )
2369	return PGM_BTH_NAME(CheckPageFaultReturnProt)(pVCpu, uErr, GCPtrPage, 1);
2370
2371	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2372	/*
2373	* Real page fault? (PDPE level)
2374	*/
2375	PX86PDPT pPdptSrc = pgmGstGetPaePDPTPtr(pVCpu);
2376	if (RT_UNLIKELY(!pPdptSrc))
2377	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 1);
2378	/** @todo Handle bad CR3 address. */
2379	PX86PDPE pPdpeSrc = pgmGstGetPaePDPEPtr(pVCpu, GCPtrPage);
2380	if (!pPdpeSrc->n.u1Present)
2381	return PGM_BTH_NAME(CheckPageFaultReturnNP)(pVCpu, uErr, GCPtrPage, 1);
2382	if (!GST_IS_PDPE_VALID(pVCpu, *pPdpeSrc))
2383	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 1);
2384	# endif /* PGM_GST_TYPE == PGM_TYPE_PAE */
2385
2386	/*
2387	* Real page fault? (PDE level)
2388	*/
2389	if (!pPdeSrc->n.u1Present)
2390	return PGM_BTH_NAME(CheckPageFaultReturnNP)(pVCpu, uErr, GCPtrPage, 2);
2391	bool const fBigPage = pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
2392	if (!fBigPage ? !GST_IS_PDE_VALID(pVCpu, pPdeSrc) : !GST_IS_BIG_PDE_VALID(pVCpu, pPdeSrc))
2393	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 2);
2394	if ( (fMaybeWriteProtFault && !pPdeSrc->n.u1Write)
2395	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2396	\|\| (fMaybeNXEFault && pPdeSrc->n.u1NoExecute)
2397	# endif
2398	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
2399	return PGM_BTH_NAME(CheckPageFaultReturnProt)(pVCpu, uErr, GCPtrPage, 2);
2400
2401	/*
2402	* First check the easy case where the page directory has been marked
2403	* read-only to track the dirty bit of an emulated BIG page.
2404	*/
2405	if (fBigPage)
2406	{
2407	/* Mark guest page directory as accessed */
2408	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2409	pPml4eSrc->n.u1Accessed = 1;
2410	pPdpeSrc->lm.u1Accessed = 1;
2411	# endif
2412	pPdeSrc->b.u1Accessed = 1;
2413
2414	/* Mark the entry guest PDE dirty it it's a write access. */
2415	if (fWriteFault)
2416	pPdeSrc->b.u1Dirty = 1;
2417	}
2418	else
2419	{
2420	/*
2421	* Map the guest page table.
2422	*/
2423	PGSTPT pPTSrc;
2424	PGSTPTE pPteSrc;
2425	GSTPTE PteSrc;
2426	rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2427	if (RT_SUCCESS(rc))
2428	{
2429	pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2430	PteSrc.u = pPteSrc->u;
2431	}
2432	else if (rc == VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS)
2433	{
2434	/* All bits in the PTE are set. */
2435	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2436	PteSrc.u = UINT32_MAX;
2437	# else
2438	PteSrc.u = UINT64_MAX;
2439	# endif
2440	pPteSrc = &PteSrc;
2441	}
2442	else
2443	{
2444	AssertRC(rc);
2445	return rc;
2446	}
2447
2448	/*
2449	* Real page fault?
2450	*/
2451	if (!PteSrc.n.u1Present)
2452	return PGM_BTH_NAME(CheckPageFaultReturnNP)(pVCpu, uErr, GCPtrPage, 3);
2453	if (!GST_IS_PTE_VALID(pVCpu, PteSrc))
2454	return PGM_BTH_NAME(CheckPageFaultReturnRSVD)(pVCpu, uErr, GCPtrPage, 3);
2455	if ( (fMaybeWriteProtFault && !PteSrc.n.u1Write)
2456	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2457	\|\| (fMaybeNXEFault && PteSrc.n.u1NoExecute)
2458	# endif
2459	\|\| (fUserLevelFault && !PteSrc.n.u1User) )
2460	return PGM_BTH_NAME(CheckPageFaultReturnProt)(pVCpu, uErr, GCPtrPage, 0);
2461
2462	LogFlow(("CheckPageFault: page fault at %RGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
2463
2464	/*
2465	* Set the accessed bits in the page directory and the page table.
2466	*/
2467	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2468	pPml4eSrc->n.u1Accessed = 1;
2469	pPdpeSrc->lm.u1Accessed = 1;
2470	# endif
2471	pPdeSrc->n.u1Accessed = 1;
2472	pPteSrc->n.u1Accessed = 1;
2473
2474	/*
2475	* Set the dirty flag in the PTE if it's a write access.
2476	*/
2477	if (fWriteFault)
2478	{
2479	# ifdef VBOX_WITH_STATISTICS
2480	if (!pPteSrc->n.u1Dirty)
2481	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtiedPage));
2482	else
2483	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageAlreadyDirty));
2484	# endif
2485
2486	pPteSrc->n.u1Dirty = 1;
2487	}
2488	}
2489	return VINF_SUCCESS;
2490	}
2491
2492
2493	/**
2494	* Handle dirty bit tracking faults.
2495	*
2496	* @returns VBox status code.
2497	* @param pVCpu The VMCPU handle.
2498	* @param uErr Page fault error code.
2499	* @param pPdeSrc Guest page directory entry.
2500	* @param pPdeDst Shadow page directory entry.
2501	* @param GCPtrPage Guest context page address.
2502	*/
2503	PGM_BTH_DECL(int, CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2504	{
2505	PVM pVM = pVCpu->CTX_SUFF(pVM);
2506	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2507
2508	Assert(PGMIsLockOwner(pVM));
2509
2510	/*
2511	* Handle big page.
2512	*/
2513	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2514	{
2515	if ( pPdeDst->n.u1Present
2516	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2517	{
2518	SHWPDE PdeDst = *pPdeDst;
2519
2520	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2521	Assert(pPdeSrc->b.u1Write);
2522
2523	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2524	* fault again and take this path to only invalidate the entry (see below).
2525	*/
2526	PdeDst.n.u1Write = 1;
2527	PdeDst.n.u1Accessed = 1;
2528	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2529	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2530	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2531	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2532	}
2533
2534	# ifdef IN_RING0
2535	/* Check for stale TLB entry; only applies to the SMP guest case. */
2536	if ( pVM->cCpus > 1
2537	&& pPdeDst->n.u1Write
2538	&& pPdeDst->n.u1Accessed)
2539	{
2540	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2541	if (pShwPage)
2542	{
2543	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2544	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2545	if ( pPteDst->n.u1Present
2546	&& pPteDst->n.u1Write)
2547	{
2548	/* Stale TLB entry. */
2549	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2550	PGM_INVL_PG(pVCpu, GCPtrPage);
2551	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2552	}
2553	}
2554	}
2555	# endif /* IN_RING0 */
2556	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2557	}
2558
2559	/*
2560	* Map the guest page table.
2561	*/
2562	PGSTPT pPTSrc;
2563	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2564	if (RT_FAILURE(rc))
2565	{
2566	AssertRC(rc);
2567	return rc;
2568	}
2569
2570	if (pPdeDst->n.u1Present)
2571	{
2572	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2573	const GSTPTE PteSrc = *pPteSrc;
2574
2575	#ifndef IN_RING0
2576	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2577	* Our individual shadow handlers will provide more information and force a fatal exit.
2578	*/
2579	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2580	{
2581	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2582	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2583	}
2584	#endif
2585	/*
2586	* Map shadow page table.
2587	*/
2588	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2589	if (pShwPage)
2590	{
2591	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2592	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2593	if (pPteDst->n.u1Present) /** @todo Optimize accessed bit emulation? */
2594	{
2595	if (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY)
2596	{
2597	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2598	SHWPTE PteDst = *pPteDst;
2599
2600	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2601	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageTrap));
2602
2603	Assert(pPteSrc->n.u1Write);
2604
2605	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2606	* entry will not harm; write access will simply fault again and
2607	* take this path to only invalidate the entry.
2608	*/
2609	if (RT_LIKELY(pPage))
2610	{
2611	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2612	{
2613	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2614	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2615	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2616	PteDst.n.u1Write = 0;
2617	}
2618	else
2619	{
2620	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2621	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2622	{
2623	rc = pgmPhysPageMakeWritable(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2624	AssertRC(rc);
2625	}
2626	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2627	PteDst.n.u1Write = 1;
2628	else
2629	{
2630	/* Still applies to shared pages. */
2631	Assert(!PGM_PAGE_IS_ZERO(pPage));
2632	PteDst.n.u1Write = 0;
2633	}
2634	}
2635	}
2636	else
2637	PteDst.n.u1Write = 1; /** @todo r=bird: This doesn't make sense to me. */
2638
2639	PteDst.n.u1Dirty = 1;
2640	PteDst.n.u1Accessed = 1;
2641	PteDst.au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
2642	ASMAtomicWriteSize(pPteDst, PteDst.u);
2643	PGM_INVL_PG(pVCpu, GCPtrPage);
2644	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2645	}
2646
2647	# ifdef IN_RING0
2648	/* Check for stale TLB entry; only applies to the SMP guest case. */
2649	if ( pVM->cCpus > 1
2650	&& pPteDst->n.u1Write == 1
2651	&& pPteDst->n.u1Accessed == 1)
2652	{
2653	/* Stale TLB entry. */
2654	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageStale));
2655	PGM_INVL_PG(pVCpu, GCPtrPage);
2656	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2657	}
2658	# endif
2659	}
2660	}
2661	else
2662	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2663	}
2664
2665	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2666	}
2667
2668	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2669
2670
2671	/**
2672	* Sync a shadow page table.
2673	*
2674	* The shadow page table is not present. This includes the case where
2675	* there is a conflict with a mapping.
2676	*
2677	* @returns VBox status code.
2678	* @param pVCpu The VMCPU handle.
2679	* @param iPD Page directory index.
2680	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2681	* Assume this is a temporary mapping.
2682	* @param GCPtrPage GC Pointer of the page that caused the fault
2683	*/
2684	PGM_BTH_DECL(int, SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2685	{
2686	PVM pVM = pVCpu->CTX_SUFF(pVM);
2687	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2688
2689	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2690	#if 0 /* rarely useful; leave for debugging. */
2691	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2692	#endif
2693	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2694
2695	Assert(PGMIsLocked(pVM));
2696
2697	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2698	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2699	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2700	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2701	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2702
2703	int rc = VINF_SUCCESS;
2704
2705	/*
2706	* Validate input a little bit.
2707	*/
2708	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2709	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2710	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2711	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
2712
2713	/* Fetch the pgm pool shadow descriptor. */
2714	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2715	Assert(pShwPde);
2716
2717	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2718	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2719	PPGMPOOLPAGE pShwPde = NULL;
2720	PX86PDPAE pPDDst;
2721	PSHWPDE pPdeDst;
2722
2723	/* Fetch the pgm pool shadow descriptor. */
2724	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
2725	AssertRCSuccessReturn(rc, rc);
2726	Assert(pShwPde);
2727
2728	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
2729	pPdeDst = &pPDDst->a[iPDDst];
2730
2731	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2732	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2733	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2734	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2735	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2736	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2737	AssertRCSuccessReturn(rc, rc);
2738	Assert(pPDDst);
2739	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2740	# endif
2741	SHWPDE PdeDst = *pPdeDst;
2742
2743	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2744	/* Fetch the pgm pool shadow descriptor. */
2745	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2746	Assert(pShwPde);
2747	# endif
2748
2749	# ifndef PGM_WITHOUT_MAPPINGS
2750	/*
2751	* Check for conflicts.
2752	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2753	* R3: Simply resolve the conflict.
2754	*/
2755	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2756	{
2757	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2758	# ifndef IN_RING3
2759	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2760	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2761	return VERR_ADDRESS_CONFLICT;
2762
2763	# else /* IN_RING3 */
2764	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2765	Assert(pMapping);
2766	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2767	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2768	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2769	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2770	# else
2771	AssertFailed(); /* can't happen for amd64 */
2772	# endif
2773	if (RT_FAILURE(rc))
2774	{
2775	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
2776	return rc;
2777	}
2778	PdeDst = *pPdeDst;
2779	# endif /* IN_RING3 */
2780	}
2781	# endif /* !PGM_WITHOUT_MAPPINGS */
2782	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2783
2784	# if defined(IN_RC)
2785	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
2786	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
2787	# endif
2788
2789	/*
2790	* Sync page directory entry.
2791	*/
2792	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2793	if (PdeSrc.n.u1Present)
2794	{
2795	/*
2796	* Allocate & map the page table.
2797	*/
2798	PSHWPT pPTDst;
2799	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2800	PPGMPOOLPAGE pShwPage;
2801	RTGCPHYS GCPhys;
2802	if (fPageTable)
2803	{
2804	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2805	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2806	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2807	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2808	# endif
2809	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2810	}
2811	else
2812	{
2813	PGMPOOLACCESS enmAccess;
2814	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2815	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2816	# else
2817	const bool fNoExecute = false;
2818	# endif
2819
2820	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
2821	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2822	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2823	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2824	# endif
2825	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2826	if (PdeSrc.n.u1User)
2827	{
2828	if (PdeSrc.n.u1Write)
2829	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2830	else
2831	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2832	}
2833	else
2834	{
2835	if (PdeSrc.n.u1Write)
2836	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2837	else
2838	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2839	}
2840	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2841	}
2842	if (rc == VINF_SUCCESS)
2843	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2844	else if (rc == VINF_PGM_CACHED_PAGE)
2845	{
2846	/*
2847	* The PT was cached, just hook it up.
2848	*/
2849	if (fPageTable)
2850	PdeDst.u = pShwPage->Core.Key
2851	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2852	else
2853	{
2854	PdeDst.u = pShwPage->Core.Key
2855	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2856	/* (see explanation and assumptions further down.) */
2857	if ( !PdeSrc.b.u1Dirty
2858	&& PdeSrc.b.u1Write)
2859	{
2860	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
2861	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2862	PdeDst.b.u1Write = 0;
2863	}
2864	}
2865	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2866	# if defined(IN_RC)
2867	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2868	# endif
2869	return VINF_SUCCESS;
2870	}
2871	else if (rc == VERR_PGM_POOL_FLUSHED)
2872	{
2873	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2874	# if defined(IN_RC)
2875	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2876	# endif
2877	return VINF_PGM_SYNC_CR3;
2878	}
2879	else
2880	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2881	PdeDst.u &= X86_PDE_AVL_MASK;
2882	PdeDst.u \|= pShwPage->Core.Key;
2883
2884	/*
2885	* Page directory has been accessed (this is a fault situation, remember).
2886	*/
2887	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2888	if (fPageTable)
2889	{
2890	/*
2891	* Page table - 4KB.
2892	*
2893	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2894	*/
2895	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2896	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2897	PGSTPT pPTSrc;
2898	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2899	if (RT_SUCCESS(rc))
2900	{
2901	/*
2902	* Start by syncing the page directory entry so CSAM's TLB trick works.
2903	*/
2904	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2905	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2906	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2907	# if defined(IN_RC)
2908	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
2909	# endif
2910
2911	/*
2912	* Directory/page user or supervisor privilege: (same goes for read/write)
2913	*
2914	* Directory Page Combined
2915	* U/S U/S U/S
2916	* 0 0 0
2917	* 0 1 0
2918	* 1 0 0
2919	* 1 1 1
2920	*
2921	* Simple AND operation. Table listed for completeness.
2922	*
2923	*/
2924	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4K));
2925	# ifdef PGM_SYNC_N_PAGES
2926	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2927	unsigned iPTDst = iPTBase;
2928	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2929	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2930	iPTDst = 0;
2931	else
2932	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2933	# else /* !PGM_SYNC_N_PAGES */
2934	unsigned iPTDst = 0;
2935	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2936	# endif /* !PGM_SYNC_N_PAGES */
2937	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2938	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2939	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2940	# else
2941	const unsigned offPTSrc = 0;
2942	# endif
2943	for (; iPTDst < iPTDstEnd; iPTDst++)
2944	{
2945	const unsigned iPTSrc = iPTDst + offPTSrc;
2946	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2947
2948	if (PteSrc.n.u1Present)
2949	{
2950	# ifndef IN_RING0
2951	/*
2952	* Assuming kernel code will be marked as supervisor - and not as user level
2953	* and executed using a conforming code selector - And marked as readonly.
2954	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2955	*/
2956	PPGMPAGE pPage;
2957	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2958	\|\| !CSAMDoesPageNeedScanning(pVM, (iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT))
2959	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2960	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2961	)
2962	# endif
2963	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2964	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2965	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2966	PteSrc.n.u1Present,
2967	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2968	PteSrc.n.u1User & PdeSrc.n.u1User,
2969	(uint64_t)PteSrc.u,
2970	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2971	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2972	}
2973	/* else: the page table was cleared by the pool */
2974	} /* for PTEs */
2975	}
2976	}
2977	else
2978	{
2979	/*
2980	* Big page - 2/4MB.
2981	*
2982	* We'll walk the ram range list in parallel and optimize lookups.
2983	* We will only sync on shadow page table at a time.
2984	*/
2985	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT4M));
2986
2987	/**
2988	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2989	*/
2990
2991	/*
2992	* Start by syncing the page directory entry.
2993	*/
2994	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2995	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2996
2997	/*
2998	* If the page is not flagged as dirty and is writable, then make it read-only
2999	* at PD level, so we can set the dirty bit when the page is modified.
3000	*
3001	* ASSUMES that page access handlers are implemented on page table entry level.
3002	* Thus we will first catch the dirty access and set PDE.D and restart. If
3003	* there is an access handler, we'll trap again and let it work on the problem.
3004	*/
3005	/** @todo move the above stuff to a section in the PGM documentation. */
3006	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3007	if ( !PdeSrc.b.u1Dirty
3008	&& PdeSrc.b.u1Write)
3009	{
3010	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,DirtyPageBig));
3011	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3012	PdeDst.b.u1Write = 0;
3013	}
3014	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3015	# if defined(IN_RC)
3016	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3017	# endif
3018
3019	/*
3020	* Fill the shadow page table.
3021	*/
3022	/* Get address and flags from the source PDE. */
3023	SHWPTE PteDstBase;
3024	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
3025
3026	/* Loop thru the entries in the shadow PT. */
3027	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3028	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3029	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
3030	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3031	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
3032	unsigned iPTDst = 0;
3033	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3034	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3035	{
3036	/* Advance ram range list. */
3037	while (pRam && GCPhys > pRam->GCPhysLast)
3038	pRam = pRam->CTX_SUFF(pNext);
3039	if (pRam && GCPhys >= pRam->GCPhys)
3040	{
3041	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3042	do
3043	{
3044	/* Make shadow PTE. */
3045	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3046	SHWPTE PteDst;
3047
3048	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3049	/* Try to make the page writable if necessary. */
3050	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3051	&& ( PGM_PAGE_IS_ZERO(pPage)
3052	\|\| ( PteDstBase.n.u1Write
3053	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3054	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3055	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3056	# endif
3057	# ifdef VBOX_WITH_PAGE_SHARING
3058	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3059	# endif
3060	&& !PGM_PAGE_IS_BALLOONED(pPage))
3061	)
3062	)
3063	{
3064	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3065	AssertRCReturn(rc, rc);
3066	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3067	break;
3068	}
3069	# endif
3070
3071	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3072	{
3073	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
3074	{
3075	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
3076	PteDst.n.u1Write = 0;
3077	}
3078	else
3079	PteDst.u = 0;
3080	}
3081	else if (PGM_PAGE_IS_BALLOONED(pPage))
3082	{
3083	/* Skip ballooned pages. */
3084	PteDst.u = 0;
3085	}
3086	# ifndef IN_RING0
3087	/*
3088	* Assuming kernel code will be marked as supervisor and not as user level and executed
3089	* using a conforming code selector. Don't check for readonly, as that implies the whole
3090	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3091	*/
3092	else if ( !PdeSrc.n.u1User
3093	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3094	PteDst.u = 0;
3095	# endif
3096	else
3097	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
3098
3099	/* Only map writable pages writable. */
3100	if ( PteDst.n.u1Write
3101	&& PteDst.n.u1Present
3102	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3103	{
3104	/* Still applies to shared pages. */
3105	Assert(!PGM_PAGE_IS_ZERO(pPage));
3106	PteDst.n.u1Write = 0; /** @todo this isn't quite working yet... */
3107	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3108	}
3109
3110	if (PteDst.n.u1Present)
3111	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3112
3113	/* commit it */
3114	pPTDst->a[iPTDst] = PteDst;
3115	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3116	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
3117	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3118
3119	/* advance */
3120	GCPhys += PAGE_SIZE;
3121	iHCPage++;
3122	iPTDst++;
3123	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3124	&& GCPhys <= pRam->GCPhysLast);
3125	}
3126	else if (pRam)
3127	{
3128	Log(("Invalid pages at %RGp\n", GCPhys));
3129	do
3130	{
3131	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
3132	GCPhys += PAGE_SIZE;
3133	iPTDst++;
3134	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3135	&& GCPhys < pRam->GCPhys);
3136	}
3137	else
3138	{
3139	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3140	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3141	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
3142	}
3143	} /* while more PTEs */
3144	} /* 4KB / 4MB */
3145	}
3146	else
3147	AssertRelease(!PdeDst.n.u1Present);
3148
3149	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3150	if (RT_FAILURE(rc))
3151	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPTFailed));
3152	return rc;
3153
3154	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3155	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3156	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3157	&& !defined(IN_RC)
3158
3159	/*
3160	* Validate input a little bit.
3161	*/
3162	int rc = VINF_SUCCESS;
3163	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3164	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3165	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3166
3167	/* Fetch the pgm pool shadow descriptor. */
3168	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3169	Assert(pShwPde);
3170
3171	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3172	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3173	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3174	PX86PDPAE pPDDst;
3175	PSHWPDE pPdeDst;
3176
3177	/* Fetch the pgm pool shadow descriptor. */
3178	rc = pgmShwGetPaePoolPagePD(&pVCpu->pgm.s, GCPtrPage, &pShwPde);
3179	AssertRCSuccessReturn(rc, rc);
3180	Assert(pShwPde);
3181
3182	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_BY_PGM(&pVM->pgm.s, pShwPde);
3183	pPdeDst = &pPDDst->a[iPDDst];
3184
3185	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3186	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3187	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3188	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3189	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3190	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3191	AssertRCSuccessReturn(rc, rc);
3192	Assert(pPDDst);
3193	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3194
3195	/* Fetch the pgm pool shadow descriptor. */
3196	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3197	Assert(pShwPde);
3198
3199	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3200	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3201	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3202	PEPTPD pPDDst;
3203	PEPTPDPT pPdptDst;
3204
3205	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3206	if (rc != VINF_SUCCESS)
3207	{
3208	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3209	AssertRC(rc);
3210	return rc;
3211	}
3212	Assert(pPDDst);
3213	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3214
3215	/* Fetch the pgm pool shadow descriptor. */
3216	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3217	Assert(pShwPde);
3218	# endif
3219	SHWPDE PdeDst = *pPdeDst;
3220
3221	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3222	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3223
3224	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3225	if (BTH_IS_NP_ACTIVE(pVM))
3226	{
3227	PPGMPAGE pPage;
3228
3229	/* Check if we allocated a big page before for this 2 MB range. */
3230	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3231	if (RT_SUCCESS(rc))
3232	{
3233	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3234
3235	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3236	{
3237	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3238	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3239	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3240	}
3241	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3242	{
3243	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3244	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3245	if (RT_SUCCESS(rc))
3246	{
3247	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3248	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3249	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3250	}
3251	}
3252	else if (PGMIsUsingLargePages(pVM))
3253	{
3254	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3255	if (RT_SUCCESS(rc))
3256	{
3257	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3258	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3259	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3260	}
3261	else
3262	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3263	}
3264
3265	if (HCPhys != NIL_RTHCPHYS)
3266	{
3267	PdeDst.u &= X86_PDE_AVL_MASK;
3268	PdeDst.u \|= HCPhys;
3269	PdeDst.n.u1Present = 1;
3270	PdeDst.n.u1Write = 1;
3271	PdeDst.b.u1Size = 1;
3272	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3273	PdeDst.n.u1Execute = 1;
3274	PdeDst.b.u1IgnorePAT = 1;
3275	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3276	# else
3277	PdeDst.n.u1User = 1;
3278	# endif
3279	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3280
3281	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3282	/* Add a reference to the first page only. */
3283	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3284
3285	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3286	return VINF_SUCCESS;
3287	}
3288	}
3289	}
3290	# endif /* HC_ARCH_BITS == 64 */
3291
3292	GSTPDE PdeSrc;
3293	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3294	PdeSrc.n.u1Present = 1;
3295	PdeSrc.n.u1Write = 1;
3296	PdeSrc.n.u1Accessed = 1;
3297	PdeSrc.n.u1User = 1;
3298
3299	/*
3300	* Allocate & map the page table.
3301	*/
3302	PSHWPT pPTDst;
3303	PPGMPOOLPAGE pShwPage;
3304	RTGCPHYS GCPhys;
3305
3306	/* Virtual address = physical address */
3307	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3308	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3309
3310	if ( rc == VINF_SUCCESS
3311	\|\| rc == VINF_PGM_CACHED_PAGE)
3312	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
3313	else
3314	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3315
3316	PdeDst.u &= X86_PDE_AVL_MASK;
3317	PdeDst.u \|= pShwPage->Core.Key;
3318	PdeDst.n.u1Present = 1;
3319	PdeDst.n.u1Write = 1;
3320	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3321	PdeDst.n.u1Execute = 1;
3322	# else
3323	PdeDst.n.u1User = 1;
3324	PdeDst.n.u1Accessed = 1;
3325	# endif
3326	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3327
3328	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3329	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3330	return rc;
3331
3332	#else
3333	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3334	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPT), a);
3335	return VERR_INTERNAL_ERROR;
3336	#endif
3337	}
3338
3339
3340
3341	/**
3342	* Prefetch a page/set of pages.
3343	*
3344	* Typically used to sync commonly used pages before entering raw mode
3345	* after a CR3 reload.
3346	*
3347	* @returns VBox status code.
3348	* @param pVCpu The VMCPU handle.
3349	* @param GCPtrPage Page to invalidate.
3350	*/
3351	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3352	{
3353	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3354	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3355	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3356	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3357	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3358	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3359	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3360
3361	/*
3362	* Check that all Guest levels thru the PDE are present, getting the
3363	* PD and PDE in the processes.
3364	*/
3365	int rc = VINF_SUCCESS;
3366	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3367	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3368	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3369	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3370	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3371	unsigned iPDSrc;
3372	X86PDPE PdpeSrc;
3373	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3374	if (!pPDSrc)
3375	return VINF_SUCCESS; /* not present */
3376	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3377	unsigned iPDSrc;
3378	PX86PML4E pPml4eSrc;
3379	X86PDPE PdpeSrc;
3380	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3381	if (!pPDSrc)
3382	return VINF_SUCCESS; /* not present */
3383	# endif
3384	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3385	# else
3386	PGSTPD pPDSrc = NULL;
3387	const unsigned iPDSrc = 0;
3388	GSTPDE PdeSrc;
3389
3390	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3391	PdeSrc.n.u1Present = 1;
3392	PdeSrc.n.u1Write = 1;
3393	PdeSrc.n.u1Accessed = 1;
3394	PdeSrc.n.u1User = 1;
3395	# endif
3396
3397	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3398	{
3399	PVM pVM = pVCpu->CTX_SUFF(pVM);
3400	pgmLock(pVM);
3401
3402	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3403	const X86PDE PdeDst = pgmShwGet32BitPDE(&pVCpu->pgm.s, GCPtrPage);
3404	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3405	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3406	PX86PDPAE pPDDst;
3407	X86PDEPAE PdeDst;
3408	# if PGM_GST_TYPE != PGM_TYPE_PAE
3409	X86PDPE PdpeSrc;
3410
3411	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3412	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3413	# endif
3414	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3415	if (rc != VINF_SUCCESS)
3416	{
3417	pgmUnlock(pVM);
3418	AssertRC(rc);
3419	return rc;
3420	}
3421	Assert(pPDDst);
3422	PdeDst = pPDDst->a[iPDDst];
3423
3424	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3425	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3426	PX86PDPAE pPDDst;
3427	X86PDEPAE PdeDst;
3428
3429	# if PGM_GST_TYPE == PGM_TYPE_PROT
3430	/* AMD-V nested paging */
3431	X86PML4E Pml4eSrc;
3432	X86PDPE PdpeSrc;
3433	PX86PML4E pPml4eSrc = &Pml4eSrc;
3434
3435	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3436	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3437	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3438	# endif
3439
3440	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3441	if (rc != VINF_SUCCESS)
3442	{
3443	pgmUnlock(pVM);
3444	AssertRC(rc);
3445	return rc;
3446	}
3447	Assert(pPDDst);
3448	PdeDst = pPDDst->a[iPDDst];
3449	# endif
3450	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3451	{
3452	if (!PdeDst.n.u1Present)
3453	{
3454	/** @todo r=bird: This guy will set the A bit on the PDE,
3455	* probably harmless. */
3456	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3457	}
3458	else
3459	{
3460	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3461	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3462	* makes no sense to prefetch more than one page.
3463	*/
3464	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3465	if (RT_SUCCESS(rc))
3466	rc = VINF_SUCCESS;
3467	}
3468	}
3469	pgmUnlock(pVM);
3470	}
3471	return rc;
3472
3473	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3474	return VINF_SUCCESS; /* ignore */
3475	#else
3476	AssertCompile(0);
3477	#endif
3478	}
3479
3480
3481
3482
3483	/**
3484	* Syncs a page during a PGMVerifyAccess() call.
3485	*
3486	* @returns VBox status code (informational included).
3487	* @param pVCpu The VMCPU handle.
3488	* @param GCPtrPage The address of the page to sync.
3489	* @param fPage The effective guest page flags.
3490	* @param uErr The trap error code.
3491	* @remarks This will normally never be called on invalid guest page
3492	* translation entries.
3493	*/
3494	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3495	{
3496	PVM pVM = pVCpu->CTX_SUFF(pVM);
3497
3498	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3499
3500	Assert(!pVM->pgm.s.fNestedPaging);
3501	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3502	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3503	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3504	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3505	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3506	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3507	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3508
3509	# ifndef IN_RING0
3510	if (!(fPage & X86_PTE_US))
3511	{
3512	/*
3513	* Mark this page as safe.
3514	*/
3515	/** @todo not correct for pages that contain both code and data!! */
3516	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3517	CSAMMarkPage(pVM, GCPtrPage, true);
3518	}
3519	# endif
3520
3521	/*
3522	* Get guest PD and index.
3523	*/
3524	/** @todo Performance: We've done all this a jiffy ago in the
3525	* PGMGstGetPage call. */
3526	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3527	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3528	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3529	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3530
3531	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3532	unsigned iPDSrc = 0;
3533	X86PDPE PdpeSrc;
3534	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3535	if (RT_UNLIKELY(!pPDSrc))
3536	{
3537	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3538	return VINF_EM_RAW_GUEST_TRAP;
3539	}
3540
3541	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3542	unsigned iPDSrc = 0; /* shut up gcc */
3543	PX86PML4E pPml4eSrc = NULL; /* ditto */
3544	X86PDPE PdpeSrc;
3545	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3546	if (RT_UNLIKELY(!pPDSrc))
3547	{
3548	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3549	return VINF_EM_RAW_GUEST_TRAP;
3550	}
3551	# endif
3552
3553	# else /* !PGM_WITH_PAGING */
3554	PGSTPD pPDSrc = NULL;
3555	const unsigned iPDSrc = 0;
3556	# endif /* !PGM_WITH_PAGING */
3557	int rc = VINF_SUCCESS;
3558
3559	pgmLock(pVM);
3560
3561	/*
3562	* First check if the shadow pd is present.
3563	*/
3564	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3565	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(&pVCpu->pgm.s, GCPtrPage);
3566
3567	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3568	PX86PDEPAE pPdeDst;
3569	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3570	PX86PDPAE pPDDst;
3571	# if PGM_GST_TYPE != PGM_TYPE_PAE
3572	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3573	X86PDPE PdpeSrc;
3574	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3575	# endif
3576	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3577	if (rc != VINF_SUCCESS)
3578	{
3579	pgmUnlock(pVM);
3580	AssertRC(rc);
3581	return rc;
3582	}
3583	Assert(pPDDst);
3584	pPdeDst = &pPDDst->a[iPDDst];
3585
3586	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3587	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3588	PX86PDPAE pPDDst;
3589	PX86PDEPAE pPdeDst;
3590
3591	# if PGM_GST_TYPE == PGM_TYPE_PROT
3592	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3593	X86PML4E Pml4eSrc;
3594	X86PDPE PdpeSrc;
3595	PX86PML4E pPml4eSrc = &Pml4eSrc;
3596	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3597	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3598	# endif
3599
3600	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3601	if (rc != VINF_SUCCESS)
3602	{
3603	pgmUnlock(pVM);
3604	AssertRC(rc);
3605	return rc;
3606	}
3607	Assert(pPDDst);
3608	pPdeDst = &pPDDst->a[iPDDst];
3609	# endif
3610
3611	# if defined(IN_RC)
3612	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3613	PGMDynLockHCPage(pVM, (uint8_t *)pPdeDst);
3614	# endif
3615
3616	if (!pPdeDst->n.u1Present)
3617	{
3618	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3619	if (rc != VINF_SUCCESS)
3620	{
3621	# if defined(IN_RC)
3622	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3623	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3624	# endif
3625	pgmUnlock(pVM);
3626	AssertRC(rc);
3627	return rc;
3628	}
3629	}
3630
3631	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3632	/* Check for dirty bit fault */
3633	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3634	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3635	Log(("PGMVerifyAccess: success (dirty)\n"));
3636	else
3637	# endif
3638	{
3639	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3640	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3641	# else
3642	GSTPDE PdeSrc;
3643	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3644	PdeSrc.n.u1Present = 1;
3645	PdeSrc.n.u1Write = 1;
3646	PdeSrc.n.u1Accessed = 1;
3647	PdeSrc.n.u1User = 1;
3648	# endif
3649
3650	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3651	if (uErr & X86_TRAP_PF_US)
3652	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncUser));
3653	else /* supervisor */
3654	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3655
3656	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3657	if (RT_SUCCESS(rc))
3658	{
3659	/* Page was successfully synced */
3660	Log2(("PGMVerifyAccess: success (sync)\n"));
3661	rc = VINF_SUCCESS;
3662	}
3663	else
3664	{
3665	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3666	rc = VINF_EM_RAW_GUEST_TRAP;
3667	}
3668	}
3669	# if defined(IN_RC)
3670	/* Make sure the dynamic pPdeDst mapping will not be reused during this function. */
3671	PGMDynUnlockHCPage(pVM, (uint8_t *)pPdeDst);
3672	# endif
3673	pgmUnlock(pVM);
3674	return rc;
3675
3676	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3677
3678	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3679	return VERR_INTERNAL_ERROR;
3680	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3681	}
3682
3683
3684	/**
3685	* Syncs the paging hierarchy starting at CR3.
3686	*
3687	* @returns VBox status code, no specials.
3688	* @param pVCpu The VMCPU handle.
3689	* @param cr0 Guest context CR0 register
3690	* @param cr3 Guest context CR3 register
3691	* @param cr4 Guest context CR4 register
3692	* @param fGlobal Including global page directories or not
3693	*/
3694	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3695	{
3696	PVM pVM = pVCpu->CTX_SUFF(pVM);
3697
3698	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3699
3700	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3701
3702	pgmLock(pVM);
3703
3704	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3705	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3706	if (pPool->cDirtyPages)
3707	pgmPoolResetDirtyPages(pVM);
3708	# endif
3709
3710	/*
3711	* Update page access handlers.
3712	* The virtual are always flushed, while the physical are only on demand.
3713	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3714	* have to look into that later because it will have a bad influence on the performance.
3715	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3716	* bird: Yes, but that won't work for aliases.
3717	*/
3718	/** @todo this MUST go away. See #1557. */
3719	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3720	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3721	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncCR3Handlers), h);
3722	pgmUnlock(pVM);
3723	#endif /* !NESTED && !EPT */
3724
3725	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3726	/*
3727	* Nested / EPT - almost no work.
3728	*/
3729	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3730	return VINF_SUCCESS;
3731
3732	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3733	/*
3734	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3735	* out the shadow parts when the guest modifies its tables.
3736	*/
3737	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3738	return VINF_SUCCESS;
3739
3740	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3741
3742	# ifndef PGM_WITHOUT_MAPPINGS
3743	/*
3744	* Check for and resolve conflicts with our guest mappings if they
3745	* are enabled and not fixed.
3746	*/
3747	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3748	{
3749	int rc = pgmMapResolveConflicts(pVM);
3750	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3751	if (rc == VINF_PGM_SYNC_CR3)
3752	{
3753	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3754	return VINF_PGM_SYNC_CR3;
3755	}
3756	}
3757	# else
3758	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3759	# endif
3760	return VINF_SUCCESS;
3761	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3762	}
3763
3764
3765
3766
3767	#ifdef VBOX_STRICT
3768	#ifdef IN_RC
3769	# undef AssertMsgFailed
3770	# define AssertMsgFailed Log
3771	#endif
3772	#ifdef IN_RING3
3773	# include <VBox/dbgf.h>
3774
3775	/**
3776	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3777	*
3778	* @returns VBox status code (VINF_SUCCESS).
3779	* @param cr3 The root of the hierarchy.
3780	* @param crr The cr4, only PAE and PSE is currently used.
3781	* @param fLongMode Set if long mode, false if not long mode.
3782	* @param cMaxDepth Number of levels to dump.
3783	* @param pHlp Pointer to the output functions.
3784	*/
3785	RT_C_DECLS_BEGIN
3786	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3787	RT_C_DECLS_END
3788
3789	#endif
3790
3791	/**
3792	* Checks that the shadow page table is in sync with the guest one.
3793	*
3794	* @returns The number of errors.
3795	* @param pVM The virtual machine.
3796	* @param pVCpu The VMCPU handle.
3797	* @param cr3 Guest context CR3 register
3798	* @param cr4 Guest context CR4 register
3799	* @param GCPtr Where to start. Defaults to 0.
3800	* @param cb How much to check. Defaults to everything.
3801	*/
3802	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3803	{
3804	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3805	return 0;
3806	#else
3807	unsigned cErrors = 0;
3808	PVM pVM = pVCpu->CTX_SUFF(pVM);
3809	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3810
3811	#if PGM_GST_TYPE == PGM_TYPE_PAE
3812	/** @todo currently broken; crashes below somewhere */
3813	AssertFailed();
3814	#endif
3815
3816	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3817	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3818	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3819
3820	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3821	PPGMCPU pPGM = &pVCpu->pgm.s;
3822	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3823	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3824	# ifndef IN_RING0
3825	RTHCPHYS HCPhys; /* general usage. */
3826	# endif
3827	int rc;
3828
3829	/*
3830	* Check that the Guest CR3 and all its mappings are correct.
3831	*/
3832	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3833	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3834	false);
3835	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3836	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3837	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3838	# else
3839	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3840	# endif
3841	AssertRCReturn(rc, 1);
3842	HCPhys = NIL_RTHCPHYS;
3843	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3844	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3845	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3846	pgmGstGet32bitPDPtr(pVCpu);
3847	RTGCPHYS GCPhys;
3848	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3849	AssertRCReturn(rc, 1);
3850	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3851	# endif
3852	# endif /* !IN_RING0 */
3853
3854	/*
3855	* Get and check the Shadow CR3.
3856	*/
3857	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3858	unsigned cPDEs = X86_PG_ENTRIES;
3859	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3860	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3861	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3862	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3863	# else
3864	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3865	# endif
3866	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3867	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3868	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3869	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3870	# endif
3871	if (cb != ~(RTGCPTR)0)
3872	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3873
3874	/** @todo call the other two PGMAssert() functions. /
3875
3876	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3877	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3878
3879	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3880	{
3881	PPGMPOOLPAGE pShwPdpt = NULL;
3882	PX86PML4E pPml4eSrc;
3883	PX86PML4E pPml4eDst;
3884	RTGCPHYS GCPhysPdptSrc;
3885
3886	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3887	pPml4eDst = pgmShwGetLongModePML4EPtr(&pVCpu->pgm.s, iPml4);
3888
3889	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3890	if (!pPml4eDst->n.u1Present)
3891	{
3892	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3893	continue;
3894	}
3895
3896	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3897	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3898
3899	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3900	{
3901	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3902	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3903	cErrors++;
3904	continue;
3905	}
3906
3907	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3908	{
3909	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3910	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3911	cErrors++;
3912	continue;
3913	}
3914
3915	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3916	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3917	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3918	{
3919	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3920	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3921	cErrors++;
3922	continue;
3923	}
3924	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3925	{
3926	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3927
3928	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3929	/*
3930	* Check the PDPTEs too.
3931	*/
3932	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3933
3934	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3935	{
3936	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3937	PPGMPOOLPAGE pShwPde = NULL;
3938	PX86PDPE pPdpeDst;
3939	RTGCPHYS GCPhysPdeSrc;
3940	# if PGM_GST_TYPE == PGM_TYPE_PAE
3941	X86PDPE PdpeSrc;
3942	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3943	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(&pVCpu->pgm.s);
3944	# else
3945	PX86PML4E pPml4eSrcIgn;
3946	X86PDPE PdpeSrc;
3947	PX86PDPT pPdptDst;
3948	PX86PDPAE pPDDst;
3949	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3950
3951	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3952	if (rc != VINF_SUCCESS)
3953	{
3954	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3955	GCPtr += 512 * _2M;
3956	continue; /* next PDPTE */
3957	}
3958	Assert(pPDDst);
3959	# endif
3960	Assert(iPDSrc == 0);
3961
3962	pPdpeDst = &pPdptDst->a[iPdpt];
3963
3964	if (!pPdpeDst->n.u1Present)
3965	{
3966	GCPtr += 512 * _2M;
3967	continue; /* next PDPTE */
3968	}
3969
3970	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3971	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3972
3973	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3974	{
3975	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3976	GCPtr += 512 * _2M;
3977	cErrors++;
3978	continue;
3979	}
3980
3981	if (GCPhysPdeSrc != pShwPde->GCPhys)
3982	{
3983	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3984	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3985	# else
3986	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3987	# endif
3988	GCPtr += 512 * _2M;
3989	cErrors++;
3990	continue;
3991	}
3992
3993	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3994	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3995	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3996	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3997	{
3998	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3999	GCPtr += 512 * _2M;
4000	cErrors++;
4001	continue;
4002	}
4003	# endif
4004
4005	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4006	{
4007	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4008	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4009	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4010	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4011	PCX86PD pPDDst = pgmShwGet32BitPDPtr(&pVCpu->pgm.s);
4012	# endif
4013	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4014	/*
4015	* Iterate the shadow page directory.
4016	*/
4017	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4018	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4019
4020	for (;
4021	iPDDst < cPDEs;
4022	iPDDst++, GCPtr += cIncrement)
4023	{
4024	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4025	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pPGM, GCPtr);
4026	# else
4027	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4028	# endif
4029	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4030	{
4031	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
4032	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4033	{
4034	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4035	cErrors++;
4036	continue;
4037	}
4038	}
4039	else if ( (PdeDst.u & X86_PDE_P)
4040	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4041	)
4042	{
4043	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4044	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4045	if (!pPoolPage)
4046	{
4047	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4048	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4049	cErrors++;
4050	continue;
4051	}
4052	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
4053
4054	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4055	{
4056	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4057	GCPtr, (uint64_t)PdeDst.u));
4058	cErrors++;
4059	}
4060
4061	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4062	{
4063	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4064	GCPtr, (uint64_t)PdeDst.u));
4065	cErrors++;
4066	}
4067
4068	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4069	if (!PdeSrc.n.u1Present)
4070	{
4071	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4072	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4073	cErrors++;
4074	continue;
4075	}
4076
4077	if ( !PdeSrc.b.u1Size
4078	\|\| !fBigPagesSupported)
4079	{
4080	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
4081	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4082	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
4083	# endif
4084	}
4085	else
4086	{
4087	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4088	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4089	{
4090	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4091	GCPtr, (uint64_t)PdeSrc.u));
4092	cErrors++;
4093	continue;
4094	}
4095	# endif
4096	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
4097	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4098	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
4099	# endif
4100	}
4101
4102	if ( pPoolPage->enmKind
4103	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4104	{
4105	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4106	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4107	cErrors++;
4108	}
4109
4110	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4111	if (!pPhysPage)
4112	{
4113	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4114	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4115	cErrors++;
4116	continue;
4117	}
4118
4119	if (GCPhysGst != pPoolPage->GCPhys)
4120	{
4121	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4122	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4123	cErrors++;
4124	continue;
4125	}
4126
4127	if ( !PdeSrc.b.u1Size
4128	\|\| !fBigPagesSupported)
4129	{
4130	/*
4131	* Page Table.
4132	*/
4133	const GSTPT *pPTSrc;
4134	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
4135	if (RT_FAILURE(rc))
4136	{
4137	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4138	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4139	cErrors++;
4140	continue;
4141	}
4142	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4143	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4144	{
4145	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4146	// (This problem will go away when/if we shadow multiple CR3s.)
4147	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4148	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4149	cErrors++;
4150	continue;
4151	}
4152	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4153	{
4154	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4155	GCPtr, (uint64_t)PdeDst.u));
4156	cErrors++;
4157	continue;
4158	}
4159
4160	/* iterate the page table. */
4161	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4162	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4163	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4164	# else
4165	const unsigned offPTSrc = 0;
4166	# endif
4167	for (unsigned iPT = 0, off = 0;
4168	iPT < RT_ELEMENTS(pPTDst->a);
4169	iPT++, off += PAGE_SIZE)
4170	{
4171	const SHWPTE PteDst = pPTDst->a[iPT];
4172
4173	/* skip not-present entries. */
4174	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4175	continue;
4176	Assert(PteDst.n.u1Present);
4177
4178	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4179	if (!PteSrc.n.u1Present)
4180	{
4181	# ifdef IN_RING3
4182	PGMAssertHandlerAndFlagsInSync(pVM);
4183	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
4184	# endif
4185	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4186	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4187	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
4188	cErrors++;
4189	continue;
4190	}
4191
4192	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4193	# if 1 /** @todo sync accessed bit properly... */
4194	fIgnoreFlags \|= X86_PTE_A;
4195	# endif
4196
4197	/* match the physical addresses */
4198	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
4199	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
4200
4201	# ifdef IN_RING3
4202	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4203	if (RT_FAILURE(rc))
4204	{
4205	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4206	{
4207	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4208	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4209	cErrors++;
4210	continue;
4211	}
4212	}
4213	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4214	{
4215	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4217	cErrors++;
4218	continue;
4219	}
4220	# endif
4221
4222	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4223	if (!pPhysPage)
4224	{
4225	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4226	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4227	{
4228	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4229	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4230	cErrors++;
4231	continue;
4232	}
4233	# endif
4234	if (PteDst.n.u1Write)
4235	{
4236	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4237	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4238	cErrors++;
4239	}
4240	fIgnoreFlags \|= X86_PTE_RW;
4241	}
4242	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4243	{
4244	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4245	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4246	cErrors++;
4247	continue;
4248	}
4249
4250	/* flags */
4251	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4252	{
4253	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4254	{
4255	if (PteDst.n.u1Write)
4256	{
4257	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4258	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4259	cErrors++;
4260	continue;
4261	}
4262	fIgnoreFlags \|= X86_PTE_RW;
4263	}
4264	else
4265	{
4266	if ( PteDst.n.u1Present
4267	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4268	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4269	# endif
4270	)
4271	{
4272	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4273	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4274	cErrors++;
4275	continue;
4276	}
4277	fIgnoreFlags \|= X86_PTE_P;
4278	}
4279	}
4280	else
4281	{
4282	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4283	{
4284	if (PteDst.n.u1Write)
4285	{
4286	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4287	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4288	cErrors++;
4289	continue;
4290	}
4291	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
4292	{
4293	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4294	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4295	cErrors++;
4296	continue;
4297	}
4298	if (PteDst.n.u1Dirty)
4299	{
4300	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4301	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4302	cErrors++;
4303	}
4304	# if 0 /** @todo sync access bit properly... */
4305	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4306	{
4307	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4308	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4309	cErrors++;
4310	}
4311	fIgnoreFlags \|= X86_PTE_RW;
4312	# else
4313	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4314	# endif
4315	}
4316	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4317	{
4318	/* access bit emulation (not implemented). */
4319	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
4320	{
4321	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4322	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4323	cErrors++;
4324	continue;
4325	}
4326	if (!PteDst.n.u1Accessed)
4327	{
4328	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4329	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4330	cErrors++;
4331	}
4332	fIgnoreFlags \|= X86_PTE_P;
4333	}
4334	# ifdef DEBUG_sandervl
4335	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4336	# endif
4337	}
4338
4339	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4340	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
4341	)
4342	{
4343	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4344	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4345	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
4346	cErrors++;
4347	continue;
4348	}
4349	} /* foreach PTE */
4350	}
4351	else
4352	{
4353	/*
4354	* Big Page.
4355	*/
4356	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4357	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4358	{
4359	if (PdeDst.n.u1Write)
4360	{
4361	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4362	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4363	cErrors++;
4364	continue;
4365	}
4366	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4367	{
4368	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4369	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4370	cErrors++;
4371	continue;
4372	}
4373	# if 0 /** @todo sync access bit properly... */
4374	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4375	{
4376	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4377	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4378	cErrors++;
4379	}
4380	fIgnoreFlags \|= X86_PTE_RW;
4381	# else
4382	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4383	# endif
4384	}
4385	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4386	{
4387	/* access bit emulation (not implemented). */
4388	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4389	{
4390	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4391	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4392	cErrors++;
4393	continue;
4394	}
4395	if (!PdeDst.n.u1Accessed)
4396	{
4397	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4398	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4399	cErrors++;
4400	}
4401	fIgnoreFlags \|= X86_PTE_P;
4402	}
4403
4404	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4405	{
4406	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4407	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4408	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4409	cErrors++;
4410	}
4411
4412	/* iterate the page table. */
4413	for (unsigned iPT = 0, off = 0;
4414	iPT < RT_ELEMENTS(pPTDst->a);
4415	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4416	{
4417	const SHWPTE PteDst = pPTDst->a[iPT];
4418
4419	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
4420	{
4421	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4422	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4423	cErrors++;
4424	}
4425
4426	/* skip not-present entries. */
4427	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
4428	continue;
4429
4430	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4431
4432	/* match the physical addresses */
4433	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
4434
4435	# ifdef IN_RING3
4436	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4437	if (RT_FAILURE(rc))
4438	{
4439	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4440	{
4441	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4442	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4443	cErrors++;
4444	}
4445	}
4446	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4447	{
4448	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4449	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4450	cErrors++;
4451	continue;
4452	}
4453	# endif
4454	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4455	if (!pPhysPage)
4456	{
4457	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4458	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4459	{
4460	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4461	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4462	cErrors++;
4463	continue;
4464	}
4465	# endif
4466	if (PteDst.n.u1Write)
4467	{
4468	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4469	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4470	cErrors++;
4471	}
4472	fIgnoreFlags \|= X86_PTE_RW;
4473	}
4474	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4475	{
4476	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4477	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4478	cErrors++;
4479	continue;
4480	}
4481
4482	/* flags */
4483	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4484	{
4485	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4486	{
4487	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4488	{
4489	if (PteDst.n.u1Write)
4490	{
4491	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4492	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4493	cErrors++;
4494	continue;
4495	}
4496	fIgnoreFlags \|= X86_PTE_RW;
4497	}
4498	}
4499	else
4500	{
4501	if ( PteDst.n.u1Present
4502	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4503	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4504	# endif
4505	)
4506	{
4507	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4508	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4509	cErrors++;
4510	continue;
4511	}
4512	fIgnoreFlags \|= X86_PTE_P;
4513	}
4514	}
4515
4516	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
4517	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
4518	)
4519	{
4520	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4521	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
4522	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
4523	cErrors++;
4524	continue;
4525	}
4526	} /* for each PTE */
4527	}
4528	}
4529	/* not present */
4530
4531	} /* for each PDE */
4532
4533	} /* for each PDPTE */
4534
4535	} /* for each PML4E */
4536
4537	# ifdef DEBUG
4538	if (cErrors)
4539	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4540	# endif
4541
4542	#endif /* GST == 32BIT, PAE or AMD64 */
4543	return cErrors;
4544
4545	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4546	}
4547	#endif /* VBOX_STRICT */
4548
4549
4550	/**
4551	* Sets up the CR3 for shadow paging
4552	*
4553	* @returns Strict VBox status code.
4554	* @retval VINF_SUCCESS.
4555	*
4556	* @param pVCpu The VMCPU handle.
4557	* @param GCPhysCR3 The physical address in the CR3 register.
4558	*/
4559	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4560	{
4561	PVM pVM = pVCpu->CTX_SUFF(pVM);
4562
4563	/* Update guest paging info. */
4564	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4565	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4566	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4567
4568	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4569
4570	/*
4571	* Map the page CR3 points at.
4572	*/
4573	RTHCPTR HCPtrGuestCR3;
4574	RTHCPHYS HCPhysGuestCR3;
4575	pgmLock(pVM);
4576	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4577	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4578	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4579	/** @todo this needs some reworking wrt. locking. */
4580	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4581	HCPtrGuestCR3 = NIL_RTHCPTR;
4582	int rc = VINF_SUCCESS;
4583	# else
4584	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4585	# endif
4586	pgmUnlock(pVM);
4587	if (RT_SUCCESS(rc))
4588	{
4589	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4590	if (RT_SUCCESS(rc))
4591	{
4592	# ifdef IN_RC
4593	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4594	# endif
4595	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4596	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4597	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4598	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4599	# endif
4600	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4601
4602	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4603	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4604	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4605	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4606	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4607	# endif
4608	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4609	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4610
4611	/*
4612	* Map the 4 PDs too.
4613	*/
4614	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4615	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4616	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4617	{
4618	if (pGuestPDPT->a[i].n.u1Present)
4619	{
4620	RTHCPTR HCPtr;
4621	RTHCPHYS HCPhys;
4622	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4623	pgmLock(pVM);
4624	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4625	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4626	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4627	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4628	HCPtr = NIL_RTHCPTR;
4629	int rc2 = VINF_SUCCESS;
4630	# else
4631	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4632	# endif
4633	pgmUnlock(pVM);
4634	if (RT_SUCCESS(rc2))
4635	{
4636	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4637	AssertRCReturn(rc, rc);
4638
4639	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4640	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4641	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4642	# endif
4643	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4644	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4645	# ifdef IN_RC
4646	PGM_INVL_PG(pVCpu, GCPtr);
4647	# endif
4648	continue;
4649	}
4650	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4651	}
4652
4653	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4654	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4655	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4656	# endif
4657	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4658	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4659	# ifdef IN_RC
4660	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4661	# endif
4662	}
4663
4664	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4665	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4666	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4667	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4668	# endif
4669	# endif
4670	}
4671	else
4672	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4673	}
4674	else
4675	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4676
4677	#else /* prot/real stub */
4678	int rc = VINF_SUCCESS;
4679	#endif
4680
4681	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4682	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4683	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4684	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4685	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4686	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4687
4688	Assert(!pVM->pgm.s.fNestedPaging);
4689
4690	/*
4691	* Update the shadow root page as well since that's not fixed.
4692	*/
4693	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4694	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4695	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4696	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4697	PPGMPOOLPAGE pNewShwPageCR3;
4698
4699	pgmLock(pVM);
4700
4701	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4702	if (pPool->cDirtyPages)
4703	pgmPoolResetDirtyPages(pVM);
4704	# endif
4705
4706	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4707	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4708	AssertFatalRC(rc);
4709	rc = VINF_SUCCESS;
4710
4711	# ifdef IN_RC
4712	/*
4713	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4714	* state will be inconsistent! Flush important things now while
4715	* we still can and then make sure there are no ring-3 calls.
4716	*/
4717	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4718	VMMRZCallRing3Disable(pVCpu);
4719	# endif
4720
4721	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4722	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4723	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4724	# ifdef IN_RING0
4725	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4726	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4727	# elif defined(IN_RC)
4728	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4729	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4730	# else
4731	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4732	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4733	# endif
4734
4735	# ifndef PGM_WITHOUT_MAPPINGS
4736	/*
4737	* Apply all hypervisor mappings to the new CR3.
4738	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4739	* make sure we check for conflicts in the new CR3 root.
4740	*/
4741	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4742	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4743	# endif
4744	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4745	AssertRCReturn(rc, rc);
4746	# endif
4747
4748	/* Set the current hypervisor CR3. */
4749	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4750	SELMShadowCR3Changed(pVM, pVCpu);
4751
4752	# ifdef IN_RC
4753	/* NOTE: The state is consistent again. */
4754	VMMRZCallRing3Enable(pVCpu);
4755	# endif
4756
4757	/* Clean up the old CR3 root. */
4758	if ( pOldShwPageCR3
4759	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4760	{
4761	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4762	# ifndef PGM_WITHOUT_MAPPINGS
4763	/* Remove the hypervisor mappings from the shadow page table. */
4764	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4765	# endif
4766	/* Mark the page as unlocked; allow flushing again. */
4767	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4768
4769	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4770	}
4771	pgmUnlock(pVM);
4772	# endif
4773
4774	return rc;
4775	}
4776
4777	/**
4778	* Unmaps the shadow CR3.
4779	*
4780	* @returns VBox status, no specials.
4781	* @param pVCpu The VMCPU handle.
4782	*/
4783	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4784	{
4785	LogFlow(("UnmapCR3\n"));
4786
4787	int rc = VINF_SUCCESS;
4788	PVM pVM = pVCpu->CTX_SUFF(pVM);
4789
4790	/*
4791	* Update guest paging info.
4792	*/
4793	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4794	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4795	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4796	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4797	# endif
4798	pVCpu->pgm.s.pGst32BitPdRC = 0;
4799
4800	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4801	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4802	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4803	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4804	# endif
4805	pVCpu->pgm.s.pGstPaePdptRC = 0;
4806	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4807	{
4808	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4809	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4810	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4811	# endif
4812	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4813	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4814	}
4815
4816	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4817	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4818	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4819	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4820	# endif
4821
4822	#else /* prot/real mode stub */
4823	/* nothing to do */
4824	#endif
4825
4826	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4827	/*
4828	* Update shadow paging info.
4829	*/
4830	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4831	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4832	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4833
4834	# if PGM_GST_TYPE != PGM_TYPE_REAL
4835	Assert(!pVM->pgm.s.fNestedPaging);
4836	# endif
4837
4838	pgmLock(pVM);
4839
4840	# ifndef PGM_WITHOUT_MAPPINGS
4841	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4842	/* Remove the hypervisor mappings from the shadow page table. */
4843	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4844	# endif
4845
4846	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4847	{
4848	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4849
4850	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4851
4852	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4853	if (pPool->cDirtyPages)
4854	pgmPoolResetDirtyPages(pVM);
4855	# endif
4856
4857	/* Mark the page as unlocked; allow flushing again. */
4858	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4859
4860	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4861	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4862	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4863	pVCpu->pgm.s.pShwPageCR3RC = 0;
4864	pVCpu->pgm.s.iShwUser = 0;
4865	pVCpu->pgm.s.iShwUserTable = 0;
4866	}
4867	pgmUnlock(pVM);
4868	# endif
4869	#endif /* !IN_RC*/
4870
4871	return rc;
4872	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 31101

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