PGMAllBth.h@ 31832

Last change on this file since 31832 was 31832, checked in by vboxsync, 15 years ago
PGM: The other w7-64 regression. Trouble is that they're using PTE bits 52:62 for something.
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File size: 199.3 KB

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1	/* $Id: PGMAllBth.h 31832 2010-08-21 00:04:57Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	}
561	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
562
563	/*
564	* Fetch the guest PDE, PDPE and PML4E.
565	*/
566	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
567	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
568	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
569
570	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
571	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
572	PX86PDPAE pPDDst;
573	# if PGM_GST_TYPE == PGM_TYPE_PAE
574	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
575	# else
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
577	# endif
578	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
579
580	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
581	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
582	PX86PDPAE pPDDst;
583	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
584	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
585	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
586	# else
587	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
588	# endif
589	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
590
591	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
592	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
593	PEPTPD pPDDst;
594	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
596	# endif
597	Assert(pPDDst);
598
599	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
600	/*
601	* Dirty page handling.
602	*
603	* If we successfully correct the write protection fault due to dirty bit
604	* tracking, then return immediately.
605	*/
606	if (uErr & X86_TRAP_PF_RW) /* write fault? */
607	{
608	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
609	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
610	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
612	{
613	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
614	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
615	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
616	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
617	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
618	return VINF_SUCCESS;
619	}
620	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
621	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
622	}
623
624	# if 0 /* rarely useful; leave for debugging. */
625	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
626	# endif
627	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
628
629	/*
630	* A common case is the not-present error caused by lazy page table syncing.
631	*
632	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
633	* here so we can safely assume that the shadow PT is present when calling
634	* SyncPage later.
635	*
636	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
637	* of mapping conflict and defer to SyncCR3 in R3.
638	* (Again, we do NOT support access handlers for non-present guest pages.)
639	*
640	*/
641	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
642	Assert(GstWalk.Pde.n.u1Present);
643	# endif
644	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
645	&& !pPDDst->a[iPDDst].n.u1Present)
646	{
647	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
648	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
649	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
650	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
651	# else
652	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
653	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
654	# endif
655	if (RT_SUCCESS(rc))
656	return rc;
657	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
658	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
659	return VINF_PGM_SYNC_CR3;
660	}
661
662	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
663	/*
664	* Check if this address is within any of our mappings.
665	*
666	* This is very fast and it's gonna save us a bit of effort below and prevent
667	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
668	* (BTW, it's impossible to have physical access handlers in a mapping.)
669	*/
670	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
671	{
672	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
673	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
674	{
675	if (pvFault < pMapping->GCPtr)
676	break;
677	if (pvFault - pMapping->GCPtr < pMapping->cb)
678	{
679	/*
680	* The first thing we check is if we've got an undetected conflict.
681	*/
682	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
683	{
684	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
685	while (iPT-- > 0)
686	if (GstWalk.pPde[iPT].n.u1Present)
687	{
688	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
689	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
690	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
691	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
692	return VINF_PGM_SYNC_CR3;
693	}
694	}
695
696	/*
697	* Check if the fault address is in a virtual page access handler range.
698	*/
699	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
700	if ( pCur
701	&& pvFault - pCur->Core.Key < pCur->cb
702	&& uErr & X86_TRAP_PF_RW)
703	{
704	# ifdef IN_RC
705	STAM_PROFILE_START(&pCur->Stat, h);
706	pgmUnlock(pVM);
707	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
708	pgmLock(pVM);
709	STAM_PROFILE_STOP(&pCur->Stat, h);
710	# else
711	AssertFailed();
712	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
713	# endif
714	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
715	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
716	return rc;
717	}
718
719	/*
720	* Pretend we're not here and let the guest handle the trap.
721	*/
722	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
723	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
724	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
725	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
726	return VINF_EM_RAW_GUEST_TRAP;
727	}
728	}
729	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
730	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
731
732	/*
733	* Check if this fault address is flagged for special treatment,
734	* which means we'll have to figure out the physical address and
735	* check flags associated with it.
736	*
737	* ASSUME that we can limit any special access handling to pages
738	* in page tables which the guest believes to be present.
739	*/
740	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
741	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
742	# else
743	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
745	PPGMPAGE pPage;
746	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
747	if (RT_FAILURE(rc))
748	{
749	/*
750	* When the guest accesses invalid physical memory (e.g. probing
751	* of RAM or accessing a remapped MMIO range), then we'll fall
752	* back to the recompiler to emulate the instruction.
753	*/
754	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
755	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
756	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
757	return VINF_EM_RAW_EMULATE_INSTR;
758	}
759
760	/*
761	* Any handlers for this page?
762	*/
763	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
764	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
765	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
766	&GstWalk));
767	# else
768	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
769	# endif
770
771	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
772
773	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
774	if (uErr & X86_TRAP_PF_P)
775	{
776	/*
777	* The page isn't marked, but it might still be monitored by a virtual page access handler.
778	* (ASSUMES no temporary disabling of virtual handlers.)
779	*/
780	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
781	* we should correct both the shadow page table and physical memory flags, and not only check for
782	* accesses within the handler region but for access to pages with virtual handlers. */
783	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
784	if (pCur)
785	{
786	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
787	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
788	\|\| !(uErr & X86_TRAP_PF_P)
789	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
790	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
791
792	if ( pvFault - pCur->Core.Key < pCur->cb
793	&& ( uErr & X86_TRAP_PF_RW
794	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
795	{
796	# ifdef IN_RC
797	STAM_PROFILE_START(&pCur->Stat, h);
798	pgmUnlock(pVM);
799	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
800	pgmLock(pVM);
801	STAM_PROFILE_STOP(&pCur->Stat, h);
802	# else
803	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
804	# endif
805	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
806	return rc;
807	}
808	}
809	}
810	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
811
812	/*
813	* We are here only if page is present in Guest page tables and
814	* trap is not handled by our handlers.
815	*
816	* Check it for page out-of-sync situation.
817	*/
818	if (!(uErr & X86_TRAP_PF_P))
819	{
820	/*
821	* Page is not present in our page tables. Try to sync it!
822	*/
823	if (uErr & X86_TRAP_PF_US)
824	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
825	else /* supervisor */
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
827
828	if (PGM_PAGE_IS_BALLOONED(pPage))
829	{
830	/* Emulate reads from ballooned pages as they are not present in
831	our shadow page tables. (Required for e.g. Solaris guests; soft
832	ecc, random nr generator.) */
833	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
834	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
835	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
836	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
837	return rc;
838	}
839
840	# if defined(LOG_ENABLED) && !defined(IN_RING0)
841	RTGCPHYS GCPhys2;
842	uint64_t fPageGst2;
843	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
844	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
845	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
846	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
847	# else
848	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
849	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
850	# endif
851	# endif /* LOG_ENABLED */
852
853	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
854	if ( !GstWalk.Core.fEffectiveUS
855	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
856	{
857	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
858	if ( pvFault == (RTGCPTR)pRegFrame->eip
859	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
860	# ifdef CSAM_DETECT_NEW_CODE_PAGES
861	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
862	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
863	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
864	)
865	{
866	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
867	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
868	if (rc != VINF_SUCCESS)
869	{
870	/*
871	* CSAM needs to perform a job in ring 3.
872	*
873	* Sync the page before going to the host context; otherwise we'll end up in a loop if
874	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
875	*/
876	LogFlow(("CSAM ring 3 job\n"));
877	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
878	AssertRC(rc2);
879
880	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
881	return rc;
882	}
883	}
884	# ifdef CSAM_DETECT_NEW_CODE_PAGES
885	else if ( uErr == X86_TRAP_PF_RW
886	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
887	&& pRegFrame->ecx < 0x10000)
888	{
889	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
890	* to detect loading of new code pages.
891	*/
892
893	/*
894	* Decode the instruction.
895	*/
896	RTGCPTR PC;
897	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
898	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
899	if (rc == VINF_SUCCESS)
900	{
901	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
902	uint32_t cbOp;
903	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
904
905	/* For now we'll restrict this to rep movsw/d instructions */
906	if ( rc == VINF_SUCCESS
907	&& pDis->pCurInstr->opcode == OP_MOVSWD
908	&& (pDis->prefix & PREFIX_REP))
909	{
910	CSAMMarkPossibleCodePage(pVM, pvFault);
911	}
912	}
913	}
914	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
915
916	/*
917	* Mark this page as safe.
918	*/
919	/** @todo not correct for pages that contain both code and data!! */
920	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
921	CSAMMarkPage(pVM, pvFault, true);
922	}
923	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
924	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
925	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
926	# else
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# endif
929	if (RT_SUCCESS(rc))
930	{
931	/* The page was successfully synced, return to the guest. */
932	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
933	return VINF_SUCCESS;
934	}
935	}
936	else /* uErr & X86_TRAP_PF_P: */
937	{
938	/*
939	* Write protected pages are made writable when the guest makes the
940	* first write to it. This happens for pages that are shared, write
941	* monitored or not yet allocated.
942	*
943	* We may also end up here when CR0.WP=0 in the guest.
944	*
945	* Also, a side effect of not flushing global PDEs are out of sync
946	* pages due to physical monitored regions, that are no longer valid.
947	* Assume for now it only applies to the read/write flag.
948	*/
949	if (uErr & X86_TRAP_PF_RW)
950	{
951	/*
952	* Check if it is a read-only page.
953	*/
954	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
955	{
956	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
957	Assert(!PGM_PAGE_IS_ZERO(pPage));
958	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
959	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
960
961	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
962	if (rc != VINF_SUCCESS)
963	{
964	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
965	return rc;
966	}
967	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
968	return VINF_EM_NO_MEMORY;
969	}
970
971	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
972	/*
973	* Check to see if we need to emulate the instruction if CR0.WP=0.
974	*/
975	if ( !GstWalk.Core.fEffectiveRW
976	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
977	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
978	{
979	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
980	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
981	if (RT_SUCCESS(rc))
982	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
983	else
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
985	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
986	return rc;
987	}
988	# endif
989	/// @todo count the above case; else
990	if (uErr & X86_TRAP_PF_US)
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
992	else /* supervisor */
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
994
995	/*
996	* Sync the page.
997	*
998	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
999	* page is not present, which is not true in this case.
1000	*/
1001	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1002	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1003	# else
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1005	# endif
1006	if (RT_SUCCESS(rc))
1007	{
1008	/*
1009	* Page was successfully synced, return to guest but invalidate
1010	* the TLB first as the page is very likely to be in it.
1011	*/
1012	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1013	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1014	# else
1015	PGM_INVL_PG(pVCpu, pvFault);
1016	# endif
1017	# ifdef VBOX_STRICT
1018	RTGCPHYS GCPhys2;
1019	uint64_t fPageGst;
1020	if (!pVM->pgm.s.fNestedPaging)
1021	{
1022	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1023	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1024	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1025	}
1026	uint64_t fPageShw;
1027	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1028	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1029	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1030	# endif /* VBOX_STRICT */
1031	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1032	return VINF_SUCCESS;
1033	}
1034	}
1035	/** @todo else: why are we here? */
1036
1037	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1038	/*
1039	* Check for VMM page flags vs. Guest page flags consistency.
1040	* Currently only for debug purposes.
1041	*/
1042	if (RT_SUCCESS(rc))
1043	{
1044	/* Get guest page flags. */
1045	uint64_t fPageGst;
1046	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1047	if (RT_SUCCESS(rc))
1048	{
1049	uint64_t fPageShw;
1050	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1051
1052	/*
1053	* Compare page flags.
1054	* Note: we have AVL, A, D bits desynched.
1055	*/
1056	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1057	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1058	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1059	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1060	}
1061	else
1062	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1063	}
1064	else
1065	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1066	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1067	}
1068
1069
1070	/*
1071	* If we get here it is because something failed above, i.e. most like guru
1072	* meditiation time.
1073	*/
1074	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1075	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1076	return rc;
1077
1078	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1079	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1080	return VERR_INTERNAL_ERROR;
1081	# endif
1082	}
1083	#endif /* !IN_RING3 */
1084
1085
1086	/**
1087	* Emulation of the invlpg instruction.
1088	*
1089	*
1090	* @returns VBox status code.
1091	*
1092	* @param pVCpu The VMCPU handle.
1093	* @param GCPtrPage Page to invalidate.
1094	*
1095	* @remark ASSUMES that the guest is updating before invalidating. This order
1096	* isn't required by the CPU, so this is speculative and could cause
1097	* trouble.
1098	* @remark No TLB shootdown is done on any other VCPU as we assume that
1099	* invlpg emulation is the only reason for calling this function.
1100	* (The guest has to shoot down TLB entries on other CPUs itself)
1101	* Currently true, but keep in mind!
1102	*
1103	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1104	*/
1105	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1106	{
1107	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1108	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1109	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1110	int rc;
1111	PVM pVM = pVCpu->CTX_SUFF(pVM);
1112	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1113
1114	Assert(PGMIsLockOwner(pVM));
1115
1116	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1117
1118	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1119	if (pPool->cDirtyPages)
1120	pgmPoolResetDirtyPages(pVM);
1121	# endif
1122
1123	/*
1124	* Get the shadow PD entry and skip out if this PD isn't present.
1125	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1126	*/
1127	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1128	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1129	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1130
1131	/* Fetch the pgm pool shadow descriptor. */
1132	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1133	Assert(pShwPde);
1134
1135	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1136	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1137	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1138
1139	/* If the shadow PDPE isn't present, then skip the invalidate. */
1140	if (!pPdptDst->a[iPdpt].n.u1Present)
1141	{
1142	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1143	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1144	return VINF_SUCCESS;
1145	}
1146
1147	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1148	PPGMPOOLPAGE pShwPde = NULL;
1149	PX86PDPAE pPDDst;
1150
1151	/* Fetch the pgm pool shadow descriptor. */
1152	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1153	AssertRCSuccessReturn(rc, rc);
1154	Assert(pShwPde);
1155
1156	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1157	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1158
1159	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1160	/* PML4 */
1161	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1162	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1163	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1164	PX86PDPAE pPDDst;
1165	PX86PDPT pPdptDst;
1166	PX86PML4E pPml4eDst;
1167	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1168	if (rc != VINF_SUCCESS)
1169	{
1170	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1171	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1172	return VINF_SUCCESS;
1173	}
1174	Assert(pPDDst);
1175
1176	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1177	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1178
1179	if (!pPdpeDst->n.u1Present)
1180	{
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1182	return VINF_SUCCESS;
1183	}
1184
1185	/* Fetch the pgm pool shadow descriptor. */
1186	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1187	Assert(pShwPde);
1188
1189	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1190
1191	const SHWPDE PdeDst = *pPdeDst;
1192	if (!PdeDst.n.u1Present)
1193	{
1194	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1195	return VINF_SUCCESS;
1196	}
1197
1198	/*
1199	* Get the guest PD entry and calc big page.
1200	*/
1201	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1202	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1203	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1204	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1205	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1206	unsigned iPDSrc = 0;
1207	# if PGM_GST_TYPE == PGM_TYPE_PAE
1208	X86PDPE PdpeSrcIgn;
1209	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1210	# else /* AMD64 */
1211	PX86PML4E pPml4eSrcIgn;
1212	X86PDPE PdpeSrcIgn;
1213	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1214	# endif
1215	GSTPDE PdeSrc;
1216
1217	if (pPDSrc)
1218	PdeSrc = pPDSrc->a[iPDSrc];
1219	else
1220	PdeSrc.u = 0;
1221	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1222	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1223
1224	# ifdef IN_RING3
1225	/*
1226	* If a CR3 Sync is pending we may ignore the invalidate page operation
1227	* depending on the kind of sync and if it's a global page or not.
1228	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1229	*/
1230	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1231	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1232	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1233	&& fIsBigPage
1234	&& PdeSrc.b.u1Global
1235	)
1236	)
1237	# else
1238	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1239	# endif
1240	{
1241	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1242	return VINF_SUCCESS;
1243	}
1244	# endif /* IN_RING3 */
1245
1246	/*
1247	* Deal with the Guest PDE.
1248	*/
1249	rc = VINF_SUCCESS;
1250	if (PdeSrc.n.u1Present)
1251	{
1252	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1253	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1254	# ifndef PGM_WITHOUT_MAPPING
1255	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1256	{
1257	/*
1258	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1259	*/
1260	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1261	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1263	}
1264	else
1265	# endif /* !PGM_WITHOUT_MAPPING */
1266	if (!fIsBigPage)
1267	{
1268	/*
1269	* 4KB - page.
1270	*/
1271	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1272	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1273
1274	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1275	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1276	if (pShwPage->cModifications)
1277	pShwPage->cModifications = 1;
1278	# endif
1279
1280	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1281	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1282	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1283	# endif
1284	if (pShwPage->GCPhys == GCPhys)
1285	{
1286	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1287	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1288	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1289	if (pPT->a[iPTEDst].n.u1Present)
1290	{
1291	/* This is very unlikely with caching/monitoring enabled. */
1292	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1293	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1294	}
1295	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1296	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1297	if (RT_SUCCESS(rc))
1298	rc = VINF_SUCCESS;
1299	# endif
1300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1301	PGM_INVL_PG(pVCpu, GCPtrPage);
1302	}
1303	else
1304	{
1305	/*
1306	* The page table address changed.
1307	*/
1308	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1309	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1310	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1311	ASMAtomicWriteSize(pPdeDst, 0);
1312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1313	PGM_INVL_VCPU_TLBS(pVCpu);
1314	}
1315	}
1316	else
1317	{
1318	/*
1319	* 2/4MB - page.
1320	*/
1321	/* Before freeing the page, check if anything really changed. */
1322	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1323	RTGCPHYS GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
1324	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1325	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1326	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1327	# endif
1328	if ( pShwPage->GCPhys == GCPhys
1329	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1330	{
1331	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1332	/** @todo PAT */
1333	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1334	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1335	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1336	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1337	{
1338	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1340	return VINF_SUCCESS;
1341	}
1342	}
1343
1344	/*
1345	* Ok, the page table is present and it's been changed in the guest.
1346	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1347	* We could do this for some flushes in GC too, but we need an algorithm for
1348	* deciding which 4MB pages containing code likely to be executed very soon.
1349	*/
1350	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1351	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1352	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1353	ASMAtomicWriteSize(pPdeDst, 0);
1354	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1355	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1356	}
1357	}
1358	else
1359	{
1360	/*
1361	* Page directory is not present, mark shadow PDE not present.
1362	*/
1363	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1364	{
1365	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1366	ASMAtomicWriteSize(pPdeDst, 0);
1367	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1368	PGM_INVL_PG(pVCpu, GCPtrPage);
1369	}
1370	else
1371	{
1372	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1373	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1374	}
1375	}
1376	return rc;
1377
1378	#else /* guest real and protected mode */
1379	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1380	return VINF_SUCCESS;
1381	#endif
1382	}
1383
1384
1385	/**
1386	* Update the tracking of shadowed pages.
1387	*
1388	* @param pVCpu The VMCPU handle.
1389	* @param pShwPage The shadow page.
1390	* @param HCPhys The physical page we is being dereferenced.
1391	* @param iPte Shadow PTE index
1392	*/
1393	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1394	{
1395	PVM pVM = pVCpu->CTX_SUFF(pVM);
1396
1397	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1398	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1399
1400	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1401	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1402	* 2. write protect all shadowed pages. I.e. implement caching.
1403	*/
1404	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1405
1406	/*
1407	* Find the guest address.
1408	*/
1409	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1410	pRam;
1411	pRam = pRam->CTX_SUFF(pNext))
1412	{
1413	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1414	while (iPage-- > 0)
1415	{
1416	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1417	{
1418	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1419
1420	Assert(pShwPage->cPresent);
1421	Assert(pPool->cPresent);
1422	pShwPage->cPresent--;
1423	pPool->cPresent--;
1424
1425	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1426	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1427	return;
1428	}
1429	}
1430	}
1431
1432	for (;;)
1433	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1434	}
1435
1436
1437	/**
1438	* Update the tracking of shadowed pages.
1439	*
1440	* @param pVCpu The VMCPU handle.
1441	* @param pShwPage The shadow page.
1442	* @param u16 The top 16-bit of the pPage->HCPhys.
1443	* @param pPage Pointer to the guest page. this will be modified.
1444	* @param iPTDst The index into the shadow table.
1445	*/
1446	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1447	{
1448	PVM pVM = pVCpu->CTX_SUFF(pVM);
1449
1450	/*
1451	* Just deal with the simple first time here.
1452	*/
1453	if (!u16)
1454	{
1455	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1456	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1457	/* Save the page table index. */
1458	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1459	}
1460	else
1461	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1462
1463	/* write back */
1464	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1465	PGM_PAGE_SET_TRACKING(pPage, u16);
1466
1467	/* update statistics. */
1468	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1469	pShwPage->cPresent++;
1470	if (pShwPage->iFirstPresent > iPTDst)
1471	pShwPage->iFirstPresent = iPTDst;
1472	}
1473
1474
1475	/**
1476	* Modifies a shadow PTE to account for access handlers.
1477	*
1478	* @param pVM The VM handle.
1479	* @param pPage The page in question.
1480	* @param fPteSrc The flags of the source PTE.
1481	* @param pPteDst The shadow PTE (output). This is temporary storage and
1482	* does not need to be set atomically.
1483	*/
1484	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint32_t fPteSrc, PSHWPTE pPteDst)
1485	{
1486	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1487	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1488	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1489	{
1490	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1491	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1492	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1493	pPteDst->n.u1Present = 1;
1494	pPteDst->n.u1Execute = 1;
1495	pPteDst->n.u1IgnorePAT = 1;
1496	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1497	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1498	#else
1499	SHW_PTE_SET(*pPteDst,
1500	(fPteSrc & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1501	\| PGM_PAGE_GET_HCPHYS(pPage));
1502	#endif
1503	}
1504	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1505	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1506	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1507	&& ( BTH_IS_NP_ACTIVE(pVM)
1508	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1509	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1510	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1511	# endif
1512	)
1513	{
1514	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1515	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1516	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1517	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1518	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1519	pPteDst->n.u1Present = 0;
1520	pPteDst->n.u1Write = 1;
1521	pPteDst->n.u1Execute = 0;
1522	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1523	pPteDst->n.u3EMT = 7;
1524	# else
1525	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1526	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1527	# endif
1528	}
1529	# endif
1530	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1531	else
1532	{
1533	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1534	SHW_PTE_SET(*pPteDst, 0);
1535	}
1536	/** @todo count these kinds of entries. */
1537	}
1538
1539
1540	/**
1541	* Creates a 4K shadow page for a guest page.
1542	*
1543	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1544	* physical address. The PdeSrc argument only the flags are used. No page
1545	* structured will be mapped in this function.
1546	*
1547	* @param pVCpu The VMCPU handle.
1548	* @param pPteDst Destination page table entry.
1549	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1550	* Can safely assume that only the flags are being used.
1551	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1552	* @param pShwPage Pointer to the shadow page.
1553	* @param iPTDst The index into the shadow table.
1554	*
1555	* @remark Not used for 2/4MB pages!
1556	*/
1557	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1558	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1559	{
1560	if ( PteSrc.n.u1Present
1561	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1562	{
1563	PVM pVM = pVCpu->CTX_SUFF(pVM);
1564
1565	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1566	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1567	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1568	if (pShwPage->fDirty)
1569	{
1570	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1571	PX86PTPAE pGstPT;
1572
1573	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1574	pGstPT->a[iPTDst].u = PteSrc.u;
1575	}
1576	# endif
1577	/*
1578	* Find the ram range.
1579	*/
1580	PPGMPAGE pPage;
1581	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1582	if (RT_SUCCESS(rc))
1583	{
1584	/* Ignore ballooned pages.
1585	Don't return errors or use a fatal assert here as part of a
1586	shadow sync range might included ballooned pages. */
1587	if (PGM_PAGE_IS_BALLOONED(pPage))
1588	{
1589	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1590	return;
1591	}
1592
1593	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1594	/* Make the page writable if necessary. */
1595	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1596	&& ( PGM_PAGE_IS_ZERO(pPage)
1597	\|\| ( PteSrc.n.u1Write
1598	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1599	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1600	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1601	# endif
1602	# ifdef VBOX_WITH_PAGE_SHARING
1603	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1604	# endif
1605	)
1606	)
1607	)
1608	{
1609	rc = pgmPhysPageMakeWritable(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1610	AssertRC(rc);
1611	}
1612	#endif
1613
1614	/*
1615	* Make page table entry.
1616	*/
1617	SHWPTE PteDst;
1618	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1619	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage,
1620	PteSrc.u & ~( X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK
1621	\| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT),
1622	&PteDst);
1623	else
1624	{
1625	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1626	/*
1627	* If the page or page directory entry is not marked accessed,
1628	* we mark the page not present.
1629	*/
1630	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1631	{
1632	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1633	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1634	SHW_PTE_SET(PteDst, 0);
1635	}
1636	/*
1637	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1638	* when the page is modified.
1639	*/
1640	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1641	{
1642	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1643	SHW_PTE_SET(PteDst,
1644	(PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1645	\| PGM_PAGE_GET_HCPHYS(pPage)
1646	\| PGM_PTFLAGS_TRACK_DIRTY);
1647	}
1648	else
1649	#endif
1650	{
1651	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1652	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1653	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1654	PteDst.n.u1Present = 1;
1655	PteDst.n.u1Write = 1;
1656	PteDst.n.u1Execute = 1;
1657	PteDst.n.u1IgnorePAT = 1;
1658	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1659	/* PteDst.n.u1Size = 0 */
1660	#else
1661	SHW_PTE_SET(PteDst,
1662	(PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1663	\| PGM_PAGE_GET_HCPHYS(pPage));
1664	#endif
1665	}
1666
1667	/*
1668	* Make sure only allocated pages are mapped writable.
1669	*/
1670	if ( SHW_PTE_IS_P_RW(PteDst)
1671	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1672	{
1673	/* Still applies to shared pages. */
1674	Assert(!PGM_PAGE_IS_ZERO(pPage));
1675	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1676	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1677	}
1678	}
1679
1680	/*
1681	* Keep user track up to date.
1682	*/
1683	if (SHW_PTE_IS_P(PteDst))
1684	{
1685	if (!SHW_PTE_IS_P(*pPteDst))
1686	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1687	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1688	{
1689	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1690	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1691	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1692	}
1693	}
1694	else if (SHW_PTE_IS_P(*pPteDst))
1695	{
1696	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1697	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1698	}
1699
1700	/*
1701	* Update statistics and commit the entry.
1702	*/
1703	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1704	if (!PteSrc.n.u1Global)
1705	pShwPage->fSeenNonGlobal = true;
1706	#endif
1707	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1708	return;
1709	}
1710
1711	/** @todo count these three different kinds. */
1712	Log2(("SyncPageWorker: invalid address in Pte\n"));
1713	}
1714	else if (!PteSrc.n.u1Present)
1715	Log2(("SyncPageWorker: page not present in Pte\n"));
1716	else
1717	Log2(("SyncPageWorker: invalid Pte\n"));
1718
1719	/*
1720	* The page is not present or the PTE is bad. Replace the shadow PTE by
1721	* an empty entry, making sure to keep the user tracking up to date.
1722	*/
1723	if (SHW_PTE_IS_P(*pPteDst))
1724	{
1725	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1726	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1727	}
1728	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1729	}
1730
1731
1732	/**
1733	* Syncs a guest OS page.
1734	*
1735	* There are no conflicts at this point, neither is there any need for
1736	* page table allocations.
1737	*
1738	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1739	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1740	*
1741	* @returns VBox status code.
1742	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1743	* @param pVCpu The VMCPU handle.
1744	* @param PdeSrc Page directory entry of the guest.
1745	* @param GCPtrPage Guest context page address.
1746	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1747	* @param uErr Fault error (X86_TRAP_PF_*).
1748	*/
1749	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1750	{
1751	PVM pVM = pVCpu->CTX_SUFF(pVM);
1752	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1753	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1754
1755	Assert(PGMIsLockOwner(pVM));
1756
1757	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1758	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1759	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1760	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1761	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1762
1763	/*
1764	* Assert preconditions.
1765	*/
1766	Assert(PdeSrc.n.u1Present);
1767	Assert(cPages);
1768	# if 0 /* rarely useful; leave for debugging. */
1769	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1770	# endif
1771
1772	/*
1773	* Get the shadow PDE, find the shadow page table in the pool.
1774	*/
1775	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1776	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1777	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1778
1779	/* Fetch the pgm pool shadow descriptor. */
1780	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1781	Assert(pShwPde);
1782
1783	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1784	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1785	PPGMPOOLPAGE pShwPde = NULL;
1786	PX86PDPAE pPDDst;
1787
1788	/* Fetch the pgm pool shadow descriptor. */
1789	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1790	AssertRCSuccessReturn(rc2, rc2);
1791	Assert(pShwPde);
1792
1793	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1794	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1795
1796	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1797	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1798	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1799	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1800	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1801
1802	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1803	AssertRCSuccessReturn(rc2, rc2);
1804	Assert(pPDDst && pPdptDst);
1805	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1806	# endif
1807	SHWPDE PdeDst = *pPdeDst;
1808
1809	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1810	if (!PdeDst.n.u1Present)
1811	{
1812	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1813	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
1814	return VINF_SUCCESS; /* force the instruction to be executed again. */
1815	}
1816
1817	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1818	Assert(pShwPage);
1819
1820	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1821	/* Fetch the pgm pool shadow descriptor. */
1822	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1823	Assert(pShwPde);
1824	# endif
1825
1826	/*
1827	* Check that the page is present and that the shadow PDE isn't out of sync.
1828	*/
1829	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1830	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1831	RTGCPHYS GCPhys;
1832	if (!fBigPage)
1833	{
1834	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1835	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1836	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1837	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1838	# endif
1839	}
1840	else
1841	{
1842	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
1843	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1844	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1845	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1846	# endif
1847	}
1848	if ( fPdeValid
1849	&& pShwPage->GCPhys == GCPhys
1850	&& PdeSrc.n.u1Present
1851	&& PdeSrc.n.u1User == PdeDst.n.u1User
1852	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1853	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1854	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1855	# endif
1856	)
1857	{
1858	/*
1859	* Check that the PDE is marked accessed already.
1860	* Since we set the accessed bit before getting here on a #PF, this
1861	* check is only meant for dealing with non-#PF'ing paths.
1862	*/
1863	if (PdeSrc.n.u1Accessed)
1864	{
1865	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1866	if (!fBigPage)
1867	{
1868	/*
1869	* 4KB Page - Map the guest page table.
1870	*/
1871	PGSTPT pPTSrc;
1872	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1873	if (RT_SUCCESS(rc))
1874	{
1875	# ifdef PGM_SYNC_N_PAGES
1876	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1877	if ( cPages > 1
1878	&& !(uErr & X86_TRAP_PF_P)
1879	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1880	{
1881	/*
1882	* This code path is currently only taken when the caller is PGMTrap0eHandler
1883	* for non-present pages!
1884	*
1885	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1886	* deal with locality.
1887	*/
1888	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1889	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1890	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1891	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1892	# else
1893	const unsigned offPTSrc = 0;
1894	# endif
1895	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1896	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1897	iPTDst = 0;
1898	else
1899	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1900	for (; iPTDst < iPTDstEnd; iPTDst++)
1901	{
1902	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1903	{
1904	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1905	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1906	NOREF(GCPtrCurPage);
1907	#ifndef IN_RING0
1908	/*
1909	* Assuming kernel code will be marked as supervisor - and not as user level
1910	* and executed using a conforming code selector - And marked as readonly.
1911	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1912	*/
1913	PPGMPAGE pPage;
1914	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1915	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1916	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1917	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1918	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1919	)
1920	#endif /* else: CSAM not active */
1921	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1922	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1923	GCPtrCurPage, PteSrc.n.u1Present,
1924	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1925	PteSrc.n.u1User & PdeSrc.n.u1User,
1926	(uint64_t)PteSrc.u,
1927	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1928	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1929	}
1930	}
1931	}
1932	else
1933	# endif /* PGM_SYNC_N_PAGES */
1934	{
1935	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1936	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1937	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1938	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1939	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1940	GCPtrPage, PteSrc.n.u1Present,
1941	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1942	PteSrc.n.u1User & PdeSrc.n.u1User,
1943	(uint64_t)PteSrc.u,
1944	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1945	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1946	}
1947	}
1948	else /* MMIO or invalid page: emulated in #PF handler. */
1949	{
1950	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1951	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1952	}
1953	}
1954	else
1955	{
1956	/*
1957	* 4/2MB page - lazy syncing shadow 4K pages.
1958	* (There are many causes of getting here, it's no longer only CSAM.)
1959	*/
1960	/* Calculate the GC physical address of this 4KB shadow page. */
1961	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1962	/* Find ram range. */
1963	PPGMPAGE pPage;
1964	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1965	if (RT_SUCCESS(rc))
1966	{
1967	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1968
1969	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1970	/* Try to make the page writable if necessary. */
1971	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1972	&& ( PGM_PAGE_IS_ZERO(pPage)
1973	\|\| ( PdeSrc.n.u1Write
1974	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1975	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1976	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1977	# endif
1978	# ifdef VBOX_WITH_PAGE_SHARING
1979	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1980	# endif
1981	)
1982	)
1983	)
1984	{
1985	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1986	AssertRC(rc);
1987	}
1988	# endif
1989
1990	/*
1991	* Make shadow PTE entry.
1992	*/
1993	SHWPTE PteDst;
1994	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1995	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage,
1996	PdeSrc.u & ~( X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK
1997	\| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT),
1998	&PteDst);
1999	else
2000	SHW_PTE_SET(PteDst,
2001	(PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
2002	\| PGM_PAGE_GET_HCPHYS(pPage));
2003
2004	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2005	if ( SHW_PTE_IS_P(PteDst)
2006	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2007	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2008
2009	/* Make sure only allocated pages are mapped writable. */
2010	if ( SHW_PTE_IS_P_RW(PteDst)
2011	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2012	{
2013	/* Still applies to shared pages. */
2014	Assert(!PGM_PAGE_IS_ZERO(pPage));
2015	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2016	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2017	}
2018
2019	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2020
2021	/*
2022	* If the page is not flagged as dirty and is writable, then make it read-only
2023	* at PD level, so we can set the dirty bit when the page is modified.
2024	*
2025	* ASSUMES that page access handlers are implemented on page table entry level.
2026	* Thus we will first catch the dirty access and set PDE.D and restart. If
2027	* there is an access handler, we'll trap again and let it work on the problem.
2028	*/
2029	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2030	* As for invlpg, it simply frees the whole shadow PT.
2031	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2032	if ( !PdeSrc.b.u1Dirty
2033	&& PdeSrc.b.u1Write)
2034	{
2035	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2036	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2037	PdeDst.n.u1Write = 0;
2038	}
2039	else
2040	{
2041	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2042	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2043	}
2044	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2045	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2046	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2047	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2048	}
2049	else
2050	{
2051	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2052	/** @todo must wipe the shadow page table in this case. */
2053	}
2054	}
2055	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2056	return VINF_SUCCESS;
2057	}
2058
2059	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2060	}
2061	else if (fPdeValid)
2062	{
2063	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2064	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2065	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2066	}
2067	else
2068	{
2069	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2070	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2071	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2072	}
2073
2074	/*
2075	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2076	* Yea, I'm lazy.
2077	*/
2078	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2079	ASMAtomicWriteSize(pPdeDst, 0);
2080
2081	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2082	PGM_INVL_VCPU_TLBS(pVCpu);
2083	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2084
2085
2086	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2087	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2088	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2089	&& !defined(IN_RC)
2090
2091	# ifdef PGM_SYNC_N_PAGES
2092	/*
2093	* Get the shadow PDE, find the shadow page table in the pool.
2094	*/
2095	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2096	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2097
2098	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2099	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2100
2101	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2102	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2103	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2104	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2105	X86PDEPAE PdeDst;
2106	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2107
2108	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2109	AssertRCSuccessReturn(rc, rc);
2110	Assert(pPDDst && pPdptDst);
2111	PdeDst = pPDDst->a[iPDDst];
2112	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2113	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2114	PEPTPD pPDDst;
2115	EPTPDE PdeDst;
2116
2117	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2118	if (rc != VINF_SUCCESS)
2119	{
2120	AssertRC(rc);
2121	return rc;
2122	}
2123	Assert(pPDDst);
2124	PdeDst = pPDDst->a[iPDDst];
2125	# endif
2126	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2127	if (!PdeDst.n.u1Present)
2128	{
2129	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2130	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2131	return VINF_SUCCESS; /* force the instruction to be executed again. */
2132	}
2133
2134	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2135	if (PdeDst.n.u1Size)
2136	{
2137	Assert(pVM->pgm.s.fNestedPaging);
2138	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2139	return VINF_SUCCESS;
2140	}
2141
2142	/* Mask away the page offset. */
2143	GCPtrPage &= ~((RTGCPTR)0xfff);
2144
2145	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2146	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2147
2148	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2149	if ( cPages > 1
2150	&& !(uErr & X86_TRAP_PF_P)
2151	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2152	{
2153	/*
2154	* This code path is currently only taken when the caller is PGMTrap0eHandler
2155	* for non-present pages!
2156	*
2157	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2158	* deal with locality.
2159	*/
2160	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2161	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2162	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2163	iPTDst = 0;
2164	else
2165	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2166	for (; iPTDst < iPTDstEnd; iPTDst++)
2167	{
2168	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2169	{
2170	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2171	GSTPTE PteSrc;
2172
2173	/* Fake the page table entry */
2174	PteSrc.u = GCPtrCurPage;
2175	PteSrc.n.u1Present = 1;
2176	PteSrc.n.u1Dirty = 1;
2177	PteSrc.n.u1Accessed = 1;
2178	PteSrc.n.u1Write = 1;
2179	PteSrc.n.u1User = 1;
2180
2181	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2182	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2183	GCPtrCurPage, PteSrc.n.u1Present,
2184	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2185	PteSrc.n.u1User & PdeSrc.n.u1User,
2186	(uint64_t)PteSrc.u,
2187	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2188	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2189
2190	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2191	break;
2192	}
2193	else
2194	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2195	}
2196	}
2197	else
2198	# endif /* PGM_SYNC_N_PAGES */
2199	{
2200	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2201	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2202	GSTPTE PteSrc;
2203
2204	/* Fake the page table entry */
2205	PteSrc.u = GCPtrCurPage;
2206	PteSrc.n.u1Present = 1;
2207	PteSrc.n.u1Dirty = 1;
2208	PteSrc.n.u1Accessed = 1;
2209	PteSrc.n.u1Write = 1;
2210	PteSrc.n.u1User = 1;
2211	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2212
2213	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2214	GCPtrPage, PteSrc.n.u1Present,
2215	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2216	PteSrc.n.u1User & PdeSrc.n.u1User,
2217	(uint64_t)PteSrc.u,
2218	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2219	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2220	}
2221	return VINF_SUCCESS;
2222
2223	#else
2224	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2225	return VERR_INTERNAL_ERROR;
2226	#endif
2227	}
2228
2229
2230	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2231
2232	/**
2233	* CheckPageFault helper for returning a page fault indicating a non-present
2234	* (NP) entry in the page translation structures.
2235	*
2236	* @returns VINF_EM_RAW_GUEST_TRAP.
2237	* @param pVCpu The virtual CPU to operate on.
2238	* @param uErr The error code of the shadow fault. Corrections to
2239	* TRPM's copy will be made if necessary.
2240	* @param GCPtrPage For logging.
2241	* @param uPageFaultLevel For logging.
2242	*/
2243	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2244	{
2245	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2246	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2247	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2248	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2249	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2250
2251	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2252	return VINF_EM_RAW_GUEST_TRAP;
2253	}
2254
2255
2256	/**
2257	* CheckPageFault helper for returning a page fault indicating a reserved bit
2258	* (RSVD) error in the page translation structures.
2259	*
2260	* @returns VINF_EM_RAW_GUEST_TRAP.
2261	* @param pVCpu The virtual CPU to operate on.
2262	* @param uErr The error code of the shadow fault. Corrections to
2263	* TRPM's copy will be made if necessary.
2264	* @param GCPtrPage For logging.
2265	* @param uPageFaultLevel For logging.
2266	*/
2267	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2268	{
2269	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2270	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2271	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2272
2273	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2274	return VINF_EM_RAW_GUEST_TRAP;
2275	}
2276
2277
2278	/**
2279	* CheckPageFault helper for returning a page protection fault (P).
2280	*
2281	* @returns VINF_EM_RAW_GUEST_TRAP.
2282	* @param pVCpu The virtual CPU to operate on.
2283	* @param uErr The error code of the shadow fault. Corrections to
2284	* TRPM's copy will be made if necessary.
2285	* @param GCPtrPage For logging.
2286	* @param uPageFaultLevel For logging.
2287	*/
2288	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2289	{
2290	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2291	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2292	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2293	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2294
2295	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2296	return VINF_EM_RAW_GUEST_TRAP;
2297	}
2298
2299
2300	/**
2301	* Handle dirty bit tracking faults.
2302	*
2303	* @returns VBox status code.
2304	* @param pVCpu The VMCPU handle.
2305	* @param uErr Page fault error code.
2306	* @param pPdeSrc Guest page directory entry.
2307	* @param pPdeDst Shadow page directory entry.
2308	* @param GCPtrPage Guest context page address.
2309	*/
2310	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2311	{
2312	PVM pVM = pVCpu->CTX_SUFF(pVM);
2313	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2314
2315	Assert(PGMIsLockOwner(pVM));
2316
2317	/*
2318	* Handle big page.
2319	*/
2320	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2321	{
2322	if ( pPdeDst->n.u1Present
2323	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2324	{
2325	SHWPDE PdeDst = *pPdeDst;
2326
2327	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2328	Assert(pPdeSrc->b.u1Write);
2329
2330	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2331	* fault again and take this path to only invalidate the entry (see below).
2332	*/
2333	PdeDst.n.u1Write = 1;
2334	PdeDst.n.u1Accessed = 1;
2335	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2336	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2337	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2338	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2339	}
2340
2341	# ifdef IN_RING0
2342	/* Check for stale TLB entry; only applies to the SMP guest case. */
2343	if ( pVM->cCpus > 1
2344	&& pPdeDst->n.u1Write
2345	&& pPdeDst->n.u1Accessed)
2346	{
2347	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2348	if (pShwPage)
2349	{
2350	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2351	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2352	if (SHW_PTE_IS_P_RW(*pPteDst))
2353	{
2354	/* Stale TLB entry. */
2355	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2356	PGM_INVL_PG(pVCpu, GCPtrPage);
2357	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2358	}
2359	}
2360	}
2361	# endif /* IN_RING0 */
2362	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2363	}
2364
2365	/*
2366	* Map the guest page table.
2367	*/
2368	PGSTPT pPTSrc;
2369	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
2370	if (RT_FAILURE(rc))
2371	{
2372	AssertRC(rc);
2373	return rc;
2374	}
2375
2376	if (pPdeDst->n.u1Present)
2377	{
2378	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2379	const GSTPTE PteSrc = *pPteSrc;
2380
2381	#ifndef IN_RING0
2382	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2383	* Our individual shadow handlers will provide more information and force a fatal exit.
2384	*/
2385	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2386	{
2387	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2388	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2389	}
2390	#endif
2391	/*
2392	* Map shadow page table.
2393	*/
2394	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2395	if (pShwPage)
2396	{
2397	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2398	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2399	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2400	{
2401	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2402	{
2403	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2404	SHWPTE PteDst = *pPteDst;
2405
2406	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2407	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2408
2409	Assert(pPteSrc->n.u1Write);
2410
2411	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2412	* entry will not harm; write access will simply fault again and
2413	* take this path to only invalidate the entry.
2414	*/
2415	if (RT_LIKELY(pPage))
2416	{
2417	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2418	{
2419	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2420	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2421	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2422	SHW_PTE_SET_RO(PteDst);
2423	}
2424	else
2425	{
2426	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2427	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2428	{
2429	rc = pgmPhysPageMakeWritable(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2430	AssertRC(rc);
2431	}
2432	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2433	SHW_PTE_SET_RW(PteDst);
2434	else
2435	{
2436	/* Still applies to shared pages. */
2437	Assert(!PGM_PAGE_IS_ZERO(pPage));
2438	SHW_PTE_SET_RO(PteDst);
2439	}
2440	}
2441	}
2442	else
2443	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2444
2445	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2446	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2447	PGM_INVL_PG(pVCpu, GCPtrPage);
2448	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2449	}
2450
2451	# ifdef IN_RING0
2452	/* Check for stale TLB entry; only applies to the SMP guest case. */
2453	if ( pVM->cCpus > 1
2454	&& SHW_PTE_IS_RW(*pPteDst)
2455	&& SHW_PTE_IS_A(*pPteDst))
2456	{
2457	/* Stale TLB entry. */
2458	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2459	PGM_INVL_PG(pVCpu, GCPtrPage);
2460	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2461	}
2462	# endif
2463	}
2464	}
2465	else
2466	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2467	}
2468
2469	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2470	}
2471
2472	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2473
2474
2475	/**
2476	* Sync a shadow page table.
2477	*
2478	* The shadow page table is not present. This includes the case where
2479	* there is a conflict with a mapping.
2480	*
2481	* @returns VBox status code.
2482	* @param pVCpu The VMCPU handle.
2483	* @param iPD Page directory index.
2484	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2485	* Assume this is a temporary mapping.
2486	* @param GCPtrPage GC Pointer of the page that caused the fault
2487	*/
2488	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2489	{
2490	PVM pVM = pVCpu->CTX_SUFF(pVM);
2491	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2492
2493	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2494	#if 0 /* rarely useful; leave for debugging. */
2495	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2496	#endif
2497	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2498
2499	Assert(PGMIsLocked(pVM));
2500
2501	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2502	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2503	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2504	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2505	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2506
2507	int rc = VINF_SUCCESS;
2508
2509	/*
2510	* Validate input a little bit.
2511	*/
2512	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2513	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2514	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2515	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2516
2517	/* Fetch the pgm pool shadow descriptor. */
2518	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2519	Assert(pShwPde);
2520
2521	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2522	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2523	PPGMPOOLPAGE pShwPde = NULL;
2524	PX86PDPAE pPDDst;
2525	PSHWPDE pPdeDst;
2526
2527	/* Fetch the pgm pool shadow descriptor. */
2528	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2529	AssertRCSuccessReturn(rc, rc);
2530	Assert(pShwPde);
2531
2532	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2533	pPdeDst = &pPDDst->a[iPDDst];
2534
2535	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2536	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2537	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2538	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2539	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2540	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2541	AssertRCSuccessReturn(rc, rc);
2542	Assert(pPDDst);
2543	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2544	# endif
2545	SHWPDE PdeDst = *pPdeDst;
2546
2547	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2548	/* Fetch the pgm pool shadow descriptor. */
2549	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2550	Assert(pShwPde);
2551	# endif
2552
2553	# ifndef PGM_WITHOUT_MAPPINGS
2554	/*
2555	* Check for conflicts.
2556	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2557	* R3: Simply resolve the conflict.
2558	*/
2559	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2560	{
2561	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2562	# ifndef IN_RING3
2563	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2564	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2565	return VERR_ADDRESS_CONFLICT;
2566
2567	# else /* IN_RING3 */
2568	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2569	Assert(pMapping);
2570	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2571	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2572	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2573	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2574	# else
2575	AssertFailed(); /* can't happen for amd64 */
2576	# endif
2577	if (RT_FAILURE(rc))
2578	{
2579	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2580	return rc;
2581	}
2582	PdeDst = *pPdeDst;
2583	# endif /* IN_RING3 */
2584	}
2585	# endif /* !PGM_WITHOUT_MAPPINGS */
2586	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2587
2588	/*
2589	* Sync page directory entry.
2590	*/
2591	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2592	if (PdeSrc.n.u1Present)
2593	{
2594	/*
2595	* Allocate & map the page table.
2596	*/
2597	PSHWPT pPTDst;
2598	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2599	PPGMPOOLPAGE pShwPage;
2600	RTGCPHYS GCPhys;
2601	if (fPageTable)
2602	{
2603	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2604	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2605	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2606	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2607	# endif
2608	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2609	}
2610	else
2611	{
2612	PGMPOOLACCESS enmAccess;
2613	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2614	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2615	# else
2616	const bool fNoExecute = false;
2617	# endif
2618
2619	GCPhys = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
2620	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2621	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2622	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2623	# endif
2624	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2625	if (PdeSrc.n.u1User)
2626	{
2627	if (PdeSrc.n.u1Write)
2628	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2629	else
2630	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2631	}
2632	else
2633	{
2634	if (PdeSrc.n.u1Write)
2635	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2636	else
2637	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2638	}
2639	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2640	}
2641	if (rc == VINF_SUCCESS)
2642	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2643	else if (rc == VINF_PGM_CACHED_PAGE)
2644	{
2645	/*
2646	* The PT was cached, just hook it up.
2647	*/
2648	if (fPageTable)
2649	PdeDst.u = pShwPage->Core.Key
2650	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2651	else
2652	{
2653	PdeDst.u = pShwPage->Core.Key
2654	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2655	/* (see explanation and assumptions further down.) */
2656	if ( !PdeSrc.b.u1Dirty
2657	&& PdeSrc.b.u1Write)
2658	{
2659	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2660	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2661	PdeDst.b.u1Write = 0;
2662	}
2663	}
2664	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2665	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2666	return VINF_SUCCESS;
2667	}
2668	else if (rc == VERR_PGM_POOL_FLUSHED)
2669	{
2670	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2671	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2672	return VINF_PGM_SYNC_CR3;
2673	}
2674	else
2675	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2676	PdeDst.u &= X86_PDE_AVL_MASK;
2677	PdeDst.u \|= pShwPage->Core.Key;
2678
2679	/*
2680	* Page directory has been accessed (this is a fault situation, remember).
2681	*/
2682	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2683	if (fPageTable)
2684	{
2685	/*
2686	* Page table - 4KB.
2687	*
2688	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2689	*/
2690	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2691	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2692	PGSTPT pPTSrc;
2693	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2694	if (RT_SUCCESS(rc))
2695	{
2696	/*
2697	* Start by syncing the page directory entry so CSAM's TLB trick works.
2698	*/
2699	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2700	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2701	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2702	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2703
2704	/*
2705	* Directory/page user or supervisor privilege: (same goes for read/write)
2706	*
2707	* Directory Page Combined
2708	* U/S U/S U/S
2709	* 0 0 0
2710	* 0 1 0
2711	* 1 0 0
2712	* 1 1 1
2713	*
2714	* Simple AND operation. Table listed for completeness.
2715	*
2716	*/
2717	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2718	# ifdef PGM_SYNC_N_PAGES
2719	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2720	unsigned iPTDst = iPTBase;
2721	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2722	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2723	iPTDst = 0;
2724	else
2725	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2726	# else /* !PGM_SYNC_N_PAGES */
2727	unsigned iPTDst = 0;
2728	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2729	# endif /* !PGM_SYNC_N_PAGES */
2730	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2731	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2732	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2733	# else
2734	const unsigned offPTSrc = 0;
2735	# endif
2736	for (; iPTDst < iPTDstEnd; iPTDst++)
2737	{
2738	const unsigned iPTSrc = iPTDst + offPTSrc;
2739	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2740
2741	if (PteSrc.n.u1Present)
2742	{
2743	# ifndef IN_RING0
2744	/*
2745	* Assuming kernel code will be marked as supervisor - and not as user level
2746	* and executed using a conforming code selector - And marked as readonly.
2747	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2748	*/
2749	PPGMPAGE pPage;
2750	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2751	\|\| !CSAMDoesPageNeedScanning(pVM, (iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT))
2752	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2753	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2754	)
2755	# endif
2756	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2757	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2758	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2759	PteSrc.n.u1Present,
2760	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2761	PteSrc.n.u1User & PdeSrc.n.u1User,
2762	(uint64_t)PteSrc.u,
2763	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2764	(RTGCPHYS)((PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)) ));
2765	}
2766	/* else: the page table was cleared by the pool */
2767	} /* for PTEs */
2768	}
2769	}
2770	else
2771	{
2772	/*
2773	* Big page - 2/4MB.
2774	*
2775	* We'll walk the ram range list in parallel and optimize lookups.
2776	* We will only sync on shadow page table at a time.
2777	*/
2778	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2779
2780	/**
2781	* @todo It might be more efficient to sync only a part of the 4MB
2782	* page (similar to what we do for 4KB PDs).
2783	*/
2784
2785	/*
2786	* Start by syncing the page directory entry.
2787	*/
2788	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2789	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2790
2791	/*
2792	* If the page is not flagged as dirty and is writable, then make it read-only
2793	* at PD level, so we can set the dirty bit when the page is modified.
2794	*
2795	* ASSUMES that page access handlers are implemented on page table entry level.
2796	* Thus we will first catch the dirty access and set PDE.D and restart. If
2797	* there is an access handler, we'll trap again and let it work on the problem.
2798	*/
2799	/** @todo move the above stuff to a section in the PGM documentation. */
2800	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2801	if ( !PdeSrc.b.u1Dirty
2802	&& PdeSrc.b.u1Write)
2803	{
2804	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2805	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2806	PdeDst.b.u1Write = 0;
2807	}
2808	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2809	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2810
2811	/*
2812	* Fill the shadow page table.
2813	*/
2814	/* Get address and flags from the source PDE. */
2815	// Assert(GST_IS_PDE_VALID(pVCpu, PdeSrc));
2816	SHWPTE PteDstBase;
2817	SHW_PTE_SET(PteDstBase, PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT));
2818
2819	/* Loop thru the entries in the shadow PT. */
2820	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2821	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2822	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2823	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2824	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2825	unsigned iPTDst = 0;
2826	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2827	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2828	{
2829	/* Advance ram range list. */
2830	while (pRam && GCPhys > pRam->GCPhysLast)
2831	pRam = pRam->CTX_SUFF(pNext);
2832	if (pRam && GCPhys >= pRam->GCPhys)
2833	{
2834	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2835	do
2836	{
2837	/* Make shadow PTE. */
2838	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2839	SHWPTE PteDst;
2840
2841	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2842	/* Try to make the page writable if necessary. */
2843	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2844	&& ( PGM_PAGE_IS_ZERO(pPage)
2845	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2846	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2847	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2848	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2849	# endif
2850	# ifdef VBOX_WITH_PAGE_SHARING
2851	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2852	# endif
2853	&& !PGM_PAGE_IS_BALLOONED(pPage))
2854	)
2855	)
2856	{
2857	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2858	AssertRCReturn(rc, rc);
2859	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2860	break;
2861	}
2862	# endif
2863
2864	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2865	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2866	else if (PGM_PAGE_IS_BALLOONED(pPage))
2867	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2868	# ifndef IN_RING0
2869	/*
2870	* Assuming kernel code will be marked as supervisor and not as user level and executed
2871	* using a conforming code selector. Don't check for readonly, as that implies the whole
2872	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2873	*/
2874	else if ( !PdeSrc.n.u1User
2875	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2876	SHW_PTE_SET(PteDst, 0);
2877	# endif
2878	else
2879	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2880
2881	/* Only map writable pages writable. */
2882	if ( SHW_PTE_IS_P_RW(PteDst)
2883	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2884	{
2885	/* Still applies to shared pages. */
2886	Assert(!PGM_PAGE_IS_ZERO(pPage));
2887	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2888	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2889	}
2890
2891	if (SHW_PTE_IS_P(PteDst))
2892	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2893
2894	/* commit it (not atomic, new table) */
2895	pPTDst->a[iPTDst] = PteDst;
2896	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2897	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2898	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2899
2900	/* advance */
2901	GCPhys += PAGE_SIZE;
2902	iHCPage++;
2903	iPTDst++;
2904	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2905	&& GCPhys <= pRam->GCPhysLast);
2906	}
2907	else if (pRam)
2908	{
2909	Log(("Invalid pages at %RGp\n", GCPhys));
2910	do
2911	{
2912	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2913	GCPhys += PAGE_SIZE;
2914	iPTDst++;
2915	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2916	&& GCPhys < pRam->GCPhys);
2917	}
2918	else
2919	{
2920	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2921	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2922	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2923	}
2924	} /* while more PTEs */
2925	} /* 4KB / 4MB */
2926	}
2927	else
2928	AssertRelease(!PdeDst.n.u1Present);
2929
2930	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2931	if (RT_FAILURE(rc))
2932	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2933	return rc;
2934
2935	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2936	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2937	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2938	&& !defined(IN_RC)
2939
2940	/*
2941	* Validate input a little bit.
2942	*/
2943	int rc = VINF_SUCCESS;
2944	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2945	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2946	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2947
2948	/* Fetch the pgm pool shadow descriptor. */
2949	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2950	Assert(pShwPde);
2951
2952	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2953	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2954	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2955	PX86PDPAE pPDDst;
2956	PSHWPDE pPdeDst;
2957
2958	/* Fetch the pgm pool shadow descriptor. */
2959	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2960	AssertRCSuccessReturn(rc, rc);
2961	Assert(pShwPde);
2962
2963	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2964	pPdeDst = &pPDDst->a[iPDDst];
2965
2966	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2967	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2968	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2969	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2970	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2971	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2972	AssertRCSuccessReturn(rc, rc);
2973	Assert(pPDDst);
2974	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2975
2976	/* Fetch the pgm pool shadow descriptor. */
2977	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2978	Assert(pShwPde);
2979
2980	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2981	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
2982	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2983	PEPTPD pPDDst;
2984	PEPTPDPT pPdptDst;
2985
2986	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
2987	if (rc != VINF_SUCCESS)
2988	{
2989	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2990	AssertRC(rc);
2991	return rc;
2992	}
2993	Assert(pPDDst);
2994	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2995
2996	/* Fetch the pgm pool shadow descriptor. */
2997	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
2998	Assert(pShwPde);
2999	# endif
3000	SHWPDE PdeDst = *pPdeDst;
3001
3002	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3003	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3004
3005	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3006	if (BTH_IS_NP_ACTIVE(pVM))
3007	{
3008	PPGMPAGE pPage;
3009
3010	/* Check if we allocated a big page before for this 2 MB range. */
3011	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3012	if (RT_SUCCESS(rc))
3013	{
3014	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3015
3016	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3017	{
3018	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3019	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3020	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3021	}
3022	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3023	{
3024	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3025	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3026	if (RT_SUCCESS(rc))
3027	{
3028	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3029	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3030	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3031	}
3032	}
3033	else if (PGMIsUsingLargePages(pVM))
3034	{
3035	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3036	if (RT_SUCCESS(rc))
3037	{
3038	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3039	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3040	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3041	}
3042	else
3043	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3044	}
3045
3046	if (HCPhys != NIL_RTHCPHYS)
3047	{
3048	PdeDst.u &= X86_PDE_AVL_MASK;
3049	PdeDst.u \|= HCPhys;
3050	PdeDst.n.u1Present = 1;
3051	PdeDst.n.u1Write = 1;
3052	PdeDst.b.u1Size = 1;
3053	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3054	PdeDst.n.u1Execute = 1;
3055	PdeDst.b.u1IgnorePAT = 1;
3056	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3057	# else
3058	PdeDst.n.u1User = 1;
3059	# endif
3060	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3061
3062	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3063	/* Add a reference to the first page only. */
3064	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3065
3066	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3067	return VINF_SUCCESS;
3068	}
3069	}
3070	}
3071	# endif /* HC_ARCH_BITS == 64 */
3072
3073	GSTPDE PdeSrc;
3074	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3075	PdeSrc.n.u1Present = 1;
3076	PdeSrc.n.u1Write = 1;
3077	PdeSrc.n.u1Accessed = 1;
3078	PdeSrc.n.u1User = 1;
3079
3080	/*
3081	* Allocate & map the page table.
3082	*/
3083	PSHWPT pPTDst;
3084	PPGMPOOLPAGE pShwPage;
3085	RTGCPHYS GCPhys;
3086
3087	/* Virtual address = physical address */
3088	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3089	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3090
3091	if ( rc == VINF_SUCCESS
3092	\|\| rc == VINF_PGM_CACHED_PAGE)
3093	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3094	else
3095	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3096
3097	PdeDst.u &= X86_PDE_AVL_MASK;
3098	PdeDst.u \|= pShwPage->Core.Key;
3099	PdeDst.n.u1Present = 1;
3100	PdeDst.n.u1Write = 1;
3101	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3102	PdeDst.n.u1Execute = 1;
3103	# else
3104	PdeDst.n.u1User = 1;
3105	PdeDst.n.u1Accessed = 1;
3106	# endif
3107	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3108
3109	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3110	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3111	return rc;
3112
3113	#else
3114	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3115	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3116	return VERR_INTERNAL_ERROR;
3117	#endif
3118	}
3119
3120
3121
3122	/**
3123	* Prefetch a page/set of pages.
3124	*
3125	* Typically used to sync commonly used pages before entering raw mode
3126	* after a CR3 reload.
3127	*
3128	* @returns VBox status code.
3129	* @param pVCpu The VMCPU handle.
3130	* @param GCPtrPage Page to invalidate.
3131	*/
3132	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3133	{
3134	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3135	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3136	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3137	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3138	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3139	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3140	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3141
3142	/*
3143	* Check that all Guest levels thru the PDE are present, getting the
3144	* PD and PDE in the processes.
3145	*/
3146	int rc = VINF_SUCCESS;
3147	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3148	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3149	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3150	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3151	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3152	unsigned iPDSrc;
3153	X86PDPE PdpeSrc;
3154	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3155	if (!pPDSrc)
3156	return VINF_SUCCESS; /* not present */
3157	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3158	unsigned iPDSrc;
3159	PX86PML4E pPml4eSrc;
3160	X86PDPE PdpeSrc;
3161	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3162	if (!pPDSrc)
3163	return VINF_SUCCESS; /* not present */
3164	# endif
3165	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3166	# else
3167	PGSTPD pPDSrc = NULL;
3168	const unsigned iPDSrc = 0;
3169	GSTPDE PdeSrc;
3170
3171	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3172	PdeSrc.n.u1Present = 1;
3173	PdeSrc.n.u1Write = 1;
3174	PdeSrc.n.u1Accessed = 1;
3175	PdeSrc.n.u1User = 1;
3176	# endif
3177
3178	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3179	{
3180	PVM pVM = pVCpu->CTX_SUFF(pVM);
3181	pgmLock(pVM);
3182
3183	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3184	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3185	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3186	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3187	PX86PDPAE pPDDst;
3188	X86PDEPAE PdeDst;
3189	# if PGM_GST_TYPE != PGM_TYPE_PAE
3190	X86PDPE PdpeSrc;
3191
3192	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3193	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3194	# endif
3195	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3196	if (rc != VINF_SUCCESS)
3197	{
3198	pgmUnlock(pVM);
3199	AssertRC(rc);
3200	return rc;
3201	}
3202	Assert(pPDDst);
3203	PdeDst = pPDDst->a[iPDDst];
3204
3205	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3206	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3207	PX86PDPAE pPDDst;
3208	X86PDEPAE PdeDst;
3209
3210	# if PGM_GST_TYPE == PGM_TYPE_PROT
3211	/* AMD-V nested paging */
3212	X86PML4E Pml4eSrc;
3213	X86PDPE PdpeSrc;
3214	PX86PML4E pPml4eSrc = &Pml4eSrc;
3215
3216	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3217	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3218	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3219	# endif
3220
3221	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3222	if (rc != VINF_SUCCESS)
3223	{
3224	pgmUnlock(pVM);
3225	AssertRC(rc);
3226	return rc;
3227	}
3228	Assert(pPDDst);
3229	PdeDst = pPDDst->a[iPDDst];
3230	# endif
3231	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3232	{
3233	if (!PdeDst.n.u1Present)
3234	{
3235	/** @todo r=bird: This guy will set the A bit on the PDE,
3236	* probably harmless. */
3237	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3238	}
3239	else
3240	{
3241	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3242	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3243	* makes no sense to prefetch more than one page.
3244	*/
3245	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3246	if (RT_SUCCESS(rc))
3247	rc = VINF_SUCCESS;
3248	}
3249	}
3250	pgmUnlock(pVM);
3251	}
3252	return rc;
3253
3254	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3255	return VINF_SUCCESS; /* ignore */
3256	#else
3257	AssertCompile(0);
3258	#endif
3259	}
3260
3261
3262
3263
3264	/**
3265	* Syncs a page during a PGMVerifyAccess() call.
3266	*
3267	* @returns VBox status code (informational included).
3268	* @param pVCpu The VMCPU handle.
3269	* @param GCPtrPage The address of the page to sync.
3270	* @param fPage The effective guest page flags.
3271	* @param uErr The trap error code.
3272	* @remarks This will normally never be called on invalid guest page
3273	* translation entries.
3274	*/
3275	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3276	{
3277	PVM pVM = pVCpu->CTX_SUFF(pVM);
3278
3279	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3280
3281	Assert(!pVM->pgm.s.fNestedPaging);
3282	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3283	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3284	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3285	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3286	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3287	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3288	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3289
3290	# ifndef IN_RING0
3291	if (!(fPage & X86_PTE_US))
3292	{
3293	/*
3294	* Mark this page as safe.
3295	*/
3296	/** @todo not correct for pages that contain both code and data!! */
3297	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3298	CSAMMarkPage(pVM, GCPtrPage, true);
3299	}
3300	# endif
3301
3302	/*
3303	* Get guest PD and index.
3304	*/
3305	/** @todo Performance: We've done all this a jiffy ago in the
3306	* PGMGstGetPage call. */
3307	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3308	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3309	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3310	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3311
3312	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3313	unsigned iPDSrc = 0;
3314	X86PDPE PdpeSrc;
3315	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3316	if (RT_UNLIKELY(!pPDSrc))
3317	{
3318	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3319	return VINF_EM_RAW_GUEST_TRAP;
3320	}
3321
3322	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3323	unsigned iPDSrc = 0; /* shut up gcc */
3324	PX86PML4E pPml4eSrc = NULL; /* ditto */
3325	X86PDPE PdpeSrc;
3326	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3327	if (RT_UNLIKELY(!pPDSrc))
3328	{
3329	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3330	return VINF_EM_RAW_GUEST_TRAP;
3331	}
3332	# endif
3333
3334	# else /* !PGM_WITH_PAGING */
3335	PGSTPD pPDSrc = NULL;
3336	const unsigned iPDSrc = 0;
3337	# endif /* !PGM_WITH_PAGING */
3338	int rc = VINF_SUCCESS;
3339
3340	pgmLock(pVM);
3341
3342	/*
3343	* First check if the shadow pd is present.
3344	*/
3345	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3346	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3347
3348	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3349	PX86PDEPAE pPdeDst;
3350	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3351	PX86PDPAE pPDDst;
3352	# if PGM_GST_TYPE != PGM_TYPE_PAE
3353	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3354	X86PDPE PdpeSrc;
3355	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3356	# endif
3357	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3358	if (rc != VINF_SUCCESS)
3359	{
3360	pgmUnlock(pVM);
3361	AssertRC(rc);
3362	return rc;
3363	}
3364	Assert(pPDDst);
3365	pPdeDst = &pPDDst->a[iPDDst];
3366
3367	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3368	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3369	PX86PDPAE pPDDst;
3370	PX86PDEPAE pPdeDst;
3371
3372	# if PGM_GST_TYPE == PGM_TYPE_PROT
3373	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3374	X86PML4E Pml4eSrc;
3375	X86PDPE PdpeSrc;
3376	PX86PML4E pPml4eSrc = &Pml4eSrc;
3377	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3378	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3379	# endif
3380
3381	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3382	if (rc != VINF_SUCCESS)
3383	{
3384	pgmUnlock(pVM);
3385	AssertRC(rc);
3386	return rc;
3387	}
3388	Assert(pPDDst);
3389	pPdeDst = &pPDDst->a[iPDDst];
3390	# endif
3391
3392	if (!pPdeDst->n.u1Present)
3393	{
3394	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3395	if (rc != VINF_SUCCESS)
3396	{
3397	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3398	pgmUnlock(pVM);
3399	AssertRC(rc);
3400	return rc;
3401	}
3402	}
3403
3404	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3405	/* Check for dirty bit fault */
3406	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3407	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3408	Log(("PGMVerifyAccess: success (dirty)\n"));
3409	else
3410	# endif
3411	{
3412	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3413	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3414	# else
3415	GSTPDE PdeSrc;
3416	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3417	PdeSrc.n.u1Present = 1;
3418	PdeSrc.n.u1Write = 1;
3419	PdeSrc.n.u1Accessed = 1;
3420	PdeSrc.n.u1User = 1;
3421	# endif
3422
3423	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3424	if (uErr & X86_TRAP_PF_US)
3425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3426	else /* supervisor */
3427	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3428
3429	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3430	if (RT_SUCCESS(rc))
3431	{
3432	/* Page was successfully synced */
3433	Log2(("PGMVerifyAccess: success (sync)\n"));
3434	rc = VINF_SUCCESS;
3435	}
3436	else
3437	{
3438	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3439	rc = VINF_EM_RAW_GUEST_TRAP;
3440	}
3441	}
3442	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3443	pgmUnlock(pVM);
3444	return rc;
3445
3446	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3447
3448	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3449	return VERR_INTERNAL_ERROR;
3450	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3451	}
3452
3453
3454	/**
3455	* Syncs the paging hierarchy starting at CR3.
3456	*
3457	* @returns VBox status code, no specials.
3458	* @param pVCpu The VMCPU handle.
3459	* @param cr0 Guest context CR0 register
3460	* @param cr3 Guest context CR3 register
3461	* @param cr4 Guest context CR4 register
3462	* @param fGlobal Including global page directories or not
3463	*/
3464	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3465	{
3466	PVM pVM = pVCpu->CTX_SUFF(pVM);
3467
3468	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3469
3470	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3471
3472	pgmLock(pVM);
3473
3474	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3475	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3476	if (pPool->cDirtyPages)
3477	pgmPoolResetDirtyPages(pVM);
3478	# endif
3479
3480	/*
3481	* Update page access handlers.
3482	* The virtual are always flushed, while the physical are only on demand.
3483	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3484	* have to look into that later because it will have a bad influence on the performance.
3485	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3486	* bird: Yes, but that won't work for aliases.
3487	*/
3488	/** @todo this MUST go away. See #1557. */
3489	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3490	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3491	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3492	pgmUnlock(pVM);
3493	#endif /* !NESTED && !EPT */
3494
3495	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3496	/*
3497	* Nested / EPT - almost no work.
3498	*/
3499	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3500	return VINF_SUCCESS;
3501
3502	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3503	/*
3504	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3505	* out the shadow parts when the guest modifies its tables.
3506	*/
3507	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3508	return VINF_SUCCESS;
3509
3510	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3511
3512	# ifndef PGM_WITHOUT_MAPPINGS
3513	/*
3514	* Check for and resolve conflicts with our guest mappings if they
3515	* are enabled and not fixed.
3516	*/
3517	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3518	{
3519	int rc = pgmMapResolveConflicts(pVM);
3520	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3521	if (rc == VINF_PGM_SYNC_CR3)
3522	{
3523	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3524	return VINF_PGM_SYNC_CR3;
3525	}
3526	}
3527	# else
3528	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3529	# endif
3530	return VINF_SUCCESS;
3531	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3532	}
3533
3534
3535
3536
3537	#ifdef VBOX_STRICT
3538	#ifdef IN_RC
3539	# undef AssertMsgFailed
3540	# define AssertMsgFailed Log
3541	#endif
3542	#ifdef IN_RING3
3543	# include <VBox/dbgf.h>
3544
3545	/**
3546	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3547	*
3548	* @returns VBox status code (VINF_SUCCESS).
3549	* @param cr3 The root of the hierarchy.
3550	* @param crr The cr4, only PAE and PSE is currently used.
3551	* @param fLongMode Set if long mode, false if not long mode.
3552	* @param cMaxDepth Number of levels to dump.
3553	* @param pHlp Pointer to the output functions.
3554	*/
3555	RT_C_DECLS_BEGIN
3556	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3557	RT_C_DECLS_END
3558
3559	#endif
3560
3561	/**
3562	* Checks that the shadow page table is in sync with the guest one.
3563	*
3564	* @returns The number of errors.
3565	* @param pVM The virtual machine.
3566	* @param pVCpu The VMCPU handle.
3567	* @param cr3 Guest context CR3 register
3568	* @param cr4 Guest context CR4 register
3569	* @param GCPtr Where to start. Defaults to 0.
3570	* @param cb How much to check. Defaults to everything.
3571	*/
3572	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3573	{
3574	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3575	return 0;
3576	#else
3577	unsigned cErrors = 0;
3578	PVM pVM = pVCpu->CTX_SUFF(pVM);
3579	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3580
3581	#if PGM_GST_TYPE == PGM_TYPE_PAE
3582	/** @todo currently broken; crashes below somewhere */
3583	AssertFailed();
3584	#endif
3585
3586	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3587	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3588	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3589
3590	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3591	PPGMCPU pPGM = &pVCpu->pgm.s;
3592	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3593	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3594	# ifndef IN_RING0
3595	RTHCPHYS HCPhys; /* general usage. */
3596	# endif
3597	int rc;
3598
3599	/*
3600	* Check that the Guest CR3 and all its mappings are correct.
3601	*/
3602	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3603	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3604	false);
3605	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3606	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3607	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3608	# else
3609	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3610	# endif
3611	AssertRCReturn(rc, 1);
3612	HCPhys = NIL_RTHCPHYS;
3613	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3614	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3615	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3616	pgmGstGet32bitPDPtr(pVCpu);
3617	RTGCPHYS GCPhys;
3618	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3619	AssertRCReturn(rc, 1);
3620	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3621	# endif
3622	# endif /* !IN_RING0 */
3623
3624	/*
3625	* Get and check the Shadow CR3.
3626	*/
3627	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3628	unsigned cPDEs = X86_PG_ENTRIES;
3629	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3630	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3631	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3632	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3633	# else
3634	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3635	# endif
3636	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3637	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3638	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3639	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3640	# endif
3641	if (cb != ~(RTGCPTR)0)
3642	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3643
3644	/** @todo call the other two PGMAssert() functions. /
3645
3646	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3647	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3648
3649	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3650	{
3651	PPGMPOOLPAGE pShwPdpt = NULL;
3652	PX86PML4E pPml4eSrc;
3653	PX86PML4E pPml4eDst;
3654	RTGCPHYS GCPhysPdptSrc;
3655
3656	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3657	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3658
3659	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3660	if (!pPml4eDst->n.u1Present)
3661	{
3662	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3663	continue;
3664	}
3665
3666	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3667	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3668
3669	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3670	{
3671	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3672	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3673	cErrors++;
3674	continue;
3675	}
3676
3677	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3678	{
3679	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3680	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3681	cErrors++;
3682	continue;
3683	}
3684
3685	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3686	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3687	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3688	{
3689	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3690	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3691	cErrors++;
3692	continue;
3693	}
3694	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3695	{
3696	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3697
3698	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3699	/*
3700	* Check the PDPTEs too.
3701	*/
3702	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3703
3704	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3705	{
3706	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3707	PPGMPOOLPAGE pShwPde = NULL;
3708	PX86PDPE pPdpeDst;
3709	RTGCPHYS GCPhysPdeSrc;
3710	# if PGM_GST_TYPE == PGM_TYPE_PAE
3711	X86PDPE PdpeSrc;
3712	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3713	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3714	# else
3715	PX86PML4E pPml4eSrcIgn;
3716	X86PDPE PdpeSrc;
3717	PX86PDPT pPdptDst;
3718	PX86PDPAE pPDDst;
3719	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3720
3721	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3722	if (rc != VINF_SUCCESS)
3723	{
3724	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3725	GCPtr += 512 * _2M;
3726	continue; /* next PDPTE */
3727	}
3728	Assert(pPDDst);
3729	# endif
3730	Assert(iPDSrc == 0);
3731
3732	pPdpeDst = &pPdptDst->a[iPdpt];
3733
3734	if (!pPdpeDst->n.u1Present)
3735	{
3736	GCPtr += 512 * _2M;
3737	continue; /* next PDPTE */
3738	}
3739
3740	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3741	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3742
3743	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3744	{
3745	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3746	GCPtr += 512 * _2M;
3747	cErrors++;
3748	continue;
3749	}
3750
3751	if (GCPhysPdeSrc != pShwPde->GCPhys)
3752	{
3753	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3754	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3755	# else
3756	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3757	# endif
3758	GCPtr += 512 * _2M;
3759	cErrors++;
3760	continue;
3761	}
3762
3763	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3764	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3765	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3766	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3767	{
3768	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3769	GCPtr += 512 * _2M;
3770	cErrors++;
3771	continue;
3772	}
3773	# endif
3774
3775	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3776	{
3777	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3778	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3779	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3780	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3781	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3782	# endif
3783	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3784	/*
3785	* Iterate the shadow page directory.
3786	*/
3787	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3788	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3789
3790	for (;
3791	iPDDst < cPDEs;
3792	iPDDst++, GCPtr += cIncrement)
3793	{
3794	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3795	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3796	# else
3797	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3798	# endif
3799	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3800	{
3801	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3802	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3803	{
3804	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3805	cErrors++;
3806	continue;
3807	}
3808	}
3809	else if ( (PdeDst.u & X86_PDE_P)
3810	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3811	)
3812	{
3813	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3814	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3815	if (!pPoolPage)
3816	{
3817	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3818	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3819	cErrors++;
3820	continue;
3821	}
3822	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3823
3824	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3825	{
3826	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3827	GCPtr, (uint64_t)PdeDst.u));
3828	cErrors++;
3829	}
3830
3831	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3832	{
3833	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3834	GCPtr, (uint64_t)PdeDst.u));
3835	cErrors++;
3836	}
3837
3838	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3839	if (!PdeSrc.n.u1Present)
3840	{
3841	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3842	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3843	cErrors++;
3844	continue;
3845	}
3846
3847	if ( !PdeSrc.b.u1Size
3848	\|\| !fBigPagesSupported)
3849	{
3850	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3851	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3852	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3853	# endif
3854	}
3855	else
3856	{
3857	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3858	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3859	{
3860	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3861	GCPtr, (uint64_t)PdeSrc.u));
3862	cErrors++;
3863	continue;
3864	}
3865	# endif
3866	GCPhysGst = GST_GET_PDE_BIG_PG_GCPHYS(pVM, PdeSrc);
3867	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3868	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3869	# endif
3870	}
3871
3872	if ( pPoolPage->enmKind
3873	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3874	{
3875	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3876	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3877	cErrors++;
3878	}
3879
3880	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3881	if (!pPhysPage)
3882	{
3883	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3884	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3885	cErrors++;
3886	continue;
3887	}
3888
3889	if (GCPhysGst != pPoolPage->GCPhys)
3890	{
3891	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3892	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3893	cErrors++;
3894	continue;
3895	}
3896
3897	if ( !PdeSrc.b.u1Size
3898	\|\| !fBigPagesSupported)
3899	{
3900	/*
3901	* Page Table.
3902	*/
3903	const GSTPT *pPTSrc;
3904	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3905	if (RT_FAILURE(rc))
3906	{
3907	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3908	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3909	cErrors++;
3910	continue;
3911	}
3912	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3913	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3914	{
3915	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3916	// (This problem will go away when/if we shadow multiple CR3s.)
3917	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3918	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3919	cErrors++;
3920	continue;
3921	}
3922	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3923	{
3924	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3925	GCPtr, (uint64_t)PdeDst.u));
3926	cErrors++;
3927	continue;
3928	}
3929
3930	/* iterate the page table. */
3931	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3932	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3933	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3934	# else
3935	const unsigned offPTSrc = 0;
3936	# endif
3937	for (unsigned iPT = 0, off = 0;
3938	iPT < RT_ELEMENTS(pPTDst->a);
3939	iPT++, off += PAGE_SIZE)
3940	{
3941	const SHWPTE PteDst = pPTDst->a[iPT];
3942
3943	/* skip not-present and dirty tracked entries. */
3944	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3945	continue;
3946	Assert(SHW_PTE_IS_P(PteDst));
3947
3948	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3949	if (!PteSrc.n.u1Present)
3950	{
3951	# ifdef IN_RING3
3952	PGMAssertHandlerAndFlagsInSync(pVM);
3953	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3954	# endif
3955	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3956	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3957	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3958	cErrors++;
3959	continue;
3960	}
3961
3962	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3963	# if 1 /** @todo sync accessed bit properly... */
3964	fIgnoreFlags \|= X86_PTE_A;
3965	# endif
3966
3967	/* match the physical addresses */
3968	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3969	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3970
3971	# ifdef IN_RING3
3972	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3973	if (RT_FAILURE(rc))
3974	{
3975	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3976	{
3977	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3978	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3979	cErrors++;
3980	continue;
3981	}
3982	}
3983	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3984	{
3985	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3986	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3987	cErrors++;
3988	continue;
3989	}
3990	# endif
3991
3992	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3993	if (!pPhysPage)
3994	{
3995	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3996	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3997	{
3998	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3999	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4000	cErrors++;
4001	continue;
4002	}
4003	# endif
4004	if (SHW_PTE_IS_RW(PteDst))
4005	{
4006	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4007	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4008	cErrors++;
4009	}
4010	fIgnoreFlags \|= X86_PTE_RW;
4011	}
4012	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4013	{
4014	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4015	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4016	cErrors++;
4017	continue;
4018	}
4019
4020	/* flags */
4021	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4022	{
4023	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4024	{
4025	if (SHW_PTE_IS_RW(PteDst))
4026	{
4027	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4029	cErrors++;
4030	continue;
4031	}
4032	fIgnoreFlags \|= X86_PTE_RW;
4033	}
4034	else
4035	{
4036	if ( SHW_PTE_IS_P(PteDst)
4037	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4038	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4039	# endif
4040	)
4041	{
4042	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4043	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4044	cErrors++;
4045	continue;
4046	}
4047	fIgnoreFlags \|= X86_PTE_P;
4048	}
4049	}
4050	else
4051	{
4052	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4053	{
4054	if (SHW_PTE_IS_RW(PteDst))
4055	{
4056	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4057	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4058	cErrors++;
4059	continue;
4060	}
4061	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4062	{
4063	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4064	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4065	cErrors++;
4066	continue;
4067	}
4068	if (SHW_PTE_IS_D(PteDst))
4069	{
4070	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4071	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4072	cErrors++;
4073	}
4074	# if 0 /** @todo sync access bit properly... */
4075	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4076	{
4077	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4078	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4079	cErrors++;
4080	}
4081	fIgnoreFlags \|= X86_PTE_RW;
4082	# else
4083	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4084	# endif
4085	}
4086	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4087	{
4088	/* access bit emulation (not implemented). */
4089	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4090	{
4091	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4092	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4093	cErrors++;
4094	continue;
4095	}
4096	if (!SHW_PTE_IS_A(PteDst))
4097	{
4098	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4100	cErrors++;
4101	}
4102	fIgnoreFlags \|= X86_PTE_P;
4103	}
4104	# ifdef DEBUG_sandervl
4105	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4106	# endif
4107	}
4108
4109	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4110	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4111	)
4112	{
4113	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4114	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4115	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4116	cErrors++;
4117	continue;
4118	}
4119	} /* foreach PTE */
4120	}
4121	else
4122	{
4123	/*
4124	* Big Page.
4125	*/
4126	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4127	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4128	{
4129	if (PdeDst.n.u1Write)
4130	{
4131	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4132	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4133	cErrors++;
4134	continue;
4135	}
4136	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4137	{
4138	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4139	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4140	cErrors++;
4141	continue;
4142	}
4143	# if 0 /** @todo sync access bit properly... */
4144	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4145	{
4146	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4147	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4148	cErrors++;
4149	}
4150	fIgnoreFlags \|= X86_PTE_RW;
4151	# else
4152	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4153	# endif
4154	}
4155	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4156	{
4157	/* access bit emulation (not implemented). */
4158	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4159	{
4160	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4161	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4162	cErrors++;
4163	continue;
4164	}
4165	if (!PdeDst.n.u1Accessed)
4166	{
4167	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4168	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4169	cErrors++;
4170	}
4171	fIgnoreFlags \|= X86_PTE_P;
4172	}
4173
4174	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4175	{
4176	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4177	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4178	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4179	cErrors++;
4180	}
4181
4182	/* iterate the page table. */
4183	for (unsigned iPT = 0, off = 0;
4184	iPT < RT_ELEMENTS(pPTDst->a);
4185	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4186	{
4187	const SHWPTE PteDst = pPTDst->a[iPT];
4188
4189	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4190	{
4191	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4192	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4193	cErrors++;
4194	}
4195
4196	/* skip not-present entries. */
4197	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4198	continue;
4199
4200	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4201
4202	/* match the physical addresses */
4203	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4204
4205	# ifdef IN_RING3
4206	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4207	if (RT_FAILURE(rc))
4208	{
4209	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4210	{
4211	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4212	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4213	cErrors++;
4214	}
4215	}
4216	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4217	{
4218	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4219	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4220	cErrors++;
4221	continue;
4222	}
4223	# endif
4224	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4225	if (!pPhysPage)
4226	{
4227	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4228	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4229	{
4230	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4232	cErrors++;
4233	continue;
4234	}
4235	# endif
4236	if (SHW_PTE_IS_RW(PteDst))
4237	{
4238	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4239	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4240	cErrors++;
4241	}
4242	fIgnoreFlags \|= X86_PTE_RW;
4243	}
4244	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4245	{
4246	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4247	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4248	cErrors++;
4249	continue;
4250	}
4251
4252	/* flags */
4253	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4254	{
4255	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4256	{
4257	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4258	{
4259	if (SHW_PTE_IS_RW(PteDst))
4260	{
4261	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4262	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4263	cErrors++;
4264	continue;
4265	}
4266	fIgnoreFlags \|= X86_PTE_RW;
4267	}
4268	}
4269	else
4270	{
4271	if ( SHW_PTE_IS_P(PteDst)
4272	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4273	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4274	# endif
4275	)
4276	{
4277	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4278	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4279	cErrors++;
4280	continue;
4281	}
4282	fIgnoreFlags \|= X86_PTE_P;
4283	}
4284	}
4285
4286	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4287	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4288	)
4289	{
4290	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4291	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4292	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4293	cErrors++;
4294	continue;
4295	}
4296	} /* for each PTE */
4297	}
4298	}
4299	/* not present */
4300
4301	} /* for each PDE */
4302
4303	} /* for each PDPTE */
4304
4305	} /* for each PML4E */
4306
4307	# ifdef DEBUG
4308	if (cErrors)
4309	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4310	# endif
4311
4312	#endif /* GST == 32BIT, PAE or AMD64 */
4313	return cErrors;
4314
4315	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4316	}
4317	#endif /* VBOX_STRICT */
4318
4319
4320	/**
4321	* Sets up the CR3 for shadow paging
4322	*
4323	* @returns Strict VBox status code.
4324	* @retval VINF_SUCCESS.
4325	*
4326	* @param pVCpu The VMCPU handle.
4327	* @param GCPhysCR3 The physical address in the CR3 register.
4328	*/
4329	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4330	{
4331	PVM pVM = pVCpu->CTX_SUFF(pVM);
4332
4333	/* Update guest paging info. */
4334	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4335	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4336	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4337
4338	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4339
4340	/*
4341	* Map the page CR3 points at.
4342	*/
4343	RTHCPTR HCPtrGuestCR3;
4344	RTHCPHYS HCPhysGuestCR3;
4345	pgmLock(pVM);
4346	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4347	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4348	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4349	/** @todo this needs some reworking wrt. locking? */
4350	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4351	HCPtrGuestCR3 = NIL_RTHCPTR;
4352	int rc = VINF_SUCCESS;
4353	# else
4354	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4355	# endif
4356	pgmUnlock(pVM);
4357	if (RT_SUCCESS(rc))
4358	{
4359	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4360	if (RT_SUCCESS(rc))
4361	{
4362	# ifdef IN_RC
4363	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4364	# endif
4365	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4366	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4367	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4368	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4369	# endif
4370	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4371
4372	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4373	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4374	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4375	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4376	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4377	# endif
4378	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4379	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4380
4381	/*
4382	* Map the 4 PDs too.
4383	*/
4384	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4385	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4386	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4387	{
4388	if (pGuestPDPT->a[i].n.u1Present)
4389	{
4390	RTHCPTR HCPtr;
4391	RTHCPHYS HCPhys;
4392	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4393	pgmLock(pVM);
4394	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4395	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4396	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4397	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4398	HCPtr = NIL_RTHCPTR;
4399	int rc2 = VINF_SUCCESS;
4400	# else
4401	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4402	# endif
4403	pgmUnlock(pVM);
4404	if (RT_SUCCESS(rc2))
4405	{
4406	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4407	AssertRCReturn(rc, rc);
4408
4409	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4410	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4411	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4412	# endif
4413	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4414	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4415	# ifdef IN_RC
4416	PGM_INVL_PG(pVCpu, GCPtr);
4417	# endif
4418	continue;
4419	}
4420	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4421	}
4422
4423	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4424	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4425	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4426	# endif
4427	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4428	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4429	# ifdef IN_RC
4430	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4431	# endif
4432	}
4433
4434	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4435	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4436	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4437	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4438	# endif
4439	# endif
4440	}
4441	else
4442	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4443	}
4444	else
4445	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4446
4447	#else /* prot/real stub */
4448	int rc = VINF_SUCCESS;
4449	#endif
4450
4451	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4452	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4453	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4454	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4455	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4456	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4457
4458	Assert(!pVM->pgm.s.fNestedPaging);
4459
4460	/*
4461	* Update the shadow root page as well since that's not fixed.
4462	*/
4463	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4464	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4465	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4466	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4467	PPGMPOOLPAGE pNewShwPageCR3;
4468
4469	pgmLock(pVM);
4470
4471	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4472	if (pPool->cDirtyPages)
4473	pgmPoolResetDirtyPages(pVM);
4474	# endif
4475
4476	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4477	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4478	AssertFatalRC(rc);
4479	rc = VINF_SUCCESS;
4480
4481	# ifdef IN_RC
4482	/*
4483	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4484	* state will be inconsistent! Flush important things now while
4485	* we still can and then make sure there are no ring-3 calls.
4486	*/
4487	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4488	VMMRZCallRing3Disable(pVCpu);
4489	# endif
4490
4491	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4492	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4493	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4494	# ifdef IN_RING0
4495	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4496	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4497	# elif defined(IN_RC)
4498	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4499	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4500	# else
4501	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4502	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4503	# endif
4504
4505	# ifndef PGM_WITHOUT_MAPPINGS
4506	/*
4507	* Apply all hypervisor mappings to the new CR3.
4508	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4509	* make sure we check for conflicts in the new CR3 root.
4510	*/
4511	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4512	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4513	# endif
4514	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4515	AssertRCReturn(rc, rc);
4516	# endif
4517
4518	/* Set the current hypervisor CR3. */
4519	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4520	SELMShadowCR3Changed(pVM, pVCpu);
4521
4522	# ifdef IN_RC
4523	/* NOTE: The state is consistent again. */
4524	VMMRZCallRing3Enable(pVCpu);
4525	# endif
4526
4527	/* Clean up the old CR3 root. */
4528	if ( pOldShwPageCR3
4529	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4530	{
4531	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4532	# ifndef PGM_WITHOUT_MAPPINGS
4533	/* Remove the hypervisor mappings from the shadow page table. */
4534	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4535	# endif
4536	/* Mark the page as unlocked; allow flushing again. */
4537	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4538
4539	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4540	}
4541	pgmUnlock(pVM);
4542	# endif
4543
4544	return rc;
4545	}
4546
4547	/**
4548	* Unmaps the shadow CR3.
4549	*
4550	* @returns VBox status, no specials.
4551	* @param pVCpu The VMCPU handle.
4552	*/
4553	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4554	{
4555	LogFlow(("UnmapCR3\n"));
4556
4557	int rc = VINF_SUCCESS;
4558	PVM pVM = pVCpu->CTX_SUFF(pVM);
4559
4560	/*
4561	* Update guest paging info.
4562	*/
4563	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4564	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4565	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4566	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4567	# endif
4568	pVCpu->pgm.s.pGst32BitPdRC = 0;
4569
4570	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4571	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4572	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4573	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4574	# endif
4575	pVCpu->pgm.s.pGstPaePdptRC = 0;
4576	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4577	{
4578	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4579	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4580	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4581	# endif
4582	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4583	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4584	}
4585
4586	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4587	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4588	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4589	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4590	# endif
4591
4592	#else /* prot/real mode stub */
4593	/* nothing to do */
4594	#endif
4595
4596	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4597	/*
4598	* Update shadow paging info.
4599	*/
4600	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4601	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4602	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4603
4604	# if PGM_GST_TYPE != PGM_TYPE_REAL
4605	Assert(!pVM->pgm.s.fNestedPaging);
4606	# endif
4607
4608	pgmLock(pVM);
4609
4610	# ifndef PGM_WITHOUT_MAPPINGS
4611	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4612	/* Remove the hypervisor mappings from the shadow page table. */
4613	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4614	# endif
4615
4616	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4617	{
4618	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4619
4620	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4621
4622	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4623	if (pPool->cDirtyPages)
4624	pgmPoolResetDirtyPages(pVM);
4625	# endif
4626
4627	/* Mark the page as unlocked; allow flushing again. */
4628	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4629
4630	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4631	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4632	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4633	pVCpu->pgm.s.pShwPageCR3RC = 0;
4634	pVCpu->pgm.s.iShwUser = 0;
4635	pVCpu->pgm.s.iShwUserTable = 0;
4636	}
4637	pgmUnlock(pVM);
4638	# endif
4639	#endif /* !IN_RC*/
4640
4641	return rc;
4642	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 31832

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