PGMAllBth.h@ 31849

Last change on this file since 31849 was 31849, checked in by vboxsync, 15 years ago
PGM: Don't shadow PDE bits 62/3:52 (NXE=1/0), only shadow the bits we need to (exception G, A and D).
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1	/* $Id: PGMAllBth.h 31849 2010-08-22 16:15:03Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	}
561	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
562
563	/*
564	* Fetch the guest PDE, PDPE and PML4E.
565	*/
566	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
567	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
568	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
569
570	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
571	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
572	PX86PDPAE pPDDst;
573	# if PGM_GST_TYPE == PGM_TYPE_PAE
574	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
575	# else
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
577	# endif
578	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
579
580	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
581	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
582	PX86PDPAE pPDDst;
583	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
584	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
585	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
586	# else
587	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
588	# endif
589	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
590
591	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
592	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
593	PEPTPD pPDDst;
594	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
596	# endif
597	Assert(pPDDst);
598
599	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
600	/*
601	* Dirty page handling.
602	*
603	* If we successfully correct the write protection fault due to dirty bit
604	* tracking, then return immediately.
605	*/
606	if (uErr & X86_TRAP_PF_RW) /* write fault? */
607	{
608	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
609	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
610	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
612	{
613	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
614	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
615	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
616	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
617	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
618	return VINF_SUCCESS;
619	}
620	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
621	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
622	}
623
624	# if 0 /* rarely useful; leave for debugging. */
625	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
626	# endif
627	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
628
629	/*
630	* A common case is the not-present error caused by lazy page table syncing.
631	*
632	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
633	* here so we can safely assume that the shadow PT is present when calling
634	* SyncPage later.
635	*
636	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
637	* of mapping conflict and defer to SyncCR3 in R3.
638	* (Again, we do NOT support access handlers for non-present guest pages.)
639	*
640	*/
641	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
642	Assert(GstWalk.Pde.n.u1Present);
643	# endif
644	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
645	&& !pPDDst->a[iPDDst].n.u1Present)
646	{
647	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
648	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
649	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
650	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
651	# else
652	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
653	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
654	# endif
655	if (RT_SUCCESS(rc))
656	return rc;
657	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
658	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
659	return VINF_PGM_SYNC_CR3;
660	}
661
662	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
663	/*
664	* Check if this address is within any of our mappings.
665	*
666	* This is very fast and it's gonna save us a bit of effort below and prevent
667	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
668	* (BTW, it's impossible to have physical access handlers in a mapping.)
669	*/
670	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
671	{
672	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
673	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
674	{
675	if (pvFault < pMapping->GCPtr)
676	break;
677	if (pvFault - pMapping->GCPtr < pMapping->cb)
678	{
679	/*
680	* The first thing we check is if we've got an undetected conflict.
681	*/
682	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
683	{
684	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
685	while (iPT-- > 0)
686	if (GstWalk.pPde[iPT].n.u1Present)
687	{
688	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
689	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
690	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
691	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
692	return VINF_PGM_SYNC_CR3;
693	}
694	}
695
696	/*
697	* Check if the fault address is in a virtual page access handler range.
698	*/
699	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
700	if ( pCur
701	&& pvFault - pCur->Core.Key < pCur->cb
702	&& uErr & X86_TRAP_PF_RW)
703	{
704	# ifdef IN_RC
705	STAM_PROFILE_START(&pCur->Stat, h);
706	pgmUnlock(pVM);
707	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
708	pgmLock(pVM);
709	STAM_PROFILE_STOP(&pCur->Stat, h);
710	# else
711	AssertFailed();
712	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
713	# endif
714	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
715	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
716	return rc;
717	}
718
719	/*
720	* Pretend we're not here and let the guest handle the trap.
721	*/
722	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
723	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
724	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
725	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
726	return VINF_EM_RAW_GUEST_TRAP;
727	}
728	}
729	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
730	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
731
732	/*
733	* Check if this fault address is flagged for special treatment,
734	* which means we'll have to figure out the physical address and
735	* check flags associated with it.
736	*
737	* ASSUME that we can limit any special access handling to pages
738	* in page tables which the guest believes to be present.
739	*/
740	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
741	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
742	# else
743	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
745	PPGMPAGE pPage;
746	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
747	if (RT_FAILURE(rc))
748	{
749	/*
750	* When the guest accesses invalid physical memory (e.g. probing
751	* of RAM or accessing a remapped MMIO range), then we'll fall
752	* back to the recompiler to emulate the instruction.
753	*/
754	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
755	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
756	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
757	return VINF_EM_RAW_EMULATE_INSTR;
758	}
759
760	/*
761	* Any handlers for this page?
762	*/
763	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
764	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
765	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
766	&GstWalk));
767	# else
768	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
769	# endif
770
771	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
772
773	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
774	if (uErr & X86_TRAP_PF_P)
775	{
776	/*
777	* The page isn't marked, but it might still be monitored by a virtual page access handler.
778	* (ASSUMES no temporary disabling of virtual handlers.)
779	*/
780	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
781	* we should correct both the shadow page table and physical memory flags, and not only check for
782	* accesses within the handler region but for access to pages with virtual handlers. */
783	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
784	if (pCur)
785	{
786	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
787	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
788	\|\| !(uErr & X86_TRAP_PF_P)
789	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
790	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
791
792	if ( pvFault - pCur->Core.Key < pCur->cb
793	&& ( uErr & X86_TRAP_PF_RW
794	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
795	{
796	# ifdef IN_RC
797	STAM_PROFILE_START(&pCur->Stat, h);
798	pgmUnlock(pVM);
799	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
800	pgmLock(pVM);
801	STAM_PROFILE_STOP(&pCur->Stat, h);
802	# else
803	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
804	# endif
805	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
806	return rc;
807	}
808	}
809	}
810	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
811
812	/*
813	* We are here only if page is present in Guest page tables and
814	* trap is not handled by our handlers.
815	*
816	* Check it for page out-of-sync situation.
817	*/
818	if (!(uErr & X86_TRAP_PF_P))
819	{
820	/*
821	* Page is not present in our page tables. Try to sync it!
822	*/
823	if (uErr & X86_TRAP_PF_US)
824	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
825	else /* supervisor */
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
827
828	if (PGM_PAGE_IS_BALLOONED(pPage))
829	{
830	/* Emulate reads from ballooned pages as they are not present in
831	our shadow page tables. (Required for e.g. Solaris guests; soft
832	ecc, random nr generator.) */
833	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
834	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
835	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
836	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
837	return rc;
838	}
839
840	# if defined(LOG_ENABLED) && !defined(IN_RING0)
841	RTGCPHYS GCPhys2;
842	uint64_t fPageGst2;
843	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
844	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
845	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
846	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
847	# else
848	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
849	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
850	# endif
851	# endif /* LOG_ENABLED */
852
853	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
854	if ( !GstWalk.Core.fEffectiveUS
855	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
856	{
857	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
858	if ( pvFault == (RTGCPTR)pRegFrame->eip
859	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
860	# ifdef CSAM_DETECT_NEW_CODE_PAGES
861	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
862	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
863	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
864	)
865	{
866	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
867	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
868	if (rc != VINF_SUCCESS)
869	{
870	/*
871	* CSAM needs to perform a job in ring 3.
872	*
873	* Sync the page before going to the host context; otherwise we'll end up in a loop if
874	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
875	*/
876	LogFlow(("CSAM ring 3 job\n"));
877	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
878	AssertRC(rc2);
879
880	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
881	return rc;
882	}
883	}
884	# ifdef CSAM_DETECT_NEW_CODE_PAGES
885	else if ( uErr == X86_TRAP_PF_RW
886	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
887	&& pRegFrame->ecx < 0x10000)
888	{
889	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
890	* to detect loading of new code pages.
891	*/
892
893	/*
894	* Decode the instruction.
895	*/
896	RTGCPTR PC;
897	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
898	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
899	if (rc == VINF_SUCCESS)
900	{
901	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
902	uint32_t cbOp;
903	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
904
905	/* For now we'll restrict this to rep movsw/d instructions */
906	if ( rc == VINF_SUCCESS
907	&& pDis->pCurInstr->opcode == OP_MOVSWD
908	&& (pDis->prefix & PREFIX_REP))
909	{
910	CSAMMarkPossibleCodePage(pVM, pvFault);
911	}
912	}
913	}
914	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
915
916	/*
917	* Mark this page as safe.
918	*/
919	/** @todo not correct for pages that contain both code and data!! */
920	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
921	CSAMMarkPage(pVM, pvFault, true);
922	}
923	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
924	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
925	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
926	# else
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# endif
929	if (RT_SUCCESS(rc))
930	{
931	/* The page was successfully synced, return to the guest. */
932	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
933	return VINF_SUCCESS;
934	}
935	}
936	else /* uErr & X86_TRAP_PF_P: */
937	{
938	/*
939	* Write protected pages are made writable when the guest makes the
940	* first write to it. This happens for pages that are shared, write
941	* monitored or not yet allocated.
942	*
943	* We may also end up here when CR0.WP=0 in the guest.
944	*
945	* Also, a side effect of not flushing global PDEs are out of sync
946	* pages due to physical monitored regions, that are no longer valid.
947	* Assume for now it only applies to the read/write flag.
948	*/
949	if (uErr & X86_TRAP_PF_RW)
950	{
951	/*
952	* Check if it is a read-only page.
953	*/
954	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
955	{
956	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
957	Assert(!PGM_PAGE_IS_ZERO(pPage));
958	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
959	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
960
961	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
962	if (rc != VINF_SUCCESS)
963	{
964	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
965	return rc;
966	}
967	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
968	return VINF_EM_NO_MEMORY;
969	}
970
971	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
972	/*
973	* Check to see if we need to emulate the instruction if CR0.WP=0.
974	*/
975	if ( !GstWalk.Core.fEffectiveRW
976	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
977	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
978	{
979	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
980	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
981	if (RT_SUCCESS(rc))
982	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
983	else
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
985	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
986	return rc;
987	}
988	# endif
989	/// @todo count the above case; else
990	if (uErr & X86_TRAP_PF_US)
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
992	else /* supervisor */
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
994
995	/*
996	* Sync the page.
997	*
998	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
999	* page is not present, which is not true in this case.
1000	*/
1001	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1002	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1003	# else
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1005	# endif
1006	if (RT_SUCCESS(rc))
1007	{
1008	/*
1009	* Page was successfully synced, return to guest but invalidate
1010	* the TLB first as the page is very likely to be in it.
1011	*/
1012	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1013	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1014	# else
1015	PGM_INVL_PG(pVCpu, pvFault);
1016	# endif
1017	# ifdef VBOX_STRICT
1018	RTGCPHYS GCPhys2;
1019	uint64_t fPageGst;
1020	if (!pVM->pgm.s.fNestedPaging)
1021	{
1022	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1023	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1024	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1025	}
1026	uint64_t fPageShw;
1027	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1028	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1029	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1030	# endif /* VBOX_STRICT */
1031	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1032	return VINF_SUCCESS;
1033	}
1034	}
1035	/** @todo else: why are we here? */
1036
1037	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1038	/*
1039	* Check for VMM page flags vs. Guest page flags consistency.
1040	* Currently only for debug purposes.
1041	*/
1042	if (RT_SUCCESS(rc))
1043	{
1044	/* Get guest page flags. */
1045	uint64_t fPageGst;
1046	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1047	if (RT_SUCCESS(rc))
1048	{
1049	uint64_t fPageShw;
1050	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1051
1052	/*
1053	* Compare page flags.
1054	* Note: we have AVL, A, D bits desynched.
1055	*/
1056	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1057	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1058	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1059	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1060	}
1061	else
1062	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1063	}
1064	else
1065	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1066	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1067	}
1068
1069
1070	/*
1071	* If we get here it is because something failed above, i.e. most like guru
1072	* meditiation time.
1073	*/
1074	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1075	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1076	return rc;
1077
1078	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1079	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1080	return VERR_INTERNAL_ERROR;
1081	# endif
1082	}
1083	#endif /* !IN_RING3 */
1084
1085
1086	/**
1087	* Emulation of the invlpg instruction.
1088	*
1089	*
1090	* @returns VBox status code.
1091	*
1092	* @param pVCpu The VMCPU handle.
1093	* @param GCPtrPage Page to invalidate.
1094	*
1095	* @remark ASSUMES that the guest is updating before invalidating. This order
1096	* isn't required by the CPU, so this is speculative and could cause
1097	* trouble.
1098	* @remark No TLB shootdown is done on any other VCPU as we assume that
1099	* invlpg emulation is the only reason for calling this function.
1100	* (The guest has to shoot down TLB entries on other CPUs itself)
1101	* Currently true, but keep in mind!
1102	*
1103	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1104	*/
1105	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1106	{
1107	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1108	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1109	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1110	int rc;
1111	PVM pVM = pVCpu->CTX_SUFF(pVM);
1112	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1113
1114	Assert(PGMIsLockOwner(pVM));
1115
1116	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1117
1118	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1119	if (pPool->cDirtyPages)
1120	pgmPoolResetDirtyPages(pVM);
1121	# endif
1122
1123	/*
1124	* Get the shadow PD entry and skip out if this PD isn't present.
1125	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1126	*/
1127	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1128	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1129	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1130
1131	/* Fetch the pgm pool shadow descriptor. */
1132	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1133	Assert(pShwPde);
1134
1135	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1136	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1137	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1138
1139	/* If the shadow PDPE isn't present, then skip the invalidate. */
1140	if (!pPdptDst->a[iPdpt].n.u1Present)
1141	{
1142	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1143	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1144	return VINF_SUCCESS;
1145	}
1146
1147	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1148	PPGMPOOLPAGE pShwPde = NULL;
1149	PX86PDPAE pPDDst;
1150
1151	/* Fetch the pgm pool shadow descriptor. */
1152	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1153	AssertRCSuccessReturn(rc, rc);
1154	Assert(pShwPde);
1155
1156	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1157	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1158
1159	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1160	/* PML4 */
1161	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1162	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1163	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1164	PX86PDPAE pPDDst;
1165	PX86PDPT pPdptDst;
1166	PX86PML4E pPml4eDst;
1167	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1168	if (rc != VINF_SUCCESS)
1169	{
1170	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1171	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1172	return VINF_SUCCESS;
1173	}
1174	Assert(pPDDst);
1175
1176	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1177	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1178
1179	if (!pPdpeDst->n.u1Present)
1180	{
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1182	return VINF_SUCCESS;
1183	}
1184
1185	/* Fetch the pgm pool shadow descriptor. */
1186	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1187	Assert(pShwPde);
1188
1189	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1190
1191	const SHWPDE PdeDst = *pPdeDst;
1192	if (!PdeDst.n.u1Present)
1193	{
1194	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1195	return VINF_SUCCESS;
1196	}
1197
1198	/*
1199	* Get the guest PD entry and calc big page.
1200	*/
1201	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1202	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1203	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1204	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1205	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1206	unsigned iPDSrc = 0;
1207	# if PGM_GST_TYPE == PGM_TYPE_PAE
1208	X86PDPE PdpeSrcIgn;
1209	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1210	# else /* AMD64 */
1211	PX86PML4E pPml4eSrcIgn;
1212	X86PDPE PdpeSrcIgn;
1213	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1214	# endif
1215	GSTPDE PdeSrc;
1216
1217	if (pPDSrc)
1218	PdeSrc = pPDSrc->a[iPDSrc];
1219	else
1220	PdeSrc.u = 0;
1221	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1222	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1223
1224	# ifdef IN_RING3
1225	/*
1226	* If a CR3 Sync is pending we may ignore the invalidate page operation
1227	* depending on the kind of sync and if it's a global page or not.
1228	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1229	*/
1230	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1231	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1232	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1233	&& fIsBigPage
1234	&& PdeSrc.b.u1Global
1235	)
1236	)
1237	# else
1238	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1239	# endif
1240	{
1241	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1242	return VINF_SUCCESS;
1243	}
1244	# endif /* IN_RING3 */
1245
1246	/*
1247	* Deal with the Guest PDE.
1248	*/
1249	rc = VINF_SUCCESS;
1250	if (PdeSrc.n.u1Present)
1251	{
1252	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1253	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1254	# ifndef PGM_WITHOUT_MAPPING
1255	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1256	{
1257	/*
1258	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1259	*/
1260	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1261	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1263	}
1264	else
1265	# endif /* !PGM_WITHOUT_MAPPING */
1266	if (!fIsBigPage)
1267	{
1268	/*
1269	* 4KB - page.
1270	*/
1271	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1272	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1273
1274	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1275	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1276	if (pShwPage->cModifications)
1277	pShwPage->cModifications = 1;
1278	# endif
1279
1280	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1281	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1282	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1283	# endif
1284	if (pShwPage->GCPhys == GCPhys)
1285	{
1286	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1287	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1288	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1289	if (pPT->a[iPTEDst].n.u1Present)
1290	{
1291	/* This is very unlikely with caching/monitoring enabled. */
1292	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1293	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1294	}
1295	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1296	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1297	if (RT_SUCCESS(rc))
1298	rc = VINF_SUCCESS;
1299	# endif
1300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1301	PGM_INVL_PG(pVCpu, GCPtrPage);
1302	}
1303	else
1304	{
1305	/*
1306	* The page table address changed.
1307	*/
1308	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1309	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1310	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1311	ASMAtomicWriteSize(pPdeDst, 0);
1312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1313	PGM_INVL_VCPU_TLBS(pVCpu);
1314	}
1315	}
1316	else
1317	{
1318	/*
1319	* 2/4MB - page.
1320	*/
1321	/* Before freeing the page, check if anything really changed. */
1322	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1323	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1324	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1325	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1326	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1327	# endif
1328	if ( pShwPage->GCPhys == GCPhys
1329	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1330	{
1331	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1332	/** @todo This test is wrong as it cannot check the G bit!
1333	* FIXME */
1334	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1335	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1336	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1337	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1338	{
1339	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1340	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1341	return VINF_SUCCESS;
1342	}
1343	}
1344
1345	/*
1346	* Ok, the page table is present and it's been changed in the guest.
1347	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1348	* We could do this for some flushes in GC too, but we need an algorithm for
1349	* deciding which 4MB pages containing code likely to be executed very soon.
1350	*/
1351	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1352	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1353	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1354	ASMAtomicWriteSize(pPdeDst, 0);
1355	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1356	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1357	}
1358	}
1359	else
1360	{
1361	/*
1362	* Page directory is not present, mark shadow PDE not present.
1363	*/
1364	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1365	{
1366	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1367	ASMAtomicWriteSize(pPdeDst, 0);
1368	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1369	PGM_INVL_PG(pVCpu, GCPtrPage);
1370	}
1371	else
1372	{
1373	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1374	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1375	}
1376	}
1377	return rc;
1378
1379	#else /* guest real and protected mode */
1380	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1381	return VINF_SUCCESS;
1382	#endif
1383	}
1384
1385
1386	/**
1387	* Update the tracking of shadowed pages.
1388	*
1389	* @param pVCpu The VMCPU handle.
1390	* @param pShwPage The shadow page.
1391	* @param HCPhys The physical page we is being dereferenced.
1392	* @param iPte Shadow PTE index
1393	*/
1394	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1395	{
1396	PVM pVM = pVCpu->CTX_SUFF(pVM);
1397
1398	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1399	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1400
1401	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1402	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1403	* 2. write protect all shadowed pages. I.e. implement caching.
1404	*/
1405	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1406
1407	/*
1408	* Find the guest address.
1409	*/
1410	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1411	pRam;
1412	pRam = pRam->CTX_SUFF(pNext))
1413	{
1414	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1415	while (iPage-- > 0)
1416	{
1417	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1418	{
1419	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1420
1421	Assert(pShwPage->cPresent);
1422	Assert(pPool->cPresent);
1423	pShwPage->cPresent--;
1424	pPool->cPresent--;
1425
1426	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1427	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1428	return;
1429	}
1430	}
1431	}
1432
1433	for (;;)
1434	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1435	}
1436
1437
1438	/**
1439	* Update the tracking of shadowed pages.
1440	*
1441	* @param pVCpu The VMCPU handle.
1442	* @param pShwPage The shadow page.
1443	* @param u16 The top 16-bit of the pPage->HCPhys.
1444	* @param pPage Pointer to the guest page. this will be modified.
1445	* @param iPTDst The index into the shadow table.
1446	*/
1447	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1448	{
1449	PVM pVM = pVCpu->CTX_SUFF(pVM);
1450
1451	/*
1452	* Just deal with the simple first time here.
1453	*/
1454	if (!u16)
1455	{
1456	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1457	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1458	/* Save the page table index. */
1459	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1460	}
1461	else
1462	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1463
1464	/* write back */
1465	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1466	PGM_PAGE_SET_TRACKING(pPage, u16);
1467
1468	/* update statistics. */
1469	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1470	pShwPage->cPresent++;
1471	if (pShwPage->iFirstPresent > iPTDst)
1472	pShwPage->iFirstPresent = iPTDst;
1473	}
1474
1475
1476	/**
1477	* Modifies a shadow PTE to account for access handlers.
1478	*
1479	* @param pVM The VM handle.
1480	* @param pPage The page in question.
1481	* @param fPteSrc The flags of the source PTE.
1482	* @param pPteDst The shadow PTE (output). This is temporary storage and
1483	* does not need to be set atomically.
1484	*/
1485	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint32_t fPteSrc, PSHWPTE pPteDst)
1486	{
1487	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1488	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1489	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1490	{
1491	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1492	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1493	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1494	pPteDst->n.u1Present = 1;
1495	pPteDst->n.u1Execute = 1;
1496	pPteDst->n.u1IgnorePAT = 1;
1497	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1498	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1499	#else
1500	SHW_PTE_SET(*pPteDst,
1501	(fPteSrc & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1502	\| PGM_PAGE_GET_HCPHYS(pPage));
1503	#endif
1504	}
1505	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1506	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1507	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1508	&& ( BTH_IS_NP_ACTIVE(pVM)
1509	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1510	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1511	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1512	# endif
1513	)
1514	{
1515	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1516	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1517	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1518	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1519	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1520	pPteDst->n.u1Present = 0;
1521	pPteDst->n.u1Write = 1;
1522	pPteDst->n.u1Execute = 0;
1523	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1524	pPteDst->n.u3EMT = 7;
1525	# else
1526	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1527	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1528	# endif
1529	}
1530	# endif
1531	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1532	else
1533	{
1534	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1535	SHW_PTE_SET(*pPteDst, 0);
1536	}
1537	/** @todo count these kinds of entries. */
1538	}
1539
1540
1541	/**
1542	* Creates a 4K shadow page for a guest page.
1543	*
1544	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1545	* physical address. The PdeSrc argument only the flags are used. No page
1546	* structured will be mapped in this function.
1547	*
1548	* @param pVCpu The VMCPU handle.
1549	* @param pPteDst Destination page table entry.
1550	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1551	* Can safely assume that only the flags are being used.
1552	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1553	* @param pShwPage Pointer to the shadow page.
1554	* @param iPTDst The index into the shadow table.
1555	*
1556	* @remark Not used for 2/4MB pages!
1557	*/
1558	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1559	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1560	{
1561	if ( PteSrc.n.u1Present
1562	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1563	{
1564	PVM pVM = pVCpu->CTX_SUFF(pVM);
1565
1566	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1567	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1568	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1569	if (pShwPage->fDirty)
1570	{
1571	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1572	PX86PTPAE pGstPT;
1573
1574	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1575	pGstPT->a[iPTDst].u = PteSrc.u;
1576	}
1577	# endif
1578	/*
1579	* Find the ram range.
1580	*/
1581	PPGMPAGE pPage;
1582	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1583	if (RT_SUCCESS(rc))
1584	{
1585	/* Ignore ballooned pages.
1586	Don't return errors or use a fatal assert here as part of a
1587	shadow sync range might included ballooned pages. */
1588	if (PGM_PAGE_IS_BALLOONED(pPage))
1589	{
1590	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1591	return;
1592	}
1593
1594	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1595	/* Make the page writable if necessary. */
1596	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1597	&& ( PGM_PAGE_IS_ZERO(pPage)
1598	\|\| ( PteSrc.n.u1Write
1599	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1600	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1601	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1602	# endif
1603	# ifdef VBOX_WITH_PAGE_SHARING
1604	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1605	# endif
1606	)
1607	)
1608	)
1609	{
1610	rc = pgmPhysPageMakeWritable(pVM, pPage, PteSrc.u & GST_PTE_PG_MASK);
1611	AssertRC(rc);
1612	}
1613	#endif
1614
1615	/*
1616	* Make page table entry.
1617	*/
1618	SHWPTE PteDst;
1619	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1620	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage,
1621	PteSrc.u & ~( X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK
1622	\| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT),
1623	&PteDst);
1624	else
1625	{
1626	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1627	/*
1628	* If the page or page directory entry is not marked accessed,
1629	* we mark the page not present.
1630	*/
1631	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1632	{
1633	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1634	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1635	SHW_PTE_SET(PteDst, 0);
1636	}
1637	/*
1638	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1639	* when the page is modified.
1640	*/
1641	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1642	{
1643	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1644	SHW_PTE_SET(PteDst,
1645	(PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1646	\| PGM_PAGE_GET_HCPHYS(pPage)
1647	\| PGM_PTFLAGS_TRACK_DIRTY);
1648	}
1649	else
1650	#endif
1651	{
1652	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1653	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1654	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1655	PteDst.n.u1Present = 1;
1656	PteDst.n.u1Write = 1;
1657	PteDst.n.u1Execute = 1;
1658	PteDst.n.u1IgnorePAT = 1;
1659	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1660	/* PteDst.n.u1Size = 0 */
1661	#else
1662	SHW_PTE_SET(PteDst,
1663	(PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1664	\| PGM_PAGE_GET_HCPHYS(pPage));
1665	#endif
1666	}
1667
1668	/*
1669	* Make sure only allocated pages are mapped writable.
1670	*/
1671	if ( SHW_PTE_IS_P_RW(PteDst)
1672	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1673	{
1674	/* Still applies to shared pages. */
1675	Assert(!PGM_PAGE_IS_ZERO(pPage));
1676	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1677	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)(PteSrc.u & X86_PTE_PAE_PG_MASK), pPage, iPTDst));
1678	}
1679	}
1680
1681	/*
1682	* Keep user track up to date.
1683	*/
1684	if (SHW_PTE_IS_P(PteDst))
1685	{
1686	if (!SHW_PTE_IS_P(*pPteDst))
1687	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1688	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1689	{
1690	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1691	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1692	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1693	}
1694	}
1695	else if (SHW_PTE_IS_P(*pPteDst))
1696	{
1697	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1698	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1699	}
1700
1701	/*
1702	* Update statistics and commit the entry.
1703	*/
1704	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1705	if (!PteSrc.n.u1Global)
1706	pShwPage->fSeenNonGlobal = true;
1707	#endif
1708	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1709	return;
1710	}
1711
1712	/** @todo count these three different kinds. */
1713	Log2(("SyncPageWorker: invalid address in Pte\n"));
1714	}
1715	else if (!PteSrc.n.u1Present)
1716	Log2(("SyncPageWorker: page not present in Pte\n"));
1717	else
1718	Log2(("SyncPageWorker: invalid Pte\n"));
1719
1720	/*
1721	* The page is not present or the PTE is bad. Replace the shadow PTE by
1722	* an empty entry, making sure to keep the user tracking up to date.
1723	*/
1724	if (SHW_PTE_IS_P(*pPteDst))
1725	{
1726	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1727	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1728	}
1729	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1730	}
1731
1732
1733	/**
1734	* Syncs a guest OS page.
1735	*
1736	* There are no conflicts at this point, neither is there any need for
1737	* page table allocations.
1738	*
1739	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1740	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1741	*
1742	* @returns VBox status code.
1743	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1744	* @param pVCpu The VMCPU handle.
1745	* @param PdeSrc Page directory entry of the guest.
1746	* @param GCPtrPage Guest context page address.
1747	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1748	* @param uErr Fault error (X86_TRAP_PF_*).
1749	*/
1750	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1751	{
1752	PVM pVM = pVCpu->CTX_SUFF(pVM);
1753	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1754	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1755
1756	Assert(PGMIsLockOwner(pVM));
1757
1758	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1759	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1760	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1761	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1762	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1763
1764	/*
1765	* Assert preconditions.
1766	*/
1767	Assert(PdeSrc.n.u1Present);
1768	Assert(cPages);
1769	# if 0 /* rarely useful; leave for debugging. */
1770	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1771	# endif
1772
1773	/*
1774	* Get the shadow PDE, find the shadow page table in the pool.
1775	*/
1776	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1777	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1778	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1779
1780	/* Fetch the pgm pool shadow descriptor. */
1781	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1782	Assert(pShwPde);
1783
1784	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1785	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1786	PPGMPOOLPAGE pShwPde = NULL;
1787	PX86PDPAE pPDDst;
1788
1789	/* Fetch the pgm pool shadow descriptor. */
1790	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1791	AssertRCSuccessReturn(rc2, rc2);
1792	Assert(pShwPde);
1793
1794	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1795	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1796
1797	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1798	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1799	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1800	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1801	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1802
1803	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1804	AssertRCSuccessReturn(rc2, rc2);
1805	Assert(pPDDst && pPdptDst);
1806	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1807	# endif
1808	SHWPDE PdeDst = *pPdeDst;
1809
1810	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1811	if (!PdeDst.n.u1Present)
1812	{
1813	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1814	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
1815	return VINF_SUCCESS; /* force the instruction to be executed again. */
1816	}
1817
1818	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1819	Assert(pShwPage);
1820
1821	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1822	/* Fetch the pgm pool shadow descriptor. */
1823	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1824	Assert(pShwPde);
1825	# endif
1826
1827	/*
1828	* Check that the page is present and that the shadow PDE isn't out of sync.
1829	*/
1830	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1831	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1832	RTGCPHYS GCPhys;
1833	if (!fBigPage)
1834	{
1835	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1836	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1837	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1838	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1839	# endif
1840	}
1841	else
1842	{
1843	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1844	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1845	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1846	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1847	# endif
1848	}
1849	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1850	if ( fPdeValid
1851	&& pShwPage->GCPhys == GCPhys
1852	&& PdeSrc.n.u1Present
1853	&& PdeSrc.n.u1User == PdeDst.n.u1User
1854	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1855	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1856	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1857	# endif
1858	)
1859	{
1860	/*
1861	* Check that the PDE is marked accessed already.
1862	* Since we set the accessed bit before getting here on a #PF, this
1863	* check is only meant for dealing with non-#PF'ing paths.
1864	*/
1865	if (PdeSrc.n.u1Accessed)
1866	{
1867	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1868	if (!fBigPage)
1869	{
1870	/*
1871	* 4KB Page - Map the guest page table.
1872	*/
1873	PGSTPT pPTSrc;
1874	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1875	if (RT_SUCCESS(rc))
1876	{
1877	# ifdef PGM_SYNC_N_PAGES
1878	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1879	if ( cPages > 1
1880	&& !(uErr & X86_TRAP_PF_P)
1881	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1882	{
1883	/*
1884	* This code path is currently only taken when the caller is PGMTrap0eHandler
1885	* for non-present pages!
1886	*
1887	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1888	* deal with locality.
1889	*/
1890	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1891	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1892	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1893	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1894	# else
1895	const unsigned offPTSrc = 0;
1896	# endif
1897	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1898	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1899	iPTDst = 0;
1900	else
1901	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1902	for (; iPTDst < iPTDstEnd; iPTDst++)
1903	{
1904	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1905	{
1906	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1907	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1908	NOREF(GCPtrCurPage);
1909	#ifndef IN_RING0
1910	/*
1911	* Assuming kernel code will be marked as supervisor - and not as user level
1912	* and executed using a conforming code selector - And marked as readonly.
1913	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1914	*/
1915	PPGMPAGE pPage;
1916	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1917	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1918	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1919	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1920	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1921	)
1922	#endif /* else: CSAM not active */
1923	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1924	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1925	GCPtrCurPage, PteSrc.n.u1Present,
1926	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1927	PteSrc.n.u1User & PdeSrc.n.u1User,
1928	(uint64_t)PteSrc.u,
1929	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1930	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1931	}
1932	}
1933	}
1934	else
1935	# endif /* PGM_SYNC_N_PAGES */
1936	{
1937	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1938	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1939	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1940	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1941	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1942	GCPtrPage, PteSrc.n.u1Present,
1943	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1944	PteSrc.n.u1User & PdeSrc.n.u1User,
1945	(uint64_t)PteSrc.u,
1946	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1947	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1948	}
1949	}
1950	else /* MMIO or invalid page: emulated in #PF handler. */
1951	{
1952	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1953	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1954	}
1955	}
1956	else
1957	{
1958	/*
1959	* 4/2MB page - lazy syncing shadow 4K pages.
1960	* (There are many causes of getting here, it's no longer only CSAM.)
1961	*/
1962	/* Calculate the GC physical address of this 4KB shadow page. */
1963	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1964	/* Find ram range. */
1965	PPGMPAGE pPage;
1966	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1967	if (RT_SUCCESS(rc))
1968	{
1969	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1970
1971	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1972	/* Try to make the page writable if necessary. */
1973	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1974	&& ( PGM_PAGE_IS_ZERO(pPage)
1975	\|\| ( PdeSrc.n.u1Write
1976	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1977	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1978	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1979	# endif
1980	# ifdef VBOX_WITH_PAGE_SHARING
1981	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1982	# endif
1983	)
1984	)
1985	)
1986	{
1987	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1988	AssertRC(rc);
1989	}
1990	# endif
1991
1992	/*
1993	* Make shadow PTE entry.
1994	*/
1995	SHWPTE PteDst;
1996	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1997	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
1998	else
1999	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2000
2001	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2002	if ( SHW_PTE_IS_P(PteDst)
2003	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2004	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2005
2006	/* Make sure only allocated pages are mapped writable. */
2007	if ( SHW_PTE_IS_P_RW(PteDst)
2008	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2009	{
2010	/* Still applies to shared pages. */
2011	Assert(!PGM_PAGE_IS_ZERO(pPage));
2012	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2013	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2014	}
2015
2016	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2017
2018	/*
2019	* If the page is not flagged as dirty and is writable, then make it read-only
2020	* at PD level, so we can set the dirty bit when the page is modified.
2021	*
2022	* ASSUMES that page access handlers are implemented on page table entry level.
2023	* Thus we will first catch the dirty access and set PDE.D and restart. If
2024	* there is an access handler, we'll trap again and let it work on the problem.
2025	*/
2026	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2027	* As for invlpg, it simply frees the whole shadow PT.
2028	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2029	if ( !PdeSrc.b.u1Dirty
2030	&& PdeSrc.b.u1Write)
2031	{
2032	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2033	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2034	PdeDst.n.u1Write = 0;
2035	}
2036	else
2037	{
2038	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2039	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2040	}
2041	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2042	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2043	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2044	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2045	}
2046	else
2047	{
2048	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2049	/** @todo must wipe the shadow page table entry in this
2050	* case. */
2051	}
2052	}
2053	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2054	return VINF_SUCCESS;
2055	}
2056
2057	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2058	}
2059	else if (fPdeValid)
2060	{
2061	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2062	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2063	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2064	}
2065	else
2066	{
2067	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2068	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2069	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2070	}
2071
2072	/*
2073	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2074	* Yea, I'm lazy.
2075	*/
2076	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2077	ASMAtomicWriteSize(pPdeDst, 0);
2078
2079	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2080	PGM_INVL_VCPU_TLBS(pVCpu);
2081	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2082
2083
2084	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2085	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2086	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2087	&& !defined(IN_RC)
2088
2089	# ifdef PGM_SYNC_N_PAGES
2090	/*
2091	* Get the shadow PDE, find the shadow page table in the pool.
2092	*/
2093	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2094	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2095
2096	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2097	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2098
2099	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2100	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2101	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2102	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2103	X86PDEPAE PdeDst;
2104	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2105
2106	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2107	AssertRCSuccessReturn(rc, rc);
2108	Assert(pPDDst && pPdptDst);
2109	PdeDst = pPDDst->a[iPDDst];
2110	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2111	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2112	PEPTPD pPDDst;
2113	EPTPDE PdeDst;
2114
2115	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2116	if (rc != VINF_SUCCESS)
2117	{
2118	AssertRC(rc);
2119	return rc;
2120	}
2121	Assert(pPDDst);
2122	PdeDst = pPDDst->a[iPDDst];
2123	# endif
2124	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2125	if (!PdeDst.n.u1Present)
2126	{
2127	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2128	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2129	return VINF_SUCCESS; /* force the instruction to be executed again. */
2130	}
2131
2132	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2133	if (PdeDst.n.u1Size)
2134	{
2135	Assert(pVM->pgm.s.fNestedPaging);
2136	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2137	return VINF_SUCCESS;
2138	}
2139
2140	/* Mask away the page offset. */
2141	GCPtrPage &= ~((RTGCPTR)0xfff);
2142
2143	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2144	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2145
2146	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2147	if ( cPages > 1
2148	&& !(uErr & X86_TRAP_PF_P)
2149	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2150	{
2151	/*
2152	* This code path is currently only taken when the caller is PGMTrap0eHandler
2153	* for non-present pages!
2154	*
2155	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2156	* deal with locality.
2157	*/
2158	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2159	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2160	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2161	iPTDst = 0;
2162	else
2163	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2164	for (; iPTDst < iPTDstEnd; iPTDst++)
2165	{
2166	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2167	{
2168	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2169	GSTPTE PteSrc;
2170
2171	/* Fake the page table entry */
2172	PteSrc.u = GCPtrCurPage;
2173	PteSrc.n.u1Present = 1;
2174	PteSrc.n.u1Dirty = 1;
2175	PteSrc.n.u1Accessed = 1;
2176	PteSrc.n.u1Write = 1;
2177	PteSrc.n.u1User = 1;
2178
2179	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2180	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2181	GCPtrCurPage, PteSrc.n.u1Present,
2182	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2183	PteSrc.n.u1User & PdeSrc.n.u1User,
2184	(uint64_t)PteSrc.u,
2185	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2186	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2187
2188	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2189	break;
2190	}
2191	else
2192	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2193	}
2194	}
2195	else
2196	# endif /* PGM_SYNC_N_PAGES */
2197	{
2198	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2199	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2200	GSTPTE PteSrc;
2201
2202	/* Fake the page table entry */
2203	PteSrc.u = GCPtrCurPage;
2204	PteSrc.n.u1Present = 1;
2205	PteSrc.n.u1Dirty = 1;
2206	PteSrc.n.u1Accessed = 1;
2207	PteSrc.n.u1Write = 1;
2208	PteSrc.n.u1User = 1;
2209	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2210
2211	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2212	GCPtrPage, PteSrc.n.u1Present,
2213	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2214	PteSrc.n.u1User & PdeSrc.n.u1User,
2215	(uint64_t)PteSrc.u,
2216	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2217	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2218	}
2219	return VINF_SUCCESS;
2220
2221	#else
2222	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2223	return VERR_INTERNAL_ERROR;
2224	#endif
2225	}
2226
2227
2228	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2229
2230	/**
2231	* CheckPageFault helper for returning a page fault indicating a non-present
2232	* (NP) entry in the page translation structures.
2233	*
2234	* @returns VINF_EM_RAW_GUEST_TRAP.
2235	* @param pVCpu The virtual CPU to operate on.
2236	* @param uErr The error code of the shadow fault. Corrections to
2237	* TRPM's copy will be made if necessary.
2238	* @param GCPtrPage For logging.
2239	* @param uPageFaultLevel For logging.
2240	*/
2241	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2242	{
2243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2244	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2245	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2246	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2247	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2248
2249	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2250	return VINF_EM_RAW_GUEST_TRAP;
2251	}
2252
2253
2254	/**
2255	* CheckPageFault helper for returning a page fault indicating a reserved bit
2256	* (RSVD) error in the page translation structures.
2257	*
2258	* @returns VINF_EM_RAW_GUEST_TRAP.
2259	* @param pVCpu The virtual CPU to operate on.
2260	* @param uErr The error code of the shadow fault. Corrections to
2261	* TRPM's copy will be made if necessary.
2262	* @param GCPtrPage For logging.
2263	* @param uPageFaultLevel For logging.
2264	*/
2265	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2266	{
2267	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2268	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2269	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2270
2271	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2272	return VINF_EM_RAW_GUEST_TRAP;
2273	}
2274
2275
2276	/**
2277	* CheckPageFault helper for returning a page protection fault (P).
2278	*
2279	* @returns VINF_EM_RAW_GUEST_TRAP.
2280	* @param pVCpu The virtual CPU to operate on.
2281	* @param uErr The error code of the shadow fault. Corrections to
2282	* TRPM's copy will be made if necessary.
2283	* @param GCPtrPage For logging.
2284	* @param uPageFaultLevel For logging.
2285	*/
2286	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2287	{
2288	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2289	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2290	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2291	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2292
2293	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2294	return VINF_EM_RAW_GUEST_TRAP;
2295	}
2296
2297
2298	/**
2299	* Handle dirty bit tracking faults.
2300	*
2301	* @returns VBox status code.
2302	* @param pVCpu The VMCPU handle.
2303	* @param uErr Page fault error code.
2304	* @param pPdeSrc Guest page directory entry.
2305	* @param pPdeDst Shadow page directory entry.
2306	* @param GCPtrPage Guest context page address.
2307	*/
2308	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2309	{
2310	PVM pVM = pVCpu->CTX_SUFF(pVM);
2311	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2312
2313	Assert(PGMIsLockOwner(pVM));
2314
2315	/*
2316	* Handle big page.
2317	*/
2318	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2319	{
2320	if ( pPdeDst->n.u1Present
2321	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2322	{
2323	SHWPDE PdeDst = *pPdeDst;
2324
2325	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2326	Assert(pPdeSrc->b.u1Write);
2327
2328	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2329	* fault again and take this path to only invalidate the entry (see below).
2330	*/
2331	PdeDst.n.u1Write = 1;
2332	PdeDst.n.u1Accessed = 1;
2333	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2334	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2335	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2336	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2337	}
2338
2339	# ifdef IN_RING0
2340	/* Check for stale TLB entry; only applies to the SMP guest case. */
2341	if ( pVM->cCpus > 1
2342	&& pPdeDst->n.u1Write
2343	&& pPdeDst->n.u1Accessed)
2344	{
2345	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2346	if (pShwPage)
2347	{
2348	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2349	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2350	if (SHW_PTE_IS_P_RW(*pPteDst))
2351	{
2352	/* Stale TLB entry. */
2353	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2354	PGM_INVL_PG(pVCpu, GCPtrPage);
2355	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2356	}
2357	}
2358	}
2359	# endif /* IN_RING0 */
2360	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2361	}
2362
2363	/*
2364	* Map the guest page table.
2365	*/
2366	PGSTPT pPTSrc;
2367	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2368	if (RT_FAILURE(rc))
2369	{
2370	AssertRC(rc);
2371	return rc;
2372	}
2373
2374	if (pPdeDst->n.u1Present)
2375	{
2376	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2377	const GSTPTE PteSrc = *pPteSrc;
2378
2379	#ifndef IN_RING0
2380	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2381	* Our individual shadow handlers will provide more information and force a fatal exit.
2382	*/
2383	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2384	{
2385	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2386	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2387	}
2388	#endif
2389	/*
2390	* Map shadow page table.
2391	*/
2392	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2393	if (pShwPage)
2394	{
2395	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2396	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2397	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2398	{
2399	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2400	{
2401	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
2402	SHWPTE PteDst = *pPteDst;
2403
2404	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2405	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2406
2407	Assert(pPteSrc->n.u1Write);
2408
2409	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2410	* entry will not harm; write access will simply fault again and
2411	* take this path to only invalidate the entry.
2412	*/
2413	if (RT_LIKELY(pPage))
2414	{
2415	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2416	{
2417	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2418	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2419	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2420	SHW_PTE_SET_RO(PteDst);
2421	}
2422	else
2423	{
2424	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2425	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2426	{
2427	rc = pgmPhysPageMakeWritable(pVM, pPage, pPteSrc->u & GST_PTE_PG_MASK);
2428	AssertRC(rc);
2429	}
2430	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2431	SHW_PTE_SET_RW(PteDst);
2432	else
2433	{
2434	/* Still applies to shared pages. */
2435	Assert(!PGM_PAGE_IS_ZERO(pPage));
2436	SHW_PTE_SET_RO(PteDst);
2437	}
2438	}
2439	}
2440	else
2441	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2442
2443	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2444	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2445	PGM_INVL_PG(pVCpu, GCPtrPage);
2446	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2447	}
2448
2449	# ifdef IN_RING0
2450	/* Check for stale TLB entry; only applies to the SMP guest case. */
2451	if ( pVM->cCpus > 1
2452	&& SHW_PTE_IS_RW(*pPteDst)
2453	&& SHW_PTE_IS_A(*pPteDst))
2454	{
2455	/* Stale TLB entry. */
2456	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2457	PGM_INVL_PG(pVCpu, GCPtrPage);
2458	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2459	}
2460	# endif
2461	}
2462	}
2463	else
2464	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2465	}
2466
2467	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2468	}
2469
2470	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2471
2472
2473	/**
2474	* Sync a shadow page table.
2475	*
2476	* The shadow page table is not present in the shadow PDE.
2477	*
2478	* Handles mapping conflicts.
2479	*
2480	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2481	* conflict), and Trap0eHandler.
2482	*
2483	* A precodition for this method is that the shadow PDE is not present. The
2484	* caller must take the PGM lock before checking this and continue to hold it
2485	* when calling this method.
2486	*
2487	* @returns VBox status code.
2488	* @param pVCpu The VMCPU handle.
2489	* @param iPD Page directory index.
2490	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2491	* Assume this is a temporary mapping.
2492	* @param GCPtrPage GC Pointer of the page that caused the fault
2493	*/
2494	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2495	{
2496	PVM pVM = pVCpu->CTX_SUFF(pVM);
2497	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2498
2499	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2500	#if 0 /* rarely useful; leave for debugging. */
2501	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2502	#endif
2503	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2504
2505	Assert(PGMIsLocked(pVM));
2506
2507	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2508	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2509	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2510	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2511	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2512
2513	int rc = VINF_SUCCESS;
2514
2515	/*
2516	* Some input validation first.
2517	*/
2518	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2519
2520	/*
2521	* Get the relevant shadow PDE entry.
2522	*/
2523	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2524	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2525	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2526
2527	/* Fetch the pgm pool shadow descriptor. */
2528	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2529	Assert(pShwPde);
2530
2531	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2532	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2533	PPGMPOOLPAGE pShwPde = NULL;
2534	PX86PDPAE pPDDst;
2535	PSHWPDE pPdeDst;
2536
2537	/* Fetch the pgm pool shadow descriptor. */
2538	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2539	AssertRCSuccessReturn(rc, rc);
2540	Assert(pShwPde);
2541
2542	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2543	pPdeDst = &pPDDst->a[iPDDst];
2544
2545	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2546	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2547	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2548	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2549	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2550	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2551	AssertRCSuccessReturn(rc, rc);
2552	Assert(pPDDst);
2553	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2554	# endif
2555	SHWPDE PdeDst = *pPdeDst;
2556
2557	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2558	/* Fetch the pgm pool shadow descriptor. */
2559	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2560	Assert(pShwPde);
2561	# endif
2562
2563	# ifndef PGM_WITHOUT_MAPPINGS
2564	/*
2565	* Check for conflicts.
2566	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2567	* R3: Simply resolve the conflict.
2568	*/
2569	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2570	{
2571	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2572	# ifndef IN_RING3
2573	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2574	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2575	return VERR_ADDRESS_CONFLICT;
2576
2577	# else /* IN_RING3 */
2578	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2579	Assert(pMapping);
2580	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2581	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2582	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2583	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2584	# else
2585	AssertFailed(); /* can't happen for amd64 */
2586	# endif
2587	if (RT_FAILURE(rc))
2588	{
2589	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2590	return rc;
2591	}
2592	PdeDst = *pPdeDst;
2593	# endif /* IN_RING3 */
2594	}
2595	# endif /* !PGM_WITHOUT_MAPPINGS */
2596	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2597
2598	/*
2599	* Sync the page directory entry.
2600	*/
2601	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2602	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2603	if ( PdeSrc.n.u1Present
2604	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2605	{
2606	/*
2607	* Allocate & map the page table.
2608	*/
2609	PSHWPT pPTDst;
2610	PPGMPOOLPAGE pShwPage;
2611	RTGCPHYS GCPhys;
2612	if (fPageTable)
2613	{
2614	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2615	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2616	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2617	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2618	# endif
2619	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2620	}
2621	else
2622	{
2623	PGMPOOLACCESS enmAccess;
2624	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2625	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2626	# else
2627	const bool fNoExecute = false;
2628	# endif
2629
2630	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2631	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2632	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2633	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2634	# endif
2635	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2636	if (PdeSrc.n.u1User)
2637	{
2638	if (PdeSrc.n.u1Write)
2639	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2640	else
2641	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2642	}
2643	else
2644	{
2645	if (PdeSrc.n.u1Write)
2646	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2647	else
2648	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2649	}
2650	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, &pShwPage);
2651	}
2652	if (rc == VINF_SUCCESS)
2653	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2654	else if (rc == VINF_PGM_CACHED_PAGE)
2655	{
2656	/*
2657	* The PT was cached, just hook it up.
2658	*/
2659	if (fPageTable)
2660	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2661	else
2662	{
2663	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2664	/* (see explanation and assumptions further down.) */
2665	if ( !PdeSrc.b.u1Dirty
2666	&& PdeSrc.b.u1Write)
2667	{
2668	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2669	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2670	PdeDst.b.u1Write = 0;
2671	}
2672	}
2673	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2674	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2675	return VINF_SUCCESS;
2676	}
2677	else if (rc == VERR_PGM_POOL_FLUSHED)
2678	{
2679	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2680	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2681	return VINF_PGM_SYNC_CR3;
2682	}
2683	else
2684	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2685	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2686	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2687	* irrelevant at this point. */
2688	PdeDst.u &= X86_PDE_AVL_MASK;
2689	PdeDst.u \|= pShwPage->Core.Key;
2690
2691	/*
2692	* Page directory has been accessed (this is a fault situation, remember).
2693	*/
2694	/** @todo
2695	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2696	* fault situation. What's more, the Trap0eHandler has already set the
2697	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2698	* might need setting the accessed flag.
2699	*
2700	* The best idea is to leave this change to the caller and add an
2701	* assertion that it's set already. */
2702	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2703	if (fPageTable)
2704	{
2705	/*
2706	* Page table - 4KB.
2707	*
2708	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2709	*/
2710	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2711	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2712	PGSTPT pPTSrc;
2713	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2714	if (RT_SUCCESS(rc))
2715	{
2716	/*
2717	* Start by syncing the page directory entry so CSAM's TLB trick works.
2718	*/
2719	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2720	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2721	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2722	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2723
2724	/*
2725	* Directory/page user or supervisor privilege: (same goes for read/write)
2726	*
2727	* Directory Page Combined
2728	* U/S U/S U/S
2729	* 0 0 0
2730	* 0 1 0
2731	* 1 0 0
2732	* 1 1 1
2733	*
2734	* Simple AND operation. Table listed for completeness.
2735	*
2736	*/
2737	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2738	# ifdef PGM_SYNC_N_PAGES
2739	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2740	unsigned iPTDst = iPTBase;
2741	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2742	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2743	iPTDst = 0;
2744	else
2745	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2746	# else /* !PGM_SYNC_N_PAGES */
2747	unsigned iPTDst = 0;
2748	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2749	# endif /* !PGM_SYNC_N_PAGES */
2750	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2751	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2752	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2753	# else
2754	const unsigned offPTSrc = 0;
2755	# endif
2756	for (; iPTDst < iPTDstEnd; iPTDst++)
2757	{
2758	const unsigned iPTSrc = iPTDst + offPTSrc;
2759	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2760
2761	if (PteSrc.n.u1Present)
2762	{
2763	# ifndef IN_RING0
2764	/*
2765	* Assuming kernel code will be marked as supervisor - and not as user level
2766	* and executed using a conforming code selector - And marked as readonly.
2767	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2768	*/
2769	PPGMPAGE pPage;
2770	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2771	\|\| !CSAMDoesPageNeedScanning(pVM, (iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT))
2772	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2773	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2774	)
2775	# endif
2776	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2777	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2778	(RTGCPTR)(((RTGCPTR)iPDSrc << GST_PD_SHIFT) \| ((RTGCPTR)iPTSrc << PAGE_SHIFT)),
2779	PteSrc.n.u1Present,
2780	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2781	PteSrc.n.u1User & PdeSrc.n.u1User,
2782	(uint64_t)PteSrc.u,
2783	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2784	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2785	}
2786	/* else: the page table was cleared by the pool */
2787	} /* for PTEs */
2788	}
2789	}
2790	else
2791	{
2792	/*
2793	* Big page - 2/4MB.
2794	*
2795	* We'll walk the ram range list in parallel and optimize lookups.
2796	* We will only sync on shadow page table at a time.
2797	*/
2798	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2799
2800	/**
2801	* @todo It might be more efficient to sync only a part of the 4MB
2802	* page (similar to what we do for 4KB PDs).
2803	*/
2804
2805	/*
2806	* Start by syncing the page directory entry.
2807	*/
2808	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2809	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2810
2811	/*
2812	* If the page is not flagged as dirty and is writable, then make it read-only
2813	* at PD level, so we can set the dirty bit when the page is modified.
2814	*
2815	* ASSUMES that page access handlers are implemented on page table entry level.
2816	* Thus we will first catch the dirty access and set PDE.D and restart. If
2817	* there is an access handler, we'll trap again and let it work on the problem.
2818	*/
2819	/** @todo move the above stuff to a section in the PGM documentation. */
2820	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2821	if ( !PdeSrc.b.u1Dirty
2822	&& PdeSrc.b.u1Write)
2823	{
2824	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2825	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2826	PdeDst.b.u1Write = 0;
2827	}
2828	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2829	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2830
2831	/*
2832	* Fill the shadow page table.
2833	*/
2834	/* Get address and flags from the source PDE. */
2835	SHWPTE PteDstBase;
2836	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2837
2838	/* Loop thru the entries in the shadow PT. */
2839	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2840	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2841	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2842	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2843	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2844	unsigned iPTDst = 0;
2845	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2846	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2847	{
2848	/* Advance ram range list. */
2849	while (pRam && GCPhys > pRam->GCPhysLast)
2850	pRam = pRam->CTX_SUFF(pNext);
2851	if (pRam && GCPhys >= pRam->GCPhys)
2852	{
2853	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2854	do
2855	{
2856	/* Make shadow PTE. */
2857	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2858	SHWPTE PteDst;
2859
2860	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2861	/* Try to make the page writable if necessary. */
2862	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2863	&& ( PGM_PAGE_IS_ZERO(pPage)
2864	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2865	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2866	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2867	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2868	# endif
2869	# ifdef VBOX_WITH_PAGE_SHARING
2870	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2871	# endif
2872	&& !PGM_PAGE_IS_BALLOONED(pPage))
2873	)
2874	)
2875	{
2876	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2877	AssertRCReturn(rc, rc);
2878	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2879	break;
2880	}
2881	# endif
2882
2883	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2884	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2885	else if (PGM_PAGE_IS_BALLOONED(pPage))
2886	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2887	# ifndef IN_RING0
2888	/*
2889	* Assuming kernel code will be marked as supervisor and not as user level and executed
2890	* using a conforming code selector. Don't check for readonly, as that implies the whole
2891	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2892	*/
2893	else if ( !PdeSrc.n.u1User
2894	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2895	SHW_PTE_SET(PteDst, 0);
2896	# endif
2897	else
2898	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2899
2900	/* Only map writable pages writable. */
2901	if ( SHW_PTE_IS_P_RW(PteDst)
2902	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2903	{
2904	/* Still applies to shared pages. */
2905	Assert(!PGM_PAGE_IS_ZERO(pPage));
2906	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2907	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2908	}
2909
2910	if (SHW_PTE_IS_P(PteDst))
2911	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2912
2913	/* commit it (not atomic, new table) */
2914	pPTDst->a[iPTDst] = PteDst;
2915	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2916	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2917	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2918
2919	/* advance */
2920	GCPhys += PAGE_SIZE;
2921	iHCPage++;
2922	iPTDst++;
2923	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2924	&& GCPhys <= pRam->GCPhysLast);
2925	}
2926	else if (pRam)
2927	{
2928	Log(("Invalid pages at %RGp\n", GCPhys));
2929	do
2930	{
2931	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2932	GCPhys += PAGE_SIZE;
2933	iPTDst++;
2934	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2935	&& GCPhys < pRam->GCPhys);
2936	}
2937	else
2938	{
2939	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2940	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2941	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2942	}
2943	} /* while more PTEs */
2944	} /* 4KB / 4MB */
2945	}
2946	else
2947	AssertRelease(!PdeDst.n.u1Present);
2948
2949	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2950	if (RT_FAILURE(rc))
2951	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2952	return rc;
2953
2954	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2955	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2956	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2957	&& !defined(IN_RC)
2958
2959	/*
2960	* Validate input a little bit.
2961	*/
2962	int rc = VINF_SUCCESS;
2963	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2964	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2965	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2966
2967	/* Fetch the pgm pool shadow descriptor. */
2968	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2969	Assert(pShwPde);
2970
2971	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2972	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2973	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2974	PX86PDPAE pPDDst;
2975	PSHWPDE pPdeDst;
2976
2977	/* Fetch the pgm pool shadow descriptor. */
2978	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2979	AssertRCSuccessReturn(rc, rc);
2980	Assert(pShwPde);
2981
2982	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2983	pPdeDst = &pPDDst->a[iPDDst];
2984
2985	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2986	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2987	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2988	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2989	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2990	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2991	AssertRCSuccessReturn(rc, rc);
2992	Assert(pPDDst);
2993	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2994
2995	/* Fetch the pgm pool shadow descriptor. */
2996	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2997	Assert(pShwPde);
2998
2999	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3000	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3001	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3002	PEPTPD pPDDst;
3003	PEPTPDPT pPdptDst;
3004
3005	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3006	if (rc != VINF_SUCCESS)
3007	{
3008	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3009	AssertRC(rc);
3010	return rc;
3011	}
3012	Assert(pPDDst);
3013	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3014
3015	/* Fetch the pgm pool shadow descriptor. */
3016	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3017	Assert(pShwPde);
3018	# endif
3019	SHWPDE PdeDst = *pPdeDst;
3020
3021	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3022	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3023
3024	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3025	if (BTH_IS_NP_ACTIVE(pVM))
3026	{
3027	PPGMPAGE pPage;
3028
3029	/* Check if we allocated a big page before for this 2 MB range. */
3030	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3031	if (RT_SUCCESS(rc))
3032	{
3033	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3034
3035	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3036	{
3037	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3038	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3039	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3040	}
3041	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3042	{
3043	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3044	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3045	if (RT_SUCCESS(rc))
3046	{
3047	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3048	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3049	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3050	}
3051	}
3052	else if (PGMIsUsingLargePages(pVM))
3053	{
3054	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3055	if (RT_SUCCESS(rc))
3056	{
3057	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3058	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3059	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3060	}
3061	else
3062	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3063	}
3064
3065	if (HCPhys != NIL_RTHCPHYS)
3066	{
3067	PdeDst.u &= X86_PDE_AVL_MASK;
3068	PdeDst.u \|= HCPhys;
3069	PdeDst.n.u1Present = 1;
3070	PdeDst.n.u1Write = 1;
3071	PdeDst.b.u1Size = 1;
3072	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3073	PdeDst.n.u1Execute = 1;
3074	PdeDst.b.u1IgnorePAT = 1;
3075	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3076	# else
3077	PdeDst.n.u1User = 1;
3078	# endif
3079	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3080
3081	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3082	/* Add a reference to the first page only. */
3083	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3084
3085	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3086	return VINF_SUCCESS;
3087	}
3088	}
3089	}
3090	# endif /* HC_ARCH_BITS == 64 */
3091
3092	GSTPDE PdeSrc;
3093	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3094	PdeSrc.n.u1Present = 1;
3095	PdeSrc.n.u1Write = 1;
3096	PdeSrc.n.u1Accessed = 1;
3097	PdeSrc.n.u1User = 1;
3098
3099	/*
3100	* Allocate & map the page table.
3101	*/
3102	PSHWPT pPTDst;
3103	PPGMPOOLPAGE pShwPage;
3104	RTGCPHYS GCPhys;
3105
3106	/* Virtual address = physical address */
3107	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3108	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3109
3110	if ( rc == VINF_SUCCESS
3111	\|\| rc == VINF_PGM_CACHED_PAGE)
3112	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3113	else
3114	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3115
3116	PdeDst.u &= X86_PDE_AVL_MASK;
3117	PdeDst.u \|= pShwPage->Core.Key;
3118	PdeDst.n.u1Present = 1;
3119	PdeDst.n.u1Write = 1;
3120	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3121	PdeDst.n.u1Execute = 1;
3122	# else
3123	PdeDst.n.u1User = 1;
3124	PdeDst.n.u1Accessed = 1;
3125	# endif
3126	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3127
3128	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3129	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3130	return rc;
3131
3132	#else
3133	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3134	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3135	return VERR_INTERNAL_ERROR;
3136	#endif
3137	}
3138
3139
3140
3141	/**
3142	* Prefetch a page/set of pages.
3143	*
3144	* Typically used to sync commonly used pages before entering raw mode
3145	* after a CR3 reload.
3146	*
3147	* @returns VBox status code.
3148	* @param pVCpu The VMCPU handle.
3149	* @param GCPtrPage Page to invalidate.
3150	*/
3151	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3152	{
3153	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3154	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3155	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3156	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3157	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3158	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3159	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3160
3161	/*
3162	* Check that all Guest levels thru the PDE are present, getting the
3163	* PD and PDE in the processes.
3164	*/
3165	int rc = VINF_SUCCESS;
3166	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3167	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3168	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3169	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3170	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3171	unsigned iPDSrc;
3172	X86PDPE PdpeSrc;
3173	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3174	if (!pPDSrc)
3175	return VINF_SUCCESS; /* not present */
3176	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3177	unsigned iPDSrc;
3178	PX86PML4E pPml4eSrc;
3179	X86PDPE PdpeSrc;
3180	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3181	if (!pPDSrc)
3182	return VINF_SUCCESS; /* not present */
3183	# endif
3184	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3185	# else
3186	PGSTPD pPDSrc = NULL;
3187	const unsigned iPDSrc = 0;
3188	GSTPDE PdeSrc;
3189
3190	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3191	PdeSrc.n.u1Present = 1;
3192	PdeSrc.n.u1Write = 1;
3193	PdeSrc.n.u1Accessed = 1;
3194	PdeSrc.n.u1User = 1;
3195	# endif
3196
3197	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3198	{
3199	PVM pVM = pVCpu->CTX_SUFF(pVM);
3200	pgmLock(pVM);
3201
3202	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3203	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3204	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3205	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3206	PX86PDPAE pPDDst;
3207	X86PDEPAE PdeDst;
3208	# if PGM_GST_TYPE != PGM_TYPE_PAE
3209	X86PDPE PdpeSrc;
3210
3211	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3212	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3213	# endif
3214	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3215	if (rc != VINF_SUCCESS)
3216	{
3217	pgmUnlock(pVM);
3218	AssertRC(rc);
3219	return rc;
3220	}
3221	Assert(pPDDst);
3222	PdeDst = pPDDst->a[iPDDst];
3223
3224	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3225	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3226	PX86PDPAE pPDDst;
3227	X86PDEPAE PdeDst;
3228
3229	# if PGM_GST_TYPE == PGM_TYPE_PROT
3230	/* AMD-V nested paging */
3231	X86PML4E Pml4eSrc;
3232	X86PDPE PdpeSrc;
3233	PX86PML4E pPml4eSrc = &Pml4eSrc;
3234
3235	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3236	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3237	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3238	# endif
3239
3240	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3241	if (rc != VINF_SUCCESS)
3242	{
3243	pgmUnlock(pVM);
3244	AssertRC(rc);
3245	return rc;
3246	}
3247	Assert(pPDDst);
3248	PdeDst = pPDDst->a[iPDDst];
3249	# endif
3250	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3251	{
3252	if (!PdeDst.n.u1Present)
3253	{
3254	/** @todo r=bird: This guy will set the A bit on the PDE,
3255	* probably harmless. */
3256	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3257	}
3258	else
3259	{
3260	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3261	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3262	* makes no sense to prefetch more than one page.
3263	*/
3264	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3265	if (RT_SUCCESS(rc))
3266	rc = VINF_SUCCESS;
3267	}
3268	}
3269	pgmUnlock(pVM);
3270	}
3271	return rc;
3272
3273	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3274	return VINF_SUCCESS; /* ignore */
3275	#else
3276	AssertCompile(0);
3277	#endif
3278	}
3279
3280
3281
3282
3283	/**
3284	* Syncs a page during a PGMVerifyAccess() call.
3285	*
3286	* @returns VBox status code (informational included).
3287	* @param pVCpu The VMCPU handle.
3288	* @param GCPtrPage The address of the page to sync.
3289	* @param fPage The effective guest page flags.
3290	* @param uErr The trap error code.
3291	* @remarks This will normally never be called on invalid guest page
3292	* translation entries.
3293	*/
3294	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3295	{
3296	PVM pVM = pVCpu->CTX_SUFF(pVM);
3297
3298	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3299
3300	Assert(!pVM->pgm.s.fNestedPaging);
3301	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3302	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3303	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3304	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3305	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3306	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3307	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3308
3309	# ifndef IN_RING0
3310	if (!(fPage & X86_PTE_US))
3311	{
3312	/*
3313	* Mark this page as safe.
3314	*/
3315	/** @todo not correct for pages that contain both code and data!! */
3316	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3317	CSAMMarkPage(pVM, GCPtrPage, true);
3318	}
3319	# endif
3320
3321	/*
3322	* Get guest PD and index.
3323	*/
3324	/** @todo Performance: We've done all this a jiffy ago in the
3325	* PGMGstGetPage call. */
3326	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3327	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3328	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3329	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3330
3331	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3332	unsigned iPDSrc = 0;
3333	X86PDPE PdpeSrc;
3334	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3335	if (RT_UNLIKELY(!pPDSrc))
3336	{
3337	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3338	return VINF_EM_RAW_GUEST_TRAP;
3339	}
3340
3341	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3342	unsigned iPDSrc = 0; /* shut up gcc */
3343	PX86PML4E pPml4eSrc = NULL; /* ditto */
3344	X86PDPE PdpeSrc;
3345	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3346	if (RT_UNLIKELY(!pPDSrc))
3347	{
3348	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3349	return VINF_EM_RAW_GUEST_TRAP;
3350	}
3351	# endif
3352
3353	# else /* !PGM_WITH_PAGING */
3354	PGSTPD pPDSrc = NULL;
3355	const unsigned iPDSrc = 0;
3356	# endif /* !PGM_WITH_PAGING */
3357	int rc = VINF_SUCCESS;
3358
3359	pgmLock(pVM);
3360
3361	/*
3362	* First check if the shadow pd is present.
3363	*/
3364	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3365	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3366
3367	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3368	PX86PDEPAE pPdeDst;
3369	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3370	PX86PDPAE pPDDst;
3371	# if PGM_GST_TYPE != PGM_TYPE_PAE
3372	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3373	X86PDPE PdpeSrc;
3374	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3375	# endif
3376	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3377	if (rc != VINF_SUCCESS)
3378	{
3379	pgmUnlock(pVM);
3380	AssertRC(rc);
3381	return rc;
3382	}
3383	Assert(pPDDst);
3384	pPdeDst = &pPDDst->a[iPDDst];
3385
3386	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3387	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3388	PX86PDPAE pPDDst;
3389	PX86PDEPAE pPdeDst;
3390
3391	# if PGM_GST_TYPE == PGM_TYPE_PROT
3392	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3393	X86PML4E Pml4eSrc;
3394	X86PDPE PdpeSrc;
3395	PX86PML4E pPml4eSrc = &Pml4eSrc;
3396	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3397	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3398	# endif
3399
3400	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3401	if (rc != VINF_SUCCESS)
3402	{
3403	pgmUnlock(pVM);
3404	AssertRC(rc);
3405	return rc;
3406	}
3407	Assert(pPDDst);
3408	pPdeDst = &pPDDst->a[iPDDst];
3409	# endif
3410
3411	if (!pPdeDst->n.u1Present)
3412	{
3413	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3414	if (rc != VINF_SUCCESS)
3415	{
3416	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3417	pgmUnlock(pVM);
3418	AssertRC(rc);
3419	return rc;
3420	}
3421	}
3422
3423	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3424	/* Check for dirty bit fault */
3425	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3426	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3427	Log(("PGMVerifyAccess: success (dirty)\n"));
3428	else
3429	# endif
3430	{
3431	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3432	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3433	# else
3434	GSTPDE PdeSrc;
3435	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3436	PdeSrc.n.u1Present = 1;
3437	PdeSrc.n.u1Write = 1;
3438	PdeSrc.n.u1Accessed = 1;
3439	PdeSrc.n.u1User = 1;
3440	# endif
3441
3442	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3443	if (uErr & X86_TRAP_PF_US)
3444	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3445	else /* supervisor */
3446	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3447
3448	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3449	if (RT_SUCCESS(rc))
3450	{
3451	/* Page was successfully synced */
3452	Log2(("PGMVerifyAccess: success (sync)\n"));
3453	rc = VINF_SUCCESS;
3454	}
3455	else
3456	{
3457	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3458	rc = VINF_EM_RAW_GUEST_TRAP;
3459	}
3460	}
3461	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3462	pgmUnlock(pVM);
3463	return rc;
3464
3465	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3466
3467	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3468	return VERR_INTERNAL_ERROR;
3469	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3470	}
3471
3472
3473	/**
3474	* Syncs the paging hierarchy starting at CR3.
3475	*
3476	* @returns VBox status code, no specials.
3477	* @param pVCpu The VMCPU handle.
3478	* @param cr0 Guest context CR0 register
3479	* @param cr3 Guest context CR3 register
3480	* @param cr4 Guest context CR4 register
3481	* @param fGlobal Including global page directories or not
3482	*/
3483	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3484	{
3485	PVM pVM = pVCpu->CTX_SUFF(pVM);
3486
3487	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3488
3489	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3490
3491	pgmLock(pVM);
3492
3493	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3494	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3495	if (pPool->cDirtyPages)
3496	pgmPoolResetDirtyPages(pVM);
3497	# endif
3498
3499	/*
3500	* Update page access handlers.
3501	* The virtual are always flushed, while the physical are only on demand.
3502	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3503	* have to look into that later because it will have a bad influence on the performance.
3504	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3505	* bird: Yes, but that won't work for aliases.
3506	*/
3507	/** @todo this MUST go away. See #1557. */
3508	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3509	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3510	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3511	pgmUnlock(pVM);
3512	#endif /* !NESTED && !EPT */
3513
3514	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3515	/*
3516	* Nested / EPT - almost no work.
3517	*/
3518	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3519	return VINF_SUCCESS;
3520
3521	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3522	/*
3523	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3524	* out the shadow parts when the guest modifies its tables.
3525	*/
3526	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3527	return VINF_SUCCESS;
3528
3529	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3530
3531	# ifndef PGM_WITHOUT_MAPPINGS
3532	/*
3533	* Check for and resolve conflicts with our guest mappings if they
3534	* are enabled and not fixed.
3535	*/
3536	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3537	{
3538	int rc = pgmMapResolveConflicts(pVM);
3539	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3540	if (rc == VINF_PGM_SYNC_CR3)
3541	{
3542	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3543	return VINF_PGM_SYNC_CR3;
3544	}
3545	}
3546	# else
3547	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3548	# endif
3549	return VINF_SUCCESS;
3550	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3551	}
3552
3553
3554
3555
3556	#ifdef VBOX_STRICT
3557	#ifdef IN_RC
3558	# undef AssertMsgFailed
3559	# define AssertMsgFailed Log
3560	#endif
3561	#ifdef IN_RING3
3562	# include <VBox/dbgf.h>
3563
3564	/**
3565	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3566	*
3567	* @returns VBox status code (VINF_SUCCESS).
3568	* @param cr3 The root of the hierarchy.
3569	* @param crr The cr4, only PAE and PSE is currently used.
3570	* @param fLongMode Set if long mode, false if not long mode.
3571	* @param cMaxDepth Number of levels to dump.
3572	* @param pHlp Pointer to the output functions.
3573	*/
3574	RT_C_DECLS_BEGIN
3575	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3576	RT_C_DECLS_END
3577
3578	#endif
3579
3580	/**
3581	* Checks that the shadow page table is in sync with the guest one.
3582	*
3583	* @returns The number of errors.
3584	* @param pVM The virtual machine.
3585	* @param pVCpu The VMCPU handle.
3586	* @param cr3 Guest context CR3 register
3587	* @param cr4 Guest context CR4 register
3588	* @param GCPtr Where to start. Defaults to 0.
3589	* @param cb How much to check. Defaults to everything.
3590	*/
3591	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3592	{
3593	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3594	return 0;
3595	#else
3596	unsigned cErrors = 0;
3597	PVM pVM = pVCpu->CTX_SUFF(pVM);
3598	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3599
3600	#if PGM_GST_TYPE == PGM_TYPE_PAE
3601	/** @todo currently broken; crashes below somewhere */
3602	AssertFailed();
3603	#endif
3604
3605	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3606	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3607	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3608
3609	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3610	PPGMCPU pPGM = &pVCpu->pgm.s;
3611	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3612	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3613	# ifndef IN_RING0
3614	RTHCPHYS HCPhys; /* general usage. */
3615	# endif
3616	int rc;
3617
3618	/*
3619	* Check that the Guest CR3 and all its mappings are correct.
3620	*/
3621	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3622	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3623	false);
3624	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3625	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3626	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3627	# else
3628	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3629	# endif
3630	AssertRCReturn(rc, 1);
3631	HCPhys = NIL_RTHCPHYS;
3632	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3633	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3634	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3635	pgmGstGet32bitPDPtr(pVCpu);
3636	RTGCPHYS GCPhys;
3637	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3638	AssertRCReturn(rc, 1);
3639	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3640	# endif
3641	# endif /* !IN_RING0 */
3642
3643	/*
3644	* Get and check the Shadow CR3.
3645	*/
3646	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3647	unsigned cPDEs = X86_PG_ENTRIES;
3648	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3649	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3650	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3651	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3652	# else
3653	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3654	# endif
3655	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3656	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3657	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3658	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3659	# endif
3660	if (cb != ~(RTGCPTR)0)
3661	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3662
3663	/** @todo call the other two PGMAssert() functions. /
3664
3665	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3666	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3667
3668	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3669	{
3670	PPGMPOOLPAGE pShwPdpt = NULL;
3671	PX86PML4E pPml4eSrc;
3672	PX86PML4E pPml4eDst;
3673	RTGCPHYS GCPhysPdptSrc;
3674
3675	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3676	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3677
3678	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3679	if (!pPml4eDst->n.u1Present)
3680	{
3681	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3682	continue;
3683	}
3684
3685	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3686	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK_FULL;
3687
3688	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3689	{
3690	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3691	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3692	cErrors++;
3693	continue;
3694	}
3695
3696	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3697	{
3698	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3699	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3700	cErrors++;
3701	continue;
3702	}
3703
3704	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3705	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3706	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3707	{
3708	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3709	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3710	cErrors++;
3711	continue;
3712	}
3713	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3714	{
3715	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3716
3717	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3718	/*
3719	* Check the PDPTEs too.
3720	*/
3721	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3722
3723	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3724	{
3725	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3726	PPGMPOOLPAGE pShwPde = NULL;
3727	PX86PDPE pPdpeDst;
3728	RTGCPHYS GCPhysPdeSrc;
3729	# if PGM_GST_TYPE == PGM_TYPE_PAE
3730	X86PDPE PdpeSrc;
3731	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3732	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3733	# else
3734	PX86PML4E pPml4eSrcIgn;
3735	X86PDPE PdpeSrc;
3736	PX86PDPT pPdptDst;
3737	PX86PDPAE pPDDst;
3738	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3739
3740	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3741	if (rc != VINF_SUCCESS)
3742	{
3743	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3744	GCPtr += 512 * _2M;
3745	continue; /* next PDPTE */
3746	}
3747	Assert(pPDDst);
3748	# endif
3749	Assert(iPDSrc == 0);
3750
3751	pPdpeDst = &pPdptDst->a[iPdpt];
3752
3753	if (!pPdpeDst->n.u1Present)
3754	{
3755	GCPtr += 512 * _2M;
3756	continue; /* next PDPTE */
3757	}
3758
3759	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3760	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3761
3762	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3763	{
3764	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3765	GCPtr += 512 * _2M;
3766	cErrors++;
3767	continue;
3768	}
3769
3770	if (GCPhysPdeSrc != pShwPde->GCPhys)
3771	{
3772	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3773	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3774	# else
3775	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3776	# endif
3777	GCPtr += 512 * _2M;
3778	cErrors++;
3779	continue;
3780	}
3781
3782	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3783	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3784	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3785	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3786	{
3787	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3788	GCPtr += 512 * _2M;
3789	cErrors++;
3790	continue;
3791	}
3792	# endif
3793
3794	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3795	{
3796	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3797	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3798	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3799	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3800	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3801	# endif
3802	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3803	/*
3804	* Iterate the shadow page directory.
3805	*/
3806	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3807	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3808
3809	for (;
3810	iPDDst < cPDEs;
3811	iPDDst++, GCPtr += cIncrement)
3812	{
3813	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3814	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3815	# else
3816	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3817	# endif
3818	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3819	{
3820	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3821	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3822	{
3823	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3824	cErrors++;
3825	continue;
3826	}
3827	}
3828	else if ( (PdeDst.u & X86_PDE_P)
3829	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3830	)
3831	{
3832	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3833	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3834	if (!pPoolPage)
3835	{
3836	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3837	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3838	cErrors++;
3839	continue;
3840	}
3841	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3842
3843	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3844	{
3845	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3846	GCPtr, (uint64_t)PdeDst.u));
3847	cErrors++;
3848	}
3849
3850	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3851	{
3852	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3853	GCPtr, (uint64_t)PdeDst.u));
3854	cErrors++;
3855	}
3856
3857	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3858	if (!PdeSrc.n.u1Present)
3859	{
3860	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3861	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3862	cErrors++;
3863	continue;
3864	}
3865
3866	if ( !PdeSrc.b.u1Size
3867	\|\| !fBigPagesSupported)
3868	{
3869	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3870	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3871	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3872	# endif
3873	}
3874	else
3875	{
3876	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3877	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3878	{
3879	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3880	GCPtr, (uint64_t)PdeSrc.u));
3881	cErrors++;
3882	continue;
3883	}
3884	# endif
3885	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3886	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3887	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3888	# endif
3889	}
3890
3891	if ( pPoolPage->enmKind
3892	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3893	{
3894	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3895	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3896	cErrors++;
3897	}
3898
3899	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3900	if (!pPhysPage)
3901	{
3902	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3903	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3904	cErrors++;
3905	continue;
3906	}
3907
3908	if (GCPhysGst != pPoolPage->GCPhys)
3909	{
3910	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3911	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3912	cErrors++;
3913	continue;
3914	}
3915
3916	if ( !PdeSrc.b.u1Size
3917	\|\| !fBigPagesSupported)
3918	{
3919	/*
3920	* Page Table.
3921	*/
3922	const GSTPT *pPTSrc;
3923	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3924	if (RT_FAILURE(rc))
3925	{
3926	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3927	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3928	cErrors++;
3929	continue;
3930	}
3931	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3932	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3933	{
3934	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3935	// (This problem will go away when/if we shadow multiple CR3s.)
3936	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3937	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3938	cErrors++;
3939	continue;
3940	}
3941	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3942	{
3943	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3944	GCPtr, (uint64_t)PdeDst.u));
3945	cErrors++;
3946	continue;
3947	}
3948
3949	/* iterate the page table. */
3950	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3951	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3952	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3953	# else
3954	const unsigned offPTSrc = 0;
3955	# endif
3956	for (unsigned iPT = 0, off = 0;
3957	iPT < RT_ELEMENTS(pPTDst->a);
3958	iPT++, off += PAGE_SIZE)
3959	{
3960	const SHWPTE PteDst = pPTDst->a[iPT];
3961
3962	/* skip not-present and dirty tracked entries. */
3963	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3964	continue;
3965	Assert(SHW_PTE_IS_P(PteDst));
3966
3967	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3968	if (!PteSrc.n.u1Present)
3969	{
3970	# ifdef IN_RING3
3971	PGMAssertHandlerAndFlagsInSync(pVM);
3972	PGMR3DumpHierarchyGC(pVM, cr3, cr4, GST_GET_PDE_GCPHYS(PdeSrc));
3973	# endif
3974	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3975	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3976	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3977	cErrors++;
3978	continue;
3979	}
3980
3981	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3982	# if 1 /** @todo sync accessed bit properly... */
3983	fIgnoreFlags \|= X86_PTE_A;
3984	# endif
3985
3986	/* match the physical addresses */
3987	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3988	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3989
3990	# ifdef IN_RING3
3991	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3992	if (RT_FAILURE(rc))
3993	{
3994	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3995	{
3996	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3997	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3998	cErrors++;
3999	continue;
4000	}
4001	}
4002	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4003	{
4004	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4005	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4006	cErrors++;
4007	continue;
4008	}
4009	# endif
4010
4011	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4012	if (!pPhysPage)
4013	{
4014	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4015	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4016	{
4017	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4018	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4019	cErrors++;
4020	continue;
4021	}
4022	# endif
4023	if (SHW_PTE_IS_RW(PteDst))
4024	{
4025	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4026	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4027	cErrors++;
4028	}
4029	fIgnoreFlags \|= X86_PTE_RW;
4030	}
4031	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4032	{
4033	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4034	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4035	cErrors++;
4036	continue;
4037	}
4038
4039	/* flags */
4040	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4041	{
4042	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4043	{
4044	if (SHW_PTE_IS_RW(PteDst))
4045	{
4046	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4047	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4048	cErrors++;
4049	continue;
4050	}
4051	fIgnoreFlags \|= X86_PTE_RW;
4052	}
4053	else
4054	{
4055	if ( SHW_PTE_IS_P(PteDst)
4056	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4057	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4058	# endif
4059	)
4060	{
4061	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4062	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4063	cErrors++;
4064	continue;
4065	}
4066	fIgnoreFlags \|= X86_PTE_P;
4067	}
4068	}
4069	else
4070	{
4071	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4072	{
4073	if (SHW_PTE_IS_RW(PteDst))
4074	{
4075	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4076	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4077	cErrors++;
4078	continue;
4079	}
4080	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4081	{
4082	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4083	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4084	cErrors++;
4085	continue;
4086	}
4087	if (SHW_PTE_IS_D(PteDst))
4088	{
4089	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4090	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4091	cErrors++;
4092	}
4093	# if 0 /** @todo sync access bit properly... */
4094	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4095	{
4096	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4097	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4098	cErrors++;
4099	}
4100	fIgnoreFlags \|= X86_PTE_RW;
4101	# else
4102	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4103	# endif
4104	}
4105	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4106	{
4107	/* access bit emulation (not implemented). */
4108	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4109	{
4110	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4111	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4112	cErrors++;
4113	continue;
4114	}
4115	if (!SHW_PTE_IS_A(PteDst))
4116	{
4117	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4118	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4119	cErrors++;
4120	}
4121	fIgnoreFlags \|= X86_PTE_P;
4122	}
4123	# ifdef DEBUG_sandervl
4124	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4125	# endif
4126	}
4127
4128	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4129	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4130	)
4131	{
4132	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4133	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4134	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4135	cErrors++;
4136	continue;
4137	}
4138	} /* foreach PTE */
4139	}
4140	else
4141	{
4142	/*
4143	* Big Page.
4144	*/
4145	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4146	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4147	{
4148	if (PdeDst.n.u1Write)
4149	{
4150	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4151	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4152	cErrors++;
4153	continue;
4154	}
4155	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4156	{
4157	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4158	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4159	cErrors++;
4160	continue;
4161	}
4162	# if 0 /** @todo sync access bit properly... */
4163	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4164	{
4165	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4166	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4167	cErrors++;
4168	}
4169	fIgnoreFlags \|= X86_PTE_RW;
4170	# else
4171	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4172	# endif
4173	}
4174	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4175	{
4176	/* access bit emulation (not implemented). */
4177	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4178	{
4179	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4180	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4181	cErrors++;
4182	continue;
4183	}
4184	if (!PdeDst.n.u1Accessed)
4185	{
4186	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4187	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4188	cErrors++;
4189	}
4190	fIgnoreFlags \|= X86_PTE_P;
4191	}
4192
4193	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4194	{
4195	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4196	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4197	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4198	cErrors++;
4199	}
4200
4201	/* iterate the page table. */
4202	for (unsigned iPT = 0, off = 0;
4203	iPT < RT_ELEMENTS(pPTDst->a);
4204	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4205	{
4206	const SHWPTE PteDst = pPTDst->a[iPT];
4207
4208	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4209	{
4210	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4211	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4212	cErrors++;
4213	}
4214
4215	/* skip not-present entries. */
4216	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4217	continue;
4218
4219	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4220
4221	/* match the physical addresses */
4222	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4223
4224	# ifdef IN_RING3
4225	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4226	if (RT_FAILURE(rc))
4227	{
4228	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4229	{
4230	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4232	cErrors++;
4233	}
4234	}
4235	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4236	{
4237	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4238	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4239	cErrors++;
4240	continue;
4241	}
4242	# endif
4243	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4244	if (!pPhysPage)
4245	{
4246	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4247	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4248	{
4249	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4250	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4251	cErrors++;
4252	continue;
4253	}
4254	# endif
4255	if (SHW_PTE_IS_RW(PteDst))
4256	{
4257	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4258	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4259	cErrors++;
4260	}
4261	fIgnoreFlags \|= X86_PTE_RW;
4262	}
4263	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4264	{
4265	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4266	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4267	cErrors++;
4268	continue;
4269	}
4270
4271	/* flags */
4272	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4273	{
4274	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4275	{
4276	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4277	{
4278	if (SHW_PTE_IS_RW(PteDst))
4279	{
4280	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4281	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4282	cErrors++;
4283	continue;
4284	}
4285	fIgnoreFlags \|= X86_PTE_RW;
4286	}
4287	}
4288	else
4289	{
4290	if ( SHW_PTE_IS_P(PteDst)
4291	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4292	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4293	# endif
4294	)
4295	{
4296	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4297	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4298	cErrors++;
4299	continue;
4300	}
4301	fIgnoreFlags \|= X86_PTE_P;
4302	}
4303	}
4304
4305	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4306	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4307	)
4308	{
4309	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4310	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4311	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4312	cErrors++;
4313	continue;
4314	}
4315	} /* for each PTE */
4316	}
4317	}
4318	/* not present */
4319
4320	} /* for each PDE */
4321
4322	} /* for each PDPTE */
4323
4324	} /* for each PML4E */
4325
4326	# ifdef DEBUG
4327	if (cErrors)
4328	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4329	# endif
4330
4331	#endif /* GST == 32BIT, PAE or AMD64 */
4332	return cErrors;
4333
4334	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4335	}
4336	#endif /* VBOX_STRICT */
4337
4338
4339	/**
4340	* Sets up the CR3 for shadow paging
4341	*
4342	* @returns Strict VBox status code.
4343	* @retval VINF_SUCCESS.
4344	*
4345	* @param pVCpu The VMCPU handle.
4346	* @param GCPhysCR3 The physical address in the CR3 register.
4347	*/
4348	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4349	{
4350	PVM pVM = pVCpu->CTX_SUFF(pVM);
4351
4352	/* Update guest paging info. */
4353	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4354	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4355	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4356
4357	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4358
4359	/*
4360	* Map the page CR3 points at.
4361	*/
4362	RTHCPTR HCPtrGuestCR3;
4363	RTHCPHYS HCPhysGuestCR3;
4364	pgmLock(pVM);
4365	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4366	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4367	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4368	/** @todo this needs some reworking wrt. locking? */
4369	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4370	HCPtrGuestCR3 = NIL_RTHCPTR;
4371	int rc = VINF_SUCCESS;
4372	# else
4373	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4374	# endif
4375	pgmUnlock(pVM);
4376	if (RT_SUCCESS(rc))
4377	{
4378	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4379	if (RT_SUCCESS(rc))
4380	{
4381	# ifdef IN_RC
4382	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4383	# endif
4384	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4385	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4386	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4387	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4388	# endif
4389	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4390
4391	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4392	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4393	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4394	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4395	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4396	# endif
4397	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4398	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4399
4400	/*
4401	* Map the 4 PDs too.
4402	*/
4403	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4404	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4405	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4406	{
4407	if (pGuestPDPT->a[i].n.u1Present)
4408	{
4409	RTHCPTR HCPtr;
4410	RTHCPHYS HCPhys;
4411	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4412	pgmLock(pVM);
4413	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4414	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4415	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4416	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4417	HCPtr = NIL_RTHCPTR;
4418	int rc2 = VINF_SUCCESS;
4419	# else
4420	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4421	# endif
4422	pgmUnlock(pVM);
4423	if (RT_SUCCESS(rc2))
4424	{
4425	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4426	AssertRCReturn(rc, rc);
4427
4428	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4429	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4430	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4431	# endif
4432	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4433	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4434	# ifdef IN_RC
4435	PGM_INVL_PG(pVCpu, GCPtr);
4436	# endif
4437	continue;
4438	}
4439	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4440	}
4441
4442	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4443	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4444	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4445	# endif
4446	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4447	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4448	# ifdef IN_RC
4449	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4450	# endif
4451	}
4452
4453	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4454	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4455	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4456	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4457	# endif
4458	# endif
4459	}
4460	else
4461	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4462	}
4463	else
4464	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4465
4466	#else /* prot/real stub */
4467	int rc = VINF_SUCCESS;
4468	#endif
4469
4470	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4471	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4472	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4473	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4474	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4475	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4476
4477	Assert(!pVM->pgm.s.fNestedPaging);
4478
4479	/*
4480	* Update the shadow root page as well since that's not fixed.
4481	*/
4482	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4483	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4484	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4485	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4486	PPGMPOOLPAGE pNewShwPageCR3;
4487
4488	pgmLock(pVM);
4489
4490	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4491	if (pPool->cDirtyPages)
4492	pgmPoolResetDirtyPages(pVM);
4493	# endif
4494
4495	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4496	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pNewShwPageCR3, true /* lock page */);
4497	AssertFatalRC(rc);
4498	rc = VINF_SUCCESS;
4499
4500	# ifdef IN_RC
4501	/*
4502	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4503	* state will be inconsistent! Flush important things now while
4504	* we still can and then make sure there are no ring-3 calls.
4505	*/
4506	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4507	VMMRZCallRing3Disable(pVCpu);
4508	# endif
4509
4510	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4511	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4512	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4513	# ifdef IN_RING0
4514	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4515	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4516	# elif defined(IN_RC)
4517	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4518	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4519	# else
4520	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4521	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4522	# endif
4523
4524	# ifndef PGM_WITHOUT_MAPPINGS
4525	/*
4526	* Apply all hypervisor mappings to the new CR3.
4527	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4528	* make sure we check for conflicts in the new CR3 root.
4529	*/
4530	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4531	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4532	# endif
4533	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4534	AssertRCReturn(rc, rc);
4535	# endif
4536
4537	/* Set the current hypervisor CR3. */
4538	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4539	SELMShadowCR3Changed(pVM, pVCpu);
4540
4541	# ifdef IN_RC
4542	/* NOTE: The state is consistent again. */
4543	VMMRZCallRing3Enable(pVCpu);
4544	# endif
4545
4546	/* Clean up the old CR3 root. */
4547	if ( pOldShwPageCR3
4548	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4549	{
4550	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4551	# ifndef PGM_WITHOUT_MAPPINGS
4552	/* Remove the hypervisor mappings from the shadow page table. */
4553	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4554	# endif
4555	/* Mark the page as unlocked; allow flushing again. */
4556	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4557
4558	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4559	}
4560	pgmUnlock(pVM);
4561	# endif
4562
4563	return rc;
4564	}
4565
4566	/**
4567	* Unmaps the shadow CR3.
4568	*
4569	* @returns VBox status, no specials.
4570	* @param pVCpu The VMCPU handle.
4571	*/
4572	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4573	{
4574	LogFlow(("UnmapCR3\n"));
4575
4576	int rc = VINF_SUCCESS;
4577	PVM pVM = pVCpu->CTX_SUFF(pVM);
4578
4579	/*
4580	* Update guest paging info.
4581	*/
4582	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4583	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4584	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4585	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4586	# endif
4587	pVCpu->pgm.s.pGst32BitPdRC = 0;
4588
4589	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4590	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4591	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4592	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4593	# endif
4594	pVCpu->pgm.s.pGstPaePdptRC = 0;
4595	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4596	{
4597	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4598	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4599	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4600	# endif
4601	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4602	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4603	}
4604
4605	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4606	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4607	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4608	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4609	# endif
4610
4611	#else /* prot/real mode stub */
4612	/* nothing to do */
4613	#endif
4614
4615	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4616	/*
4617	* Update shadow paging info.
4618	*/
4619	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4620	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4621	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4622
4623	# if PGM_GST_TYPE != PGM_TYPE_REAL
4624	Assert(!pVM->pgm.s.fNestedPaging);
4625	# endif
4626
4627	pgmLock(pVM);
4628
4629	# ifndef PGM_WITHOUT_MAPPINGS
4630	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4631	/* Remove the hypervisor mappings from the shadow page table. */
4632	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4633	# endif
4634
4635	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4636	{
4637	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4638
4639	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4640
4641	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4642	if (pPool->cDirtyPages)
4643	pgmPoolResetDirtyPages(pVM);
4644	# endif
4645
4646	/* Mark the page as unlocked; allow flushing again. */
4647	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4648
4649	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4650	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4651	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4652	pVCpu->pgm.s.pShwPageCR3RC = 0;
4653	pVCpu->pgm.s.iShwUser = 0;
4654	pVCpu->pgm.s.iShwUserTable = 0;
4655	}
4656	pgmUnlock(pVM);
4657	# endif
4658	#endif /* !IN_RC*/
4659
4660	return rc;
4661	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 31849

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