PGMAllBth.h@ 32009

Last change on this file since 32009 was 32009, checked in by vboxsync, 14 years ago
Removed GST_PDPE_PG_MASK and renamed GST_PDPE_PG_MASK_FULL to GST_PDPE_PG_MASK.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 199.2 KB

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1	/* $Id: PGMAllBth.h 32009 2010-08-26 16:41:19Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK_FULL) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK_FULL));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	}
561	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
562
563	/*
564	* Fetch the guest PDE, PDPE and PML4E.
565	*/
566	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
567	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
568	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
569
570	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
571	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
572	PX86PDPAE pPDDst;
573	# if PGM_GST_TYPE == PGM_TYPE_PAE
574	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
575	# else
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
577	# endif
578	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
579
580	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
581	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
582	PX86PDPAE pPDDst;
583	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
584	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
585	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
586	# else
587	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
588	# endif
589	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
590
591	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
592	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
593	PEPTPD pPDDst;
594	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
596	# endif
597	Assert(pPDDst);
598
599	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
600	/*
601	* Dirty page handling.
602	*
603	* If we successfully correct the write protection fault due to dirty bit
604	* tracking, then return immediately.
605	*/
606	if (uErr & X86_TRAP_PF_RW) /* write fault? */
607	{
608	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
609	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
610	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
612	{
613	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
614	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
615	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
616	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
617	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
618	return VINF_SUCCESS;
619	}
620	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
621	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
622	}
623
624	# if 0 /* rarely useful; leave for debugging. */
625	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
626	# endif
627	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
628
629	/*
630	* A common case is the not-present error caused by lazy page table syncing.
631	*
632	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
633	* here so we can safely assume that the shadow PT is present when calling
634	* SyncPage later.
635	*
636	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
637	* of mapping conflict and defer to SyncCR3 in R3.
638	* (Again, we do NOT support access handlers for non-present guest pages.)
639	*
640	*/
641	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
642	Assert(GstWalk.Pde.n.u1Present);
643	# endif
644	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
645	&& !pPDDst->a[iPDDst].n.u1Present)
646	{
647	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
648	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
649	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
650	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
651	# else
652	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
653	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
654	# endif
655	if (RT_SUCCESS(rc))
656	return rc;
657	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
658	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
659	return VINF_PGM_SYNC_CR3;
660	}
661
662	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
663	/*
664	* Check if this address is within any of our mappings.
665	*
666	* This is very fast and it's gonna save us a bit of effort below and prevent
667	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
668	* (BTW, it's impossible to have physical access handlers in a mapping.)
669	*/
670	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
671	{
672	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
673	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
674	{
675	if (pvFault < pMapping->GCPtr)
676	break;
677	if (pvFault - pMapping->GCPtr < pMapping->cb)
678	{
679	/*
680	* The first thing we check is if we've got an undetected conflict.
681	*/
682	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
683	{
684	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
685	while (iPT-- > 0)
686	if (GstWalk.pPde[iPT].n.u1Present)
687	{
688	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
689	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
690	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
691	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
692	return VINF_PGM_SYNC_CR3;
693	}
694	}
695
696	/*
697	* Check if the fault address is in a virtual page access handler range.
698	*/
699	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
700	if ( pCur
701	&& pvFault - pCur->Core.Key < pCur->cb
702	&& uErr & X86_TRAP_PF_RW)
703	{
704	# ifdef IN_RC
705	STAM_PROFILE_START(&pCur->Stat, h);
706	pgmUnlock(pVM);
707	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
708	pgmLock(pVM);
709	STAM_PROFILE_STOP(&pCur->Stat, h);
710	# else
711	AssertFailed();
712	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
713	# endif
714	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
715	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
716	return rc;
717	}
718
719	/*
720	* Pretend we're not here and let the guest handle the trap.
721	*/
722	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
723	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
724	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
725	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
726	return VINF_EM_RAW_GUEST_TRAP;
727	}
728	}
729	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
730	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
731
732	/*
733	* Check if this fault address is flagged for special treatment,
734	* which means we'll have to figure out the physical address and
735	* check flags associated with it.
736	*
737	* ASSUME that we can limit any special access handling to pages
738	* in page tables which the guest believes to be present.
739	*/
740	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
741	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
742	# else
743	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
745	PPGMPAGE pPage;
746	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
747	if (RT_FAILURE(rc))
748	{
749	/*
750	* When the guest accesses invalid physical memory (e.g. probing
751	* of RAM or accessing a remapped MMIO range), then we'll fall
752	* back to the recompiler to emulate the instruction.
753	*/
754	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
755	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
756	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
757	return VINF_EM_RAW_EMULATE_INSTR;
758	}
759
760	/*
761	* Any handlers for this page?
762	*/
763	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
764	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
765	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
766	&GstWalk));
767	# else
768	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
769	# endif
770
771	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
772
773	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
774	if (uErr & X86_TRAP_PF_P)
775	{
776	/*
777	* The page isn't marked, but it might still be monitored by a virtual page access handler.
778	* (ASSUMES no temporary disabling of virtual handlers.)
779	*/
780	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
781	* we should correct both the shadow page table and physical memory flags, and not only check for
782	* accesses within the handler region but for access to pages with virtual handlers. */
783	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
784	if (pCur)
785	{
786	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
787	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
788	\|\| !(uErr & X86_TRAP_PF_P)
789	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
790	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
791
792	if ( pvFault - pCur->Core.Key < pCur->cb
793	&& ( uErr & X86_TRAP_PF_RW
794	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
795	{
796	# ifdef IN_RC
797	STAM_PROFILE_START(&pCur->Stat, h);
798	pgmUnlock(pVM);
799	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
800	pgmLock(pVM);
801	STAM_PROFILE_STOP(&pCur->Stat, h);
802	# else
803	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
804	# endif
805	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
806	return rc;
807	}
808	}
809	}
810	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
811
812	/*
813	* We are here only if page is present in Guest page tables and
814	* trap is not handled by our handlers.
815	*
816	* Check it for page out-of-sync situation.
817	*/
818	if (!(uErr & X86_TRAP_PF_P))
819	{
820	/*
821	* Page is not present in our page tables. Try to sync it!
822	*/
823	if (uErr & X86_TRAP_PF_US)
824	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
825	else /* supervisor */
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
827
828	if (PGM_PAGE_IS_BALLOONED(pPage))
829	{
830	/* Emulate reads from ballooned pages as they are not present in
831	our shadow page tables. (Required for e.g. Solaris guests; soft
832	ecc, random nr generator.) */
833	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
834	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
835	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
836	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
837	return rc;
838	}
839
840	# if defined(LOG_ENABLED) && !defined(IN_RING0)
841	RTGCPHYS GCPhys2;
842	uint64_t fPageGst2;
843	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
844	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
845	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
846	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
847	# else
848	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
849	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
850	# endif
851	# endif /* LOG_ENABLED */
852
853	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
854	if ( !GstWalk.Core.fEffectiveUS
855	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
856	{
857	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
858	if ( pvFault == (RTGCPTR)pRegFrame->eip
859	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
860	# ifdef CSAM_DETECT_NEW_CODE_PAGES
861	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
862	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
863	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
864	)
865	{
866	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
867	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
868	if (rc != VINF_SUCCESS)
869	{
870	/*
871	* CSAM needs to perform a job in ring 3.
872	*
873	* Sync the page before going to the host context; otherwise we'll end up in a loop if
874	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
875	*/
876	LogFlow(("CSAM ring 3 job\n"));
877	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
878	AssertRC(rc2);
879
880	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
881	return rc;
882	}
883	}
884	# ifdef CSAM_DETECT_NEW_CODE_PAGES
885	else if ( uErr == X86_TRAP_PF_RW
886	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
887	&& pRegFrame->ecx < 0x10000)
888	{
889	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
890	* to detect loading of new code pages.
891	*/
892
893	/*
894	* Decode the instruction.
895	*/
896	RTGCPTR PC;
897	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
898	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
899	if (rc == VINF_SUCCESS)
900	{
901	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
902	uint32_t cbOp;
903	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
904
905	/* For now we'll restrict this to rep movsw/d instructions */
906	if ( rc == VINF_SUCCESS
907	&& pDis->pCurInstr->opcode == OP_MOVSWD
908	&& (pDis->prefix & PREFIX_REP))
909	{
910	CSAMMarkPossibleCodePage(pVM, pvFault);
911	}
912	}
913	}
914	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
915
916	/*
917	* Mark this page as safe.
918	*/
919	/** @todo not correct for pages that contain both code and data!! */
920	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
921	CSAMMarkPage(pVM, pvFault, true);
922	}
923	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
924	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
925	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
926	# else
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# endif
929	if (RT_SUCCESS(rc))
930	{
931	/* The page was successfully synced, return to the guest. */
932	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
933	return VINF_SUCCESS;
934	}
935	}
936	else /* uErr & X86_TRAP_PF_P: */
937	{
938	/*
939	* Write protected pages are made writable when the guest makes the
940	* first write to it. This happens for pages that are shared, write
941	* monitored or not yet allocated.
942	*
943	* We may also end up here when CR0.WP=0 in the guest.
944	*
945	* Also, a side effect of not flushing global PDEs are out of sync
946	* pages due to physical monitored regions, that are no longer valid.
947	* Assume for now it only applies to the read/write flag.
948	*/
949	if (uErr & X86_TRAP_PF_RW)
950	{
951	/*
952	* Check if it is a read-only page.
953	*/
954	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
955	{
956	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
957	Assert(!PGM_PAGE_IS_ZERO(pPage));
958	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
959	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
960
961	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
962	if (rc != VINF_SUCCESS)
963	{
964	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
965	return rc;
966	}
967	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
968	return VINF_EM_NO_MEMORY;
969	}
970
971	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
972	/*
973	* Check to see if we need to emulate the instruction if CR0.WP=0.
974	*/
975	if ( !GstWalk.Core.fEffectiveRW
976	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
977	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
978	{
979	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
980	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
981	if (RT_SUCCESS(rc))
982	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
983	else
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
985	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
986	return rc;
987	}
988	# endif
989	/// @todo count the above case; else
990	if (uErr & X86_TRAP_PF_US)
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
992	else /* supervisor */
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
994
995	/*
996	* Sync the page.
997	*
998	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
999	* page is not present, which is not true in this case.
1000	*/
1001	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1002	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1003	# else
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1005	# endif
1006	if (RT_SUCCESS(rc))
1007	{
1008	/*
1009	* Page was successfully synced, return to guest but invalidate
1010	* the TLB first as the page is very likely to be in it.
1011	*/
1012	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1013	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1014	# else
1015	PGM_INVL_PG(pVCpu, pvFault);
1016	# endif
1017	# ifdef VBOX_STRICT
1018	RTGCPHYS GCPhys2;
1019	uint64_t fPageGst;
1020	if (!pVM->pgm.s.fNestedPaging)
1021	{
1022	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1023	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1024	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1025	}
1026	uint64_t fPageShw;
1027	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1028	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1029	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1030	# endif /* VBOX_STRICT */
1031	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1032	return VINF_SUCCESS;
1033	}
1034	}
1035	/** @todo else: why are we here? */
1036
1037	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1038	/*
1039	* Check for VMM page flags vs. Guest page flags consistency.
1040	* Currently only for debug purposes.
1041	*/
1042	if (RT_SUCCESS(rc))
1043	{
1044	/* Get guest page flags. */
1045	uint64_t fPageGst;
1046	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1047	if (RT_SUCCESS(rc))
1048	{
1049	uint64_t fPageShw;
1050	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1051
1052	/*
1053	* Compare page flags.
1054	* Note: we have AVL, A, D bits desynched.
1055	*/
1056	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1057	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1058	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1059	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1060	}
1061	else
1062	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1063	}
1064	else
1065	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1066	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1067	}
1068
1069
1070	/*
1071	* If we get here it is because something failed above, i.e. most like guru
1072	* meditiation time.
1073	*/
1074	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1075	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1076	return rc;
1077
1078	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1079	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1080	return VERR_INTERNAL_ERROR;
1081	# endif
1082	}
1083	#endif /* !IN_RING3 */
1084
1085
1086	/**
1087	* Emulation of the invlpg instruction.
1088	*
1089	*
1090	* @returns VBox status code.
1091	*
1092	* @param pVCpu The VMCPU handle.
1093	* @param GCPtrPage Page to invalidate.
1094	*
1095	* @remark ASSUMES that the guest is updating before invalidating. This order
1096	* isn't required by the CPU, so this is speculative and could cause
1097	* trouble.
1098	* @remark No TLB shootdown is done on any other VCPU as we assume that
1099	* invlpg emulation is the only reason for calling this function.
1100	* (The guest has to shoot down TLB entries on other CPUs itself)
1101	* Currently true, but keep in mind!
1102	*
1103	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1104	*/
1105	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1106	{
1107	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1108	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1109	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1110	int rc;
1111	PVM pVM = pVCpu->CTX_SUFF(pVM);
1112	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1113
1114	Assert(PGMIsLockOwner(pVM));
1115
1116	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1117
1118	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1119	if (pPool->cDirtyPages)
1120	pgmPoolResetDirtyPages(pVM);
1121	# endif
1122
1123	/*
1124	* Get the shadow PD entry and skip out if this PD isn't present.
1125	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1126	*/
1127	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1128	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1129	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1130
1131	/* Fetch the pgm pool shadow descriptor. */
1132	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1133	Assert(pShwPde);
1134
1135	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1136	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1137	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1138
1139	/* If the shadow PDPE isn't present, then skip the invalidate. */
1140	if (!pPdptDst->a[iPdpt].n.u1Present)
1141	{
1142	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1143	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1144	return VINF_SUCCESS;
1145	}
1146
1147	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1148	PPGMPOOLPAGE pShwPde = NULL;
1149	PX86PDPAE pPDDst;
1150
1151	/* Fetch the pgm pool shadow descriptor. */
1152	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1153	AssertRCSuccessReturn(rc, rc);
1154	Assert(pShwPde);
1155
1156	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1157	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1158
1159	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1160	/* PML4 */
1161	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1162	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1163	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1164	PX86PDPAE pPDDst;
1165	PX86PDPT pPdptDst;
1166	PX86PML4E pPml4eDst;
1167	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1168	if (rc != VINF_SUCCESS)
1169	{
1170	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1171	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1172	return VINF_SUCCESS;
1173	}
1174	Assert(pPDDst);
1175
1176	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1177	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1178
1179	if (!pPdpeDst->n.u1Present)
1180	{
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1182	return VINF_SUCCESS;
1183	}
1184
1185	/* Fetch the pgm pool shadow descriptor. */
1186	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1187	Assert(pShwPde);
1188
1189	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1190
1191	const SHWPDE PdeDst = *pPdeDst;
1192	if (!PdeDst.n.u1Present)
1193	{
1194	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1195	return VINF_SUCCESS;
1196	}
1197
1198	/*
1199	* Get the guest PD entry and calc big page.
1200	*/
1201	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1202	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1203	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1204	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1205	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1206	unsigned iPDSrc = 0;
1207	# if PGM_GST_TYPE == PGM_TYPE_PAE
1208	X86PDPE PdpeSrcIgn;
1209	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1210	# else /* AMD64 */
1211	PX86PML4E pPml4eSrcIgn;
1212	X86PDPE PdpeSrcIgn;
1213	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1214	# endif
1215	GSTPDE PdeSrc;
1216
1217	if (pPDSrc)
1218	PdeSrc = pPDSrc->a[iPDSrc];
1219	else
1220	PdeSrc.u = 0;
1221	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1222	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1223
1224	# ifdef IN_RING3
1225	/*
1226	* If a CR3 Sync is pending we may ignore the invalidate page operation
1227	* depending on the kind of sync and if it's a global page or not.
1228	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1229	*/
1230	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1231	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1232	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1233	&& fIsBigPage
1234	&& PdeSrc.b.u1Global
1235	)
1236	)
1237	# else
1238	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1239	# endif
1240	{
1241	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1242	return VINF_SUCCESS;
1243	}
1244	# endif /* IN_RING3 */
1245
1246	/*
1247	* Deal with the Guest PDE.
1248	*/
1249	rc = VINF_SUCCESS;
1250	if (PdeSrc.n.u1Present)
1251	{
1252	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1253	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1254	# ifndef PGM_WITHOUT_MAPPING
1255	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1256	{
1257	/*
1258	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1259	*/
1260	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1261	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1263	}
1264	else
1265	# endif /* !PGM_WITHOUT_MAPPING */
1266	if (!fIsBigPage)
1267	{
1268	/*
1269	* 4KB - page.
1270	*/
1271	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1272	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1273
1274	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1275	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1276	if (pShwPage->cModifications)
1277	pShwPage->cModifications = 1;
1278	# endif
1279
1280	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1281	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1282	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1283	# endif
1284	if (pShwPage->GCPhys == GCPhys)
1285	{
1286	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1287	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1288	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1289	if (pPT->a[iPTEDst].n.u1Present)
1290	{
1291	/* This is very unlikely with caching/monitoring enabled. */
1292	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1293	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1294	}
1295	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1296	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1297	if (RT_SUCCESS(rc))
1298	rc = VINF_SUCCESS;
1299	# endif
1300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1301	PGM_INVL_PG(pVCpu, GCPtrPage);
1302	}
1303	else
1304	{
1305	/*
1306	* The page table address changed.
1307	*/
1308	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1309	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1310	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1311	ASMAtomicWriteSize(pPdeDst, 0);
1312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1313	PGM_INVL_VCPU_TLBS(pVCpu);
1314	}
1315	}
1316	else
1317	{
1318	/*
1319	* 2/4MB - page.
1320	*/
1321	/* Before freeing the page, check if anything really changed. */
1322	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1323	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1324	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1325	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1326	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1327	# endif
1328	if ( pShwPage->GCPhys == GCPhys
1329	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1330	{
1331	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1332	/** @todo This test is wrong as it cannot check the G bit!
1333	* FIXME */
1334	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1335	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1336	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1337	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1338	{
1339	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1340	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1341	return VINF_SUCCESS;
1342	}
1343	}
1344
1345	/*
1346	* Ok, the page table is present and it's been changed in the guest.
1347	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1348	* We could do this for some flushes in GC too, but we need an algorithm for
1349	* deciding which 4MB pages containing code likely to be executed very soon.
1350	*/
1351	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1352	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1353	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1354	ASMAtomicWriteSize(pPdeDst, 0);
1355	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1356	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1357	}
1358	}
1359	else
1360	{
1361	/*
1362	* Page directory is not present, mark shadow PDE not present.
1363	*/
1364	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1365	{
1366	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1367	ASMAtomicWriteSize(pPdeDst, 0);
1368	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1369	PGM_INVL_PG(pVCpu, GCPtrPage);
1370	}
1371	else
1372	{
1373	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1374	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1375	}
1376	}
1377	return rc;
1378
1379	#else /* guest real and protected mode */
1380	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1381	return VINF_SUCCESS;
1382	#endif
1383	}
1384
1385
1386	/**
1387	* Update the tracking of shadowed pages.
1388	*
1389	* @param pVCpu The VMCPU handle.
1390	* @param pShwPage The shadow page.
1391	* @param HCPhys The physical page we is being dereferenced.
1392	* @param iPte Shadow PTE index
1393	*/
1394	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1395	{
1396	PVM pVM = pVCpu->CTX_SUFF(pVM);
1397
1398	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1399	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1400
1401	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1402	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1403	* 2. write protect all shadowed pages. I.e. implement caching.
1404	*/
1405	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1406
1407	/*
1408	* Find the guest address.
1409	*/
1410	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1411	pRam;
1412	pRam = pRam->CTX_SUFF(pNext))
1413	{
1414	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1415	while (iPage-- > 0)
1416	{
1417	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1418	{
1419	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1420
1421	Assert(pShwPage->cPresent);
1422	Assert(pPool->cPresent);
1423	pShwPage->cPresent--;
1424	pPool->cPresent--;
1425
1426	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1427	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1428	return;
1429	}
1430	}
1431	}
1432
1433	for (;;)
1434	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1435	}
1436
1437
1438	/**
1439	* Update the tracking of shadowed pages.
1440	*
1441	* @param pVCpu The VMCPU handle.
1442	* @param pShwPage The shadow page.
1443	* @param u16 The top 16-bit of the pPage->HCPhys.
1444	* @param pPage Pointer to the guest page. this will be modified.
1445	* @param iPTDst The index into the shadow table.
1446	*/
1447	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1448	{
1449	PVM pVM = pVCpu->CTX_SUFF(pVM);
1450
1451	/*
1452	* Just deal with the simple first time here.
1453	*/
1454	if (!u16)
1455	{
1456	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1457	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1458	/* Save the page table index. */
1459	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1460	}
1461	else
1462	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1463
1464	/* write back */
1465	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1466	PGM_PAGE_SET_TRACKING(pPage, u16);
1467
1468	/* update statistics. */
1469	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1470	pShwPage->cPresent++;
1471	if (pShwPage->iFirstPresent > iPTDst)
1472	pShwPage->iFirstPresent = iPTDst;
1473	}
1474
1475
1476	/**
1477	* Modifies a shadow PTE to account for access handlers.
1478	*
1479	* @param pVM The VM handle.
1480	* @param pPage The page in question.
1481	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1482	* A (accessed) bit so it can be emulated correctly.
1483	* @param pPteDst The shadow PTE (output). This is temporary storage and
1484	* does not need to be set atomically.
1485	*/
1486	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1487	{
1488	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1489	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1490	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1491	{
1492	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1493	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1494	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1495	pPteDst->n.u1Present = 1;
1496	pPteDst->n.u1Execute = 1;
1497	pPteDst->n.u1IgnorePAT = 1;
1498	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1499	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1500	#else
1501	if (fPteSrc & X86_PTE_A)
1502	{
1503	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1504	SHW_PTE_SET_RO(*pPteDst);
1505	}
1506	else
1507	SHW_PTE_SET(*pPteDst, 0);
1508	#endif
1509	}
1510	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1511	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1512	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1513	&& ( BTH_IS_NP_ACTIVE(pVM)
1514	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1515	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1516	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1517	# endif
1518	)
1519	{
1520	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1521	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1522	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1523	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1524	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1525	pPteDst->n.u1Present = 0;
1526	pPteDst->n.u1Write = 1;
1527	pPteDst->n.u1Execute = 0;
1528	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1529	pPteDst->n.u3EMT = 7;
1530	# else
1531	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1532	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1533	# endif
1534	}
1535	# endif
1536	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1537	else
1538	{
1539	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1540	SHW_PTE_SET(*pPteDst, 0);
1541	}
1542	/** @todo count these kinds of entries. */
1543	}
1544
1545
1546	/**
1547	* Creates a 4K shadow page for a guest page.
1548	*
1549	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1550	* physical address. The PdeSrc argument only the flags are used. No page
1551	* structured will be mapped in this function.
1552	*
1553	* @param pVCpu The VMCPU handle.
1554	* @param pPteDst Destination page table entry.
1555	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1556	* Can safely assume that only the flags are being used.
1557	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1558	* @param pShwPage Pointer to the shadow page.
1559	* @param iPTDst The index into the shadow table.
1560	*
1561	* @remark Not used for 2/4MB pages!
1562	*/
1563	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1564	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1565	{
1566	if ( PteSrc.n.u1Present
1567	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1568	{
1569	PVM pVM = pVCpu->CTX_SUFF(pVM);
1570
1571	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1572	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1573	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1574	if (pShwPage->fDirty)
1575	{
1576	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1577	PX86PTPAE pGstPT;
1578
1579	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1580	pGstPT->a[iPTDst].u = PteSrc.u;
1581	}
1582	# endif
1583	/*
1584	* Find the ram range.
1585	*/
1586	PPGMPAGE pPage;
1587	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc), &pPage);
1588	if (RT_SUCCESS(rc))
1589	{
1590	/* Ignore ballooned pages.
1591	Don't return errors or use a fatal assert here as part of a
1592	shadow sync range might included ballooned pages. */
1593	if (PGM_PAGE_IS_BALLOONED(pPage))
1594	{
1595	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1596	return;
1597	}
1598
1599	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1600	/* Make the page writable if necessary. */
1601	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1602	&& ( PGM_PAGE_IS_ZERO(pPage)
1603	\|\| ( PteSrc.n.u1Write
1604	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1605	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1606	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1607	# endif
1608	# ifdef VBOX_WITH_PAGE_SHARING
1609	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1610	# endif
1611	)
1612	)
1613	)
1614	{
1615	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
1616	AssertRC(rc);
1617	}
1618	#endif
1619
1620	/*
1621	* Make page table entry.
1622	*/
1623	SHWPTE PteDst;
1624	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1625	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc), &PteDst);
1626	else
1627	{
1628	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1629	/*
1630	* If the page or page directory entry is not marked accessed,
1631	* we mark the page not present.
1632	*/
1633	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1634	{
1635	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1636	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1637	SHW_PTE_SET(PteDst, 0);
1638	}
1639	/*
1640	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1641	* when the page is modified.
1642	*/
1643	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1644	{
1645	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1646	SHW_PTE_SET(PteDst,
1647	GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc)
1648	\| PGM_PAGE_GET_HCPHYS(pPage)
1649	\| PGM_PTFLAGS_TRACK_DIRTY);
1650	SHW_PTE_SET_RO(PteDst);
1651	}
1652	else
1653	#endif
1654	{
1655	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1656	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1657	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1658	PteDst.n.u1Present = 1;
1659	PteDst.n.u1Write = 1;
1660	PteDst.n.u1Execute = 1;
1661	PteDst.n.u1IgnorePAT = 1;
1662	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1663	/* PteDst.n.u1Size = 0 */
1664	#else
1665	SHW_PTE_SET(PteDst, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1666	#endif
1667	}
1668
1669	/*
1670	* Make sure only allocated pages are mapped writable.
1671	*/
1672	if ( SHW_PTE_IS_P_RW(PteDst)
1673	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1674	{
1675	/* Still applies to shared pages. */
1676	Assert(!PGM_PAGE_IS_ZERO(pPage));
1677	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1678	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)GST_GET_PTE_GCPHYS(PteSrc), pPage, iPTDst));
1679	}
1680	}
1681
1682	/*
1683	* Keep user track up to date.
1684	*/
1685	if (SHW_PTE_IS_P(PteDst))
1686	{
1687	if (!SHW_PTE_IS_P(*pPteDst))
1688	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1689	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1690	{
1691	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1692	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1693	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1694	}
1695	}
1696	else if (SHW_PTE_IS_P(*pPteDst))
1697	{
1698	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1699	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1700	}
1701
1702	/*
1703	* Update statistics and commit the entry.
1704	*/
1705	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1706	if (!PteSrc.n.u1Global)
1707	pShwPage->fSeenNonGlobal = true;
1708	#endif
1709	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1710	return;
1711	}
1712
1713	/** @todo count these three different kinds. */
1714	Log2(("SyncPageWorker: invalid address in Pte\n"));
1715	}
1716	else if (!PteSrc.n.u1Present)
1717	Log2(("SyncPageWorker: page not present in Pte\n"));
1718	else
1719	Log2(("SyncPageWorker: invalid Pte\n"));
1720
1721	/*
1722	* The page is not present or the PTE is bad. Replace the shadow PTE by
1723	* an empty entry, making sure to keep the user tracking up to date.
1724	*/
1725	if (SHW_PTE_IS_P(*pPteDst))
1726	{
1727	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1728	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1729	}
1730	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1731	}
1732
1733
1734	/**
1735	* Syncs a guest OS page.
1736	*
1737	* There are no conflicts at this point, neither is there any need for
1738	* page table allocations.
1739	*
1740	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1741	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1742	*
1743	* @returns VBox status code.
1744	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1745	* @param pVCpu The VMCPU handle.
1746	* @param PdeSrc Page directory entry of the guest.
1747	* @param GCPtrPage Guest context page address.
1748	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1749	* @param uErr Fault error (X86_TRAP_PF_*).
1750	*/
1751	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1752	{
1753	PVM pVM = pVCpu->CTX_SUFF(pVM);
1754	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1755	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1756
1757	Assert(PGMIsLockOwner(pVM));
1758
1759	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1760	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1761	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1762	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1763	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1764
1765	/*
1766	* Assert preconditions.
1767	*/
1768	Assert(PdeSrc.n.u1Present);
1769	Assert(cPages);
1770	# if 0 /* rarely useful; leave for debugging. */
1771	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1772	# endif
1773
1774	/*
1775	* Get the shadow PDE, find the shadow page table in the pool.
1776	*/
1777	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1778	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1779	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1780
1781	/* Fetch the pgm pool shadow descriptor. */
1782	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1783	Assert(pShwPde);
1784
1785	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1786	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1787	PPGMPOOLPAGE pShwPde = NULL;
1788	PX86PDPAE pPDDst;
1789
1790	/* Fetch the pgm pool shadow descriptor. */
1791	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1792	AssertRCSuccessReturn(rc2, rc2);
1793	Assert(pShwPde);
1794
1795	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1796	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1797
1798	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1799	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1800	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1801	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1802	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1803
1804	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1805	AssertRCSuccessReturn(rc2, rc2);
1806	Assert(pPDDst && pPdptDst);
1807	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1808	# endif
1809	SHWPDE PdeDst = *pPdeDst;
1810
1811	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1812	if (!PdeDst.n.u1Present)
1813	{
1814	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1815	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
1816	return VINF_SUCCESS; /* force the instruction to be executed again. */
1817	}
1818
1819	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1820	Assert(pShwPage);
1821
1822	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1823	/* Fetch the pgm pool shadow descriptor. */
1824	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1825	Assert(pShwPde);
1826	# endif
1827
1828	/*
1829	* Check that the page is present and that the shadow PDE isn't out of sync.
1830	*/
1831	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1832	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1833	RTGCPHYS GCPhys;
1834	if (!fBigPage)
1835	{
1836	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1837	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1838	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1839	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1840	# endif
1841	}
1842	else
1843	{
1844	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1845	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1846	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1847	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1848	# endif
1849	}
1850	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1851	if ( fPdeValid
1852	&& pShwPage->GCPhys == GCPhys
1853	&& PdeSrc.n.u1Present
1854	&& PdeSrc.n.u1User == PdeDst.n.u1User
1855	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1856	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1857	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1858	# endif
1859	)
1860	{
1861	/*
1862	* Check that the PDE is marked accessed already.
1863	* Since we set the accessed bit before getting here on a #PF, this
1864	* check is only meant for dealing with non-#PF'ing paths.
1865	*/
1866	if (PdeSrc.n.u1Accessed)
1867	{
1868	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1869	if (!fBigPage)
1870	{
1871	/*
1872	* 4KB Page - Map the guest page table.
1873	*/
1874	PGSTPT pPTSrc;
1875	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1876	if (RT_SUCCESS(rc))
1877	{
1878	# ifdef PGM_SYNC_N_PAGES
1879	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1880	if ( cPages > 1
1881	&& !(uErr & X86_TRAP_PF_P)
1882	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1883	{
1884	/*
1885	* This code path is currently only taken when the caller is PGMTrap0eHandler
1886	* for non-present pages!
1887	*
1888	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1889	* deal with locality.
1890	*/
1891	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1892	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1893	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1894	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1895	# else
1896	const unsigned offPTSrc = 0;
1897	# endif
1898	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1899	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1900	iPTDst = 0;
1901	else
1902	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1903	for (; iPTDst < iPTDstEnd; iPTDst++)
1904	{
1905	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1906	{
1907	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1908	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1909	NOREF(GCPtrCurPage);
1910	#ifndef IN_RING0
1911	/*
1912	* Assuming kernel code will be marked as supervisor - and not as user level
1913	* and executed using a conforming code selector - And marked as readonly.
1914	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1915	*/
1916	PPGMPAGE pPage;
1917	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1918	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1919	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1920	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1921	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1922	)
1923	#endif /* else: CSAM not active */
1924	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1925	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1926	GCPtrCurPage, PteSrc.n.u1Present,
1927	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1928	PteSrc.n.u1User & PdeSrc.n.u1User,
1929	(uint64_t)PteSrc.u,
1930	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1931	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1932	}
1933	}
1934	}
1935	else
1936	# endif /* PGM_SYNC_N_PAGES */
1937	{
1938	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1939	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1940	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1941	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1942	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1943	GCPtrPage, PteSrc.n.u1Present,
1944	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1945	PteSrc.n.u1User & PdeSrc.n.u1User,
1946	(uint64_t)PteSrc.u,
1947	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1948	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1949	}
1950	}
1951	else /* MMIO or invalid page: emulated in #PF handler. */
1952	{
1953	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1954	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1955	}
1956	}
1957	else
1958	{
1959	/*
1960	* 4/2MB page - lazy syncing shadow 4K pages.
1961	* (There are many causes of getting here, it's no longer only CSAM.)
1962	*/
1963	/* Calculate the GC physical address of this 4KB shadow page. */
1964	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1965	/* Find ram range. */
1966	PPGMPAGE pPage;
1967	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1968	if (RT_SUCCESS(rc))
1969	{
1970	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1971
1972	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1973	/* Try to make the page writable if necessary. */
1974	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1975	&& ( PGM_PAGE_IS_ZERO(pPage)
1976	\|\| ( PdeSrc.n.u1Write
1977	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1978	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1979	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1980	# endif
1981	# ifdef VBOX_WITH_PAGE_SHARING
1982	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1983	# endif
1984	)
1985	)
1986	)
1987	{
1988	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1989	AssertRC(rc);
1990	}
1991	# endif
1992
1993	/*
1994	* Make shadow PTE entry.
1995	*/
1996	SHWPTE PteDst;
1997	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1998	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
1999	else
2000	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2001
2002	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2003	if ( SHW_PTE_IS_P(PteDst)
2004	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2005	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2006
2007	/* Make sure only allocated pages are mapped writable. */
2008	if ( SHW_PTE_IS_P_RW(PteDst)
2009	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2010	{
2011	/* Still applies to shared pages. */
2012	Assert(!PGM_PAGE_IS_ZERO(pPage));
2013	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2014	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2015	}
2016
2017	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2018
2019	/*
2020	* If the page is not flagged as dirty and is writable, then make it read-only
2021	* at PD level, so we can set the dirty bit when the page is modified.
2022	*
2023	* ASSUMES that page access handlers are implemented on page table entry level.
2024	* Thus we will first catch the dirty access and set PDE.D and restart. If
2025	* there is an access handler, we'll trap again and let it work on the problem.
2026	*/
2027	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2028	* As for invlpg, it simply frees the whole shadow PT.
2029	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2030	if ( !PdeSrc.b.u1Dirty
2031	&& PdeSrc.b.u1Write)
2032	{
2033	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2034	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2035	PdeDst.n.u1Write = 0;
2036	}
2037	else
2038	{
2039	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2040	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2041	}
2042	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2043	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2044	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2045	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2046	}
2047	else
2048	{
2049	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2050	/** @todo must wipe the shadow page table entry in this
2051	* case. */
2052	}
2053	}
2054	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2055	return VINF_SUCCESS;
2056	}
2057
2058	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2059	}
2060	else if (fPdeValid)
2061	{
2062	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2063	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2064	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2065	}
2066	else
2067	{
2068	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2069	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2070	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2071	}
2072
2073	/*
2074	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2075	* Yea, I'm lazy.
2076	*/
2077	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2078	ASMAtomicWriteSize(pPdeDst, 0);
2079
2080	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2081	PGM_INVL_VCPU_TLBS(pVCpu);
2082	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2083
2084
2085	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2086	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2087	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2088	&& !defined(IN_RC)
2089
2090	# ifdef PGM_SYNC_N_PAGES
2091	/*
2092	* Get the shadow PDE, find the shadow page table in the pool.
2093	*/
2094	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2095	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2096
2097	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2098	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2099
2100	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2101	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2102	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2103	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2104	X86PDEPAE PdeDst;
2105	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2106
2107	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2108	AssertRCSuccessReturn(rc, rc);
2109	Assert(pPDDst && pPdptDst);
2110	PdeDst = pPDDst->a[iPDDst];
2111	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2112	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2113	PEPTPD pPDDst;
2114	EPTPDE PdeDst;
2115
2116	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2117	if (rc != VINF_SUCCESS)
2118	{
2119	AssertRC(rc);
2120	return rc;
2121	}
2122	Assert(pPDDst);
2123	PdeDst = pPDDst->a[iPDDst];
2124	# endif
2125	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2126	if (!PdeDst.n.u1Present)
2127	{
2128	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2129	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2130	return VINF_SUCCESS; /* force the instruction to be executed again. */
2131	}
2132
2133	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2134	if (PdeDst.n.u1Size)
2135	{
2136	Assert(pVM->pgm.s.fNestedPaging);
2137	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2138	return VINF_SUCCESS;
2139	}
2140
2141	/* Mask away the page offset. */
2142	GCPtrPage &= ~((RTGCPTR)0xfff);
2143
2144	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2145	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2146
2147	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2148	if ( cPages > 1
2149	&& !(uErr & X86_TRAP_PF_P)
2150	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2151	{
2152	/*
2153	* This code path is currently only taken when the caller is PGMTrap0eHandler
2154	* for non-present pages!
2155	*
2156	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2157	* deal with locality.
2158	*/
2159	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2160	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2161	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2162	iPTDst = 0;
2163	else
2164	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2165	for (; iPTDst < iPTDstEnd; iPTDst++)
2166	{
2167	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2168	{
2169	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2170	GSTPTE PteSrc;
2171
2172	/* Fake the page table entry */
2173	PteSrc.u = GCPtrCurPage;
2174	PteSrc.n.u1Present = 1;
2175	PteSrc.n.u1Dirty = 1;
2176	PteSrc.n.u1Accessed = 1;
2177	PteSrc.n.u1Write = 1;
2178	PteSrc.n.u1User = 1;
2179
2180	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2181	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2182	GCPtrCurPage, PteSrc.n.u1Present,
2183	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2184	PteSrc.n.u1User & PdeSrc.n.u1User,
2185	(uint64_t)PteSrc.u,
2186	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2187	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2188
2189	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2190	break;
2191	}
2192	else
2193	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2194	}
2195	}
2196	else
2197	# endif /* PGM_SYNC_N_PAGES */
2198	{
2199	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2200	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2201	GSTPTE PteSrc;
2202
2203	/* Fake the page table entry */
2204	PteSrc.u = GCPtrCurPage;
2205	PteSrc.n.u1Present = 1;
2206	PteSrc.n.u1Dirty = 1;
2207	PteSrc.n.u1Accessed = 1;
2208	PteSrc.n.u1Write = 1;
2209	PteSrc.n.u1User = 1;
2210	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2211
2212	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2213	GCPtrPage, PteSrc.n.u1Present,
2214	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2215	PteSrc.n.u1User & PdeSrc.n.u1User,
2216	(uint64_t)PteSrc.u,
2217	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2218	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2219	}
2220	return VINF_SUCCESS;
2221
2222	#else
2223	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2224	return VERR_INTERNAL_ERROR;
2225	#endif
2226	}
2227
2228
2229	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2230
2231	/**
2232	* CheckPageFault helper for returning a page fault indicating a non-present
2233	* (NP) entry in the page translation structures.
2234	*
2235	* @returns VINF_EM_RAW_GUEST_TRAP.
2236	* @param pVCpu The virtual CPU to operate on.
2237	* @param uErr The error code of the shadow fault. Corrections to
2238	* TRPM's copy will be made if necessary.
2239	* @param GCPtrPage For logging.
2240	* @param uPageFaultLevel For logging.
2241	*/
2242	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2243	{
2244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2245	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2246	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2247	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2248	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2249
2250	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2251	return VINF_EM_RAW_GUEST_TRAP;
2252	}
2253
2254
2255	/**
2256	* CheckPageFault helper for returning a page fault indicating a reserved bit
2257	* (RSVD) error in the page translation structures.
2258	*
2259	* @returns VINF_EM_RAW_GUEST_TRAP.
2260	* @param pVCpu The virtual CPU to operate on.
2261	* @param uErr The error code of the shadow fault. Corrections to
2262	* TRPM's copy will be made if necessary.
2263	* @param GCPtrPage For logging.
2264	* @param uPageFaultLevel For logging.
2265	*/
2266	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2267	{
2268	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2269	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2270	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2271
2272	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2273	return VINF_EM_RAW_GUEST_TRAP;
2274	}
2275
2276
2277	/**
2278	* CheckPageFault helper for returning a page protection fault (P).
2279	*
2280	* @returns VINF_EM_RAW_GUEST_TRAP.
2281	* @param pVCpu The virtual CPU to operate on.
2282	* @param uErr The error code of the shadow fault. Corrections to
2283	* TRPM's copy will be made if necessary.
2284	* @param GCPtrPage For logging.
2285	* @param uPageFaultLevel For logging.
2286	*/
2287	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2288	{
2289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2290	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2291	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2292	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2293
2294	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2295	return VINF_EM_RAW_GUEST_TRAP;
2296	}
2297
2298
2299	/**
2300	* Handle dirty bit tracking faults.
2301	*
2302	* @returns VBox status code.
2303	* @param pVCpu The VMCPU handle.
2304	* @param uErr Page fault error code.
2305	* @param pPdeSrc Guest page directory entry.
2306	* @param pPdeDst Shadow page directory entry.
2307	* @param GCPtrPage Guest context page address.
2308	*/
2309	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2310	{
2311	PVM pVM = pVCpu->CTX_SUFF(pVM);
2312	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2313
2314	Assert(PGMIsLockOwner(pVM));
2315
2316	/*
2317	* Handle big page.
2318	*/
2319	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2320	{
2321	if ( pPdeDst->n.u1Present
2322	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2323	{
2324	SHWPDE PdeDst = *pPdeDst;
2325
2326	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2327	Assert(pPdeSrc->b.u1Write);
2328
2329	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2330	* fault again and take this path to only invalidate the entry (see below).
2331	*/
2332	PdeDst.n.u1Write = 1;
2333	PdeDst.n.u1Accessed = 1;
2334	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2335	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2336	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2337	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2338	}
2339
2340	# ifdef IN_RING0
2341	/* Check for stale TLB entry; only applies to the SMP guest case. */
2342	if ( pVM->cCpus > 1
2343	&& pPdeDst->n.u1Write
2344	&& pPdeDst->n.u1Accessed)
2345	{
2346	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2347	if (pShwPage)
2348	{
2349	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2350	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2351	if (SHW_PTE_IS_P_RW(*pPteDst))
2352	{
2353	/* Stale TLB entry. */
2354	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2355	PGM_INVL_PG(pVCpu, GCPtrPage);
2356	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2357	}
2358	}
2359	}
2360	# endif /* IN_RING0 */
2361	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2362	}
2363
2364	/*
2365	* Map the guest page table.
2366	*/
2367	PGSTPT pPTSrc;
2368	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2369	if (RT_FAILURE(rc))
2370	{
2371	AssertRC(rc);
2372	return rc;
2373	}
2374
2375	if (pPdeDst->n.u1Present)
2376	{
2377	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2378	const GSTPTE PteSrc = *pPteSrc;
2379
2380	#ifndef IN_RING0
2381	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2382	* Our individual shadow handlers will provide more information and force a fatal exit.
2383	*/
2384	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2385	{
2386	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2387	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2388	}
2389	#endif
2390	/*
2391	* Map shadow page table.
2392	*/
2393	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2394	if (pShwPage)
2395	{
2396	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2397	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2398	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2399	{
2400	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2401	{
2402	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2403	SHWPTE PteDst = *pPteDst;
2404
2405	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2406	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2407
2408	Assert(pPteSrc->n.u1Write);
2409
2410	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2411	* entry will not harm; write access will simply fault again and
2412	* take this path to only invalidate the entry.
2413	*/
2414	if (RT_LIKELY(pPage))
2415	{
2416	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2417	{
2418	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2419	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2420	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2421	SHW_PTE_SET_RO(PteDst);
2422	}
2423	else
2424	{
2425	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2426	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2427	{
2428	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2429	AssertRC(rc);
2430	}
2431	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2432	SHW_PTE_SET_RW(PteDst);
2433	else
2434	{
2435	/* Still applies to shared pages. */
2436	Assert(!PGM_PAGE_IS_ZERO(pPage));
2437	SHW_PTE_SET_RO(PteDst);
2438	}
2439	}
2440	}
2441	else
2442	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2443
2444	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2445	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2446	PGM_INVL_PG(pVCpu, GCPtrPage);
2447	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2448	}
2449
2450	# ifdef IN_RING0
2451	/* Check for stale TLB entry; only applies to the SMP guest case. */
2452	if ( pVM->cCpus > 1
2453	&& SHW_PTE_IS_RW(*pPteDst)
2454	&& SHW_PTE_IS_A(*pPteDst))
2455	{
2456	/* Stale TLB entry. */
2457	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2458	PGM_INVL_PG(pVCpu, GCPtrPage);
2459	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2460	}
2461	# endif
2462	}
2463	}
2464	else
2465	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2466	}
2467
2468	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2469	}
2470
2471	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2472
2473
2474	/**
2475	* Sync a shadow page table.
2476	*
2477	* The shadow page table is not present in the shadow PDE.
2478	*
2479	* Handles mapping conflicts.
2480	*
2481	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2482	* conflict), and Trap0eHandler.
2483	*
2484	* A precodition for this method is that the shadow PDE is not present. The
2485	* caller must take the PGM lock before checking this and continue to hold it
2486	* when calling this method.
2487	*
2488	* @returns VBox status code.
2489	* @param pVCpu The VMCPU handle.
2490	* @param iPD Page directory index.
2491	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2492	* Assume this is a temporary mapping.
2493	* @param GCPtrPage GC Pointer of the page that caused the fault
2494	*/
2495	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2496	{
2497	PVM pVM = pVCpu->CTX_SUFF(pVM);
2498	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2499
2500	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2501	#if 0 /* rarely useful; leave for debugging. */
2502	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2503	#endif
2504	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2505
2506	Assert(PGMIsLocked(pVM));
2507
2508	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2509	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2510	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2511	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2512	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2513
2514	int rc = VINF_SUCCESS;
2515
2516	/*
2517	* Some input validation first.
2518	*/
2519	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2520
2521	/*
2522	* Get the relevant shadow PDE entry.
2523	*/
2524	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2525	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2526	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2527
2528	/* Fetch the pgm pool shadow descriptor. */
2529	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2530	Assert(pShwPde);
2531
2532	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2533	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2534	PPGMPOOLPAGE pShwPde = NULL;
2535	PX86PDPAE pPDDst;
2536	PSHWPDE pPdeDst;
2537
2538	/* Fetch the pgm pool shadow descriptor. */
2539	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2540	AssertRCSuccessReturn(rc, rc);
2541	Assert(pShwPde);
2542
2543	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2544	pPdeDst = &pPDDst->a[iPDDst];
2545
2546	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2547	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2548	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2549	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2550	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2551	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2552	AssertRCSuccessReturn(rc, rc);
2553	Assert(pPDDst);
2554	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2555	# endif
2556	SHWPDE PdeDst = *pPdeDst;
2557
2558	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2559	/* Fetch the pgm pool shadow descriptor. */
2560	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2561	Assert(pShwPde);
2562	# endif
2563
2564	# ifndef PGM_WITHOUT_MAPPINGS
2565	/*
2566	* Check for conflicts.
2567	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2568	* R3: Simply resolve the conflict.
2569	*/
2570	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2571	{
2572	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2573	# ifndef IN_RING3
2574	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2575	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2576	return VERR_ADDRESS_CONFLICT;
2577
2578	# else /* IN_RING3 */
2579	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2580	Assert(pMapping);
2581	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2582	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2583	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2584	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2585	# else
2586	AssertFailed(); /* can't happen for amd64 */
2587	# endif
2588	if (RT_FAILURE(rc))
2589	{
2590	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2591	return rc;
2592	}
2593	PdeDst = *pPdeDst;
2594	# endif /* IN_RING3 */
2595	}
2596	# endif /* !PGM_WITHOUT_MAPPINGS */
2597	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2598
2599	/*
2600	* Sync the page directory entry.
2601	*/
2602	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2603	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2604	if ( PdeSrc.n.u1Present
2605	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2606	{
2607	/*
2608	* Allocate & map the page table.
2609	*/
2610	PSHWPT pPTDst;
2611	PPGMPOOLPAGE pShwPage;
2612	RTGCPHYS GCPhys;
2613	if (fPageTable)
2614	{
2615	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2616	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2617	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2618	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2619	# endif
2620	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2621	}
2622	else
2623	{
2624	PGMPOOLACCESS enmAccess;
2625	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2626	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2627	# else
2628	const bool fNoExecute = false;
2629	# endif
2630
2631	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2632	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2633	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2634	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2635	# endif
2636	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2637	if (PdeSrc.n.u1User)
2638	{
2639	if (PdeSrc.n.u1Write)
2640	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2641	else
2642	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2643	}
2644	else
2645	{
2646	if (PdeSrc.n.u1Write)
2647	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2648	else
2649	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2650	}
2651	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2652	&pShwPage);
2653	}
2654	if (rc == VINF_SUCCESS)
2655	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2656	else if (rc == VINF_PGM_CACHED_PAGE)
2657	{
2658	/*
2659	* The PT was cached, just hook it up.
2660	*/
2661	if (fPageTable)
2662	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2663	else
2664	{
2665	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2666	/* (see explanation and assumptions further down.) */
2667	if ( !PdeSrc.b.u1Dirty
2668	&& PdeSrc.b.u1Write)
2669	{
2670	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2671	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2672	PdeDst.b.u1Write = 0;
2673	}
2674	}
2675	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2676	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2677	return VINF_SUCCESS;
2678	}
2679	else if (rc == VERR_PGM_POOL_FLUSHED)
2680	{
2681	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2682	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2683	return VINF_PGM_SYNC_CR3;
2684	}
2685	else
2686	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2687	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2688	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2689	* irrelevant at this point. */
2690	PdeDst.u &= X86_PDE_AVL_MASK;
2691	PdeDst.u \|= pShwPage->Core.Key;
2692
2693	/*
2694	* Page directory has been accessed (this is a fault situation, remember).
2695	*/
2696	/** @todo
2697	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2698	* fault situation. What's more, the Trap0eHandler has already set the
2699	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2700	* might need setting the accessed flag.
2701	*
2702	* The best idea is to leave this change to the caller and add an
2703	* assertion that it's set already. */
2704	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2705	if (fPageTable)
2706	{
2707	/*
2708	* Page table - 4KB.
2709	*
2710	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2711	*/
2712	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2713	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2714	PGSTPT pPTSrc;
2715	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2716	if (RT_SUCCESS(rc))
2717	{
2718	/*
2719	* Start by syncing the page directory entry so CSAM's TLB trick works.
2720	*/
2721	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2722	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2723	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2724	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2725
2726	/*
2727	* Directory/page user or supervisor privilege: (same goes for read/write)
2728	*
2729	* Directory Page Combined
2730	* U/S U/S U/S
2731	* 0 0 0
2732	* 0 1 0
2733	* 1 0 0
2734	* 1 1 1
2735	*
2736	* Simple AND operation. Table listed for completeness.
2737	*
2738	*/
2739	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2740	# ifdef PGM_SYNC_N_PAGES
2741	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2742	unsigned iPTDst = iPTBase;
2743	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2744	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2745	iPTDst = 0;
2746	else
2747	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2748	# else /* !PGM_SYNC_N_PAGES */
2749	unsigned iPTDst = 0;
2750	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2751	# endif /* !PGM_SYNC_N_PAGES */
2752	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2753	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2754	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2755	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2756	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2757	# else
2758	const unsigned offPTSrc = 0;
2759	# endif
2760	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2761	{
2762	const unsigned iPTSrc = iPTDst + offPTSrc;
2763	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2764
2765	if (PteSrc.n.u1Present)
2766	{
2767	# ifndef IN_RING0
2768	/*
2769	* Assuming kernel code will be marked as supervisor - and not as user level
2770	* and executed using a conforming code selector - And marked as readonly.
2771	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2772	*/
2773	PPGMPAGE pPage;
2774	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2775	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2776	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2777	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2778	)
2779	# endif
2780	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2781	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2782	GCPtrCur,
2783	PteSrc.n.u1Present,
2784	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2785	PteSrc.n.u1User & PdeSrc.n.u1User,
2786	(uint64_t)PteSrc.u,
2787	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2788	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2789	}
2790	/* else: the page table was cleared by the pool */
2791	} /* for PTEs */
2792	}
2793	}
2794	else
2795	{
2796	/*
2797	* Big page - 2/4MB.
2798	*
2799	* We'll walk the ram range list in parallel and optimize lookups.
2800	* We will only sync on shadow page table at a time.
2801	*/
2802	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2803
2804	/**
2805	* @todo It might be more efficient to sync only a part of the 4MB
2806	* page (similar to what we do for 4KB PDs).
2807	*/
2808
2809	/*
2810	* Start by syncing the page directory entry.
2811	*/
2812	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2813	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2814
2815	/*
2816	* If the page is not flagged as dirty and is writable, then make it read-only
2817	* at PD level, so we can set the dirty bit when the page is modified.
2818	*
2819	* ASSUMES that page access handlers are implemented on page table entry level.
2820	* Thus we will first catch the dirty access and set PDE.D and restart. If
2821	* there is an access handler, we'll trap again and let it work on the problem.
2822	*/
2823	/** @todo move the above stuff to a section in the PGM documentation. */
2824	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2825	if ( !PdeSrc.b.u1Dirty
2826	&& PdeSrc.b.u1Write)
2827	{
2828	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2829	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2830	PdeDst.b.u1Write = 0;
2831	}
2832	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2833	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2834
2835	/*
2836	* Fill the shadow page table.
2837	*/
2838	/* Get address and flags from the source PDE. */
2839	SHWPTE PteDstBase;
2840	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2841
2842	/* Loop thru the entries in the shadow PT. */
2843	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2844	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2845	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2846	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2847	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2848	unsigned iPTDst = 0;
2849	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2850	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2851	{
2852	/* Advance ram range list. */
2853	while (pRam && GCPhys > pRam->GCPhysLast)
2854	pRam = pRam->CTX_SUFF(pNext);
2855	if (pRam && GCPhys >= pRam->GCPhys)
2856	{
2857	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2858	do
2859	{
2860	/* Make shadow PTE. */
2861	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2862	SHWPTE PteDst;
2863
2864	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2865	/* Try to make the page writable if necessary. */
2866	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2867	&& ( PGM_PAGE_IS_ZERO(pPage)
2868	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2869	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2870	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2871	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2872	# endif
2873	# ifdef VBOX_WITH_PAGE_SHARING
2874	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2875	# endif
2876	&& !PGM_PAGE_IS_BALLOONED(pPage))
2877	)
2878	)
2879	{
2880	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2881	AssertRCReturn(rc, rc);
2882	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2883	break;
2884	}
2885	# endif
2886
2887	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2888	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2889	else if (PGM_PAGE_IS_BALLOONED(pPage))
2890	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2891	# ifndef IN_RING0
2892	/*
2893	* Assuming kernel code will be marked as supervisor and not as user level and executed
2894	* using a conforming code selector. Don't check for readonly, as that implies the whole
2895	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2896	*/
2897	else if ( !PdeSrc.n.u1User
2898	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2899	SHW_PTE_SET(PteDst, 0);
2900	# endif
2901	else
2902	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2903
2904	/* Only map writable pages writable. */
2905	if ( SHW_PTE_IS_P_RW(PteDst)
2906	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2907	{
2908	/* Still applies to shared pages. */
2909	Assert(!PGM_PAGE_IS_ZERO(pPage));
2910	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2911	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2912	}
2913
2914	if (SHW_PTE_IS_P(PteDst))
2915	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2916
2917	/* commit it (not atomic, new table) */
2918	pPTDst->a[iPTDst] = PteDst;
2919	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2920	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2921	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2922
2923	/* advance */
2924	GCPhys += PAGE_SIZE;
2925	iHCPage++;
2926	iPTDst++;
2927	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2928	&& GCPhys <= pRam->GCPhysLast);
2929	}
2930	else if (pRam)
2931	{
2932	Log(("Invalid pages at %RGp\n", GCPhys));
2933	do
2934	{
2935	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2936	GCPhys += PAGE_SIZE;
2937	iPTDst++;
2938	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2939	&& GCPhys < pRam->GCPhys);
2940	}
2941	else
2942	{
2943	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2944	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2945	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2946	}
2947	} /* while more PTEs */
2948	} /* 4KB / 4MB */
2949	}
2950	else
2951	AssertRelease(!PdeDst.n.u1Present);
2952
2953	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2954	if (RT_FAILURE(rc))
2955	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2956	return rc;
2957
2958	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2959	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2960	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2961	&& !defined(IN_RC)
2962
2963	/*
2964	* Validate input a little bit.
2965	*/
2966	int rc = VINF_SUCCESS;
2967	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2968	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2969	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2970
2971	/* Fetch the pgm pool shadow descriptor. */
2972	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2973	Assert(pShwPde);
2974
2975	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2976	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2977	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2978	PX86PDPAE pPDDst;
2979	PSHWPDE pPdeDst;
2980
2981	/* Fetch the pgm pool shadow descriptor. */
2982	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2983	AssertRCSuccessReturn(rc, rc);
2984	Assert(pShwPde);
2985
2986	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2987	pPdeDst = &pPDDst->a[iPDDst];
2988
2989	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2990	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2991	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2992	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2993	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2994	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2995	AssertRCSuccessReturn(rc, rc);
2996	Assert(pPDDst);
2997	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2998
2999	/* Fetch the pgm pool shadow descriptor. */
3000	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3001	Assert(pShwPde);
3002
3003	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3004	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3005	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3006	PEPTPD pPDDst;
3007	PEPTPDPT pPdptDst;
3008
3009	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3010	if (rc != VINF_SUCCESS)
3011	{
3012	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3013	AssertRC(rc);
3014	return rc;
3015	}
3016	Assert(pPDDst);
3017	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3018
3019	/* Fetch the pgm pool shadow descriptor. */
3020	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3021	Assert(pShwPde);
3022	# endif
3023	SHWPDE PdeDst = *pPdeDst;
3024
3025	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3026	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3027
3028	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3029	if (BTH_IS_NP_ACTIVE(pVM))
3030	{
3031	PPGMPAGE pPage;
3032
3033	/* Check if we allocated a big page before for this 2 MB range. */
3034	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3035	if (RT_SUCCESS(rc))
3036	{
3037	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3038
3039	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3040	{
3041	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3042	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3043	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3044	}
3045	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3046	{
3047	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3048	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3049	if (RT_SUCCESS(rc))
3050	{
3051	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3052	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3053	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3054	}
3055	}
3056	else if (PGMIsUsingLargePages(pVM))
3057	{
3058	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3059	if (RT_SUCCESS(rc))
3060	{
3061	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3062	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3063	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3064	}
3065	else
3066	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3067	}
3068
3069	if (HCPhys != NIL_RTHCPHYS)
3070	{
3071	PdeDst.u &= X86_PDE_AVL_MASK;
3072	PdeDst.u \|= HCPhys;
3073	PdeDst.n.u1Present = 1;
3074	PdeDst.n.u1Write = 1;
3075	PdeDst.b.u1Size = 1;
3076	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3077	PdeDst.n.u1Execute = 1;
3078	PdeDst.b.u1IgnorePAT = 1;
3079	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3080	# else
3081	PdeDst.n.u1User = 1;
3082	# endif
3083	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3084
3085	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3086	/* Add a reference to the first page only. */
3087	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3088
3089	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3090	return VINF_SUCCESS;
3091	}
3092	}
3093	}
3094	# endif /* HC_ARCH_BITS == 64 */
3095
3096	GSTPDE PdeSrc;
3097	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3098	PdeSrc.n.u1Present = 1;
3099	PdeSrc.n.u1Write = 1;
3100	PdeSrc.n.u1Accessed = 1;
3101	PdeSrc.n.u1User = 1;
3102
3103	/*
3104	* Allocate & map the page table.
3105	*/
3106	PSHWPT pPTDst;
3107	PPGMPOOLPAGE pShwPage;
3108	RTGCPHYS GCPhys;
3109
3110	/* Virtual address = physical address */
3111	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3112	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3113
3114	if ( rc == VINF_SUCCESS
3115	\|\| rc == VINF_PGM_CACHED_PAGE)
3116	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3117	else
3118	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3119
3120	PdeDst.u &= X86_PDE_AVL_MASK;
3121	PdeDst.u \|= pShwPage->Core.Key;
3122	PdeDst.n.u1Present = 1;
3123	PdeDst.n.u1Write = 1;
3124	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3125	PdeDst.n.u1Execute = 1;
3126	# else
3127	PdeDst.n.u1User = 1;
3128	PdeDst.n.u1Accessed = 1;
3129	# endif
3130	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3131
3132	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3133	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3134	return rc;
3135
3136	#else
3137	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3138	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3139	return VERR_INTERNAL_ERROR;
3140	#endif
3141	}
3142
3143
3144
3145	/**
3146	* Prefetch a page/set of pages.
3147	*
3148	* Typically used to sync commonly used pages before entering raw mode
3149	* after a CR3 reload.
3150	*
3151	* @returns VBox status code.
3152	* @param pVCpu The VMCPU handle.
3153	* @param GCPtrPage Page to invalidate.
3154	*/
3155	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3156	{
3157	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3158	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3159	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3160	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3161	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3162	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3163	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3164
3165	/*
3166	* Check that all Guest levels thru the PDE are present, getting the
3167	* PD and PDE in the processes.
3168	*/
3169	int rc = VINF_SUCCESS;
3170	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3171	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3172	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3173	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3174	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3175	unsigned iPDSrc;
3176	X86PDPE PdpeSrc;
3177	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3178	if (!pPDSrc)
3179	return VINF_SUCCESS; /* not present */
3180	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3181	unsigned iPDSrc;
3182	PX86PML4E pPml4eSrc;
3183	X86PDPE PdpeSrc;
3184	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3185	if (!pPDSrc)
3186	return VINF_SUCCESS; /* not present */
3187	# endif
3188	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3189	# else
3190	PGSTPD pPDSrc = NULL;
3191	const unsigned iPDSrc = 0;
3192	GSTPDE PdeSrc;
3193
3194	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3195	PdeSrc.n.u1Present = 1;
3196	PdeSrc.n.u1Write = 1;
3197	PdeSrc.n.u1Accessed = 1;
3198	PdeSrc.n.u1User = 1;
3199	# endif
3200
3201	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3202	{
3203	PVM pVM = pVCpu->CTX_SUFF(pVM);
3204	pgmLock(pVM);
3205
3206	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3207	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3208	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3209	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3210	PX86PDPAE pPDDst;
3211	X86PDEPAE PdeDst;
3212	# if PGM_GST_TYPE != PGM_TYPE_PAE
3213	X86PDPE PdpeSrc;
3214
3215	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3216	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3217	# endif
3218	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3219	if (rc != VINF_SUCCESS)
3220	{
3221	pgmUnlock(pVM);
3222	AssertRC(rc);
3223	return rc;
3224	}
3225	Assert(pPDDst);
3226	PdeDst = pPDDst->a[iPDDst];
3227
3228	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3229	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3230	PX86PDPAE pPDDst;
3231	X86PDEPAE PdeDst;
3232
3233	# if PGM_GST_TYPE == PGM_TYPE_PROT
3234	/* AMD-V nested paging */
3235	X86PML4E Pml4eSrc;
3236	X86PDPE PdpeSrc;
3237	PX86PML4E pPml4eSrc = &Pml4eSrc;
3238
3239	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3240	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3241	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3242	# endif
3243
3244	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3245	if (rc != VINF_SUCCESS)
3246	{
3247	pgmUnlock(pVM);
3248	AssertRC(rc);
3249	return rc;
3250	}
3251	Assert(pPDDst);
3252	PdeDst = pPDDst->a[iPDDst];
3253	# endif
3254	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3255	{
3256	if (!PdeDst.n.u1Present)
3257	{
3258	/** @todo r=bird: This guy will set the A bit on the PDE,
3259	* probably harmless. */
3260	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3261	}
3262	else
3263	{
3264	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3265	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3266	* makes no sense to prefetch more than one page.
3267	*/
3268	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3269	if (RT_SUCCESS(rc))
3270	rc = VINF_SUCCESS;
3271	}
3272	}
3273	pgmUnlock(pVM);
3274	}
3275	return rc;
3276
3277	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3278	return VINF_SUCCESS; /* ignore */
3279	#else
3280	AssertCompile(0);
3281	#endif
3282	}
3283
3284
3285
3286
3287	/**
3288	* Syncs a page during a PGMVerifyAccess() call.
3289	*
3290	* @returns VBox status code (informational included).
3291	* @param pVCpu The VMCPU handle.
3292	* @param GCPtrPage The address of the page to sync.
3293	* @param fPage The effective guest page flags.
3294	* @param uErr The trap error code.
3295	* @remarks This will normally never be called on invalid guest page
3296	* translation entries.
3297	*/
3298	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3299	{
3300	PVM pVM = pVCpu->CTX_SUFF(pVM);
3301
3302	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3303
3304	Assert(!pVM->pgm.s.fNestedPaging);
3305	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3306	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3307	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3308	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3309	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3310	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3311	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3312
3313	# ifndef IN_RING0
3314	if (!(fPage & X86_PTE_US))
3315	{
3316	/*
3317	* Mark this page as safe.
3318	*/
3319	/** @todo not correct for pages that contain both code and data!! */
3320	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3321	CSAMMarkPage(pVM, GCPtrPage, true);
3322	}
3323	# endif
3324
3325	/*
3326	* Get guest PD and index.
3327	*/
3328	/** @todo Performance: We've done all this a jiffy ago in the
3329	* PGMGstGetPage call. */
3330	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3331	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3332	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3333	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3334
3335	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3336	unsigned iPDSrc = 0;
3337	X86PDPE PdpeSrc;
3338	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3339	if (RT_UNLIKELY(!pPDSrc))
3340	{
3341	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3342	return VINF_EM_RAW_GUEST_TRAP;
3343	}
3344
3345	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3346	unsigned iPDSrc = 0; /* shut up gcc */
3347	PX86PML4E pPml4eSrc = NULL; /* ditto */
3348	X86PDPE PdpeSrc;
3349	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3350	if (RT_UNLIKELY(!pPDSrc))
3351	{
3352	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3353	return VINF_EM_RAW_GUEST_TRAP;
3354	}
3355	# endif
3356
3357	# else /* !PGM_WITH_PAGING */
3358	PGSTPD pPDSrc = NULL;
3359	const unsigned iPDSrc = 0;
3360	# endif /* !PGM_WITH_PAGING */
3361	int rc = VINF_SUCCESS;
3362
3363	pgmLock(pVM);
3364
3365	/*
3366	* First check if the shadow pd is present.
3367	*/
3368	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3369	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3370
3371	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3372	PX86PDEPAE pPdeDst;
3373	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3374	PX86PDPAE pPDDst;
3375	# if PGM_GST_TYPE != PGM_TYPE_PAE
3376	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3377	X86PDPE PdpeSrc;
3378	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3379	# endif
3380	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3381	if (rc != VINF_SUCCESS)
3382	{
3383	pgmUnlock(pVM);
3384	AssertRC(rc);
3385	return rc;
3386	}
3387	Assert(pPDDst);
3388	pPdeDst = &pPDDst->a[iPDDst];
3389
3390	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3391	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3392	PX86PDPAE pPDDst;
3393	PX86PDEPAE pPdeDst;
3394
3395	# if PGM_GST_TYPE == PGM_TYPE_PROT
3396	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3397	X86PML4E Pml4eSrc;
3398	X86PDPE PdpeSrc;
3399	PX86PML4E pPml4eSrc = &Pml4eSrc;
3400	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3401	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3402	# endif
3403
3404	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3405	if (rc != VINF_SUCCESS)
3406	{
3407	pgmUnlock(pVM);
3408	AssertRC(rc);
3409	return rc;
3410	}
3411	Assert(pPDDst);
3412	pPdeDst = &pPDDst->a[iPDDst];
3413	# endif
3414
3415	if (!pPdeDst->n.u1Present)
3416	{
3417	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3418	if (rc != VINF_SUCCESS)
3419	{
3420	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3421	pgmUnlock(pVM);
3422	AssertRC(rc);
3423	return rc;
3424	}
3425	}
3426
3427	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3428	/* Check for dirty bit fault */
3429	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3430	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3431	Log(("PGMVerifyAccess: success (dirty)\n"));
3432	else
3433	# endif
3434	{
3435	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3436	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3437	# else
3438	GSTPDE PdeSrc;
3439	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3440	PdeSrc.n.u1Present = 1;
3441	PdeSrc.n.u1Write = 1;
3442	PdeSrc.n.u1Accessed = 1;
3443	PdeSrc.n.u1User = 1;
3444	# endif
3445
3446	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3447	if (uErr & X86_TRAP_PF_US)
3448	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3449	else /* supervisor */
3450	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3451
3452	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3453	if (RT_SUCCESS(rc))
3454	{
3455	/* Page was successfully synced */
3456	Log2(("PGMVerifyAccess: success (sync)\n"));
3457	rc = VINF_SUCCESS;
3458	}
3459	else
3460	{
3461	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3462	rc = VINF_EM_RAW_GUEST_TRAP;
3463	}
3464	}
3465	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3466	pgmUnlock(pVM);
3467	return rc;
3468
3469	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3470
3471	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3472	return VERR_INTERNAL_ERROR;
3473	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3474	}
3475
3476
3477	/**
3478	* Syncs the paging hierarchy starting at CR3.
3479	*
3480	* @returns VBox status code, no specials.
3481	* @param pVCpu The VMCPU handle.
3482	* @param cr0 Guest context CR0 register
3483	* @param cr3 Guest context CR3 register
3484	* @param cr4 Guest context CR4 register
3485	* @param fGlobal Including global page directories or not
3486	*/
3487	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3488	{
3489	PVM pVM = pVCpu->CTX_SUFF(pVM);
3490
3491	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3492
3493	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3494
3495	pgmLock(pVM);
3496
3497	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3498	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3499	if (pPool->cDirtyPages)
3500	pgmPoolResetDirtyPages(pVM);
3501	# endif
3502
3503	/*
3504	* Update page access handlers.
3505	* The virtual are always flushed, while the physical are only on demand.
3506	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3507	* have to look into that later because it will have a bad influence on the performance.
3508	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3509	* bird: Yes, but that won't work for aliases.
3510	*/
3511	/** @todo this MUST go away. See #1557. */
3512	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3513	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3514	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3515	pgmUnlock(pVM);
3516	#endif /* !NESTED && !EPT */
3517
3518	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3519	/*
3520	* Nested / EPT - almost no work.
3521	*/
3522	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3523	return VINF_SUCCESS;
3524
3525	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3526	/*
3527	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3528	* out the shadow parts when the guest modifies its tables.
3529	*/
3530	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3531	return VINF_SUCCESS;
3532
3533	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3534
3535	# ifndef PGM_WITHOUT_MAPPINGS
3536	/*
3537	* Check for and resolve conflicts with our guest mappings if they
3538	* are enabled and not fixed.
3539	*/
3540	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3541	{
3542	int rc = pgmMapResolveConflicts(pVM);
3543	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3544	if (rc == VINF_PGM_SYNC_CR3)
3545	{
3546	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3547	return VINF_PGM_SYNC_CR3;
3548	}
3549	}
3550	# else
3551	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3552	# endif
3553	return VINF_SUCCESS;
3554	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3555	}
3556
3557
3558
3559
3560	#ifdef VBOX_STRICT
3561	# ifdef IN_RC
3562	# undef AssertMsgFailed
3563	# define AssertMsgFailed Log
3564	# endif
3565
3566	/**
3567	* Checks that the shadow page table is in sync with the guest one.
3568	*
3569	* @returns The number of errors.
3570	* @param pVM The virtual machine.
3571	* @param pVCpu The VMCPU handle.
3572	* @param cr3 Guest context CR3 register
3573	* @param cr4 Guest context CR4 register
3574	* @param GCPtr Where to start. Defaults to 0.
3575	* @param cb How much to check. Defaults to everything.
3576	*/
3577	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3578	{
3579	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3580	return 0;
3581	#else
3582	unsigned cErrors = 0;
3583	PVM pVM = pVCpu->CTX_SUFF(pVM);
3584	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3585
3586	#if PGM_GST_TYPE == PGM_TYPE_PAE
3587	/** @todo currently broken; crashes below somewhere */
3588	AssertFailed();
3589	#endif
3590
3591	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3592	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3593	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3594
3595	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3596	PPGMCPU pPGM = &pVCpu->pgm.s;
3597	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3598	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3599	# ifndef IN_RING0
3600	RTHCPHYS HCPhys; /* general usage. */
3601	# endif
3602	int rc;
3603
3604	/*
3605	* Check that the Guest CR3 and all its mappings are correct.
3606	*/
3607	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3608	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3609	false);
3610	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3611	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3612	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3613	# else
3614	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3615	# endif
3616	AssertRCReturn(rc, 1);
3617	HCPhys = NIL_RTHCPHYS;
3618	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3619	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3620	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3621	pgmGstGet32bitPDPtr(pVCpu);
3622	RTGCPHYS GCPhys;
3623	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3624	AssertRCReturn(rc, 1);
3625	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3626	# endif
3627	# endif /* !IN_RING0 */
3628
3629	/*
3630	* Get and check the Shadow CR3.
3631	*/
3632	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3633	unsigned cPDEs = X86_PG_ENTRIES;
3634	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3635	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3636	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3637	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3638	# else
3639	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3640	# endif
3641	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3642	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3643	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3644	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3645	# endif
3646	if (cb != ~(RTGCPTR)0)
3647	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3648
3649	/** @todo call the other two PGMAssert() functions. /
3650
3651	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3652	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3653
3654	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3655	{
3656	PPGMPOOLPAGE pShwPdpt = NULL;
3657	PX86PML4E pPml4eSrc;
3658	PX86PML4E pPml4eDst;
3659	RTGCPHYS GCPhysPdptSrc;
3660
3661	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3662	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3663
3664	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3665	if (!pPml4eDst->n.u1Present)
3666	{
3667	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3668	continue;
3669	}
3670
3671	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3672	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3673
3674	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3675	{
3676	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3677	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3678	cErrors++;
3679	continue;
3680	}
3681
3682	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3683	{
3684	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3685	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3686	cErrors++;
3687	continue;
3688	}
3689
3690	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3691	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3692	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3693	{
3694	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3695	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3696	cErrors++;
3697	continue;
3698	}
3699	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3700	{
3701	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3702
3703	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3704	/*
3705	* Check the PDPTEs too.
3706	*/
3707	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3708
3709	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3710	{
3711	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3712	PPGMPOOLPAGE pShwPde = NULL;
3713	PX86PDPE pPdpeDst;
3714	RTGCPHYS GCPhysPdeSrc;
3715	# if PGM_GST_TYPE == PGM_TYPE_PAE
3716	X86PDPE PdpeSrc;
3717	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3718	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3719	# else
3720	PX86PML4E pPml4eSrcIgn;
3721	X86PDPE PdpeSrc;
3722	PX86PDPT pPdptDst;
3723	PX86PDPAE pPDDst;
3724	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3725
3726	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3727	if (rc != VINF_SUCCESS)
3728	{
3729	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3730	GCPtr += 512 * _2M;
3731	continue; /* next PDPTE */
3732	}
3733	Assert(pPDDst);
3734	# endif
3735	Assert(iPDSrc == 0);
3736
3737	pPdpeDst = &pPdptDst->a[iPdpt];
3738
3739	if (!pPdpeDst->n.u1Present)
3740	{
3741	GCPtr += 512 * _2M;
3742	continue; /* next PDPTE */
3743	}
3744
3745	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3746	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3747
3748	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3749	{
3750	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3751	GCPtr += 512 * _2M;
3752	cErrors++;
3753	continue;
3754	}
3755
3756	if (GCPhysPdeSrc != pShwPde->GCPhys)
3757	{
3758	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3759	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3760	# else
3761	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3762	# endif
3763	GCPtr += 512 * _2M;
3764	cErrors++;
3765	continue;
3766	}
3767
3768	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3769	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3770	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3771	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3772	{
3773	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3774	GCPtr += 512 * _2M;
3775	cErrors++;
3776	continue;
3777	}
3778	# endif
3779
3780	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3781	{
3782	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3783	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3784	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3785	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3786	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3787	# endif
3788	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3789	/*
3790	* Iterate the shadow page directory.
3791	*/
3792	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3793	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3794
3795	for (;
3796	iPDDst < cPDEs;
3797	iPDDst++, GCPtr += cIncrement)
3798	{
3799	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3800	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3801	# else
3802	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3803	# endif
3804	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3805	{
3806	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3807	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3808	{
3809	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3810	cErrors++;
3811	continue;
3812	}
3813	}
3814	else if ( (PdeDst.u & X86_PDE_P)
3815	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3816	)
3817	{
3818	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3819	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3820	if (!pPoolPage)
3821	{
3822	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3823	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3824	cErrors++;
3825	continue;
3826	}
3827	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3828
3829	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3830	{
3831	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3832	GCPtr, (uint64_t)PdeDst.u));
3833	cErrors++;
3834	}
3835
3836	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3837	{
3838	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3839	GCPtr, (uint64_t)PdeDst.u));
3840	cErrors++;
3841	}
3842
3843	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3844	if (!PdeSrc.n.u1Present)
3845	{
3846	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3847	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3848	cErrors++;
3849	continue;
3850	}
3851
3852	if ( !PdeSrc.b.u1Size
3853	\|\| !fBigPagesSupported)
3854	{
3855	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3856	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3857	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3858	# endif
3859	}
3860	else
3861	{
3862	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3863	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3864	{
3865	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3866	GCPtr, (uint64_t)PdeSrc.u));
3867	cErrors++;
3868	continue;
3869	}
3870	# endif
3871	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3872	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3873	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3874	# endif
3875	}
3876
3877	if ( pPoolPage->enmKind
3878	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3879	{
3880	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3881	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3882	cErrors++;
3883	}
3884
3885	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3886	if (!pPhysPage)
3887	{
3888	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3889	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3890	cErrors++;
3891	continue;
3892	}
3893
3894	if (GCPhysGst != pPoolPage->GCPhys)
3895	{
3896	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3897	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3898	cErrors++;
3899	continue;
3900	}
3901
3902	if ( !PdeSrc.b.u1Size
3903	\|\| !fBigPagesSupported)
3904	{
3905	/*
3906	* Page Table.
3907	*/
3908	const GSTPT *pPTSrc;
3909	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3910	if (RT_FAILURE(rc))
3911	{
3912	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3913	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3914	cErrors++;
3915	continue;
3916	}
3917	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3918	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3919	{
3920	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3921	// (This problem will go away when/if we shadow multiple CR3s.)
3922	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3923	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3924	cErrors++;
3925	continue;
3926	}
3927	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3928	{
3929	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3930	GCPtr, (uint64_t)PdeDst.u));
3931	cErrors++;
3932	continue;
3933	}
3934
3935	/* iterate the page table. */
3936	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3937	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3938	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3939	# else
3940	const unsigned offPTSrc = 0;
3941	# endif
3942	for (unsigned iPT = 0, off = 0;
3943	iPT < RT_ELEMENTS(pPTDst->a);
3944	iPT++, off += PAGE_SIZE)
3945	{
3946	const SHWPTE PteDst = pPTDst->a[iPT];
3947
3948	/* skip not-present and dirty tracked entries. */
3949	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3950	continue;
3951	Assert(SHW_PTE_IS_P(PteDst));
3952
3953	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3954	if (!PteSrc.n.u1Present)
3955	{
3956	# ifdef IN_RING3
3957	PGMAssertHandlerAndFlagsInSync(pVM);
3958	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3959	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3960	0, 0, UINT64_MAX, 99, NULL);
3961	# endif
3962	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3963	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3964	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3965	cErrors++;
3966	continue;
3967	}
3968
3969	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3970	# if 1 /** @todo sync accessed bit properly... */
3971	fIgnoreFlags \|= X86_PTE_A;
3972	# endif
3973
3974	/* match the physical addresses */
3975	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3976	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
3977
3978	# ifdef IN_RING3
3979	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3980	if (RT_FAILURE(rc))
3981	{
3982	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3983	{
3984	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3985	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3986	cErrors++;
3987	continue;
3988	}
3989	}
3990	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3991	{
3992	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3993	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3994	cErrors++;
3995	continue;
3996	}
3997	# endif
3998
3999	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4000	if (!pPhysPage)
4001	{
4002	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4003	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4004	{
4005	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4006	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4007	cErrors++;
4008	continue;
4009	}
4010	# endif
4011	if (SHW_PTE_IS_RW(PteDst))
4012	{
4013	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4014	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4015	cErrors++;
4016	}
4017	fIgnoreFlags \|= X86_PTE_RW;
4018	}
4019	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4020	{
4021	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4022	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4023	cErrors++;
4024	continue;
4025	}
4026
4027	/* flags */
4028	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4029	{
4030	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4031	{
4032	if (SHW_PTE_IS_RW(PteDst))
4033	{
4034	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4035	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4036	cErrors++;
4037	continue;
4038	}
4039	fIgnoreFlags \|= X86_PTE_RW;
4040	}
4041	else
4042	{
4043	if ( SHW_PTE_IS_P(PteDst)
4044	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4045	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4046	# endif
4047	)
4048	{
4049	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4050	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4051	cErrors++;
4052	continue;
4053	}
4054	fIgnoreFlags \|= X86_PTE_P;
4055	}
4056	}
4057	else
4058	{
4059	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4060	{
4061	if (SHW_PTE_IS_RW(PteDst))
4062	{
4063	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4064	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4065	cErrors++;
4066	continue;
4067	}
4068	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4069	{
4070	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4071	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4072	cErrors++;
4073	continue;
4074	}
4075	if (SHW_PTE_IS_D(PteDst))
4076	{
4077	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4078	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4079	cErrors++;
4080	}
4081	# if 0 /** @todo sync access bit properly... */
4082	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4083	{
4084	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4085	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4086	cErrors++;
4087	}
4088	fIgnoreFlags \|= X86_PTE_RW;
4089	# else
4090	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4091	# endif
4092	}
4093	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4094	{
4095	/* access bit emulation (not implemented). */
4096	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4097	{
4098	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4100	cErrors++;
4101	continue;
4102	}
4103	if (!SHW_PTE_IS_A(PteDst))
4104	{
4105	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4106	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4107	cErrors++;
4108	}
4109	fIgnoreFlags \|= X86_PTE_P;
4110	}
4111	# ifdef DEBUG_sandervl
4112	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4113	# endif
4114	}
4115
4116	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4117	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4118	)
4119	{
4120	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4121	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4122	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4123	cErrors++;
4124	continue;
4125	}
4126	} /* foreach PTE */
4127	}
4128	else
4129	{
4130	/*
4131	* Big Page.
4132	*/
4133	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4134	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4135	{
4136	if (PdeDst.n.u1Write)
4137	{
4138	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4139	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4140	cErrors++;
4141	continue;
4142	}
4143	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4144	{
4145	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4146	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4147	cErrors++;
4148	continue;
4149	}
4150	# if 0 /** @todo sync access bit properly... */
4151	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4152	{
4153	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4154	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4155	cErrors++;
4156	}
4157	fIgnoreFlags \|= X86_PTE_RW;
4158	# else
4159	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4160	# endif
4161	}
4162	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4163	{
4164	/* access bit emulation (not implemented). */
4165	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4166	{
4167	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4168	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4169	cErrors++;
4170	continue;
4171	}
4172	if (!PdeDst.n.u1Accessed)
4173	{
4174	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4175	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4176	cErrors++;
4177	}
4178	fIgnoreFlags \|= X86_PTE_P;
4179	}
4180
4181	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4182	{
4183	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4184	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4185	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4186	cErrors++;
4187	}
4188
4189	/* iterate the page table. */
4190	for (unsigned iPT = 0, off = 0;
4191	iPT < RT_ELEMENTS(pPTDst->a);
4192	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4193	{
4194	const SHWPTE PteDst = pPTDst->a[iPT];
4195
4196	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4197	{
4198	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4199	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4200	cErrors++;
4201	}
4202
4203	/* skip not-present entries. */
4204	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4205	continue;
4206
4207	fIgnoreFlags = X86_PTE_PAE_PG_MASK_FULL \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4208
4209	/* match the physical addresses */
4210	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4211
4212	# ifdef IN_RING3
4213	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4214	if (RT_FAILURE(rc))
4215	{
4216	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4217	{
4218	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4219	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4220	cErrors++;
4221	}
4222	}
4223	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4224	{
4225	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4226	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4227	cErrors++;
4228	continue;
4229	}
4230	# endif
4231	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4232	if (!pPhysPage)
4233	{
4234	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4235	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4236	{
4237	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4238	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4239	cErrors++;
4240	continue;
4241	}
4242	# endif
4243	if (SHW_PTE_IS_RW(PteDst))
4244	{
4245	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4246	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4247	cErrors++;
4248	}
4249	fIgnoreFlags \|= X86_PTE_RW;
4250	}
4251	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4252	{
4253	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4254	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4255	cErrors++;
4256	continue;
4257	}
4258
4259	/* flags */
4260	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4261	{
4262	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4263	{
4264	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4265	{
4266	if (SHW_PTE_IS_RW(PteDst))
4267	{
4268	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4269	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4270	cErrors++;
4271	continue;
4272	}
4273	fIgnoreFlags \|= X86_PTE_RW;
4274	}
4275	}
4276	else
4277	{
4278	if ( SHW_PTE_IS_P(PteDst)
4279	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4280	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4281	# endif
4282	)
4283	{
4284	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4285	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4286	cErrors++;
4287	continue;
4288	}
4289	fIgnoreFlags \|= X86_PTE_P;
4290	}
4291	}
4292
4293	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4294	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4295	)
4296	{
4297	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4298	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4299	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4300	cErrors++;
4301	continue;
4302	}
4303	} /* for each PTE */
4304	}
4305	}
4306	/* not present */
4307
4308	} /* for each PDE */
4309
4310	} /* for each PDPTE */
4311
4312	} /* for each PML4E */
4313
4314	# ifdef DEBUG
4315	if (cErrors)
4316	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4317	# endif
4318
4319	#endif /* GST == 32BIT, PAE or AMD64 */
4320	return cErrors;
4321
4322	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4323	}
4324	#endif /* VBOX_STRICT */
4325
4326
4327	/**
4328	* Sets up the CR3 for shadow paging
4329	*
4330	* @returns Strict VBox status code.
4331	* @retval VINF_SUCCESS.
4332	*
4333	* @param pVCpu The VMCPU handle.
4334	* @param GCPhysCR3 The physical address in the CR3 register.
4335	*/
4336	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4337	{
4338	PVM pVM = pVCpu->CTX_SUFF(pVM);
4339
4340	/* Update guest paging info. */
4341	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4342	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4343	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4344
4345	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4346
4347	/*
4348	* Map the page CR3 points at.
4349	*/
4350	RTHCPTR HCPtrGuestCR3;
4351	RTHCPHYS HCPhysGuestCR3;
4352	pgmLock(pVM);
4353	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4354	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4355	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4356	/** @todo this needs some reworking wrt. locking? */
4357	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4358	HCPtrGuestCR3 = NIL_RTHCPTR;
4359	int rc = VINF_SUCCESS;
4360	# else
4361	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4362	# endif
4363	pgmUnlock(pVM);
4364	if (RT_SUCCESS(rc))
4365	{
4366	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4367	if (RT_SUCCESS(rc))
4368	{
4369	# ifdef IN_RC
4370	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4371	# endif
4372	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4373	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4374	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4375	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4376	# endif
4377	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4378
4379	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4380	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4381	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4382	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4383	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4384	# endif
4385	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4386	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4387
4388	/*
4389	* Map the 4 PDs too.
4390	*/
4391	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4392	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4393	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4394	{
4395	if (pGuestPDPT->a[i].n.u1Present)
4396	{
4397	RTHCPTR HCPtr;
4398	RTHCPHYS HCPhys;
4399	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4400	pgmLock(pVM);
4401	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4402	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4403	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4404	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4405	HCPtr = NIL_RTHCPTR;
4406	int rc2 = VINF_SUCCESS;
4407	# else
4408	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4409	# endif
4410	pgmUnlock(pVM);
4411	if (RT_SUCCESS(rc2))
4412	{
4413	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4414	AssertRCReturn(rc, rc);
4415
4416	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4417	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4418	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4419	# endif
4420	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4421	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4422	# ifdef IN_RC
4423	PGM_INVL_PG(pVCpu, GCPtr);
4424	# endif
4425	continue;
4426	}
4427	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4428	}
4429
4430	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4431	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4432	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4433	# endif
4434	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4435	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4436	# ifdef IN_RC
4437	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4438	# endif
4439	}
4440
4441	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4442	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4443	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4444	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4445	# endif
4446	# endif
4447	}
4448	else
4449	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4450	}
4451	else
4452	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4453
4454	#else /* prot/real stub */
4455	int rc = VINF_SUCCESS;
4456	#endif
4457
4458	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4459	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4460	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4461	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4462	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4463	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4464
4465	Assert(!pVM->pgm.s.fNestedPaging);
4466
4467	/*
4468	* Update the shadow root page as well since that's not fixed.
4469	*/
4470	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4471	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4472	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4473	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4474	PPGMPOOLPAGE pNewShwPageCR3;
4475
4476	pgmLock(pVM);
4477
4478	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4479	if (pPool->cDirtyPages)
4480	pgmPoolResetDirtyPages(pVM);
4481	# endif
4482
4483	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4484	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4485	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4486	AssertFatalRC(rc);
4487	rc = VINF_SUCCESS;
4488
4489	# ifdef IN_RC
4490	/*
4491	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4492	* state will be inconsistent! Flush important things now while
4493	* we still can and then make sure there are no ring-3 calls.
4494	*/
4495	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4496	VMMRZCallRing3Disable(pVCpu);
4497	# endif
4498
4499	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4500	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4501	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4502	# ifdef IN_RING0
4503	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4504	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4505	# elif defined(IN_RC)
4506	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4507	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4508	# else
4509	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4510	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4511	# endif
4512
4513	# ifndef PGM_WITHOUT_MAPPINGS
4514	/*
4515	* Apply all hypervisor mappings to the new CR3.
4516	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4517	* make sure we check for conflicts in the new CR3 root.
4518	*/
4519	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4520	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4521	# endif
4522	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4523	AssertRCReturn(rc, rc);
4524	# endif
4525
4526	/* Set the current hypervisor CR3. */
4527	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4528	SELMShadowCR3Changed(pVM, pVCpu);
4529
4530	# ifdef IN_RC
4531	/* NOTE: The state is consistent again. */
4532	VMMRZCallRing3Enable(pVCpu);
4533	# endif
4534
4535	/* Clean up the old CR3 root. */
4536	if ( pOldShwPageCR3
4537	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4538	{
4539	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4540	# ifndef PGM_WITHOUT_MAPPINGS
4541	/* Remove the hypervisor mappings from the shadow page table. */
4542	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4543	# endif
4544	/* Mark the page as unlocked; allow flushing again. */
4545	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4546
4547	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4548	}
4549	pgmUnlock(pVM);
4550	# endif
4551
4552	return rc;
4553	}
4554
4555	/**
4556	* Unmaps the shadow CR3.
4557	*
4558	* @returns VBox status, no specials.
4559	* @param pVCpu The VMCPU handle.
4560	*/
4561	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4562	{
4563	LogFlow(("UnmapCR3\n"));
4564
4565	int rc = VINF_SUCCESS;
4566	PVM pVM = pVCpu->CTX_SUFF(pVM);
4567
4568	/*
4569	* Update guest paging info.
4570	*/
4571	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4572	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4573	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4574	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4575	# endif
4576	pVCpu->pgm.s.pGst32BitPdRC = 0;
4577
4578	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4579	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4580	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4581	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4582	# endif
4583	pVCpu->pgm.s.pGstPaePdptRC = 0;
4584	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4585	{
4586	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4587	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4588	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4589	# endif
4590	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4591	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4592	}
4593
4594	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4595	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4596	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4597	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4598	# endif
4599
4600	#else /* prot/real mode stub */
4601	/* nothing to do */
4602	#endif
4603
4604	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4605	/*
4606	* Update shadow paging info.
4607	*/
4608	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4609	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4610	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4611
4612	# if PGM_GST_TYPE != PGM_TYPE_REAL
4613	Assert(!pVM->pgm.s.fNestedPaging);
4614	# endif
4615
4616	pgmLock(pVM);
4617
4618	# ifndef PGM_WITHOUT_MAPPINGS
4619	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4620	/* Remove the hypervisor mappings from the shadow page table. */
4621	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4622	# endif
4623
4624	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4625	{
4626	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4627
4628	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4629
4630	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4631	if (pPool->cDirtyPages)
4632	pgmPoolResetDirtyPages(pVM);
4633	# endif
4634
4635	/* Mark the page as unlocked; allow flushing again. */
4636	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4637
4638	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4639	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4640	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4641	pVCpu->pgm.s.pShwPageCR3RC = 0;
4642	pVCpu->pgm.s.iShwUser = 0;
4643	pVCpu->pgm.s.iShwUserTable = 0;
4644	}
4645	pgmUnlock(pVM);
4646	# endif
4647	#endif /* !IN_RC*/
4648
4649	return rc;
4650	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 32009

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