PGMAllBth.h@ 32027

Last change on this file since 32027 was 32027, checked in by vboxsync, 14 years ago
PGM/SyncPage: To be on the safe side, always sync the target page when doing multiple pages.
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File size: 199.4 KB

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1	/* $Id: PGMAllBth.h 32027 2010-08-27 09:17:42Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK_FULL) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK_FULL));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	}
561	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
562
563	/*
564	* Fetch the guest PDE, PDPE and PML4E.
565	*/
566	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
567	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
568	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
569
570	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
571	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
572	PX86PDPAE pPDDst;
573	# if PGM_GST_TYPE == PGM_TYPE_PAE
574	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
575	# else
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
577	# endif
578	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
579
580	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
581	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
582	PX86PDPAE pPDDst;
583	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
584	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
585	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
586	# else
587	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
588	# endif
589	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
590
591	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
592	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
593	PEPTPD pPDDst;
594	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
596	# endif
597	Assert(pPDDst);
598
599	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
600	/*
601	* Dirty page handling.
602	*
603	* If we successfully correct the write protection fault due to dirty bit
604	* tracking, then return immediately.
605	*/
606	if (uErr & X86_TRAP_PF_RW) /* write fault? */
607	{
608	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
609	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
610	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
612	{
613	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
614	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
615	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
616	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
617	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
618	return VINF_SUCCESS;
619	}
620	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
621	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
622	}
623
624	# if 0 /* rarely useful; leave for debugging. */
625	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
626	# endif
627	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
628
629	/*
630	* A common case is the not-present error caused by lazy page table syncing.
631	*
632	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
633	* here so we can safely assume that the shadow PT is present when calling
634	* SyncPage later.
635	*
636	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
637	* of mapping conflict and defer to SyncCR3 in R3.
638	* (Again, we do NOT support access handlers for non-present guest pages.)
639	*
640	*/
641	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
642	Assert(GstWalk.Pde.n.u1Present);
643	# endif
644	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
645	&& !pPDDst->a[iPDDst].n.u1Present)
646	{
647	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
648	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
649	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
650	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
651	# else
652	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
653	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
654	# endif
655	if (RT_SUCCESS(rc))
656	return rc;
657	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
658	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
659	return VINF_PGM_SYNC_CR3;
660	}
661
662	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
663	/*
664	* Check if this address is within any of our mappings.
665	*
666	* This is very fast and it's gonna save us a bit of effort below and prevent
667	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
668	* (BTW, it's impossible to have physical access handlers in a mapping.)
669	*/
670	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
671	{
672	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
673	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
674	{
675	if (pvFault < pMapping->GCPtr)
676	break;
677	if (pvFault - pMapping->GCPtr < pMapping->cb)
678	{
679	/*
680	* The first thing we check is if we've got an undetected conflict.
681	*/
682	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
683	{
684	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
685	while (iPT-- > 0)
686	if (GstWalk.pPde[iPT].n.u1Present)
687	{
688	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
689	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
690	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
691	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
692	return VINF_PGM_SYNC_CR3;
693	}
694	}
695
696	/*
697	* Check if the fault address is in a virtual page access handler range.
698	*/
699	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
700	if ( pCur
701	&& pvFault - pCur->Core.Key < pCur->cb
702	&& uErr & X86_TRAP_PF_RW)
703	{
704	# ifdef IN_RC
705	STAM_PROFILE_START(&pCur->Stat, h);
706	pgmUnlock(pVM);
707	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
708	pgmLock(pVM);
709	STAM_PROFILE_STOP(&pCur->Stat, h);
710	# else
711	AssertFailed();
712	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
713	# endif
714	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
715	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
716	return rc;
717	}
718
719	/*
720	* Pretend we're not here and let the guest handle the trap.
721	*/
722	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
723	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
724	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
725	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
726	return VINF_EM_RAW_GUEST_TRAP;
727	}
728	}
729	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
730	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
731
732	/*
733	* Check if this fault address is flagged for special treatment,
734	* which means we'll have to figure out the physical address and
735	* check flags associated with it.
736	*
737	* ASSUME that we can limit any special access handling to pages
738	* in page tables which the guest believes to be present.
739	*/
740	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
741	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
742	# else
743	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
745	PPGMPAGE pPage;
746	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
747	if (RT_FAILURE(rc))
748	{
749	/*
750	* When the guest accesses invalid physical memory (e.g. probing
751	* of RAM or accessing a remapped MMIO range), then we'll fall
752	* back to the recompiler to emulate the instruction.
753	*/
754	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
755	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
756	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
757	return VINF_EM_RAW_EMULATE_INSTR;
758	}
759
760	/*
761	* Any handlers for this page?
762	*/
763	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
764	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
765	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
766	&GstWalk));
767	# else
768	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
769	# endif
770
771	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
772
773	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
774	if (uErr & X86_TRAP_PF_P)
775	{
776	/*
777	* The page isn't marked, but it might still be monitored by a virtual page access handler.
778	* (ASSUMES no temporary disabling of virtual handlers.)
779	*/
780	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
781	* we should correct both the shadow page table and physical memory flags, and not only check for
782	* accesses within the handler region but for access to pages with virtual handlers. */
783	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
784	if (pCur)
785	{
786	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
787	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
788	\|\| !(uErr & X86_TRAP_PF_P)
789	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
790	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
791
792	if ( pvFault - pCur->Core.Key < pCur->cb
793	&& ( uErr & X86_TRAP_PF_RW
794	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
795	{
796	# ifdef IN_RC
797	STAM_PROFILE_START(&pCur->Stat, h);
798	pgmUnlock(pVM);
799	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
800	pgmLock(pVM);
801	STAM_PROFILE_STOP(&pCur->Stat, h);
802	# else
803	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
804	# endif
805	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
806	return rc;
807	}
808	}
809	}
810	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
811
812	/*
813	* We are here only if page is present in Guest page tables and
814	* trap is not handled by our handlers.
815	*
816	* Check it for page out-of-sync situation.
817	*/
818	if (!(uErr & X86_TRAP_PF_P))
819	{
820	/*
821	* Page is not present in our page tables. Try to sync it!
822	*/
823	if (uErr & X86_TRAP_PF_US)
824	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
825	else /* supervisor */
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
827
828	if (PGM_PAGE_IS_BALLOONED(pPage))
829	{
830	/* Emulate reads from ballooned pages as they are not present in
831	our shadow page tables. (Required for e.g. Solaris guests; soft
832	ecc, random nr generator.) */
833	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
834	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
835	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
836	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
837	return rc;
838	}
839
840	# if defined(LOG_ENABLED) && !defined(IN_RING0)
841	RTGCPHYS GCPhys2;
842	uint64_t fPageGst2;
843	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
844	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
845	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
846	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
847	# else
848	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
849	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
850	# endif
851	# endif /* LOG_ENABLED */
852
853	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
854	if ( !GstWalk.Core.fEffectiveUS
855	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
856	{
857	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
858	if ( pvFault == (RTGCPTR)pRegFrame->eip
859	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
860	# ifdef CSAM_DETECT_NEW_CODE_PAGES
861	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
862	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
863	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
864	)
865	{
866	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
867	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
868	if (rc != VINF_SUCCESS)
869	{
870	/*
871	* CSAM needs to perform a job in ring 3.
872	*
873	* Sync the page before going to the host context; otherwise we'll end up in a loop if
874	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
875	*/
876	LogFlow(("CSAM ring 3 job\n"));
877	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
878	AssertRC(rc2);
879
880	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
881	return rc;
882	}
883	}
884	# ifdef CSAM_DETECT_NEW_CODE_PAGES
885	else if ( uErr == X86_TRAP_PF_RW
886	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
887	&& pRegFrame->ecx < 0x10000)
888	{
889	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
890	* to detect loading of new code pages.
891	*/
892
893	/*
894	* Decode the instruction.
895	*/
896	RTGCPTR PC;
897	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
898	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
899	if (rc == VINF_SUCCESS)
900	{
901	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
902	uint32_t cbOp;
903	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
904
905	/* For now we'll restrict this to rep movsw/d instructions */
906	if ( rc == VINF_SUCCESS
907	&& pDis->pCurInstr->opcode == OP_MOVSWD
908	&& (pDis->prefix & PREFIX_REP))
909	{
910	CSAMMarkPossibleCodePage(pVM, pvFault);
911	}
912	}
913	}
914	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
915
916	/*
917	* Mark this page as safe.
918	*/
919	/** @todo not correct for pages that contain both code and data!! */
920	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
921	CSAMMarkPage(pVM, pvFault, true);
922	}
923	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
924	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
925	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
926	# else
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# endif
929	if (RT_SUCCESS(rc))
930	{
931	/* The page was successfully synced, return to the guest. */
932	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
933	return VINF_SUCCESS;
934	}
935	}
936	else /* uErr & X86_TRAP_PF_P: */
937	{
938	/*
939	* Write protected pages are made writable when the guest makes the
940	* first write to it. This happens for pages that are shared, write
941	* monitored or not yet allocated.
942	*
943	* We may also end up here when CR0.WP=0 in the guest.
944	*
945	* Also, a side effect of not flushing global PDEs are out of sync
946	* pages due to physical monitored regions, that are no longer valid.
947	* Assume for now it only applies to the read/write flag.
948	*/
949	if (uErr & X86_TRAP_PF_RW)
950	{
951	/*
952	* Check if it is a read-only page.
953	*/
954	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
955	{
956	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
957	Assert(!PGM_PAGE_IS_ZERO(pPage));
958	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
959	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
960
961	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
962	if (rc != VINF_SUCCESS)
963	{
964	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
965	return rc;
966	}
967	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
968	return VINF_EM_NO_MEMORY;
969	}
970
971	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
972	/*
973	* Check to see if we need to emulate the instruction if CR0.WP=0.
974	*/
975	if ( !GstWalk.Core.fEffectiveRW
976	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
977	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
978	{
979	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
980	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
981	if (RT_SUCCESS(rc))
982	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
983	else
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
985	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
986	return rc;
987	}
988	# endif
989	/// @todo count the above case; else
990	if (uErr & X86_TRAP_PF_US)
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
992	else /* supervisor */
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
994
995	/*
996	* Sync the page.
997	*
998	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
999	* page is not present, which is not true in this case.
1000	*/
1001	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1002	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1003	# else
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1005	# endif
1006	if (RT_SUCCESS(rc))
1007	{
1008	/*
1009	* Page was successfully synced, return to guest but invalidate
1010	* the TLB first as the page is very likely to be in it.
1011	*/
1012	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1013	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1014	# else
1015	PGM_INVL_PG(pVCpu, pvFault);
1016	# endif
1017	# ifdef VBOX_STRICT
1018	RTGCPHYS GCPhys2;
1019	uint64_t fPageGst;
1020	if (!pVM->pgm.s.fNestedPaging)
1021	{
1022	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1023	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1024	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1025	}
1026	uint64_t fPageShw;
1027	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1028	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1029	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1030	# endif /* VBOX_STRICT */
1031	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1032	return VINF_SUCCESS;
1033	}
1034	}
1035	/** @todo else: why are we here? */
1036
1037	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1038	/*
1039	* Check for VMM page flags vs. Guest page flags consistency.
1040	* Currently only for debug purposes.
1041	*/
1042	if (RT_SUCCESS(rc))
1043	{
1044	/* Get guest page flags. */
1045	uint64_t fPageGst;
1046	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1047	if (RT_SUCCESS(rc))
1048	{
1049	uint64_t fPageShw;
1050	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1051
1052	/*
1053	* Compare page flags.
1054	* Note: we have AVL, A, D bits desynched.
1055	*/
1056	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1057	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1058	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1059	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1060	}
1061	else
1062	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1063	}
1064	else
1065	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1066	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1067	}
1068
1069
1070	/*
1071	* If we get here it is because something failed above, i.e. most like guru
1072	* meditiation time.
1073	*/
1074	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1075	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1076	return rc;
1077
1078	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1079	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1080	return VERR_INTERNAL_ERROR;
1081	# endif
1082	}
1083	#endif /* !IN_RING3 */
1084
1085
1086	/**
1087	* Emulation of the invlpg instruction.
1088	*
1089	*
1090	* @returns VBox status code.
1091	*
1092	* @param pVCpu The VMCPU handle.
1093	* @param GCPtrPage Page to invalidate.
1094	*
1095	* @remark ASSUMES that the guest is updating before invalidating. This order
1096	* isn't required by the CPU, so this is speculative and could cause
1097	* trouble.
1098	* @remark No TLB shootdown is done on any other VCPU as we assume that
1099	* invlpg emulation is the only reason for calling this function.
1100	* (The guest has to shoot down TLB entries on other CPUs itself)
1101	* Currently true, but keep in mind!
1102	*
1103	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1104	*/
1105	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1106	{
1107	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1108	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1109	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1110	int rc;
1111	PVM pVM = pVCpu->CTX_SUFF(pVM);
1112	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1113
1114	Assert(PGMIsLockOwner(pVM));
1115
1116	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1117
1118	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1119	if (pPool->cDirtyPages)
1120	pgmPoolResetDirtyPages(pVM);
1121	# endif
1122
1123	/*
1124	* Get the shadow PD entry and skip out if this PD isn't present.
1125	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1126	*/
1127	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1128	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1129	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1130
1131	/* Fetch the pgm pool shadow descriptor. */
1132	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1133	Assert(pShwPde);
1134
1135	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1136	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1137	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1138
1139	/* If the shadow PDPE isn't present, then skip the invalidate. */
1140	if (!pPdptDst->a[iPdpt].n.u1Present)
1141	{
1142	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1143	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1144	return VINF_SUCCESS;
1145	}
1146
1147	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1148	PPGMPOOLPAGE pShwPde = NULL;
1149	PX86PDPAE pPDDst;
1150
1151	/* Fetch the pgm pool shadow descriptor. */
1152	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1153	AssertRCSuccessReturn(rc, rc);
1154	Assert(pShwPde);
1155
1156	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1157	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1158
1159	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1160	/* PML4 */
1161	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1162	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1163	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1164	PX86PDPAE pPDDst;
1165	PX86PDPT pPdptDst;
1166	PX86PML4E pPml4eDst;
1167	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1168	if (rc != VINF_SUCCESS)
1169	{
1170	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1171	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1172	return VINF_SUCCESS;
1173	}
1174	Assert(pPDDst);
1175
1176	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1177	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1178
1179	if (!pPdpeDst->n.u1Present)
1180	{
1181	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1182	return VINF_SUCCESS;
1183	}
1184
1185	/* Fetch the pgm pool shadow descriptor. */
1186	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1187	Assert(pShwPde);
1188
1189	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1190
1191	const SHWPDE PdeDst = *pPdeDst;
1192	if (!PdeDst.n.u1Present)
1193	{
1194	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1195	return VINF_SUCCESS;
1196	}
1197
1198	/*
1199	* Get the guest PD entry and calc big page.
1200	*/
1201	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1202	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1203	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1204	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1205	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1206	unsigned iPDSrc = 0;
1207	# if PGM_GST_TYPE == PGM_TYPE_PAE
1208	X86PDPE PdpeSrcIgn;
1209	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1210	# else /* AMD64 */
1211	PX86PML4E pPml4eSrcIgn;
1212	X86PDPE PdpeSrcIgn;
1213	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1214	# endif
1215	GSTPDE PdeSrc;
1216
1217	if (pPDSrc)
1218	PdeSrc = pPDSrc->a[iPDSrc];
1219	else
1220	PdeSrc.u = 0;
1221	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1222	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1223
1224	# ifdef IN_RING3
1225	/*
1226	* If a CR3 Sync is pending we may ignore the invalidate page operation
1227	* depending on the kind of sync and if it's a global page or not.
1228	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1229	*/
1230	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1231	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1232	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1233	&& fIsBigPage
1234	&& PdeSrc.b.u1Global
1235	)
1236	)
1237	# else
1238	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1239	# endif
1240	{
1241	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1242	return VINF_SUCCESS;
1243	}
1244	# endif /* IN_RING3 */
1245
1246	/*
1247	* Deal with the Guest PDE.
1248	*/
1249	rc = VINF_SUCCESS;
1250	if (PdeSrc.n.u1Present)
1251	{
1252	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1253	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1254	# ifndef PGM_WITHOUT_MAPPING
1255	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1256	{
1257	/*
1258	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1259	*/
1260	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1261	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1263	}
1264	else
1265	# endif /* !PGM_WITHOUT_MAPPING */
1266	if (!fIsBigPage)
1267	{
1268	/*
1269	* 4KB - page.
1270	*/
1271	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1272	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1273
1274	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1275	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1276	if (pShwPage->cModifications)
1277	pShwPage->cModifications = 1;
1278	# endif
1279
1280	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1281	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1282	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1283	# endif
1284	if (pShwPage->GCPhys == GCPhys)
1285	{
1286	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1287	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1288	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1289	if (pPT->a[iPTEDst].n.u1Present)
1290	{
1291	/* This is very unlikely with caching/monitoring enabled. */
1292	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1293	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1294	}
1295	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1296	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1297	if (RT_SUCCESS(rc))
1298	rc = VINF_SUCCESS;
1299	# endif
1300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1301	PGM_INVL_PG(pVCpu, GCPtrPage);
1302	}
1303	else
1304	{
1305	/*
1306	* The page table address changed.
1307	*/
1308	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1309	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1310	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1311	ASMAtomicWriteSize(pPdeDst, 0);
1312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1313	PGM_INVL_VCPU_TLBS(pVCpu);
1314	}
1315	}
1316	else
1317	{
1318	/*
1319	* 2/4MB - page.
1320	*/
1321	/* Before freeing the page, check if anything really changed. */
1322	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1323	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1324	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1325	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1326	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1327	# endif
1328	if ( pShwPage->GCPhys == GCPhys
1329	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1330	{
1331	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1332	/** @todo This test is wrong as it cannot check the G bit!
1333	* FIXME */
1334	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1335	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1336	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1337	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1338	{
1339	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1340	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1341	return VINF_SUCCESS;
1342	}
1343	}
1344
1345	/*
1346	* Ok, the page table is present and it's been changed in the guest.
1347	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1348	* We could do this for some flushes in GC too, but we need an algorithm for
1349	* deciding which 4MB pages containing code likely to be executed very soon.
1350	*/
1351	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1352	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1353	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1354	ASMAtomicWriteSize(pPdeDst, 0);
1355	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1356	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1357	}
1358	}
1359	else
1360	{
1361	/*
1362	* Page directory is not present, mark shadow PDE not present.
1363	*/
1364	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1365	{
1366	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1367	ASMAtomicWriteSize(pPdeDst, 0);
1368	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1369	PGM_INVL_PG(pVCpu, GCPtrPage);
1370	}
1371	else
1372	{
1373	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1374	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1375	}
1376	}
1377	return rc;
1378
1379	#else /* guest real and protected mode */
1380	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1381	return VINF_SUCCESS;
1382	#endif
1383	}
1384
1385
1386	/**
1387	* Update the tracking of shadowed pages.
1388	*
1389	* @param pVCpu The VMCPU handle.
1390	* @param pShwPage The shadow page.
1391	* @param HCPhys The physical page we is being dereferenced.
1392	* @param iPte Shadow PTE index
1393	*/
1394	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1395	{
1396	PVM pVM = pVCpu->CTX_SUFF(pVM);
1397
1398	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1399	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1400
1401	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1402	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1403	* 2. write protect all shadowed pages. I.e. implement caching.
1404	*/
1405	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1406
1407	/*
1408	* Find the guest address.
1409	*/
1410	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1411	pRam;
1412	pRam = pRam->CTX_SUFF(pNext))
1413	{
1414	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1415	while (iPage-- > 0)
1416	{
1417	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1418	{
1419	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1420
1421	Assert(pShwPage->cPresent);
1422	Assert(pPool->cPresent);
1423	pShwPage->cPresent--;
1424	pPool->cPresent--;
1425
1426	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1427	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1428	return;
1429	}
1430	}
1431	}
1432
1433	for (;;)
1434	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1435	}
1436
1437
1438	/**
1439	* Update the tracking of shadowed pages.
1440	*
1441	* @param pVCpu The VMCPU handle.
1442	* @param pShwPage The shadow page.
1443	* @param u16 The top 16-bit of the pPage->HCPhys.
1444	* @param pPage Pointer to the guest page. this will be modified.
1445	* @param iPTDst The index into the shadow table.
1446	*/
1447	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1448	{
1449	PVM pVM = pVCpu->CTX_SUFF(pVM);
1450
1451	/*
1452	* Just deal with the simple first time here.
1453	*/
1454	if (!u16)
1455	{
1456	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1457	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1458	/* Save the page table index. */
1459	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1460	}
1461	else
1462	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1463
1464	/* write back */
1465	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1466	PGM_PAGE_SET_TRACKING(pPage, u16);
1467
1468	/* update statistics. */
1469	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1470	pShwPage->cPresent++;
1471	if (pShwPage->iFirstPresent > iPTDst)
1472	pShwPage->iFirstPresent = iPTDst;
1473	}
1474
1475
1476	/**
1477	* Modifies a shadow PTE to account for access handlers.
1478	*
1479	* @param pVM The VM handle.
1480	* @param pPage The page in question.
1481	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1482	* A (accessed) bit so it can be emulated correctly.
1483	* @param pPteDst The shadow PTE (output). This is temporary storage and
1484	* does not need to be set atomically.
1485	*/
1486	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1487	{
1488	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1489	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1490	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1491	{
1492	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1493	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1494	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1495	pPteDst->n.u1Present = 1;
1496	pPteDst->n.u1Execute = 1;
1497	pPteDst->n.u1IgnorePAT = 1;
1498	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1499	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1500	#else
1501	if (fPteSrc & X86_PTE_A)
1502	{
1503	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1504	SHW_PTE_SET_RO(*pPteDst);
1505	}
1506	else
1507	SHW_PTE_SET(*pPteDst, 0);
1508	#endif
1509	}
1510	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1511	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1512	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1513	&& ( BTH_IS_NP_ACTIVE(pVM)
1514	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1515	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1516	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1517	# endif
1518	)
1519	{
1520	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1521	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1522	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1523	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1524	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1525	pPteDst->n.u1Present = 0;
1526	pPteDst->n.u1Write = 1;
1527	pPteDst->n.u1Execute = 0;
1528	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1529	pPteDst->n.u3EMT = 7;
1530	# else
1531	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1532	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1533	# endif
1534	}
1535	# endif
1536	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1537	else
1538	{
1539	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1540	SHW_PTE_SET(*pPteDst, 0);
1541	}
1542	/** @todo count these kinds of entries. */
1543	}
1544
1545
1546	/**
1547	* Creates a 4K shadow page for a guest page.
1548	*
1549	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1550	* physical address. The PdeSrc argument only the flags are used. No page
1551	* structured will be mapped in this function.
1552	*
1553	* @param pVCpu The VMCPU handle.
1554	* @param pPteDst Destination page table entry.
1555	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1556	* Can safely assume that only the flags are being used.
1557	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1558	* @param pShwPage Pointer to the shadow page.
1559	* @param iPTDst The index into the shadow table.
1560	*
1561	* @remark Not used for 2/4MB pages!
1562	*/
1563	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1564	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1565	{
1566	if ( PteSrc.n.u1Present
1567	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1568	{
1569	PVM pVM = pVCpu->CTX_SUFF(pVM);
1570
1571	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1572	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1573	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64)
1574	if (pShwPage->fDirty)
1575	{
1576	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1577	PX86PTPAE pGstPT;
1578
1579	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty][0];
1580	pGstPT->a[iPTDst].u = PteSrc.u;
1581	}
1582	# endif
1583	/*
1584	* Find the ram range.
1585	*/
1586	PPGMPAGE pPage;
1587	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc), &pPage);
1588	if (RT_SUCCESS(rc))
1589	{
1590	/* Ignore ballooned pages.
1591	Don't return errors or use a fatal assert here as part of a
1592	shadow sync range might included ballooned pages. */
1593	if (PGM_PAGE_IS_BALLOONED(pPage))
1594	{
1595	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1596	return;
1597	}
1598
1599	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1600	/* Make the page writable if necessary. */
1601	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1602	&& ( PGM_PAGE_IS_ZERO(pPage)
1603	\|\| ( PteSrc.n.u1Write
1604	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1605	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1606	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1607	# endif
1608	# ifdef VBOX_WITH_PAGE_SHARING
1609	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1610	# endif
1611	)
1612	)
1613	)
1614	{
1615	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
1616	AssertRC(rc);
1617	}
1618	#endif
1619
1620	/*
1621	* Make page table entry.
1622	*/
1623	SHWPTE PteDst;
1624	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1625	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc), &PteDst);
1626	else
1627	{
1628	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1629	/*
1630	* If the page or page directory entry is not marked accessed,
1631	* we mark the page not present.
1632	*/
1633	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1634	{
1635	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1636	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1637	SHW_PTE_SET(PteDst, 0);
1638	}
1639	/*
1640	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1641	* when the page is modified.
1642	*/
1643	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1644	{
1645	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1646	SHW_PTE_SET(PteDst,
1647	GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc)
1648	\| PGM_PAGE_GET_HCPHYS(pPage)
1649	\| PGM_PTFLAGS_TRACK_DIRTY);
1650	SHW_PTE_SET_RO(PteDst);
1651	}
1652	else
1653	#endif
1654	{
1655	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1656	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1657	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1658	PteDst.n.u1Present = 1;
1659	PteDst.n.u1Write = 1;
1660	PteDst.n.u1Execute = 1;
1661	PteDst.n.u1IgnorePAT = 1;
1662	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1663	/* PteDst.n.u1Size = 0 */
1664	#else
1665	SHW_PTE_SET(PteDst, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1666	#endif
1667	}
1668
1669	/*
1670	* Make sure only allocated pages are mapped writable.
1671	*/
1672	if ( SHW_PTE_IS_P_RW(PteDst)
1673	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1674	{
1675	/* Still applies to shared pages. */
1676	Assert(!PGM_PAGE_IS_ZERO(pPage));
1677	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1678	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)GST_GET_PTE_GCPHYS(PteSrc), pPage, iPTDst));
1679	}
1680	}
1681
1682	/*
1683	* Keep user track up to date.
1684	*/
1685	if (SHW_PTE_IS_P(PteDst))
1686	{
1687	if (!SHW_PTE_IS_P(*pPteDst))
1688	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1689	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1690	{
1691	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1692	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1693	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1694	}
1695	}
1696	else if (SHW_PTE_IS_P(*pPteDst))
1697	{
1698	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1699	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1700	}
1701
1702	/*
1703	* Update statistics and commit the entry.
1704	*/
1705	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1706	if (!PteSrc.n.u1Global)
1707	pShwPage->fSeenNonGlobal = true;
1708	#endif
1709	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1710	return;
1711	}
1712
1713	/** @todo count these three different kinds. */
1714	Log2(("SyncPageWorker: invalid address in Pte\n"));
1715	}
1716	else if (!PteSrc.n.u1Present)
1717	Log2(("SyncPageWorker: page not present in Pte\n"));
1718	else
1719	Log2(("SyncPageWorker: invalid Pte\n"));
1720
1721	/*
1722	* The page is not present or the PTE is bad. Replace the shadow PTE by
1723	* an empty entry, making sure to keep the user tracking up to date.
1724	*/
1725	if (SHW_PTE_IS_P(*pPteDst))
1726	{
1727	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1728	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1729	}
1730	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1731	}
1732
1733
1734	/**
1735	* Syncs a guest OS page.
1736	*
1737	* There are no conflicts at this point, neither is there any need for
1738	* page table allocations.
1739	*
1740	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1741	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1742	*
1743	* @returns VBox status code.
1744	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1745	* @param pVCpu The VMCPU handle.
1746	* @param PdeSrc Page directory entry of the guest.
1747	* @param GCPtrPage Guest context page address.
1748	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1749	* @param uErr Fault error (X86_TRAP_PF_*).
1750	*/
1751	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1752	{
1753	PVM pVM = pVCpu->CTX_SUFF(pVM);
1754	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1755	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1756
1757	Assert(PGMIsLockOwner(pVM));
1758
1759	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1760	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1761	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1762	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1763	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1764
1765	/*
1766	* Assert preconditions.
1767	*/
1768	Assert(PdeSrc.n.u1Present);
1769	Assert(cPages);
1770	# if 0 /* rarely useful; leave for debugging. */
1771	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1772	# endif
1773
1774	/*
1775	* Get the shadow PDE, find the shadow page table in the pool.
1776	*/
1777	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1778	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1779	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1780
1781	/* Fetch the pgm pool shadow descriptor. */
1782	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1783	Assert(pShwPde);
1784
1785	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1786	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1787	PPGMPOOLPAGE pShwPde = NULL;
1788	PX86PDPAE pPDDst;
1789
1790	/* Fetch the pgm pool shadow descriptor. */
1791	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1792	AssertRCSuccessReturn(rc2, rc2);
1793	Assert(pShwPde);
1794
1795	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1796	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1797
1798	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1799	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1800	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1801	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1802	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1803
1804	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1805	AssertRCSuccessReturn(rc2, rc2);
1806	Assert(pPDDst && pPdptDst);
1807	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1808	# endif
1809	SHWPDE PdeDst = *pPdeDst;
1810
1811	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
1812	if (!PdeDst.n.u1Present)
1813	{
1814	LogAlways(("CPU%d: SyncPage: Pde at %RGv changed behind our back! (pPdeDst=%p/%RX64)\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u));
1815	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE p=%p/%RX64\n", pPdeDst, (uint64_t)PdeDst.u));
1816	return VINF_SUCCESS; /* force the instruction to be executed again. */
1817	}
1818
1819	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1820	Assert(pShwPage);
1821
1822	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1823	/* Fetch the pgm pool shadow descriptor. */
1824	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1825	Assert(pShwPde);
1826	# endif
1827
1828	/*
1829	* Check that the page is present and that the shadow PDE isn't out of sync.
1830	*/
1831	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1832	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1833	RTGCPHYS GCPhys;
1834	if (!fBigPage)
1835	{
1836	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1837	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1838	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1839	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1840	# endif
1841	}
1842	else
1843	{
1844	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1845	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1846	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1847	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1848	# endif
1849	}
1850	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1851	if ( fPdeValid
1852	&& pShwPage->GCPhys == GCPhys
1853	&& PdeSrc.n.u1Present
1854	&& PdeSrc.n.u1User == PdeDst.n.u1User
1855	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1856	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1857	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1858	# endif
1859	)
1860	{
1861	/*
1862	* Check that the PDE is marked accessed already.
1863	* Since we set the accessed bit before getting here on a #PF, this
1864	* check is only meant for dealing with non-#PF'ing paths.
1865	*/
1866	if (PdeSrc.n.u1Accessed)
1867	{
1868	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1869	if (!fBigPage)
1870	{
1871	/*
1872	* 4KB Page - Map the guest page table.
1873	*/
1874	PGSTPT pPTSrc;
1875	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1876	if (RT_SUCCESS(rc))
1877	{
1878	# ifdef PGM_SYNC_N_PAGES
1879	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1880	if ( cPages > 1
1881	&& !(uErr & X86_TRAP_PF_P)
1882	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1883	{
1884	/*
1885	* This code path is currently only taken when the caller is PGMTrap0eHandler
1886	* for non-present pages!
1887	*
1888	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1889	* deal with locality.
1890	*/
1891	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1892	const unsigned iPTDstPage = iPTDst;
1893	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1894	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1895	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1896	# else
1897	const unsigned offPTSrc = 0;
1898	# endif
1899	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1900	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1901	iPTDst = 0;
1902	else
1903	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1904	for (; iPTDst < iPTDstEnd; iPTDst++)
1905	{
1906	if ( !SHW_PTE_IS_P(pPTDst->a[iPTDst])
1907	\|\| iPTDst == iPTDstPage) /* always sync GCPtrPage */
1908	{
1909	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1910	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1911	NOREF(GCPtrCurPage);
1912	#ifndef IN_RING0
1913	/*
1914	* Assuming kernel code will be marked as supervisor - and not as user level
1915	* and executed using a conforming code selector - And marked as readonly.
1916	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1917	*/
1918	PPGMPAGE pPage;
1919	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1920	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1921	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1922	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1923	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1924	)
1925	#endif /* else: CSAM not active */
1926	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1927	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1928	GCPtrCurPage, PteSrc.n.u1Present,
1929	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1930	PteSrc.n.u1User & PdeSrc.n.u1User,
1931	(uint64_t)PteSrc.u,
1932	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1933	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1934	}
1935	}
1936	}
1937	else
1938	# endif /* PGM_SYNC_N_PAGES */
1939	{
1940	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1941	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1942	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1943	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1944	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1945	GCPtrPage, PteSrc.n.u1Present,
1946	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1947	PteSrc.n.u1User & PdeSrc.n.u1User,
1948	(uint64_t)PteSrc.u,
1949	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1950	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1951	}
1952	}
1953	else /* MMIO or invalid page: emulated in #PF handler. */
1954	{
1955	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1956	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1957	}
1958	}
1959	else
1960	{
1961	/*
1962	* 4/2MB page - lazy syncing shadow 4K pages.
1963	* (There are many causes of getting here, it's no longer only CSAM.)
1964	*/
1965	/* Calculate the GC physical address of this 4KB shadow page. */
1966	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1967	/* Find ram range. */
1968	PPGMPAGE pPage;
1969	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1970	if (RT_SUCCESS(rc))
1971	{
1972	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1973
1974	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1975	/* Try to make the page writable if necessary. */
1976	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1977	&& ( PGM_PAGE_IS_ZERO(pPage)
1978	\|\| ( PdeSrc.n.u1Write
1979	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1980	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1981	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1982	# endif
1983	# ifdef VBOX_WITH_PAGE_SHARING
1984	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1985	# endif
1986	)
1987	)
1988	)
1989	{
1990	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
1991	AssertRC(rc);
1992	}
1993	# endif
1994
1995	/*
1996	* Make shadow PTE entry.
1997	*/
1998	SHWPTE PteDst;
1999	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2000	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2001	else
2002	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2003
2004	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2005	if ( SHW_PTE_IS_P(PteDst)
2006	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2007	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2008
2009	/* Make sure only allocated pages are mapped writable. */
2010	if ( SHW_PTE_IS_P_RW(PteDst)
2011	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2012	{
2013	/* Still applies to shared pages. */
2014	Assert(!PGM_PAGE_IS_ZERO(pPage));
2015	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2016	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2017	}
2018
2019	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2020
2021	/*
2022	* If the page is not flagged as dirty and is writable, then make it read-only
2023	* at PD level, so we can set the dirty bit when the page is modified.
2024	*
2025	* ASSUMES that page access handlers are implemented on page table entry level.
2026	* Thus we will first catch the dirty access and set PDE.D and restart. If
2027	* there is an access handler, we'll trap again and let it work on the problem.
2028	*/
2029	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2030	* As for invlpg, it simply frees the whole shadow PT.
2031	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2032	if ( !PdeSrc.b.u1Dirty
2033	&& PdeSrc.b.u1Write)
2034	{
2035	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2036	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2037	PdeDst.n.u1Write = 0;
2038	}
2039	else
2040	{
2041	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2042	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2043	}
2044	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2045	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2046	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2047	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2048	}
2049	else
2050	{
2051	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2052	/** @todo must wipe the shadow page table entry in this
2053	* case. */
2054	}
2055	}
2056	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2057	return VINF_SUCCESS;
2058	}
2059
2060	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2061	}
2062	else if (fPdeValid)
2063	{
2064	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2065	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2066	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2067	}
2068	else
2069	{
2070	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2071	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2072	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2073	}
2074
2075	/*
2076	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2077	* Yea, I'm lazy.
2078	*/
2079	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2080	ASMAtomicWriteSize(pPdeDst, 0);
2081
2082	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2083	PGM_INVL_VCPU_TLBS(pVCpu);
2084	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2085
2086
2087	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2088	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2089	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2090	&& !defined(IN_RC)
2091
2092	# ifdef PGM_SYNC_N_PAGES
2093	/*
2094	* Get the shadow PDE, find the shadow page table in the pool.
2095	*/
2096	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2097	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2098
2099	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2100	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2101
2102	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2103	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2104	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2105	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2106	X86PDEPAE PdeDst;
2107	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2108
2109	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2110	AssertRCSuccessReturn(rc, rc);
2111	Assert(pPDDst && pPdptDst);
2112	PdeDst = pPDDst->a[iPDDst];
2113	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2114	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2115	PEPTPD pPDDst;
2116	EPTPDE PdeDst;
2117
2118	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2119	if (rc != VINF_SUCCESS)
2120	{
2121	AssertRC(rc);
2122	return rc;
2123	}
2124	Assert(pPDDst);
2125	PdeDst = pPDDst->a[iPDDst];
2126	# endif
2127	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2128	if (!PdeDst.n.u1Present)
2129	{
2130	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2131	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2132	return VINF_SUCCESS; /* force the instruction to be executed again. */
2133	}
2134
2135	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2136	if (PdeDst.n.u1Size)
2137	{
2138	Assert(pVM->pgm.s.fNestedPaging);
2139	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2140	return VINF_SUCCESS;
2141	}
2142
2143	/* Mask away the page offset. */
2144	GCPtrPage &= ~((RTGCPTR)0xfff);
2145
2146	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2147	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2148
2149	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2150	if ( cPages > 1
2151	&& !(uErr & X86_TRAP_PF_P)
2152	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2153	{
2154	/*
2155	* This code path is currently only taken when the caller is PGMTrap0eHandler
2156	* for non-present pages!
2157	*
2158	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2159	* deal with locality.
2160	*/
2161	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2162	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2163	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2164	iPTDst = 0;
2165	else
2166	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2167	for (; iPTDst < iPTDstEnd; iPTDst++)
2168	{
2169	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2170	{
2171	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2172	GSTPTE PteSrc;
2173
2174	/* Fake the page table entry */
2175	PteSrc.u = GCPtrCurPage;
2176	PteSrc.n.u1Present = 1;
2177	PteSrc.n.u1Dirty = 1;
2178	PteSrc.n.u1Accessed = 1;
2179	PteSrc.n.u1Write = 1;
2180	PteSrc.n.u1User = 1;
2181
2182	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2183	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2184	GCPtrCurPage, PteSrc.n.u1Present,
2185	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2186	PteSrc.n.u1User & PdeSrc.n.u1User,
2187	(uint64_t)PteSrc.u,
2188	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2189	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2190
2191	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2192	break;
2193	}
2194	else
2195	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2196	}
2197	}
2198	else
2199	# endif /* PGM_SYNC_N_PAGES */
2200	{
2201	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2202	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2203	GSTPTE PteSrc;
2204
2205	/* Fake the page table entry */
2206	PteSrc.u = GCPtrCurPage;
2207	PteSrc.n.u1Present = 1;
2208	PteSrc.n.u1Dirty = 1;
2209	PteSrc.n.u1Accessed = 1;
2210	PteSrc.n.u1Write = 1;
2211	PteSrc.n.u1User = 1;
2212	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2213
2214	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2215	GCPtrPage, PteSrc.n.u1Present,
2216	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2217	PteSrc.n.u1User & PdeSrc.n.u1User,
2218	(uint64_t)PteSrc.u,
2219	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2220	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2221	}
2222	return VINF_SUCCESS;
2223
2224	#else
2225	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2226	return VERR_INTERNAL_ERROR;
2227	#endif
2228	}
2229
2230
2231	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2232
2233	/**
2234	* CheckPageFault helper for returning a page fault indicating a non-present
2235	* (NP) entry in the page translation structures.
2236	*
2237	* @returns VINF_EM_RAW_GUEST_TRAP.
2238	* @param pVCpu The virtual CPU to operate on.
2239	* @param uErr The error code of the shadow fault. Corrections to
2240	* TRPM's copy will be made if necessary.
2241	* @param GCPtrPage For logging.
2242	* @param uPageFaultLevel For logging.
2243	*/
2244	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2245	{
2246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2247	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2248	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2249	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2250	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2251
2252	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2253	return VINF_EM_RAW_GUEST_TRAP;
2254	}
2255
2256
2257	/**
2258	* CheckPageFault helper for returning a page fault indicating a reserved bit
2259	* (RSVD) error in the page translation structures.
2260	*
2261	* @returns VINF_EM_RAW_GUEST_TRAP.
2262	* @param pVCpu The virtual CPU to operate on.
2263	* @param uErr The error code of the shadow fault. Corrections to
2264	* TRPM's copy will be made if necessary.
2265	* @param GCPtrPage For logging.
2266	* @param uPageFaultLevel For logging.
2267	*/
2268	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2269	{
2270	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2271	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2272	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2273
2274	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2275	return VINF_EM_RAW_GUEST_TRAP;
2276	}
2277
2278
2279	/**
2280	* CheckPageFault helper for returning a page protection fault (P).
2281	*
2282	* @returns VINF_EM_RAW_GUEST_TRAP.
2283	* @param pVCpu The virtual CPU to operate on.
2284	* @param uErr The error code of the shadow fault. Corrections to
2285	* TRPM's copy will be made if necessary.
2286	* @param GCPtrPage For logging.
2287	* @param uPageFaultLevel For logging.
2288	*/
2289	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2290	{
2291	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2292	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2293	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2294	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2295
2296	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2297	return VINF_EM_RAW_GUEST_TRAP;
2298	}
2299
2300
2301	/**
2302	* Handle dirty bit tracking faults.
2303	*
2304	* @returns VBox status code.
2305	* @param pVCpu The VMCPU handle.
2306	* @param uErr Page fault error code.
2307	* @param pPdeSrc Guest page directory entry.
2308	* @param pPdeDst Shadow page directory entry.
2309	* @param GCPtrPage Guest context page address.
2310	*/
2311	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2312	{
2313	PVM pVM = pVCpu->CTX_SUFF(pVM);
2314	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2315
2316	Assert(PGMIsLockOwner(pVM));
2317
2318	/*
2319	* Handle big page.
2320	*/
2321	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2322	{
2323	if ( pPdeDst->n.u1Present
2324	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2325	{
2326	SHWPDE PdeDst = *pPdeDst;
2327
2328	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2329	Assert(pPdeSrc->b.u1Write);
2330
2331	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2332	* fault again and take this path to only invalidate the entry (see below).
2333	*/
2334	PdeDst.n.u1Write = 1;
2335	PdeDst.n.u1Accessed = 1;
2336	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2337	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2338	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2339	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2340	}
2341
2342	# ifdef IN_RING0
2343	/* Check for stale TLB entry; only applies to the SMP guest case. */
2344	if ( pVM->cCpus > 1
2345	&& pPdeDst->n.u1Write
2346	&& pPdeDst->n.u1Accessed)
2347	{
2348	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2349	if (pShwPage)
2350	{
2351	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2352	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2353	if (SHW_PTE_IS_P_RW(*pPteDst))
2354	{
2355	/* Stale TLB entry. */
2356	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2357	PGM_INVL_PG(pVCpu, GCPtrPage);
2358	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2359	}
2360	}
2361	}
2362	# endif /* IN_RING0 */
2363	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2364	}
2365
2366	/*
2367	* Map the guest page table.
2368	*/
2369	PGSTPT pPTSrc;
2370	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2371	if (RT_FAILURE(rc))
2372	{
2373	AssertRC(rc);
2374	return rc;
2375	}
2376
2377	if (pPdeDst->n.u1Present)
2378	{
2379	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2380	const GSTPTE PteSrc = *pPteSrc;
2381
2382	#ifndef IN_RING0
2383	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2384	* Our individual shadow handlers will provide more information and force a fatal exit.
2385	*/
2386	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2387	{
2388	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2389	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2390	}
2391	#endif
2392	/*
2393	* Map shadow page table.
2394	*/
2395	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2396	if (pShwPage)
2397	{
2398	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2399	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2400	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2401	{
2402	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2403	{
2404	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2405	SHWPTE PteDst = *pPteDst;
2406
2407	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2408	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2409
2410	Assert(pPteSrc->n.u1Write);
2411
2412	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2413	* entry will not harm; write access will simply fault again and
2414	* take this path to only invalidate the entry.
2415	*/
2416	if (RT_LIKELY(pPage))
2417	{
2418	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2419	{
2420	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2421	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2422	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2423	SHW_PTE_SET_RO(PteDst);
2424	}
2425	else
2426	{
2427	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2428	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2429	{
2430	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2431	AssertRC(rc);
2432	}
2433	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2434	SHW_PTE_SET_RW(PteDst);
2435	else
2436	{
2437	/* Still applies to shared pages. */
2438	Assert(!PGM_PAGE_IS_ZERO(pPage));
2439	SHW_PTE_SET_RO(PteDst);
2440	}
2441	}
2442	}
2443	else
2444	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2445
2446	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2447	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2448	PGM_INVL_PG(pVCpu, GCPtrPage);
2449	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2450	}
2451
2452	# ifdef IN_RING0
2453	/* Check for stale TLB entry; only applies to the SMP guest case. */
2454	if ( pVM->cCpus > 1
2455	&& SHW_PTE_IS_RW(*pPteDst)
2456	&& SHW_PTE_IS_A(*pPteDst))
2457	{
2458	/* Stale TLB entry. */
2459	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2460	PGM_INVL_PG(pVCpu, GCPtrPage);
2461	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2462	}
2463	# endif
2464	}
2465	}
2466	else
2467	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2468	}
2469
2470	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2471	}
2472
2473	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2474
2475
2476	/**
2477	* Sync a shadow page table.
2478	*
2479	* The shadow page table is not present in the shadow PDE.
2480	*
2481	* Handles mapping conflicts.
2482	*
2483	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2484	* conflict), and Trap0eHandler.
2485	*
2486	* A precodition for this method is that the shadow PDE is not present. The
2487	* caller must take the PGM lock before checking this and continue to hold it
2488	* when calling this method.
2489	*
2490	* @returns VBox status code.
2491	* @param pVCpu The VMCPU handle.
2492	* @param iPD Page directory index.
2493	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2494	* Assume this is a temporary mapping.
2495	* @param GCPtrPage GC Pointer of the page that caused the fault
2496	*/
2497	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2498	{
2499	PVM pVM = pVCpu->CTX_SUFF(pVM);
2500	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2501
2502	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2503	#if 0 /* rarely useful; leave for debugging. */
2504	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2505	#endif
2506	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2507
2508	Assert(PGMIsLocked(pVM));
2509
2510	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2511	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2512	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2513	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2514	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2515
2516	int rc = VINF_SUCCESS;
2517
2518	/*
2519	* Some input validation first.
2520	*/
2521	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2522
2523	/*
2524	* Get the relevant shadow PDE entry.
2525	*/
2526	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2527	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2528	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2529
2530	/* Fetch the pgm pool shadow descriptor. */
2531	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2532	Assert(pShwPde);
2533
2534	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2535	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2536	PPGMPOOLPAGE pShwPde = NULL;
2537	PX86PDPAE pPDDst;
2538	PSHWPDE pPdeDst;
2539
2540	/* Fetch the pgm pool shadow descriptor. */
2541	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2542	AssertRCSuccessReturn(rc, rc);
2543	Assert(pShwPde);
2544
2545	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2546	pPdeDst = &pPDDst->a[iPDDst];
2547
2548	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2549	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2550	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2551	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2552	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2553	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2554	AssertRCSuccessReturn(rc, rc);
2555	Assert(pPDDst);
2556	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2557	# endif
2558	SHWPDE PdeDst = *pPdeDst;
2559
2560	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2561	/* Fetch the pgm pool shadow descriptor. */
2562	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2563	Assert(pShwPde);
2564	# endif
2565
2566	# ifndef PGM_WITHOUT_MAPPINGS
2567	/*
2568	* Check for conflicts.
2569	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2570	* R3: Simply resolve the conflict.
2571	*/
2572	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2573	{
2574	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2575	# ifndef IN_RING3
2576	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2577	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2578	return VERR_ADDRESS_CONFLICT;
2579
2580	# else /* IN_RING3 */
2581	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2582	Assert(pMapping);
2583	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2584	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2585	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2586	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2587	# else
2588	AssertFailed(); /* can't happen for amd64 */
2589	# endif
2590	if (RT_FAILURE(rc))
2591	{
2592	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2593	return rc;
2594	}
2595	PdeDst = *pPdeDst;
2596	# endif /* IN_RING3 */
2597	}
2598	# endif /* !PGM_WITHOUT_MAPPINGS */
2599	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2600
2601	/*
2602	* Sync the page directory entry.
2603	*/
2604	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2605	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2606	if ( PdeSrc.n.u1Present
2607	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2608	{
2609	/*
2610	* Allocate & map the page table.
2611	*/
2612	PSHWPT pPTDst;
2613	PPGMPOOLPAGE pShwPage;
2614	RTGCPHYS GCPhys;
2615	if (fPageTable)
2616	{
2617	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2618	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2619	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2620	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2621	# endif
2622	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2623	}
2624	else
2625	{
2626	PGMPOOLACCESS enmAccess;
2627	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2628	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2629	# else
2630	const bool fNoExecute = false;
2631	# endif
2632
2633	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2634	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2635	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2636	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2637	# endif
2638	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2639	if (PdeSrc.n.u1User)
2640	{
2641	if (PdeSrc.n.u1Write)
2642	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2643	else
2644	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2645	}
2646	else
2647	{
2648	if (PdeSrc.n.u1Write)
2649	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2650	else
2651	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2652	}
2653	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2654	&pShwPage);
2655	}
2656	if (rc == VINF_SUCCESS)
2657	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2658	else if (rc == VINF_PGM_CACHED_PAGE)
2659	{
2660	/*
2661	* The PT was cached, just hook it up.
2662	*/
2663	if (fPageTable)
2664	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2665	else
2666	{
2667	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2668	/* (see explanation and assumptions further down.) */
2669	if ( !PdeSrc.b.u1Dirty
2670	&& PdeSrc.b.u1Write)
2671	{
2672	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2673	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2674	PdeDst.b.u1Write = 0;
2675	}
2676	}
2677	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2678	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2679	return VINF_SUCCESS;
2680	}
2681	else if (rc == VERR_PGM_POOL_FLUSHED)
2682	{
2683	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2684	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2685	return VINF_PGM_SYNC_CR3;
2686	}
2687	else
2688	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2689	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2690	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2691	* irrelevant at this point. */
2692	PdeDst.u &= X86_PDE_AVL_MASK;
2693	PdeDst.u \|= pShwPage->Core.Key;
2694
2695	/*
2696	* Page directory has been accessed (this is a fault situation, remember).
2697	*/
2698	/** @todo
2699	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2700	* fault situation. What's more, the Trap0eHandler has already set the
2701	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2702	* might need setting the accessed flag.
2703	*
2704	* The best idea is to leave this change to the caller and add an
2705	* assertion that it's set already. */
2706	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2707	if (fPageTable)
2708	{
2709	/*
2710	* Page table - 4KB.
2711	*
2712	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2713	*/
2714	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2715	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2716	PGSTPT pPTSrc;
2717	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2718	if (RT_SUCCESS(rc))
2719	{
2720	/*
2721	* Start by syncing the page directory entry so CSAM's TLB trick works.
2722	*/
2723	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2724	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2725	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2726	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2727
2728	/*
2729	* Directory/page user or supervisor privilege: (same goes for read/write)
2730	*
2731	* Directory Page Combined
2732	* U/S U/S U/S
2733	* 0 0 0
2734	* 0 1 0
2735	* 1 0 0
2736	* 1 1 1
2737	*
2738	* Simple AND operation. Table listed for completeness.
2739	*
2740	*/
2741	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2742	# ifdef PGM_SYNC_N_PAGES
2743	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2744	unsigned iPTDst = iPTBase;
2745	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2746	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2747	iPTDst = 0;
2748	else
2749	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2750	# else /* !PGM_SYNC_N_PAGES */
2751	unsigned iPTDst = 0;
2752	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2753	# endif /* !PGM_SYNC_N_PAGES */
2754	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2755	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2756	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2757	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2758	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2759	# else
2760	const unsigned offPTSrc = 0;
2761	# endif
2762	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2763	{
2764	const unsigned iPTSrc = iPTDst + offPTSrc;
2765	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2766
2767	if (PteSrc.n.u1Present)
2768	{
2769	# ifndef IN_RING0
2770	/*
2771	* Assuming kernel code will be marked as supervisor - and not as user level
2772	* and executed using a conforming code selector - And marked as readonly.
2773	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2774	*/
2775	PPGMPAGE pPage;
2776	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2777	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2778	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2779	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2780	)
2781	# endif
2782	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2783	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2784	GCPtrCur,
2785	PteSrc.n.u1Present,
2786	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2787	PteSrc.n.u1User & PdeSrc.n.u1User,
2788	(uint64_t)PteSrc.u,
2789	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2790	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2791	}
2792	/* else: the page table was cleared by the pool */
2793	} /* for PTEs */
2794	}
2795	}
2796	else
2797	{
2798	/*
2799	* Big page - 2/4MB.
2800	*
2801	* We'll walk the ram range list in parallel and optimize lookups.
2802	* We will only sync on shadow page table at a time.
2803	*/
2804	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2805
2806	/**
2807	* @todo It might be more efficient to sync only a part of the 4MB
2808	* page (similar to what we do for 4KB PDs).
2809	*/
2810
2811	/*
2812	* Start by syncing the page directory entry.
2813	*/
2814	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2815	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2816
2817	/*
2818	* If the page is not flagged as dirty and is writable, then make it read-only
2819	* at PD level, so we can set the dirty bit when the page is modified.
2820	*
2821	* ASSUMES that page access handlers are implemented on page table entry level.
2822	* Thus we will first catch the dirty access and set PDE.D and restart. If
2823	* there is an access handler, we'll trap again and let it work on the problem.
2824	*/
2825	/** @todo move the above stuff to a section in the PGM documentation. */
2826	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2827	if ( !PdeSrc.b.u1Dirty
2828	&& PdeSrc.b.u1Write)
2829	{
2830	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2831	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2832	PdeDst.b.u1Write = 0;
2833	}
2834	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2835	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2836
2837	/*
2838	* Fill the shadow page table.
2839	*/
2840	/* Get address and flags from the source PDE. */
2841	SHWPTE PteDstBase;
2842	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2843
2844	/* Loop thru the entries in the shadow PT. */
2845	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2846	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2847	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2848	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2849	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2850	unsigned iPTDst = 0;
2851	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2852	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2853	{
2854	/* Advance ram range list. */
2855	while (pRam && GCPhys > pRam->GCPhysLast)
2856	pRam = pRam->CTX_SUFF(pNext);
2857	if (pRam && GCPhys >= pRam->GCPhys)
2858	{
2859	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2860	do
2861	{
2862	/* Make shadow PTE. */
2863	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2864	SHWPTE PteDst;
2865
2866	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2867	/* Try to make the page writable if necessary. */
2868	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2869	&& ( PGM_PAGE_IS_ZERO(pPage)
2870	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2871	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2872	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2873	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2874	# endif
2875	# ifdef VBOX_WITH_PAGE_SHARING
2876	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2877	# endif
2878	&& !PGM_PAGE_IS_BALLOONED(pPage))
2879	)
2880	)
2881	{
2882	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2883	AssertRCReturn(rc, rc);
2884	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2885	break;
2886	}
2887	# endif
2888
2889	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2890	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2891	else if (PGM_PAGE_IS_BALLOONED(pPage))
2892	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2893	# ifndef IN_RING0
2894	/*
2895	* Assuming kernel code will be marked as supervisor and not as user level and executed
2896	* using a conforming code selector. Don't check for readonly, as that implies the whole
2897	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2898	*/
2899	else if ( !PdeSrc.n.u1User
2900	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2901	SHW_PTE_SET(PteDst, 0);
2902	# endif
2903	else
2904	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2905
2906	/* Only map writable pages writable. */
2907	if ( SHW_PTE_IS_P_RW(PteDst)
2908	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2909	{
2910	/* Still applies to shared pages. */
2911	Assert(!PGM_PAGE_IS_ZERO(pPage));
2912	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2913	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2914	}
2915
2916	if (SHW_PTE_IS_P(PteDst))
2917	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2918
2919	/* commit it (not atomic, new table) */
2920	pPTDst->a[iPTDst] = PteDst;
2921	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2922	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2923	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2924
2925	/* advance */
2926	GCPhys += PAGE_SIZE;
2927	iHCPage++;
2928	iPTDst++;
2929	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2930	&& GCPhys <= pRam->GCPhysLast);
2931	}
2932	else if (pRam)
2933	{
2934	Log(("Invalid pages at %RGp\n", GCPhys));
2935	do
2936	{
2937	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2938	GCPhys += PAGE_SIZE;
2939	iPTDst++;
2940	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2941	&& GCPhys < pRam->GCPhys);
2942	}
2943	else
2944	{
2945	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2946	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2947	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2948	}
2949	} /* while more PTEs */
2950	} /* 4KB / 4MB */
2951	}
2952	else
2953	AssertRelease(!PdeDst.n.u1Present);
2954
2955	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2956	if (RT_FAILURE(rc))
2957	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2958	return rc;
2959
2960	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2961	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2962	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2963	&& !defined(IN_RC)
2964
2965	/*
2966	* Validate input a little bit.
2967	*/
2968	int rc = VINF_SUCCESS;
2969	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2970	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2971	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2972
2973	/* Fetch the pgm pool shadow descriptor. */
2974	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2975	Assert(pShwPde);
2976
2977	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2978	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2979	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2980	PX86PDPAE pPDDst;
2981	PSHWPDE pPdeDst;
2982
2983	/* Fetch the pgm pool shadow descriptor. */
2984	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2985	AssertRCSuccessReturn(rc, rc);
2986	Assert(pShwPde);
2987
2988	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2989	pPdeDst = &pPDDst->a[iPDDst];
2990
2991	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2992	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2993	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2994	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2995	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
2996	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2997	AssertRCSuccessReturn(rc, rc);
2998	Assert(pPDDst);
2999	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3000
3001	/* Fetch the pgm pool shadow descriptor. */
3002	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3003	Assert(pShwPde);
3004
3005	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3006	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3007	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3008	PEPTPD pPDDst;
3009	PEPTPDPT pPdptDst;
3010
3011	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3012	if (rc != VINF_SUCCESS)
3013	{
3014	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3015	AssertRC(rc);
3016	return rc;
3017	}
3018	Assert(pPDDst);
3019	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3020
3021	/* Fetch the pgm pool shadow descriptor. */
3022	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3023	Assert(pShwPde);
3024	# endif
3025	SHWPDE PdeDst = *pPdeDst;
3026
3027	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3028	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3029
3030	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3031	if (BTH_IS_NP_ACTIVE(pVM))
3032	{
3033	PPGMPAGE pPage;
3034
3035	/* Check if we allocated a big page before for this 2 MB range. */
3036	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3037	if (RT_SUCCESS(rc))
3038	{
3039	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3040
3041	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3042	{
3043	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3044	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3045	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3046	}
3047	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3048	{
3049	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3050	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3051	if (RT_SUCCESS(rc))
3052	{
3053	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3054	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3055	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3056	}
3057	}
3058	else if (PGMIsUsingLargePages(pVM))
3059	{
3060	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3061	if (RT_SUCCESS(rc))
3062	{
3063	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3064	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3065	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3066	}
3067	else
3068	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3069	}
3070
3071	if (HCPhys != NIL_RTHCPHYS)
3072	{
3073	PdeDst.u &= X86_PDE_AVL_MASK;
3074	PdeDst.u \|= HCPhys;
3075	PdeDst.n.u1Present = 1;
3076	PdeDst.n.u1Write = 1;
3077	PdeDst.b.u1Size = 1;
3078	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3079	PdeDst.n.u1Execute = 1;
3080	PdeDst.b.u1IgnorePAT = 1;
3081	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3082	# else
3083	PdeDst.n.u1User = 1;
3084	# endif
3085	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3086
3087	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3088	/* Add a reference to the first page only. */
3089	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3090
3091	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3092	return VINF_SUCCESS;
3093	}
3094	}
3095	}
3096	# endif /* HC_ARCH_BITS == 64 */
3097
3098	GSTPDE PdeSrc;
3099	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3100	PdeSrc.n.u1Present = 1;
3101	PdeSrc.n.u1Write = 1;
3102	PdeSrc.n.u1Accessed = 1;
3103	PdeSrc.n.u1User = 1;
3104
3105	/*
3106	* Allocate & map the page table.
3107	*/
3108	PSHWPT pPTDst;
3109	PPGMPOOLPAGE pShwPage;
3110	RTGCPHYS GCPhys;
3111
3112	/* Virtual address = physical address */
3113	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3114	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3115
3116	if ( rc == VINF_SUCCESS
3117	\|\| rc == VINF_PGM_CACHED_PAGE)
3118	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3119	else
3120	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3121
3122	PdeDst.u &= X86_PDE_AVL_MASK;
3123	PdeDst.u \|= pShwPage->Core.Key;
3124	PdeDst.n.u1Present = 1;
3125	PdeDst.n.u1Write = 1;
3126	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3127	PdeDst.n.u1Execute = 1;
3128	# else
3129	PdeDst.n.u1User = 1;
3130	PdeDst.n.u1Accessed = 1;
3131	# endif
3132	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3133
3134	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3135	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3136	return rc;
3137
3138	#else
3139	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3140	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3141	return VERR_INTERNAL_ERROR;
3142	#endif
3143	}
3144
3145
3146
3147	/**
3148	* Prefetch a page/set of pages.
3149	*
3150	* Typically used to sync commonly used pages before entering raw mode
3151	* after a CR3 reload.
3152	*
3153	* @returns VBox status code.
3154	* @param pVCpu The VMCPU handle.
3155	* @param GCPtrPage Page to invalidate.
3156	*/
3157	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3158	{
3159	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3160	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3161	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3162	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3163	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3164	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3165	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3166
3167	/*
3168	* Check that all Guest levels thru the PDE are present, getting the
3169	* PD and PDE in the processes.
3170	*/
3171	int rc = VINF_SUCCESS;
3172	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3173	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3174	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3175	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3176	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3177	unsigned iPDSrc;
3178	X86PDPE PdpeSrc;
3179	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3180	if (!pPDSrc)
3181	return VINF_SUCCESS; /* not present */
3182	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3183	unsigned iPDSrc;
3184	PX86PML4E pPml4eSrc;
3185	X86PDPE PdpeSrc;
3186	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3187	if (!pPDSrc)
3188	return VINF_SUCCESS; /* not present */
3189	# endif
3190	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3191	# else
3192	PGSTPD pPDSrc = NULL;
3193	const unsigned iPDSrc = 0;
3194	GSTPDE PdeSrc;
3195
3196	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3197	PdeSrc.n.u1Present = 1;
3198	PdeSrc.n.u1Write = 1;
3199	PdeSrc.n.u1Accessed = 1;
3200	PdeSrc.n.u1User = 1;
3201	# endif
3202
3203	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3204	{
3205	PVM pVM = pVCpu->CTX_SUFF(pVM);
3206	pgmLock(pVM);
3207
3208	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3209	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3210	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3211	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3212	PX86PDPAE pPDDst;
3213	X86PDEPAE PdeDst;
3214	# if PGM_GST_TYPE != PGM_TYPE_PAE
3215	X86PDPE PdpeSrc;
3216
3217	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3218	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3219	# endif
3220	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3221	if (rc != VINF_SUCCESS)
3222	{
3223	pgmUnlock(pVM);
3224	AssertRC(rc);
3225	return rc;
3226	}
3227	Assert(pPDDst);
3228	PdeDst = pPDDst->a[iPDDst];
3229
3230	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3231	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3232	PX86PDPAE pPDDst;
3233	X86PDEPAE PdeDst;
3234
3235	# if PGM_GST_TYPE == PGM_TYPE_PROT
3236	/* AMD-V nested paging */
3237	X86PML4E Pml4eSrc;
3238	X86PDPE PdpeSrc;
3239	PX86PML4E pPml4eSrc = &Pml4eSrc;
3240
3241	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3242	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3243	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3244	# endif
3245
3246	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3247	if (rc != VINF_SUCCESS)
3248	{
3249	pgmUnlock(pVM);
3250	AssertRC(rc);
3251	return rc;
3252	}
3253	Assert(pPDDst);
3254	PdeDst = pPDDst->a[iPDDst];
3255	# endif
3256	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3257	{
3258	if (!PdeDst.n.u1Present)
3259	{
3260	/** @todo r=bird: This guy will set the A bit on the PDE,
3261	* probably harmless. */
3262	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3263	}
3264	else
3265	{
3266	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3267	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3268	* makes no sense to prefetch more than one page.
3269	*/
3270	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3271	if (RT_SUCCESS(rc))
3272	rc = VINF_SUCCESS;
3273	}
3274	}
3275	pgmUnlock(pVM);
3276	}
3277	return rc;
3278
3279	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3280	return VINF_SUCCESS; /* ignore */
3281	#else
3282	AssertCompile(0);
3283	#endif
3284	}
3285
3286
3287
3288
3289	/**
3290	* Syncs a page during a PGMVerifyAccess() call.
3291	*
3292	* @returns VBox status code (informational included).
3293	* @param pVCpu The VMCPU handle.
3294	* @param GCPtrPage The address of the page to sync.
3295	* @param fPage The effective guest page flags.
3296	* @param uErr The trap error code.
3297	* @remarks This will normally never be called on invalid guest page
3298	* translation entries.
3299	*/
3300	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3301	{
3302	PVM pVM = pVCpu->CTX_SUFF(pVM);
3303
3304	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3305
3306	Assert(!pVM->pgm.s.fNestedPaging);
3307	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3308	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3309	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3310	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3311	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3312	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3313	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3314
3315	# ifndef IN_RING0
3316	if (!(fPage & X86_PTE_US))
3317	{
3318	/*
3319	* Mark this page as safe.
3320	*/
3321	/** @todo not correct for pages that contain both code and data!! */
3322	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3323	CSAMMarkPage(pVM, GCPtrPage, true);
3324	}
3325	# endif
3326
3327	/*
3328	* Get guest PD and index.
3329	*/
3330	/** @todo Performance: We've done all this a jiffy ago in the
3331	* PGMGstGetPage call. */
3332	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3333	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3334	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3335	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3336
3337	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3338	unsigned iPDSrc = 0;
3339	X86PDPE PdpeSrc;
3340	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3341	if (RT_UNLIKELY(!pPDSrc))
3342	{
3343	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3344	return VINF_EM_RAW_GUEST_TRAP;
3345	}
3346
3347	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3348	unsigned iPDSrc = 0; /* shut up gcc */
3349	PX86PML4E pPml4eSrc = NULL; /* ditto */
3350	X86PDPE PdpeSrc;
3351	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3352	if (RT_UNLIKELY(!pPDSrc))
3353	{
3354	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3355	return VINF_EM_RAW_GUEST_TRAP;
3356	}
3357	# endif
3358
3359	# else /* !PGM_WITH_PAGING */
3360	PGSTPD pPDSrc = NULL;
3361	const unsigned iPDSrc = 0;
3362	# endif /* !PGM_WITH_PAGING */
3363	int rc = VINF_SUCCESS;
3364
3365	pgmLock(pVM);
3366
3367	/*
3368	* First check if the shadow pd is present.
3369	*/
3370	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3371	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3372
3373	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3374	PX86PDEPAE pPdeDst;
3375	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3376	PX86PDPAE pPDDst;
3377	# if PGM_GST_TYPE != PGM_TYPE_PAE
3378	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3379	X86PDPE PdpeSrc;
3380	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3381	# endif
3382	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3383	if (rc != VINF_SUCCESS)
3384	{
3385	pgmUnlock(pVM);
3386	AssertRC(rc);
3387	return rc;
3388	}
3389	Assert(pPDDst);
3390	pPdeDst = &pPDDst->a[iPDDst];
3391
3392	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3393	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3394	PX86PDPAE pPDDst;
3395	PX86PDEPAE pPdeDst;
3396
3397	# if PGM_GST_TYPE == PGM_TYPE_PROT
3398	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3399	X86PML4E Pml4eSrc;
3400	X86PDPE PdpeSrc;
3401	PX86PML4E pPml4eSrc = &Pml4eSrc;
3402	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3403	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3404	# endif
3405
3406	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3407	if (rc != VINF_SUCCESS)
3408	{
3409	pgmUnlock(pVM);
3410	AssertRC(rc);
3411	return rc;
3412	}
3413	Assert(pPDDst);
3414	pPdeDst = &pPDDst->a[iPDDst];
3415	# endif
3416
3417	if (!pPdeDst->n.u1Present)
3418	{
3419	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3420	if (rc != VINF_SUCCESS)
3421	{
3422	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3423	pgmUnlock(pVM);
3424	AssertRC(rc);
3425	return rc;
3426	}
3427	}
3428
3429	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3430	/* Check for dirty bit fault */
3431	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3432	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3433	Log(("PGMVerifyAccess: success (dirty)\n"));
3434	else
3435	# endif
3436	{
3437	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3438	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3439	# else
3440	GSTPDE PdeSrc;
3441	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3442	PdeSrc.n.u1Present = 1;
3443	PdeSrc.n.u1Write = 1;
3444	PdeSrc.n.u1Accessed = 1;
3445	PdeSrc.n.u1User = 1;
3446	# endif
3447
3448	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3449	if (uErr & X86_TRAP_PF_US)
3450	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3451	else /* supervisor */
3452	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3453
3454	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3455	if (RT_SUCCESS(rc))
3456	{
3457	/* Page was successfully synced */
3458	Log2(("PGMVerifyAccess: success (sync)\n"));
3459	rc = VINF_SUCCESS;
3460	}
3461	else
3462	{
3463	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3464	rc = VINF_EM_RAW_GUEST_TRAP;
3465	}
3466	}
3467	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3468	pgmUnlock(pVM);
3469	return rc;
3470
3471	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3472
3473	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3474	return VERR_INTERNAL_ERROR;
3475	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3476	}
3477
3478
3479	/**
3480	* Syncs the paging hierarchy starting at CR3.
3481	*
3482	* @returns VBox status code, no specials.
3483	* @param pVCpu The VMCPU handle.
3484	* @param cr0 Guest context CR0 register
3485	* @param cr3 Guest context CR3 register
3486	* @param cr4 Guest context CR4 register
3487	* @param fGlobal Including global page directories or not
3488	*/
3489	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3490	{
3491	PVM pVM = pVCpu->CTX_SUFF(pVM);
3492
3493	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3494
3495	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3496
3497	pgmLock(pVM);
3498
3499	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3500	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3501	if (pPool->cDirtyPages)
3502	pgmPoolResetDirtyPages(pVM);
3503	# endif
3504
3505	/*
3506	* Update page access handlers.
3507	* The virtual are always flushed, while the physical are only on demand.
3508	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3509	* have to look into that later because it will have a bad influence on the performance.
3510	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3511	* bird: Yes, but that won't work for aliases.
3512	*/
3513	/** @todo this MUST go away. See #1557. */
3514	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3515	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3516	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3517	pgmUnlock(pVM);
3518	#endif /* !NESTED && !EPT */
3519
3520	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3521	/*
3522	* Nested / EPT - almost no work.
3523	*/
3524	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3525	return VINF_SUCCESS;
3526
3527	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3528	/*
3529	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3530	* out the shadow parts when the guest modifies its tables.
3531	*/
3532	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3533	return VINF_SUCCESS;
3534
3535	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3536
3537	# ifndef PGM_WITHOUT_MAPPINGS
3538	/*
3539	* Check for and resolve conflicts with our guest mappings if they
3540	* are enabled and not fixed.
3541	*/
3542	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3543	{
3544	int rc = pgmMapResolveConflicts(pVM);
3545	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3546	if (rc == VINF_PGM_SYNC_CR3)
3547	{
3548	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3549	return VINF_PGM_SYNC_CR3;
3550	}
3551	}
3552	# else
3553	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3554	# endif
3555	return VINF_SUCCESS;
3556	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3557	}
3558
3559
3560
3561
3562	#ifdef VBOX_STRICT
3563	# ifdef IN_RC
3564	# undef AssertMsgFailed
3565	# define AssertMsgFailed Log
3566	# endif
3567
3568	/**
3569	* Checks that the shadow page table is in sync with the guest one.
3570	*
3571	* @returns The number of errors.
3572	* @param pVM The virtual machine.
3573	* @param pVCpu The VMCPU handle.
3574	* @param cr3 Guest context CR3 register
3575	* @param cr4 Guest context CR4 register
3576	* @param GCPtr Where to start. Defaults to 0.
3577	* @param cb How much to check. Defaults to everything.
3578	*/
3579	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3580	{
3581	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3582	return 0;
3583	#else
3584	unsigned cErrors = 0;
3585	PVM pVM = pVCpu->CTX_SUFF(pVM);
3586	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3587
3588	#if PGM_GST_TYPE == PGM_TYPE_PAE
3589	/** @todo currently broken; crashes below somewhere */
3590	AssertFailed();
3591	#endif
3592
3593	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3594	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3595	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3596
3597	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3598	PPGMCPU pPGM = &pVCpu->pgm.s;
3599	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3600	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3601	# ifndef IN_RING0
3602	RTHCPHYS HCPhys; /* general usage. */
3603	# endif
3604	int rc;
3605
3606	/*
3607	* Check that the Guest CR3 and all its mappings are correct.
3608	*/
3609	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3610	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3611	false);
3612	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3613	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3614	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3615	# else
3616	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3617	# endif
3618	AssertRCReturn(rc, 1);
3619	HCPhys = NIL_RTHCPHYS;
3620	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3621	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3622	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3623	pgmGstGet32bitPDPtr(pVCpu);
3624	RTGCPHYS GCPhys;
3625	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3626	AssertRCReturn(rc, 1);
3627	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3628	# endif
3629	# endif /* !IN_RING0 */
3630
3631	/*
3632	* Get and check the Shadow CR3.
3633	*/
3634	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3635	unsigned cPDEs = X86_PG_ENTRIES;
3636	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3637	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3638	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3639	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3640	# else
3641	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3642	# endif
3643	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3644	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3645	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3646	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3647	# endif
3648	if (cb != ~(RTGCPTR)0)
3649	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3650
3651	/** @todo call the other two PGMAssert() functions. /
3652
3653	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3654	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3655
3656	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3657	{
3658	PPGMPOOLPAGE pShwPdpt = NULL;
3659	PX86PML4E pPml4eSrc;
3660	PX86PML4E pPml4eDst;
3661	RTGCPHYS GCPhysPdptSrc;
3662
3663	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3664	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3665
3666	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3667	if (!pPml4eDst->n.u1Present)
3668	{
3669	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3670	continue;
3671	}
3672
3673	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3674	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3675
3676	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3677	{
3678	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3679	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3680	cErrors++;
3681	continue;
3682	}
3683
3684	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3685	{
3686	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3687	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3688	cErrors++;
3689	continue;
3690	}
3691
3692	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3693	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3694	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3695	{
3696	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3697	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3698	cErrors++;
3699	continue;
3700	}
3701	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3702	{
3703	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3704
3705	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3706	/*
3707	* Check the PDPTEs too.
3708	*/
3709	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3710
3711	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3712	{
3713	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3714	PPGMPOOLPAGE pShwPde = NULL;
3715	PX86PDPE pPdpeDst;
3716	RTGCPHYS GCPhysPdeSrc;
3717	# if PGM_GST_TYPE == PGM_TYPE_PAE
3718	X86PDPE PdpeSrc;
3719	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3720	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3721	# else
3722	PX86PML4E pPml4eSrcIgn;
3723	X86PDPE PdpeSrc;
3724	PX86PDPT pPdptDst;
3725	PX86PDPAE pPDDst;
3726	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3727
3728	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3729	if (rc != VINF_SUCCESS)
3730	{
3731	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3732	GCPtr += 512 * _2M;
3733	continue; /* next PDPTE */
3734	}
3735	Assert(pPDDst);
3736	# endif
3737	Assert(iPDSrc == 0);
3738
3739	pPdpeDst = &pPdptDst->a[iPdpt];
3740
3741	if (!pPdpeDst->n.u1Present)
3742	{
3743	GCPtr += 512 * _2M;
3744	continue; /* next PDPTE */
3745	}
3746
3747	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3748	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3749
3750	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3751	{
3752	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3753	GCPtr += 512 * _2M;
3754	cErrors++;
3755	continue;
3756	}
3757
3758	if (GCPhysPdeSrc != pShwPde->GCPhys)
3759	{
3760	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3761	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3762	# else
3763	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3764	# endif
3765	GCPtr += 512 * _2M;
3766	cErrors++;
3767	continue;
3768	}
3769
3770	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3771	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3772	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3773	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3774	{
3775	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3776	GCPtr += 512 * _2M;
3777	cErrors++;
3778	continue;
3779	}
3780	# endif
3781
3782	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3783	{
3784	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3785	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3786	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3787	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3788	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3789	# endif
3790	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3791	/*
3792	* Iterate the shadow page directory.
3793	*/
3794	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3795	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3796
3797	for (;
3798	iPDDst < cPDEs;
3799	iPDDst++, GCPtr += cIncrement)
3800	{
3801	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3802	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3803	# else
3804	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3805	# endif
3806	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3807	{
3808	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3809	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3810	{
3811	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3812	cErrors++;
3813	continue;
3814	}
3815	}
3816	else if ( (PdeDst.u & X86_PDE_P)
3817	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3818	)
3819	{
3820	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3821	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3822	if (!pPoolPage)
3823	{
3824	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3825	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3826	cErrors++;
3827	continue;
3828	}
3829	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3830
3831	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3832	{
3833	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3834	GCPtr, (uint64_t)PdeDst.u));
3835	cErrors++;
3836	}
3837
3838	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3839	{
3840	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3841	GCPtr, (uint64_t)PdeDst.u));
3842	cErrors++;
3843	}
3844
3845	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3846	if (!PdeSrc.n.u1Present)
3847	{
3848	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3849	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3850	cErrors++;
3851	continue;
3852	}
3853
3854	if ( !PdeSrc.b.u1Size
3855	\|\| !fBigPagesSupported)
3856	{
3857	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3858	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3859	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3860	# endif
3861	}
3862	else
3863	{
3864	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3865	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3866	{
3867	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3868	GCPtr, (uint64_t)PdeSrc.u));
3869	cErrors++;
3870	continue;
3871	}
3872	# endif
3873	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3874	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3875	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3876	# endif
3877	}
3878
3879	if ( pPoolPage->enmKind
3880	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3881	{
3882	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3883	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3884	cErrors++;
3885	}
3886
3887	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3888	if (!pPhysPage)
3889	{
3890	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3891	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3892	cErrors++;
3893	continue;
3894	}
3895
3896	if (GCPhysGst != pPoolPage->GCPhys)
3897	{
3898	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3899	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3900	cErrors++;
3901	continue;
3902	}
3903
3904	if ( !PdeSrc.b.u1Size
3905	\|\| !fBigPagesSupported)
3906	{
3907	/*
3908	* Page Table.
3909	*/
3910	const GSTPT *pPTSrc;
3911	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3912	if (RT_FAILURE(rc))
3913	{
3914	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3915	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3916	cErrors++;
3917	continue;
3918	}
3919	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3920	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3921	{
3922	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3923	// (This problem will go away when/if we shadow multiple CR3s.)
3924	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3925	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3926	cErrors++;
3927	continue;
3928	}
3929	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3930	{
3931	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3932	GCPtr, (uint64_t)PdeDst.u));
3933	cErrors++;
3934	continue;
3935	}
3936
3937	/* iterate the page table. */
3938	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3939	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3940	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3941	# else
3942	const unsigned offPTSrc = 0;
3943	# endif
3944	for (unsigned iPT = 0, off = 0;
3945	iPT < RT_ELEMENTS(pPTDst->a);
3946	iPT++, off += PAGE_SIZE)
3947	{
3948	const SHWPTE PteDst = pPTDst->a[iPT];
3949
3950	/* skip not-present and dirty tracked entries. */
3951	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3952	continue;
3953	Assert(SHW_PTE_IS_P(PteDst));
3954
3955	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3956	if (!PteSrc.n.u1Present)
3957	{
3958	# ifdef IN_RING3
3959	PGMAssertHandlerAndFlagsInSync(pVM);
3960	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3961	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3962	0, 0, UINT64_MAX, 99, NULL);
3963	# endif
3964	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3965	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3966	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3967	cErrors++;
3968	continue;
3969	}
3970
3971	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3972	# if 1 /** @todo sync accessed bit properly... */
3973	fIgnoreFlags \|= X86_PTE_A;
3974	# endif
3975
3976	/* match the physical addresses */
3977	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3978	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
3979
3980	# ifdef IN_RING3
3981	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3982	if (RT_FAILURE(rc))
3983	{
3984	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3985	{
3986	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3987	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3988	cErrors++;
3989	continue;
3990	}
3991	}
3992	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3993	{
3994	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
3995	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
3996	cErrors++;
3997	continue;
3998	}
3999	# endif
4000
4001	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4002	if (!pPhysPage)
4003	{
4004	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4005	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4006	{
4007	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4008	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4009	cErrors++;
4010	continue;
4011	}
4012	# endif
4013	if (SHW_PTE_IS_RW(PteDst))
4014	{
4015	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4016	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4017	cErrors++;
4018	}
4019	fIgnoreFlags \|= X86_PTE_RW;
4020	}
4021	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4022	{
4023	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4024	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4025	cErrors++;
4026	continue;
4027	}
4028
4029	/* flags */
4030	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4031	{
4032	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4033	{
4034	if (SHW_PTE_IS_RW(PteDst))
4035	{
4036	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4037	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4038	cErrors++;
4039	continue;
4040	}
4041	fIgnoreFlags \|= X86_PTE_RW;
4042	}
4043	else
4044	{
4045	if ( SHW_PTE_IS_P(PteDst)
4046	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4047	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4048	# endif
4049	)
4050	{
4051	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4052	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4053	cErrors++;
4054	continue;
4055	}
4056	fIgnoreFlags \|= X86_PTE_P;
4057	}
4058	}
4059	else
4060	{
4061	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4062	{
4063	if (SHW_PTE_IS_RW(PteDst))
4064	{
4065	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4066	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4067	cErrors++;
4068	continue;
4069	}
4070	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4071	{
4072	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4073	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4074	cErrors++;
4075	continue;
4076	}
4077	if (SHW_PTE_IS_D(PteDst))
4078	{
4079	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4080	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4081	cErrors++;
4082	}
4083	# if 0 /** @todo sync access bit properly... */
4084	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4085	{
4086	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4087	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4088	cErrors++;
4089	}
4090	fIgnoreFlags \|= X86_PTE_RW;
4091	# else
4092	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4093	# endif
4094	}
4095	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4096	{
4097	/* access bit emulation (not implemented). */
4098	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4099	{
4100	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4101	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4102	cErrors++;
4103	continue;
4104	}
4105	if (!SHW_PTE_IS_A(PteDst))
4106	{
4107	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4108	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4109	cErrors++;
4110	}
4111	fIgnoreFlags \|= X86_PTE_P;
4112	}
4113	# ifdef DEBUG_sandervl
4114	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4115	# endif
4116	}
4117
4118	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4119	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4120	)
4121	{
4122	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4123	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4124	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4125	cErrors++;
4126	continue;
4127	}
4128	} /* foreach PTE */
4129	}
4130	else
4131	{
4132	/*
4133	* Big Page.
4134	*/
4135	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4136	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4137	{
4138	if (PdeDst.n.u1Write)
4139	{
4140	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4141	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4142	cErrors++;
4143	continue;
4144	}
4145	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4146	{
4147	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4148	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4149	cErrors++;
4150	continue;
4151	}
4152	# if 0 /** @todo sync access bit properly... */
4153	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4154	{
4155	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4156	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4157	cErrors++;
4158	}
4159	fIgnoreFlags \|= X86_PTE_RW;
4160	# else
4161	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4162	# endif
4163	}
4164	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4165	{
4166	/* access bit emulation (not implemented). */
4167	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4168	{
4169	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4170	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4171	cErrors++;
4172	continue;
4173	}
4174	if (!PdeDst.n.u1Accessed)
4175	{
4176	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4177	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4178	cErrors++;
4179	}
4180	fIgnoreFlags \|= X86_PTE_P;
4181	}
4182
4183	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4184	{
4185	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4186	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4187	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4188	cErrors++;
4189	}
4190
4191	/* iterate the page table. */
4192	for (unsigned iPT = 0, off = 0;
4193	iPT < RT_ELEMENTS(pPTDst->a);
4194	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4195	{
4196	const SHWPTE PteDst = pPTDst->a[iPT];
4197
4198	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4199	{
4200	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4201	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4202	cErrors++;
4203	}
4204
4205	/* skip not-present entries. */
4206	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4207	continue;
4208
4209	fIgnoreFlags = X86_PTE_PAE_PG_MASK_FULL \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4210
4211	/* match the physical addresses */
4212	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4213
4214	# ifdef IN_RING3
4215	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4216	if (RT_FAILURE(rc))
4217	{
4218	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4219	{
4220	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4221	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4222	cErrors++;
4223	}
4224	}
4225	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4226	{
4227	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4228	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4229	cErrors++;
4230	continue;
4231	}
4232	# endif
4233	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4234	if (!pPhysPage)
4235	{
4236	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4237	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4238	{
4239	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4240	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4241	cErrors++;
4242	continue;
4243	}
4244	# endif
4245	if (SHW_PTE_IS_RW(PteDst))
4246	{
4247	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4248	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4249	cErrors++;
4250	}
4251	fIgnoreFlags \|= X86_PTE_RW;
4252	}
4253	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4254	{
4255	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4256	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4257	cErrors++;
4258	continue;
4259	}
4260
4261	/* flags */
4262	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4263	{
4264	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4265	{
4266	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4267	{
4268	if (SHW_PTE_IS_RW(PteDst))
4269	{
4270	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4271	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4272	cErrors++;
4273	continue;
4274	}
4275	fIgnoreFlags \|= X86_PTE_RW;
4276	}
4277	}
4278	else
4279	{
4280	if ( SHW_PTE_IS_P(PteDst)
4281	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4282	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4283	# endif
4284	)
4285	{
4286	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4287	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4288	cErrors++;
4289	continue;
4290	}
4291	fIgnoreFlags \|= X86_PTE_P;
4292	}
4293	}
4294
4295	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4296	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4297	)
4298	{
4299	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4300	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4301	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4302	cErrors++;
4303	continue;
4304	}
4305	} /* for each PTE */
4306	}
4307	}
4308	/* not present */
4309
4310	} /* for each PDE */
4311
4312	} /* for each PDPTE */
4313
4314	} /* for each PML4E */
4315
4316	# ifdef DEBUG
4317	if (cErrors)
4318	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4319	# endif
4320
4321	#endif /* GST == 32BIT, PAE or AMD64 */
4322	return cErrors;
4323
4324	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4325	}
4326	#endif /* VBOX_STRICT */
4327
4328
4329	/**
4330	* Sets up the CR3 for shadow paging
4331	*
4332	* @returns Strict VBox status code.
4333	* @retval VINF_SUCCESS.
4334	*
4335	* @param pVCpu The VMCPU handle.
4336	* @param GCPhysCR3 The physical address in the CR3 register.
4337	*/
4338	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4339	{
4340	PVM pVM = pVCpu->CTX_SUFF(pVM);
4341
4342	/* Update guest paging info. */
4343	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4344	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4345	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4346
4347	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4348
4349	/*
4350	* Map the page CR3 points at.
4351	*/
4352	RTHCPTR HCPtrGuestCR3;
4353	RTHCPHYS HCPhysGuestCR3;
4354	pgmLock(pVM);
4355	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4356	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4357	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4358	/** @todo this needs some reworking wrt. locking? */
4359	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4360	HCPtrGuestCR3 = NIL_RTHCPTR;
4361	int rc = VINF_SUCCESS;
4362	# else
4363	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4364	# endif
4365	pgmUnlock(pVM);
4366	if (RT_SUCCESS(rc))
4367	{
4368	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4369	if (RT_SUCCESS(rc))
4370	{
4371	# ifdef IN_RC
4372	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4373	# endif
4374	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4375	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4376	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4377	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4378	# endif
4379	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4380
4381	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4382	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4383	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4384	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4385	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4386	# endif
4387	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4388	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4389
4390	/*
4391	* Map the 4 PDs too.
4392	*/
4393	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4394	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4395	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4396	{
4397	if (pGuestPDPT->a[i].n.u1Present)
4398	{
4399	RTHCPTR HCPtr;
4400	RTHCPHYS HCPhys;
4401	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4402	pgmLock(pVM);
4403	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4404	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4405	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4406	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4407	HCPtr = NIL_RTHCPTR;
4408	int rc2 = VINF_SUCCESS;
4409	# else
4410	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4411	# endif
4412	pgmUnlock(pVM);
4413	if (RT_SUCCESS(rc2))
4414	{
4415	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4416	AssertRCReturn(rc, rc);
4417
4418	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4419	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4420	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4421	# endif
4422	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4423	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4424	# ifdef IN_RC
4425	PGM_INVL_PG(pVCpu, GCPtr);
4426	# endif
4427	continue;
4428	}
4429	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4430	}
4431
4432	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4433	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4434	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4435	# endif
4436	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4437	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4438	# ifdef IN_RC
4439	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4440	# endif
4441	}
4442
4443	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4444	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4445	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4446	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4447	# endif
4448	# endif
4449	}
4450	else
4451	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4452	}
4453	else
4454	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4455
4456	#else /* prot/real stub */
4457	int rc = VINF_SUCCESS;
4458	#endif
4459
4460	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4461	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4462	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4463	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4464	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4465	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4466
4467	Assert(!pVM->pgm.s.fNestedPaging);
4468
4469	/*
4470	* Update the shadow root page as well since that's not fixed.
4471	*/
4472	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4473	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4474	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4475	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4476	PPGMPOOLPAGE pNewShwPageCR3;
4477
4478	pgmLock(pVM);
4479
4480	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4481	if (pPool->cDirtyPages)
4482	pgmPoolResetDirtyPages(pVM);
4483	# endif
4484
4485	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4486	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4487	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4488	AssertFatalRC(rc);
4489	rc = VINF_SUCCESS;
4490
4491	# ifdef IN_RC
4492	/*
4493	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4494	* state will be inconsistent! Flush important things now while
4495	* we still can and then make sure there are no ring-3 calls.
4496	*/
4497	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4498	VMMRZCallRing3Disable(pVCpu);
4499	# endif
4500
4501	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4502	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4503	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4504	# ifdef IN_RING0
4505	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4506	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4507	# elif defined(IN_RC)
4508	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4509	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4510	# else
4511	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4512	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4513	# endif
4514
4515	# ifndef PGM_WITHOUT_MAPPINGS
4516	/*
4517	* Apply all hypervisor mappings to the new CR3.
4518	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4519	* make sure we check for conflicts in the new CR3 root.
4520	*/
4521	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4522	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4523	# endif
4524	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4525	AssertRCReturn(rc, rc);
4526	# endif
4527
4528	/* Set the current hypervisor CR3. */
4529	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4530	SELMShadowCR3Changed(pVM, pVCpu);
4531
4532	# ifdef IN_RC
4533	/* NOTE: The state is consistent again. */
4534	VMMRZCallRing3Enable(pVCpu);
4535	# endif
4536
4537	/* Clean up the old CR3 root. */
4538	if ( pOldShwPageCR3
4539	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4540	{
4541	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4542	# ifndef PGM_WITHOUT_MAPPINGS
4543	/* Remove the hypervisor mappings from the shadow page table. */
4544	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4545	# endif
4546	/* Mark the page as unlocked; allow flushing again. */
4547	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4548
4549	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4550	}
4551	pgmUnlock(pVM);
4552	# endif
4553
4554	return rc;
4555	}
4556
4557	/**
4558	* Unmaps the shadow CR3.
4559	*
4560	* @returns VBox status, no specials.
4561	* @param pVCpu The VMCPU handle.
4562	*/
4563	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4564	{
4565	LogFlow(("UnmapCR3\n"));
4566
4567	int rc = VINF_SUCCESS;
4568	PVM pVM = pVCpu->CTX_SUFF(pVM);
4569
4570	/*
4571	* Update guest paging info.
4572	*/
4573	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4574	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4575	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4576	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4577	# endif
4578	pVCpu->pgm.s.pGst32BitPdRC = 0;
4579
4580	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4581	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4582	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4583	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4584	# endif
4585	pVCpu->pgm.s.pGstPaePdptRC = 0;
4586	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4587	{
4588	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4589	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4590	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4591	# endif
4592	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4593	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4594	}
4595
4596	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4597	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4598	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4599	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4600	# endif
4601
4602	#else /* prot/real mode stub */
4603	/* nothing to do */
4604	#endif
4605
4606	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4607	/*
4608	* Update shadow paging info.
4609	*/
4610	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4611	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4612	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4613
4614	# if PGM_GST_TYPE != PGM_TYPE_REAL
4615	Assert(!pVM->pgm.s.fNestedPaging);
4616	# endif
4617
4618	pgmLock(pVM);
4619
4620	# ifndef PGM_WITHOUT_MAPPINGS
4621	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4622	/* Remove the hypervisor mappings from the shadow page table. */
4623	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4624	# endif
4625
4626	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4627	{
4628	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4629
4630	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4631
4632	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4633	if (pPool->cDirtyPages)
4634	pgmPoolResetDirtyPages(pVM);
4635	# endif
4636
4637	/* Mark the page as unlocked; allow flushing again. */
4638	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4639
4640	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4641	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4642	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4643	pVCpu->pgm.s.pShwPageCR3RC = 0;
4644	pVCpu->pgm.s.iShwUser = 0;
4645	pVCpu->pgm.s.iShwUserTable = 0;
4646	}
4647	pgmUnlock(pVM);
4648	# endif
4649	#endif /* !IN_RC*/
4650
4651	return rc;
4652	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 32027

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