PGMAllBth.h@ 32384

Last change on this file since 32384 was 32384, checked in by vboxsync, 14 years ago
Extended dirty page optimization for the pae/32-bit shw/gst combination (disabled).
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File size: 200.3 KB

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1	/* $Id: PGMAllBth.h 32384 2010-09-10 09:57:16Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	PGM_INVL_PG(pVCpu, pvFault);
561	return rc; /* Restart with the corrected entry. */
562	}
563	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
564
565	/*
566	* Fetch the guest PDE, PDPE and PML4E.
567	*/
568	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
569	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
570	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
571
572	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
573	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
574	PX86PDPAE pPDDst;
575	# if PGM_GST_TYPE == PGM_TYPE_PAE
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
577	# else
578	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
579	# endif
580	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
583	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
586	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
587	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
588	# else
589	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
590	# endif
591	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
592
593	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
594	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
595	PEPTPD pPDDst;
596	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
597	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
598	# endif
599	Assert(pPDDst);
600
601	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
602	/*
603	* Dirty page handling.
604	*
605	* If we successfully correct the write protection fault due to dirty bit
606	* tracking, then return immediately.
607	*/
608	if (uErr & X86_TRAP_PF_RW) /* write fault? */
609	{
610	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
612	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
613	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
614	{
615	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
616	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
617	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
618	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
619	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
620	return VINF_SUCCESS;
621	}
622	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
623	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
624	}
625
626	# if 0 /* rarely useful; leave for debugging. */
627	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
628	# endif
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630
631	/*
632	* A common case is the not-present error caused by lazy page table syncing.
633	*
634	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
635	* here so we can safely assume that the shadow PT is present when calling
636	* SyncPage later.
637	*
638	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
639	* of mapping conflict and defer to SyncCR3 in R3.
640	* (Again, we do NOT support access handlers for non-present guest pages.)
641	*
642	*/
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
644	Assert(GstWalk.Pde.n.u1Present);
645	# endif
646	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
647	&& !pPDDst->a[iPDDst].n.u1Present)
648	{
649	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
650	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
651	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
652	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
653	# else
654	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
655	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
656	# endif
657	if (RT_SUCCESS(rc))
658	return rc;
659	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
660	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
661	return VINF_PGM_SYNC_CR3;
662	}
663
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
665	/*
666	* Check if this address is within any of our mappings.
667	*
668	* This is very fast and it's gonna save us a bit of effort below and prevent
669	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
670	* (BTW, it's impossible to have physical access handlers in a mapping.)
671	*/
672	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
673	{
674	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
675	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
676	{
677	if (pvFault < pMapping->GCPtr)
678	break;
679	if (pvFault - pMapping->GCPtr < pMapping->cb)
680	{
681	/*
682	* The first thing we check is if we've got an undetected conflict.
683	*/
684	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
685	{
686	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
687	while (iPT-- > 0)
688	if (GstWalk.pPde[iPT].n.u1Present)
689	{
690	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
691	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
692	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
693	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
694	return VINF_PGM_SYNC_CR3;
695	}
696	}
697
698	/*
699	* Check if the fault address is in a virtual page access handler range.
700	*/
701	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
702	if ( pCur
703	&& pvFault - pCur->Core.Key < pCur->cb
704	&& uErr & X86_TRAP_PF_RW)
705	{
706	# ifdef IN_RC
707	STAM_PROFILE_START(&pCur->Stat, h);
708	pgmUnlock(pVM);
709	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
710	pgmLock(pVM);
711	STAM_PROFILE_STOP(&pCur->Stat, h);
712	# else
713	AssertFailed();
714	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
715	# endif
716	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
717	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
718	return rc;
719	}
720
721	/*
722	* Pretend we're not here and let the guest handle the trap.
723	*/
724	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
725	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
726	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return VINF_EM_RAW_GUEST_TRAP;
729	}
730	}
731	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
732	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
733
734	/*
735	* Check if this fault address is flagged for special treatment,
736	* which means we'll have to figure out the physical address and
737	* check flags associated with it.
738	*
739	* ASSUME that we can limit any special access handling to pages
740	* in page tables which the guest believes to be present.
741	*/
742	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
743	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# else
745	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
746	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
747	PPGMPAGE pPage;
748	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
749	if (RT_FAILURE(rc))
750	{
751	/*
752	* When the guest accesses invalid physical memory (e.g. probing
753	* of RAM or accessing a remapped MMIO range), then we'll fall
754	* back to the recompiler to emulate the instruction.
755	*/
756	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
757	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
758	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
759	return VINF_EM_RAW_EMULATE_INSTR;
760	}
761
762	/*
763	* Any handlers for this page?
764	*/
765	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
766	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
767	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
768	&GstWalk));
769	# else
770	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
771	# endif
772
773	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
774
775	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
776	if (uErr & X86_TRAP_PF_P)
777	{
778	/*
779	* The page isn't marked, but it might still be monitored by a virtual page access handler.
780	* (ASSUMES no temporary disabling of virtual handlers.)
781	*/
782	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
783	* we should correct both the shadow page table and physical memory flags, and not only check for
784	* accesses within the handler region but for access to pages with virtual handlers. */
785	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
786	if (pCur)
787	{
788	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
789	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
790	\|\| !(uErr & X86_TRAP_PF_P)
791	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
792	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
793
794	if ( pvFault - pCur->Core.Key < pCur->cb
795	&& ( uErr & X86_TRAP_PF_RW
796	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
797	{
798	# ifdef IN_RC
799	STAM_PROFILE_START(&pCur->Stat, h);
800	pgmUnlock(pVM);
801	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
802	pgmLock(pVM);
803	STAM_PROFILE_STOP(&pCur->Stat, h);
804	# else
805	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
806	# endif
807	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
808	return rc;
809	}
810	}
811	}
812	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
813
814	/*
815	* We are here only if page is present in Guest page tables and
816	* trap is not handled by our handlers.
817	*
818	* Check it for page out-of-sync situation.
819	*/
820	if (!(uErr & X86_TRAP_PF_P))
821	{
822	/*
823	* Page is not present in our page tables. Try to sync it!
824	*/
825	if (uErr & X86_TRAP_PF_US)
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
827	else /* supervisor */
828	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
829
830	if (PGM_PAGE_IS_BALLOONED(pPage))
831	{
832	/* Emulate reads from ballooned pages as they are not present in
833	our shadow page tables. (Required for e.g. Solaris guests; soft
834	ecc, random nr generator.) */
835	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
836	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
838	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
839	return rc;
840	}
841
842	# if defined(LOG_ENABLED) && !defined(IN_RING0)
843	RTGCPHYS GCPhys2;
844	uint64_t fPageGst2;
845	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
846	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
847	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
848	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
849	# else
850	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
851	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
852	# endif
853	# endif /* LOG_ENABLED */
854
855	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
856	if ( !GstWalk.Core.fEffectiveUS
857	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
858	{
859	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
860	if ( pvFault == (RTGCPTR)pRegFrame->eip
861	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
862	# ifdef CSAM_DETECT_NEW_CODE_PAGES
863	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
864	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
865	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
866	)
867	{
868	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
869	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
870	if (rc != VINF_SUCCESS)
871	{
872	/*
873	* CSAM needs to perform a job in ring 3.
874	*
875	* Sync the page before going to the host context; otherwise we'll end up in a loop if
876	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
877	*/
878	LogFlow(("CSAM ring 3 job\n"));
879	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
880	AssertRC(rc2);
881
882	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
883	return rc;
884	}
885	}
886	# ifdef CSAM_DETECT_NEW_CODE_PAGES
887	else if ( uErr == X86_TRAP_PF_RW
888	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
889	&& pRegFrame->ecx < 0x10000)
890	{
891	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
892	* to detect loading of new code pages.
893	*/
894
895	/*
896	* Decode the instruction.
897	*/
898	RTGCPTR PC;
899	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
900	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
901	if (rc == VINF_SUCCESS)
902	{
903	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
904	uint32_t cbOp;
905	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
906
907	/* For now we'll restrict this to rep movsw/d instructions */
908	if ( rc == VINF_SUCCESS
909	&& pDis->pCurInstr->opcode == OP_MOVSWD
910	&& (pDis->prefix & PREFIX_REP))
911	{
912	CSAMMarkPossibleCodePage(pVM, pvFault);
913	}
914	}
915	}
916	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
917
918	/*
919	* Mark this page as safe.
920	*/
921	/** @todo not correct for pages that contain both code and data!! */
922	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
923	CSAMMarkPage(pVM, pvFault, true);
924	}
925	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
926	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# else
929	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
930	# endif
931	if (RT_SUCCESS(rc))
932	{
933	/* The page was successfully synced, return to the guest. */
934	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
935	return VINF_SUCCESS;
936	}
937	}
938	else /* uErr & X86_TRAP_PF_P: */
939	{
940	/*
941	* Write protected pages are made writable when the guest makes the
942	* first write to it. This happens for pages that are shared, write
943	* monitored or not yet allocated.
944	*
945	* We may also end up here when CR0.WP=0 in the guest.
946	*
947	* Also, a side effect of not flushing global PDEs are out of sync
948	* pages due to physical monitored regions, that are no longer valid.
949	* Assume for now it only applies to the read/write flag.
950	*/
951	if (uErr & X86_TRAP_PF_RW)
952	{
953	/*
954	* Check if it is a read-only page.
955	*/
956	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
957	{
958	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
959	Assert(!PGM_PAGE_IS_ZERO(pPage));
960	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
961	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
962
963	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
964	if (rc != VINF_SUCCESS)
965	{
966	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
967	return rc;
968	}
969	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
970	return VINF_EM_NO_MEMORY;
971	}
972
973	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
974	/*
975	* Check to see if we need to emulate the instruction if CR0.WP=0.
976	*/
977	if ( !GstWalk.Core.fEffectiveRW
978	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
979	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
980	{
981	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
982	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
983	if (RT_SUCCESS(rc))
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
985	else
986	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
987	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
988	return rc;
989	}
990	# endif
991	/// @todo count the above case; else
992	if (uErr & X86_TRAP_PF_US)
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
994	else /* supervisor */
995	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
996
997	/*
998	* Sync the page.
999	*
1000	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1001	* page is not present, which is not true in this case.
1002	*/
1003	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1005	# else
1006	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1007	# endif
1008	if (RT_SUCCESS(rc))
1009	{
1010	/*
1011	* Page was successfully synced, return to guest but invalidate
1012	* the TLB first as the page is very likely to be in it.
1013	*/
1014	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1015	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1016	# else
1017	PGM_INVL_PG(pVCpu, pvFault);
1018	# endif
1019	# ifdef VBOX_STRICT
1020	RTGCPHYS GCPhys2;
1021	uint64_t fPageGst;
1022	if (!pVM->pgm.s.fNestedPaging)
1023	{
1024	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1025	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1026	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1027	}
1028	uint64_t fPageShw;
1029	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1030	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1031	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1032	# endif /* VBOX_STRICT */
1033	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1034	return VINF_SUCCESS;
1035	}
1036	}
1037	/** @todo else: why are we here? */
1038
1039	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1040	/*
1041	* Check for VMM page flags vs. Guest page flags consistency.
1042	* Currently only for debug purposes.
1043	*/
1044	if (RT_SUCCESS(rc))
1045	{
1046	/* Get guest page flags. */
1047	uint64_t fPageGst;
1048	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1049	if (RT_SUCCESS(rc))
1050	{
1051	uint64_t fPageShw;
1052	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1053
1054	/*
1055	* Compare page flags.
1056	* Note: we have AVL, A, D bits desynched.
1057	*/
1058	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1059	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1060	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1061	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1062	}
1063	else
1064	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1065	}
1066	else
1067	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1068	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1069	}
1070
1071
1072	/*
1073	* If we get here it is because something failed above, i.e. most like guru
1074	* meditiation time.
1075	*/
1076	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1077	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1078	return rc;
1079
1080	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1081	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1082	return VERR_INTERNAL_ERROR;
1083	# endif
1084	}
1085	#endif /* !IN_RING3 */
1086
1087
1088	/**
1089	* Emulation of the invlpg instruction.
1090	*
1091	*
1092	* @returns VBox status code.
1093	*
1094	* @param pVCpu The VMCPU handle.
1095	* @param GCPtrPage Page to invalidate.
1096	*
1097	* @remark ASSUMES that the guest is updating before invalidating. This order
1098	* isn't required by the CPU, so this is speculative and could cause
1099	* trouble.
1100	* @remark No TLB shootdown is done on any other VCPU as we assume that
1101	* invlpg emulation is the only reason for calling this function.
1102	* (The guest has to shoot down TLB entries on other CPUs itself)
1103	* Currently true, but keep in mind!
1104	*
1105	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1106	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1107	*/
1108	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1109	{
1110	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1111	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1112	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1113	int rc;
1114	PVM pVM = pVCpu->CTX_SUFF(pVM);
1115	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1116
1117	Assert(PGMIsLockOwner(pVM));
1118
1119	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1120
1121	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1122	/** @todo this shouldn't be necessary. */
1123	if (pPool->cDirtyPages)
1124	pgmPoolResetDirtyPages(pVM);
1125	# endif
1126
1127	/*
1128	* Get the shadow PD entry and skip out if this PD isn't present.
1129	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1130	*/
1131	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1132	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1133	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1134
1135	/* Fetch the pgm pool shadow descriptor. */
1136	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1137	Assert(pShwPde);
1138
1139	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1140	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1141	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1142
1143	/* If the shadow PDPE isn't present, then skip the invalidate. */
1144	if (!pPdptDst->a[iPdpt].n.u1Present)
1145	{
1146	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1147	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1148	return VINF_SUCCESS;
1149	}
1150
1151	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1152	PPGMPOOLPAGE pShwPde = NULL;
1153	PX86PDPAE pPDDst;
1154
1155	/* Fetch the pgm pool shadow descriptor. */
1156	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1157	AssertRCSuccessReturn(rc, rc);
1158	Assert(pShwPde);
1159
1160	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1161	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1162
1163	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1164	/* PML4 */
1165	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1166	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1167	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1168	PX86PDPAE pPDDst;
1169	PX86PDPT pPdptDst;
1170	PX86PML4E pPml4eDst;
1171	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1172	if (rc != VINF_SUCCESS)
1173	{
1174	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1175	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1176	return VINF_SUCCESS;
1177	}
1178	Assert(pPDDst);
1179
1180	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1181	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1182
1183	if (!pPdpeDst->n.u1Present)
1184	{
1185	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1186	return VINF_SUCCESS;
1187	}
1188
1189	/* Fetch the pgm pool shadow descriptor. */
1190	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1191	Assert(pShwPde);
1192
1193	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1194
1195	const SHWPDE PdeDst = *pPdeDst;
1196	if (!PdeDst.n.u1Present)
1197	{
1198	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1199	return VINF_SUCCESS;
1200	}
1201
1202	/*
1203	* Get the guest PD entry and calc big page.
1204	*/
1205	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1206	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1207	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1208	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1209	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1210	unsigned iPDSrc = 0;
1211	# if PGM_GST_TYPE == PGM_TYPE_PAE
1212	X86PDPE PdpeSrcIgn;
1213	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1214	# else /* AMD64 */
1215	PX86PML4E pPml4eSrcIgn;
1216	X86PDPE PdpeSrcIgn;
1217	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1218	# endif
1219	GSTPDE PdeSrc;
1220
1221	if (pPDSrc)
1222	PdeSrc = pPDSrc->a[iPDSrc];
1223	else
1224	PdeSrc.u = 0;
1225	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1226	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1227
1228	# ifdef IN_RING3
1229	/*
1230	* If a CR3 Sync is pending we may ignore the invalidate page operation
1231	* depending on the kind of sync and if it's a global page or not.
1232	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1233	*/
1234	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1235	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1236	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1237	&& fIsBigPage
1238	&& PdeSrc.b.u1Global
1239	)
1240	)
1241	# else
1242	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1243	# endif
1244	{
1245	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1246	return VINF_SUCCESS;
1247	}
1248	# endif /* IN_RING3 */
1249
1250	/*
1251	* Deal with the Guest PDE.
1252	*/
1253	rc = VINF_SUCCESS;
1254	if (PdeSrc.n.u1Present)
1255	{
1256	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1257	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1258	# ifndef PGM_WITHOUT_MAPPING
1259	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1260	{
1261	/*
1262	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1263	*/
1264	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1265	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1267	}
1268	else
1269	# endif /* !PGM_WITHOUT_MAPPING */
1270	if (!fIsBigPage)
1271	{
1272	/*
1273	* 4KB - page.
1274	*/
1275	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1276	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1277
1278	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1279	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1280	if (pShwPage->cModifications)
1281	pShwPage->cModifications = 1;
1282	# endif
1283
1284	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1285	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1286	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1287	# endif
1288	if (pShwPage->GCPhys == GCPhys)
1289	{
1290	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1291	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1292	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1293	if (pPT->a[iPTEDst].n.u1Present)
1294	{
1295	/* This is very unlikely with caching/monitoring enabled. */
1296	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1297	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1298	}
1299	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1300	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1301	if (RT_SUCCESS(rc))
1302	rc = VINF_SUCCESS;
1303	# endif
1304	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1305	PGM_INVL_PG(pVCpu, GCPtrPage);
1306	}
1307	else
1308	{
1309	/*
1310	* The page table address changed.
1311	*/
1312	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1313	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1314	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1315	ASMAtomicWriteSize(pPdeDst, 0);
1316	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1317	PGM_INVL_VCPU_TLBS(pVCpu);
1318	}
1319	}
1320	else
1321	{
1322	/*
1323	* 2/4MB - page.
1324	*/
1325	/* Before freeing the page, check if anything really changed. */
1326	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1327	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1328	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1329	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1330	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1331	# endif
1332	if ( pShwPage->GCPhys == GCPhys
1333	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1334	{
1335	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1336	/** @todo This test is wrong as it cannot check the G bit!
1337	* FIXME */
1338	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1339	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1340	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1341	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1342	{
1343	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1344	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1345	return VINF_SUCCESS;
1346	}
1347	}
1348
1349	/*
1350	* Ok, the page table is present and it's been changed in the guest.
1351	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1352	* We could do this for some flushes in GC too, but we need an algorithm for
1353	* deciding which 4MB pages containing code likely to be executed very soon.
1354	*/
1355	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1356	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1357	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1358	ASMAtomicWriteSize(pPdeDst, 0);
1359	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1360	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1361	}
1362	}
1363	else
1364	{
1365	/*
1366	* Page directory is not present, mark shadow PDE not present.
1367	*/
1368	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1369	{
1370	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1371	ASMAtomicWriteSize(pPdeDst, 0);
1372	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1373	PGM_INVL_PG(pVCpu, GCPtrPage);
1374	}
1375	else
1376	{
1377	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1378	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1379	}
1380	}
1381	return rc;
1382
1383	#else /* guest real and protected mode */
1384	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1385	return VINF_SUCCESS;
1386	#endif
1387	}
1388
1389
1390	/**
1391	* Update the tracking of shadowed pages.
1392	*
1393	* @param pVCpu The VMCPU handle.
1394	* @param pShwPage The shadow page.
1395	* @param HCPhys The physical page we is being dereferenced.
1396	* @param iPte Shadow PTE index
1397	*/
1398	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1399	{
1400	PVM pVM = pVCpu->CTX_SUFF(pVM);
1401
1402	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1403	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1404
1405	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1406	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1407	* 2. write protect all shadowed pages. I.e. implement caching.
1408	*/
1409	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1410
1411	/*
1412	* Find the guest address.
1413	*/
1414	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1415	pRam;
1416	pRam = pRam->CTX_SUFF(pNext))
1417	{
1418	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1419	while (iPage-- > 0)
1420	{
1421	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1422	{
1423	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1424
1425	Assert(pShwPage->cPresent);
1426	Assert(pPool->cPresent);
1427	pShwPage->cPresent--;
1428	pPool->cPresent--;
1429
1430	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1431	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1432	return;
1433	}
1434	}
1435	}
1436
1437	for (;;)
1438	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1439	}
1440
1441
1442	/**
1443	* Update the tracking of shadowed pages.
1444	*
1445	* @param pVCpu The VMCPU handle.
1446	* @param pShwPage The shadow page.
1447	* @param u16 The top 16-bit of the pPage->HCPhys.
1448	* @param pPage Pointer to the guest page. this will be modified.
1449	* @param iPTDst The index into the shadow table.
1450	*/
1451	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1452	{
1453	PVM pVM = pVCpu->CTX_SUFF(pVM);
1454
1455	/*
1456	* Just deal with the simple first time here.
1457	*/
1458	if (!u16)
1459	{
1460	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1461	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1462	/* Save the page table index. */
1463	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1464	}
1465	else
1466	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1467
1468	/* write back */
1469	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1470	PGM_PAGE_SET_TRACKING(pPage, u16);
1471
1472	/* update statistics. */
1473	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1474	pShwPage->cPresent++;
1475	if (pShwPage->iFirstPresent > iPTDst)
1476	pShwPage->iFirstPresent = iPTDst;
1477	}
1478
1479
1480	/**
1481	* Modifies a shadow PTE to account for access handlers.
1482	*
1483	* @param pVM The VM handle.
1484	* @param pPage The page in question.
1485	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1486	* A (accessed) bit so it can be emulated correctly.
1487	* @param pPteDst The shadow PTE (output). This is temporary storage and
1488	* does not need to be set atomically.
1489	*/
1490	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1491	{
1492	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1493	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1494	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1495	{
1496	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1497	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1498	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1499	pPteDst->n.u1Present = 1;
1500	pPteDst->n.u1Execute = 1;
1501	pPteDst->n.u1IgnorePAT = 1;
1502	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1503	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1504	#else
1505	if (fPteSrc & X86_PTE_A)
1506	{
1507	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1508	SHW_PTE_SET_RO(*pPteDst);
1509	}
1510	else
1511	SHW_PTE_SET(*pPteDst, 0);
1512	#endif
1513	}
1514	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1515	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1516	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1517	&& ( BTH_IS_NP_ACTIVE(pVM)
1518	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1519	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1520	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1521	# endif
1522	)
1523	{
1524	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1525	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1526	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1527	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1528	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1529	pPteDst->n.u1Present = 0;
1530	pPteDst->n.u1Write = 1;
1531	pPteDst->n.u1Execute = 0;
1532	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1533	pPteDst->n.u3EMT = 7;
1534	# else
1535	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1536	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1537	# endif
1538	}
1539	# endif
1540	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1541	else
1542	{
1543	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1544	SHW_PTE_SET(*pPteDst, 0);
1545	}
1546	/** @todo count these kinds of entries. */
1547	}
1548
1549
1550	/**
1551	* Creates a 4K shadow page for a guest page.
1552	*
1553	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1554	* physical address. The PdeSrc argument only the flags are used. No page
1555	* structured will be mapped in this function.
1556	*
1557	* @param pVCpu The VMCPU handle.
1558	* @param pPteDst Destination page table entry.
1559	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1560	* Can safely assume that only the flags are being used.
1561	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1562	* @param pShwPage Pointer to the shadow page.
1563	* @param iPTDst The index into the shadow table.
1564	*
1565	* @remark Not used for 2/4MB pages!
1566	*/
1567	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1568	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1569	{
1570	PVM pVM = pVCpu->CTX_SUFF(pVM);
1571
1572	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1573	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1574	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1575	if (pShwPage->fDirty)
1576	{
1577	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1578	PX86PTPAE pGstPT;
1579
1580	pGstPT = (PX86PTPAE)&pPool->aDirtyPages[pShwPage->idxDirty].aPage[0];
1581	pGstPT->a[iPTDst].u = PteSrc.u;
1582	}
1583	# else
1584	Assert(!pShwPage->fDirty);
1585	# endif
1586
1587	if ( PteSrc.n.u1Present
1588	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1589	{
1590	/*
1591	* Find the ram range.
1592	*/
1593	PPGMPAGE pPage;
1594	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc), &pPage);
1595	if (RT_SUCCESS(rc))
1596	{
1597	/* Ignore ballooned pages.
1598	Don't return errors or use a fatal assert here as part of a
1599	shadow sync range might included ballooned pages. */
1600	if (PGM_PAGE_IS_BALLOONED(pPage))
1601	{
1602	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1603	return;
1604	}
1605
1606	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1607	/* Make the page writable if necessary. */
1608	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1609	&& ( PGM_PAGE_IS_ZERO(pPage)
1610	\|\| ( PteSrc.n.u1Write
1611	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1612	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1613	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1614	# endif
1615	# ifdef VBOX_WITH_PAGE_SHARING
1616	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1617	# endif
1618	)
1619	)
1620	)
1621	{
1622	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
1623	AssertRC(rc);
1624	}
1625	#endif
1626
1627	/*
1628	* Make page table entry.
1629	*/
1630	SHWPTE PteDst;
1631	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1632	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc), &PteDst);
1633	else
1634	{
1635	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1636	/*
1637	* If the page or page directory entry is not marked accessed,
1638	* we mark the page not present.
1639	*/
1640	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1641	{
1642	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1643	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1644	SHW_PTE_SET(PteDst, 0);
1645	}
1646	/*
1647	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1648	* when the page is modified.
1649	*/
1650	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1651	{
1652	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1653	SHW_PTE_SET(PteDst,
1654	GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc)
1655	\| PGM_PAGE_GET_HCPHYS(pPage)
1656	\| PGM_PTFLAGS_TRACK_DIRTY);
1657	SHW_PTE_SET_RO(PteDst);
1658	}
1659	else
1660	#endif
1661	{
1662	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1663	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1664	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1665	PteDst.n.u1Present = 1;
1666	PteDst.n.u1Write = 1;
1667	PteDst.n.u1Execute = 1;
1668	PteDst.n.u1IgnorePAT = 1;
1669	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1670	/* PteDst.n.u1Size = 0 */
1671	#else
1672	SHW_PTE_SET(PteDst, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1673	#endif
1674	}
1675
1676	/*
1677	* Make sure only allocated pages are mapped writable.
1678	*/
1679	if ( SHW_PTE_IS_P_RW(PteDst)
1680	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1681	{
1682	/* Still applies to shared pages. */
1683	Assert(!PGM_PAGE_IS_ZERO(pPage));
1684	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1685	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)GST_GET_PTE_GCPHYS(PteSrc), pPage, iPTDst));
1686	}
1687	}
1688
1689	/*
1690	* Keep user track up to date.
1691	*/
1692	if (SHW_PTE_IS_P(PteDst))
1693	{
1694	if (!SHW_PTE_IS_P(*pPteDst))
1695	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1696	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1697	{
1698	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1699	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1700	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1701	}
1702	}
1703	else if (SHW_PTE_IS_P(*pPteDst))
1704	{
1705	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1706	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1707	}
1708
1709	/*
1710	* Update statistics and commit the entry.
1711	*/
1712	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1713	if (!PteSrc.n.u1Global)
1714	pShwPage->fSeenNonGlobal = true;
1715	#endif
1716	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1717	return;
1718	}
1719
1720	/** @todo count these three different kinds. */
1721	Log2(("SyncPageWorker: invalid address in Pte\n"));
1722	}
1723	else if (!PteSrc.n.u1Present)
1724	Log2(("SyncPageWorker: page not present in Pte\n"));
1725	else
1726	Log2(("SyncPageWorker: invalid Pte\n"));
1727
1728	/*
1729	* The page is not present or the PTE is bad. Replace the shadow PTE by
1730	* an empty entry, making sure to keep the user tracking up to date.
1731	*/
1732	if (SHW_PTE_IS_P(*pPteDst))
1733	{
1734	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1735	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1736	}
1737	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1738	}
1739
1740
1741	/**
1742	* Syncs a guest OS page.
1743	*
1744	* There are no conflicts at this point, neither is there any need for
1745	* page table allocations.
1746	*
1747	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1748	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1749	*
1750	* @returns VBox status code.
1751	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1752	* @param pVCpu The VMCPU handle.
1753	* @param PdeSrc Page directory entry of the guest.
1754	* @param GCPtrPage Guest context page address.
1755	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1756	* @param uErr Fault error (X86_TRAP_PF_*).
1757	*/
1758	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1759	{
1760	PVM pVM = pVCpu->CTX_SUFF(pVM);
1761	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1762	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1763
1764	Assert(PGMIsLockOwner(pVM));
1765
1766	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1767	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1768	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1769	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1770	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1771
1772	/*
1773	* Assert preconditions.
1774	*/
1775	Assert(PdeSrc.n.u1Present);
1776	Assert(cPages);
1777	# if 0 /* rarely useful; leave for debugging. */
1778	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1779	# endif
1780
1781	/*
1782	* Get the shadow PDE, find the shadow page table in the pool.
1783	*/
1784	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1785	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1786	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1787
1788	/* Fetch the pgm pool shadow descriptor. */
1789	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1790	Assert(pShwPde);
1791
1792	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1793	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1794	PPGMPOOLPAGE pShwPde = NULL;
1795	PX86PDPAE pPDDst;
1796
1797	/* Fetch the pgm pool shadow descriptor. */
1798	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1799	AssertRCSuccessReturn(rc2, rc2);
1800	Assert(pShwPde);
1801
1802	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1803	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1804
1805	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1806	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1807	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1808	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1809	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1810
1811	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1812	AssertRCSuccessReturn(rc2, rc2);
1813	Assert(pPDDst && pPdptDst);
1814	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1815	# endif
1816	SHWPDE PdeDst = *pPdeDst;
1817
1818	/*
1819	* - In the guest SMP case we could have blocked while another VCPU reused
1820	* this page table.
1821	* - With W7-64 we may also take this path when the the A bit is cleared on
1822	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1823	* relevant TLB entries. If we're write monitoring any page mapped by
1824	* the modified entry, we may end up here with a "stale" TLB entry.
1825	*/
1826	if (!PdeDst.n.u1Present)
1827	{
1828	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1829	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1830	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1831	if (uErr & X86_TRAP_PF_P)
1832	PGM_INVL_PG(pVCpu, GCPtrPage);
1833	return VINF_SUCCESS; /* force the instruction to be executed again. */
1834	}
1835
1836	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1837	Assert(pShwPage);
1838
1839	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1840	/* Fetch the pgm pool shadow descriptor. */
1841	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1842	Assert(pShwPde);
1843	# endif
1844
1845	/*
1846	* Check that the page is present and that the shadow PDE isn't out of sync.
1847	*/
1848	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1849	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1850	RTGCPHYS GCPhys;
1851	if (!fBigPage)
1852	{
1853	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1854	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1855	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1856	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1857	# endif
1858	}
1859	else
1860	{
1861	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1862	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1863	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1864	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1865	# endif
1866	}
1867	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1868	if ( fPdeValid
1869	&& pShwPage->GCPhys == GCPhys
1870	&& PdeSrc.n.u1Present
1871	&& PdeSrc.n.u1User == PdeDst.n.u1User
1872	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1873	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1874	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1875	# endif
1876	)
1877	{
1878	/*
1879	* Check that the PDE is marked accessed already.
1880	* Since we set the accessed bit before getting here on a #PF, this
1881	* check is only meant for dealing with non-#PF'ing paths.
1882	*/
1883	if (PdeSrc.n.u1Accessed)
1884	{
1885	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1886	if (!fBigPage)
1887	{
1888	/*
1889	* 4KB Page - Map the guest page table.
1890	*/
1891	PGSTPT pPTSrc;
1892	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1893	if (RT_SUCCESS(rc))
1894	{
1895	# ifdef PGM_SYNC_N_PAGES
1896	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1897	if ( cPages > 1
1898	&& !(uErr & X86_TRAP_PF_P)
1899	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1900	{
1901	/*
1902	* This code path is currently only taken when the caller is PGMTrap0eHandler
1903	* for non-present pages!
1904	*
1905	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1906	* deal with locality.
1907	*/
1908	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1909	const unsigned iPTDstPage = iPTDst;
1910	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1911	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1912	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1913	# else
1914	const unsigned offPTSrc = 0;
1915	# endif
1916	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1917	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1918	iPTDst = 0;
1919	else
1920	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1921	for (; iPTDst < iPTDstEnd; iPTDst++)
1922	{
1923	if ( !SHW_PTE_IS_P(pPTDst->a[iPTDst])
1924	\|\| iPTDst == iPTDstPage) /* always sync GCPtrPage */
1925	{
1926	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1927	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1928	NOREF(GCPtrCurPage);
1929	#ifndef IN_RING0
1930	/*
1931	* Assuming kernel code will be marked as supervisor - and not as user level
1932	* and executed using a conforming code selector - And marked as readonly.
1933	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1934	*/
1935	PPGMPAGE pPage;
1936	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1937	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1938	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1939	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1940	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1941	)
1942	#endif /* else: CSAM not active */
1943	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1944	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1945	GCPtrCurPage, PteSrc.n.u1Present,
1946	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1947	PteSrc.n.u1User & PdeSrc.n.u1User,
1948	(uint64_t)PteSrc.u,
1949	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1950	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1951	}
1952	}
1953	}
1954	else
1955	# endif /* PGM_SYNC_N_PAGES */
1956	{
1957	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1958	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1959	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1960	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1961	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1962	GCPtrPage, PteSrc.n.u1Present,
1963	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1964	PteSrc.n.u1User & PdeSrc.n.u1User,
1965	(uint64_t)PteSrc.u,
1966	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1967	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1968	}
1969	}
1970	else /* MMIO or invalid page: emulated in #PF handler. */
1971	{
1972	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1973	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1974	}
1975	}
1976	else
1977	{
1978	/*
1979	* 4/2MB page - lazy syncing shadow 4K pages.
1980	* (There are many causes of getting here, it's no longer only CSAM.)
1981	*/
1982	/* Calculate the GC physical address of this 4KB shadow page. */
1983	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1984	/* Find ram range. */
1985	PPGMPAGE pPage;
1986	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1987	if (RT_SUCCESS(rc))
1988	{
1989	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1990
1991	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1992	/* Try to make the page writable if necessary. */
1993	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1994	&& ( PGM_PAGE_IS_ZERO(pPage)
1995	\|\| ( PdeSrc.n.u1Write
1996	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1997	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1998	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1999	# endif
2000	# ifdef VBOX_WITH_PAGE_SHARING
2001	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2002	# endif
2003	)
2004	)
2005	)
2006	{
2007	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2008	AssertRC(rc);
2009	}
2010	# endif
2011
2012	/*
2013	* Make shadow PTE entry.
2014	*/
2015	SHWPTE PteDst;
2016	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2017	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2018	else
2019	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2020
2021	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2022	if ( SHW_PTE_IS_P(PteDst)
2023	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2024	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2025
2026	/* Make sure only allocated pages are mapped writable. */
2027	if ( SHW_PTE_IS_P_RW(PteDst)
2028	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2029	{
2030	/* Still applies to shared pages. */
2031	Assert(!PGM_PAGE_IS_ZERO(pPage));
2032	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2033	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2034	}
2035
2036	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2037
2038	/*
2039	* If the page is not flagged as dirty and is writable, then make it read-only
2040	* at PD level, so we can set the dirty bit when the page is modified.
2041	*
2042	* ASSUMES that page access handlers are implemented on page table entry level.
2043	* Thus we will first catch the dirty access and set PDE.D and restart. If
2044	* there is an access handler, we'll trap again and let it work on the problem.
2045	*/
2046	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2047	* As for invlpg, it simply frees the whole shadow PT.
2048	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2049	if ( !PdeSrc.b.u1Dirty
2050	&& PdeSrc.b.u1Write)
2051	{
2052	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2053	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2054	PdeDst.n.u1Write = 0;
2055	}
2056	else
2057	{
2058	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2059	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2060	}
2061	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2062	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2063	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2064	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2065	}
2066	else
2067	{
2068	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2069	/** @todo must wipe the shadow page table entry in this
2070	* case. */
2071	}
2072	}
2073	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2074	return VINF_SUCCESS;
2075	}
2076
2077	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2078	}
2079	else if (fPdeValid)
2080	{
2081	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2082	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2083	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2084	}
2085	else
2086	{
2087	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2088	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2089	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2090	}
2091
2092	/*
2093	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2094	* Yea, I'm lazy.
2095	*/
2096	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2097	ASMAtomicWriteSize(pPdeDst, 0);
2098
2099	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2100	PGM_INVL_VCPU_TLBS(pVCpu);
2101	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2102
2103
2104	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2105	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2106	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2107	&& !defined(IN_RC)
2108
2109	# ifdef PGM_SYNC_N_PAGES
2110	/*
2111	* Get the shadow PDE, find the shadow page table in the pool.
2112	*/
2113	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2114	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2115
2116	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2117	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2118
2119	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2120	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2121	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2122	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2123	X86PDEPAE PdeDst;
2124	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2125
2126	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2127	AssertRCSuccessReturn(rc, rc);
2128	Assert(pPDDst && pPdptDst);
2129	PdeDst = pPDDst->a[iPDDst];
2130	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2131	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2132	PEPTPD pPDDst;
2133	EPTPDE PdeDst;
2134
2135	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2136	if (rc != VINF_SUCCESS)
2137	{
2138	AssertRC(rc);
2139	return rc;
2140	}
2141	Assert(pPDDst);
2142	PdeDst = pPDDst->a[iPDDst];
2143	# endif
2144	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2145	if (!PdeDst.n.u1Present)
2146	{
2147	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2148	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2149	return VINF_SUCCESS; /* force the instruction to be executed again. */
2150	}
2151
2152	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2153	if (PdeDst.n.u1Size)
2154	{
2155	Assert(pVM->pgm.s.fNestedPaging);
2156	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2157	return VINF_SUCCESS;
2158	}
2159
2160	/* Mask away the page offset. */
2161	GCPtrPage &= ~((RTGCPTR)0xfff);
2162
2163	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2164	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2165
2166	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2167	if ( cPages > 1
2168	&& !(uErr & X86_TRAP_PF_P)
2169	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2170	{
2171	/*
2172	* This code path is currently only taken when the caller is PGMTrap0eHandler
2173	* for non-present pages!
2174	*
2175	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2176	* deal with locality.
2177	*/
2178	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2179	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2180	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2181	iPTDst = 0;
2182	else
2183	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2184	for (; iPTDst < iPTDstEnd; iPTDst++)
2185	{
2186	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2187	{
2188	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2189	GSTPTE PteSrc;
2190
2191	/* Fake the page table entry */
2192	PteSrc.u = GCPtrCurPage;
2193	PteSrc.n.u1Present = 1;
2194	PteSrc.n.u1Dirty = 1;
2195	PteSrc.n.u1Accessed = 1;
2196	PteSrc.n.u1Write = 1;
2197	PteSrc.n.u1User = 1;
2198
2199	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2200	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2201	GCPtrCurPage, PteSrc.n.u1Present,
2202	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2203	PteSrc.n.u1User & PdeSrc.n.u1User,
2204	(uint64_t)PteSrc.u,
2205	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2206	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2207
2208	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2209	break;
2210	}
2211	else
2212	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2213	}
2214	}
2215	else
2216	# endif /* PGM_SYNC_N_PAGES */
2217	{
2218	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2219	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2220	GSTPTE PteSrc;
2221
2222	/* Fake the page table entry */
2223	PteSrc.u = GCPtrCurPage;
2224	PteSrc.n.u1Present = 1;
2225	PteSrc.n.u1Dirty = 1;
2226	PteSrc.n.u1Accessed = 1;
2227	PteSrc.n.u1Write = 1;
2228	PteSrc.n.u1User = 1;
2229	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2230
2231	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2232	GCPtrPage, PteSrc.n.u1Present,
2233	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2234	PteSrc.n.u1User & PdeSrc.n.u1User,
2235	(uint64_t)PteSrc.u,
2236	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2237	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2238	}
2239	return VINF_SUCCESS;
2240
2241	#else
2242	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2243	return VERR_INTERNAL_ERROR;
2244	#endif
2245	}
2246
2247
2248	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2249
2250	/**
2251	* CheckPageFault helper for returning a page fault indicating a non-present
2252	* (NP) entry in the page translation structures.
2253	*
2254	* @returns VINF_EM_RAW_GUEST_TRAP.
2255	* @param pVCpu The virtual CPU to operate on.
2256	* @param uErr The error code of the shadow fault. Corrections to
2257	* TRPM's copy will be made if necessary.
2258	* @param GCPtrPage For logging.
2259	* @param uPageFaultLevel For logging.
2260	*/
2261	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2262	{
2263	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2264	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2265	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2266	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2267	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2268
2269	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2270	return VINF_EM_RAW_GUEST_TRAP;
2271	}
2272
2273
2274	/**
2275	* CheckPageFault helper for returning a page fault indicating a reserved bit
2276	* (RSVD) error in the page translation structures.
2277	*
2278	* @returns VINF_EM_RAW_GUEST_TRAP.
2279	* @param pVCpu The virtual CPU to operate on.
2280	* @param uErr The error code of the shadow fault. Corrections to
2281	* TRPM's copy will be made if necessary.
2282	* @param GCPtrPage For logging.
2283	* @param uPageFaultLevel For logging.
2284	*/
2285	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2286	{
2287	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2288	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2289	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2290
2291	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2292	return VINF_EM_RAW_GUEST_TRAP;
2293	}
2294
2295
2296	/**
2297	* CheckPageFault helper for returning a page protection fault (P).
2298	*
2299	* @returns VINF_EM_RAW_GUEST_TRAP.
2300	* @param pVCpu The virtual CPU to operate on.
2301	* @param uErr The error code of the shadow fault. Corrections to
2302	* TRPM's copy will be made if necessary.
2303	* @param GCPtrPage For logging.
2304	* @param uPageFaultLevel For logging.
2305	*/
2306	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2307	{
2308	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2309	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2310	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2311	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2312
2313	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2314	return VINF_EM_RAW_GUEST_TRAP;
2315	}
2316
2317
2318	/**
2319	* Handle dirty bit tracking faults.
2320	*
2321	* @returns VBox status code.
2322	* @param pVCpu The VMCPU handle.
2323	* @param uErr Page fault error code.
2324	* @param pPdeSrc Guest page directory entry.
2325	* @param pPdeDst Shadow page directory entry.
2326	* @param GCPtrPage Guest context page address.
2327	*/
2328	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2329	{
2330	PVM pVM = pVCpu->CTX_SUFF(pVM);
2331	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2332
2333	Assert(PGMIsLockOwner(pVM));
2334
2335	/*
2336	* Handle big page.
2337	*/
2338	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2339	{
2340	if ( pPdeDst->n.u1Present
2341	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2342	{
2343	SHWPDE PdeDst = *pPdeDst;
2344
2345	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2346	Assert(pPdeSrc->b.u1Write);
2347
2348	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2349	* fault again and take this path to only invalidate the entry (see below).
2350	*/
2351	PdeDst.n.u1Write = 1;
2352	PdeDst.n.u1Accessed = 1;
2353	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2354	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2355	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2356	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2357	}
2358
2359	# ifdef IN_RING0
2360	/* Check for stale TLB entry; only applies to the SMP guest case. */
2361	if ( pVM->cCpus > 1
2362	&& pPdeDst->n.u1Write
2363	&& pPdeDst->n.u1Accessed)
2364	{
2365	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2366	if (pShwPage)
2367	{
2368	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2369	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2370	if (SHW_PTE_IS_P_RW(*pPteDst))
2371	{
2372	/* Stale TLB entry. */
2373	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2374	PGM_INVL_PG(pVCpu, GCPtrPage);
2375	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2376	}
2377	}
2378	}
2379	# endif /* IN_RING0 */
2380	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2381	}
2382
2383	/*
2384	* Map the guest page table.
2385	*/
2386	PGSTPT pPTSrc;
2387	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2388	if (RT_FAILURE(rc))
2389	{
2390	AssertRC(rc);
2391	return rc;
2392	}
2393
2394	if (pPdeDst->n.u1Present)
2395	{
2396	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2397	const GSTPTE PteSrc = *pPteSrc;
2398
2399	#ifndef IN_RING0
2400	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2401	* Our individual shadow handlers will provide more information and force a fatal exit.
2402	*/
2403	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2404	{
2405	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2406	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2407	}
2408	#endif
2409	/*
2410	* Map shadow page table.
2411	*/
2412	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2413	if (pShwPage)
2414	{
2415	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2416	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2417	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2418	{
2419	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2420	{
2421	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2422	SHWPTE PteDst = *pPteDst;
2423
2424	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2426
2427	Assert(pPteSrc->n.u1Write);
2428
2429	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2430	* entry will not harm; write access will simply fault again and
2431	* take this path to only invalidate the entry.
2432	*/
2433	if (RT_LIKELY(pPage))
2434	{
2435	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2436	{
2437	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2438	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2439	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2440	SHW_PTE_SET_RO(PteDst);
2441	}
2442	else
2443	{
2444	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2445	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2446	{
2447	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2448	AssertRC(rc);
2449	}
2450	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2451	SHW_PTE_SET_RW(PteDst);
2452	else
2453	{
2454	/* Still applies to shared pages. */
2455	Assert(!PGM_PAGE_IS_ZERO(pPage));
2456	SHW_PTE_SET_RO(PteDst);
2457	}
2458	}
2459	}
2460	else
2461	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2462
2463	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2464	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2465	PGM_INVL_PG(pVCpu, GCPtrPage);
2466	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2467	}
2468
2469	# ifdef IN_RING0
2470	/* Check for stale TLB entry; only applies to the SMP guest case. */
2471	if ( pVM->cCpus > 1
2472	&& SHW_PTE_IS_RW(*pPteDst)
2473	&& SHW_PTE_IS_A(*pPteDst))
2474	{
2475	/* Stale TLB entry. */
2476	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2477	PGM_INVL_PG(pVCpu, GCPtrPage);
2478	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2479	}
2480	# endif
2481	}
2482	}
2483	else
2484	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2485	}
2486
2487	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2488	}
2489
2490	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2491
2492
2493	/**
2494	* Sync a shadow page table.
2495	*
2496	* The shadow page table is not present in the shadow PDE.
2497	*
2498	* Handles mapping conflicts.
2499	*
2500	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2501	* conflict), and Trap0eHandler.
2502	*
2503	* A precodition for this method is that the shadow PDE is not present. The
2504	* caller must take the PGM lock before checking this and continue to hold it
2505	* when calling this method.
2506	*
2507	* @returns VBox status code.
2508	* @param pVCpu The VMCPU handle.
2509	* @param iPD Page directory index.
2510	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2511	* Assume this is a temporary mapping.
2512	* @param GCPtrPage GC Pointer of the page that caused the fault
2513	*/
2514	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2515	{
2516	PVM pVM = pVCpu->CTX_SUFF(pVM);
2517	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2518
2519	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2520	#if 0 /* rarely useful; leave for debugging. */
2521	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2522	#endif
2523	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2524
2525	Assert(PGMIsLocked(pVM));
2526
2527	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2528	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2529	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2530	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2531	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2532
2533	int rc = VINF_SUCCESS;
2534
2535	/*
2536	* Some input validation first.
2537	*/
2538	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2539
2540	/*
2541	* Get the relevant shadow PDE entry.
2542	*/
2543	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2544	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2545	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2546
2547	/* Fetch the pgm pool shadow descriptor. */
2548	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2549	Assert(pShwPde);
2550
2551	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2552	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2553	PPGMPOOLPAGE pShwPde = NULL;
2554	PX86PDPAE pPDDst;
2555	PSHWPDE pPdeDst;
2556
2557	/* Fetch the pgm pool shadow descriptor. */
2558	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2559	AssertRCSuccessReturn(rc, rc);
2560	Assert(pShwPde);
2561
2562	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2563	pPdeDst = &pPDDst->a[iPDDst];
2564
2565	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2566	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2567	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2568	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2569	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2570	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2571	AssertRCSuccessReturn(rc, rc);
2572	Assert(pPDDst);
2573	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2574	# endif
2575	SHWPDE PdeDst = *pPdeDst;
2576
2577	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2578	/* Fetch the pgm pool shadow descriptor. */
2579	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2580	Assert(pShwPde);
2581	# endif
2582
2583	# ifndef PGM_WITHOUT_MAPPINGS
2584	/*
2585	* Check for conflicts.
2586	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2587	* R3: Simply resolve the conflict.
2588	*/
2589	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2590	{
2591	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2592	# ifndef IN_RING3
2593	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2594	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2595	return VERR_ADDRESS_CONFLICT;
2596
2597	# else /* IN_RING3 */
2598	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2599	Assert(pMapping);
2600	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2601	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2602	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2603	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2604	# else
2605	AssertFailed(); /* can't happen for amd64 */
2606	# endif
2607	if (RT_FAILURE(rc))
2608	{
2609	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2610	return rc;
2611	}
2612	PdeDst = *pPdeDst;
2613	# endif /* IN_RING3 */
2614	}
2615	# endif /* !PGM_WITHOUT_MAPPINGS */
2616	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2617
2618	/*
2619	* Sync the page directory entry.
2620	*/
2621	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2622	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2623	if ( PdeSrc.n.u1Present
2624	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2625	{
2626	/*
2627	* Allocate & map the page table.
2628	*/
2629	PSHWPT pPTDst;
2630	PPGMPOOLPAGE pShwPage;
2631	RTGCPHYS GCPhys;
2632	if (fPageTable)
2633	{
2634	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2635	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2636	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2637	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2638	# endif
2639	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2640	}
2641	else
2642	{
2643	PGMPOOLACCESS enmAccess;
2644	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2645	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2646	# else
2647	const bool fNoExecute = false;
2648	# endif
2649
2650	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2651	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2652	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2653	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2654	# endif
2655	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2656	if (PdeSrc.n.u1User)
2657	{
2658	if (PdeSrc.n.u1Write)
2659	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2660	else
2661	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2662	}
2663	else
2664	{
2665	if (PdeSrc.n.u1Write)
2666	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2667	else
2668	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2669	}
2670	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2671	&pShwPage);
2672	}
2673	if (rc == VINF_SUCCESS)
2674	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2675	else if (rc == VINF_PGM_CACHED_PAGE)
2676	{
2677	/*
2678	* The PT was cached, just hook it up.
2679	*/
2680	if (fPageTable)
2681	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2682	else
2683	{
2684	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2685	/* (see explanation and assumptions further down.) */
2686	if ( !PdeSrc.b.u1Dirty
2687	&& PdeSrc.b.u1Write)
2688	{
2689	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2690	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2691	PdeDst.b.u1Write = 0;
2692	}
2693	}
2694	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2695	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2696	return VINF_SUCCESS;
2697	}
2698	else if (rc == VERR_PGM_POOL_FLUSHED)
2699	{
2700	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2701	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2702	return VINF_PGM_SYNC_CR3;
2703	}
2704	else
2705	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2706	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2707	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2708	* irrelevant at this point. */
2709	PdeDst.u &= X86_PDE_AVL_MASK;
2710	PdeDst.u \|= pShwPage->Core.Key;
2711
2712	/*
2713	* Page directory has been accessed (this is a fault situation, remember).
2714	*/
2715	/** @todo
2716	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2717	* fault situation. What's more, the Trap0eHandler has already set the
2718	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2719	* might need setting the accessed flag.
2720	*
2721	* The best idea is to leave this change to the caller and add an
2722	* assertion that it's set already. */
2723	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2724	if (fPageTable)
2725	{
2726	/*
2727	* Page table - 4KB.
2728	*
2729	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2730	*/
2731	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2732	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2733	PGSTPT pPTSrc;
2734	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2735	if (RT_SUCCESS(rc))
2736	{
2737	/*
2738	* Start by syncing the page directory entry so CSAM's TLB trick works.
2739	*/
2740	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2741	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2742	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2743	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2744
2745	/*
2746	* Directory/page user or supervisor privilege: (same goes for read/write)
2747	*
2748	* Directory Page Combined
2749	* U/S U/S U/S
2750	* 0 0 0
2751	* 0 1 0
2752	* 1 0 0
2753	* 1 1 1
2754	*
2755	* Simple AND operation. Table listed for completeness.
2756	*
2757	*/
2758	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2759	# ifdef PGM_SYNC_N_PAGES
2760	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2761	unsigned iPTDst = iPTBase;
2762	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2763	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2764	iPTDst = 0;
2765	else
2766	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2767	# else /* !PGM_SYNC_N_PAGES */
2768	unsigned iPTDst = 0;
2769	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2770	# endif /* !PGM_SYNC_N_PAGES */
2771	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2772	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2773	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2774	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2775	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2776	# else
2777	const unsigned offPTSrc = 0;
2778	# endif
2779	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2780	{
2781	const unsigned iPTSrc = iPTDst + offPTSrc;
2782	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2783
2784	if (PteSrc.n.u1Present)
2785	{
2786	# ifndef IN_RING0
2787	/*
2788	* Assuming kernel code will be marked as supervisor - and not as user level
2789	* and executed using a conforming code selector - And marked as readonly.
2790	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2791	*/
2792	PPGMPAGE pPage;
2793	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2794	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2795	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2796	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2797	)
2798	# endif
2799	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2800	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2801	GCPtrCur,
2802	PteSrc.n.u1Present,
2803	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2804	PteSrc.n.u1User & PdeSrc.n.u1User,
2805	(uint64_t)PteSrc.u,
2806	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2807	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2808	}
2809	/* else: the page table was cleared by the pool */
2810	} /* for PTEs */
2811	}
2812	}
2813	else
2814	{
2815	/*
2816	* Big page - 2/4MB.
2817	*
2818	* We'll walk the ram range list in parallel and optimize lookups.
2819	* We will only sync on shadow page table at a time.
2820	*/
2821	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2822
2823	/**
2824	* @todo It might be more efficient to sync only a part of the 4MB
2825	* page (similar to what we do for 4KB PDs).
2826	*/
2827
2828	/*
2829	* Start by syncing the page directory entry.
2830	*/
2831	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2832	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2833
2834	/*
2835	* If the page is not flagged as dirty and is writable, then make it read-only
2836	* at PD level, so we can set the dirty bit when the page is modified.
2837	*
2838	* ASSUMES that page access handlers are implemented on page table entry level.
2839	* Thus we will first catch the dirty access and set PDE.D and restart. If
2840	* there is an access handler, we'll trap again and let it work on the problem.
2841	*/
2842	/** @todo move the above stuff to a section in the PGM documentation. */
2843	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2844	if ( !PdeSrc.b.u1Dirty
2845	&& PdeSrc.b.u1Write)
2846	{
2847	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2848	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2849	PdeDst.b.u1Write = 0;
2850	}
2851	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2852	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2853
2854	/*
2855	* Fill the shadow page table.
2856	*/
2857	/* Get address and flags from the source PDE. */
2858	SHWPTE PteDstBase;
2859	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2860
2861	/* Loop thru the entries in the shadow PT. */
2862	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2863	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2864	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2865	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2866	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2867	unsigned iPTDst = 0;
2868	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2869	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2870	{
2871	/* Advance ram range list. */
2872	while (pRam && GCPhys > pRam->GCPhysLast)
2873	pRam = pRam->CTX_SUFF(pNext);
2874	if (pRam && GCPhys >= pRam->GCPhys)
2875	{
2876	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2877	do
2878	{
2879	/* Make shadow PTE. */
2880	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2881	SHWPTE PteDst;
2882
2883	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2884	/* Try to make the page writable if necessary. */
2885	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2886	&& ( PGM_PAGE_IS_ZERO(pPage)
2887	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2888	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2889	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2890	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2891	# endif
2892	# ifdef VBOX_WITH_PAGE_SHARING
2893	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2894	# endif
2895	&& !PGM_PAGE_IS_BALLOONED(pPage))
2896	)
2897	)
2898	{
2899	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2900	AssertRCReturn(rc, rc);
2901	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2902	break;
2903	}
2904	# endif
2905
2906	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2907	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2908	else if (PGM_PAGE_IS_BALLOONED(pPage))
2909	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2910	# ifndef IN_RING0
2911	/*
2912	* Assuming kernel code will be marked as supervisor and not as user level and executed
2913	* using a conforming code selector. Don't check for readonly, as that implies the whole
2914	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2915	*/
2916	else if ( !PdeSrc.n.u1User
2917	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2918	SHW_PTE_SET(PteDst, 0);
2919	# endif
2920	else
2921	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2922
2923	/* Only map writable pages writable. */
2924	if ( SHW_PTE_IS_P_RW(PteDst)
2925	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2926	{
2927	/* Still applies to shared pages. */
2928	Assert(!PGM_PAGE_IS_ZERO(pPage));
2929	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2930	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2931	}
2932
2933	if (SHW_PTE_IS_P(PteDst))
2934	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2935
2936	/* commit it (not atomic, new table) */
2937	pPTDst->a[iPTDst] = PteDst;
2938	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2939	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2940	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2941
2942	/* advance */
2943	GCPhys += PAGE_SIZE;
2944	iHCPage++;
2945	iPTDst++;
2946	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2947	&& GCPhys <= pRam->GCPhysLast);
2948	}
2949	else if (pRam)
2950	{
2951	Log(("Invalid pages at %RGp\n", GCPhys));
2952	do
2953	{
2954	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2955	GCPhys += PAGE_SIZE;
2956	iPTDst++;
2957	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2958	&& GCPhys < pRam->GCPhys);
2959	}
2960	else
2961	{
2962	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2963	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2964	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2965	}
2966	} /* while more PTEs */
2967	} /* 4KB / 4MB */
2968	}
2969	else
2970	AssertRelease(!PdeDst.n.u1Present);
2971
2972	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2973	if (RT_FAILURE(rc))
2974	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2975	return rc;
2976
2977	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2978	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2979	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2980	&& !defined(IN_RC)
2981
2982	/*
2983	* Validate input a little bit.
2984	*/
2985	int rc = VINF_SUCCESS;
2986	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2987	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2988	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2989
2990	/* Fetch the pgm pool shadow descriptor. */
2991	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2992	Assert(pShwPde);
2993
2994	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2995	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2996	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2997	PX86PDPAE pPDDst;
2998	PSHWPDE pPdeDst;
2999
3000	/* Fetch the pgm pool shadow descriptor. */
3001	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3002	AssertRCSuccessReturn(rc, rc);
3003	Assert(pShwPde);
3004
3005	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3006	pPdeDst = &pPDDst->a[iPDDst];
3007
3008	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3009	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3010	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3011	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3012	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3013	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3014	AssertRCSuccessReturn(rc, rc);
3015	Assert(pPDDst);
3016	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3017
3018	/* Fetch the pgm pool shadow descriptor. */
3019	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3020	Assert(pShwPde);
3021
3022	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3023	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3024	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3025	PEPTPD pPDDst;
3026	PEPTPDPT pPdptDst;
3027
3028	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3029	if (rc != VINF_SUCCESS)
3030	{
3031	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3032	AssertRC(rc);
3033	return rc;
3034	}
3035	Assert(pPDDst);
3036	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3037
3038	/* Fetch the pgm pool shadow descriptor. */
3039	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3040	Assert(pShwPde);
3041	# endif
3042	SHWPDE PdeDst = *pPdeDst;
3043
3044	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3045	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3046
3047	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3048	if (BTH_IS_NP_ACTIVE(pVM))
3049	{
3050	PPGMPAGE pPage;
3051
3052	/* Check if we allocated a big page before for this 2 MB range. */
3053	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3054	if (RT_SUCCESS(rc))
3055	{
3056	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3057
3058	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3059	{
3060	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3061	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3062	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3063	}
3064	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3065	{
3066	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3067	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3068	if (RT_SUCCESS(rc))
3069	{
3070	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3071	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3072	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3073	}
3074	}
3075	else if (PGMIsUsingLargePages(pVM))
3076	{
3077	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3078	if (RT_SUCCESS(rc))
3079	{
3080	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3081	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3082	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3083	}
3084	else
3085	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3086	}
3087
3088	if (HCPhys != NIL_RTHCPHYS)
3089	{
3090	PdeDst.u &= X86_PDE_AVL_MASK;
3091	PdeDst.u \|= HCPhys;
3092	PdeDst.n.u1Present = 1;
3093	PdeDst.n.u1Write = 1;
3094	PdeDst.b.u1Size = 1;
3095	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3096	PdeDst.n.u1Execute = 1;
3097	PdeDst.b.u1IgnorePAT = 1;
3098	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3099	# else
3100	PdeDst.n.u1User = 1;
3101	# endif
3102	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3103
3104	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3105	/* Add a reference to the first page only. */
3106	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3107
3108	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3109	return VINF_SUCCESS;
3110	}
3111	}
3112	}
3113	# endif /* HC_ARCH_BITS == 64 */
3114
3115	GSTPDE PdeSrc;
3116	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3117	PdeSrc.n.u1Present = 1;
3118	PdeSrc.n.u1Write = 1;
3119	PdeSrc.n.u1Accessed = 1;
3120	PdeSrc.n.u1User = 1;
3121
3122	/*
3123	* Allocate & map the page table.
3124	*/
3125	PSHWPT pPTDst;
3126	PPGMPOOLPAGE pShwPage;
3127	RTGCPHYS GCPhys;
3128
3129	/* Virtual address = physical address */
3130	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3131	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3132
3133	if ( rc == VINF_SUCCESS
3134	\|\| rc == VINF_PGM_CACHED_PAGE)
3135	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3136	else
3137	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3138
3139	PdeDst.u &= X86_PDE_AVL_MASK;
3140	PdeDst.u \|= pShwPage->Core.Key;
3141	PdeDst.n.u1Present = 1;
3142	PdeDst.n.u1Write = 1;
3143	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3144	PdeDst.n.u1Execute = 1;
3145	# else
3146	PdeDst.n.u1User = 1;
3147	PdeDst.n.u1Accessed = 1;
3148	# endif
3149	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3150
3151	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3152	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3153	return rc;
3154
3155	#else
3156	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3157	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3158	return VERR_INTERNAL_ERROR;
3159	#endif
3160	}
3161
3162
3163
3164	/**
3165	* Prefetch a page/set of pages.
3166	*
3167	* Typically used to sync commonly used pages before entering raw mode
3168	* after a CR3 reload.
3169	*
3170	* @returns VBox status code.
3171	* @param pVCpu The VMCPU handle.
3172	* @param GCPtrPage Page to invalidate.
3173	*/
3174	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3175	{
3176	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3177	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3178	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3179	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3180	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3181	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3182	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3183
3184	/*
3185	* Check that all Guest levels thru the PDE are present, getting the
3186	* PD and PDE in the processes.
3187	*/
3188	int rc = VINF_SUCCESS;
3189	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3190	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3191	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3192	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3193	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3194	unsigned iPDSrc;
3195	X86PDPE PdpeSrc;
3196	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3197	if (!pPDSrc)
3198	return VINF_SUCCESS; /* not present */
3199	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3200	unsigned iPDSrc;
3201	PX86PML4E pPml4eSrc;
3202	X86PDPE PdpeSrc;
3203	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3204	if (!pPDSrc)
3205	return VINF_SUCCESS; /* not present */
3206	# endif
3207	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3208	# else
3209	PGSTPD pPDSrc = NULL;
3210	const unsigned iPDSrc = 0;
3211	GSTPDE PdeSrc;
3212
3213	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3214	PdeSrc.n.u1Present = 1;
3215	PdeSrc.n.u1Write = 1;
3216	PdeSrc.n.u1Accessed = 1;
3217	PdeSrc.n.u1User = 1;
3218	# endif
3219
3220	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3221	{
3222	PVM pVM = pVCpu->CTX_SUFF(pVM);
3223	pgmLock(pVM);
3224
3225	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3226	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3227	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3228	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3229	PX86PDPAE pPDDst;
3230	X86PDEPAE PdeDst;
3231	# if PGM_GST_TYPE != PGM_TYPE_PAE
3232	X86PDPE PdpeSrc;
3233
3234	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3235	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3236	# endif
3237	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3238	if (rc != VINF_SUCCESS)
3239	{
3240	pgmUnlock(pVM);
3241	AssertRC(rc);
3242	return rc;
3243	}
3244	Assert(pPDDst);
3245	PdeDst = pPDDst->a[iPDDst];
3246
3247	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3248	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3249	PX86PDPAE pPDDst;
3250	X86PDEPAE PdeDst;
3251
3252	# if PGM_GST_TYPE == PGM_TYPE_PROT
3253	/* AMD-V nested paging */
3254	X86PML4E Pml4eSrc;
3255	X86PDPE PdpeSrc;
3256	PX86PML4E pPml4eSrc = &Pml4eSrc;
3257
3258	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3259	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3260	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3261	# endif
3262
3263	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3264	if (rc != VINF_SUCCESS)
3265	{
3266	pgmUnlock(pVM);
3267	AssertRC(rc);
3268	return rc;
3269	}
3270	Assert(pPDDst);
3271	PdeDst = pPDDst->a[iPDDst];
3272	# endif
3273	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3274	{
3275	if (!PdeDst.n.u1Present)
3276	{
3277	/** @todo r=bird: This guy will set the A bit on the PDE,
3278	* probably harmless. */
3279	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3280	}
3281	else
3282	{
3283	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3284	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3285	* makes no sense to prefetch more than one page.
3286	*/
3287	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3288	if (RT_SUCCESS(rc))
3289	rc = VINF_SUCCESS;
3290	}
3291	}
3292	pgmUnlock(pVM);
3293	}
3294	return rc;
3295
3296	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3297	return VINF_SUCCESS; /* ignore */
3298	#else
3299	AssertCompile(0);
3300	#endif
3301	}
3302
3303
3304
3305
3306	/**
3307	* Syncs a page during a PGMVerifyAccess() call.
3308	*
3309	* @returns VBox status code (informational included).
3310	* @param pVCpu The VMCPU handle.
3311	* @param GCPtrPage The address of the page to sync.
3312	* @param fPage The effective guest page flags.
3313	* @param uErr The trap error code.
3314	* @remarks This will normally never be called on invalid guest page
3315	* translation entries.
3316	*/
3317	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3318	{
3319	PVM pVM = pVCpu->CTX_SUFF(pVM);
3320
3321	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3322
3323	Assert(!pVM->pgm.s.fNestedPaging);
3324	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3325	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3326	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3327	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3328	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3329	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3330	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3331
3332	# ifndef IN_RING0
3333	if (!(fPage & X86_PTE_US))
3334	{
3335	/*
3336	* Mark this page as safe.
3337	*/
3338	/** @todo not correct for pages that contain both code and data!! */
3339	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3340	CSAMMarkPage(pVM, GCPtrPage, true);
3341	}
3342	# endif
3343
3344	/*
3345	* Get guest PD and index.
3346	*/
3347	/** @todo Performance: We've done all this a jiffy ago in the
3348	* PGMGstGetPage call. */
3349	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3350	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3351	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3352	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3353
3354	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3355	unsigned iPDSrc = 0;
3356	X86PDPE PdpeSrc;
3357	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3358	if (RT_UNLIKELY(!pPDSrc))
3359	{
3360	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3361	return VINF_EM_RAW_GUEST_TRAP;
3362	}
3363
3364	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3365	unsigned iPDSrc = 0; /* shut up gcc */
3366	PX86PML4E pPml4eSrc = NULL; /* ditto */
3367	X86PDPE PdpeSrc;
3368	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3369	if (RT_UNLIKELY(!pPDSrc))
3370	{
3371	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3372	return VINF_EM_RAW_GUEST_TRAP;
3373	}
3374	# endif
3375
3376	# else /* !PGM_WITH_PAGING */
3377	PGSTPD pPDSrc = NULL;
3378	const unsigned iPDSrc = 0;
3379	# endif /* !PGM_WITH_PAGING */
3380	int rc = VINF_SUCCESS;
3381
3382	pgmLock(pVM);
3383
3384	/*
3385	* First check if the shadow pd is present.
3386	*/
3387	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3388	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3389
3390	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3391	PX86PDEPAE pPdeDst;
3392	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3393	PX86PDPAE pPDDst;
3394	# if PGM_GST_TYPE != PGM_TYPE_PAE
3395	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3396	X86PDPE PdpeSrc;
3397	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3398	# endif
3399	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3400	if (rc != VINF_SUCCESS)
3401	{
3402	pgmUnlock(pVM);
3403	AssertRC(rc);
3404	return rc;
3405	}
3406	Assert(pPDDst);
3407	pPdeDst = &pPDDst->a[iPDDst];
3408
3409	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3410	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3411	PX86PDPAE pPDDst;
3412	PX86PDEPAE pPdeDst;
3413
3414	# if PGM_GST_TYPE == PGM_TYPE_PROT
3415	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3416	X86PML4E Pml4eSrc;
3417	X86PDPE PdpeSrc;
3418	PX86PML4E pPml4eSrc = &Pml4eSrc;
3419	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3420	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3421	# endif
3422
3423	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3424	if (rc != VINF_SUCCESS)
3425	{
3426	pgmUnlock(pVM);
3427	AssertRC(rc);
3428	return rc;
3429	}
3430	Assert(pPDDst);
3431	pPdeDst = &pPDDst->a[iPDDst];
3432	# endif
3433
3434	if (!pPdeDst->n.u1Present)
3435	{
3436	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3437	if (rc != VINF_SUCCESS)
3438	{
3439	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3440	pgmUnlock(pVM);
3441	AssertRC(rc);
3442	return rc;
3443	}
3444	}
3445
3446	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3447	/* Check for dirty bit fault */
3448	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3449	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3450	Log(("PGMVerifyAccess: success (dirty)\n"));
3451	else
3452	# endif
3453	{
3454	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3455	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3456	# else
3457	GSTPDE PdeSrc;
3458	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3459	PdeSrc.n.u1Present = 1;
3460	PdeSrc.n.u1Write = 1;
3461	PdeSrc.n.u1Accessed = 1;
3462	PdeSrc.n.u1User = 1;
3463	# endif
3464
3465	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3466	if (uErr & X86_TRAP_PF_US)
3467	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3468	else /* supervisor */
3469	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3470
3471	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3472	if (RT_SUCCESS(rc))
3473	{
3474	/* Page was successfully synced */
3475	Log2(("PGMVerifyAccess: success (sync)\n"));
3476	rc = VINF_SUCCESS;
3477	}
3478	else
3479	{
3480	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3481	rc = VINF_EM_RAW_GUEST_TRAP;
3482	}
3483	}
3484	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3485	pgmUnlock(pVM);
3486	return rc;
3487
3488	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3489
3490	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3491	return VERR_INTERNAL_ERROR;
3492	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3493	}
3494
3495
3496	/**
3497	* Syncs the paging hierarchy starting at CR3.
3498	*
3499	* @returns VBox status code, no specials.
3500	* @param pVCpu The VMCPU handle.
3501	* @param cr0 Guest context CR0 register
3502	* @param cr3 Guest context CR3 register
3503	* @param cr4 Guest context CR4 register
3504	* @param fGlobal Including global page directories or not
3505	*/
3506	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3507	{
3508	PVM pVM = pVCpu->CTX_SUFF(pVM);
3509
3510	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3511
3512	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3513
3514	pgmLock(pVM);
3515
3516	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3517	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3518	if (pPool->cDirtyPages)
3519	pgmPoolResetDirtyPages(pVM);
3520	# endif
3521
3522	/*
3523	* Update page access handlers.
3524	* The virtual are always flushed, while the physical are only on demand.
3525	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3526	* have to look into that later because it will have a bad influence on the performance.
3527	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3528	* bird: Yes, but that won't work for aliases.
3529	*/
3530	/** @todo this MUST go away. See #1557. */
3531	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3532	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3533	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3534	pgmUnlock(pVM);
3535	#endif /* !NESTED && !EPT */
3536
3537	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3538	/*
3539	* Nested / EPT - almost no work.
3540	*/
3541	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3542	return VINF_SUCCESS;
3543
3544	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3545	/*
3546	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3547	* out the shadow parts when the guest modifies its tables.
3548	*/
3549	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3550	return VINF_SUCCESS;
3551
3552	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3553
3554	# ifndef PGM_WITHOUT_MAPPINGS
3555	/*
3556	* Check for and resolve conflicts with our guest mappings if they
3557	* are enabled and not fixed.
3558	*/
3559	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3560	{
3561	int rc = pgmMapResolveConflicts(pVM);
3562	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3563	if (rc == VINF_PGM_SYNC_CR3)
3564	{
3565	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3566	return VINF_PGM_SYNC_CR3;
3567	}
3568	}
3569	# else
3570	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3571	# endif
3572	return VINF_SUCCESS;
3573	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3574	}
3575
3576
3577
3578
3579	#ifdef VBOX_STRICT
3580	# ifdef IN_RC
3581	# undef AssertMsgFailed
3582	# define AssertMsgFailed Log
3583	# endif
3584
3585	/**
3586	* Checks that the shadow page table is in sync with the guest one.
3587	*
3588	* @returns The number of errors.
3589	* @param pVM The virtual machine.
3590	* @param pVCpu The VMCPU handle.
3591	* @param cr3 Guest context CR3 register
3592	* @param cr4 Guest context CR4 register
3593	* @param GCPtr Where to start. Defaults to 0.
3594	* @param cb How much to check. Defaults to everything.
3595	*/
3596	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3597	{
3598	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3599	return 0;
3600	#else
3601	unsigned cErrors = 0;
3602	PVM pVM = pVCpu->CTX_SUFF(pVM);
3603	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3604
3605	#if PGM_GST_TYPE == PGM_TYPE_PAE
3606	/** @todo currently broken; crashes below somewhere */
3607	AssertFailed();
3608	#endif
3609
3610	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3611	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3612	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3613
3614	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3615	PPGMCPU pPGM = &pVCpu->pgm.s;
3616	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3617	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3618	# ifndef IN_RING0
3619	RTHCPHYS HCPhys; /* general usage. */
3620	# endif
3621	int rc;
3622
3623	/*
3624	* Check that the Guest CR3 and all its mappings are correct.
3625	*/
3626	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3627	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3628	false);
3629	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3630	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3631	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3632	# else
3633	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3634	# endif
3635	AssertRCReturn(rc, 1);
3636	HCPhys = NIL_RTHCPHYS;
3637	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3638	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3639	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3640	pgmGstGet32bitPDPtr(pVCpu);
3641	RTGCPHYS GCPhys;
3642	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3643	AssertRCReturn(rc, 1);
3644	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3645	# endif
3646	# endif /* !IN_RING0 */
3647
3648	/*
3649	* Get and check the Shadow CR3.
3650	*/
3651	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3652	unsigned cPDEs = X86_PG_ENTRIES;
3653	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3654	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3655	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3656	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3657	# else
3658	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3659	# endif
3660	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3661	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3662	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3663	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3664	# endif
3665	if (cb != ~(RTGCPTR)0)
3666	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3667
3668	/** @todo call the other two PGMAssert() functions. /
3669
3670	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3671	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3672
3673	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3674	{
3675	PPGMPOOLPAGE pShwPdpt = NULL;
3676	PX86PML4E pPml4eSrc;
3677	PX86PML4E pPml4eDst;
3678	RTGCPHYS GCPhysPdptSrc;
3679
3680	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3681	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3682
3683	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3684	if (!pPml4eDst->n.u1Present)
3685	{
3686	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3687	continue;
3688	}
3689
3690	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3691	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3692
3693	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3694	{
3695	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3696	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3697	cErrors++;
3698	continue;
3699	}
3700
3701	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3702	{
3703	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3704	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3705	cErrors++;
3706	continue;
3707	}
3708
3709	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3710	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3711	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3712	{
3713	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3714	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3715	cErrors++;
3716	continue;
3717	}
3718	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3719	{
3720	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3721
3722	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3723	/*
3724	* Check the PDPTEs too.
3725	*/
3726	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3727
3728	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3729	{
3730	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3731	PPGMPOOLPAGE pShwPde = NULL;
3732	PX86PDPE pPdpeDst;
3733	RTGCPHYS GCPhysPdeSrc;
3734	# if PGM_GST_TYPE == PGM_TYPE_PAE
3735	X86PDPE PdpeSrc;
3736	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3737	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3738	# else
3739	PX86PML4E pPml4eSrcIgn;
3740	X86PDPE PdpeSrc;
3741	PX86PDPT pPdptDst;
3742	PX86PDPAE pPDDst;
3743	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3744
3745	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3746	if (rc != VINF_SUCCESS)
3747	{
3748	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3749	GCPtr += 512 * _2M;
3750	continue; /* next PDPTE */
3751	}
3752	Assert(pPDDst);
3753	# endif
3754	Assert(iPDSrc == 0);
3755
3756	pPdpeDst = &pPdptDst->a[iPdpt];
3757
3758	if (!pPdpeDst->n.u1Present)
3759	{
3760	GCPtr += 512 * _2M;
3761	continue; /* next PDPTE */
3762	}
3763
3764	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3765	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3766
3767	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3768	{
3769	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3770	GCPtr += 512 * _2M;
3771	cErrors++;
3772	continue;
3773	}
3774
3775	if (GCPhysPdeSrc != pShwPde->GCPhys)
3776	{
3777	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3778	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3779	# else
3780	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3781	# endif
3782	GCPtr += 512 * _2M;
3783	cErrors++;
3784	continue;
3785	}
3786
3787	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3788	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3789	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3790	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3791	{
3792	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3793	GCPtr += 512 * _2M;
3794	cErrors++;
3795	continue;
3796	}
3797	# endif
3798
3799	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3800	{
3801	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3802	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3803	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3804	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3805	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3806	# endif
3807	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3808	/*
3809	* Iterate the shadow page directory.
3810	*/
3811	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3812	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3813
3814	for (;
3815	iPDDst < cPDEs;
3816	iPDDst++, GCPtr += cIncrement)
3817	{
3818	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3819	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3820	# else
3821	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3822	# endif
3823	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3824	{
3825	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3826	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3827	{
3828	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3829	cErrors++;
3830	continue;
3831	}
3832	}
3833	else if ( (PdeDst.u & X86_PDE_P)
3834	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3835	)
3836	{
3837	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3838	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3839	if (!pPoolPage)
3840	{
3841	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3842	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3843	cErrors++;
3844	continue;
3845	}
3846	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3847
3848	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3849	{
3850	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3851	GCPtr, (uint64_t)PdeDst.u));
3852	cErrors++;
3853	}
3854
3855	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3856	{
3857	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3858	GCPtr, (uint64_t)PdeDst.u));
3859	cErrors++;
3860	}
3861
3862	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3863	if (!PdeSrc.n.u1Present)
3864	{
3865	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3866	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3867	cErrors++;
3868	continue;
3869	}
3870
3871	if ( !PdeSrc.b.u1Size
3872	\|\| !fBigPagesSupported)
3873	{
3874	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3875	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3876	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3877	# endif
3878	}
3879	else
3880	{
3881	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3882	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3883	{
3884	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3885	GCPtr, (uint64_t)PdeSrc.u));
3886	cErrors++;
3887	continue;
3888	}
3889	# endif
3890	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3891	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3892	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3893	# endif
3894	}
3895
3896	if ( pPoolPage->enmKind
3897	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3898	{
3899	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3900	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3901	cErrors++;
3902	}
3903
3904	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3905	if (!pPhysPage)
3906	{
3907	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3908	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3909	cErrors++;
3910	continue;
3911	}
3912
3913	if (GCPhysGst != pPoolPage->GCPhys)
3914	{
3915	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3916	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3917	cErrors++;
3918	continue;
3919	}
3920
3921	if ( !PdeSrc.b.u1Size
3922	\|\| !fBigPagesSupported)
3923	{
3924	/*
3925	* Page Table.
3926	*/
3927	const GSTPT *pPTSrc;
3928	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3929	if (RT_FAILURE(rc))
3930	{
3931	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3932	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3933	cErrors++;
3934	continue;
3935	}
3936	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3937	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3938	{
3939	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3940	// (This problem will go away when/if we shadow multiple CR3s.)
3941	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3942	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3943	cErrors++;
3944	continue;
3945	}
3946	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3947	{
3948	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3949	GCPtr, (uint64_t)PdeDst.u));
3950	cErrors++;
3951	continue;
3952	}
3953
3954	/* iterate the page table. */
3955	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3956	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3957	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3958	# else
3959	const unsigned offPTSrc = 0;
3960	# endif
3961	for (unsigned iPT = 0, off = 0;
3962	iPT < RT_ELEMENTS(pPTDst->a);
3963	iPT++, off += PAGE_SIZE)
3964	{
3965	const SHWPTE PteDst = pPTDst->a[iPT];
3966
3967	/* skip not-present and dirty tracked entries. */
3968	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3969	continue;
3970	Assert(SHW_PTE_IS_P(PteDst));
3971
3972	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3973	if (!PteSrc.n.u1Present)
3974	{
3975	# ifdef IN_RING3
3976	PGMAssertHandlerAndFlagsInSync(pVM);
3977	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3978	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3979	0, 0, UINT64_MAX, 99, NULL);
3980	# endif
3981	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3982	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3983	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3984	cErrors++;
3985	continue;
3986	}
3987
3988	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3989	# if 1 /** @todo sync accessed bit properly... */
3990	fIgnoreFlags \|= X86_PTE_A;
3991	# endif
3992
3993	/* match the physical addresses */
3994	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3995	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
3996
3997	# ifdef IN_RING3
3998	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3999	if (RT_FAILURE(rc))
4000	{
4001	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4002	{
4003	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4004	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4005	cErrors++;
4006	continue;
4007	}
4008	}
4009	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4010	{
4011	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4012	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4013	cErrors++;
4014	continue;
4015	}
4016	# endif
4017
4018	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4019	if (!pPhysPage)
4020	{
4021	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4022	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4023	{
4024	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4025	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4026	cErrors++;
4027	continue;
4028	}
4029	# endif
4030	if (SHW_PTE_IS_RW(PteDst))
4031	{
4032	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4033	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4034	cErrors++;
4035	}
4036	fIgnoreFlags \|= X86_PTE_RW;
4037	}
4038	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4039	{
4040	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4041	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4042	cErrors++;
4043	continue;
4044	}
4045
4046	/* flags */
4047	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4048	{
4049	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4050	{
4051	if (SHW_PTE_IS_RW(PteDst))
4052	{
4053	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4054	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4055	cErrors++;
4056	continue;
4057	}
4058	fIgnoreFlags \|= X86_PTE_RW;
4059	}
4060	else
4061	{
4062	if ( SHW_PTE_IS_P(PteDst)
4063	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4064	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4065	# endif
4066	)
4067	{
4068	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4069	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4070	cErrors++;
4071	continue;
4072	}
4073	fIgnoreFlags \|= X86_PTE_P;
4074	}
4075	}
4076	else
4077	{
4078	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4079	{
4080	if (SHW_PTE_IS_RW(PteDst))
4081	{
4082	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4083	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4084	cErrors++;
4085	continue;
4086	}
4087	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4088	{
4089	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4090	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4091	cErrors++;
4092	continue;
4093	}
4094	if (SHW_PTE_IS_D(PteDst))
4095	{
4096	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4097	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4098	cErrors++;
4099	}
4100	# if 0 /** @todo sync access bit properly... */
4101	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4102	{
4103	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4104	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4105	cErrors++;
4106	}
4107	fIgnoreFlags \|= X86_PTE_RW;
4108	# else
4109	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4110	# endif
4111	}
4112	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4113	{
4114	/* access bit emulation (not implemented). */
4115	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4116	{
4117	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4118	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4119	cErrors++;
4120	continue;
4121	}
4122	if (!SHW_PTE_IS_A(PteDst))
4123	{
4124	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4125	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4126	cErrors++;
4127	}
4128	fIgnoreFlags \|= X86_PTE_P;
4129	}
4130	# ifdef DEBUG_sandervl
4131	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4132	# endif
4133	}
4134
4135	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4136	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4137	)
4138	{
4139	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4140	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4141	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4142	cErrors++;
4143	continue;
4144	}
4145	} /* foreach PTE */
4146	}
4147	else
4148	{
4149	/*
4150	* Big Page.
4151	*/
4152	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4153	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4154	{
4155	if (PdeDst.n.u1Write)
4156	{
4157	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4158	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4159	cErrors++;
4160	continue;
4161	}
4162	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4163	{
4164	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4165	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4166	cErrors++;
4167	continue;
4168	}
4169	# if 0 /** @todo sync access bit properly... */
4170	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4171	{
4172	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4173	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4174	cErrors++;
4175	}
4176	fIgnoreFlags \|= X86_PTE_RW;
4177	# else
4178	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4179	# endif
4180	}
4181	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4182	{
4183	/* access bit emulation (not implemented). */
4184	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4185	{
4186	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4187	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4188	cErrors++;
4189	continue;
4190	}
4191	if (!PdeDst.n.u1Accessed)
4192	{
4193	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4194	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4195	cErrors++;
4196	}
4197	fIgnoreFlags \|= X86_PTE_P;
4198	}
4199
4200	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4201	{
4202	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4203	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4204	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4205	cErrors++;
4206	}
4207
4208	/* iterate the page table. */
4209	for (unsigned iPT = 0, off = 0;
4210	iPT < RT_ELEMENTS(pPTDst->a);
4211	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4212	{
4213	const SHWPTE PteDst = pPTDst->a[iPT];
4214
4215	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4216	{
4217	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4218	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4219	cErrors++;
4220	}
4221
4222	/* skip not-present entries. */
4223	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4224	continue;
4225
4226	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4227
4228	/* match the physical addresses */
4229	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4230
4231	# ifdef IN_RING3
4232	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4233	if (RT_FAILURE(rc))
4234	{
4235	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4236	{
4237	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4238	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4239	cErrors++;
4240	}
4241	}
4242	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4243	{
4244	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4245	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4246	cErrors++;
4247	continue;
4248	}
4249	# endif
4250	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4251	if (!pPhysPage)
4252	{
4253	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4254	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4255	{
4256	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4257	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4258	cErrors++;
4259	continue;
4260	}
4261	# endif
4262	if (SHW_PTE_IS_RW(PteDst))
4263	{
4264	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4265	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4266	cErrors++;
4267	}
4268	fIgnoreFlags \|= X86_PTE_RW;
4269	}
4270	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4271	{
4272	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4273	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4274	cErrors++;
4275	continue;
4276	}
4277
4278	/* flags */
4279	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4280	{
4281	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4282	{
4283	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4284	{
4285	if (SHW_PTE_IS_RW(PteDst))
4286	{
4287	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4288	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4289	cErrors++;
4290	continue;
4291	}
4292	fIgnoreFlags \|= X86_PTE_RW;
4293	}
4294	}
4295	else
4296	{
4297	if ( SHW_PTE_IS_P(PteDst)
4298	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4299	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4300	# endif
4301	)
4302	{
4303	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4304	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4305	cErrors++;
4306	continue;
4307	}
4308	fIgnoreFlags \|= X86_PTE_P;
4309	}
4310	}
4311
4312	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4313	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4314	)
4315	{
4316	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4317	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4318	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4319	cErrors++;
4320	continue;
4321	}
4322	} /* for each PTE */
4323	}
4324	}
4325	/* not present */
4326
4327	} /* for each PDE */
4328
4329	} /* for each PDPTE */
4330
4331	} /* for each PML4E */
4332
4333	# ifdef DEBUG
4334	if (cErrors)
4335	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4336	# endif
4337
4338	#endif /* GST == 32BIT, PAE or AMD64 */
4339	return cErrors;
4340
4341	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4342	}
4343	#endif /* VBOX_STRICT */
4344
4345
4346	/**
4347	* Sets up the CR3 for shadow paging
4348	*
4349	* @returns Strict VBox status code.
4350	* @retval VINF_SUCCESS.
4351	*
4352	* @param pVCpu The VMCPU handle.
4353	* @param GCPhysCR3 The physical address in the CR3 register.
4354	*/
4355	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4356	{
4357	PVM pVM = pVCpu->CTX_SUFF(pVM);
4358
4359	/* Update guest paging info. */
4360	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4361	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4362	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4363
4364	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4365
4366	/*
4367	* Map the page CR3 points at.
4368	*/
4369	RTHCPTR HCPtrGuestCR3;
4370	RTHCPHYS HCPhysGuestCR3;
4371	pgmLock(pVM);
4372	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4373	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4374	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4375	/** @todo this needs some reworking wrt. locking? */
4376	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4377	HCPtrGuestCR3 = NIL_RTHCPTR;
4378	int rc = VINF_SUCCESS;
4379	# else
4380	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4381	# endif
4382	pgmUnlock(pVM);
4383	if (RT_SUCCESS(rc))
4384	{
4385	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4386	if (RT_SUCCESS(rc))
4387	{
4388	# ifdef IN_RC
4389	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4390	# endif
4391	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4392	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4393	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4394	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4395	# endif
4396	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4397
4398	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4399	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4400	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4401	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4402	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4403	# endif
4404	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4405	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4406
4407	/*
4408	* Map the 4 PDs too.
4409	*/
4410	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4411	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4412	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4413	{
4414	if (pGuestPDPT->a[i].n.u1Present)
4415	{
4416	RTHCPTR HCPtr;
4417	RTHCPHYS HCPhys;
4418	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4419	pgmLock(pVM);
4420	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4421	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4422	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4423	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4424	HCPtr = NIL_RTHCPTR;
4425	int rc2 = VINF_SUCCESS;
4426	# else
4427	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4428	# endif
4429	pgmUnlock(pVM);
4430	if (RT_SUCCESS(rc2))
4431	{
4432	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4433	AssertRCReturn(rc, rc);
4434
4435	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4436	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4437	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4438	# endif
4439	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4440	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4441	# ifdef IN_RC
4442	PGM_INVL_PG(pVCpu, GCPtr);
4443	# endif
4444	continue;
4445	}
4446	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4447	}
4448
4449	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4450	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4451	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4452	# endif
4453	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4454	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4455	# ifdef IN_RC
4456	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4457	# endif
4458	}
4459
4460	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4461	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4462	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4463	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4464	# endif
4465	# endif
4466	}
4467	else
4468	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4469	}
4470	else
4471	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4472
4473	#else /* prot/real stub */
4474	int rc = VINF_SUCCESS;
4475	#endif
4476
4477	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4478	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4479	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4480	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4481	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4482	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4483
4484	Assert(!pVM->pgm.s.fNestedPaging);
4485
4486	/*
4487	* Update the shadow root page as well since that's not fixed.
4488	*/
4489	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4490	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4491	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4492	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4493	PPGMPOOLPAGE pNewShwPageCR3;
4494
4495	pgmLock(pVM);
4496
4497	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4498	if (pPool->cDirtyPages)
4499	pgmPoolResetDirtyPages(pVM);
4500	# endif
4501
4502	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4503	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4504	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4505	AssertFatalRC(rc);
4506	rc = VINF_SUCCESS;
4507
4508	# ifdef IN_RC
4509	/*
4510	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4511	* state will be inconsistent! Flush important things now while
4512	* we still can and then make sure there are no ring-3 calls.
4513	*/
4514	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4515	VMMRZCallRing3Disable(pVCpu);
4516	# endif
4517
4518	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4519	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4520	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4521	# ifdef IN_RING0
4522	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4523	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4524	# elif defined(IN_RC)
4525	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4526	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4527	# else
4528	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4529	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4530	# endif
4531
4532	# ifndef PGM_WITHOUT_MAPPINGS
4533	/*
4534	* Apply all hypervisor mappings to the new CR3.
4535	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4536	* make sure we check for conflicts in the new CR3 root.
4537	*/
4538	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4539	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4540	# endif
4541	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4542	AssertRCReturn(rc, rc);
4543	# endif
4544
4545	/* Set the current hypervisor CR3. */
4546	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4547	SELMShadowCR3Changed(pVM, pVCpu);
4548
4549	# ifdef IN_RC
4550	/* NOTE: The state is consistent again. */
4551	VMMRZCallRing3Enable(pVCpu);
4552	# endif
4553
4554	/* Clean up the old CR3 root. */
4555	if ( pOldShwPageCR3
4556	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4557	{
4558	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4559	# ifndef PGM_WITHOUT_MAPPINGS
4560	/* Remove the hypervisor mappings from the shadow page table. */
4561	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4562	# endif
4563	/* Mark the page as unlocked; allow flushing again. */
4564	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4565
4566	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4567	}
4568	pgmUnlock(pVM);
4569	# endif
4570
4571	return rc;
4572	}
4573
4574	/**
4575	* Unmaps the shadow CR3.
4576	*
4577	* @returns VBox status, no specials.
4578	* @param pVCpu The VMCPU handle.
4579	*/
4580	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4581	{
4582	LogFlow(("UnmapCR3\n"));
4583
4584	int rc = VINF_SUCCESS;
4585	PVM pVM = pVCpu->CTX_SUFF(pVM);
4586
4587	/*
4588	* Update guest paging info.
4589	*/
4590	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4591	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4592	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4593	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4594	# endif
4595	pVCpu->pgm.s.pGst32BitPdRC = 0;
4596
4597	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4598	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4599	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4600	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4601	# endif
4602	pVCpu->pgm.s.pGstPaePdptRC = 0;
4603	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4604	{
4605	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4606	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4607	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4608	# endif
4609	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4610	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4611	}
4612
4613	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4614	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4615	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4616	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4617	# endif
4618
4619	#else /* prot/real mode stub */
4620	/* nothing to do */
4621	#endif
4622
4623	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4624	/*
4625	* Update shadow paging info.
4626	*/
4627	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4628	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4629	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4630
4631	# if PGM_GST_TYPE != PGM_TYPE_REAL
4632	Assert(!pVM->pgm.s.fNestedPaging);
4633	# endif
4634
4635	pgmLock(pVM);
4636
4637	# ifndef PGM_WITHOUT_MAPPINGS
4638	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4639	/* Remove the hypervisor mappings from the shadow page table. */
4640	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4641	# endif
4642
4643	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4644	{
4645	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4646
4647	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4648
4649	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4650	if (pPool->cDirtyPages)
4651	pgmPoolResetDirtyPages(pVM);
4652	# endif
4653
4654	/* Mark the page as unlocked; allow flushing again. */
4655	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4656
4657	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4658	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4659	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4660	pVCpu->pgm.s.pShwPageCR3RC = 0;
4661	pVCpu->pgm.s.iShwUser = 0;
4662	pVCpu->pgm.s.iShwUserTable = 0;
4663	}
4664	pgmUnlock(pVM);
4665	# endif
4666	#endif /* !IN_RC*/
4667
4668	return rc;
4669	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 32384

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