PGMAllBth.h@ 32410

Last change on this file since 32410 was 32410, checked in by vboxsync, 14 years ago
Got rid of unnecessary dirty page flush in InvalidatePage. (NOTE: high risk change)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 200.2 KB

Line
1	/* $Id: PGMAllBth.h 32410 2010-09-10 14:19:33Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	PGM_INVL_PG(pVCpu, pvFault);
561	return rc; /* Restart with the corrected entry. */
562	}
563	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
564
565	/*
566	* Fetch the guest PDE, PDPE and PML4E.
567	*/
568	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
569	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
570	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
571
572	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
573	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
574	PX86PDPAE pPDDst;
575	# if PGM_GST_TYPE == PGM_TYPE_PAE
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
577	# else
578	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
579	# endif
580	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
583	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
586	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
587	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
588	# else
589	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
590	# endif
591	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
592
593	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
594	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
595	PEPTPD pPDDst;
596	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
597	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
598	# endif
599	Assert(pPDDst);
600
601	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
602	/*
603	* Dirty page handling.
604	*
605	* If we successfully correct the write protection fault due to dirty bit
606	* tracking, then return immediately.
607	*/
608	if (uErr & X86_TRAP_PF_RW) /* write fault? */
609	{
610	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
612	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
613	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
614	{
615	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
616	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
617	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
618	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
619	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
620	return VINF_SUCCESS;
621	}
622	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
623	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
624	}
625
626	# if 0 /* rarely useful; leave for debugging. */
627	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
628	# endif
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630
631	/*
632	* A common case is the not-present error caused by lazy page table syncing.
633	*
634	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
635	* here so we can safely assume that the shadow PT is present when calling
636	* SyncPage later.
637	*
638	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
639	* of mapping conflict and defer to SyncCR3 in R3.
640	* (Again, we do NOT support access handlers for non-present guest pages.)
641	*
642	*/
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
644	Assert(GstWalk.Pde.n.u1Present);
645	# endif
646	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
647	&& !pPDDst->a[iPDDst].n.u1Present)
648	{
649	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
650	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
651	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
652	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
653	# else
654	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
655	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
656	# endif
657	if (RT_SUCCESS(rc))
658	return rc;
659	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
660	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
661	return VINF_PGM_SYNC_CR3;
662	}
663
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
665	/*
666	* Check if this address is within any of our mappings.
667	*
668	* This is very fast and it's gonna save us a bit of effort below and prevent
669	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
670	* (BTW, it's impossible to have physical access handlers in a mapping.)
671	*/
672	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
673	{
674	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
675	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
676	{
677	if (pvFault < pMapping->GCPtr)
678	break;
679	if (pvFault - pMapping->GCPtr < pMapping->cb)
680	{
681	/*
682	* The first thing we check is if we've got an undetected conflict.
683	*/
684	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
685	{
686	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
687	while (iPT-- > 0)
688	if (GstWalk.pPde[iPT].n.u1Present)
689	{
690	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
691	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
692	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
693	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
694	return VINF_PGM_SYNC_CR3;
695	}
696	}
697
698	/*
699	* Check if the fault address is in a virtual page access handler range.
700	*/
701	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
702	if ( pCur
703	&& pvFault - pCur->Core.Key < pCur->cb
704	&& uErr & X86_TRAP_PF_RW)
705	{
706	# ifdef IN_RC
707	STAM_PROFILE_START(&pCur->Stat, h);
708	pgmUnlock(pVM);
709	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
710	pgmLock(pVM);
711	STAM_PROFILE_STOP(&pCur->Stat, h);
712	# else
713	AssertFailed();
714	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
715	# endif
716	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
717	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
718	return rc;
719	}
720
721	/*
722	* Pretend we're not here and let the guest handle the trap.
723	*/
724	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
725	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
726	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return VINF_EM_RAW_GUEST_TRAP;
729	}
730	}
731	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
732	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
733
734	/*
735	* Check if this fault address is flagged for special treatment,
736	* which means we'll have to figure out the physical address and
737	* check flags associated with it.
738	*
739	* ASSUME that we can limit any special access handling to pages
740	* in page tables which the guest believes to be present.
741	*/
742	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
743	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# else
745	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
746	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
747	PPGMPAGE pPage;
748	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
749	if (RT_FAILURE(rc))
750	{
751	/*
752	* When the guest accesses invalid physical memory (e.g. probing
753	* of RAM or accessing a remapped MMIO range), then we'll fall
754	* back to the recompiler to emulate the instruction.
755	*/
756	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
757	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
758	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
759	return VINF_EM_RAW_EMULATE_INSTR;
760	}
761
762	/*
763	* Any handlers for this page?
764	*/
765	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
766	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
767	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
768	&GstWalk));
769	# else
770	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
771	# endif
772
773	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
774
775	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
776	if (uErr & X86_TRAP_PF_P)
777	{
778	/*
779	* The page isn't marked, but it might still be monitored by a virtual page access handler.
780	* (ASSUMES no temporary disabling of virtual handlers.)
781	*/
782	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
783	* we should correct both the shadow page table and physical memory flags, and not only check for
784	* accesses within the handler region but for access to pages with virtual handlers. */
785	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
786	if (pCur)
787	{
788	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
789	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
790	\|\| !(uErr & X86_TRAP_PF_P)
791	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
792	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
793
794	if ( pvFault - pCur->Core.Key < pCur->cb
795	&& ( uErr & X86_TRAP_PF_RW
796	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
797	{
798	# ifdef IN_RC
799	STAM_PROFILE_START(&pCur->Stat, h);
800	pgmUnlock(pVM);
801	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
802	pgmLock(pVM);
803	STAM_PROFILE_STOP(&pCur->Stat, h);
804	# else
805	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
806	# endif
807	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
808	return rc;
809	}
810	}
811	}
812	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
813
814	/*
815	* We are here only if page is present in Guest page tables and
816	* trap is not handled by our handlers.
817	*
818	* Check it for page out-of-sync situation.
819	*/
820	if (!(uErr & X86_TRAP_PF_P))
821	{
822	/*
823	* Page is not present in our page tables. Try to sync it!
824	*/
825	if (uErr & X86_TRAP_PF_US)
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
827	else /* supervisor */
828	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
829
830	if (PGM_PAGE_IS_BALLOONED(pPage))
831	{
832	/* Emulate reads from ballooned pages as they are not present in
833	our shadow page tables. (Required for e.g. Solaris guests; soft
834	ecc, random nr generator.) */
835	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
836	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
838	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
839	return rc;
840	}
841
842	# if defined(LOG_ENABLED) && !defined(IN_RING0)
843	RTGCPHYS GCPhys2;
844	uint64_t fPageGst2;
845	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
846	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
847	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
848	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
849	# else
850	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
851	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
852	# endif
853	# endif /* LOG_ENABLED */
854
855	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
856	if ( !GstWalk.Core.fEffectiveUS
857	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
858	{
859	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
860	if ( pvFault == (RTGCPTR)pRegFrame->eip
861	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
862	# ifdef CSAM_DETECT_NEW_CODE_PAGES
863	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
864	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
865	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
866	)
867	{
868	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
869	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
870	if (rc != VINF_SUCCESS)
871	{
872	/*
873	* CSAM needs to perform a job in ring 3.
874	*
875	* Sync the page before going to the host context; otherwise we'll end up in a loop if
876	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
877	*/
878	LogFlow(("CSAM ring 3 job\n"));
879	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
880	AssertRC(rc2);
881
882	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
883	return rc;
884	}
885	}
886	# ifdef CSAM_DETECT_NEW_CODE_PAGES
887	else if ( uErr == X86_TRAP_PF_RW
888	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
889	&& pRegFrame->ecx < 0x10000)
890	{
891	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
892	* to detect loading of new code pages.
893	*/
894
895	/*
896	* Decode the instruction.
897	*/
898	RTGCPTR PC;
899	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
900	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
901	if (rc == VINF_SUCCESS)
902	{
903	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
904	uint32_t cbOp;
905	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
906
907	/* For now we'll restrict this to rep movsw/d instructions */
908	if ( rc == VINF_SUCCESS
909	&& pDis->pCurInstr->opcode == OP_MOVSWD
910	&& (pDis->prefix & PREFIX_REP))
911	{
912	CSAMMarkPossibleCodePage(pVM, pvFault);
913	}
914	}
915	}
916	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
917
918	/*
919	* Mark this page as safe.
920	*/
921	/** @todo not correct for pages that contain both code and data!! */
922	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
923	CSAMMarkPage(pVM, pvFault, true);
924	}
925	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
926	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# else
929	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
930	# endif
931	if (RT_SUCCESS(rc))
932	{
933	/* The page was successfully synced, return to the guest. */
934	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
935	return VINF_SUCCESS;
936	}
937	}
938	else /* uErr & X86_TRAP_PF_P: */
939	{
940	/*
941	* Write protected pages are made writable when the guest makes the
942	* first write to it. This happens for pages that are shared, write
943	* monitored or not yet allocated.
944	*
945	* We may also end up here when CR0.WP=0 in the guest.
946	*
947	* Also, a side effect of not flushing global PDEs are out of sync
948	* pages due to physical monitored regions, that are no longer valid.
949	* Assume for now it only applies to the read/write flag.
950	*/
951	if (uErr & X86_TRAP_PF_RW)
952	{
953	/*
954	* Check if it is a read-only page.
955	*/
956	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
957	{
958	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
959	Assert(!PGM_PAGE_IS_ZERO(pPage));
960	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
961	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
962
963	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
964	if (rc != VINF_SUCCESS)
965	{
966	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
967	return rc;
968	}
969	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
970	return VINF_EM_NO_MEMORY;
971	}
972
973	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
974	/*
975	* Check to see if we need to emulate the instruction if CR0.WP=0.
976	*/
977	if ( !GstWalk.Core.fEffectiveRW
978	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
979	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
980	{
981	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
982	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
983	if (RT_SUCCESS(rc))
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
985	else
986	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
987	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
988	return rc;
989	}
990	# endif
991	/// @todo count the above case; else
992	if (uErr & X86_TRAP_PF_US)
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
994	else /* supervisor */
995	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
996
997	/*
998	* Sync the page.
999	*
1000	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1001	* page is not present, which is not true in this case.
1002	*/
1003	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1005	# else
1006	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1007	# endif
1008	if (RT_SUCCESS(rc))
1009	{
1010	/*
1011	* Page was successfully synced, return to guest but invalidate
1012	* the TLB first as the page is very likely to be in it.
1013	*/
1014	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1015	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1016	# else
1017	PGM_INVL_PG(pVCpu, pvFault);
1018	# endif
1019	# ifdef VBOX_STRICT
1020	RTGCPHYS GCPhys2;
1021	uint64_t fPageGst;
1022	if (!pVM->pgm.s.fNestedPaging)
1023	{
1024	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1025	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1026	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1027	}
1028	uint64_t fPageShw;
1029	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1030	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1031	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1032	# endif /* VBOX_STRICT */
1033	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1034	return VINF_SUCCESS;
1035	}
1036	}
1037	/** @todo else: why are we here? */
1038
1039	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1040	/*
1041	* Check for VMM page flags vs. Guest page flags consistency.
1042	* Currently only for debug purposes.
1043	*/
1044	if (RT_SUCCESS(rc))
1045	{
1046	/* Get guest page flags. */
1047	uint64_t fPageGst;
1048	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1049	if (RT_SUCCESS(rc))
1050	{
1051	uint64_t fPageShw;
1052	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1053
1054	/*
1055	* Compare page flags.
1056	* Note: we have AVL, A, D bits desynched.
1057	*/
1058	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1059	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1060	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1061	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1062	}
1063	else
1064	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1065	}
1066	else
1067	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1068	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1069	}
1070
1071
1072	/*
1073	* If we get here it is because something failed above, i.e. most like guru
1074	* meditiation time.
1075	*/
1076	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1077	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1078	return rc;
1079
1080	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1081	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1082	return VERR_INTERNAL_ERROR;
1083	# endif
1084	}
1085	#endif /* !IN_RING3 */
1086
1087
1088	/**
1089	* Emulation of the invlpg instruction.
1090	*
1091	*
1092	* @returns VBox status code.
1093	*
1094	* @param pVCpu The VMCPU handle.
1095	* @param GCPtrPage Page to invalidate.
1096	*
1097	* @remark ASSUMES that the guest is updating before invalidating. This order
1098	* isn't required by the CPU, so this is speculative and could cause
1099	* trouble.
1100	* @remark No TLB shootdown is done on any other VCPU as we assume that
1101	* invlpg emulation is the only reason for calling this function.
1102	* (The guest has to shoot down TLB entries on other CPUs itself)
1103	* Currently true, but keep in mind!
1104	*
1105	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1106	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1107	*/
1108	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1109	{
1110	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1111	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1112	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1113	int rc;
1114	PVM pVM = pVCpu->CTX_SUFF(pVM);
1115	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1116
1117	Assert(PGMIsLockOwner(pVM));
1118
1119	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1120
1121	/*
1122	* Get the shadow PD entry and skip out if this PD isn't present.
1123	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1124	*/
1125	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1126	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1127	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1128
1129	/* Fetch the pgm pool shadow descriptor. */
1130	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1131	Assert(pShwPde);
1132
1133	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1134	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1135	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1136
1137	/* If the shadow PDPE isn't present, then skip the invalidate. */
1138	if (!pPdptDst->a[iPdpt].n.u1Present)
1139	{
1140	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1141	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1142	return VINF_SUCCESS;
1143	}
1144
1145	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1146	PPGMPOOLPAGE pShwPde = NULL;
1147	PX86PDPAE pPDDst;
1148
1149	/* Fetch the pgm pool shadow descriptor. */
1150	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1151	AssertRCSuccessReturn(rc, rc);
1152	Assert(pShwPde);
1153
1154	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1155	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1156
1157	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1158	/* PML4 */
1159	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1160	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1161	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1162	PX86PDPAE pPDDst;
1163	PX86PDPT pPdptDst;
1164	PX86PML4E pPml4eDst;
1165	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1166	if (rc != VINF_SUCCESS)
1167	{
1168	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1169	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1170	return VINF_SUCCESS;
1171	}
1172	Assert(pPDDst);
1173
1174	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1175	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1176
1177	if (!pPdpeDst->n.u1Present)
1178	{
1179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1180	return VINF_SUCCESS;
1181	}
1182
1183	/* Fetch the pgm pool shadow descriptor. */
1184	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1185	Assert(pShwPde);
1186
1187	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1188
1189	const SHWPDE PdeDst = *pPdeDst;
1190	if (!PdeDst.n.u1Present)
1191	{
1192	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1193	return VINF_SUCCESS;
1194	}
1195
1196	/*
1197	* Get the guest PD entry and calc big page.
1198	*/
1199	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1200	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1201	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1202	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1203	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1204	unsigned iPDSrc = 0;
1205	# if PGM_GST_TYPE == PGM_TYPE_PAE
1206	X86PDPE PdpeSrcIgn;
1207	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1208	# else /* AMD64 */
1209	PX86PML4E pPml4eSrcIgn;
1210	X86PDPE PdpeSrcIgn;
1211	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1212	# endif
1213	GSTPDE PdeSrc;
1214
1215	if (pPDSrc)
1216	PdeSrc = pPDSrc->a[iPDSrc];
1217	else
1218	PdeSrc.u = 0;
1219	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1220	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1221
1222	# ifdef IN_RING3
1223	/*
1224	* If a CR3 Sync is pending we may ignore the invalidate page operation
1225	* depending on the kind of sync and if it's a global page or not.
1226	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1227	*/
1228	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1229	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1230	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1231	&& fIsBigPage
1232	&& PdeSrc.b.u1Global
1233	)
1234	)
1235	# else
1236	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1237	# endif
1238	{
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1240	return VINF_SUCCESS;
1241	}
1242	# endif /* IN_RING3 */
1243
1244	/*
1245	* Deal with the Guest PDE.
1246	*/
1247	rc = VINF_SUCCESS;
1248	if (PdeSrc.n.u1Present)
1249	{
1250	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1251	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1252	# ifndef PGM_WITHOUT_MAPPING
1253	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1254	{
1255	/*
1256	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1257	*/
1258	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1259	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1260	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1261	}
1262	else
1263	# endif /* !PGM_WITHOUT_MAPPING */
1264	if (!fIsBigPage)
1265	{
1266	/*
1267	* 4KB - page.
1268	*/
1269	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1270	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1271
1272	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
1273	/* Reset the modification counter (OpenSolaris trashes tlb entries very often) */
1274	if ( !pShwPage->fDirty
1275	&& pShwPage->cModifications)
1276	pShwPage->cModifications = 1;
1277	# endif
1278
1279	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1280	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1281	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1282	# endif
1283	if (pShwPage->GCPhys == GCPhys)
1284	{
1285	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1286	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1287	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1288	if (pPT->a[iPTEDst].n.u1Present)
1289	{
1290	/* This is very unlikely with caching/monitoring enabled. */
1291	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1292	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1293	}
1294	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1295	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1296	if (RT_SUCCESS(rc))
1297	rc = VINF_SUCCESS;
1298	# endif
1299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1300	PGM_INVL_PG(pVCpu, GCPtrPage);
1301	}
1302	else
1303	{
1304	/*
1305	* The page table address changed.
1306	*/
1307	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1308	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1309	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1310	ASMAtomicWriteSize(pPdeDst, 0);
1311	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1312	PGM_INVL_VCPU_TLBS(pVCpu);
1313	}
1314	}
1315	else
1316	{
1317	/*
1318	* 2/4MB - page.
1319	*/
1320	/* Before freeing the page, check if anything really changed. */
1321	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1322	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1323	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1324	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1325	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1326	# endif
1327	if ( pShwPage->GCPhys == GCPhys
1328	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1329	{
1330	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1331	/** @todo This test is wrong as it cannot check the G bit!
1332	* FIXME */
1333	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1334	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1335	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1336	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1337	{
1338	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1340	return VINF_SUCCESS;
1341	}
1342	}
1343
1344	/*
1345	* Ok, the page table is present and it's been changed in the guest.
1346	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1347	* We could do this for some flushes in GC too, but we need an algorithm for
1348	* deciding which 4MB pages containing code likely to be executed very soon.
1349	*/
1350	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1351	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1352	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1353	ASMAtomicWriteSize(pPdeDst, 0);
1354	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1355	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1356	}
1357	}
1358	else
1359	{
1360	/*
1361	* Page directory is not present, mark shadow PDE not present.
1362	*/
1363	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1364	{
1365	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1366	ASMAtomicWriteSize(pPdeDst, 0);
1367	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1368	PGM_INVL_PG(pVCpu, GCPtrPage);
1369	}
1370	else
1371	{
1372	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1373	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1374	}
1375	}
1376	return rc;
1377
1378	#else /* guest real and protected mode */
1379	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1380	return VINF_SUCCESS;
1381	#endif
1382	}
1383
1384
1385	/**
1386	* Update the tracking of shadowed pages.
1387	*
1388	* @param pVCpu The VMCPU handle.
1389	* @param pShwPage The shadow page.
1390	* @param HCPhys The physical page we is being dereferenced.
1391	* @param iPte Shadow PTE index
1392	*/
1393	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte)
1394	{
1395	PVM pVM = pVCpu->CTX_SUFF(pVM);
1396
1397	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1398	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1399
1400	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1401	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1402	* 2. write protect all shadowed pages. I.e. implement caching.
1403	*/
1404	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1405
1406	/*
1407	* Find the guest address.
1408	*/
1409	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1410	pRam;
1411	pRam = pRam->CTX_SUFF(pNext))
1412	{
1413	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1414	while (iPage-- > 0)
1415	{
1416	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1417	{
1418	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1419
1420	Assert(pShwPage->cPresent);
1421	Assert(pPool->cPresent);
1422	pShwPage->cPresent--;
1423	pPool->cPresent--;
1424
1425	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1426	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1427	return;
1428	}
1429	}
1430	}
1431
1432	for (;;)
1433	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1434	}
1435
1436
1437	/**
1438	* Update the tracking of shadowed pages.
1439	*
1440	* @param pVCpu The VMCPU handle.
1441	* @param pShwPage The shadow page.
1442	* @param u16 The top 16-bit of the pPage->HCPhys.
1443	* @param pPage Pointer to the guest page. this will be modified.
1444	* @param iPTDst The index into the shadow table.
1445	*/
1446	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1447	{
1448	PVM pVM = pVCpu->CTX_SUFF(pVM);
1449
1450	/*
1451	* Just deal with the simple first time here.
1452	*/
1453	if (!u16)
1454	{
1455	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1456	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1457	/* Save the page table index. */
1458	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1459	}
1460	else
1461	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1462
1463	/* write back */
1464	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1465	PGM_PAGE_SET_TRACKING(pPage, u16);
1466
1467	/* update statistics. */
1468	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1469	pShwPage->cPresent++;
1470	if (pShwPage->iFirstPresent > iPTDst)
1471	pShwPage->iFirstPresent = iPTDst;
1472	}
1473
1474
1475	/**
1476	* Modifies a shadow PTE to account for access handlers.
1477	*
1478	* @param pVM The VM handle.
1479	* @param pPage The page in question.
1480	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1481	* A (accessed) bit so it can be emulated correctly.
1482	* @param pPteDst The shadow PTE (output). This is temporary storage and
1483	* does not need to be set atomically.
1484	*/
1485	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1486	{
1487	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1488	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1489	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1490	{
1491	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1492	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1493	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1494	pPteDst->n.u1Present = 1;
1495	pPteDst->n.u1Execute = 1;
1496	pPteDst->n.u1IgnorePAT = 1;
1497	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1498	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1499	#else
1500	if (fPteSrc & X86_PTE_A)
1501	{
1502	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1503	SHW_PTE_SET_RO(*pPteDst);
1504	}
1505	else
1506	SHW_PTE_SET(*pPteDst, 0);
1507	#endif
1508	}
1509	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1510	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1511	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1512	&& ( BTH_IS_NP_ACTIVE(pVM)
1513	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1514	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1515	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1516	# endif
1517	)
1518	{
1519	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1520	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1521	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1522	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1523	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1524	pPteDst->n.u1Present = 0;
1525	pPteDst->n.u1Write = 1;
1526	pPteDst->n.u1Execute = 0;
1527	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1528	pPteDst->n.u3EMT = 7;
1529	# else
1530	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1531	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1532	# endif
1533	}
1534	# endif
1535	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1536	else
1537	{
1538	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1539	SHW_PTE_SET(*pPteDst, 0);
1540	}
1541	/** @todo count these kinds of entries. */
1542	}
1543
1544
1545	/**
1546	* Creates a 4K shadow page for a guest page.
1547	*
1548	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1549	* physical address. The PdeSrc argument only the flags are used. No page
1550	* structured will be mapped in this function.
1551	*
1552	* @param pVCpu The VMCPU handle.
1553	* @param pPteDst Destination page table entry.
1554	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1555	* Can safely assume that only the flags are being used.
1556	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1557	* @param pShwPage Pointer to the shadow page.
1558	* @param iPTDst The index into the shadow table.
1559	*
1560	* @remark Not used for 2/4MB pages!
1561	*/
1562	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1563	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1564	{
1565	PVM pVM = pVCpu->CTX_SUFF(pVM);
1566
1567	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1568	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1569	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1570	if (pShwPage->fDirty)
1571	{
1572	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1573	PGSTPT pGstPT;
1574
1575	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirty].aPage[0];
1576	pGstPT->a[iPTDst].u = PteSrc.u;
1577	}
1578	# else
1579	Assert(!pShwPage->fDirty);
1580	# endif
1581
1582	if ( PteSrc.n.u1Present
1583	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1584	{
1585	/*
1586	* Find the ram range.
1587	*/
1588	PPGMPAGE pPage;
1589	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc), &pPage);
1590	if (RT_SUCCESS(rc))
1591	{
1592	/* Ignore ballooned pages.
1593	Don't return errors or use a fatal assert here as part of a
1594	shadow sync range might included ballooned pages. */
1595	if (PGM_PAGE_IS_BALLOONED(pPage))
1596	{
1597	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1598	return;
1599	}
1600
1601	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1602	/* Make the page writable if necessary. */
1603	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1604	&& ( PGM_PAGE_IS_ZERO(pPage)
1605	\|\| ( PteSrc.n.u1Write
1606	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1607	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1608	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1609	# endif
1610	# ifdef VBOX_WITH_PAGE_SHARING
1611	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1612	# endif
1613	)
1614	)
1615	)
1616	{
1617	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
1618	AssertRC(rc);
1619	}
1620	#endif
1621
1622	/*
1623	* Make page table entry.
1624	*/
1625	SHWPTE PteDst;
1626	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1627	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc), &PteDst);
1628	else
1629	{
1630	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1631	/*
1632	* If the page or page directory entry is not marked accessed,
1633	* we mark the page not present.
1634	*/
1635	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1636	{
1637	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1638	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1639	SHW_PTE_SET(PteDst, 0);
1640	}
1641	/*
1642	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1643	* when the page is modified.
1644	*/
1645	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1646	{
1647	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1648	SHW_PTE_SET(PteDst,
1649	GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc)
1650	\| PGM_PAGE_GET_HCPHYS(pPage)
1651	\| PGM_PTFLAGS_TRACK_DIRTY);
1652	SHW_PTE_SET_RO(PteDst);
1653	}
1654	else
1655	#endif
1656	{
1657	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1658	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1659	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1660	PteDst.n.u1Present = 1;
1661	PteDst.n.u1Write = 1;
1662	PteDst.n.u1Execute = 1;
1663	PteDst.n.u1IgnorePAT = 1;
1664	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1665	/* PteDst.n.u1Size = 0 */
1666	#else
1667	SHW_PTE_SET(PteDst, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1668	#endif
1669	}
1670
1671	/*
1672	* Make sure only allocated pages are mapped writable.
1673	*/
1674	if ( SHW_PTE_IS_P_RW(PteDst)
1675	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1676	{
1677	/* Still applies to shared pages. */
1678	Assert(!PGM_PAGE_IS_ZERO(pPage));
1679	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1680	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)GST_GET_PTE_GCPHYS(PteSrc), pPage, iPTDst));
1681	}
1682	}
1683
1684	/*
1685	* Keep user track up to date.
1686	*/
1687	if (SHW_PTE_IS_P(PteDst))
1688	{
1689	if (!SHW_PTE_IS_P(*pPteDst))
1690	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1691	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1692	{
1693	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1694	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1695	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1696	}
1697	}
1698	else if (SHW_PTE_IS_P(*pPteDst))
1699	{
1700	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1701	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1702	}
1703
1704	/*
1705	* Update statistics and commit the entry.
1706	*/
1707	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1708	if (!PteSrc.n.u1Global)
1709	pShwPage->fSeenNonGlobal = true;
1710	#endif
1711	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1712	return;
1713	}
1714
1715	/** @todo count these three different kinds. */
1716	Log2(("SyncPageWorker: invalid address in Pte\n"));
1717	}
1718	else if (!PteSrc.n.u1Present)
1719	Log2(("SyncPageWorker: page not present in Pte\n"));
1720	else
1721	Log2(("SyncPageWorker: invalid Pte\n"));
1722
1723	/*
1724	* The page is not present or the PTE is bad. Replace the shadow PTE by
1725	* an empty entry, making sure to keep the user tracking up to date.
1726	*/
1727	if (SHW_PTE_IS_P(*pPteDst))
1728	{
1729	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1730	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst);
1731	}
1732	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1733	}
1734
1735
1736	/**
1737	* Syncs a guest OS page.
1738	*
1739	* There are no conflicts at this point, neither is there any need for
1740	* page table allocations.
1741	*
1742	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1743	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1744	*
1745	* @returns VBox status code.
1746	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1747	* @param pVCpu The VMCPU handle.
1748	* @param PdeSrc Page directory entry of the guest.
1749	* @param GCPtrPage Guest context page address.
1750	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1751	* @param uErr Fault error (X86_TRAP_PF_*).
1752	*/
1753	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1754	{
1755	PVM pVM = pVCpu->CTX_SUFF(pVM);
1756	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1757	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1758
1759	Assert(PGMIsLockOwner(pVM));
1760
1761	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1762	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1763	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1764	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1765	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1766
1767	/*
1768	* Assert preconditions.
1769	*/
1770	Assert(PdeSrc.n.u1Present);
1771	Assert(cPages);
1772	# if 0 /* rarely useful; leave for debugging. */
1773	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1774	# endif
1775
1776	/*
1777	* Get the shadow PDE, find the shadow page table in the pool.
1778	*/
1779	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1780	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1781	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1782
1783	/* Fetch the pgm pool shadow descriptor. */
1784	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1785	Assert(pShwPde);
1786
1787	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1788	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1789	PPGMPOOLPAGE pShwPde = NULL;
1790	PX86PDPAE pPDDst;
1791
1792	/* Fetch the pgm pool shadow descriptor. */
1793	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1794	AssertRCSuccessReturn(rc2, rc2);
1795	Assert(pShwPde);
1796
1797	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1798	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1799
1800	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1801	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1802	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1803	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1804	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1805
1806	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1807	AssertRCSuccessReturn(rc2, rc2);
1808	Assert(pPDDst && pPdptDst);
1809	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1810	# endif
1811	SHWPDE PdeDst = *pPdeDst;
1812
1813	/*
1814	* - In the guest SMP case we could have blocked while another VCPU reused
1815	* this page table.
1816	* - With W7-64 we may also take this path when the the A bit is cleared on
1817	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1818	* relevant TLB entries. If we're write monitoring any page mapped by
1819	* the modified entry, we may end up here with a "stale" TLB entry.
1820	*/
1821	if (!PdeDst.n.u1Present)
1822	{
1823	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1824	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1825	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1826	if (uErr & X86_TRAP_PF_P)
1827	PGM_INVL_PG(pVCpu, GCPtrPage);
1828	return VINF_SUCCESS; /* force the instruction to be executed again. */
1829	}
1830
1831	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1832	Assert(pShwPage);
1833
1834	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1835	/* Fetch the pgm pool shadow descriptor. */
1836	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1837	Assert(pShwPde);
1838	# endif
1839
1840	/*
1841	* Check that the page is present and that the shadow PDE isn't out of sync.
1842	*/
1843	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1844	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1845	RTGCPHYS GCPhys;
1846	if (!fBigPage)
1847	{
1848	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1849	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1850	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1851	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1852	# endif
1853	}
1854	else
1855	{
1856	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1857	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1858	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1859	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1860	# endif
1861	}
1862	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1863	if ( fPdeValid
1864	&& pShwPage->GCPhys == GCPhys
1865	&& PdeSrc.n.u1Present
1866	&& PdeSrc.n.u1User == PdeDst.n.u1User
1867	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1868	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1869	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1870	# endif
1871	)
1872	{
1873	/*
1874	* Check that the PDE is marked accessed already.
1875	* Since we set the accessed bit before getting here on a #PF, this
1876	* check is only meant for dealing with non-#PF'ing paths.
1877	*/
1878	if (PdeSrc.n.u1Accessed)
1879	{
1880	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1881	if (!fBigPage)
1882	{
1883	/*
1884	* 4KB Page - Map the guest page table.
1885	*/
1886	PGSTPT pPTSrc;
1887	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1888	if (RT_SUCCESS(rc))
1889	{
1890	# ifdef PGM_SYNC_N_PAGES
1891	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1892	if ( cPages > 1
1893	&& !(uErr & X86_TRAP_PF_P)
1894	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1895	{
1896	/*
1897	* This code path is currently only taken when the caller is PGMTrap0eHandler
1898	* for non-present pages!
1899	*
1900	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1901	* deal with locality.
1902	*/
1903	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1904	const unsigned iPTDstPage = iPTDst;
1905	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1906	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1907	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1908	# else
1909	const unsigned offPTSrc = 0;
1910	# endif
1911	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1912	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1913	iPTDst = 0;
1914	else
1915	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1916	for (; iPTDst < iPTDstEnd; iPTDst++)
1917	{
1918	if ( !SHW_PTE_IS_P(pPTDst->a[iPTDst])
1919	\|\| iPTDst == iPTDstPage) /* always sync GCPtrPage */
1920	{
1921	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1922	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1923	NOREF(GCPtrCurPage);
1924	#ifndef IN_RING0
1925	/*
1926	* Assuming kernel code will be marked as supervisor - and not as user level
1927	* and executed using a conforming code selector - And marked as readonly.
1928	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1929	*/
1930	PPGMPAGE pPage;
1931	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1932	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1933	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1934	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1935	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1936	)
1937	#endif /* else: CSAM not active */
1938	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1939	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1940	GCPtrCurPage, PteSrc.n.u1Present,
1941	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1942	PteSrc.n.u1User & PdeSrc.n.u1User,
1943	(uint64_t)PteSrc.u,
1944	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1945	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1946	}
1947	}
1948	}
1949	else
1950	# endif /* PGM_SYNC_N_PAGES */
1951	{
1952	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1953	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1954	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1955	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1956	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1957	GCPtrPage, PteSrc.n.u1Present,
1958	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1959	PteSrc.n.u1User & PdeSrc.n.u1User,
1960	(uint64_t)PteSrc.u,
1961	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1962	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1963	}
1964	}
1965	else /* MMIO or invalid page: emulated in #PF handler. */
1966	{
1967	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1968	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1969	}
1970	}
1971	else
1972	{
1973	/*
1974	* 4/2MB page - lazy syncing shadow 4K pages.
1975	* (There are many causes of getting here, it's no longer only CSAM.)
1976	*/
1977	/* Calculate the GC physical address of this 4KB shadow page. */
1978	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1979	/* Find ram range. */
1980	PPGMPAGE pPage;
1981	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1982	if (RT_SUCCESS(rc))
1983	{
1984	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1985
1986	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1987	/* Try to make the page writable if necessary. */
1988	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1989	&& ( PGM_PAGE_IS_ZERO(pPage)
1990	\|\| ( PdeSrc.n.u1Write
1991	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1992	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1993	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1994	# endif
1995	# ifdef VBOX_WITH_PAGE_SHARING
1996	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1997	# endif
1998	)
1999	)
2000	)
2001	{
2002	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2003	AssertRC(rc);
2004	}
2005	# endif
2006
2007	/*
2008	* Make shadow PTE entry.
2009	*/
2010	SHWPTE PteDst;
2011	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2012	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2013	else
2014	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2015
2016	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2017	if ( SHW_PTE_IS_P(PteDst)
2018	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2019	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2020
2021	/* Make sure only allocated pages are mapped writable. */
2022	if ( SHW_PTE_IS_P_RW(PteDst)
2023	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2024	{
2025	/* Still applies to shared pages. */
2026	Assert(!PGM_PAGE_IS_ZERO(pPage));
2027	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2028	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2029	}
2030
2031	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2032
2033	/*
2034	* If the page is not flagged as dirty and is writable, then make it read-only
2035	* at PD level, so we can set the dirty bit when the page is modified.
2036	*
2037	* ASSUMES that page access handlers are implemented on page table entry level.
2038	* Thus we will first catch the dirty access and set PDE.D and restart. If
2039	* there is an access handler, we'll trap again and let it work on the problem.
2040	*/
2041	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2042	* As for invlpg, it simply frees the whole shadow PT.
2043	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2044	if ( !PdeSrc.b.u1Dirty
2045	&& PdeSrc.b.u1Write)
2046	{
2047	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2048	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2049	PdeDst.n.u1Write = 0;
2050	}
2051	else
2052	{
2053	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2054	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2055	}
2056	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2057	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2058	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2059	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2060	}
2061	else
2062	{
2063	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2064	/** @todo must wipe the shadow page table entry in this
2065	* case. */
2066	}
2067	}
2068	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2069	return VINF_SUCCESS;
2070	}
2071
2072	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2073	}
2074	else if (fPdeValid)
2075	{
2076	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2077	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2078	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2079	}
2080	else
2081	{
2082	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2083	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2084	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2085	}
2086
2087	/*
2088	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2089	* Yea, I'm lazy.
2090	*/
2091	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2092	ASMAtomicWriteSize(pPdeDst, 0);
2093
2094	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2095	PGM_INVL_VCPU_TLBS(pVCpu);
2096	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2097
2098
2099	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2100	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2101	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2102	&& !defined(IN_RC)
2103
2104	# ifdef PGM_SYNC_N_PAGES
2105	/*
2106	* Get the shadow PDE, find the shadow page table in the pool.
2107	*/
2108	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2109	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2110
2111	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2112	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2113
2114	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2115	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2116	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2117	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2118	X86PDEPAE PdeDst;
2119	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2120
2121	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2122	AssertRCSuccessReturn(rc, rc);
2123	Assert(pPDDst && pPdptDst);
2124	PdeDst = pPDDst->a[iPDDst];
2125	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2126	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2127	PEPTPD pPDDst;
2128	EPTPDE PdeDst;
2129
2130	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2131	if (rc != VINF_SUCCESS)
2132	{
2133	AssertRC(rc);
2134	return rc;
2135	}
2136	Assert(pPDDst);
2137	PdeDst = pPDDst->a[iPDDst];
2138	# endif
2139	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2140	if (!PdeDst.n.u1Present)
2141	{
2142	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2143	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2144	return VINF_SUCCESS; /* force the instruction to be executed again. */
2145	}
2146
2147	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2148	if (PdeDst.n.u1Size)
2149	{
2150	Assert(pVM->pgm.s.fNestedPaging);
2151	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2152	return VINF_SUCCESS;
2153	}
2154
2155	/* Mask away the page offset. */
2156	GCPtrPage &= ~((RTGCPTR)0xfff);
2157
2158	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2159	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2160
2161	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2162	if ( cPages > 1
2163	&& !(uErr & X86_TRAP_PF_P)
2164	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2165	{
2166	/*
2167	* This code path is currently only taken when the caller is PGMTrap0eHandler
2168	* for non-present pages!
2169	*
2170	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2171	* deal with locality.
2172	*/
2173	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2174	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2175	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2176	iPTDst = 0;
2177	else
2178	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2179	for (; iPTDst < iPTDstEnd; iPTDst++)
2180	{
2181	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2182	{
2183	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2184	GSTPTE PteSrc;
2185
2186	/* Fake the page table entry */
2187	PteSrc.u = GCPtrCurPage;
2188	PteSrc.n.u1Present = 1;
2189	PteSrc.n.u1Dirty = 1;
2190	PteSrc.n.u1Accessed = 1;
2191	PteSrc.n.u1Write = 1;
2192	PteSrc.n.u1User = 1;
2193
2194	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2195	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2196	GCPtrCurPage, PteSrc.n.u1Present,
2197	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2198	PteSrc.n.u1User & PdeSrc.n.u1User,
2199	(uint64_t)PteSrc.u,
2200	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2201	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2202
2203	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2204	break;
2205	}
2206	else
2207	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2208	}
2209	}
2210	else
2211	# endif /* PGM_SYNC_N_PAGES */
2212	{
2213	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2214	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2215	GSTPTE PteSrc;
2216
2217	/* Fake the page table entry */
2218	PteSrc.u = GCPtrCurPage;
2219	PteSrc.n.u1Present = 1;
2220	PteSrc.n.u1Dirty = 1;
2221	PteSrc.n.u1Accessed = 1;
2222	PteSrc.n.u1Write = 1;
2223	PteSrc.n.u1User = 1;
2224	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2225
2226	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2227	GCPtrPage, PteSrc.n.u1Present,
2228	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2229	PteSrc.n.u1User & PdeSrc.n.u1User,
2230	(uint64_t)PteSrc.u,
2231	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2232	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2233	}
2234	return VINF_SUCCESS;
2235
2236	#else
2237	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2238	return VERR_INTERNAL_ERROR;
2239	#endif
2240	}
2241
2242
2243	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2244
2245	/**
2246	* CheckPageFault helper for returning a page fault indicating a non-present
2247	* (NP) entry in the page translation structures.
2248	*
2249	* @returns VINF_EM_RAW_GUEST_TRAP.
2250	* @param pVCpu The virtual CPU to operate on.
2251	* @param uErr The error code of the shadow fault. Corrections to
2252	* TRPM's copy will be made if necessary.
2253	* @param GCPtrPage For logging.
2254	* @param uPageFaultLevel For logging.
2255	*/
2256	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2257	{
2258	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2259	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2260	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2261	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2262	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2263
2264	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2265	return VINF_EM_RAW_GUEST_TRAP;
2266	}
2267
2268
2269	/**
2270	* CheckPageFault helper for returning a page fault indicating a reserved bit
2271	* (RSVD) error in the page translation structures.
2272	*
2273	* @returns VINF_EM_RAW_GUEST_TRAP.
2274	* @param pVCpu The virtual CPU to operate on.
2275	* @param uErr The error code of the shadow fault. Corrections to
2276	* TRPM's copy will be made if necessary.
2277	* @param GCPtrPage For logging.
2278	* @param uPageFaultLevel For logging.
2279	*/
2280	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2281	{
2282	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2283	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2284	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2285
2286	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2287	return VINF_EM_RAW_GUEST_TRAP;
2288	}
2289
2290
2291	/**
2292	* CheckPageFault helper for returning a page protection fault (P).
2293	*
2294	* @returns VINF_EM_RAW_GUEST_TRAP.
2295	* @param pVCpu The virtual CPU to operate on.
2296	* @param uErr The error code of the shadow fault. Corrections to
2297	* TRPM's copy will be made if necessary.
2298	* @param GCPtrPage For logging.
2299	* @param uPageFaultLevel For logging.
2300	*/
2301	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2302	{
2303	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2304	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2305	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2306	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2307
2308	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2309	return VINF_EM_RAW_GUEST_TRAP;
2310	}
2311
2312
2313	/**
2314	* Handle dirty bit tracking faults.
2315	*
2316	* @returns VBox status code.
2317	* @param pVCpu The VMCPU handle.
2318	* @param uErr Page fault error code.
2319	* @param pPdeSrc Guest page directory entry.
2320	* @param pPdeDst Shadow page directory entry.
2321	* @param GCPtrPage Guest context page address.
2322	*/
2323	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2324	{
2325	PVM pVM = pVCpu->CTX_SUFF(pVM);
2326	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2327
2328	Assert(PGMIsLockOwner(pVM));
2329
2330	/*
2331	* Handle big page.
2332	*/
2333	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2334	{
2335	if ( pPdeDst->n.u1Present
2336	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2337	{
2338	SHWPDE PdeDst = *pPdeDst;
2339
2340	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2341	Assert(pPdeSrc->b.u1Write);
2342
2343	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2344	* fault again and take this path to only invalidate the entry (see below).
2345	*/
2346	PdeDst.n.u1Write = 1;
2347	PdeDst.n.u1Accessed = 1;
2348	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2349	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2350	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2351	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2352	}
2353
2354	# ifdef IN_RING0
2355	/* Check for stale TLB entry; only applies to the SMP guest case. */
2356	if ( pVM->cCpus > 1
2357	&& pPdeDst->n.u1Write
2358	&& pPdeDst->n.u1Accessed)
2359	{
2360	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2361	if (pShwPage)
2362	{
2363	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2364	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2365	if (SHW_PTE_IS_P_RW(*pPteDst))
2366	{
2367	/* Stale TLB entry. */
2368	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2369	PGM_INVL_PG(pVCpu, GCPtrPage);
2370	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2371	}
2372	}
2373	}
2374	# endif /* IN_RING0 */
2375	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2376	}
2377
2378	/*
2379	* Map the guest page table.
2380	*/
2381	PGSTPT pPTSrc;
2382	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2383	if (RT_FAILURE(rc))
2384	{
2385	AssertRC(rc);
2386	return rc;
2387	}
2388
2389	if (pPdeDst->n.u1Present)
2390	{
2391	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2392	const GSTPTE PteSrc = *pPteSrc;
2393
2394	#ifndef IN_RING0
2395	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2396	* Our individual shadow handlers will provide more information and force a fatal exit.
2397	*/
2398	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2399	{
2400	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2401	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2402	}
2403	#endif
2404	/*
2405	* Map shadow page table.
2406	*/
2407	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2408	if (pShwPage)
2409	{
2410	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2411	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2412	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2413	{
2414	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2415	{
2416	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2417	SHWPTE PteDst = *pPteDst;
2418
2419	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2420	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2421
2422	Assert(pPteSrc->n.u1Write);
2423
2424	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2425	* entry will not harm; write access will simply fault again and
2426	* take this path to only invalidate the entry.
2427	*/
2428	if (RT_LIKELY(pPage))
2429	{
2430	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2431	{
2432	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2433	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2434	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2435	SHW_PTE_SET_RO(PteDst);
2436	}
2437	else
2438	{
2439	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2440	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2441	{
2442	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2443	AssertRC(rc);
2444	}
2445	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2446	SHW_PTE_SET_RW(PteDst);
2447	else
2448	{
2449	/* Still applies to shared pages. */
2450	Assert(!PGM_PAGE_IS_ZERO(pPage));
2451	SHW_PTE_SET_RO(PteDst);
2452	}
2453	}
2454	}
2455	else
2456	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2457
2458	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2459	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2460	PGM_INVL_PG(pVCpu, GCPtrPage);
2461	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2462	}
2463
2464	# ifdef IN_RING0
2465	/* Check for stale TLB entry; only applies to the SMP guest case. */
2466	if ( pVM->cCpus > 1
2467	&& SHW_PTE_IS_RW(*pPteDst)
2468	&& SHW_PTE_IS_A(*pPteDst))
2469	{
2470	/* Stale TLB entry. */
2471	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2472	PGM_INVL_PG(pVCpu, GCPtrPage);
2473	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2474	}
2475	# endif
2476	}
2477	}
2478	else
2479	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2480	}
2481
2482	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2483	}
2484
2485	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2486
2487
2488	/**
2489	* Sync a shadow page table.
2490	*
2491	* The shadow page table is not present in the shadow PDE.
2492	*
2493	* Handles mapping conflicts.
2494	*
2495	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2496	* conflict), and Trap0eHandler.
2497	*
2498	* A precodition for this method is that the shadow PDE is not present. The
2499	* caller must take the PGM lock before checking this and continue to hold it
2500	* when calling this method.
2501	*
2502	* @returns VBox status code.
2503	* @param pVCpu The VMCPU handle.
2504	* @param iPD Page directory index.
2505	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2506	* Assume this is a temporary mapping.
2507	* @param GCPtrPage GC Pointer of the page that caused the fault
2508	*/
2509	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2510	{
2511	PVM pVM = pVCpu->CTX_SUFF(pVM);
2512	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2513
2514	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2515	#if 0 /* rarely useful; leave for debugging. */
2516	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2517	#endif
2518	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2519
2520	Assert(PGMIsLocked(pVM));
2521
2522	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2523	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2524	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2525	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2526	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2527
2528	int rc = VINF_SUCCESS;
2529
2530	/*
2531	* Some input validation first.
2532	*/
2533	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2534
2535	/*
2536	* Get the relevant shadow PDE entry.
2537	*/
2538	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2539	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2540	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2541
2542	/* Fetch the pgm pool shadow descriptor. */
2543	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2544	Assert(pShwPde);
2545
2546	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2547	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2548	PPGMPOOLPAGE pShwPde = NULL;
2549	PX86PDPAE pPDDst;
2550	PSHWPDE pPdeDst;
2551
2552	/* Fetch the pgm pool shadow descriptor. */
2553	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2554	AssertRCSuccessReturn(rc, rc);
2555	Assert(pShwPde);
2556
2557	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2558	pPdeDst = &pPDDst->a[iPDDst];
2559
2560	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2561	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2562	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2563	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2564	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2565	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2566	AssertRCSuccessReturn(rc, rc);
2567	Assert(pPDDst);
2568	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2569	# endif
2570	SHWPDE PdeDst = *pPdeDst;
2571
2572	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2573	/* Fetch the pgm pool shadow descriptor. */
2574	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2575	Assert(pShwPde);
2576	# endif
2577
2578	# ifndef PGM_WITHOUT_MAPPINGS
2579	/*
2580	* Check for conflicts.
2581	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2582	* R3: Simply resolve the conflict.
2583	*/
2584	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2585	{
2586	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2587	# ifndef IN_RING3
2588	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2589	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2590	return VERR_ADDRESS_CONFLICT;
2591
2592	# else /* IN_RING3 */
2593	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2594	Assert(pMapping);
2595	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2596	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2597	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2598	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2599	# else
2600	AssertFailed(); /* can't happen for amd64 */
2601	# endif
2602	if (RT_FAILURE(rc))
2603	{
2604	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2605	return rc;
2606	}
2607	PdeDst = *pPdeDst;
2608	# endif /* IN_RING3 */
2609	}
2610	# endif /* !PGM_WITHOUT_MAPPINGS */
2611	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2612
2613	/*
2614	* Sync the page directory entry.
2615	*/
2616	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2617	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2618	if ( PdeSrc.n.u1Present
2619	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2620	{
2621	/*
2622	* Allocate & map the page table.
2623	*/
2624	PSHWPT pPTDst;
2625	PPGMPOOLPAGE pShwPage;
2626	RTGCPHYS GCPhys;
2627	if (fPageTable)
2628	{
2629	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2630	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2631	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2632	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2633	# endif
2634	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2635	}
2636	else
2637	{
2638	PGMPOOLACCESS enmAccess;
2639	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2640	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2641	# else
2642	const bool fNoExecute = false;
2643	# endif
2644
2645	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2646	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2647	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2648	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2649	# endif
2650	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2651	if (PdeSrc.n.u1User)
2652	{
2653	if (PdeSrc.n.u1Write)
2654	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2655	else
2656	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2657	}
2658	else
2659	{
2660	if (PdeSrc.n.u1Write)
2661	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2662	else
2663	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2664	}
2665	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2666	&pShwPage);
2667	}
2668	if (rc == VINF_SUCCESS)
2669	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2670	else if (rc == VINF_PGM_CACHED_PAGE)
2671	{
2672	/*
2673	* The PT was cached, just hook it up.
2674	*/
2675	if (fPageTable)
2676	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2677	else
2678	{
2679	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2680	/* (see explanation and assumptions further down.) */
2681	if ( !PdeSrc.b.u1Dirty
2682	&& PdeSrc.b.u1Write)
2683	{
2684	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2685	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2686	PdeDst.b.u1Write = 0;
2687	}
2688	}
2689	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2690	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2691	return VINF_SUCCESS;
2692	}
2693	else if (rc == VERR_PGM_POOL_FLUSHED)
2694	{
2695	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2696	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2697	return VINF_PGM_SYNC_CR3;
2698	}
2699	else
2700	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2701	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2702	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2703	* irrelevant at this point. */
2704	PdeDst.u &= X86_PDE_AVL_MASK;
2705	PdeDst.u \|= pShwPage->Core.Key;
2706
2707	/*
2708	* Page directory has been accessed (this is a fault situation, remember).
2709	*/
2710	/** @todo
2711	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2712	* fault situation. What's more, the Trap0eHandler has already set the
2713	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2714	* might need setting the accessed flag.
2715	*
2716	* The best idea is to leave this change to the caller and add an
2717	* assertion that it's set already. */
2718	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2719	if (fPageTable)
2720	{
2721	/*
2722	* Page table - 4KB.
2723	*
2724	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2725	*/
2726	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2727	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2728	PGSTPT pPTSrc;
2729	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2730	if (RT_SUCCESS(rc))
2731	{
2732	/*
2733	* Start by syncing the page directory entry so CSAM's TLB trick works.
2734	*/
2735	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2736	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2737	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2738	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2739
2740	/*
2741	* Directory/page user or supervisor privilege: (same goes for read/write)
2742	*
2743	* Directory Page Combined
2744	* U/S U/S U/S
2745	* 0 0 0
2746	* 0 1 0
2747	* 1 0 0
2748	* 1 1 1
2749	*
2750	* Simple AND operation. Table listed for completeness.
2751	*
2752	*/
2753	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2754	# ifdef PGM_SYNC_N_PAGES
2755	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2756	unsigned iPTDst = iPTBase;
2757	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2758	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2759	iPTDst = 0;
2760	else
2761	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2762	# else /* !PGM_SYNC_N_PAGES */
2763	unsigned iPTDst = 0;
2764	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2765	# endif /* !PGM_SYNC_N_PAGES */
2766	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2767	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2768	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2769	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2770	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2771	# else
2772	const unsigned offPTSrc = 0;
2773	# endif
2774	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2775	{
2776	const unsigned iPTSrc = iPTDst + offPTSrc;
2777	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2778
2779	if (PteSrc.n.u1Present)
2780	{
2781	# ifndef IN_RING0
2782	/*
2783	* Assuming kernel code will be marked as supervisor - and not as user level
2784	* and executed using a conforming code selector - And marked as readonly.
2785	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2786	*/
2787	PPGMPAGE pPage;
2788	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2789	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2790	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2791	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2792	)
2793	# endif
2794	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2795	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2796	GCPtrCur,
2797	PteSrc.n.u1Present,
2798	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2799	PteSrc.n.u1User & PdeSrc.n.u1User,
2800	(uint64_t)PteSrc.u,
2801	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2802	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2803	}
2804	/* else: the page table was cleared by the pool */
2805	} /* for PTEs */
2806	}
2807	}
2808	else
2809	{
2810	/*
2811	* Big page - 2/4MB.
2812	*
2813	* We'll walk the ram range list in parallel and optimize lookups.
2814	* We will only sync on shadow page table at a time.
2815	*/
2816	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2817
2818	/**
2819	* @todo It might be more efficient to sync only a part of the 4MB
2820	* page (similar to what we do for 4KB PDs).
2821	*/
2822
2823	/*
2824	* Start by syncing the page directory entry.
2825	*/
2826	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2827	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2828
2829	/*
2830	* If the page is not flagged as dirty and is writable, then make it read-only
2831	* at PD level, so we can set the dirty bit when the page is modified.
2832	*
2833	* ASSUMES that page access handlers are implemented on page table entry level.
2834	* Thus we will first catch the dirty access and set PDE.D and restart. If
2835	* there is an access handler, we'll trap again and let it work on the problem.
2836	*/
2837	/** @todo move the above stuff to a section in the PGM documentation. */
2838	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2839	if ( !PdeSrc.b.u1Dirty
2840	&& PdeSrc.b.u1Write)
2841	{
2842	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2843	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2844	PdeDst.b.u1Write = 0;
2845	}
2846	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2847	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2848
2849	/*
2850	* Fill the shadow page table.
2851	*/
2852	/* Get address and flags from the source PDE. */
2853	SHWPTE PteDstBase;
2854	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2855
2856	/* Loop thru the entries in the shadow PT. */
2857	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2858	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2859	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2860	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2861	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2862	unsigned iPTDst = 0;
2863	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2864	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2865	{
2866	/* Advance ram range list. */
2867	while (pRam && GCPhys > pRam->GCPhysLast)
2868	pRam = pRam->CTX_SUFF(pNext);
2869	if (pRam && GCPhys >= pRam->GCPhys)
2870	{
2871	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2872	do
2873	{
2874	/* Make shadow PTE. */
2875	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2876	SHWPTE PteDst;
2877
2878	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2879	/* Try to make the page writable if necessary. */
2880	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2881	&& ( PGM_PAGE_IS_ZERO(pPage)
2882	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2883	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2884	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2885	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2886	# endif
2887	# ifdef VBOX_WITH_PAGE_SHARING
2888	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2889	# endif
2890	&& !PGM_PAGE_IS_BALLOONED(pPage))
2891	)
2892	)
2893	{
2894	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2895	AssertRCReturn(rc, rc);
2896	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2897	break;
2898	}
2899	# endif
2900
2901	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2902	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2903	else if (PGM_PAGE_IS_BALLOONED(pPage))
2904	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2905	# ifndef IN_RING0
2906	/*
2907	* Assuming kernel code will be marked as supervisor and not as user level and executed
2908	* using a conforming code selector. Don't check for readonly, as that implies the whole
2909	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2910	*/
2911	else if ( !PdeSrc.n.u1User
2912	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2913	SHW_PTE_SET(PteDst, 0);
2914	# endif
2915	else
2916	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2917
2918	/* Only map writable pages writable. */
2919	if ( SHW_PTE_IS_P_RW(PteDst)
2920	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2921	{
2922	/* Still applies to shared pages. */
2923	Assert(!PGM_PAGE_IS_ZERO(pPage));
2924	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2925	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2926	}
2927
2928	if (SHW_PTE_IS_P(PteDst))
2929	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2930
2931	/* commit it (not atomic, new table) */
2932	pPTDst->a[iPTDst] = PteDst;
2933	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2934	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2935	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2936
2937	/* advance */
2938	GCPhys += PAGE_SIZE;
2939	iHCPage++;
2940	iPTDst++;
2941	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2942	&& GCPhys <= pRam->GCPhysLast);
2943	}
2944	else if (pRam)
2945	{
2946	Log(("Invalid pages at %RGp\n", GCPhys));
2947	do
2948	{
2949	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2950	GCPhys += PAGE_SIZE;
2951	iPTDst++;
2952	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2953	&& GCPhys < pRam->GCPhys);
2954	}
2955	else
2956	{
2957	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2958	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2959	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2960	}
2961	} /* while more PTEs */
2962	} /* 4KB / 4MB */
2963	}
2964	else
2965	AssertRelease(!PdeDst.n.u1Present);
2966
2967	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2968	if (RT_FAILURE(rc))
2969	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2970	return rc;
2971
2972	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2973	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2974	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2975	&& !defined(IN_RC)
2976
2977	/*
2978	* Validate input a little bit.
2979	*/
2980	int rc = VINF_SUCCESS;
2981	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2982	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2983	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2984
2985	/* Fetch the pgm pool shadow descriptor. */
2986	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2987	Assert(pShwPde);
2988
2989	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2990	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2991	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
2992	PX86PDPAE pPDDst;
2993	PSHWPDE pPdeDst;
2994
2995	/* Fetch the pgm pool shadow descriptor. */
2996	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2997	AssertRCSuccessReturn(rc, rc);
2998	Assert(pShwPde);
2999
3000	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3001	pPdeDst = &pPDDst->a[iPDDst];
3002
3003	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3004	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3005	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3006	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3007	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3008	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3009	AssertRCSuccessReturn(rc, rc);
3010	Assert(pPDDst);
3011	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3012
3013	/* Fetch the pgm pool shadow descriptor. */
3014	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3015	Assert(pShwPde);
3016
3017	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3018	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3019	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3020	PEPTPD pPDDst;
3021	PEPTPDPT pPdptDst;
3022
3023	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3024	if (rc != VINF_SUCCESS)
3025	{
3026	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3027	AssertRC(rc);
3028	return rc;
3029	}
3030	Assert(pPDDst);
3031	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3032
3033	/* Fetch the pgm pool shadow descriptor. */
3034	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3035	Assert(pShwPde);
3036	# endif
3037	SHWPDE PdeDst = *pPdeDst;
3038
3039	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3040	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3041
3042	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3043	if (BTH_IS_NP_ACTIVE(pVM))
3044	{
3045	PPGMPAGE pPage;
3046
3047	/* Check if we allocated a big page before for this 2 MB range. */
3048	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3049	if (RT_SUCCESS(rc))
3050	{
3051	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3052
3053	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3054	{
3055	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3056	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3057	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3058	}
3059	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3060	{
3061	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3062	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3063	if (RT_SUCCESS(rc))
3064	{
3065	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3066	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3067	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3068	}
3069	}
3070	else if (PGMIsUsingLargePages(pVM))
3071	{
3072	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3073	if (RT_SUCCESS(rc))
3074	{
3075	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3076	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3077	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3078	}
3079	else
3080	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3081	}
3082
3083	if (HCPhys != NIL_RTHCPHYS)
3084	{
3085	PdeDst.u &= X86_PDE_AVL_MASK;
3086	PdeDst.u \|= HCPhys;
3087	PdeDst.n.u1Present = 1;
3088	PdeDst.n.u1Write = 1;
3089	PdeDst.b.u1Size = 1;
3090	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3091	PdeDst.n.u1Execute = 1;
3092	PdeDst.b.u1IgnorePAT = 1;
3093	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3094	# else
3095	PdeDst.n.u1User = 1;
3096	# endif
3097	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3098
3099	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3100	/* Add a reference to the first page only. */
3101	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3102
3103	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3104	return VINF_SUCCESS;
3105	}
3106	}
3107	}
3108	# endif /* HC_ARCH_BITS == 64 */
3109
3110	GSTPDE PdeSrc;
3111	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3112	PdeSrc.n.u1Present = 1;
3113	PdeSrc.n.u1Write = 1;
3114	PdeSrc.n.u1Accessed = 1;
3115	PdeSrc.n.u1User = 1;
3116
3117	/*
3118	* Allocate & map the page table.
3119	*/
3120	PSHWPT pPTDst;
3121	PPGMPOOLPAGE pShwPage;
3122	RTGCPHYS GCPhys;
3123
3124	/* Virtual address = physical address */
3125	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3126	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3127
3128	if ( rc == VINF_SUCCESS
3129	\|\| rc == VINF_PGM_CACHED_PAGE)
3130	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3131	else
3132	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3133
3134	PdeDst.u &= X86_PDE_AVL_MASK;
3135	PdeDst.u \|= pShwPage->Core.Key;
3136	PdeDst.n.u1Present = 1;
3137	PdeDst.n.u1Write = 1;
3138	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3139	PdeDst.n.u1Execute = 1;
3140	# else
3141	PdeDst.n.u1User = 1;
3142	PdeDst.n.u1Accessed = 1;
3143	# endif
3144	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3145
3146	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3147	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3148	return rc;
3149
3150	#else
3151	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3152	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3153	return VERR_INTERNAL_ERROR;
3154	#endif
3155	}
3156
3157
3158
3159	/**
3160	* Prefetch a page/set of pages.
3161	*
3162	* Typically used to sync commonly used pages before entering raw mode
3163	* after a CR3 reload.
3164	*
3165	* @returns VBox status code.
3166	* @param pVCpu The VMCPU handle.
3167	* @param GCPtrPage Page to invalidate.
3168	*/
3169	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3170	{
3171	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3172	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3173	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3174	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3175	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3176	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3177	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3178
3179	/*
3180	* Check that all Guest levels thru the PDE are present, getting the
3181	* PD and PDE in the processes.
3182	*/
3183	int rc = VINF_SUCCESS;
3184	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3185	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3186	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3187	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3188	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3189	unsigned iPDSrc;
3190	X86PDPE PdpeSrc;
3191	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3192	if (!pPDSrc)
3193	return VINF_SUCCESS; /* not present */
3194	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3195	unsigned iPDSrc;
3196	PX86PML4E pPml4eSrc;
3197	X86PDPE PdpeSrc;
3198	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3199	if (!pPDSrc)
3200	return VINF_SUCCESS; /* not present */
3201	# endif
3202	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3203	# else
3204	PGSTPD pPDSrc = NULL;
3205	const unsigned iPDSrc = 0;
3206	GSTPDE PdeSrc;
3207
3208	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3209	PdeSrc.n.u1Present = 1;
3210	PdeSrc.n.u1Write = 1;
3211	PdeSrc.n.u1Accessed = 1;
3212	PdeSrc.n.u1User = 1;
3213	# endif
3214
3215	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3216	{
3217	PVM pVM = pVCpu->CTX_SUFF(pVM);
3218	pgmLock(pVM);
3219
3220	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3221	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3222	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3223	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3224	PX86PDPAE pPDDst;
3225	X86PDEPAE PdeDst;
3226	# if PGM_GST_TYPE != PGM_TYPE_PAE
3227	X86PDPE PdpeSrc;
3228
3229	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3230	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3231	# endif
3232	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3233	if (rc != VINF_SUCCESS)
3234	{
3235	pgmUnlock(pVM);
3236	AssertRC(rc);
3237	return rc;
3238	}
3239	Assert(pPDDst);
3240	PdeDst = pPDDst->a[iPDDst];
3241
3242	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3243	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3244	PX86PDPAE pPDDst;
3245	X86PDEPAE PdeDst;
3246
3247	# if PGM_GST_TYPE == PGM_TYPE_PROT
3248	/* AMD-V nested paging */
3249	X86PML4E Pml4eSrc;
3250	X86PDPE PdpeSrc;
3251	PX86PML4E pPml4eSrc = &Pml4eSrc;
3252
3253	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3254	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3255	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3256	# endif
3257
3258	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3259	if (rc != VINF_SUCCESS)
3260	{
3261	pgmUnlock(pVM);
3262	AssertRC(rc);
3263	return rc;
3264	}
3265	Assert(pPDDst);
3266	PdeDst = pPDDst->a[iPDDst];
3267	# endif
3268	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3269	{
3270	if (!PdeDst.n.u1Present)
3271	{
3272	/** @todo r=bird: This guy will set the A bit on the PDE,
3273	* probably harmless. */
3274	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3275	}
3276	else
3277	{
3278	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3279	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3280	* makes no sense to prefetch more than one page.
3281	*/
3282	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3283	if (RT_SUCCESS(rc))
3284	rc = VINF_SUCCESS;
3285	}
3286	}
3287	pgmUnlock(pVM);
3288	}
3289	return rc;
3290
3291	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3292	return VINF_SUCCESS; /* ignore */
3293	#else
3294	AssertCompile(0);
3295	#endif
3296	}
3297
3298
3299
3300
3301	/**
3302	* Syncs a page during a PGMVerifyAccess() call.
3303	*
3304	* @returns VBox status code (informational included).
3305	* @param pVCpu The VMCPU handle.
3306	* @param GCPtrPage The address of the page to sync.
3307	* @param fPage The effective guest page flags.
3308	* @param uErr The trap error code.
3309	* @remarks This will normally never be called on invalid guest page
3310	* translation entries.
3311	*/
3312	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3313	{
3314	PVM pVM = pVCpu->CTX_SUFF(pVM);
3315
3316	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3317
3318	Assert(!pVM->pgm.s.fNestedPaging);
3319	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3320	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3321	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3322	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3323	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3324	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3325	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3326
3327	# ifndef IN_RING0
3328	if (!(fPage & X86_PTE_US))
3329	{
3330	/*
3331	* Mark this page as safe.
3332	*/
3333	/** @todo not correct for pages that contain both code and data!! */
3334	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3335	CSAMMarkPage(pVM, GCPtrPage, true);
3336	}
3337	# endif
3338
3339	/*
3340	* Get guest PD and index.
3341	*/
3342	/** @todo Performance: We've done all this a jiffy ago in the
3343	* PGMGstGetPage call. */
3344	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3345	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3346	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3347	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3348
3349	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3350	unsigned iPDSrc = 0;
3351	X86PDPE PdpeSrc;
3352	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3353	if (RT_UNLIKELY(!pPDSrc))
3354	{
3355	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3356	return VINF_EM_RAW_GUEST_TRAP;
3357	}
3358
3359	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3360	unsigned iPDSrc = 0; /* shut up gcc */
3361	PX86PML4E pPml4eSrc = NULL; /* ditto */
3362	X86PDPE PdpeSrc;
3363	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3364	if (RT_UNLIKELY(!pPDSrc))
3365	{
3366	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3367	return VINF_EM_RAW_GUEST_TRAP;
3368	}
3369	# endif
3370
3371	# else /* !PGM_WITH_PAGING */
3372	PGSTPD pPDSrc = NULL;
3373	const unsigned iPDSrc = 0;
3374	# endif /* !PGM_WITH_PAGING */
3375	int rc = VINF_SUCCESS;
3376
3377	pgmLock(pVM);
3378
3379	/*
3380	* First check if the shadow pd is present.
3381	*/
3382	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3383	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3384
3385	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3386	PX86PDEPAE pPdeDst;
3387	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3388	PX86PDPAE pPDDst;
3389	# if PGM_GST_TYPE != PGM_TYPE_PAE
3390	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3391	X86PDPE PdpeSrc;
3392	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3393	# endif
3394	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3395	if (rc != VINF_SUCCESS)
3396	{
3397	pgmUnlock(pVM);
3398	AssertRC(rc);
3399	return rc;
3400	}
3401	Assert(pPDDst);
3402	pPdeDst = &pPDDst->a[iPDDst];
3403
3404	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3405	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3406	PX86PDPAE pPDDst;
3407	PX86PDEPAE pPdeDst;
3408
3409	# if PGM_GST_TYPE == PGM_TYPE_PROT
3410	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3411	X86PML4E Pml4eSrc;
3412	X86PDPE PdpeSrc;
3413	PX86PML4E pPml4eSrc = &Pml4eSrc;
3414	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3415	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3416	# endif
3417
3418	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3419	if (rc != VINF_SUCCESS)
3420	{
3421	pgmUnlock(pVM);
3422	AssertRC(rc);
3423	return rc;
3424	}
3425	Assert(pPDDst);
3426	pPdeDst = &pPDDst->a[iPDDst];
3427	# endif
3428
3429	if (!pPdeDst->n.u1Present)
3430	{
3431	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3432	if (rc != VINF_SUCCESS)
3433	{
3434	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3435	pgmUnlock(pVM);
3436	AssertRC(rc);
3437	return rc;
3438	}
3439	}
3440
3441	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3442	/* Check for dirty bit fault */
3443	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3444	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3445	Log(("PGMVerifyAccess: success (dirty)\n"));
3446	else
3447	# endif
3448	{
3449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3450	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3451	# else
3452	GSTPDE PdeSrc;
3453	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3454	PdeSrc.n.u1Present = 1;
3455	PdeSrc.n.u1Write = 1;
3456	PdeSrc.n.u1Accessed = 1;
3457	PdeSrc.n.u1User = 1;
3458	# endif
3459
3460	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3461	if (uErr & X86_TRAP_PF_US)
3462	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3463	else /* supervisor */
3464	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3465
3466	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3467	if (RT_SUCCESS(rc))
3468	{
3469	/* Page was successfully synced */
3470	Log2(("PGMVerifyAccess: success (sync)\n"));
3471	rc = VINF_SUCCESS;
3472	}
3473	else
3474	{
3475	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3476	rc = VINF_EM_RAW_GUEST_TRAP;
3477	}
3478	}
3479	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3480	pgmUnlock(pVM);
3481	return rc;
3482
3483	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3484
3485	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3486	return VERR_INTERNAL_ERROR;
3487	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3488	}
3489
3490
3491	/**
3492	* Syncs the paging hierarchy starting at CR3.
3493	*
3494	* @returns VBox status code, no specials.
3495	* @param pVCpu The VMCPU handle.
3496	* @param cr0 Guest context CR0 register
3497	* @param cr3 Guest context CR3 register
3498	* @param cr4 Guest context CR4 register
3499	* @param fGlobal Including global page directories or not
3500	*/
3501	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3502	{
3503	PVM pVM = pVCpu->CTX_SUFF(pVM);
3504
3505	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3506
3507	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3508
3509	pgmLock(pVM);
3510
3511	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3512	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3513	if (pPool->cDirtyPages)
3514	pgmPoolResetDirtyPages(pVM);
3515	# endif
3516
3517	/*
3518	* Update page access handlers.
3519	* The virtual are always flushed, while the physical are only on demand.
3520	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3521	* have to look into that later because it will have a bad influence on the performance.
3522	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3523	* bird: Yes, but that won't work for aliases.
3524	*/
3525	/** @todo this MUST go away. See #1557. */
3526	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3527	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3528	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3529	pgmUnlock(pVM);
3530	#endif /* !NESTED && !EPT */
3531
3532	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3533	/*
3534	* Nested / EPT - almost no work.
3535	*/
3536	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3537	return VINF_SUCCESS;
3538
3539	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3540	/*
3541	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3542	* out the shadow parts when the guest modifies its tables.
3543	*/
3544	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3545	return VINF_SUCCESS;
3546
3547	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3548
3549	# ifndef PGM_WITHOUT_MAPPINGS
3550	/*
3551	* Check for and resolve conflicts with our guest mappings if they
3552	* are enabled and not fixed.
3553	*/
3554	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3555	{
3556	int rc = pgmMapResolveConflicts(pVM);
3557	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3558	if (rc == VINF_PGM_SYNC_CR3)
3559	{
3560	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3561	return VINF_PGM_SYNC_CR3;
3562	}
3563	}
3564	# else
3565	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3566	# endif
3567	return VINF_SUCCESS;
3568	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3569	}
3570
3571
3572
3573
3574	#ifdef VBOX_STRICT
3575	# ifdef IN_RC
3576	# undef AssertMsgFailed
3577	# define AssertMsgFailed Log
3578	# endif
3579
3580	/**
3581	* Checks that the shadow page table is in sync with the guest one.
3582	*
3583	* @returns The number of errors.
3584	* @param pVM The virtual machine.
3585	* @param pVCpu The VMCPU handle.
3586	* @param cr3 Guest context CR3 register
3587	* @param cr4 Guest context CR4 register
3588	* @param GCPtr Where to start. Defaults to 0.
3589	* @param cb How much to check. Defaults to everything.
3590	*/
3591	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3592	{
3593	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3594	return 0;
3595	#else
3596	unsigned cErrors = 0;
3597	PVM pVM = pVCpu->CTX_SUFF(pVM);
3598	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3599
3600	#if PGM_GST_TYPE == PGM_TYPE_PAE
3601	/** @todo currently broken; crashes below somewhere */
3602	AssertFailed();
3603	#endif
3604
3605	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3606	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3607	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3608
3609	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3610	PPGMCPU pPGM = &pVCpu->pgm.s;
3611	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3612	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3613	# ifndef IN_RING0
3614	RTHCPHYS HCPhys; /* general usage. */
3615	# endif
3616	int rc;
3617
3618	/*
3619	* Check that the Guest CR3 and all its mappings are correct.
3620	*/
3621	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3622	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3623	false);
3624	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3625	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3626	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3627	# else
3628	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3629	# endif
3630	AssertRCReturn(rc, 1);
3631	HCPhys = NIL_RTHCPHYS;
3632	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3633	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3634	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3635	pgmGstGet32bitPDPtr(pVCpu);
3636	RTGCPHYS GCPhys;
3637	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3638	AssertRCReturn(rc, 1);
3639	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3640	# endif
3641	# endif /* !IN_RING0 */
3642
3643	/*
3644	* Get and check the Shadow CR3.
3645	*/
3646	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3647	unsigned cPDEs = X86_PG_ENTRIES;
3648	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3649	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3650	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3651	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3652	# else
3653	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3654	# endif
3655	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3656	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3657	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3658	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3659	# endif
3660	if (cb != ~(RTGCPTR)0)
3661	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3662
3663	/** @todo call the other two PGMAssert() functions. /
3664
3665	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3666	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3667
3668	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3669	{
3670	PPGMPOOLPAGE pShwPdpt = NULL;
3671	PX86PML4E pPml4eSrc;
3672	PX86PML4E pPml4eDst;
3673	RTGCPHYS GCPhysPdptSrc;
3674
3675	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3676	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3677
3678	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3679	if (!pPml4eDst->n.u1Present)
3680	{
3681	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3682	continue;
3683	}
3684
3685	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3686	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3687
3688	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3689	{
3690	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3691	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3692	cErrors++;
3693	continue;
3694	}
3695
3696	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3697	{
3698	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3699	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3700	cErrors++;
3701	continue;
3702	}
3703
3704	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3705	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3706	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3707	{
3708	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3709	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3710	cErrors++;
3711	continue;
3712	}
3713	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3714	{
3715	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3716
3717	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3718	/*
3719	* Check the PDPTEs too.
3720	*/
3721	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3722
3723	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3724	{
3725	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3726	PPGMPOOLPAGE pShwPde = NULL;
3727	PX86PDPE pPdpeDst;
3728	RTGCPHYS GCPhysPdeSrc;
3729	# if PGM_GST_TYPE == PGM_TYPE_PAE
3730	X86PDPE PdpeSrc;
3731	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3732	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3733	# else
3734	PX86PML4E pPml4eSrcIgn;
3735	X86PDPE PdpeSrc;
3736	PX86PDPT pPdptDst;
3737	PX86PDPAE pPDDst;
3738	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3739
3740	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3741	if (rc != VINF_SUCCESS)
3742	{
3743	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3744	GCPtr += 512 * _2M;
3745	continue; /* next PDPTE */
3746	}
3747	Assert(pPDDst);
3748	# endif
3749	Assert(iPDSrc == 0);
3750
3751	pPdpeDst = &pPdptDst->a[iPdpt];
3752
3753	if (!pPdpeDst->n.u1Present)
3754	{
3755	GCPtr += 512 * _2M;
3756	continue; /* next PDPTE */
3757	}
3758
3759	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3760	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3761
3762	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3763	{
3764	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3765	GCPtr += 512 * _2M;
3766	cErrors++;
3767	continue;
3768	}
3769
3770	if (GCPhysPdeSrc != pShwPde->GCPhys)
3771	{
3772	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3773	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3774	# else
3775	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3776	# endif
3777	GCPtr += 512 * _2M;
3778	cErrors++;
3779	continue;
3780	}
3781
3782	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3783	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3784	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3785	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3786	{
3787	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3788	GCPtr += 512 * _2M;
3789	cErrors++;
3790	continue;
3791	}
3792	# endif
3793
3794	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3795	{
3796	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3797	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3798	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3799	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3800	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3801	# endif
3802	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3803	/*
3804	* Iterate the shadow page directory.
3805	*/
3806	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3807	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3808
3809	for (;
3810	iPDDst < cPDEs;
3811	iPDDst++, GCPtr += cIncrement)
3812	{
3813	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3814	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3815	# else
3816	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3817	# endif
3818	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3819	{
3820	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3821	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3822	{
3823	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3824	cErrors++;
3825	continue;
3826	}
3827	}
3828	else if ( (PdeDst.u & X86_PDE_P)
3829	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3830	)
3831	{
3832	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3833	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3834	if (!pPoolPage)
3835	{
3836	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3837	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3838	cErrors++;
3839	continue;
3840	}
3841	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3842
3843	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3844	{
3845	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3846	GCPtr, (uint64_t)PdeDst.u));
3847	cErrors++;
3848	}
3849
3850	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3851	{
3852	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3853	GCPtr, (uint64_t)PdeDst.u));
3854	cErrors++;
3855	}
3856
3857	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3858	if (!PdeSrc.n.u1Present)
3859	{
3860	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3861	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3862	cErrors++;
3863	continue;
3864	}
3865
3866	if ( !PdeSrc.b.u1Size
3867	\|\| !fBigPagesSupported)
3868	{
3869	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3870	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3871	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3872	# endif
3873	}
3874	else
3875	{
3876	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3877	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3878	{
3879	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3880	GCPtr, (uint64_t)PdeSrc.u));
3881	cErrors++;
3882	continue;
3883	}
3884	# endif
3885	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3886	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3887	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3888	# endif
3889	}
3890
3891	if ( pPoolPage->enmKind
3892	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3893	{
3894	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3895	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3896	cErrors++;
3897	}
3898
3899	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3900	if (!pPhysPage)
3901	{
3902	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3903	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3904	cErrors++;
3905	continue;
3906	}
3907
3908	if (GCPhysGst != pPoolPage->GCPhys)
3909	{
3910	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3911	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3912	cErrors++;
3913	continue;
3914	}
3915
3916	if ( !PdeSrc.b.u1Size
3917	\|\| !fBigPagesSupported)
3918	{
3919	/*
3920	* Page Table.
3921	*/
3922	const GSTPT *pPTSrc;
3923	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3924	if (RT_FAILURE(rc))
3925	{
3926	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3927	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3928	cErrors++;
3929	continue;
3930	}
3931	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3932	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3933	{
3934	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3935	// (This problem will go away when/if we shadow multiple CR3s.)
3936	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3937	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3938	cErrors++;
3939	continue;
3940	}
3941	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3942	{
3943	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3944	GCPtr, (uint64_t)PdeDst.u));
3945	cErrors++;
3946	continue;
3947	}
3948
3949	/* iterate the page table. */
3950	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3951	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3952	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3953	# else
3954	const unsigned offPTSrc = 0;
3955	# endif
3956	for (unsigned iPT = 0, off = 0;
3957	iPT < RT_ELEMENTS(pPTDst->a);
3958	iPT++, off += PAGE_SIZE)
3959	{
3960	const SHWPTE PteDst = pPTDst->a[iPT];
3961
3962	/* skip not-present and dirty tracked entries. */
3963	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3964	continue;
3965	Assert(SHW_PTE_IS_P(PteDst));
3966
3967	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3968	if (!PteSrc.n.u1Present)
3969	{
3970	# ifdef IN_RING3
3971	PGMAssertHandlerAndFlagsInSync(pVM);
3972	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3973	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3974	0, 0, UINT64_MAX, 99, NULL);
3975	# endif
3976	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3977	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3978	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3979	cErrors++;
3980	continue;
3981	}
3982
3983	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3984	# if 1 /** @todo sync accessed bit properly... */
3985	fIgnoreFlags \|= X86_PTE_A;
3986	# endif
3987
3988	/* match the physical addresses */
3989	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
3990	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
3991
3992	# ifdef IN_RING3
3993	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3994	if (RT_FAILURE(rc))
3995	{
3996	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
3997	{
3998	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3999	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4000	cErrors++;
4001	continue;
4002	}
4003	}
4004	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4005	{
4006	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4007	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4008	cErrors++;
4009	continue;
4010	}
4011	# endif
4012
4013	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4014	if (!pPhysPage)
4015	{
4016	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4017	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4018	{
4019	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4020	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4021	cErrors++;
4022	continue;
4023	}
4024	# endif
4025	if (SHW_PTE_IS_RW(PteDst))
4026	{
4027	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4028	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4029	cErrors++;
4030	}
4031	fIgnoreFlags \|= X86_PTE_RW;
4032	}
4033	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4034	{
4035	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4036	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4037	cErrors++;
4038	continue;
4039	}
4040
4041	/* flags */
4042	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4043	{
4044	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4045	{
4046	if (SHW_PTE_IS_RW(PteDst))
4047	{
4048	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4049	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4050	cErrors++;
4051	continue;
4052	}
4053	fIgnoreFlags \|= X86_PTE_RW;
4054	}
4055	else
4056	{
4057	if ( SHW_PTE_IS_P(PteDst)
4058	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4059	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4060	# endif
4061	)
4062	{
4063	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4064	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4065	cErrors++;
4066	continue;
4067	}
4068	fIgnoreFlags \|= X86_PTE_P;
4069	}
4070	}
4071	else
4072	{
4073	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4074	{
4075	if (SHW_PTE_IS_RW(PteDst))
4076	{
4077	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4078	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4079	cErrors++;
4080	continue;
4081	}
4082	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4083	{
4084	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4085	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4086	cErrors++;
4087	continue;
4088	}
4089	if (SHW_PTE_IS_D(PteDst))
4090	{
4091	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4092	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4093	cErrors++;
4094	}
4095	# if 0 /** @todo sync access bit properly... */
4096	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4097	{
4098	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4100	cErrors++;
4101	}
4102	fIgnoreFlags \|= X86_PTE_RW;
4103	# else
4104	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4105	# endif
4106	}
4107	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4108	{
4109	/* access bit emulation (not implemented). */
4110	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4111	{
4112	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4113	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4114	cErrors++;
4115	continue;
4116	}
4117	if (!SHW_PTE_IS_A(PteDst))
4118	{
4119	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4120	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4121	cErrors++;
4122	}
4123	fIgnoreFlags \|= X86_PTE_P;
4124	}
4125	# ifdef DEBUG_sandervl
4126	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4127	# endif
4128	}
4129
4130	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4131	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4132	)
4133	{
4134	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4135	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4136	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4137	cErrors++;
4138	continue;
4139	}
4140	} /* foreach PTE */
4141	}
4142	else
4143	{
4144	/*
4145	* Big Page.
4146	*/
4147	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4148	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4149	{
4150	if (PdeDst.n.u1Write)
4151	{
4152	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4153	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4154	cErrors++;
4155	continue;
4156	}
4157	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4158	{
4159	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4160	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4161	cErrors++;
4162	continue;
4163	}
4164	# if 0 /** @todo sync access bit properly... */
4165	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4166	{
4167	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4168	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4169	cErrors++;
4170	}
4171	fIgnoreFlags \|= X86_PTE_RW;
4172	# else
4173	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4174	# endif
4175	}
4176	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4177	{
4178	/* access bit emulation (not implemented). */
4179	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4180	{
4181	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4182	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4183	cErrors++;
4184	continue;
4185	}
4186	if (!PdeDst.n.u1Accessed)
4187	{
4188	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4189	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4190	cErrors++;
4191	}
4192	fIgnoreFlags \|= X86_PTE_P;
4193	}
4194
4195	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4196	{
4197	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4198	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4199	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4200	cErrors++;
4201	}
4202
4203	/* iterate the page table. */
4204	for (unsigned iPT = 0, off = 0;
4205	iPT < RT_ELEMENTS(pPTDst->a);
4206	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4207	{
4208	const SHWPTE PteDst = pPTDst->a[iPT];
4209
4210	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4211	{
4212	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4213	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4214	cErrors++;
4215	}
4216
4217	/* skip not-present entries. */
4218	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4219	continue;
4220
4221	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4222
4223	/* match the physical addresses */
4224	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4225
4226	# ifdef IN_RING3
4227	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4228	if (RT_FAILURE(rc))
4229	{
4230	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4231	{
4232	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4233	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4234	cErrors++;
4235	}
4236	}
4237	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4238	{
4239	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4240	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4241	cErrors++;
4242	continue;
4243	}
4244	# endif
4245	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4246	if (!pPhysPage)
4247	{
4248	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4249	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4250	{
4251	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4252	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4253	cErrors++;
4254	continue;
4255	}
4256	# endif
4257	if (SHW_PTE_IS_RW(PteDst))
4258	{
4259	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4260	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4261	cErrors++;
4262	}
4263	fIgnoreFlags \|= X86_PTE_RW;
4264	}
4265	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4266	{
4267	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4268	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4269	cErrors++;
4270	continue;
4271	}
4272
4273	/* flags */
4274	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4275	{
4276	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4277	{
4278	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4279	{
4280	if (SHW_PTE_IS_RW(PteDst))
4281	{
4282	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4283	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4284	cErrors++;
4285	continue;
4286	}
4287	fIgnoreFlags \|= X86_PTE_RW;
4288	}
4289	}
4290	else
4291	{
4292	if ( SHW_PTE_IS_P(PteDst)
4293	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4294	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4295	# endif
4296	)
4297	{
4298	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4299	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4300	cErrors++;
4301	continue;
4302	}
4303	fIgnoreFlags \|= X86_PTE_P;
4304	}
4305	}
4306
4307	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4308	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4309	)
4310	{
4311	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4312	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4313	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4314	cErrors++;
4315	continue;
4316	}
4317	} /* for each PTE */
4318	}
4319	}
4320	/* not present */
4321
4322	} /* for each PDE */
4323
4324	} /* for each PDPTE */
4325
4326	} /* for each PML4E */
4327
4328	# ifdef DEBUG
4329	if (cErrors)
4330	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4331	# endif
4332
4333	#endif /* GST == 32BIT, PAE or AMD64 */
4334	return cErrors;
4335
4336	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4337	}
4338	#endif /* VBOX_STRICT */
4339
4340
4341	/**
4342	* Sets up the CR3 for shadow paging
4343	*
4344	* @returns Strict VBox status code.
4345	* @retval VINF_SUCCESS.
4346	*
4347	* @param pVCpu The VMCPU handle.
4348	* @param GCPhysCR3 The physical address in the CR3 register.
4349	*/
4350	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4351	{
4352	PVM pVM = pVCpu->CTX_SUFF(pVM);
4353
4354	/* Update guest paging info. */
4355	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4356	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4357	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4358
4359	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4360
4361	/*
4362	* Map the page CR3 points at.
4363	*/
4364	RTHCPTR HCPtrGuestCR3;
4365	RTHCPHYS HCPhysGuestCR3;
4366	pgmLock(pVM);
4367	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4368	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4369	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4370	/** @todo this needs some reworking wrt. locking? */
4371	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4372	HCPtrGuestCR3 = NIL_RTHCPTR;
4373	int rc = VINF_SUCCESS;
4374	# else
4375	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4376	# endif
4377	pgmUnlock(pVM);
4378	if (RT_SUCCESS(rc))
4379	{
4380	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4381	if (RT_SUCCESS(rc))
4382	{
4383	# ifdef IN_RC
4384	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4385	# endif
4386	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4387	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4388	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4389	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4390	# endif
4391	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4392
4393	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4394	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4395	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4396	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4397	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4398	# endif
4399	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4400	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4401
4402	/*
4403	* Map the 4 PDs too.
4404	*/
4405	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4406	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4407	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4408	{
4409	if (pGuestPDPT->a[i].n.u1Present)
4410	{
4411	RTHCPTR HCPtr;
4412	RTHCPHYS HCPhys;
4413	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4414	pgmLock(pVM);
4415	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4416	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4417	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4418	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4419	HCPtr = NIL_RTHCPTR;
4420	int rc2 = VINF_SUCCESS;
4421	# else
4422	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4423	# endif
4424	pgmUnlock(pVM);
4425	if (RT_SUCCESS(rc2))
4426	{
4427	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4428	AssertRCReturn(rc, rc);
4429
4430	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4431	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4432	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4433	# endif
4434	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4435	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4436	# ifdef IN_RC
4437	PGM_INVL_PG(pVCpu, GCPtr);
4438	# endif
4439	continue;
4440	}
4441	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4442	}
4443
4444	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4445	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4446	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4447	# endif
4448	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4449	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4450	# ifdef IN_RC
4451	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4452	# endif
4453	}
4454
4455	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4456	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4457	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4458	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4459	# endif
4460	# endif
4461	}
4462	else
4463	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4464	}
4465	else
4466	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4467
4468	#else /* prot/real stub */
4469	int rc = VINF_SUCCESS;
4470	#endif
4471
4472	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4473	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4474	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4475	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4476	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4477	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4478
4479	Assert(!pVM->pgm.s.fNestedPaging);
4480
4481	/*
4482	* Update the shadow root page as well since that's not fixed.
4483	*/
4484	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4485	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4486	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4487	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4488	PPGMPOOLPAGE pNewShwPageCR3;
4489
4490	pgmLock(pVM);
4491
4492	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4493	if (pPool->cDirtyPages)
4494	pgmPoolResetDirtyPages(pVM);
4495	# endif
4496
4497	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4498	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4499	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4500	AssertFatalRC(rc);
4501	rc = VINF_SUCCESS;
4502
4503	# ifdef IN_RC
4504	/*
4505	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4506	* state will be inconsistent! Flush important things now while
4507	* we still can and then make sure there are no ring-3 calls.
4508	*/
4509	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4510	VMMRZCallRing3Disable(pVCpu);
4511	# endif
4512
4513	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4514	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4515	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4516	# ifdef IN_RING0
4517	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4518	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4519	# elif defined(IN_RC)
4520	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4521	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4522	# else
4523	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4524	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4525	# endif
4526
4527	# ifndef PGM_WITHOUT_MAPPINGS
4528	/*
4529	* Apply all hypervisor mappings to the new CR3.
4530	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4531	* make sure we check for conflicts in the new CR3 root.
4532	*/
4533	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4534	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4535	# endif
4536	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4537	AssertRCReturn(rc, rc);
4538	# endif
4539
4540	/* Set the current hypervisor CR3. */
4541	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4542	SELMShadowCR3Changed(pVM, pVCpu);
4543
4544	# ifdef IN_RC
4545	/* NOTE: The state is consistent again. */
4546	VMMRZCallRing3Enable(pVCpu);
4547	# endif
4548
4549	/* Clean up the old CR3 root. */
4550	if ( pOldShwPageCR3
4551	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4552	{
4553	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4554	# ifndef PGM_WITHOUT_MAPPINGS
4555	/* Remove the hypervisor mappings from the shadow page table. */
4556	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4557	# endif
4558	/* Mark the page as unlocked; allow flushing again. */
4559	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4560
4561	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4562	}
4563	pgmUnlock(pVM);
4564	# endif
4565
4566	return rc;
4567	}
4568
4569	/**
4570	* Unmaps the shadow CR3.
4571	*
4572	* @returns VBox status, no specials.
4573	* @param pVCpu The VMCPU handle.
4574	*/
4575	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4576	{
4577	LogFlow(("UnmapCR3\n"));
4578
4579	int rc = VINF_SUCCESS;
4580	PVM pVM = pVCpu->CTX_SUFF(pVM);
4581
4582	/*
4583	* Update guest paging info.
4584	*/
4585	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4586	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4587	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4588	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4589	# endif
4590	pVCpu->pgm.s.pGst32BitPdRC = 0;
4591
4592	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4593	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4594	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4595	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4596	# endif
4597	pVCpu->pgm.s.pGstPaePdptRC = 0;
4598	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4599	{
4600	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4601	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4602	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4603	# endif
4604	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4605	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4606	}
4607
4608	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4609	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4610	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4611	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4612	# endif
4613
4614	#else /* prot/real mode stub */
4615	/* nothing to do */
4616	#endif
4617
4618	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4619	/*
4620	* Update shadow paging info.
4621	*/
4622	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4623	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4624	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4625
4626	# if PGM_GST_TYPE != PGM_TYPE_REAL
4627	Assert(!pVM->pgm.s.fNestedPaging);
4628	# endif
4629
4630	pgmLock(pVM);
4631
4632	# ifndef PGM_WITHOUT_MAPPINGS
4633	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4634	/* Remove the hypervisor mappings from the shadow page table. */
4635	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4636	# endif
4637
4638	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4639	{
4640	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4641
4642	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4643
4644	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4645	if (pPool->cDirtyPages)
4646	pgmPoolResetDirtyPages(pVM);
4647	# endif
4648
4649	/* Mark the page as unlocked; allow flushing again. */
4650	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4651
4652	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4653	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4654	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4655	pVCpu->pgm.s.pShwPageCR3RC = 0;
4656	pVCpu->pgm.s.iShwUser = 0;
4657	pVCpu->pgm.s.iShwUserTable = 0;
4658	}
4659	pgmUnlock(pVM);
4660	# endif
4661	#endif /* !IN_RC*/
4662
4663	return rc;
4664	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 32410

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