PGMAllBth.h@ 32486

Last change on this file since 32486 was 32486, checked in by vboxsync, 14 years ago
Moved logging and stat
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1	/* $Id: PGMAllBth.h 32486 2010-09-14 14:21:25Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	PGM_INVL_PG(pVCpu, pvFault);
561	return rc; /* Restart with the corrected entry. */
562	}
563	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
564
565	/*
566	* Fetch the guest PDE, PDPE and PML4E.
567	*/
568	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
569	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
570	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
571
572	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
573	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
574	PX86PDPAE pPDDst;
575	# if PGM_GST_TYPE == PGM_TYPE_PAE
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
577	# else
578	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
579	# endif
580	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
583	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
586	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
587	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
588	# else
589	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
590	# endif
591	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
592
593	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
594	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
595	PEPTPD pPDDst;
596	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
597	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
598	# endif
599	Assert(pPDDst);
600
601	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
602	/*
603	* Dirty page handling.
604	*
605	* If we successfully correct the write protection fault due to dirty bit
606	* tracking, then return immediately.
607	*/
608	if (uErr & X86_TRAP_PF_RW) /* write fault? */
609	{
610	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
612	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
613	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
614	{
615	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
616	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
617	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
618	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
619	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
620	return VINF_SUCCESS;
621	}
622	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
623	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
624	}
625
626	# if 0 /* rarely useful; leave for debugging. */
627	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
628	# endif
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630
631	/*
632	* A common case is the not-present error caused by lazy page table syncing.
633	*
634	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
635	* here so we can safely assume that the shadow PT is present when calling
636	* SyncPage later.
637	*
638	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
639	* of mapping conflict and defer to SyncCR3 in R3.
640	* (Again, we do NOT support access handlers for non-present guest pages.)
641	*
642	*/
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
644	Assert(GstWalk.Pde.n.u1Present);
645	# endif
646	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
647	&& !pPDDst->a[iPDDst].n.u1Present)
648	{
649	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
650	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
651	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
652	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
653	# else
654	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
655	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
656	# endif
657	if (RT_SUCCESS(rc))
658	return rc;
659	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
660	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
661	return VINF_PGM_SYNC_CR3;
662	}
663
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
665	/*
666	* Check if this address is within any of our mappings.
667	*
668	* This is very fast and it's gonna save us a bit of effort below and prevent
669	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
670	* (BTW, it's impossible to have physical access handlers in a mapping.)
671	*/
672	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
673	{
674	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
675	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
676	{
677	if (pvFault < pMapping->GCPtr)
678	break;
679	if (pvFault - pMapping->GCPtr < pMapping->cb)
680	{
681	/*
682	* The first thing we check is if we've got an undetected conflict.
683	*/
684	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
685	{
686	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
687	while (iPT-- > 0)
688	if (GstWalk.pPde[iPT].n.u1Present)
689	{
690	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
691	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
692	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
693	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
694	return VINF_PGM_SYNC_CR3;
695	}
696	}
697
698	/*
699	* Check if the fault address is in a virtual page access handler range.
700	*/
701	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
702	if ( pCur
703	&& pvFault - pCur->Core.Key < pCur->cb
704	&& uErr & X86_TRAP_PF_RW)
705	{
706	# ifdef IN_RC
707	STAM_PROFILE_START(&pCur->Stat, h);
708	pgmUnlock(pVM);
709	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
710	pgmLock(pVM);
711	STAM_PROFILE_STOP(&pCur->Stat, h);
712	# else
713	AssertFailed();
714	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
715	# endif
716	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
717	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
718	return rc;
719	}
720
721	/*
722	* Pretend we're not here and let the guest handle the trap.
723	*/
724	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
725	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
726	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return VINF_EM_RAW_GUEST_TRAP;
729	}
730	}
731	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
732	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
733
734	/*
735	* Check if this fault address is flagged for special treatment,
736	* which means we'll have to figure out the physical address and
737	* check flags associated with it.
738	*
739	* ASSUME that we can limit any special access handling to pages
740	* in page tables which the guest believes to be present.
741	*/
742	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
743	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# else
745	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
746	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
747	PPGMPAGE pPage;
748	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
749	if (RT_FAILURE(rc))
750	{
751	/*
752	* When the guest accesses invalid physical memory (e.g. probing
753	* of RAM or accessing a remapped MMIO range), then we'll fall
754	* back to the recompiler to emulate the instruction.
755	*/
756	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
757	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
758	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
759	return VINF_EM_RAW_EMULATE_INSTR;
760	}
761
762	/*
763	* Any handlers for this page?
764	*/
765	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
766	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
767	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
768	&GstWalk));
769	# else
770	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
771	# endif
772
773	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
774
775	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
776	if (uErr & X86_TRAP_PF_P)
777	{
778	/*
779	* The page isn't marked, but it might still be monitored by a virtual page access handler.
780	* (ASSUMES no temporary disabling of virtual handlers.)
781	*/
782	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
783	* we should correct both the shadow page table and physical memory flags, and not only check for
784	* accesses within the handler region but for access to pages with virtual handlers. */
785	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
786	if (pCur)
787	{
788	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
789	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
790	\|\| !(uErr & X86_TRAP_PF_P)
791	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
792	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
793
794	if ( pvFault - pCur->Core.Key < pCur->cb
795	&& ( uErr & X86_TRAP_PF_RW
796	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
797	{
798	# ifdef IN_RC
799	STAM_PROFILE_START(&pCur->Stat, h);
800	pgmUnlock(pVM);
801	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
802	pgmLock(pVM);
803	STAM_PROFILE_STOP(&pCur->Stat, h);
804	# else
805	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
806	# endif
807	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
808	return rc;
809	}
810	}
811	}
812	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
813
814	/*
815	* We are here only if page is present in Guest page tables and
816	* trap is not handled by our handlers.
817	*
818	* Check it for page out-of-sync situation.
819	*/
820	if (!(uErr & X86_TRAP_PF_P))
821	{
822	/*
823	* Page is not present in our page tables. Try to sync it!
824	*/
825	if (uErr & X86_TRAP_PF_US)
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
827	else /* supervisor */
828	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
829
830	if (PGM_PAGE_IS_BALLOONED(pPage))
831	{
832	/* Emulate reads from ballooned pages as they are not present in
833	our shadow page tables. (Required for e.g. Solaris guests; soft
834	ecc, random nr generator.) */
835	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
836	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
838	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
839	return rc;
840	}
841
842	# if defined(LOG_ENABLED) && !defined(IN_RING0)
843	RTGCPHYS GCPhys2;
844	uint64_t fPageGst2;
845	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
846	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
847	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
848	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
849	# else
850	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
851	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
852	# endif
853	# endif /* LOG_ENABLED */
854
855	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
856	if ( !GstWalk.Core.fEffectiveUS
857	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
858	{
859	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
860	if ( pvFault == (RTGCPTR)pRegFrame->eip
861	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
862	# ifdef CSAM_DETECT_NEW_CODE_PAGES
863	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
864	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
865	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
866	)
867	{
868	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
869	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
870	if (rc != VINF_SUCCESS)
871	{
872	/*
873	* CSAM needs to perform a job in ring 3.
874	*
875	* Sync the page before going to the host context; otherwise we'll end up in a loop if
876	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
877	*/
878	LogFlow(("CSAM ring 3 job\n"));
879	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
880	AssertRC(rc2);
881
882	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
883	return rc;
884	}
885	}
886	# ifdef CSAM_DETECT_NEW_CODE_PAGES
887	else if ( uErr == X86_TRAP_PF_RW
888	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
889	&& pRegFrame->ecx < 0x10000)
890	{
891	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
892	* to detect loading of new code pages.
893	*/
894
895	/*
896	* Decode the instruction.
897	*/
898	RTGCPTR PC;
899	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
900	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
901	if (rc == VINF_SUCCESS)
902	{
903	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
904	uint32_t cbOp;
905	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
906
907	/* For now we'll restrict this to rep movsw/d instructions */
908	if ( rc == VINF_SUCCESS
909	&& pDis->pCurInstr->opcode == OP_MOVSWD
910	&& (pDis->prefix & PREFIX_REP))
911	{
912	CSAMMarkPossibleCodePage(pVM, pvFault);
913	}
914	}
915	}
916	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
917
918	/*
919	* Mark this page as safe.
920	*/
921	/** @todo not correct for pages that contain both code and data!! */
922	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
923	CSAMMarkPage(pVM, pvFault, true);
924	}
925	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
926	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# else
929	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
930	# endif
931	if (RT_SUCCESS(rc))
932	{
933	/* The page was successfully synced, return to the guest. */
934	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
935	return VINF_SUCCESS;
936	}
937	}
938	else /* uErr & X86_TRAP_PF_P: */
939	{
940	/*
941	* Write protected pages are made writable when the guest makes the
942	* first write to it. This happens for pages that are shared, write
943	* monitored or not yet allocated.
944	*
945	* We may also end up here when CR0.WP=0 in the guest.
946	*
947	* Also, a side effect of not flushing global PDEs are out of sync
948	* pages due to physical monitored regions, that are no longer valid.
949	* Assume for now it only applies to the read/write flag.
950	*/
951	if (uErr & X86_TRAP_PF_RW)
952	{
953	/*
954	* Check if it is a read-only page.
955	*/
956	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
957	{
958	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
959	Assert(!PGM_PAGE_IS_ZERO(pPage));
960	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
961	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
962
963	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
964	if (rc != VINF_SUCCESS)
965	{
966	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
967	return rc;
968	}
969	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
970	return VINF_EM_NO_MEMORY;
971	}
972
973	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
974	/*
975	* Check to see if we need to emulate the instruction if CR0.WP=0.
976	*/
977	if ( !GstWalk.Core.fEffectiveRW
978	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
979	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
980	{
981	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
982	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
983	if (RT_SUCCESS(rc))
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
985	else
986	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
987	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
988	return rc;
989	}
990	# endif
991	/// @todo count the above case; else
992	if (uErr & X86_TRAP_PF_US)
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
994	else /* supervisor */
995	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
996
997	/*
998	* Sync the page.
999	*
1000	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1001	* page is not present, which is not true in this case.
1002	*/
1003	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1005	# else
1006	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1007	# endif
1008	if (RT_SUCCESS(rc))
1009	{
1010	/*
1011	* Page was successfully synced, return to guest but invalidate
1012	* the TLB first as the page is very likely to be in it.
1013	*/
1014	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1015	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1016	# else
1017	PGM_INVL_PG(pVCpu, pvFault);
1018	# endif
1019	# ifdef VBOX_STRICT
1020	RTGCPHYS GCPhys2;
1021	uint64_t fPageGst;
1022	if (!pVM->pgm.s.fNestedPaging)
1023	{
1024	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1025	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1026	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1027	}
1028	uint64_t fPageShw;
1029	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1030	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1031	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1032	# endif /* VBOX_STRICT */
1033	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1034	return VINF_SUCCESS;
1035	}
1036	}
1037	/** @todo else: why are we here? */
1038
1039	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1040	/*
1041	* Check for VMM page flags vs. Guest page flags consistency.
1042	* Currently only for debug purposes.
1043	*/
1044	if (RT_SUCCESS(rc))
1045	{
1046	/* Get guest page flags. */
1047	uint64_t fPageGst;
1048	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1049	if (RT_SUCCESS(rc))
1050	{
1051	uint64_t fPageShw;
1052	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1053
1054	/*
1055	* Compare page flags.
1056	* Note: we have AVL, A, D bits desynched.
1057	*/
1058	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1059	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1060	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1061	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1062	}
1063	else
1064	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1065	}
1066	else
1067	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1068	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1069	}
1070
1071
1072	/*
1073	* If we get here it is because something failed above, i.e. most like guru
1074	* meditiation time.
1075	*/
1076	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1077	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1078	return rc;
1079
1080	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1081	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1082	return VERR_INTERNAL_ERROR;
1083	# endif
1084	}
1085	#endif /* !IN_RING3 */
1086
1087
1088	/**
1089	* Emulation of the invlpg instruction.
1090	*
1091	*
1092	* @returns VBox status code.
1093	*
1094	* @param pVCpu The VMCPU handle.
1095	* @param GCPtrPage Page to invalidate.
1096	*
1097	* @remark ASSUMES that the guest is updating before invalidating. This order
1098	* isn't required by the CPU, so this is speculative and could cause
1099	* trouble.
1100	* @remark No TLB shootdown is done on any other VCPU as we assume that
1101	* invlpg emulation is the only reason for calling this function.
1102	* (The guest has to shoot down TLB entries on other CPUs itself)
1103	* Currently true, but keep in mind!
1104	*
1105	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1106	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1107	*/
1108	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1109	{
1110	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1111	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1112	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1113	int rc;
1114	PVM pVM = pVCpu->CTX_SUFF(pVM);
1115	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1116
1117	Assert(PGMIsLockOwner(pVM));
1118
1119	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1120
1121	/*
1122	* Get the shadow PD entry and skip out if this PD isn't present.
1123	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1124	*/
1125	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1126	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1127	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1128
1129	/* Fetch the pgm pool shadow descriptor. */
1130	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1131	Assert(pShwPde);
1132
1133	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1134	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1135	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1136
1137	/* If the shadow PDPE isn't present, then skip the invalidate. */
1138	if (!pPdptDst->a[iPdpt].n.u1Present)
1139	{
1140	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1141	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1142	return VINF_SUCCESS;
1143	}
1144
1145	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1146	PPGMPOOLPAGE pShwPde = NULL;
1147	PX86PDPAE pPDDst;
1148
1149	/* Fetch the pgm pool shadow descriptor. */
1150	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1151	AssertRCSuccessReturn(rc, rc);
1152	Assert(pShwPde);
1153
1154	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1155	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1156
1157	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1158	/* PML4 */
1159	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1160	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1161	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1162	PX86PDPAE pPDDst;
1163	PX86PDPT pPdptDst;
1164	PX86PML4E pPml4eDst;
1165	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1166	if (rc != VINF_SUCCESS)
1167	{
1168	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1169	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1170	return VINF_SUCCESS;
1171	}
1172	Assert(pPDDst);
1173
1174	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1175	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1176
1177	if (!pPdpeDst->n.u1Present)
1178	{
1179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1180	return VINF_SUCCESS;
1181	}
1182
1183	/* Fetch the pgm pool shadow descriptor. */
1184	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1185	Assert(pShwPde);
1186
1187	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1188
1189	const SHWPDE PdeDst = *pPdeDst;
1190	if (!PdeDst.n.u1Present)
1191	{
1192	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1193	return VINF_SUCCESS;
1194	}
1195
1196	/*
1197	* Get the guest PD entry and calc big page.
1198	*/
1199	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1200	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1201	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1202	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1203	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1204	unsigned iPDSrc = 0;
1205	# if PGM_GST_TYPE == PGM_TYPE_PAE
1206	X86PDPE PdpeSrcIgn;
1207	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1208	# else /* AMD64 */
1209	PX86PML4E pPml4eSrcIgn;
1210	X86PDPE PdpeSrcIgn;
1211	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1212	# endif
1213	GSTPDE PdeSrc;
1214
1215	if (pPDSrc)
1216	PdeSrc = pPDSrc->a[iPDSrc];
1217	else
1218	PdeSrc.u = 0;
1219	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1220	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1221
1222	# ifdef IN_RING3
1223	/*
1224	* If a CR3 Sync is pending we may ignore the invalidate page operation
1225	* depending on the kind of sync and if it's a global page or not.
1226	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1227	*/
1228	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1229	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1230	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1231	&& fIsBigPage
1232	&& PdeSrc.b.u1Global
1233	)
1234	)
1235	# else
1236	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1237	# endif
1238	{
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1240	return VINF_SUCCESS;
1241	}
1242	# endif /* IN_RING3 */
1243
1244	/*
1245	* Deal with the Guest PDE.
1246	*/
1247	rc = VINF_SUCCESS;
1248	if (PdeSrc.n.u1Present)
1249	{
1250	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1251	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1252	# ifndef PGM_WITHOUT_MAPPING
1253	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1254	{
1255	/*
1256	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1257	*/
1258	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1259	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1260	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1261	}
1262	else
1263	# endif /* !PGM_WITHOUT_MAPPING */
1264	if (!fIsBigPage)
1265	{
1266	/*
1267	* 4KB - page.
1268	*/
1269	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1270	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1271
1272	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1273	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1274	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1275	# endif
1276	if (pShwPage->GCPhys == GCPhys)
1277	{
1278	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
1279	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1280	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1281	if (pPT->a[iPTEDst].n.u1Present)
1282	{
1283	/* This is very unlikely with caching/monitoring enabled. */
1284	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK, iPTEDst);
1285	ASMAtomicWriteSize(&pPT->a[iPTEDst], 0);
1286	}
1287	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1288	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1289	if (RT_SUCCESS(rc))
1290	rc = VINF_SUCCESS;
1291	# endif
1292	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1293	PGM_INVL_PG(pVCpu, GCPtrPage);
1294	}
1295	else
1296	{
1297	/*
1298	* The page table address changed.
1299	*/
1300	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1301	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1302	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1303	ASMAtomicWriteSize(pPdeDst, 0);
1304	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1305	PGM_INVL_VCPU_TLBS(pVCpu);
1306	}
1307	}
1308	else
1309	{
1310	/*
1311	* 2/4MB - page.
1312	*/
1313	/* Before freeing the page, check if anything really changed. */
1314	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1315	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1316	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1317	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1318	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1319	# endif
1320	if ( pShwPage->GCPhys == GCPhys
1321	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1322	{
1323	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1324	/** @todo This test is wrong as it cannot check the G bit!
1325	* FIXME */
1326	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1327	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1328	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1329	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1330	{
1331	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1332	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1333	return VINF_SUCCESS;
1334	}
1335	}
1336
1337	/*
1338	* Ok, the page table is present and it's been changed in the guest.
1339	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1340	* We could do this for some flushes in GC too, but we need an algorithm for
1341	* deciding which 4MB pages containing code likely to be executed very soon.
1342	*/
1343	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1344	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1345	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1346	ASMAtomicWriteSize(pPdeDst, 0);
1347	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1348	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1349	}
1350	}
1351	else
1352	{
1353	/*
1354	* Page directory is not present, mark shadow PDE not present.
1355	*/
1356	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1357	{
1358	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1359	ASMAtomicWriteSize(pPdeDst, 0);
1360	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1361	PGM_INVL_PG(pVCpu, GCPtrPage);
1362	}
1363	else
1364	{
1365	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1366	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1367	}
1368	}
1369	return rc;
1370
1371	#else /* guest real and protected mode */
1372	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1373	return VINF_SUCCESS;
1374	#endif
1375	}
1376
1377
1378	/**
1379	* Update the tracking of shadowed pages.
1380	*
1381	* @param pVCpu The VMCPU handle.
1382	* @param pShwPage The shadow page.
1383	* @param HCPhys The physical page we is being dereferenced.
1384	* @param iPte Shadow PTE index
1385	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1386	*/
1387	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte, RTGCPHYS GCPhysPage)
1388	{
1389	PVM pVM = pVCpu->CTX_SUFF(pVM);
1390
1391	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1392	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1393	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1394
1395	/* Use the hint we retrieved from the cached guest PT. */
1396	if (pShwPage->fDirty)
1397	{
1398	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1399
1400	Assert(pShwPage->cPresent);
1401	Assert(pPool->cPresent);
1402	pShwPage->cPresent--;
1403	pPool->cPresent--;
1404
1405	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysPage);
1406	AssertRelease(pPhysPage);
1407	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1408	return;
1409	}
1410	# endif
1411
1412	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1413	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1414
1415	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1416	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1417	* 2. write protect all shadowed pages. I.e. implement caching.
1418	*/
1419	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1420
1421	/*
1422	* Find the guest address.
1423	*/
1424	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1425	pRam;
1426	pRam = pRam->CTX_SUFF(pNext))
1427	{
1428	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1429	while (iPage-- > 0)
1430	{
1431	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1432	{
1433	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1434
1435	Assert(pShwPage->cPresent);
1436	Assert(pPool->cPresent);
1437	pShwPage->cPresent--;
1438	pPool->cPresent--;
1439
1440	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1441	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1442	return;
1443	}
1444	}
1445	}
1446
1447	for (;;)
1448	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1449	}
1450
1451
1452	/**
1453	* Update the tracking of shadowed pages.
1454	*
1455	* @param pVCpu The VMCPU handle.
1456	* @param pShwPage The shadow page.
1457	* @param u16 The top 16-bit of the pPage->HCPhys.
1458	* @param pPage Pointer to the guest page. this will be modified.
1459	* @param iPTDst The index into the shadow table.
1460	*/
1461	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1462	{
1463	PVM pVM = pVCpu->CTX_SUFF(pVM);
1464
1465	/*
1466	* Just deal with the simple first time here.
1467	*/
1468	if (!u16)
1469	{
1470	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1471	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1472	/* Save the page table index. */
1473	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1474	}
1475	else
1476	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1477
1478	/* write back */
1479	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1480	PGM_PAGE_SET_TRACKING(pPage, u16);
1481
1482	/* update statistics. */
1483	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1484	pShwPage->cPresent++;
1485	if (pShwPage->iFirstPresent > iPTDst)
1486	pShwPage->iFirstPresent = iPTDst;
1487	}
1488
1489
1490	/**
1491	* Modifies a shadow PTE to account for access handlers.
1492	*
1493	* @param pVM The VM handle.
1494	* @param pPage The page in question.
1495	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1496	* A (accessed) bit so it can be emulated correctly.
1497	* @param pPteDst The shadow PTE (output). This is temporary storage and
1498	* does not need to be set atomically.
1499	*/
1500	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1501	{
1502	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1503	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1504	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1505	{
1506	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1507	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1508	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1509	pPteDst->n.u1Present = 1;
1510	pPteDst->n.u1Execute = 1;
1511	pPteDst->n.u1IgnorePAT = 1;
1512	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1513	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1514	#else
1515	if (fPteSrc & X86_PTE_A)
1516	{
1517	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1518	SHW_PTE_SET_RO(*pPteDst);
1519	}
1520	else
1521	SHW_PTE_SET(*pPteDst, 0);
1522	#endif
1523	}
1524	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1525	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1526	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1527	&& ( BTH_IS_NP_ACTIVE(pVM)
1528	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1529	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1530	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1531	# endif
1532	)
1533	{
1534	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1535	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1536	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1537	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1538	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1539	pPteDst->n.u1Present = 0;
1540	pPteDst->n.u1Write = 1;
1541	pPteDst->n.u1Execute = 0;
1542	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1543	pPteDst->n.u3EMT = 7;
1544	# else
1545	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1546	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1547	# endif
1548	}
1549	# endif
1550	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1551	else
1552	{
1553	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1554	SHW_PTE_SET(*pPteDst, 0);
1555	}
1556	/** @todo count these kinds of entries. */
1557	}
1558
1559
1560	/**
1561	* Creates a 4K shadow page for a guest page.
1562	*
1563	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1564	* physical address. The PdeSrc argument only the flags are used. No page
1565	* structured will be mapped in this function.
1566	*
1567	* @param pVCpu The VMCPU handle.
1568	* @param pPteDst Destination page table entry.
1569	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1570	* Can safely assume that only the flags are being used.
1571	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1572	* @param pShwPage Pointer to the shadow page.
1573	* @param iPTDst The index into the shadow table.
1574	*
1575	* @remark Not used for 2/4MB pages!
1576	*/
1577	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1578	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1579	{
1580	PVM pVM = pVCpu->CTX_SUFF(pVM);
1581	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1582
1583	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1584	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1585	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1586
1587	if (pShwPage->fDirty)
1588	{
1589	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1590	PGSTPT pGstPT;
1591
1592	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirty].aPage[0];
1593	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1594	pGstPT->a[iPTDst].u = PteSrc.u;
1595	}
1596	#else
1597	Assert(!pShwPage->fDirty);
1598	#endif
1599
1600	if ( PteSrc.n.u1Present
1601	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1602	{
1603	/*
1604	* Find the ram range.
1605	*/
1606	PPGMPAGE pPage;
1607	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc), &pPage);
1608	if (RT_SUCCESS(rc))
1609	{
1610	/* Ignore ballooned pages.
1611	Don't return errors or use a fatal assert here as part of a
1612	shadow sync range might included ballooned pages. */
1613	if (PGM_PAGE_IS_BALLOONED(pPage))
1614	{
1615	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1616	return;
1617	}
1618
1619	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1620	/* Make the page writable if necessary. */
1621	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1622	&& ( PGM_PAGE_IS_ZERO(pPage)
1623	\|\| ( PteSrc.n.u1Write
1624	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1625	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1626	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1627	# endif
1628	# ifdef VBOX_WITH_PAGE_SHARING
1629	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1630	# endif
1631	)
1632	)
1633	)
1634	{
1635	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
1636	AssertRC(rc);
1637	}
1638	#endif
1639
1640	/*
1641	* Make page table entry.
1642	*/
1643	SHWPTE PteDst;
1644	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1645	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc), &PteDst);
1646	else
1647	{
1648	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1649	/*
1650	* If the page or page directory entry is not marked accessed,
1651	* we mark the page not present.
1652	*/
1653	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1654	{
1655	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1656	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1657	SHW_PTE_SET(PteDst, 0);
1658	}
1659	/*
1660	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1661	* when the page is modified.
1662	*/
1663	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1664	{
1665	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1666	SHW_PTE_SET(PteDst,
1667	GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc)
1668	\| PGM_PAGE_GET_HCPHYS(pPage)
1669	\| PGM_PTFLAGS_TRACK_DIRTY);
1670	SHW_PTE_SET_RO(PteDst);
1671	}
1672	else
1673	#endif
1674	{
1675	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1676	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1677	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1678	PteDst.n.u1Present = 1;
1679	PteDst.n.u1Write = 1;
1680	PteDst.n.u1Execute = 1;
1681	PteDst.n.u1IgnorePAT = 1;
1682	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1683	/* PteDst.n.u1Size = 0 */
1684	#else
1685	SHW_PTE_SET(PteDst, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1686	#endif
1687	}
1688
1689	/*
1690	* Make sure only allocated pages are mapped writable.
1691	*/
1692	if ( SHW_PTE_IS_P_RW(PteDst)
1693	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1694	{
1695	/* Still applies to shared pages. */
1696	Assert(!PGM_PAGE_IS_ZERO(pPage));
1697	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1698	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)GST_GET_PTE_GCPHYS(PteSrc), pPage, iPTDst));
1699	}
1700	}
1701
1702	/*
1703	* Keep user track up to date.
1704	*/
1705	if (SHW_PTE_IS_P(PteDst))
1706	{
1707	if (!SHW_PTE_IS_P(*pPteDst))
1708	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1709	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1710	{
1711	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1712	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1713	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1714	}
1715	}
1716	else if (SHW_PTE_IS_P(*pPteDst))
1717	{
1718	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1719	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1720	}
1721
1722	/*
1723	* Update statistics and commit the entry.
1724	*/
1725	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1726	if (!PteSrc.n.u1Global)
1727	pShwPage->fSeenNonGlobal = true;
1728	#endif
1729	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1730	return;
1731	}
1732
1733	/** @todo count these three different kinds. */
1734	Log2(("SyncPageWorker: invalid address in Pte\n"));
1735	}
1736	else if (!PteSrc.n.u1Present)
1737	Log2(("SyncPageWorker: page not present in Pte\n"));
1738	else
1739	Log2(("SyncPageWorker: invalid Pte\n"));
1740
1741	/*
1742	* The page is not present or the PTE is bad. Replace the shadow PTE by
1743	* an empty entry, making sure to keep the user tracking up to date.
1744	*/
1745	if (SHW_PTE_IS_P(*pPteDst))
1746	{
1747	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1748	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1749	}
1750	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1751	}
1752
1753
1754	/**
1755	* Syncs a guest OS page.
1756	*
1757	* There are no conflicts at this point, neither is there any need for
1758	* page table allocations.
1759	*
1760	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1761	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1762	*
1763	* @returns VBox status code.
1764	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1765	* @param pVCpu The VMCPU handle.
1766	* @param PdeSrc Page directory entry of the guest.
1767	* @param GCPtrPage Guest context page address.
1768	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1769	* @param uErr Fault error (X86_TRAP_PF_*).
1770	*/
1771	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1772	{
1773	PVM pVM = pVCpu->CTX_SUFF(pVM);
1774	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1775	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1776
1777	Assert(PGMIsLockOwner(pVM));
1778
1779	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1780	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1781	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1782	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1783	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1784
1785	/*
1786	* Assert preconditions.
1787	*/
1788	Assert(PdeSrc.n.u1Present);
1789	Assert(cPages);
1790	# if 0 /* rarely useful; leave for debugging. */
1791	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1792	# endif
1793
1794	/*
1795	* Get the shadow PDE, find the shadow page table in the pool.
1796	*/
1797	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1798	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1799	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1800
1801	/* Fetch the pgm pool shadow descriptor. */
1802	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1803	Assert(pShwPde);
1804
1805	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1806	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1807	PPGMPOOLPAGE pShwPde = NULL;
1808	PX86PDPAE pPDDst;
1809
1810	/* Fetch the pgm pool shadow descriptor. */
1811	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1812	AssertRCSuccessReturn(rc2, rc2);
1813	Assert(pShwPde);
1814
1815	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1816	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1817
1818	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1819	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1820	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1821	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1822	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1823
1824	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1825	AssertRCSuccessReturn(rc2, rc2);
1826	Assert(pPDDst && pPdptDst);
1827	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1828	# endif
1829	SHWPDE PdeDst = *pPdeDst;
1830
1831	/*
1832	* - In the guest SMP case we could have blocked while another VCPU reused
1833	* this page table.
1834	* - With W7-64 we may also take this path when the the A bit is cleared on
1835	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1836	* relevant TLB entries. If we're write monitoring any page mapped by
1837	* the modified entry, we may end up here with a "stale" TLB entry.
1838	*/
1839	if (!PdeDst.n.u1Present)
1840	{
1841	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1842	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1843	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1844	if (uErr & X86_TRAP_PF_P)
1845	PGM_INVL_PG(pVCpu, GCPtrPage);
1846	return VINF_SUCCESS; /* force the instruction to be executed again. */
1847	}
1848
1849	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1850	Assert(pShwPage);
1851
1852	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1853	/* Fetch the pgm pool shadow descriptor. */
1854	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1855	Assert(pShwPde);
1856	# endif
1857
1858	/*
1859	* Check that the page is present and that the shadow PDE isn't out of sync.
1860	*/
1861	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1862	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1863	RTGCPHYS GCPhys;
1864	if (!fBigPage)
1865	{
1866	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1867	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1868	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1869	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1870	# endif
1871	}
1872	else
1873	{
1874	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1875	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1876	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1877	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1878	# endif
1879	}
1880	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1881	if ( fPdeValid
1882	&& pShwPage->GCPhys == GCPhys
1883	&& PdeSrc.n.u1Present
1884	&& PdeSrc.n.u1User == PdeDst.n.u1User
1885	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1886	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1887	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1888	# endif
1889	)
1890	{
1891	/*
1892	* Check that the PDE is marked accessed already.
1893	* Since we set the accessed bit before getting here on a #PF, this
1894	* check is only meant for dealing with non-#PF'ing paths.
1895	*/
1896	if (PdeSrc.n.u1Accessed)
1897	{
1898	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1899	if (!fBigPage)
1900	{
1901	/*
1902	* 4KB Page - Map the guest page table.
1903	*/
1904	PGSTPT pPTSrc;
1905	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1906	if (RT_SUCCESS(rc))
1907	{
1908	# ifdef PGM_SYNC_N_PAGES
1909	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1910	if ( cPages > 1
1911	&& !(uErr & X86_TRAP_PF_P)
1912	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1913	{
1914	/*
1915	* This code path is currently only taken when the caller is PGMTrap0eHandler
1916	* for non-present pages!
1917	*
1918	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1919	* deal with locality.
1920	*/
1921	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1922	const unsigned iPTDstPage = iPTDst;
1923	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1924	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1925	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1926	# else
1927	const unsigned offPTSrc = 0;
1928	# endif
1929	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1930	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1931	iPTDst = 0;
1932	else
1933	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1934	for (; iPTDst < iPTDstEnd; iPTDst++)
1935	{
1936	if ( !SHW_PTE_IS_P(pPTDst->a[iPTDst])
1937	\|\| iPTDst == iPTDstPage) /* always sync GCPtrPage */
1938	{
1939	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1940	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1941	NOREF(GCPtrCurPage);
1942	#ifndef IN_RING0
1943	/*
1944	* Assuming kernel code will be marked as supervisor - and not as user level
1945	* and executed using a conforming code selector - And marked as readonly.
1946	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1947	*/
1948	PPGMPAGE pPage;
1949	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1950	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1951	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1952	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1953	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1954	)
1955	#endif /* else: CSAM not active */
1956	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1957	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1958	GCPtrCurPage, PteSrc.n.u1Present,
1959	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1960	PteSrc.n.u1User & PdeSrc.n.u1User,
1961	(uint64_t)PteSrc.u,
1962	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1963	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1964	}
1965	}
1966	}
1967	else
1968	# endif /* PGM_SYNC_N_PAGES */
1969	{
1970	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1971	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1972	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1973	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1974	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1975	GCPtrPage, PteSrc.n.u1Present,
1976	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1977	PteSrc.n.u1User & PdeSrc.n.u1User,
1978	(uint64_t)PteSrc.u,
1979	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1980	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1981	}
1982	}
1983	else /* MMIO or invalid page: emulated in #PF handler. */
1984	{
1985	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1986	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1987	}
1988	}
1989	else
1990	{
1991	/*
1992	* 4/2MB page - lazy syncing shadow 4K pages.
1993	* (There are many causes of getting here, it's no longer only CSAM.)
1994	*/
1995	/* Calculate the GC physical address of this 4KB shadow page. */
1996	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1997	/* Find ram range. */
1998	PPGMPAGE pPage;
1999	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
2000	if (RT_SUCCESS(rc))
2001	{
2002	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2003
2004	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2005	/* Try to make the page writable if necessary. */
2006	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2007	&& ( PGM_PAGE_IS_ZERO(pPage)
2008	\|\| ( PdeSrc.n.u1Write
2009	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2010	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2011	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2012	# endif
2013	# ifdef VBOX_WITH_PAGE_SHARING
2014	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2015	# endif
2016	)
2017	)
2018	)
2019	{
2020	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2021	AssertRC(rc);
2022	}
2023	# endif
2024
2025	/*
2026	* Make shadow PTE entry.
2027	*/
2028	SHWPTE PteDst;
2029	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2030	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2031	else
2032	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2033
2034	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2035	if ( SHW_PTE_IS_P(PteDst)
2036	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2037	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2038
2039	/* Make sure only allocated pages are mapped writable. */
2040	if ( SHW_PTE_IS_P_RW(PteDst)
2041	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2042	{
2043	/* Still applies to shared pages. */
2044	Assert(!PGM_PAGE_IS_ZERO(pPage));
2045	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2046	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2047	}
2048
2049	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2050
2051	/*
2052	* If the page is not flagged as dirty and is writable, then make it read-only
2053	* at PD level, so we can set the dirty bit when the page is modified.
2054	*
2055	* ASSUMES that page access handlers are implemented on page table entry level.
2056	* Thus we will first catch the dirty access and set PDE.D and restart. If
2057	* there is an access handler, we'll trap again and let it work on the problem.
2058	*/
2059	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2060	* As for invlpg, it simply frees the whole shadow PT.
2061	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2062	if ( !PdeSrc.b.u1Dirty
2063	&& PdeSrc.b.u1Write)
2064	{
2065	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2066	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2067	PdeDst.n.u1Write = 0;
2068	}
2069	else
2070	{
2071	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2072	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2073	}
2074	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2075	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2076	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2077	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2078	}
2079	else
2080	{
2081	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2082	/** @todo must wipe the shadow page table entry in this
2083	* case. */
2084	}
2085	}
2086	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2087	return VINF_SUCCESS;
2088	}
2089
2090	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2091	}
2092	else if (fPdeValid)
2093	{
2094	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2095	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2096	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2097	}
2098	else
2099	{
2100	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2101	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2102	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2103	}
2104
2105	/*
2106	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2107	* Yea, I'm lazy.
2108	*/
2109	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2110	ASMAtomicWriteSize(pPdeDst, 0);
2111
2112	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2113	PGM_INVL_VCPU_TLBS(pVCpu);
2114	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2115
2116
2117	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2118	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2119	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2120	&& !defined(IN_RC)
2121
2122	# ifdef PGM_SYNC_N_PAGES
2123	/*
2124	* Get the shadow PDE, find the shadow page table in the pool.
2125	*/
2126	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2127	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2128
2129	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2130	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2131
2132	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2133	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2134	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2135	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2136	X86PDEPAE PdeDst;
2137	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2138
2139	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2140	AssertRCSuccessReturn(rc, rc);
2141	Assert(pPDDst && pPdptDst);
2142	PdeDst = pPDDst->a[iPDDst];
2143	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2144	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2145	PEPTPD pPDDst;
2146	EPTPDE PdeDst;
2147
2148	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2149	if (rc != VINF_SUCCESS)
2150	{
2151	AssertRC(rc);
2152	return rc;
2153	}
2154	Assert(pPDDst);
2155	PdeDst = pPDDst->a[iPDDst];
2156	# endif
2157	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2158	if (!PdeDst.n.u1Present)
2159	{
2160	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2161	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2162	return VINF_SUCCESS; /* force the instruction to be executed again. */
2163	}
2164
2165	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2166	if (PdeDst.n.u1Size)
2167	{
2168	Assert(pVM->pgm.s.fNestedPaging);
2169	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2170	return VINF_SUCCESS;
2171	}
2172
2173	/* Mask away the page offset. */
2174	GCPtrPage &= ~((RTGCPTR)0xfff);
2175
2176	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2177	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2178
2179	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2180	if ( cPages > 1
2181	&& !(uErr & X86_TRAP_PF_P)
2182	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2183	{
2184	/*
2185	* This code path is currently only taken when the caller is PGMTrap0eHandler
2186	* for non-present pages!
2187	*
2188	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2189	* deal with locality.
2190	*/
2191	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2192	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2193	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2194	iPTDst = 0;
2195	else
2196	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2197	for (; iPTDst < iPTDstEnd; iPTDst++)
2198	{
2199	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2200	{
2201	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2202	GSTPTE PteSrc;
2203
2204	/* Fake the page table entry */
2205	PteSrc.u = GCPtrCurPage;
2206	PteSrc.n.u1Present = 1;
2207	PteSrc.n.u1Dirty = 1;
2208	PteSrc.n.u1Accessed = 1;
2209	PteSrc.n.u1Write = 1;
2210	PteSrc.n.u1User = 1;
2211
2212	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2213	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2214	GCPtrCurPage, PteSrc.n.u1Present,
2215	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2216	PteSrc.n.u1User & PdeSrc.n.u1User,
2217	(uint64_t)PteSrc.u,
2218	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2219	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2220
2221	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2222	break;
2223	}
2224	else
2225	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2226	}
2227	}
2228	else
2229	# endif /* PGM_SYNC_N_PAGES */
2230	{
2231	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2232	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2233	GSTPTE PteSrc;
2234
2235	/* Fake the page table entry */
2236	PteSrc.u = GCPtrCurPage;
2237	PteSrc.n.u1Present = 1;
2238	PteSrc.n.u1Dirty = 1;
2239	PteSrc.n.u1Accessed = 1;
2240	PteSrc.n.u1Write = 1;
2241	PteSrc.n.u1User = 1;
2242	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2243
2244	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2245	GCPtrPage, PteSrc.n.u1Present,
2246	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2247	PteSrc.n.u1User & PdeSrc.n.u1User,
2248	(uint64_t)PteSrc.u,
2249	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2250	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2251	}
2252	return VINF_SUCCESS;
2253
2254	#else
2255	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2256	return VERR_INTERNAL_ERROR;
2257	#endif
2258	}
2259
2260
2261	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2262
2263	/**
2264	* CheckPageFault helper for returning a page fault indicating a non-present
2265	* (NP) entry in the page translation structures.
2266	*
2267	* @returns VINF_EM_RAW_GUEST_TRAP.
2268	* @param pVCpu The virtual CPU to operate on.
2269	* @param uErr The error code of the shadow fault. Corrections to
2270	* TRPM's copy will be made if necessary.
2271	* @param GCPtrPage For logging.
2272	* @param uPageFaultLevel For logging.
2273	*/
2274	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2275	{
2276	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2277	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2278	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2279	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2280	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2281
2282	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2283	return VINF_EM_RAW_GUEST_TRAP;
2284	}
2285
2286
2287	/**
2288	* CheckPageFault helper for returning a page fault indicating a reserved bit
2289	* (RSVD) error in the page translation structures.
2290	*
2291	* @returns VINF_EM_RAW_GUEST_TRAP.
2292	* @param pVCpu The virtual CPU to operate on.
2293	* @param uErr The error code of the shadow fault. Corrections to
2294	* TRPM's copy will be made if necessary.
2295	* @param GCPtrPage For logging.
2296	* @param uPageFaultLevel For logging.
2297	*/
2298	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2299	{
2300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2301	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2302	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2303
2304	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2305	return VINF_EM_RAW_GUEST_TRAP;
2306	}
2307
2308
2309	/**
2310	* CheckPageFault helper for returning a page protection fault (P).
2311	*
2312	* @returns VINF_EM_RAW_GUEST_TRAP.
2313	* @param pVCpu The virtual CPU to operate on.
2314	* @param uErr The error code of the shadow fault. Corrections to
2315	* TRPM's copy will be made if necessary.
2316	* @param GCPtrPage For logging.
2317	* @param uPageFaultLevel For logging.
2318	*/
2319	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2320	{
2321	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2322	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2323	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2324	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2325
2326	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2327	return VINF_EM_RAW_GUEST_TRAP;
2328	}
2329
2330
2331	/**
2332	* Handle dirty bit tracking faults.
2333	*
2334	* @returns VBox status code.
2335	* @param pVCpu The VMCPU handle.
2336	* @param uErr Page fault error code.
2337	* @param pPdeSrc Guest page directory entry.
2338	* @param pPdeDst Shadow page directory entry.
2339	* @param GCPtrPage Guest context page address.
2340	*/
2341	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2342	{
2343	PVM pVM = pVCpu->CTX_SUFF(pVM);
2344	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2345
2346	Assert(PGMIsLockOwner(pVM));
2347
2348	/*
2349	* Handle big page.
2350	*/
2351	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2352	{
2353	if ( pPdeDst->n.u1Present
2354	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2355	{
2356	SHWPDE PdeDst = *pPdeDst;
2357
2358	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2359	Assert(pPdeSrc->b.u1Write);
2360
2361	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2362	* fault again and take this path to only invalidate the entry (see below).
2363	*/
2364	PdeDst.n.u1Write = 1;
2365	PdeDst.n.u1Accessed = 1;
2366	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2367	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2368	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2369	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2370	}
2371
2372	# ifdef IN_RING0
2373	/* Check for stale TLB entry; only applies to the SMP guest case. */
2374	if ( pVM->cCpus > 1
2375	&& pPdeDst->n.u1Write
2376	&& pPdeDst->n.u1Accessed)
2377	{
2378	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2379	if (pShwPage)
2380	{
2381	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2382	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2383	if (SHW_PTE_IS_P_RW(*pPteDst))
2384	{
2385	/* Stale TLB entry. */
2386	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2387	PGM_INVL_PG(pVCpu, GCPtrPage);
2388	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2389	}
2390	}
2391	}
2392	# endif /* IN_RING0 */
2393	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2394	}
2395
2396	/*
2397	* Map the guest page table.
2398	*/
2399	PGSTPT pPTSrc;
2400	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2401	if (RT_FAILURE(rc))
2402	{
2403	AssertRC(rc);
2404	return rc;
2405	}
2406
2407	if (pPdeDst->n.u1Present)
2408	{
2409	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2410	const GSTPTE PteSrc = *pPteSrc;
2411
2412	#ifndef IN_RING0
2413	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2414	* Our individual shadow handlers will provide more information and force a fatal exit.
2415	*/
2416	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2417	{
2418	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2419	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2420	}
2421	#endif
2422	/*
2423	* Map shadow page table.
2424	*/
2425	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2426	if (pShwPage)
2427	{
2428	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2429	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2430	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2431	{
2432	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2433	{
2434	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2435	SHWPTE PteDst = *pPteDst;
2436
2437	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2438	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2439
2440	Assert(pPteSrc->n.u1Write);
2441
2442	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2443	* entry will not harm; write access will simply fault again and
2444	* take this path to only invalidate the entry.
2445	*/
2446	if (RT_LIKELY(pPage))
2447	{
2448	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2449	{
2450	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2451	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2452	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2453	SHW_PTE_SET_RO(PteDst);
2454	}
2455	else
2456	{
2457	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2458	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2459	{
2460	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2461	AssertRC(rc);
2462	}
2463	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2464	SHW_PTE_SET_RW(PteDst);
2465	else
2466	{
2467	/* Still applies to shared pages. */
2468	Assert(!PGM_PAGE_IS_ZERO(pPage));
2469	SHW_PTE_SET_RO(PteDst);
2470	}
2471	}
2472	}
2473	else
2474	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2475
2476	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2477	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2478	PGM_INVL_PG(pVCpu, GCPtrPage);
2479	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2480	}
2481
2482	# ifdef IN_RING0
2483	/* Check for stale TLB entry; only applies to the SMP guest case. */
2484	if ( pVM->cCpus > 1
2485	&& SHW_PTE_IS_RW(*pPteDst)
2486	&& SHW_PTE_IS_A(*pPteDst))
2487	{
2488	/* Stale TLB entry. */
2489	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2490	PGM_INVL_PG(pVCpu, GCPtrPage);
2491	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2492	}
2493	# endif
2494	}
2495	}
2496	else
2497	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2498	}
2499
2500	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2501	}
2502
2503	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2504
2505
2506	/**
2507	* Sync a shadow page table.
2508	*
2509	* The shadow page table is not present in the shadow PDE.
2510	*
2511	* Handles mapping conflicts.
2512	*
2513	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2514	* conflict), and Trap0eHandler.
2515	*
2516	* A precodition for this method is that the shadow PDE is not present. The
2517	* caller must take the PGM lock before checking this and continue to hold it
2518	* when calling this method.
2519	*
2520	* @returns VBox status code.
2521	* @param pVCpu The VMCPU handle.
2522	* @param iPD Page directory index.
2523	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2524	* Assume this is a temporary mapping.
2525	* @param GCPtrPage GC Pointer of the page that caused the fault
2526	*/
2527	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2528	{
2529	PVM pVM = pVCpu->CTX_SUFF(pVM);
2530	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2531
2532	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2533	#if 0 /* rarely useful; leave for debugging. */
2534	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2535	#endif
2536	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2537
2538	Assert(PGMIsLocked(pVM));
2539
2540	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2541	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2542	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2543	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2544	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2545
2546	int rc = VINF_SUCCESS;
2547
2548	/*
2549	* Some input validation first.
2550	*/
2551	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2552
2553	/*
2554	* Get the relevant shadow PDE entry.
2555	*/
2556	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2557	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2558	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2559
2560	/* Fetch the pgm pool shadow descriptor. */
2561	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2562	Assert(pShwPde);
2563
2564	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2565	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2566	PPGMPOOLPAGE pShwPde = NULL;
2567	PX86PDPAE pPDDst;
2568	PSHWPDE pPdeDst;
2569
2570	/* Fetch the pgm pool shadow descriptor. */
2571	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2572	AssertRCSuccessReturn(rc, rc);
2573	Assert(pShwPde);
2574
2575	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2576	pPdeDst = &pPDDst->a[iPDDst];
2577
2578	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2579	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2580	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2581	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2582	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2583	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2584	AssertRCSuccessReturn(rc, rc);
2585	Assert(pPDDst);
2586	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2587	# endif
2588	SHWPDE PdeDst = *pPdeDst;
2589
2590	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2591	/* Fetch the pgm pool shadow descriptor. */
2592	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2593	Assert(pShwPde);
2594	# endif
2595
2596	# ifndef PGM_WITHOUT_MAPPINGS
2597	/*
2598	* Check for conflicts.
2599	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2600	* R3: Simply resolve the conflict.
2601	*/
2602	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2603	{
2604	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2605	# ifndef IN_RING3
2606	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2607	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2608	return VERR_ADDRESS_CONFLICT;
2609
2610	# else /* IN_RING3 */
2611	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2612	Assert(pMapping);
2613	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2614	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2615	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2616	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2617	# else
2618	AssertFailed(); /* can't happen for amd64 */
2619	# endif
2620	if (RT_FAILURE(rc))
2621	{
2622	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2623	return rc;
2624	}
2625	PdeDst = *pPdeDst;
2626	# endif /* IN_RING3 */
2627	}
2628	# endif /* !PGM_WITHOUT_MAPPINGS */
2629	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2630
2631	/*
2632	* Sync the page directory entry.
2633	*/
2634	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2635	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2636	if ( PdeSrc.n.u1Present
2637	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2638	{
2639	/*
2640	* Allocate & map the page table.
2641	*/
2642	PSHWPT pPTDst;
2643	PPGMPOOLPAGE pShwPage;
2644	RTGCPHYS GCPhys;
2645	if (fPageTable)
2646	{
2647	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2648	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2649	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2650	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2651	# endif
2652	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2653	}
2654	else
2655	{
2656	PGMPOOLACCESS enmAccess;
2657	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2658	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2659	# else
2660	const bool fNoExecute = false;
2661	# endif
2662
2663	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2664	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2665	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2666	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2667	# endif
2668	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2669	if (PdeSrc.n.u1User)
2670	{
2671	if (PdeSrc.n.u1Write)
2672	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2673	else
2674	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2675	}
2676	else
2677	{
2678	if (PdeSrc.n.u1Write)
2679	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2680	else
2681	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2682	}
2683	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2684	&pShwPage);
2685	}
2686	if (rc == VINF_SUCCESS)
2687	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2688	else if (rc == VINF_PGM_CACHED_PAGE)
2689	{
2690	/*
2691	* The PT was cached, just hook it up.
2692	*/
2693	if (fPageTable)
2694	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2695	else
2696	{
2697	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2698	/* (see explanation and assumptions further down.) */
2699	if ( !PdeSrc.b.u1Dirty
2700	&& PdeSrc.b.u1Write)
2701	{
2702	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2703	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2704	PdeDst.b.u1Write = 0;
2705	}
2706	}
2707	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2708	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2709	return VINF_SUCCESS;
2710	}
2711	else if (rc == VERR_PGM_POOL_FLUSHED)
2712	{
2713	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2714	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2715	return VINF_PGM_SYNC_CR3;
2716	}
2717	else
2718	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2719	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2720	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2721	* irrelevant at this point. */
2722	PdeDst.u &= X86_PDE_AVL_MASK;
2723	PdeDst.u \|= pShwPage->Core.Key;
2724
2725	/*
2726	* Page directory has been accessed (this is a fault situation, remember).
2727	*/
2728	/** @todo
2729	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2730	* fault situation. What's more, the Trap0eHandler has already set the
2731	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2732	* might need setting the accessed flag.
2733	*
2734	* The best idea is to leave this change to the caller and add an
2735	* assertion that it's set already. */
2736	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2737	if (fPageTable)
2738	{
2739	/*
2740	* Page table - 4KB.
2741	*
2742	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2743	*/
2744	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2745	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2746	PGSTPT pPTSrc;
2747	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2748	if (RT_SUCCESS(rc))
2749	{
2750	/*
2751	* Start by syncing the page directory entry so CSAM's TLB trick works.
2752	*/
2753	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2754	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2755	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2756	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2757
2758	/*
2759	* Directory/page user or supervisor privilege: (same goes for read/write)
2760	*
2761	* Directory Page Combined
2762	* U/S U/S U/S
2763	* 0 0 0
2764	* 0 1 0
2765	* 1 0 0
2766	* 1 1 1
2767	*
2768	* Simple AND operation. Table listed for completeness.
2769	*
2770	*/
2771	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2772	# ifdef PGM_SYNC_N_PAGES
2773	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2774	unsigned iPTDst = iPTBase;
2775	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2776	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2777	iPTDst = 0;
2778	else
2779	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2780	# else /* !PGM_SYNC_N_PAGES */
2781	unsigned iPTDst = 0;
2782	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2783	# endif /* !PGM_SYNC_N_PAGES */
2784	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2785	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2786	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2787	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2788	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2789	# else
2790	const unsigned offPTSrc = 0;
2791	# endif
2792	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2793	{
2794	const unsigned iPTSrc = iPTDst + offPTSrc;
2795	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2796
2797	if (PteSrc.n.u1Present)
2798	{
2799	# ifndef IN_RING0
2800	/*
2801	* Assuming kernel code will be marked as supervisor - and not as user level
2802	* and executed using a conforming code selector - And marked as readonly.
2803	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2804	*/
2805	PPGMPAGE pPage;
2806	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2807	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2808	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2809	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2810	)
2811	# endif
2812	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2813	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2814	GCPtrCur,
2815	PteSrc.n.u1Present,
2816	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2817	PteSrc.n.u1User & PdeSrc.n.u1User,
2818	(uint64_t)PteSrc.u,
2819	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2820	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2821	}
2822	/* else: the page table was cleared by the pool */
2823	} /* for PTEs */
2824	}
2825	}
2826	else
2827	{
2828	/*
2829	* Big page - 2/4MB.
2830	*
2831	* We'll walk the ram range list in parallel and optimize lookups.
2832	* We will only sync on shadow page table at a time.
2833	*/
2834	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2835
2836	/**
2837	* @todo It might be more efficient to sync only a part of the 4MB
2838	* page (similar to what we do for 4KB PDs).
2839	*/
2840
2841	/*
2842	* Start by syncing the page directory entry.
2843	*/
2844	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2845	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2846
2847	/*
2848	* If the page is not flagged as dirty and is writable, then make it read-only
2849	* at PD level, so we can set the dirty bit when the page is modified.
2850	*
2851	* ASSUMES that page access handlers are implemented on page table entry level.
2852	* Thus we will first catch the dirty access and set PDE.D and restart. If
2853	* there is an access handler, we'll trap again and let it work on the problem.
2854	*/
2855	/** @todo move the above stuff to a section in the PGM documentation. */
2856	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2857	if ( !PdeSrc.b.u1Dirty
2858	&& PdeSrc.b.u1Write)
2859	{
2860	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2861	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2862	PdeDst.b.u1Write = 0;
2863	}
2864	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2865	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2866
2867	/*
2868	* Fill the shadow page table.
2869	*/
2870	/* Get address and flags from the source PDE. */
2871	SHWPTE PteDstBase;
2872	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2873
2874	/* Loop thru the entries in the shadow PT. */
2875	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2876	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2877	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2878	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2879	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2880	unsigned iPTDst = 0;
2881	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2882	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2883	{
2884	/* Advance ram range list. */
2885	while (pRam && GCPhys > pRam->GCPhysLast)
2886	pRam = pRam->CTX_SUFF(pNext);
2887	if (pRam && GCPhys >= pRam->GCPhys)
2888	{
2889	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2890	do
2891	{
2892	/* Make shadow PTE. */
2893	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2894	SHWPTE PteDst;
2895
2896	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2897	/* Try to make the page writable if necessary. */
2898	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2899	&& ( PGM_PAGE_IS_ZERO(pPage)
2900	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2901	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2902	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2903	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2904	# endif
2905	# ifdef VBOX_WITH_PAGE_SHARING
2906	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2907	# endif
2908	&& !PGM_PAGE_IS_BALLOONED(pPage))
2909	)
2910	)
2911	{
2912	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2913	AssertRCReturn(rc, rc);
2914	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2915	break;
2916	}
2917	# endif
2918
2919	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2920	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2921	else if (PGM_PAGE_IS_BALLOONED(pPage))
2922	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2923	# ifndef IN_RING0
2924	/*
2925	* Assuming kernel code will be marked as supervisor and not as user level and executed
2926	* using a conforming code selector. Don't check for readonly, as that implies the whole
2927	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2928	*/
2929	else if ( !PdeSrc.n.u1User
2930	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2931	SHW_PTE_SET(PteDst, 0);
2932	# endif
2933	else
2934	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2935
2936	/* Only map writable pages writable. */
2937	if ( SHW_PTE_IS_P_RW(PteDst)
2938	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2939	{
2940	/* Still applies to shared pages. */
2941	Assert(!PGM_PAGE_IS_ZERO(pPage));
2942	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2943	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2944	}
2945
2946	if (SHW_PTE_IS_P(PteDst))
2947	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2948
2949	/* commit it (not atomic, new table) */
2950	pPTDst->a[iPTDst] = PteDst;
2951	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2952	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2953	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2954
2955	/* advance */
2956	GCPhys += PAGE_SIZE;
2957	iHCPage++;
2958	iPTDst++;
2959	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2960	&& GCPhys <= pRam->GCPhysLast);
2961	}
2962	else if (pRam)
2963	{
2964	Log(("Invalid pages at %RGp\n", GCPhys));
2965	do
2966	{
2967	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2968	GCPhys += PAGE_SIZE;
2969	iPTDst++;
2970	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2971	&& GCPhys < pRam->GCPhys);
2972	}
2973	else
2974	{
2975	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2976	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2977	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2978	}
2979	} /* while more PTEs */
2980	} /* 4KB / 4MB */
2981	}
2982	else
2983	AssertRelease(!PdeDst.n.u1Present);
2984
2985	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2986	if (RT_FAILURE(rc))
2987	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2988	return rc;
2989
2990	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2991	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2992	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2993	&& !defined(IN_RC)
2994
2995	/*
2996	* Validate input a little bit.
2997	*/
2998	int rc = VINF_SUCCESS;
2999	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3000	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3001	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3002
3003	/* Fetch the pgm pool shadow descriptor. */
3004	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3005	Assert(pShwPde);
3006
3007	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3008	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3009	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3010	PX86PDPAE pPDDst;
3011	PSHWPDE pPdeDst;
3012
3013	/* Fetch the pgm pool shadow descriptor. */
3014	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3015	AssertRCSuccessReturn(rc, rc);
3016	Assert(pShwPde);
3017
3018	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3019	pPdeDst = &pPDDst->a[iPDDst];
3020
3021	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3022	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3023	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3024	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3025	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3026	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3027	AssertRCSuccessReturn(rc, rc);
3028	Assert(pPDDst);
3029	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3030
3031	/* Fetch the pgm pool shadow descriptor. */
3032	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3033	Assert(pShwPde);
3034
3035	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3036	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3037	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3038	PEPTPD pPDDst;
3039	PEPTPDPT pPdptDst;
3040
3041	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3042	if (rc != VINF_SUCCESS)
3043	{
3044	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3045	AssertRC(rc);
3046	return rc;
3047	}
3048	Assert(pPDDst);
3049	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3050
3051	/* Fetch the pgm pool shadow descriptor. */
3052	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3053	Assert(pShwPde);
3054	# endif
3055	SHWPDE PdeDst = *pPdeDst;
3056
3057	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3058	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3059
3060	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3061	if (BTH_IS_NP_ACTIVE(pVM))
3062	{
3063	PPGMPAGE pPage;
3064
3065	/* Check if we allocated a big page before for this 2 MB range. */
3066	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3067	if (RT_SUCCESS(rc))
3068	{
3069	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3070
3071	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3072	{
3073	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3074	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3075	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3076	}
3077	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3078	{
3079	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3080	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3081	if (RT_SUCCESS(rc))
3082	{
3083	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3084	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3085	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3086	}
3087	}
3088	else if (PGMIsUsingLargePages(pVM))
3089	{
3090	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3091	if (RT_SUCCESS(rc))
3092	{
3093	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3094	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3095	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3096	}
3097	else
3098	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3099	}
3100
3101	if (HCPhys != NIL_RTHCPHYS)
3102	{
3103	PdeDst.u &= X86_PDE_AVL_MASK;
3104	PdeDst.u \|= HCPhys;
3105	PdeDst.n.u1Present = 1;
3106	PdeDst.n.u1Write = 1;
3107	PdeDst.b.u1Size = 1;
3108	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3109	PdeDst.n.u1Execute = 1;
3110	PdeDst.b.u1IgnorePAT = 1;
3111	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3112	# else
3113	PdeDst.n.u1User = 1;
3114	# endif
3115	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3116
3117	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3118	/* Add a reference to the first page only. */
3119	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3120
3121	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3122	return VINF_SUCCESS;
3123	}
3124	}
3125	}
3126	# endif /* HC_ARCH_BITS == 64 */
3127
3128	GSTPDE PdeSrc;
3129	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3130	PdeSrc.n.u1Present = 1;
3131	PdeSrc.n.u1Write = 1;
3132	PdeSrc.n.u1Accessed = 1;
3133	PdeSrc.n.u1User = 1;
3134
3135	/*
3136	* Allocate & map the page table.
3137	*/
3138	PSHWPT pPTDst;
3139	PPGMPOOLPAGE pShwPage;
3140	RTGCPHYS GCPhys;
3141
3142	/* Virtual address = physical address */
3143	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3144	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3145
3146	if ( rc == VINF_SUCCESS
3147	\|\| rc == VINF_PGM_CACHED_PAGE)
3148	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3149	else
3150	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3151
3152	PdeDst.u &= X86_PDE_AVL_MASK;
3153	PdeDst.u \|= pShwPage->Core.Key;
3154	PdeDst.n.u1Present = 1;
3155	PdeDst.n.u1Write = 1;
3156	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3157	PdeDst.n.u1Execute = 1;
3158	# else
3159	PdeDst.n.u1User = 1;
3160	PdeDst.n.u1Accessed = 1;
3161	# endif
3162	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3163
3164	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3165	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3166	return rc;
3167
3168	#else
3169	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3170	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3171	return VERR_INTERNAL_ERROR;
3172	#endif
3173	}
3174
3175
3176
3177	/**
3178	* Prefetch a page/set of pages.
3179	*
3180	* Typically used to sync commonly used pages before entering raw mode
3181	* after a CR3 reload.
3182	*
3183	* @returns VBox status code.
3184	* @param pVCpu The VMCPU handle.
3185	* @param GCPtrPage Page to invalidate.
3186	*/
3187	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3188	{
3189	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3190	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3191	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3192	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3193	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3194	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3195	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3196
3197	/*
3198	* Check that all Guest levels thru the PDE are present, getting the
3199	* PD and PDE in the processes.
3200	*/
3201	int rc = VINF_SUCCESS;
3202	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3203	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3204	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3205	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3206	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3207	unsigned iPDSrc;
3208	X86PDPE PdpeSrc;
3209	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3210	if (!pPDSrc)
3211	return VINF_SUCCESS; /* not present */
3212	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3213	unsigned iPDSrc;
3214	PX86PML4E pPml4eSrc;
3215	X86PDPE PdpeSrc;
3216	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3217	if (!pPDSrc)
3218	return VINF_SUCCESS; /* not present */
3219	# endif
3220	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3221	# else
3222	PGSTPD pPDSrc = NULL;
3223	const unsigned iPDSrc = 0;
3224	GSTPDE PdeSrc;
3225
3226	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3227	PdeSrc.n.u1Present = 1;
3228	PdeSrc.n.u1Write = 1;
3229	PdeSrc.n.u1Accessed = 1;
3230	PdeSrc.n.u1User = 1;
3231	# endif
3232
3233	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3234	{
3235	PVM pVM = pVCpu->CTX_SUFF(pVM);
3236	pgmLock(pVM);
3237
3238	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3239	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3240	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3241	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3242	PX86PDPAE pPDDst;
3243	X86PDEPAE PdeDst;
3244	# if PGM_GST_TYPE != PGM_TYPE_PAE
3245	X86PDPE PdpeSrc;
3246
3247	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3248	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3249	# endif
3250	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3251	if (rc != VINF_SUCCESS)
3252	{
3253	pgmUnlock(pVM);
3254	AssertRC(rc);
3255	return rc;
3256	}
3257	Assert(pPDDst);
3258	PdeDst = pPDDst->a[iPDDst];
3259
3260	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3261	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3262	PX86PDPAE pPDDst;
3263	X86PDEPAE PdeDst;
3264
3265	# if PGM_GST_TYPE == PGM_TYPE_PROT
3266	/* AMD-V nested paging */
3267	X86PML4E Pml4eSrc;
3268	X86PDPE PdpeSrc;
3269	PX86PML4E pPml4eSrc = &Pml4eSrc;
3270
3271	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3272	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3273	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3274	# endif
3275
3276	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3277	if (rc != VINF_SUCCESS)
3278	{
3279	pgmUnlock(pVM);
3280	AssertRC(rc);
3281	return rc;
3282	}
3283	Assert(pPDDst);
3284	PdeDst = pPDDst->a[iPDDst];
3285	# endif
3286	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3287	{
3288	if (!PdeDst.n.u1Present)
3289	{
3290	/** @todo r=bird: This guy will set the A bit on the PDE,
3291	* probably harmless. */
3292	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3293	}
3294	else
3295	{
3296	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3297	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3298	* makes no sense to prefetch more than one page.
3299	*/
3300	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3301	if (RT_SUCCESS(rc))
3302	rc = VINF_SUCCESS;
3303	}
3304	}
3305	pgmUnlock(pVM);
3306	}
3307	return rc;
3308
3309	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3310	return VINF_SUCCESS; /* ignore */
3311	#else
3312	AssertCompile(0);
3313	#endif
3314	}
3315
3316
3317
3318
3319	/**
3320	* Syncs a page during a PGMVerifyAccess() call.
3321	*
3322	* @returns VBox status code (informational included).
3323	* @param pVCpu The VMCPU handle.
3324	* @param GCPtrPage The address of the page to sync.
3325	* @param fPage The effective guest page flags.
3326	* @param uErr The trap error code.
3327	* @remarks This will normally never be called on invalid guest page
3328	* translation entries.
3329	*/
3330	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3331	{
3332	PVM pVM = pVCpu->CTX_SUFF(pVM);
3333
3334	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3335
3336	Assert(!pVM->pgm.s.fNestedPaging);
3337	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3338	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3339	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3340	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3341	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3342	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3343	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3344
3345	# ifndef IN_RING0
3346	if (!(fPage & X86_PTE_US))
3347	{
3348	/*
3349	* Mark this page as safe.
3350	*/
3351	/** @todo not correct for pages that contain both code and data!! */
3352	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3353	CSAMMarkPage(pVM, GCPtrPage, true);
3354	}
3355	# endif
3356
3357	/*
3358	* Get guest PD and index.
3359	*/
3360	/** @todo Performance: We've done all this a jiffy ago in the
3361	* PGMGstGetPage call. */
3362	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3363	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3364	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3365	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3366
3367	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3368	unsigned iPDSrc = 0;
3369	X86PDPE PdpeSrc;
3370	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3371	if (RT_UNLIKELY(!pPDSrc))
3372	{
3373	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3374	return VINF_EM_RAW_GUEST_TRAP;
3375	}
3376
3377	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3378	unsigned iPDSrc = 0; /* shut up gcc */
3379	PX86PML4E pPml4eSrc = NULL; /* ditto */
3380	X86PDPE PdpeSrc;
3381	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3382	if (RT_UNLIKELY(!pPDSrc))
3383	{
3384	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3385	return VINF_EM_RAW_GUEST_TRAP;
3386	}
3387	# endif
3388
3389	# else /* !PGM_WITH_PAGING */
3390	PGSTPD pPDSrc = NULL;
3391	const unsigned iPDSrc = 0;
3392	# endif /* !PGM_WITH_PAGING */
3393	int rc = VINF_SUCCESS;
3394
3395	pgmLock(pVM);
3396
3397	/*
3398	* First check if the shadow pd is present.
3399	*/
3400	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3401	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3402
3403	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3404	PX86PDEPAE pPdeDst;
3405	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3406	PX86PDPAE pPDDst;
3407	# if PGM_GST_TYPE != PGM_TYPE_PAE
3408	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3409	X86PDPE PdpeSrc;
3410	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3411	# endif
3412	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3413	if (rc != VINF_SUCCESS)
3414	{
3415	pgmUnlock(pVM);
3416	AssertRC(rc);
3417	return rc;
3418	}
3419	Assert(pPDDst);
3420	pPdeDst = &pPDDst->a[iPDDst];
3421
3422	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3423	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3424	PX86PDPAE pPDDst;
3425	PX86PDEPAE pPdeDst;
3426
3427	# if PGM_GST_TYPE == PGM_TYPE_PROT
3428	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3429	X86PML4E Pml4eSrc;
3430	X86PDPE PdpeSrc;
3431	PX86PML4E pPml4eSrc = &Pml4eSrc;
3432	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3433	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3434	# endif
3435
3436	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3437	if (rc != VINF_SUCCESS)
3438	{
3439	pgmUnlock(pVM);
3440	AssertRC(rc);
3441	return rc;
3442	}
3443	Assert(pPDDst);
3444	pPdeDst = &pPDDst->a[iPDDst];
3445	# endif
3446
3447	if (!pPdeDst->n.u1Present)
3448	{
3449	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3450	if (rc != VINF_SUCCESS)
3451	{
3452	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3453	pgmUnlock(pVM);
3454	AssertRC(rc);
3455	return rc;
3456	}
3457	}
3458
3459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3460	/* Check for dirty bit fault */
3461	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3462	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3463	Log(("PGMVerifyAccess: success (dirty)\n"));
3464	else
3465	# endif
3466	{
3467	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3468	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3469	# else
3470	GSTPDE PdeSrc;
3471	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3472	PdeSrc.n.u1Present = 1;
3473	PdeSrc.n.u1Write = 1;
3474	PdeSrc.n.u1Accessed = 1;
3475	PdeSrc.n.u1User = 1;
3476	# endif
3477
3478	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3479	if (uErr & X86_TRAP_PF_US)
3480	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3481	else /* supervisor */
3482	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3483
3484	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3485	if (RT_SUCCESS(rc))
3486	{
3487	/* Page was successfully synced */
3488	Log2(("PGMVerifyAccess: success (sync)\n"));
3489	rc = VINF_SUCCESS;
3490	}
3491	else
3492	{
3493	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3494	rc = VINF_EM_RAW_GUEST_TRAP;
3495	}
3496	}
3497	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3498	pgmUnlock(pVM);
3499	return rc;
3500
3501	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3502
3503	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3504	return VERR_INTERNAL_ERROR;
3505	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3506	}
3507
3508
3509	/**
3510	* Syncs the paging hierarchy starting at CR3.
3511	*
3512	* @returns VBox status code, no specials.
3513	* @param pVCpu The VMCPU handle.
3514	* @param cr0 Guest context CR0 register
3515	* @param cr3 Guest context CR3 register
3516	* @param cr4 Guest context CR4 register
3517	* @param fGlobal Including global page directories or not
3518	*/
3519	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3520	{
3521	PVM pVM = pVCpu->CTX_SUFF(pVM);
3522
3523	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3524
3525	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3526
3527	pgmLock(pVM);
3528
3529	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3530	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3531	if (pPool->cDirtyPages)
3532	pgmPoolResetDirtyPages(pVM);
3533	# endif
3534
3535	/*
3536	* Update page access handlers.
3537	* The virtual are always flushed, while the physical are only on demand.
3538	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3539	* have to look into that later because it will have a bad influence on the performance.
3540	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3541	* bird: Yes, but that won't work for aliases.
3542	*/
3543	/** @todo this MUST go away. See #1557. */
3544	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3545	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3546	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3547	pgmUnlock(pVM);
3548	#endif /* !NESTED && !EPT */
3549
3550	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3551	/*
3552	* Nested / EPT - almost no work.
3553	*/
3554	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3555	return VINF_SUCCESS;
3556
3557	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3558	/*
3559	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3560	* out the shadow parts when the guest modifies its tables.
3561	*/
3562	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3563	return VINF_SUCCESS;
3564
3565	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3566
3567	# ifndef PGM_WITHOUT_MAPPINGS
3568	/*
3569	* Check for and resolve conflicts with our guest mappings if they
3570	* are enabled and not fixed.
3571	*/
3572	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3573	{
3574	int rc = pgmMapResolveConflicts(pVM);
3575	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3576	if (rc == VINF_PGM_SYNC_CR3)
3577	{
3578	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3579	return VINF_PGM_SYNC_CR3;
3580	}
3581	}
3582	# else
3583	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3584	# endif
3585	return VINF_SUCCESS;
3586	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3587	}
3588
3589
3590
3591
3592	#ifdef VBOX_STRICT
3593	# ifdef IN_RC
3594	# undef AssertMsgFailed
3595	# define AssertMsgFailed Log
3596	# endif
3597
3598	/**
3599	* Checks that the shadow page table is in sync with the guest one.
3600	*
3601	* @returns The number of errors.
3602	* @param pVM The virtual machine.
3603	* @param pVCpu The VMCPU handle.
3604	* @param cr3 Guest context CR3 register
3605	* @param cr4 Guest context CR4 register
3606	* @param GCPtr Where to start. Defaults to 0.
3607	* @param cb How much to check. Defaults to everything.
3608	*/
3609	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3610	{
3611	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3612	return 0;
3613	#else
3614	unsigned cErrors = 0;
3615	PVM pVM = pVCpu->CTX_SUFF(pVM);
3616	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3617
3618	#if PGM_GST_TYPE == PGM_TYPE_PAE
3619	/** @todo currently broken; crashes below somewhere */
3620	AssertFailed();
3621	#endif
3622
3623	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3624	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3625	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3626
3627	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3628	PPGMCPU pPGM = &pVCpu->pgm.s;
3629	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3630	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3631	# ifndef IN_RING0
3632	RTHCPHYS HCPhys; /* general usage. */
3633	# endif
3634	int rc;
3635
3636	/*
3637	* Check that the Guest CR3 and all its mappings are correct.
3638	*/
3639	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3640	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3641	false);
3642	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3643	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3644	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3645	# else
3646	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3647	# endif
3648	AssertRCReturn(rc, 1);
3649	HCPhys = NIL_RTHCPHYS;
3650	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3651	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3652	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3653	pgmGstGet32bitPDPtr(pVCpu);
3654	RTGCPHYS GCPhys;
3655	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3656	AssertRCReturn(rc, 1);
3657	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3658	# endif
3659	# endif /* !IN_RING0 */
3660
3661	/*
3662	* Get and check the Shadow CR3.
3663	*/
3664	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3665	unsigned cPDEs = X86_PG_ENTRIES;
3666	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3667	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3668	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3669	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3670	# else
3671	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3672	# endif
3673	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3674	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3675	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3676	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3677	# endif
3678	if (cb != ~(RTGCPTR)0)
3679	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3680
3681	/** @todo call the other two PGMAssert() functions. /
3682
3683	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3684	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3685
3686	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3687	{
3688	PPGMPOOLPAGE pShwPdpt = NULL;
3689	PX86PML4E pPml4eSrc;
3690	PX86PML4E pPml4eDst;
3691	RTGCPHYS GCPhysPdptSrc;
3692
3693	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3694	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3695
3696	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3697	if (!pPml4eDst->n.u1Present)
3698	{
3699	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3700	continue;
3701	}
3702
3703	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3704	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3705
3706	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3707	{
3708	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3709	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3710	cErrors++;
3711	continue;
3712	}
3713
3714	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3715	{
3716	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3717	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3718	cErrors++;
3719	continue;
3720	}
3721
3722	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3723	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3724	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3725	{
3726	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3727	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3728	cErrors++;
3729	continue;
3730	}
3731	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3732	{
3733	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3734
3735	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3736	/*
3737	* Check the PDPTEs too.
3738	*/
3739	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3740
3741	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3742	{
3743	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3744	PPGMPOOLPAGE pShwPde = NULL;
3745	PX86PDPE pPdpeDst;
3746	RTGCPHYS GCPhysPdeSrc;
3747	# if PGM_GST_TYPE == PGM_TYPE_PAE
3748	X86PDPE PdpeSrc;
3749	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3750	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3751	# else
3752	PX86PML4E pPml4eSrcIgn;
3753	X86PDPE PdpeSrc;
3754	PX86PDPT pPdptDst;
3755	PX86PDPAE pPDDst;
3756	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3757
3758	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3759	if (rc != VINF_SUCCESS)
3760	{
3761	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3762	GCPtr += 512 * _2M;
3763	continue; /* next PDPTE */
3764	}
3765	Assert(pPDDst);
3766	# endif
3767	Assert(iPDSrc == 0);
3768
3769	pPdpeDst = &pPdptDst->a[iPdpt];
3770
3771	if (!pPdpeDst->n.u1Present)
3772	{
3773	GCPtr += 512 * _2M;
3774	continue; /* next PDPTE */
3775	}
3776
3777	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3778	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3779
3780	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3781	{
3782	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3783	GCPtr += 512 * _2M;
3784	cErrors++;
3785	continue;
3786	}
3787
3788	if (GCPhysPdeSrc != pShwPde->GCPhys)
3789	{
3790	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3791	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3792	# else
3793	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3794	# endif
3795	GCPtr += 512 * _2M;
3796	cErrors++;
3797	continue;
3798	}
3799
3800	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3801	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3802	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3803	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3804	{
3805	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3806	GCPtr += 512 * _2M;
3807	cErrors++;
3808	continue;
3809	}
3810	# endif
3811
3812	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3813	{
3814	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3815	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3816	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3817	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3818	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3819	# endif
3820	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3821	/*
3822	* Iterate the shadow page directory.
3823	*/
3824	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3825	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3826
3827	for (;
3828	iPDDst < cPDEs;
3829	iPDDst++, GCPtr += cIncrement)
3830	{
3831	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3832	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3833	# else
3834	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3835	# endif
3836	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3837	{
3838	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3839	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3840	{
3841	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3842	cErrors++;
3843	continue;
3844	}
3845	}
3846	else if ( (PdeDst.u & X86_PDE_P)
3847	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3848	)
3849	{
3850	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3851	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3852	if (!pPoolPage)
3853	{
3854	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3855	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3856	cErrors++;
3857	continue;
3858	}
3859	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3860
3861	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3862	{
3863	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3864	GCPtr, (uint64_t)PdeDst.u));
3865	cErrors++;
3866	}
3867
3868	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3869	{
3870	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3871	GCPtr, (uint64_t)PdeDst.u));
3872	cErrors++;
3873	}
3874
3875	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3876	if (!PdeSrc.n.u1Present)
3877	{
3878	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3879	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3880	cErrors++;
3881	continue;
3882	}
3883
3884	if ( !PdeSrc.b.u1Size
3885	\|\| !fBigPagesSupported)
3886	{
3887	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3888	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3889	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3890	# endif
3891	}
3892	else
3893	{
3894	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3895	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3896	{
3897	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3898	GCPtr, (uint64_t)PdeSrc.u));
3899	cErrors++;
3900	continue;
3901	}
3902	# endif
3903	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3904	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3905	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3906	# endif
3907	}
3908
3909	if ( pPoolPage->enmKind
3910	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3911	{
3912	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3913	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3914	cErrors++;
3915	}
3916
3917	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3918	if (!pPhysPage)
3919	{
3920	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3921	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3922	cErrors++;
3923	continue;
3924	}
3925
3926	if (GCPhysGst != pPoolPage->GCPhys)
3927	{
3928	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3929	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3930	cErrors++;
3931	continue;
3932	}
3933
3934	if ( !PdeSrc.b.u1Size
3935	\|\| !fBigPagesSupported)
3936	{
3937	/*
3938	* Page Table.
3939	*/
3940	const GSTPT *pPTSrc;
3941	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3942	if (RT_FAILURE(rc))
3943	{
3944	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3945	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3946	cErrors++;
3947	continue;
3948	}
3949	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3950	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3951	{
3952	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3953	// (This problem will go away when/if we shadow multiple CR3s.)
3954	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3955	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3956	cErrors++;
3957	continue;
3958	}
3959	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3960	{
3961	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3962	GCPtr, (uint64_t)PdeDst.u));
3963	cErrors++;
3964	continue;
3965	}
3966
3967	/* iterate the page table. */
3968	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3969	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3970	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3971	# else
3972	const unsigned offPTSrc = 0;
3973	# endif
3974	for (unsigned iPT = 0, off = 0;
3975	iPT < RT_ELEMENTS(pPTDst->a);
3976	iPT++, off += PAGE_SIZE)
3977	{
3978	const SHWPTE PteDst = pPTDst->a[iPT];
3979
3980	/* skip not-present and dirty tracked entries. */
3981	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3982	continue;
3983	Assert(SHW_PTE_IS_P(PteDst));
3984
3985	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3986	if (!PteSrc.n.u1Present)
3987	{
3988	# ifdef IN_RING3
3989	PGMAssertHandlerAndFlagsInSync(pVM);
3990	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3991	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3992	0, 0, UINT64_MAX, 99, NULL);
3993	# endif
3994	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3995	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3996	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3997	cErrors++;
3998	continue;
3999	}
4000
4001	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4002	# if 1 /** @todo sync accessed bit properly... */
4003	fIgnoreFlags \|= X86_PTE_A;
4004	# endif
4005
4006	/* match the physical addresses */
4007	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4008	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4009
4010	# ifdef IN_RING3
4011	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4012	if (RT_FAILURE(rc))
4013	{
4014	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4015	{
4016	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4017	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4018	cErrors++;
4019	continue;
4020	}
4021	}
4022	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4023	{
4024	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4025	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4026	cErrors++;
4027	continue;
4028	}
4029	# endif
4030
4031	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4032	if (!pPhysPage)
4033	{
4034	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4035	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4036	{
4037	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4038	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4039	cErrors++;
4040	continue;
4041	}
4042	# endif
4043	if (SHW_PTE_IS_RW(PteDst))
4044	{
4045	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4046	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4047	cErrors++;
4048	}
4049	fIgnoreFlags \|= X86_PTE_RW;
4050	}
4051	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4052	{
4053	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4054	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4055	cErrors++;
4056	continue;
4057	}
4058
4059	/* flags */
4060	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4061	{
4062	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4063	{
4064	if (SHW_PTE_IS_RW(PteDst))
4065	{
4066	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4067	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4068	cErrors++;
4069	continue;
4070	}
4071	fIgnoreFlags \|= X86_PTE_RW;
4072	}
4073	else
4074	{
4075	if ( SHW_PTE_IS_P(PteDst)
4076	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4077	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4078	# endif
4079	)
4080	{
4081	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4082	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4083	cErrors++;
4084	continue;
4085	}
4086	fIgnoreFlags \|= X86_PTE_P;
4087	}
4088	}
4089	else
4090	{
4091	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4092	{
4093	if (SHW_PTE_IS_RW(PteDst))
4094	{
4095	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4096	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4097	cErrors++;
4098	continue;
4099	}
4100	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4101	{
4102	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4103	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4104	cErrors++;
4105	continue;
4106	}
4107	if (SHW_PTE_IS_D(PteDst))
4108	{
4109	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4110	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4111	cErrors++;
4112	}
4113	# if 0 /** @todo sync access bit properly... */
4114	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4115	{
4116	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4117	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4118	cErrors++;
4119	}
4120	fIgnoreFlags \|= X86_PTE_RW;
4121	# else
4122	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4123	# endif
4124	}
4125	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4126	{
4127	/* access bit emulation (not implemented). */
4128	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4129	{
4130	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4131	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4132	cErrors++;
4133	continue;
4134	}
4135	if (!SHW_PTE_IS_A(PteDst))
4136	{
4137	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4138	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4139	cErrors++;
4140	}
4141	fIgnoreFlags \|= X86_PTE_P;
4142	}
4143	# ifdef DEBUG_sandervl
4144	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4145	# endif
4146	}
4147
4148	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4149	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4150	)
4151	{
4152	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4153	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4154	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4155	cErrors++;
4156	continue;
4157	}
4158	} /* foreach PTE */
4159	}
4160	else
4161	{
4162	/*
4163	* Big Page.
4164	*/
4165	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4166	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4167	{
4168	if (PdeDst.n.u1Write)
4169	{
4170	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4171	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4172	cErrors++;
4173	continue;
4174	}
4175	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4176	{
4177	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4178	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4179	cErrors++;
4180	continue;
4181	}
4182	# if 0 /** @todo sync access bit properly... */
4183	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4184	{
4185	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4186	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4187	cErrors++;
4188	}
4189	fIgnoreFlags \|= X86_PTE_RW;
4190	# else
4191	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4192	# endif
4193	}
4194	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4195	{
4196	/* access bit emulation (not implemented). */
4197	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4198	{
4199	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4200	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4201	cErrors++;
4202	continue;
4203	}
4204	if (!PdeDst.n.u1Accessed)
4205	{
4206	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4207	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4208	cErrors++;
4209	}
4210	fIgnoreFlags \|= X86_PTE_P;
4211	}
4212
4213	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4214	{
4215	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4216	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4217	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4218	cErrors++;
4219	}
4220
4221	/* iterate the page table. */
4222	for (unsigned iPT = 0, off = 0;
4223	iPT < RT_ELEMENTS(pPTDst->a);
4224	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4225	{
4226	const SHWPTE PteDst = pPTDst->a[iPT];
4227
4228	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4229	{
4230	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4232	cErrors++;
4233	}
4234
4235	/* skip not-present entries. */
4236	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4237	continue;
4238
4239	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4240
4241	/* match the physical addresses */
4242	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4243
4244	# ifdef IN_RING3
4245	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4246	if (RT_FAILURE(rc))
4247	{
4248	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4249	{
4250	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4251	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4252	cErrors++;
4253	}
4254	}
4255	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4256	{
4257	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4258	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4259	cErrors++;
4260	continue;
4261	}
4262	# endif
4263	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4264	if (!pPhysPage)
4265	{
4266	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4267	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4268	{
4269	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4270	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4271	cErrors++;
4272	continue;
4273	}
4274	# endif
4275	if (SHW_PTE_IS_RW(PteDst))
4276	{
4277	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4278	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4279	cErrors++;
4280	}
4281	fIgnoreFlags \|= X86_PTE_RW;
4282	}
4283	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4284	{
4285	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4286	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4287	cErrors++;
4288	continue;
4289	}
4290
4291	/* flags */
4292	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4293	{
4294	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4295	{
4296	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4297	{
4298	if (SHW_PTE_IS_RW(PteDst))
4299	{
4300	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4301	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4302	cErrors++;
4303	continue;
4304	}
4305	fIgnoreFlags \|= X86_PTE_RW;
4306	}
4307	}
4308	else
4309	{
4310	if ( SHW_PTE_IS_P(PteDst)
4311	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4312	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4313	# endif
4314	)
4315	{
4316	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4317	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4318	cErrors++;
4319	continue;
4320	}
4321	fIgnoreFlags \|= X86_PTE_P;
4322	}
4323	}
4324
4325	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4326	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4327	)
4328	{
4329	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4330	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4331	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4332	cErrors++;
4333	continue;
4334	}
4335	} /* for each PTE */
4336	}
4337	}
4338	/* not present */
4339
4340	} /* for each PDE */
4341
4342	} /* for each PDPTE */
4343
4344	} /* for each PML4E */
4345
4346	# ifdef DEBUG
4347	if (cErrors)
4348	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4349	# endif
4350
4351	#endif /* GST == 32BIT, PAE or AMD64 */
4352	return cErrors;
4353
4354	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4355	}
4356	#endif /* VBOX_STRICT */
4357
4358
4359	/**
4360	* Sets up the CR3 for shadow paging
4361	*
4362	* @returns Strict VBox status code.
4363	* @retval VINF_SUCCESS.
4364	*
4365	* @param pVCpu The VMCPU handle.
4366	* @param GCPhysCR3 The physical address in the CR3 register.
4367	*/
4368	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4369	{
4370	PVM pVM = pVCpu->CTX_SUFF(pVM);
4371
4372	/* Update guest paging info. */
4373	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4374	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4375	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4376
4377	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4378
4379	/*
4380	* Map the page CR3 points at.
4381	*/
4382	RTHCPTR HCPtrGuestCR3;
4383	RTHCPHYS HCPhysGuestCR3;
4384	pgmLock(pVM);
4385	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4386	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4387	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4388	/** @todo this needs some reworking wrt. locking? */
4389	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4390	HCPtrGuestCR3 = NIL_RTHCPTR;
4391	int rc = VINF_SUCCESS;
4392	# else
4393	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4394	# endif
4395	pgmUnlock(pVM);
4396	if (RT_SUCCESS(rc))
4397	{
4398	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4399	if (RT_SUCCESS(rc))
4400	{
4401	# ifdef IN_RC
4402	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4403	# endif
4404	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4405	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4406	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4407	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4408	# endif
4409	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4410
4411	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4412	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4413	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4414	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4415	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4416	# endif
4417	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4418	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4419
4420	/*
4421	* Map the 4 PDs too.
4422	*/
4423	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4424	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4425	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4426	{
4427	if (pGuestPDPT->a[i].n.u1Present)
4428	{
4429	RTHCPTR HCPtr;
4430	RTHCPHYS HCPhys;
4431	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4432	pgmLock(pVM);
4433	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4434	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4435	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4436	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4437	HCPtr = NIL_RTHCPTR;
4438	int rc2 = VINF_SUCCESS;
4439	# else
4440	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4441	# endif
4442	pgmUnlock(pVM);
4443	if (RT_SUCCESS(rc2))
4444	{
4445	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4446	AssertRCReturn(rc, rc);
4447
4448	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4449	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4450	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4451	# endif
4452	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4453	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4454	# ifdef IN_RC
4455	PGM_INVL_PG(pVCpu, GCPtr);
4456	# endif
4457	continue;
4458	}
4459	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4460	}
4461
4462	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4463	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4464	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4465	# endif
4466	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4467	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4468	# ifdef IN_RC
4469	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4470	# endif
4471	}
4472
4473	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4474	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4475	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4476	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4477	# endif
4478	# endif
4479	}
4480	else
4481	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4482	}
4483	else
4484	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4485
4486	#else /* prot/real stub */
4487	int rc = VINF_SUCCESS;
4488	#endif
4489
4490	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4491	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4492	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4493	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4494	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4495	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4496
4497	Assert(!pVM->pgm.s.fNestedPaging);
4498
4499	/*
4500	* Update the shadow root page as well since that's not fixed.
4501	*/
4502	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4503	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4504	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4505	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4506	PPGMPOOLPAGE pNewShwPageCR3;
4507
4508	pgmLock(pVM);
4509
4510	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4511	if (pPool->cDirtyPages)
4512	pgmPoolResetDirtyPages(pVM);
4513	# endif
4514
4515	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4516	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4517	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4518	AssertFatalRC(rc);
4519	rc = VINF_SUCCESS;
4520
4521	# ifdef IN_RC
4522	/*
4523	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4524	* state will be inconsistent! Flush important things now while
4525	* we still can and then make sure there are no ring-3 calls.
4526	*/
4527	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4528	VMMRZCallRing3Disable(pVCpu);
4529	# endif
4530
4531	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4532	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4533	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4534	# ifdef IN_RING0
4535	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4536	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4537	# elif defined(IN_RC)
4538	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4539	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4540	# else
4541	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4542	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4543	# endif
4544
4545	# ifndef PGM_WITHOUT_MAPPINGS
4546	/*
4547	* Apply all hypervisor mappings to the new CR3.
4548	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4549	* make sure we check for conflicts in the new CR3 root.
4550	*/
4551	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4552	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4553	# endif
4554	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4555	AssertRCReturn(rc, rc);
4556	# endif
4557
4558	/* Set the current hypervisor CR3. */
4559	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4560	SELMShadowCR3Changed(pVM, pVCpu);
4561
4562	# ifdef IN_RC
4563	/* NOTE: The state is consistent again. */
4564	VMMRZCallRing3Enable(pVCpu);
4565	# endif
4566
4567	/* Clean up the old CR3 root. */
4568	if ( pOldShwPageCR3
4569	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4570	{
4571	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4572	# ifndef PGM_WITHOUT_MAPPINGS
4573	/* Remove the hypervisor mappings from the shadow page table. */
4574	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4575	# endif
4576	/* Mark the page as unlocked; allow flushing again. */
4577	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4578
4579	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4580	}
4581	pgmUnlock(pVM);
4582	# endif
4583
4584	return rc;
4585	}
4586
4587	/**
4588	* Unmaps the shadow CR3.
4589	*
4590	* @returns VBox status, no specials.
4591	* @param pVCpu The VMCPU handle.
4592	*/
4593	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4594	{
4595	LogFlow(("UnmapCR3\n"));
4596
4597	int rc = VINF_SUCCESS;
4598	PVM pVM = pVCpu->CTX_SUFF(pVM);
4599
4600	/*
4601	* Update guest paging info.
4602	*/
4603	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4604	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4605	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4606	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4607	# endif
4608	pVCpu->pgm.s.pGst32BitPdRC = 0;
4609
4610	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4611	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4612	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4613	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4614	# endif
4615	pVCpu->pgm.s.pGstPaePdptRC = 0;
4616	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4617	{
4618	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4619	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4620	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4621	# endif
4622	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4623	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4624	}
4625
4626	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4627	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4628	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4629	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4630	# endif
4631
4632	#else /* prot/real mode stub */
4633	/* nothing to do */
4634	#endif
4635
4636	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4637	/*
4638	* Update shadow paging info.
4639	*/
4640	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4641	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4642	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4643
4644	# if PGM_GST_TYPE != PGM_TYPE_REAL
4645	Assert(!pVM->pgm.s.fNestedPaging);
4646	# endif
4647
4648	pgmLock(pVM);
4649
4650	# ifndef PGM_WITHOUT_MAPPINGS
4651	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4652	/* Remove the hypervisor mappings from the shadow page table. */
4653	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4654	# endif
4655
4656	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4657	{
4658	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4659
4660	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4661
4662	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4663	if (pPool->cDirtyPages)
4664	pgmPoolResetDirtyPages(pVM);
4665	# endif
4666
4667	/* Mark the page as unlocked; allow flushing again. */
4668	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4669
4670	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4671	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4672	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4673	pVCpu->pgm.s.pShwPageCR3RC = 0;
4674	pVCpu->pgm.s.iShwUser = 0;
4675	pVCpu->pgm.s.iShwUserTable = 0;
4676	}
4677	pgmUnlock(pVM);
4678	# endif
4679	#endif /* !IN_RC*/
4680
4681	return rc;
4682	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 32486

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