PGMAllBth.h@ 32560

Last change on this file since 32560 was 32560, checked in by vboxsync, 14 years ago
Cleaned up a bit
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1	/* $Id: PGMAllBth.h 32560 2010-09-16 13:22:04Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
40	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
42	#ifdef VBOX_STRICT
43	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
44	#endif
45	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
46	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
47	RT_C_DECLS_END
48
49
50	/*
51	* Filter out some illegal combinations of guest and shadow paging, so we can
52	* remove redundant checks inside functions.
53	*/
54	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
55	# error "Invalid combination; PAE guest implies PAE shadow"
56	#endif
57
58	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
59	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
60	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
69	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
70	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
71	#endif
72
73	#ifndef IN_RING3
74
75	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
76	/**
77	* Deal with a guest page fault.
78	*
79	* @returns Strict VBox status code.
80	* @retval VINF_EM_RAW_GUEST_TRAP
81	* @retval VINF_EM_RAW_EMULATE_INSTR
82	*
83	* @param pVCpu The current CPU.
84	* @param pGstWalk The guest page table walk result.
85	* @param uErr The error code.
86	*/
87	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
88	{
89	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
90	/*
91	* Check for write conflicts with our hypervisor mapping.
92	*
93	* If the guest happens to access a non-present page, where our hypervisor
94	* is currently mapped, then we'll create a #PF storm in the guest.
95	*/
96	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
97	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
98	{
99	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
100	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
101	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
102	return VINF_EM_RAW_EMULATE_INSTR;
103	}
104	# endif
105
106	/*
107	* Calc the error code for the guest trap.
108	*/
109	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
110	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
111	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
112	if (pGstWalk->Core.fBadPhysAddr)
113	{
114	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
115	Assert(!pGstWalk->Core.fNotPresent);
116	}
117	else if (!pGstWalk->Core.fNotPresent)
118	uNewErr \|= X86_TRAP_PF_P;
119	TRPMSetErrorCode(pVCpu, uNewErr);
120
121	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
122	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
123	return VINF_EM_RAW_GUEST_TRAP;
124	}
125	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
126
127
128	/**
129	* Deal with a guest page fault.
130	*
131	* The caller has taken the PGM lock.
132	*
133	* @returns Strict VBox status code.
134	*
135	* @param pVCpu The current CPU.
136	* @param uErr The error code.
137	* @param pRegFrame The register frame.
138	* @param pvFault The fault address.
139	* @param pPage The guest page at @a pvFault.
140	* @param pGstWalk The guest page table walk result.
141	* @param pfLockTaken PGM lock taken here or not (out). This is true
142	* when we're called.
143	*/
144	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
145	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
146	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
147	, PGSTPTWALK pGstWalk
148	# endif
149	)
150	{
151	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
153	#endif
154	PVM pVM = pVCpu->CTX_SUFF(pVM);
155	int rc;
156
157	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
158	{
159	/*
160	* Physical page access handler.
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
164	# else
165	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
166	# endif
167	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
168	if (pCur)
169	{
170	# ifdef PGM_SYNC_N_PAGES
171	/*
172	* If the region is write protected and we got a page not present fault, then sync
173	* the pages. If the fault was caused by a read, then restart the instruction.
174	* In case of write access continue to the GC write handler.
175	*
176	* ASSUMES that there is only one handler per page or that they have similar write properties.
177	*/
178	if ( !(uErr & X86_TRAP_PF_P)
179	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
180	{
181	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
182	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
183	# else
184	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
185	# endif
186	if ( RT_FAILURE(rc)
187	\|\| !(uErr & X86_TRAP_PF_RW)
188	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
189	{
190	AssertRC(rc);
191	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
192	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
193	return rc;
194	}
195	}
196	# endif
197	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
198	/*
199	* If the access was not thru a #PF(RSVD\|...) resync the page.
200	*/
201	if ( !(uErr & X86_TRAP_PF_RSVD)
202	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
203	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
204	&& pGstWalk->Core.fEffectiveRW
205	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
206	# endif
207	)
208	{
209	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
210	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
211	# else
212	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
213	# endif
214	if ( RT_FAILURE(rc)
215	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
216	{
217	AssertRC(rc);
218	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
219	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
220	return rc;
221	}
222	}
223	# endif
224
225	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
226	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
227	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
228	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
229	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
230	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
231	else
232	{
233	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
234	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
235	}
236
237	if (pCur->CTX_SUFF(pfnHandler))
238	{
239	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
240	void *pvUser = pCur->CTX_SUFF(pvUser);
241	# ifdef IN_RING0
242	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
243	# else
244	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
245	# endif
246
247	STAM_PROFILE_START(&pCur->Stat, h);
248	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
249	{
250	pgmUnlock(pVM);
251	*pfLockTaken = false;
252	}
253
254	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
255
256	# ifdef VBOX_WITH_STATISTICS
257	pgmLock(pVM);
258	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
259	if (pCur)
260	STAM_PROFILE_STOP(&pCur->Stat, h);
261	pgmUnlock(pVM);
262	# endif
263	}
264	else
265	rc = VINF_EM_RAW_EMULATE_INSTR;
266
267	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
268	return rc;
269	}
270	}
271	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
272	else
273	{
274	# ifdef PGM_SYNC_N_PAGES
275	/*
276	* If the region is write protected and we got a page not present fault, then sync
277	* the pages. If the fault was caused by a read, then restart the instruction.
278	* In case of write access continue to the GC write handler.
279	*/
280	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
281	&& !(uErr & X86_TRAP_PF_P))
282	{
283	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
284	if ( RT_FAILURE(rc)
285	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
286	\|\| !(uErr & X86_TRAP_PF_RW))
287	{
288	AssertRC(rc);
289	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
290	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
291	return rc;
292	}
293	}
294	# endif
295	/*
296	* Ok, it's an virtual page access handler.
297	*
298	* Since it's faster to search by address, we'll do that first
299	* and then retry by GCPhys if that fails.
300	*/
301	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
302	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
303	* out of sync, because the page was changed without us noticing it (not-present -> present
304	* without invlpg or mov cr3, xxx).
305	*/
306	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
307	if (pCur)
308	{
309	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
310	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
311	\|\| !(uErr & X86_TRAP_PF_P)
312	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
313	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
314	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
315
316	if ( pvFault - pCur->Core.Key < pCur->cb
317	&& ( uErr & X86_TRAP_PF_RW
318	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
319	{
320	# ifdef IN_RC
321	STAM_PROFILE_START(&pCur->Stat, h);
322	RTGCPTR GCPtrStart = pCur->Core.Key;
323	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
324	pgmUnlock(pVM);
325	*pfLockTaken = false;
326
327	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
328
329	# ifdef VBOX_WITH_STATISTICS
330	pgmLock(pVM);
331	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
332	if (pCur)
333	STAM_PROFILE_STOP(&pCur->Stat, h);
334	pgmUnlock(pVM);
335	# endif
336	# else
337	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
338	# endif
339	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
340	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
341	return rc;
342	}
343	/* Unhandled part of a monitored page */
344	}
345	else
346	{
347	/* Check by physical address. */
348	unsigned iPage;
349	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
350	Assert(RT_SUCCESS(rc) \|\| !pCur);
351	if ( pCur
352	&& ( uErr & X86_TRAP_PF_RW
353	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
354	{
355	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
356	# ifdef IN_RC
357	STAM_PROFILE_START(&pCur->Stat, h);
358	RTGCPTR GCPtrStart = pCur->Core.Key;
359	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
360	pgmUnlock(pVM);
361	*pfLockTaken = false;
362
363	RTGCPTR off = (iPage << PAGE_SHIFT)
364	+ (pvFault & PAGE_OFFSET_MASK)
365	- (GCPtrStart & PAGE_OFFSET_MASK);
366	Assert(off < pCur->cb);
367	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
368
369	# ifdef VBOX_WITH_STATISTICS
370	pgmLock(pVM);
371	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
372	if (pCur)
373	STAM_PROFILE_STOP(&pCur->Stat, h);
374	pgmUnlock(pVM);
375	# endif
376	# else
377	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
378	# endif
379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
380	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
381	return rc;
382	}
383	}
384	}
385	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
386
387	/*
388	* There is a handled area of the page, but this fault doesn't belong to it.
389	* We must emulate the instruction.
390	*
391	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
392	* we first check if this was a page-not-present fault for a page with only
393	* write access handlers. Restart the instruction if it wasn't a write access.
394	*/
395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
396
397	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
398	&& !(uErr & X86_TRAP_PF_P))
399	{
400	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
401	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
402	# else
403	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
404	# endif
405	if ( RT_FAILURE(rc)
406	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
407	\|\| !(uErr & X86_TRAP_PF_RW))
408	{
409	AssertRC(rc);
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
411	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
412	return rc;
413	}
414	}
415
416	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
417	* It's writing to an unhandled part of the LDT page several million times.
418	*/
419	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
420	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
422	return rc;
423	} /* if any kind of handler */
424
425
426	/**
427	* #PF Handler for raw-mode guest execution.
428	*
429	* @returns VBox status code (appropriate for trap handling and GC return).
430	*
431	* @param pVCpu VMCPU Handle.
432	* @param uErr The trap error code.
433	* @param pRegFrame Trap register frame.
434	* @param pvFault The fault address.
435	* @param pfLockTaken PGM lock taken here or not (out)
436	*/
437	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
438	{
439	PVM pVM = pVCpu->CTX_SUFF(pVM);
440
441	*pfLockTaken = false;
442
443	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
444	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
445	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
446	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
447	int rc;
448
449	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
450	/*
451	* Walk the guest page translation tables and check if it's a guest fault.
452	*/
453	GSTPTWALK GstWalk;
454	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
455	if (RT_FAILURE_NP(rc))
456	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
457
458	/* assert some GstWalk sanity. */
459	# if PGM_GST_TYPE == PGM_TYPE_AMD64
460	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
461	# endif
462	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
463	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
464	# endif
465	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
466	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
467	Assert(GstWalk.Core.fSucceeded);
468
469	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
470	{
471	if ( ( (uErr & X86_TRAP_PF_RW)
472	&& !GstWalk.Core.fEffectiveRW
473	&& ( (uErr & X86_TRAP_PF_US)
474	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
475	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
476	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
477	)
478	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
479	}
480
481	/*
482	* Set the accessed and dirty flags.
483	*/
484	# if PGM_GST_TYPE == PGM_TYPE_AMD64
485	GstWalk.Pml4e.u \|= X86_PML4E_A;
486	GstWalk.pPml4e->u \|= X86_PML4E_A;
487	GstWalk.Pdpe.u \|= X86_PDPE_A;
488	GstWalk.pPdpe->u \|= X86_PDPE_A;
489	# endif
490	if (GstWalk.Core.fBigPage)
491	{
492	Assert(GstWalk.Pde.b.u1Size);
493	if (uErr & X86_TRAP_PF_RW)
494	{
495	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
496	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
497	}
498	else
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A;
501	GstWalk.pPde->u \|= X86_PDE4M_A;
502	}
503	}
504	else
505	{
506	Assert(!GstWalk.Pde.b.u1Size);
507	GstWalk.Pde.u \|= X86_PDE_A;
508	GstWalk.pPde->u \|= X86_PDE_A;
509	if (uErr & X86_TRAP_PF_RW)
510	{
511	# ifdef VBOX_WITH_STATISTICS
512	if (!GstWalk.Pte.n.u1Dirty)
513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
514	else
515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
516	# endif
517	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
518	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
519	}
520	else
521	{
522	GstWalk.Pte.u \|= X86_PTE_A;
523	GstWalk.pPte->u \|= X86_PTE_A;
524	}
525	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
526	}
527	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
528	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
529	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
530	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
531	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
532
533	/* Take the big lock now. */
534	*pfLockTaken = true;
535	pgmLock(pVM);
536
537	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
538	/*
539	* If it is a reserved bit fault we know that it is an MMIO (access
540	* handler) related fault and can skip some 200 lines of code.
541	*/
542	if (uErr & X86_TRAP_PF_RSVD)
543	{
544	Assert(uErr & X86_TRAP_PF_P);
545	PPGMPAGE pPage;
546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
547	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
548	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
549	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
550	pfLockTaken, &GstWalk));
551	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
552	# else
553	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
554	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
555	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
556	pfLockTaken));
557	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
558	# endif
559	AssertRC(rc);
560	PGM_INVL_PG(pVCpu, pvFault);
561	return rc; /* Restart with the corrected entry. */
562	}
563	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
564
565	/*
566	* Fetch the guest PDE, PDPE and PML4E.
567	*/
568	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
569	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
570	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
571
572	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
573	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
574	PX86PDPAE pPDDst;
575	# if PGM_GST_TYPE == PGM_TYPE_PAE
576	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
577	# else
578	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
579	# endif
580	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
583	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
586	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
587	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
588	# else
589	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
590	# endif
591	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
592
593	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
594	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
595	PEPTPD pPDDst;
596	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
597	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
598	# endif
599	Assert(pPDDst);
600
601	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
602	/*
603	* Dirty page handling.
604	*
605	* If we successfully correct the write protection fault due to dirty bit
606	* tracking, then return immediately.
607	*/
608	if (uErr & X86_TRAP_PF_RW) /* write fault? */
609	{
610	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
611	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
612	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
613	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
614	{
615	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
616	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
617	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
618	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
619	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
620	return VINF_SUCCESS;
621	}
622	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
623	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
624	}
625
626	# if 0 /* rarely useful; leave for debugging. */
627	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
628	# endif
629	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
630
631	/*
632	* A common case is the not-present error caused by lazy page table syncing.
633	*
634	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
635	* here so we can safely assume that the shadow PT is present when calling
636	* SyncPage later.
637	*
638	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
639	* of mapping conflict and defer to SyncCR3 in R3.
640	* (Again, we do NOT support access handlers for non-present guest pages.)
641	*
642	*/
643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
644	Assert(GstWalk.Pde.n.u1Present);
645	# endif
646	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
647	&& !pPDDst->a[iPDDst].n.u1Present)
648	{
649	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
650	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
651	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
652	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
653	# else
654	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
655	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
656	# endif
657	if (RT_SUCCESS(rc))
658	return rc;
659	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
660	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
661	return VINF_PGM_SYNC_CR3;
662	}
663
664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
665	/*
666	* Check if this address is within any of our mappings.
667	*
668	* This is very fast and it's gonna save us a bit of effort below and prevent
669	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
670	* (BTW, it's impossible to have physical access handlers in a mapping.)
671	*/
672	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
673	{
674	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
675	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
676	{
677	if (pvFault < pMapping->GCPtr)
678	break;
679	if (pvFault - pMapping->GCPtr < pMapping->cb)
680	{
681	/*
682	* The first thing we check is if we've got an undetected conflict.
683	*/
684	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
685	{
686	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
687	while (iPT-- > 0)
688	if (GstWalk.pPde[iPT].n.u1Present)
689	{
690	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
691	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
692	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
693	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
694	return VINF_PGM_SYNC_CR3;
695	}
696	}
697
698	/*
699	* Check if the fault address is in a virtual page access handler range.
700	*/
701	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
702	if ( pCur
703	&& pvFault - pCur->Core.Key < pCur->cb
704	&& uErr & X86_TRAP_PF_RW)
705	{
706	# ifdef IN_RC
707	STAM_PROFILE_START(&pCur->Stat, h);
708	pgmUnlock(pVM);
709	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
710	pgmLock(pVM);
711	STAM_PROFILE_STOP(&pCur->Stat, h);
712	# else
713	AssertFailed();
714	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
715	# endif
716	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
717	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
718	return rc;
719	}
720
721	/*
722	* Pretend we're not here and let the guest handle the trap.
723	*/
724	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
725	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
726	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return VINF_EM_RAW_GUEST_TRAP;
729	}
730	}
731	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
732	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
733
734	/*
735	* Check if this fault address is flagged for special treatment,
736	* which means we'll have to figure out the physical address and
737	* check flags associated with it.
738	*
739	* ASSUME that we can limit any special access handling to pages
740	* in page tables which the guest believes to be present.
741	*/
742	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
743	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
744	# else
745	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
746	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
747	PPGMPAGE pPage;
748	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
749	if (RT_FAILURE(rc))
750	{
751	/*
752	* When the guest accesses invalid physical memory (e.g. probing
753	* of RAM or accessing a remapped MMIO range), then we'll fall
754	* back to the recompiler to emulate the instruction.
755	*/
756	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
757	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
758	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
759	return VINF_EM_RAW_EMULATE_INSTR;
760	}
761
762	/*
763	* Any handlers for this page?
764	*/
765	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
766	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
767	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
768	&GstWalk));
769	# else
770	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
771	# endif
772
773	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
774
775	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
776	if (uErr & X86_TRAP_PF_P)
777	{
778	/*
779	* The page isn't marked, but it might still be monitored by a virtual page access handler.
780	* (ASSUMES no temporary disabling of virtual handlers.)
781	*/
782	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
783	* we should correct both the shadow page table and physical memory flags, and not only check for
784	* accesses within the handler region but for access to pages with virtual handlers. */
785	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
786	if (pCur)
787	{
788	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
789	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
790	\|\| !(uErr & X86_TRAP_PF_P)
791	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
792	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
793
794	if ( pvFault - pCur->Core.Key < pCur->cb
795	&& ( uErr & X86_TRAP_PF_RW
796	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
797	{
798	# ifdef IN_RC
799	STAM_PROFILE_START(&pCur->Stat, h);
800	pgmUnlock(pVM);
801	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
802	pgmLock(pVM);
803	STAM_PROFILE_STOP(&pCur->Stat, h);
804	# else
805	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
806	# endif
807	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
808	return rc;
809	}
810	}
811	}
812	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
813
814	/*
815	* We are here only if page is present in Guest page tables and
816	* trap is not handled by our handlers.
817	*
818	* Check it for page out-of-sync situation.
819	*/
820	if (!(uErr & X86_TRAP_PF_P))
821	{
822	/*
823	* Page is not present in our page tables. Try to sync it!
824	*/
825	if (uErr & X86_TRAP_PF_US)
826	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
827	else /* supervisor */
828	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
829
830	if (PGM_PAGE_IS_BALLOONED(pPage))
831	{
832	/* Emulate reads from ballooned pages as they are not present in
833	our shadow page tables. (Required for e.g. Solaris guests; soft
834	ecc, random nr generator.) */
835	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
836	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
838	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
839	return rc;
840	}
841
842	# if defined(LOG_ENABLED) && !defined(IN_RING0)
843	RTGCPHYS GCPhys2;
844	uint64_t fPageGst2;
845	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
846	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
847	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
848	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
849	# else
850	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
851	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
852	# endif
853	# endif /* LOG_ENABLED */
854
855	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
856	if ( !GstWalk.Core.fEffectiveUS
857	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
858	{
859	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
860	if ( pvFault == (RTGCPTR)pRegFrame->eip
861	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
862	# ifdef CSAM_DETECT_NEW_CODE_PAGES
863	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
864	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
865	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
866	)
867	{
868	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
869	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
870	if (rc != VINF_SUCCESS)
871	{
872	/*
873	* CSAM needs to perform a job in ring 3.
874	*
875	* Sync the page before going to the host context; otherwise we'll end up in a loop if
876	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
877	*/
878	LogFlow(("CSAM ring 3 job\n"));
879	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
880	AssertRC(rc2);
881
882	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
883	return rc;
884	}
885	}
886	# ifdef CSAM_DETECT_NEW_CODE_PAGES
887	else if ( uErr == X86_TRAP_PF_RW
888	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
889	&& pRegFrame->ecx < 0x10000)
890	{
891	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
892	* to detect loading of new code pages.
893	*/
894
895	/*
896	* Decode the instruction.
897	*/
898	RTGCPTR PC;
899	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
900	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
901	if (rc == VINF_SUCCESS)
902	{
903	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
904	uint32_t cbOp;
905	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
906
907	/* For now we'll restrict this to rep movsw/d instructions */
908	if ( rc == VINF_SUCCESS
909	&& pDis->pCurInstr->opcode == OP_MOVSWD
910	&& (pDis->prefix & PREFIX_REP))
911	{
912	CSAMMarkPossibleCodePage(pVM, pvFault);
913	}
914	}
915	}
916	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
917
918	/*
919	* Mark this page as safe.
920	*/
921	/** @todo not correct for pages that contain both code and data!! */
922	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
923	CSAMMarkPage(pVM, pvFault, true);
924	}
925	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
926	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
927	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
928	# else
929	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
930	# endif
931	if (RT_SUCCESS(rc))
932	{
933	/* The page was successfully synced, return to the guest. */
934	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
935	return VINF_SUCCESS;
936	}
937	}
938	else /* uErr & X86_TRAP_PF_P: */
939	{
940	/*
941	* Write protected pages are made writable when the guest makes the
942	* first write to it. This happens for pages that are shared, write
943	* monitored or not yet allocated.
944	*
945	* We may also end up here when CR0.WP=0 in the guest.
946	*
947	* Also, a side effect of not flushing global PDEs are out of sync
948	* pages due to physical monitored regions, that are no longer valid.
949	* Assume for now it only applies to the read/write flag.
950	*/
951	if (uErr & X86_TRAP_PF_RW)
952	{
953	/*
954	* Check if it is a read-only page.
955	*/
956	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
957	{
958	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
959	Assert(!PGM_PAGE_IS_ZERO(pPage));
960	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
961	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
962
963	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
964	if (rc != VINF_SUCCESS)
965	{
966	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
967	return rc;
968	}
969	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
970	return VINF_EM_NO_MEMORY;
971	}
972
973	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
974	/*
975	* Check to see if we need to emulate the instruction if CR0.WP=0.
976	*/
977	if ( !GstWalk.Core.fEffectiveRW
978	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
979	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
980	{
981	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
982	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
983	if (RT_SUCCESS(rc))
984	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
985	else
986	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
987	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
988	return rc;
989	}
990	# endif
991	/// @todo count the above case; else
992	if (uErr & X86_TRAP_PF_US)
993	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
994	else /* supervisor */
995	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
996
997	/*
998	* Sync the page.
999	*
1000	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1001	* page is not present, which is not true in this case.
1002	*/
1003	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1004	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1005	# else
1006	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1007	# endif
1008	if (RT_SUCCESS(rc))
1009	{
1010	/*
1011	* Page was successfully synced, return to guest but invalidate
1012	* the TLB first as the page is very likely to be in it.
1013	*/
1014	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1015	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1016	# else
1017	PGM_INVL_PG(pVCpu, pvFault);
1018	# endif
1019	# ifdef VBOX_STRICT
1020	RTGCPHYS GCPhys2;
1021	uint64_t fPageGst;
1022	if (!pVM->pgm.s.fNestedPaging)
1023	{
1024	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1025	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1026	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1027	}
1028	uint64_t fPageShw;
1029	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1030	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1031	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1032	# endif /* VBOX_STRICT */
1033	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1034	return VINF_SUCCESS;
1035	}
1036	}
1037	/** @todo else: why are we here? */
1038
1039	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1040	/*
1041	* Check for VMM page flags vs. Guest page flags consistency.
1042	* Currently only for debug purposes.
1043	*/
1044	if (RT_SUCCESS(rc))
1045	{
1046	/* Get guest page flags. */
1047	uint64_t fPageGst;
1048	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1049	if (RT_SUCCESS(rc))
1050	{
1051	uint64_t fPageShw;
1052	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1053
1054	/*
1055	* Compare page flags.
1056	* Note: we have AVL, A, D bits desynched.
1057	*/
1058	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1059	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1060	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1061	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1062	}
1063	else
1064	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1065	}
1066	else
1067	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1068	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1069	}
1070
1071
1072	/*
1073	* If we get here it is because something failed above, i.e. most like guru
1074	* meditiation time.
1075	*/
1076	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1077	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1078	return rc;
1079
1080	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1081	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1082	return VERR_INTERNAL_ERROR;
1083	# endif
1084	}
1085	#endif /* !IN_RING3 */
1086
1087
1088	/**
1089	* Emulation of the invlpg instruction.
1090	*
1091	*
1092	* @returns VBox status code.
1093	*
1094	* @param pVCpu The VMCPU handle.
1095	* @param GCPtrPage Page to invalidate.
1096	*
1097	* @remark ASSUMES that the guest is updating before invalidating. This order
1098	* isn't required by the CPU, so this is speculative and could cause
1099	* trouble.
1100	* @remark No TLB shootdown is done on any other VCPU as we assume that
1101	* invlpg emulation is the only reason for calling this function.
1102	* (The guest has to shoot down TLB entries on other CPUs itself)
1103	* Currently true, but keep in mind!
1104	*
1105	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1106	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1107	*/
1108	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1109	{
1110	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1111	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1112	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1113	int rc;
1114	PVM pVM = pVCpu->CTX_SUFF(pVM);
1115	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1116
1117	Assert(PGMIsLockOwner(pVM));
1118
1119	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1120
1121	/*
1122	* Get the shadow PD entry and skip out if this PD isn't present.
1123	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1124	*/
1125	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1126	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1127	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1128
1129	/* Fetch the pgm pool shadow descriptor. */
1130	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1131	Assert(pShwPde);
1132
1133	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1134	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1135	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1136
1137	/* If the shadow PDPE isn't present, then skip the invalidate. */
1138	if (!pPdptDst->a[iPdpt].n.u1Present)
1139	{
1140	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1141	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1142	return VINF_SUCCESS;
1143	}
1144
1145	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1146	PPGMPOOLPAGE pShwPde = NULL;
1147	PX86PDPAE pPDDst;
1148
1149	/* Fetch the pgm pool shadow descriptor. */
1150	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1151	AssertRCSuccessReturn(rc, rc);
1152	Assert(pShwPde);
1153
1154	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1155	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1156
1157	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1158	/* PML4 */
1159	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1160	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1161	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1162	PX86PDPAE pPDDst;
1163	PX86PDPT pPdptDst;
1164	PX86PML4E pPml4eDst;
1165	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1166	if (rc != VINF_SUCCESS)
1167	{
1168	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1169	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1170	return VINF_SUCCESS;
1171	}
1172	Assert(pPDDst);
1173
1174	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1175	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1176
1177	if (!pPdpeDst->n.u1Present)
1178	{
1179	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1180	return VINF_SUCCESS;
1181	}
1182
1183	/* Fetch the pgm pool shadow descriptor. */
1184	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1185	Assert(pShwPde);
1186
1187	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1188
1189	const SHWPDE PdeDst = *pPdeDst;
1190	if (!PdeDst.n.u1Present)
1191	{
1192	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1193	return VINF_SUCCESS;
1194	}
1195
1196	/*
1197	* Get the guest PD entry and calc big page.
1198	*/
1199	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1200	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1201	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1202	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1203	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1204	unsigned iPDSrc = 0;
1205	# if PGM_GST_TYPE == PGM_TYPE_PAE
1206	X86PDPE PdpeSrcIgn;
1207	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1208	# else /* AMD64 */
1209	PX86PML4E pPml4eSrcIgn;
1210	X86PDPE PdpeSrcIgn;
1211	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1212	# endif
1213	GSTPDE PdeSrc;
1214
1215	if (pPDSrc)
1216	PdeSrc = pPDSrc->a[iPDSrc];
1217	else
1218	PdeSrc.u = 0;
1219	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1220	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1221
1222	# ifdef IN_RING3
1223	/*
1224	* If a CR3 Sync is pending we may ignore the invalidate page operation
1225	* depending on the kind of sync and if it's a global page or not.
1226	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1227	*/
1228	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1229	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1230	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1231	&& fIsBigPage
1232	&& PdeSrc.b.u1Global
1233	)
1234	)
1235	# else
1236	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1237	# endif
1238	{
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1240	return VINF_SUCCESS;
1241	}
1242	# endif /* IN_RING3 */
1243
1244	/*
1245	* Deal with the Guest PDE.
1246	*/
1247	rc = VINF_SUCCESS;
1248	if (PdeSrc.n.u1Present)
1249	{
1250	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1251	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1252	# ifndef PGM_WITHOUT_MAPPING
1253	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1254	{
1255	/*
1256	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1257	*/
1258	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1259	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1260	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1261	}
1262	else
1263	# endif /* !PGM_WITHOUT_MAPPING */
1264	if (!fIsBigPage)
1265	{
1266	/*
1267	* 4KB - page.
1268	*/
1269	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1270	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1271
1272	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1273	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1274	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1275	# endif
1276	if (pShwPage->GCPhys == GCPhys)
1277	{
1278	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1279	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
1280	if (RT_SUCCESS(rc))
1281	rc = VINF_SUCCESS;
1282	# endif
1283	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1284	PGM_INVL_PG(pVCpu, GCPtrPage);
1285	}
1286	else
1287	{
1288	/*
1289	* The page table address changed.
1290	*/
1291	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1292	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1293	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1294	ASMAtomicWriteSize(pPdeDst, 0);
1295	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1296	PGM_INVL_VCPU_TLBS(pVCpu);
1297	}
1298	}
1299	else
1300	{
1301	/*
1302	* 2/4MB - page.
1303	*/
1304	/* Before freeing the page, check if anything really changed. */
1305	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1306	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1307	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1308	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1309	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1310	# endif
1311	if ( pShwPage->GCPhys == GCPhys
1312	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1313	{
1314	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1315	/** @todo This test is wrong as it cannot check the G bit!
1316	* FIXME */
1317	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1318	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1319	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1320	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1321	{
1322	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1323	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1324	return VINF_SUCCESS;
1325	}
1326	}
1327
1328	/*
1329	* Ok, the page table is present and it's been changed in the guest.
1330	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1331	* We could do this for some flushes in GC too, but we need an algorithm for
1332	* deciding which 4MB pages containing code likely to be executed very soon.
1333	*/
1334	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1335	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1336	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1337	ASMAtomicWriteSize(pPdeDst, 0);
1338	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1339	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1340	}
1341	}
1342	else
1343	{
1344	/*
1345	* Page directory is not present, mark shadow PDE not present.
1346	*/
1347	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1348	{
1349	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1350	ASMAtomicWriteSize(pPdeDst, 0);
1351	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1352	PGM_INVL_PG(pVCpu, GCPtrPage);
1353	}
1354	else
1355	{
1356	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1357	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1358	}
1359	}
1360	return rc;
1361
1362	#else /* guest real and protected mode */
1363	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1364	return VINF_SUCCESS;
1365	#endif
1366	}
1367
1368
1369	/**
1370	* Update the tracking of shadowed pages.
1371	*
1372	* @param pVCpu The VMCPU handle.
1373	* @param pShwPage The shadow page.
1374	* @param HCPhys The physical page we is being dereferenced.
1375	* @param iPte Shadow PTE index
1376	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1377	*/
1378	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte, RTGCPHYS GCPhysPage)
1379	{
1380	PVM pVM = pVCpu->CTX_SUFF(pVM);
1381
1382	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1383	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1384	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1385
1386	/* Use the hint we retrieved from the cached guest PT. */
1387	if (pShwPage->fDirty)
1388	{
1389	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1390
1391	Assert(pShwPage->cPresent);
1392	Assert(pPool->cPresent);
1393	pShwPage->cPresent--;
1394	pPool->cPresent--;
1395
1396	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysPage);
1397	AssertRelease(pPhysPage);
1398	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1399	return;
1400	}
1401	# endif
1402
1403	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1404	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1405
1406	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1407	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1408	* 2. write protect all shadowed pages. I.e. implement caching.
1409	*/
1410	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1411
1412	/*
1413	* Find the guest address.
1414	*/
1415	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1416	pRam;
1417	pRam = pRam->CTX_SUFF(pNext))
1418	{
1419	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1420	while (iPage-- > 0)
1421	{
1422	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1423	{
1424	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1425
1426	Assert(pShwPage->cPresent);
1427	Assert(pPool->cPresent);
1428	pShwPage->cPresent--;
1429	pPool->cPresent--;
1430
1431	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1432	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1433	return;
1434	}
1435	}
1436	}
1437
1438	for (;;)
1439	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1440	}
1441
1442
1443	/**
1444	* Update the tracking of shadowed pages.
1445	*
1446	* @param pVCpu The VMCPU handle.
1447	* @param pShwPage The shadow page.
1448	* @param u16 The top 16-bit of the pPage->HCPhys.
1449	* @param pPage Pointer to the guest page. this will be modified.
1450	* @param iPTDst The index into the shadow table.
1451	*/
1452	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1453	{
1454	PVM pVM = pVCpu->CTX_SUFF(pVM);
1455
1456	/*
1457	* Just deal with the simple first time here.
1458	*/
1459	if (!u16)
1460	{
1461	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1462	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1463	/* Save the page table index. */
1464	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1465	}
1466	else
1467	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1468
1469	/* write back */
1470	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1471	PGM_PAGE_SET_TRACKING(pPage, u16);
1472
1473	/* update statistics. */
1474	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1475	pShwPage->cPresent++;
1476	if (pShwPage->iFirstPresent > iPTDst)
1477	pShwPage->iFirstPresent = iPTDst;
1478	}
1479
1480
1481	/**
1482	* Modifies a shadow PTE to account for access handlers.
1483	*
1484	* @param pVM The VM handle.
1485	* @param pPage The page in question.
1486	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1487	* A (accessed) bit so it can be emulated correctly.
1488	* @param pPteDst The shadow PTE (output). This is temporary storage and
1489	* does not need to be set atomically.
1490	*/
1491	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1492	{
1493	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1494	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1495	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1496	{
1497	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1498	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1499	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1500	pPteDst->n.u1Present = 1;
1501	pPteDst->n.u1Execute = 1;
1502	pPteDst->n.u1IgnorePAT = 1;
1503	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1504	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1505	#else
1506	if (fPteSrc & X86_PTE_A)
1507	{
1508	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1509	SHW_PTE_SET_RO(*pPteDst);
1510	}
1511	else
1512	SHW_PTE_SET(*pPteDst, 0);
1513	#endif
1514	}
1515	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1516	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1517	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1518	&& ( BTH_IS_NP_ACTIVE(pVM)
1519	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1520	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1521	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1522	# endif
1523	)
1524	{
1525	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1526	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1527	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1528	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1529	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1530	pPteDst->n.u1Present = 0;
1531	pPteDst->n.u1Write = 1;
1532	pPteDst->n.u1Execute = 0;
1533	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1534	pPteDst->n.u3EMT = 7;
1535	# else
1536	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1537	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1538	# endif
1539	}
1540	# endif
1541	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1542	else
1543	{
1544	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1545	SHW_PTE_SET(*pPteDst, 0);
1546	}
1547	/** @todo count these kinds of entries. */
1548	}
1549
1550
1551	/**
1552	* Creates a 4K shadow page for a guest page.
1553	*
1554	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1555	* physical address. The PdeSrc argument only the flags are used. No page
1556	* structured will be mapped in this function.
1557	*
1558	* @param pVCpu The VMCPU handle.
1559	* @param pPteDst Destination page table entry.
1560	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1561	* Can safely assume that only the flags are being used.
1562	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1563	* @param pShwPage Pointer to the shadow page.
1564	* @param iPTDst The index into the shadow table.
1565	*
1566	* @remark Not used for 2/4MB pages!
1567	*/
1568	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1569	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1570	{
1571	PVM pVM = pVCpu->CTX_SUFF(pVM);
1572	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1573
1574	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1575	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1576	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1577
1578	if (pShwPage->fDirty)
1579	{
1580	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1581	PGSTPT pGstPT;
1582
1583	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirty].aPage[0];
1584	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1585	pGstPT->a[iPTDst].u = PteSrc.u;
1586	}
1587	#else
1588	Assert(!pShwPage->fDirty);
1589	#endif
1590
1591	if ( PteSrc.n.u1Present
1592	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1593	{
1594	/*
1595	* Find the ram range.
1596	*/
1597	PPGMPAGE pPage;
1598	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc), &pPage);
1599	if (RT_SUCCESS(rc))
1600	{
1601	/* Ignore ballooned pages.
1602	Don't return errors or use a fatal assert here as part of a
1603	shadow sync range might included ballooned pages. */
1604	if (PGM_PAGE_IS_BALLOONED(pPage))
1605	{
1606	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1607	return;
1608	}
1609
1610	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1611	/* Make the page writable if necessary. */
1612	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1613	&& ( PGM_PAGE_IS_ZERO(pPage)
1614	\|\| ( PteSrc.n.u1Write
1615	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1616	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1617	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1618	# endif
1619	# ifdef VBOX_WITH_PAGE_SHARING
1620	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1621	# endif
1622	)
1623	)
1624	)
1625	{
1626	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
1627	AssertRC(rc);
1628	}
1629	#endif
1630
1631	/*
1632	* Make page table entry.
1633	*/
1634	SHWPTE PteDst;
1635	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1636	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc), &PteDst);
1637	else
1638	{
1639	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1640	/*
1641	* If the page or page directory entry is not marked accessed,
1642	* we mark the page not present.
1643	*/
1644	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1645	{
1646	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1647	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1648	SHW_PTE_SET(PteDst, 0);
1649	}
1650	/*
1651	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1652	* when the page is modified.
1653	*/
1654	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1655	{
1656	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1657	SHW_PTE_SET(PteDst,
1658	GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc)
1659	\| PGM_PAGE_GET_HCPHYS(pPage)
1660	\| PGM_PTFLAGS_TRACK_DIRTY);
1661	SHW_PTE_SET_RO(PteDst);
1662	}
1663	else
1664	#endif
1665	{
1666	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1667	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1668	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1669	PteDst.n.u1Present = 1;
1670	PteDst.n.u1Write = 1;
1671	PteDst.n.u1Execute = 1;
1672	PteDst.n.u1IgnorePAT = 1;
1673	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1674	/* PteDst.n.u1Size = 0 */
1675	#else
1676	SHW_PTE_SET(PteDst, GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
1677	#endif
1678	}
1679
1680	/*
1681	* Make sure only allocated pages are mapped writable.
1682	*/
1683	if ( SHW_PTE_IS_P_RW(PteDst)
1684	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1685	{
1686	/* Still applies to shared pages. */
1687	Assert(!PGM_PAGE_IS_ZERO(pPage));
1688	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1689	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", (RTGCPHYS)GST_GET_PTE_GCPHYS(PteSrc), pPage, iPTDst));
1690	}
1691	}
1692
1693	/*
1694	* Keep user track up to date.
1695	*/
1696	if (SHW_PTE_IS_P(PteDst))
1697	{
1698	if (!SHW_PTE_IS_P(*pPteDst))
1699	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1700	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1701	{
1702	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1703	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1704	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1705	}
1706	}
1707	else if (SHW_PTE_IS_P(*pPteDst))
1708	{
1709	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1710	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1711	}
1712
1713	/*
1714	* Update statistics and commit the entry.
1715	*/
1716	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1717	if (!PteSrc.n.u1Global)
1718	pShwPage->fSeenNonGlobal = true;
1719	#endif
1720	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1721	return;
1722	}
1723
1724	/** @todo count these three different kinds. */
1725	Log2(("SyncPageWorker: invalid address in Pte\n"));
1726	}
1727	else if (!PteSrc.n.u1Present)
1728	Log2(("SyncPageWorker: page not present in Pte\n"));
1729	else
1730	Log2(("SyncPageWorker: invalid Pte\n"));
1731
1732	/*
1733	* The page is not present or the PTE is bad. Replace the shadow PTE by
1734	* an empty entry, making sure to keep the user tracking up to date.
1735	*/
1736	if (SHW_PTE_IS_P(*pPteDst))
1737	{
1738	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1739	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1740	}
1741	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1742	}
1743
1744
1745	/**
1746	* Syncs a guest OS page.
1747	*
1748	* There are no conflicts at this point, neither is there any need for
1749	* page table allocations.
1750	*
1751	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1752	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1753	*
1754	* @returns VBox status code.
1755	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1756	* @param pVCpu The VMCPU handle.
1757	* @param PdeSrc Page directory entry of the guest.
1758	* @param GCPtrPage Guest context page address.
1759	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1760	* @param uErr Fault error (X86_TRAP_PF_*).
1761	*/
1762	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1763	{
1764	PVM pVM = pVCpu->CTX_SUFF(pVM);
1765	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1766	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1767
1768	Assert(PGMIsLockOwner(pVM));
1769
1770	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1771	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1772	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1773	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1774	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1775
1776	/*
1777	* Assert preconditions.
1778	*/
1779	Assert(PdeSrc.n.u1Present);
1780	Assert(cPages);
1781	# if 0 /* rarely useful; leave for debugging. */
1782	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1783	# endif
1784
1785	/*
1786	* Get the shadow PDE, find the shadow page table in the pool.
1787	*/
1788	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1789	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1790	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1791
1792	/* Fetch the pgm pool shadow descriptor. */
1793	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1794	Assert(pShwPde);
1795
1796	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1797	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1798	PPGMPOOLPAGE pShwPde = NULL;
1799	PX86PDPAE pPDDst;
1800
1801	/* Fetch the pgm pool shadow descriptor. */
1802	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1803	AssertRCSuccessReturn(rc2, rc2);
1804	Assert(pShwPde);
1805
1806	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1807	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1808
1809	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1810	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1811	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1812	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1813	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1814
1815	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1816	AssertRCSuccessReturn(rc2, rc2);
1817	Assert(pPDDst && pPdptDst);
1818	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1819	# endif
1820	SHWPDE PdeDst = *pPdeDst;
1821
1822	/*
1823	* - In the guest SMP case we could have blocked while another VCPU reused
1824	* this page table.
1825	* - With W7-64 we may also take this path when the the A bit is cleared on
1826	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1827	* relevant TLB entries. If we're write monitoring any page mapped by
1828	* the modified entry, we may end up here with a "stale" TLB entry.
1829	*/
1830	if (!PdeDst.n.u1Present)
1831	{
1832	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1833	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1834	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1835	if (uErr & X86_TRAP_PF_P)
1836	PGM_INVL_PG(pVCpu, GCPtrPage);
1837	return VINF_SUCCESS; /* force the instruction to be executed again. */
1838	}
1839
1840	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1841	Assert(pShwPage);
1842
1843	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1844	/* Fetch the pgm pool shadow descriptor. */
1845	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1846	Assert(pShwPde);
1847	# endif
1848
1849	/*
1850	* Check that the page is present and that the shadow PDE isn't out of sync.
1851	*/
1852	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1853	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1854	RTGCPHYS GCPhys;
1855	if (!fBigPage)
1856	{
1857	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1858	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1859	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1860	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1861	# endif
1862	}
1863	else
1864	{
1865	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1866	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1867	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1868	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1869	# endif
1870	}
1871	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1872	if ( fPdeValid
1873	&& pShwPage->GCPhys == GCPhys
1874	&& PdeSrc.n.u1Present
1875	&& PdeSrc.n.u1User == PdeDst.n.u1User
1876	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1877	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1878	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1879	# endif
1880	)
1881	{
1882	/*
1883	* Check that the PDE is marked accessed already.
1884	* Since we set the accessed bit before getting here on a #PF, this
1885	* check is only meant for dealing with non-#PF'ing paths.
1886	*/
1887	if (PdeSrc.n.u1Accessed)
1888	{
1889	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1890	if (!fBigPage)
1891	{
1892	/*
1893	* 4KB Page - Map the guest page table.
1894	*/
1895	PGSTPT pPTSrc;
1896	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1897	if (RT_SUCCESS(rc))
1898	{
1899	# ifdef PGM_SYNC_N_PAGES
1900	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1901	if ( cPages > 1
1902	&& !(uErr & X86_TRAP_PF_P)
1903	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1904	{
1905	/*
1906	* This code path is currently only taken when the caller is PGMTrap0eHandler
1907	* for non-present pages!
1908	*
1909	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1910	* deal with locality.
1911	*/
1912	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1913	const unsigned iPTDstPage = iPTDst;
1914	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1915	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1916	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1917	# else
1918	const unsigned offPTSrc = 0;
1919	# endif
1920	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1921	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1922	iPTDst = 0;
1923	else
1924	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1925
1926	for (; iPTDst < iPTDstEnd; iPTDst++)
1927	{
1928	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1929
1930	if ( pPteSrc->n.u1Present
1931	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1932	{
1933	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1934	NOREF(GCPtrCurPage);
1935	#ifndef IN_RING0
1936	/*
1937	* Assuming kernel code will be marked as supervisor - and not as user level
1938	* and executed using a conforming code selector - And marked as readonly.
1939	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1940	*/
1941	PPGMPAGE pPage;
1942	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1943	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1944	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1945	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK))
1946	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1947	)
1948	#endif /* else: CSAM not active */
1949	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1950	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1951	GCPtrCurPage, pPteSrc->n.u1Present,
1952	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
1953	pPteSrc->n.u1User & PdeSrc.n.u1User,
1954	(uint64_t)pPteSrc->u,
1955	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1956	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1957	}
1958	}
1959	}
1960	else
1961	# endif /* PGM_SYNC_N_PAGES */
1962	{
1963	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1964	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1965	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1966	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1967	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1968	GCPtrPage, PteSrc.n.u1Present,
1969	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1970	PteSrc.n.u1User & PdeSrc.n.u1User,
1971	(uint64_t)PteSrc.u,
1972	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1973	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1974	}
1975	}
1976	else /* MMIO or invalid page: emulated in #PF handler. */
1977	{
1978	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
1979	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
1980	}
1981	}
1982	else
1983	{
1984	/*
1985	* 4/2MB page - lazy syncing shadow 4K pages.
1986	* (There are many causes of getting here, it's no longer only CSAM.)
1987	*/
1988	/* Calculate the GC physical address of this 4KB shadow page. */
1989	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1990	/* Find ram range. */
1991	PPGMPAGE pPage;
1992	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1993	if (RT_SUCCESS(rc))
1994	{
1995	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
1996
1997	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1998	/* Try to make the page writable if necessary. */
1999	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2000	&& ( PGM_PAGE_IS_ZERO(pPage)
2001	\|\| ( PdeSrc.n.u1Write
2002	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2003	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2004	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2005	# endif
2006	# ifdef VBOX_WITH_PAGE_SHARING
2007	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2008	# endif
2009	)
2010	)
2011	)
2012	{
2013	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2014	AssertRC(rc);
2015	}
2016	# endif
2017
2018	/*
2019	* Make shadow PTE entry.
2020	*/
2021	SHWPTE PteDst;
2022	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2023	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2024	else
2025	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2026
2027	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2028	if ( SHW_PTE_IS_P(PteDst)
2029	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2030	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2031
2032	/* Make sure only allocated pages are mapped writable. */
2033	if ( SHW_PTE_IS_P_RW(PteDst)
2034	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2035	{
2036	/* Still applies to shared pages. */
2037	Assert(!PGM_PAGE_IS_ZERO(pPage));
2038	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2039	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2040	}
2041
2042	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2043
2044	/*
2045	* If the page is not flagged as dirty and is writable, then make it read-only
2046	* at PD level, so we can set the dirty bit when the page is modified.
2047	*
2048	* ASSUMES that page access handlers are implemented on page table entry level.
2049	* Thus we will first catch the dirty access and set PDE.D and restart. If
2050	* there is an access handler, we'll trap again and let it work on the problem.
2051	*/
2052	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2053	* As for invlpg, it simply frees the whole shadow PT.
2054	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2055	if ( !PdeSrc.b.u1Dirty
2056	&& PdeSrc.b.u1Write)
2057	{
2058	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2059	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2060	PdeDst.n.u1Write = 0;
2061	}
2062	else
2063	{
2064	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2065	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2066	}
2067	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2068	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2069	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2070	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2071	}
2072	else
2073	{
2074	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2075	/** @todo must wipe the shadow page table entry in this
2076	* case. */
2077	}
2078	}
2079	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2080	return VINF_SUCCESS;
2081	}
2082
2083	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2084	}
2085	else if (fPdeValid)
2086	{
2087	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2088	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2089	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2090	}
2091	else
2092	{
2093	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2094	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2095	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2096	}
2097
2098	/*
2099	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2100	* Yea, I'm lazy.
2101	*/
2102	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2103	ASMAtomicWriteSize(pPdeDst, 0);
2104
2105	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2106	PGM_INVL_VCPU_TLBS(pVCpu);
2107	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2108
2109
2110	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2111	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2112	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2113	&& !defined(IN_RC)
2114
2115	# ifdef PGM_SYNC_N_PAGES
2116	/*
2117	* Get the shadow PDE, find the shadow page table in the pool.
2118	*/
2119	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2120	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2121
2122	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2123	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2124
2125	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2126	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2127	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2128	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2129	X86PDEPAE PdeDst;
2130	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2131
2132	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2133	AssertRCSuccessReturn(rc, rc);
2134	Assert(pPDDst && pPdptDst);
2135	PdeDst = pPDDst->a[iPDDst];
2136	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2137	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2138	PEPTPD pPDDst;
2139	EPTPDE PdeDst;
2140
2141	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2142	if (rc != VINF_SUCCESS)
2143	{
2144	AssertRC(rc);
2145	return rc;
2146	}
2147	Assert(pPDDst);
2148	PdeDst = pPDDst->a[iPDDst];
2149	# endif
2150	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2151	if (!PdeDst.n.u1Present)
2152	{
2153	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2154	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2155	return VINF_SUCCESS; /* force the instruction to be executed again. */
2156	}
2157
2158	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2159	if (PdeDst.n.u1Size)
2160	{
2161	Assert(pVM->pgm.s.fNestedPaging);
2162	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2163	return VINF_SUCCESS;
2164	}
2165
2166	/* Mask away the page offset. */
2167	GCPtrPage &= ~((RTGCPTR)0xfff);
2168
2169	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2170	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2171
2172	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2173	if ( cPages > 1
2174	&& !(uErr & X86_TRAP_PF_P)
2175	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2176	{
2177	/*
2178	* This code path is currently only taken when the caller is PGMTrap0eHandler
2179	* for non-present pages!
2180	*
2181	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2182	* deal with locality.
2183	*/
2184	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2185	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2186	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2187	iPTDst = 0;
2188	else
2189	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2190	for (; iPTDst < iPTDstEnd; iPTDst++)
2191	{
2192	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2193	{
2194	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2195	GSTPTE PteSrc;
2196
2197	/* Fake the page table entry */
2198	PteSrc.u = GCPtrCurPage;
2199	PteSrc.n.u1Present = 1;
2200	PteSrc.n.u1Dirty = 1;
2201	PteSrc.n.u1Accessed = 1;
2202	PteSrc.n.u1Write = 1;
2203	PteSrc.n.u1User = 1;
2204
2205	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2206	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2207	GCPtrCurPage, PteSrc.n.u1Present,
2208	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2209	PteSrc.n.u1User & PdeSrc.n.u1User,
2210	(uint64_t)PteSrc.u,
2211	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2212	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2213
2214	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2215	break;
2216	}
2217	else
2218	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2219	}
2220	}
2221	else
2222	# endif /* PGM_SYNC_N_PAGES */
2223	{
2224	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2225	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2226	GSTPTE PteSrc;
2227
2228	/* Fake the page table entry */
2229	PteSrc.u = GCPtrCurPage;
2230	PteSrc.n.u1Present = 1;
2231	PteSrc.n.u1Dirty = 1;
2232	PteSrc.n.u1Accessed = 1;
2233	PteSrc.n.u1Write = 1;
2234	PteSrc.n.u1User = 1;
2235	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2236
2237	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}PteDst=%08llx%s\n",
2238	GCPtrPage, PteSrc.n.u1Present,
2239	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2240	PteSrc.n.u1User & PdeSrc.n.u1User,
2241	(uint64_t)PteSrc.u,
2242	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2243	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2244	}
2245	return VINF_SUCCESS;
2246
2247	#else
2248	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2249	return VERR_INTERNAL_ERROR;
2250	#endif
2251	}
2252
2253
2254	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2255
2256	/**
2257	* CheckPageFault helper for returning a page fault indicating a non-present
2258	* (NP) entry in the page translation structures.
2259	*
2260	* @returns VINF_EM_RAW_GUEST_TRAP.
2261	* @param pVCpu The virtual CPU to operate on.
2262	* @param uErr The error code of the shadow fault. Corrections to
2263	* TRPM's copy will be made if necessary.
2264	* @param GCPtrPage For logging.
2265	* @param uPageFaultLevel For logging.
2266	*/
2267	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2268	{
2269	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2270	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2271	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2272	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2273	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2274
2275	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2276	return VINF_EM_RAW_GUEST_TRAP;
2277	}
2278
2279
2280	/**
2281	* CheckPageFault helper for returning a page fault indicating a reserved bit
2282	* (RSVD) error in the page translation structures.
2283	*
2284	* @returns VINF_EM_RAW_GUEST_TRAP.
2285	* @param pVCpu The virtual CPU to operate on.
2286	* @param uErr The error code of the shadow fault. Corrections to
2287	* TRPM's copy will be made if necessary.
2288	* @param GCPtrPage For logging.
2289	* @param uPageFaultLevel For logging.
2290	*/
2291	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2292	{
2293	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2294	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2295	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2296
2297	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2298	return VINF_EM_RAW_GUEST_TRAP;
2299	}
2300
2301
2302	/**
2303	* CheckPageFault helper for returning a page protection fault (P).
2304	*
2305	* @returns VINF_EM_RAW_GUEST_TRAP.
2306	* @param pVCpu The virtual CPU to operate on.
2307	* @param uErr The error code of the shadow fault. Corrections to
2308	* TRPM's copy will be made if necessary.
2309	* @param GCPtrPage For logging.
2310	* @param uPageFaultLevel For logging.
2311	*/
2312	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2313	{
2314	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2315	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2316	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2317	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2318
2319	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2320	return VINF_EM_RAW_GUEST_TRAP;
2321	}
2322
2323
2324	/**
2325	* Handle dirty bit tracking faults.
2326	*
2327	* @returns VBox status code.
2328	* @param pVCpu The VMCPU handle.
2329	* @param uErr Page fault error code.
2330	* @param pPdeSrc Guest page directory entry.
2331	* @param pPdeDst Shadow page directory entry.
2332	* @param GCPtrPage Guest context page address.
2333	*/
2334	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2335	{
2336	PVM pVM = pVCpu->CTX_SUFF(pVM);
2337	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2338
2339	Assert(PGMIsLockOwner(pVM));
2340
2341	/*
2342	* Handle big page.
2343	*/
2344	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2345	{
2346	if ( pPdeDst->n.u1Present
2347	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2348	{
2349	SHWPDE PdeDst = *pPdeDst;
2350
2351	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2352	Assert(pPdeSrc->b.u1Write);
2353
2354	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2355	* fault again and take this path to only invalidate the entry (see below).
2356	*/
2357	PdeDst.n.u1Write = 1;
2358	PdeDst.n.u1Accessed = 1;
2359	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2360	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2361	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2362	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2363	}
2364
2365	# ifdef IN_RING0
2366	/* Check for stale TLB entry; only applies to the SMP guest case. */
2367	if ( pVM->cCpus > 1
2368	&& pPdeDst->n.u1Write
2369	&& pPdeDst->n.u1Accessed)
2370	{
2371	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2372	if (pShwPage)
2373	{
2374	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2375	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2376	if (SHW_PTE_IS_P_RW(*pPteDst))
2377	{
2378	/* Stale TLB entry. */
2379	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2380	PGM_INVL_PG(pVCpu, GCPtrPage);
2381	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2382	}
2383	}
2384	}
2385	# endif /* IN_RING0 */
2386	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2387	}
2388
2389	/*
2390	* Map the guest page table.
2391	*/
2392	PGSTPT pPTSrc;
2393	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2394	if (RT_FAILURE(rc))
2395	{
2396	AssertRC(rc);
2397	return rc;
2398	}
2399
2400	if (pPdeDst->n.u1Present)
2401	{
2402	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2403	const GSTPTE PteSrc = *pPteSrc;
2404
2405	#ifndef IN_RING0
2406	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2407	* Our individual shadow handlers will provide more information and force a fatal exit.
2408	*/
2409	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2410	{
2411	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2412	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2413	}
2414	#endif
2415	/*
2416	* Map shadow page table.
2417	*/
2418	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2419	if (pShwPage)
2420	{
2421	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2422	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2423	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2424	{
2425	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2426	{
2427	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2428	SHWPTE PteDst = *pPteDst;
2429
2430	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2431	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2432
2433	Assert(pPteSrc->n.u1Write);
2434
2435	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2436	* entry will not harm; write access will simply fault again and
2437	* take this path to only invalidate the entry.
2438	*/
2439	if (RT_LIKELY(pPage))
2440	{
2441	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2442	{
2443	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2444	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2445	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2446	SHW_PTE_SET_RO(PteDst);
2447	}
2448	else
2449	{
2450	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2451	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2452	{
2453	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2454	AssertRC(rc);
2455	}
2456	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2457	SHW_PTE_SET_RW(PteDst);
2458	else
2459	{
2460	/* Still applies to shared pages. */
2461	Assert(!PGM_PAGE_IS_ZERO(pPage));
2462	SHW_PTE_SET_RO(PteDst);
2463	}
2464	}
2465	}
2466	else
2467	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2468
2469	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2470	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2471	PGM_INVL_PG(pVCpu, GCPtrPage);
2472	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2473	}
2474
2475	# ifdef IN_RING0
2476	/* Check for stale TLB entry; only applies to the SMP guest case. */
2477	if ( pVM->cCpus > 1
2478	&& SHW_PTE_IS_RW(*pPteDst)
2479	&& SHW_PTE_IS_A(*pPteDst))
2480	{
2481	/* Stale TLB entry. */
2482	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2483	PGM_INVL_PG(pVCpu, GCPtrPage);
2484	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2485	}
2486	# endif
2487	}
2488	}
2489	else
2490	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2491	}
2492
2493	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2494	}
2495
2496	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2497
2498
2499	/**
2500	* Sync a shadow page table.
2501	*
2502	* The shadow page table is not present in the shadow PDE.
2503	*
2504	* Handles mapping conflicts.
2505	*
2506	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2507	* conflict), and Trap0eHandler.
2508	*
2509	* A precodition for this method is that the shadow PDE is not present. The
2510	* caller must take the PGM lock before checking this and continue to hold it
2511	* when calling this method.
2512	*
2513	* @returns VBox status code.
2514	* @param pVCpu The VMCPU handle.
2515	* @param iPD Page directory index.
2516	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2517	* Assume this is a temporary mapping.
2518	* @param GCPtrPage GC Pointer of the page that caused the fault
2519	*/
2520	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2521	{
2522	PVM pVM = pVCpu->CTX_SUFF(pVM);
2523	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2524
2525	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2526	#if 0 /* rarely useful; leave for debugging. */
2527	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2528	#endif
2529	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2530
2531	Assert(PGMIsLocked(pVM));
2532
2533	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2534	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2535	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2536	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2537	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2538
2539	int rc = VINF_SUCCESS;
2540
2541	/*
2542	* Some input validation first.
2543	*/
2544	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2545
2546	/*
2547	* Get the relevant shadow PDE entry.
2548	*/
2549	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2550	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2551	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2552
2553	/* Fetch the pgm pool shadow descriptor. */
2554	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2555	Assert(pShwPde);
2556
2557	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2558	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2559	PPGMPOOLPAGE pShwPde = NULL;
2560	PX86PDPAE pPDDst;
2561	PSHWPDE pPdeDst;
2562
2563	/* Fetch the pgm pool shadow descriptor. */
2564	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2565	AssertRCSuccessReturn(rc, rc);
2566	Assert(pShwPde);
2567
2568	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2569	pPdeDst = &pPDDst->a[iPDDst];
2570
2571	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2572	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2573	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2574	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2575	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2576	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2577	AssertRCSuccessReturn(rc, rc);
2578	Assert(pPDDst);
2579	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2580	# endif
2581	SHWPDE PdeDst = *pPdeDst;
2582
2583	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2584	/* Fetch the pgm pool shadow descriptor. */
2585	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2586	Assert(pShwPde);
2587	# endif
2588
2589	# ifndef PGM_WITHOUT_MAPPINGS
2590	/*
2591	* Check for conflicts.
2592	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2593	* R3: Simply resolve the conflict.
2594	*/
2595	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2596	{
2597	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2598	# ifndef IN_RING3
2599	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2600	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2601	return VERR_ADDRESS_CONFLICT;
2602
2603	# else /* IN_RING3 */
2604	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2605	Assert(pMapping);
2606	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2607	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2608	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2609	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2610	# else
2611	AssertFailed(); /* can't happen for amd64 */
2612	# endif
2613	if (RT_FAILURE(rc))
2614	{
2615	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2616	return rc;
2617	}
2618	PdeDst = *pPdeDst;
2619	# endif /* IN_RING3 */
2620	}
2621	# endif /* !PGM_WITHOUT_MAPPINGS */
2622	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2623
2624	/*
2625	* Sync the page directory entry.
2626	*/
2627	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2628	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2629	if ( PdeSrc.n.u1Present
2630	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2631	{
2632	/*
2633	* Allocate & map the page table.
2634	*/
2635	PSHWPT pPTDst;
2636	PPGMPOOLPAGE pShwPage;
2637	RTGCPHYS GCPhys;
2638	if (fPageTable)
2639	{
2640	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2641	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2642	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2643	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2644	# endif
2645	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2646	}
2647	else
2648	{
2649	PGMPOOLACCESS enmAccess;
2650	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2651	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2652	# else
2653	const bool fNoExecute = false;
2654	# endif
2655
2656	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2657	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2658	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2659	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2660	# endif
2661	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2662	if (PdeSrc.n.u1User)
2663	{
2664	if (PdeSrc.n.u1Write)
2665	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2666	else
2667	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2668	}
2669	else
2670	{
2671	if (PdeSrc.n.u1Write)
2672	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2673	else
2674	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2675	}
2676	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2677	&pShwPage);
2678	}
2679	if (rc == VINF_SUCCESS)
2680	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2681	else if (rc == VINF_PGM_CACHED_PAGE)
2682	{
2683	/*
2684	* The PT was cached, just hook it up.
2685	*/
2686	if (fPageTable)
2687	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2688	else
2689	{
2690	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2691	/* (see explanation and assumptions further down.) */
2692	if ( !PdeSrc.b.u1Dirty
2693	&& PdeSrc.b.u1Write)
2694	{
2695	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2696	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2697	PdeDst.b.u1Write = 0;
2698	}
2699	}
2700	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2701	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2702	return VINF_SUCCESS;
2703	}
2704	else if (rc == VERR_PGM_POOL_FLUSHED)
2705	{
2706	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2707	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2708	return VINF_PGM_SYNC_CR3;
2709	}
2710	else
2711	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2712	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2713	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2714	* irrelevant at this point. */
2715	PdeDst.u &= X86_PDE_AVL_MASK;
2716	PdeDst.u \|= pShwPage->Core.Key;
2717
2718	/*
2719	* Page directory has been accessed (this is a fault situation, remember).
2720	*/
2721	/** @todo
2722	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2723	* fault situation. What's more, the Trap0eHandler has already set the
2724	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2725	* might need setting the accessed flag.
2726	*
2727	* The best idea is to leave this change to the caller and add an
2728	* assertion that it's set already. */
2729	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2730	if (fPageTable)
2731	{
2732	/*
2733	* Page table - 4KB.
2734	*
2735	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2736	*/
2737	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2738	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2739	PGSTPT pPTSrc;
2740	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2741	if (RT_SUCCESS(rc))
2742	{
2743	/*
2744	* Start by syncing the page directory entry so CSAM's TLB trick works.
2745	*/
2746	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2747	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2748	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2749	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2750
2751	/*
2752	* Directory/page user or supervisor privilege: (same goes for read/write)
2753	*
2754	* Directory Page Combined
2755	* U/S U/S U/S
2756	* 0 0 0
2757	* 0 1 0
2758	* 1 0 0
2759	* 1 1 1
2760	*
2761	* Simple AND operation. Table listed for completeness.
2762	*
2763	*/
2764	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2765	# ifdef PGM_SYNC_N_PAGES
2766	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2767	unsigned iPTDst = iPTBase;
2768	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2769	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2770	iPTDst = 0;
2771	else
2772	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2773	# else /* !PGM_SYNC_N_PAGES */
2774	unsigned iPTDst = 0;
2775	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2776	# endif /* !PGM_SYNC_N_PAGES */
2777	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2778	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2779	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2780	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2781	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2782	# else
2783	const unsigned offPTSrc = 0;
2784	# endif
2785	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2786	{
2787	const unsigned iPTSrc = iPTDst + offPTSrc;
2788	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2789
2790	if (PteSrc.n.u1Present)
2791	{
2792	# ifndef IN_RING0
2793	/*
2794	* Assuming kernel code will be marked as supervisor - and not as user level
2795	* and executed using a conforming code selector - And marked as readonly.
2796	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2797	*/
2798	PPGMPAGE pPage;
2799	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2800	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2801	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2802	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2803	)
2804	# endif
2805	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2806	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2807	GCPtrCur,
2808	PteSrc.n.u1Present,
2809	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2810	PteSrc.n.u1User & PdeSrc.n.u1User,
2811	(uint64_t)PteSrc.u,
2812	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2813	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2814	}
2815	/* else: the page table was cleared by the pool */
2816	} /* for PTEs */
2817	}
2818	}
2819	else
2820	{
2821	/*
2822	* Big page - 2/4MB.
2823	*
2824	* We'll walk the ram range list in parallel and optimize lookups.
2825	* We will only sync on shadow page table at a time.
2826	*/
2827	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2828
2829	/**
2830	* @todo It might be more efficient to sync only a part of the 4MB
2831	* page (similar to what we do for 4KB PDs).
2832	*/
2833
2834	/*
2835	* Start by syncing the page directory entry.
2836	*/
2837	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2838	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2839
2840	/*
2841	* If the page is not flagged as dirty and is writable, then make it read-only
2842	* at PD level, so we can set the dirty bit when the page is modified.
2843	*
2844	* ASSUMES that page access handlers are implemented on page table entry level.
2845	* Thus we will first catch the dirty access and set PDE.D and restart. If
2846	* there is an access handler, we'll trap again and let it work on the problem.
2847	*/
2848	/** @todo move the above stuff to a section in the PGM documentation. */
2849	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2850	if ( !PdeSrc.b.u1Dirty
2851	&& PdeSrc.b.u1Write)
2852	{
2853	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2854	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2855	PdeDst.b.u1Write = 0;
2856	}
2857	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2858	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2859
2860	/*
2861	* Fill the shadow page table.
2862	*/
2863	/* Get address and flags from the source PDE. */
2864	SHWPTE PteDstBase;
2865	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2866
2867	/* Loop thru the entries in the shadow PT. */
2868	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2869	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2870	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2871	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2872	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2873	unsigned iPTDst = 0;
2874	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2875	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2876	{
2877	/* Advance ram range list. */
2878	while (pRam && GCPhys > pRam->GCPhysLast)
2879	pRam = pRam->CTX_SUFF(pNext);
2880	if (pRam && GCPhys >= pRam->GCPhys)
2881	{
2882	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2883	do
2884	{
2885	/* Make shadow PTE. */
2886	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2887	SHWPTE PteDst;
2888
2889	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2890	/* Try to make the page writable if necessary. */
2891	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2892	&& ( PGM_PAGE_IS_ZERO(pPage)
2893	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2894	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2895	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2896	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2897	# endif
2898	# ifdef VBOX_WITH_PAGE_SHARING
2899	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2900	# endif
2901	&& !PGM_PAGE_IS_BALLOONED(pPage))
2902	)
2903	)
2904	{
2905	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2906	AssertRCReturn(rc, rc);
2907	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2908	break;
2909	}
2910	# endif
2911
2912	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2913	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2914	else if (PGM_PAGE_IS_BALLOONED(pPage))
2915	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2916	# ifndef IN_RING0
2917	/*
2918	* Assuming kernel code will be marked as supervisor and not as user level and executed
2919	* using a conforming code selector. Don't check for readonly, as that implies the whole
2920	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2921	*/
2922	else if ( !PdeSrc.n.u1User
2923	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2924	SHW_PTE_SET(PteDst, 0);
2925	# endif
2926	else
2927	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2928
2929	/* Only map writable pages writable. */
2930	if ( SHW_PTE_IS_P_RW(PteDst)
2931	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2932	{
2933	/* Still applies to shared pages. */
2934	Assert(!PGM_PAGE_IS_ZERO(pPage));
2935	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2936	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2937	}
2938
2939	if (SHW_PTE_IS_P(PteDst))
2940	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2941
2942	/* commit it (not atomic, new table) */
2943	pPTDst->a[iPTDst] = PteDst;
2944	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2945	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2946	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2947
2948	/* advance */
2949	GCPhys += PAGE_SIZE;
2950	iHCPage++;
2951	iPTDst++;
2952	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2953	&& GCPhys <= pRam->GCPhysLast);
2954	}
2955	else if (pRam)
2956	{
2957	Log(("Invalid pages at %RGp\n", GCPhys));
2958	do
2959	{
2960	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2961	GCPhys += PAGE_SIZE;
2962	iPTDst++;
2963	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2964	&& GCPhys < pRam->GCPhys);
2965	}
2966	else
2967	{
2968	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2969	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2970	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2971	}
2972	} /* while more PTEs */
2973	} /* 4KB / 4MB */
2974	}
2975	else
2976	AssertRelease(!PdeDst.n.u1Present);
2977
2978	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2979	if (RT_FAILURE(rc))
2980	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2981	return rc;
2982
2983	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2984	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2985	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2986	&& !defined(IN_RC)
2987
2988	/*
2989	* Validate input a little bit.
2990	*/
2991	int rc = VINF_SUCCESS;
2992	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2993	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2994	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2995
2996	/* Fetch the pgm pool shadow descriptor. */
2997	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2998	Assert(pShwPde);
2999
3000	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3001	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3002	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3003	PX86PDPAE pPDDst;
3004	PSHWPDE pPdeDst;
3005
3006	/* Fetch the pgm pool shadow descriptor. */
3007	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3008	AssertRCSuccessReturn(rc, rc);
3009	Assert(pShwPde);
3010
3011	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3012	pPdeDst = &pPDDst->a[iPDDst];
3013
3014	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3015	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3016	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3017	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3018	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3019	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3020	AssertRCSuccessReturn(rc, rc);
3021	Assert(pPDDst);
3022	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3023
3024	/* Fetch the pgm pool shadow descriptor. */
3025	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3026	Assert(pShwPde);
3027
3028	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3029	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3030	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3031	PEPTPD pPDDst;
3032	PEPTPDPT pPdptDst;
3033
3034	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3035	if (rc != VINF_SUCCESS)
3036	{
3037	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3038	AssertRC(rc);
3039	return rc;
3040	}
3041	Assert(pPDDst);
3042	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3043
3044	/* Fetch the pgm pool shadow descriptor. */
3045	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3046	Assert(pShwPde);
3047	# endif
3048	SHWPDE PdeDst = *pPdeDst;
3049
3050	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3051	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3052
3053	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3054	if (BTH_IS_NP_ACTIVE(pVM))
3055	{
3056	PPGMPAGE pPage;
3057
3058	/* Check if we allocated a big page before for this 2 MB range. */
3059	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3060	if (RT_SUCCESS(rc))
3061	{
3062	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3063
3064	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3065	{
3066	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3067	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3068	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3069	}
3070	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3071	{
3072	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3073	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3074	if (RT_SUCCESS(rc))
3075	{
3076	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3077	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3078	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3079	}
3080	}
3081	else if (PGMIsUsingLargePages(pVM))
3082	{
3083	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3084	if (RT_SUCCESS(rc))
3085	{
3086	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3087	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3088	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3089	}
3090	else
3091	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3092	}
3093
3094	if (HCPhys != NIL_RTHCPHYS)
3095	{
3096	PdeDst.u &= X86_PDE_AVL_MASK;
3097	PdeDst.u \|= HCPhys;
3098	PdeDst.n.u1Present = 1;
3099	PdeDst.n.u1Write = 1;
3100	PdeDst.b.u1Size = 1;
3101	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3102	PdeDst.n.u1Execute = 1;
3103	PdeDst.b.u1IgnorePAT = 1;
3104	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3105	# else
3106	PdeDst.n.u1User = 1;
3107	# endif
3108	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3109
3110	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3111	/* Add a reference to the first page only. */
3112	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3113
3114	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3115	return VINF_SUCCESS;
3116	}
3117	}
3118	}
3119	# endif /* HC_ARCH_BITS == 64 */
3120
3121	GSTPDE PdeSrc;
3122	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3123	PdeSrc.n.u1Present = 1;
3124	PdeSrc.n.u1Write = 1;
3125	PdeSrc.n.u1Accessed = 1;
3126	PdeSrc.n.u1User = 1;
3127
3128	/*
3129	* Allocate & map the page table.
3130	*/
3131	PSHWPT pPTDst;
3132	PPGMPOOLPAGE pShwPage;
3133	RTGCPHYS GCPhys;
3134
3135	/* Virtual address = physical address */
3136	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3137	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3138
3139	if ( rc == VINF_SUCCESS
3140	\|\| rc == VINF_PGM_CACHED_PAGE)
3141	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3142	else
3143	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3144
3145	PdeDst.u &= X86_PDE_AVL_MASK;
3146	PdeDst.u \|= pShwPage->Core.Key;
3147	PdeDst.n.u1Present = 1;
3148	PdeDst.n.u1Write = 1;
3149	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3150	PdeDst.n.u1Execute = 1;
3151	# else
3152	PdeDst.n.u1User = 1;
3153	PdeDst.n.u1Accessed = 1;
3154	# endif
3155	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3156
3157	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
3158	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3159	return rc;
3160
3161	#else
3162	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3163	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3164	return VERR_INTERNAL_ERROR;
3165	#endif
3166	}
3167
3168
3169
3170	/**
3171	* Prefetch a page/set of pages.
3172	*
3173	* Typically used to sync commonly used pages before entering raw mode
3174	* after a CR3 reload.
3175	*
3176	* @returns VBox status code.
3177	* @param pVCpu The VMCPU handle.
3178	* @param GCPtrPage Page to invalidate.
3179	*/
3180	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3181	{
3182	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3183	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3184	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3185	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3186	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3187	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3188	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3189
3190	/*
3191	* Check that all Guest levels thru the PDE are present, getting the
3192	* PD and PDE in the processes.
3193	*/
3194	int rc = VINF_SUCCESS;
3195	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3196	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3197	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3198	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3199	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3200	unsigned iPDSrc;
3201	X86PDPE PdpeSrc;
3202	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3203	if (!pPDSrc)
3204	return VINF_SUCCESS; /* not present */
3205	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3206	unsigned iPDSrc;
3207	PX86PML4E pPml4eSrc;
3208	X86PDPE PdpeSrc;
3209	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3210	if (!pPDSrc)
3211	return VINF_SUCCESS; /* not present */
3212	# endif
3213	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3214	# else
3215	PGSTPD pPDSrc = NULL;
3216	const unsigned iPDSrc = 0;
3217	GSTPDE PdeSrc;
3218
3219	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3220	PdeSrc.n.u1Present = 1;
3221	PdeSrc.n.u1Write = 1;
3222	PdeSrc.n.u1Accessed = 1;
3223	PdeSrc.n.u1User = 1;
3224	# endif
3225
3226	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3227	{
3228	PVM pVM = pVCpu->CTX_SUFF(pVM);
3229	pgmLock(pVM);
3230
3231	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3232	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3233	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3234	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3235	PX86PDPAE pPDDst;
3236	X86PDEPAE PdeDst;
3237	# if PGM_GST_TYPE != PGM_TYPE_PAE
3238	X86PDPE PdpeSrc;
3239
3240	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3241	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3242	# endif
3243	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3244	if (rc != VINF_SUCCESS)
3245	{
3246	pgmUnlock(pVM);
3247	AssertRC(rc);
3248	return rc;
3249	}
3250	Assert(pPDDst);
3251	PdeDst = pPDDst->a[iPDDst];
3252
3253	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3254	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3255	PX86PDPAE pPDDst;
3256	X86PDEPAE PdeDst;
3257
3258	# if PGM_GST_TYPE == PGM_TYPE_PROT
3259	/* AMD-V nested paging */
3260	X86PML4E Pml4eSrc;
3261	X86PDPE PdpeSrc;
3262	PX86PML4E pPml4eSrc = &Pml4eSrc;
3263
3264	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3265	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3266	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3267	# endif
3268
3269	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3270	if (rc != VINF_SUCCESS)
3271	{
3272	pgmUnlock(pVM);
3273	AssertRC(rc);
3274	return rc;
3275	}
3276	Assert(pPDDst);
3277	PdeDst = pPDDst->a[iPDDst];
3278	# endif
3279	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3280	{
3281	if (!PdeDst.n.u1Present)
3282	{
3283	/** @todo r=bird: This guy will set the A bit on the PDE,
3284	* probably harmless. */
3285	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3286	}
3287	else
3288	{
3289	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3290	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3291	* makes no sense to prefetch more than one page.
3292	*/
3293	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3294	if (RT_SUCCESS(rc))
3295	rc = VINF_SUCCESS;
3296	}
3297	}
3298	pgmUnlock(pVM);
3299	}
3300	return rc;
3301
3302	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3303	return VINF_SUCCESS; /* ignore */
3304	#else
3305	AssertCompile(0);
3306	#endif
3307	}
3308
3309
3310
3311
3312	/**
3313	* Syncs a page during a PGMVerifyAccess() call.
3314	*
3315	* @returns VBox status code (informational included).
3316	* @param pVCpu The VMCPU handle.
3317	* @param GCPtrPage The address of the page to sync.
3318	* @param fPage The effective guest page flags.
3319	* @param uErr The trap error code.
3320	* @remarks This will normally never be called on invalid guest page
3321	* translation entries.
3322	*/
3323	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3324	{
3325	PVM pVM = pVCpu->CTX_SUFF(pVM);
3326
3327	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3328
3329	Assert(!pVM->pgm.s.fNestedPaging);
3330	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3331	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3332	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3333	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3334	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3335	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3336	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3337
3338	# ifndef IN_RING0
3339	if (!(fPage & X86_PTE_US))
3340	{
3341	/*
3342	* Mark this page as safe.
3343	*/
3344	/** @todo not correct for pages that contain both code and data!! */
3345	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3346	CSAMMarkPage(pVM, GCPtrPage, true);
3347	}
3348	# endif
3349
3350	/*
3351	* Get guest PD and index.
3352	*/
3353	/** @todo Performance: We've done all this a jiffy ago in the
3354	* PGMGstGetPage call. */
3355	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3356	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3357	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3358	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3359
3360	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3361	unsigned iPDSrc = 0;
3362	X86PDPE PdpeSrc;
3363	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3364	if (RT_UNLIKELY(!pPDSrc))
3365	{
3366	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3367	return VINF_EM_RAW_GUEST_TRAP;
3368	}
3369
3370	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3371	unsigned iPDSrc = 0; /* shut up gcc */
3372	PX86PML4E pPml4eSrc = NULL; /* ditto */
3373	X86PDPE PdpeSrc;
3374	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3375	if (RT_UNLIKELY(!pPDSrc))
3376	{
3377	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3378	return VINF_EM_RAW_GUEST_TRAP;
3379	}
3380	# endif
3381
3382	# else /* !PGM_WITH_PAGING */
3383	PGSTPD pPDSrc = NULL;
3384	const unsigned iPDSrc = 0;
3385	# endif /* !PGM_WITH_PAGING */
3386	int rc = VINF_SUCCESS;
3387
3388	pgmLock(pVM);
3389
3390	/*
3391	* First check if the shadow pd is present.
3392	*/
3393	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3394	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3395
3396	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3397	PX86PDEPAE pPdeDst;
3398	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3399	PX86PDPAE pPDDst;
3400	# if PGM_GST_TYPE != PGM_TYPE_PAE
3401	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3402	X86PDPE PdpeSrc;
3403	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3404	# endif
3405	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3406	if (rc != VINF_SUCCESS)
3407	{
3408	pgmUnlock(pVM);
3409	AssertRC(rc);
3410	return rc;
3411	}
3412	Assert(pPDDst);
3413	pPdeDst = &pPDDst->a[iPDDst];
3414
3415	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3416	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3417	PX86PDPAE pPDDst;
3418	PX86PDEPAE pPdeDst;
3419
3420	# if PGM_GST_TYPE == PGM_TYPE_PROT
3421	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3422	X86PML4E Pml4eSrc;
3423	X86PDPE PdpeSrc;
3424	PX86PML4E pPml4eSrc = &Pml4eSrc;
3425	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3426	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3427	# endif
3428
3429	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3430	if (rc != VINF_SUCCESS)
3431	{
3432	pgmUnlock(pVM);
3433	AssertRC(rc);
3434	return rc;
3435	}
3436	Assert(pPDDst);
3437	pPdeDst = &pPDDst->a[iPDDst];
3438	# endif
3439
3440	if (!pPdeDst->n.u1Present)
3441	{
3442	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3443	if (rc != VINF_SUCCESS)
3444	{
3445	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3446	pgmUnlock(pVM);
3447	AssertRC(rc);
3448	return rc;
3449	}
3450	}
3451
3452	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3453	/* Check for dirty bit fault */
3454	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3455	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3456	Log(("PGMVerifyAccess: success (dirty)\n"));
3457	else
3458	# endif
3459	{
3460	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3461	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3462	# else
3463	GSTPDE PdeSrc;
3464	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3465	PdeSrc.n.u1Present = 1;
3466	PdeSrc.n.u1Write = 1;
3467	PdeSrc.n.u1Accessed = 1;
3468	PdeSrc.n.u1User = 1;
3469	# endif
3470
3471	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3472	if (uErr & X86_TRAP_PF_US)
3473	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3474	else /* supervisor */
3475	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3476
3477	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3478	if (RT_SUCCESS(rc))
3479	{
3480	/* Page was successfully synced */
3481	Log2(("PGMVerifyAccess: success (sync)\n"));
3482	rc = VINF_SUCCESS;
3483	}
3484	else
3485	{
3486	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3487	rc = VINF_EM_RAW_GUEST_TRAP;
3488	}
3489	}
3490	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3491	pgmUnlock(pVM);
3492	return rc;
3493
3494	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3495
3496	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3497	return VERR_INTERNAL_ERROR;
3498	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3499	}
3500
3501
3502	/**
3503	* Syncs the paging hierarchy starting at CR3.
3504	*
3505	* @returns VBox status code, no specials.
3506	* @param pVCpu The VMCPU handle.
3507	* @param cr0 Guest context CR0 register
3508	* @param cr3 Guest context CR3 register
3509	* @param cr4 Guest context CR4 register
3510	* @param fGlobal Including global page directories or not
3511	*/
3512	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3513	{
3514	PVM pVM = pVCpu->CTX_SUFF(pVM);
3515
3516	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3517
3518	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3519
3520	pgmLock(pVM);
3521
3522	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3523	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3524	if (pPool->cDirtyPages)
3525	pgmPoolResetDirtyPages(pVM);
3526	# endif
3527
3528	/*
3529	* Update page access handlers.
3530	* The virtual are always flushed, while the physical are only on demand.
3531	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3532	* have to look into that later because it will have a bad influence on the performance.
3533	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3534	* bird: Yes, but that won't work for aliases.
3535	*/
3536	/** @todo this MUST go away. See #1557. */
3537	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3538	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3539	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3540	pgmUnlock(pVM);
3541	#endif /* !NESTED && !EPT */
3542
3543	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3544	/*
3545	* Nested / EPT - almost no work.
3546	*/
3547	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3548	return VINF_SUCCESS;
3549
3550	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3551	/*
3552	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3553	* out the shadow parts when the guest modifies its tables.
3554	*/
3555	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3556	return VINF_SUCCESS;
3557
3558	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3559
3560	# ifndef PGM_WITHOUT_MAPPINGS
3561	/*
3562	* Check for and resolve conflicts with our guest mappings if they
3563	* are enabled and not fixed.
3564	*/
3565	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3566	{
3567	int rc = pgmMapResolveConflicts(pVM);
3568	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3569	if (rc == VINF_PGM_SYNC_CR3)
3570	{
3571	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3572	return VINF_PGM_SYNC_CR3;
3573	}
3574	}
3575	# else
3576	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3577	# endif
3578	return VINF_SUCCESS;
3579	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3580	}
3581
3582
3583
3584
3585	#ifdef VBOX_STRICT
3586	# ifdef IN_RC
3587	# undef AssertMsgFailed
3588	# define AssertMsgFailed Log
3589	# endif
3590
3591	/**
3592	* Checks that the shadow page table is in sync with the guest one.
3593	*
3594	* @returns The number of errors.
3595	* @param pVM The virtual machine.
3596	* @param pVCpu The VMCPU handle.
3597	* @param cr3 Guest context CR3 register
3598	* @param cr4 Guest context CR4 register
3599	* @param GCPtr Where to start. Defaults to 0.
3600	* @param cb How much to check. Defaults to everything.
3601	*/
3602	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3603	{
3604	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3605	return 0;
3606	#else
3607	unsigned cErrors = 0;
3608	PVM pVM = pVCpu->CTX_SUFF(pVM);
3609	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3610
3611	#if PGM_GST_TYPE == PGM_TYPE_PAE
3612	/** @todo currently broken; crashes below somewhere */
3613	AssertFailed();
3614	#endif
3615
3616	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3617	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3618	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3619
3620	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3621	PPGMCPU pPGM = &pVCpu->pgm.s;
3622	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3623	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3624	# ifndef IN_RING0
3625	RTHCPHYS HCPhys; /* general usage. */
3626	# endif
3627	int rc;
3628
3629	/*
3630	* Check that the Guest CR3 and all its mappings are correct.
3631	*/
3632	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3633	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3634	false);
3635	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3636	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3637	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3638	# else
3639	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3640	# endif
3641	AssertRCReturn(rc, 1);
3642	HCPhys = NIL_RTHCPHYS;
3643	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3644	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3645	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3646	pgmGstGet32bitPDPtr(pVCpu);
3647	RTGCPHYS GCPhys;
3648	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3649	AssertRCReturn(rc, 1);
3650	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3651	# endif
3652	# endif /* !IN_RING0 */
3653
3654	/*
3655	* Get and check the Shadow CR3.
3656	*/
3657	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3658	unsigned cPDEs = X86_PG_ENTRIES;
3659	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3660	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3661	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3662	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3663	# else
3664	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3665	# endif
3666	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3667	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3668	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3669	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3670	# endif
3671	if (cb != ~(RTGCPTR)0)
3672	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3673
3674	/** @todo call the other two PGMAssert() functions. /
3675
3676	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3677	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3678
3679	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3680	{
3681	PPGMPOOLPAGE pShwPdpt = NULL;
3682	PX86PML4E pPml4eSrc;
3683	PX86PML4E pPml4eDst;
3684	RTGCPHYS GCPhysPdptSrc;
3685
3686	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3687	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3688
3689	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3690	if (!pPml4eDst->n.u1Present)
3691	{
3692	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3693	continue;
3694	}
3695
3696	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3697	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3698
3699	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3700	{
3701	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3702	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3703	cErrors++;
3704	continue;
3705	}
3706
3707	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3708	{
3709	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3710	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3711	cErrors++;
3712	continue;
3713	}
3714
3715	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3716	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3717	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3718	{
3719	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3720	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3721	cErrors++;
3722	continue;
3723	}
3724	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3725	{
3726	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3727
3728	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3729	/*
3730	* Check the PDPTEs too.
3731	*/
3732	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3733
3734	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3735	{
3736	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3737	PPGMPOOLPAGE pShwPde = NULL;
3738	PX86PDPE pPdpeDst;
3739	RTGCPHYS GCPhysPdeSrc;
3740	# if PGM_GST_TYPE == PGM_TYPE_PAE
3741	X86PDPE PdpeSrc;
3742	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3743	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3744	# else
3745	PX86PML4E pPml4eSrcIgn;
3746	X86PDPE PdpeSrc;
3747	PX86PDPT pPdptDst;
3748	PX86PDPAE pPDDst;
3749	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3750
3751	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3752	if (rc != VINF_SUCCESS)
3753	{
3754	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3755	GCPtr += 512 * _2M;
3756	continue; /* next PDPTE */
3757	}
3758	Assert(pPDDst);
3759	# endif
3760	Assert(iPDSrc == 0);
3761
3762	pPdpeDst = &pPdptDst->a[iPdpt];
3763
3764	if (!pPdpeDst->n.u1Present)
3765	{
3766	GCPtr += 512 * _2M;
3767	continue; /* next PDPTE */
3768	}
3769
3770	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3771	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3772
3773	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3774	{
3775	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3776	GCPtr += 512 * _2M;
3777	cErrors++;
3778	continue;
3779	}
3780
3781	if (GCPhysPdeSrc != pShwPde->GCPhys)
3782	{
3783	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3784	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3785	# else
3786	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3787	# endif
3788	GCPtr += 512 * _2M;
3789	cErrors++;
3790	continue;
3791	}
3792
3793	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3794	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3795	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3796	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3797	{
3798	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3799	GCPtr += 512 * _2M;
3800	cErrors++;
3801	continue;
3802	}
3803	# endif
3804
3805	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3806	{
3807	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3808	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3809	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3810	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3811	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3812	# endif
3813	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3814	/*
3815	* Iterate the shadow page directory.
3816	*/
3817	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3818	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3819
3820	for (;
3821	iPDDst < cPDEs;
3822	iPDDst++, GCPtr += cIncrement)
3823	{
3824	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3825	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3826	# else
3827	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3828	# endif
3829	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3830	{
3831	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3832	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3833	{
3834	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3835	cErrors++;
3836	continue;
3837	}
3838	}
3839	else if ( (PdeDst.u & X86_PDE_P)
3840	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3841	)
3842	{
3843	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3844	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3845	if (!pPoolPage)
3846	{
3847	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3848	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3849	cErrors++;
3850	continue;
3851	}
3852	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3853
3854	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3855	{
3856	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3857	GCPtr, (uint64_t)PdeDst.u));
3858	cErrors++;
3859	}
3860
3861	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3862	{
3863	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3864	GCPtr, (uint64_t)PdeDst.u));
3865	cErrors++;
3866	}
3867
3868	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3869	if (!PdeSrc.n.u1Present)
3870	{
3871	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3872	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3873	cErrors++;
3874	continue;
3875	}
3876
3877	if ( !PdeSrc.b.u1Size
3878	\|\| !fBigPagesSupported)
3879	{
3880	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3881	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3882	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3883	# endif
3884	}
3885	else
3886	{
3887	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3888	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3889	{
3890	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3891	GCPtr, (uint64_t)PdeSrc.u));
3892	cErrors++;
3893	continue;
3894	}
3895	# endif
3896	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3897	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3898	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3899	# endif
3900	}
3901
3902	if ( pPoolPage->enmKind
3903	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3904	{
3905	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3906	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3907	cErrors++;
3908	}
3909
3910	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3911	if (!pPhysPage)
3912	{
3913	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3914	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3915	cErrors++;
3916	continue;
3917	}
3918
3919	if (GCPhysGst != pPoolPage->GCPhys)
3920	{
3921	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3922	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3923	cErrors++;
3924	continue;
3925	}
3926
3927	if ( !PdeSrc.b.u1Size
3928	\|\| !fBigPagesSupported)
3929	{
3930	/*
3931	* Page Table.
3932	*/
3933	const GSTPT *pPTSrc;
3934	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3935	if (RT_FAILURE(rc))
3936	{
3937	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3938	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3939	cErrors++;
3940	continue;
3941	}
3942	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3943	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3944	{
3945	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3946	// (This problem will go away when/if we shadow multiple CR3s.)
3947	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3948	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3949	cErrors++;
3950	continue;
3951	}
3952	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3953	{
3954	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3955	GCPtr, (uint64_t)PdeDst.u));
3956	cErrors++;
3957	continue;
3958	}
3959
3960	/* iterate the page table. */
3961	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3962	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3963	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3964	# else
3965	const unsigned offPTSrc = 0;
3966	# endif
3967	for (unsigned iPT = 0, off = 0;
3968	iPT < RT_ELEMENTS(pPTDst->a);
3969	iPT++, off += PAGE_SIZE)
3970	{
3971	const SHWPTE PteDst = pPTDst->a[iPT];
3972
3973	/* skip not-present and dirty tracked entries. */
3974	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3975	continue;
3976	Assert(SHW_PTE_IS_P(PteDst));
3977
3978	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3979	if (!PteSrc.n.u1Present)
3980	{
3981	# ifdef IN_RING3
3982	PGMAssertHandlerAndFlagsInSync(pVM);
3983	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
3984	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
3985	0, 0, UINT64_MAX, 99, NULL);
3986	# endif
3987	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
3988	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3989	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
3990	cErrors++;
3991	continue;
3992	}
3993
3994	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3995	# if 1 /** @todo sync accessed bit properly... */
3996	fIgnoreFlags \|= X86_PTE_A;
3997	# endif
3998
3999	/* match the physical addresses */
4000	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4001	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4002
4003	# ifdef IN_RING3
4004	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4005	if (RT_FAILURE(rc))
4006	{
4007	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4008	{
4009	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4010	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4011	cErrors++;
4012	continue;
4013	}
4014	}
4015	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4016	{
4017	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4018	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4019	cErrors++;
4020	continue;
4021	}
4022	# endif
4023
4024	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4025	if (!pPhysPage)
4026	{
4027	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4028	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4029	{
4030	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4031	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4032	cErrors++;
4033	continue;
4034	}
4035	# endif
4036	if (SHW_PTE_IS_RW(PteDst))
4037	{
4038	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4039	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4040	cErrors++;
4041	}
4042	fIgnoreFlags \|= X86_PTE_RW;
4043	}
4044	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4045	{
4046	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4047	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4048	cErrors++;
4049	continue;
4050	}
4051
4052	/* flags */
4053	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4054	{
4055	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4056	{
4057	if (SHW_PTE_IS_RW(PteDst))
4058	{
4059	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4060	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4061	cErrors++;
4062	continue;
4063	}
4064	fIgnoreFlags \|= X86_PTE_RW;
4065	}
4066	else
4067	{
4068	if ( SHW_PTE_IS_P(PteDst)
4069	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4070	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4071	# endif
4072	)
4073	{
4074	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4075	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4076	cErrors++;
4077	continue;
4078	}
4079	fIgnoreFlags \|= X86_PTE_P;
4080	}
4081	}
4082	else
4083	{
4084	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4085	{
4086	if (SHW_PTE_IS_RW(PteDst))
4087	{
4088	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4089	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4090	cErrors++;
4091	continue;
4092	}
4093	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4094	{
4095	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4096	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4097	cErrors++;
4098	continue;
4099	}
4100	if (SHW_PTE_IS_D(PteDst))
4101	{
4102	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4103	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4104	cErrors++;
4105	}
4106	# if 0 /** @todo sync access bit properly... */
4107	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4108	{
4109	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4110	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4111	cErrors++;
4112	}
4113	fIgnoreFlags \|= X86_PTE_RW;
4114	# else
4115	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4116	# endif
4117	}
4118	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4119	{
4120	/* access bit emulation (not implemented). */
4121	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4122	{
4123	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4125	cErrors++;
4126	continue;
4127	}
4128	if (!SHW_PTE_IS_A(PteDst))
4129	{
4130	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4131	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4132	cErrors++;
4133	}
4134	fIgnoreFlags \|= X86_PTE_P;
4135	}
4136	# ifdef DEBUG_sandervl
4137	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4138	# endif
4139	}
4140
4141	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4142	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4143	)
4144	{
4145	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4146	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4147	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4148	cErrors++;
4149	continue;
4150	}
4151	} /* foreach PTE */
4152	}
4153	else
4154	{
4155	/*
4156	* Big Page.
4157	*/
4158	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4159	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4160	{
4161	if (PdeDst.n.u1Write)
4162	{
4163	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4164	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4165	cErrors++;
4166	continue;
4167	}
4168	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4169	{
4170	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4171	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4172	cErrors++;
4173	continue;
4174	}
4175	# if 0 /** @todo sync access bit properly... */
4176	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4177	{
4178	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4179	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4180	cErrors++;
4181	}
4182	fIgnoreFlags \|= X86_PTE_RW;
4183	# else
4184	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4185	# endif
4186	}
4187	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4188	{
4189	/* access bit emulation (not implemented). */
4190	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4191	{
4192	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4193	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4194	cErrors++;
4195	continue;
4196	}
4197	if (!PdeDst.n.u1Accessed)
4198	{
4199	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4200	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4201	cErrors++;
4202	}
4203	fIgnoreFlags \|= X86_PTE_P;
4204	}
4205
4206	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4207	{
4208	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4209	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4210	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4211	cErrors++;
4212	}
4213
4214	/* iterate the page table. */
4215	for (unsigned iPT = 0, off = 0;
4216	iPT < RT_ELEMENTS(pPTDst->a);
4217	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4218	{
4219	const SHWPTE PteDst = pPTDst->a[iPT];
4220
4221	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4222	{
4223	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4224	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4225	cErrors++;
4226	}
4227
4228	/* skip not-present entries. */
4229	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4230	continue;
4231
4232	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4233
4234	/* match the physical addresses */
4235	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4236
4237	# ifdef IN_RING3
4238	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4239	if (RT_FAILURE(rc))
4240	{
4241	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4242	{
4243	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4244	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4245	cErrors++;
4246	}
4247	}
4248	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4249	{
4250	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4251	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4252	cErrors++;
4253	continue;
4254	}
4255	# endif
4256	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4257	if (!pPhysPage)
4258	{
4259	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4260	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4261	{
4262	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4263	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4264	cErrors++;
4265	continue;
4266	}
4267	# endif
4268	if (SHW_PTE_IS_RW(PteDst))
4269	{
4270	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4271	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4272	cErrors++;
4273	}
4274	fIgnoreFlags \|= X86_PTE_RW;
4275	}
4276	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4277	{
4278	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4279	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4280	cErrors++;
4281	continue;
4282	}
4283
4284	/* flags */
4285	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4286	{
4287	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4288	{
4289	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4290	{
4291	if (SHW_PTE_IS_RW(PteDst))
4292	{
4293	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4294	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4295	cErrors++;
4296	continue;
4297	}
4298	fIgnoreFlags \|= X86_PTE_RW;
4299	}
4300	}
4301	else
4302	{
4303	if ( SHW_PTE_IS_P(PteDst)
4304	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4305	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4306	# endif
4307	)
4308	{
4309	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4310	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4311	cErrors++;
4312	continue;
4313	}
4314	fIgnoreFlags \|= X86_PTE_P;
4315	}
4316	}
4317
4318	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4319	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4320	)
4321	{
4322	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4323	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4324	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4325	cErrors++;
4326	continue;
4327	}
4328	} /* for each PTE */
4329	}
4330	}
4331	/* not present */
4332
4333	} /* for each PDE */
4334
4335	} /* for each PDPTE */
4336
4337	} /* for each PML4E */
4338
4339	# ifdef DEBUG
4340	if (cErrors)
4341	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4342	# endif
4343
4344	#endif /* GST == 32BIT, PAE or AMD64 */
4345	return cErrors;
4346
4347	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4348	}
4349	#endif /* VBOX_STRICT */
4350
4351
4352	/**
4353	* Sets up the CR3 for shadow paging
4354	*
4355	* @returns Strict VBox status code.
4356	* @retval VINF_SUCCESS.
4357	*
4358	* @param pVCpu The VMCPU handle.
4359	* @param GCPhysCR3 The physical address in the CR3 register.
4360	*/
4361	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4362	{
4363	PVM pVM = pVCpu->CTX_SUFF(pVM);
4364
4365	/* Update guest paging info. */
4366	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4367	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4368	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4369
4370	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4371
4372	/*
4373	* Map the page CR3 points at.
4374	*/
4375	RTHCPTR HCPtrGuestCR3;
4376	RTHCPHYS HCPhysGuestCR3;
4377	pgmLock(pVM);
4378	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4379	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4380	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4381	/** @todo this needs some reworking wrt. locking? */
4382	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4383	HCPtrGuestCR3 = NIL_RTHCPTR;
4384	int rc = VINF_SUCCESS;
4385	# else
4386	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4387	# endif
4388	pgmUnlock(pVM);
4389	if (RT_SUCCESS(rc))
4390	{
4391	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4392	if (RT_SUCCESS(rc))
4393	{
4394	# ifdef IN_RC
4395	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4396	# endif
4397	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4398	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4399	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4400	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4401	# endif
4402	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4403
4404	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4405	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4406	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4407	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4408	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4409	# endif
4410	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4411	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4412
4413	/*
4414	* Map the 4 PDs too.
4415	*/
4416	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4417	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4418	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4419	{
4420	if (pGuestPDPT->a[i].n.u1Present)
4421	{
4422	RTHCPTR HCPtr;
4423	RTHCPHYS HCPhys;
4424	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4425	pgmLock(pVM);
4426	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4427	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4428	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4429	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4430	HCPtr = NIL_RTHCPTR;
4431	int rc2 = VINF_SUCCESS;
4432	# else
4433	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4434	# endif
4435	pgmUnlock(pVM);
4436	if (RT_SUCCESS(rc2))
4437	{
4438	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4439	AssertRCReturn(rc, rc);
4440
4441	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4442	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4443	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4444	# endif
4445	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4446	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4447	# ifdef IN_RC
4448	PGM_INVL_PG(pVCpu, GCPtr);
4449	# endif
4450	continue;
4451	}
4452	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4453	}
4454
4455	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4456	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4457	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4458	# endif
4459	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4460	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4461	# ifdef IN_RC
4462	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4463	# endif
4464	}
4465
4466	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4467	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4468	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4469	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4470	# endif
4471	# endif
4472	}
4473	else
4474	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4475	}
4476	else
4477	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4478
4479	#else /* prot/real stub */
4480	int rc = VINF_SUCCESS;
4481	#endif
4482
4483	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4484	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4485	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4486	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4487	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4488	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4489
4490	Assert(!pVM->pgm.s.fNestedPaging);
4491
4492	/*
4493	* Update the shadow root page as well since that's not fixed.
4494	*/
4495	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4496	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4497	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4498	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4499	PPGMPOOLPAGE pNewShwPageCR3;
4500
4501	pgmLock(pVM);
4502
4503	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4504	if (pPool->cDirtyPages)
4505	pgmPoolResetDirtyPages(pVM);
4506	# endif
4507
4508	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4509	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4510	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4511	AssertFatalRC(rc);
4512	rc = VINF_SUCCESS;
4513
4514	# ifdef IN_RC
4515	/*
4516	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4517	* state will be inconsistent! Flush important things now while
4518	* we still can and then make sure there are no ring-3 calls.
4519	*/
4520	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4521	VMMRZCallRing3Disable(pVCpu);
4522	# endif
4523
4524	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4525	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4526	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4527	# ifdef IN_RING0
4528	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4529	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4530	# elif defined(IN_RC)
4531	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4532	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4533	# else
4534	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4535	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4536	# endif
4537
4538	# ifndef PGM_WITHOUT_MAPPINGS
4539	/*
4540	* Apply all hypervisor mappings to the new CR3.
4541	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4542	* make sure we check for conflicts in the new CR3 root.
4543	*/
4544	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4545	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4546	# endif
4547	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4548	AssertRCReturn(rc, rc);
4549	# endif
4550
4551	/* Set the current hypervisor CR3. */
4552	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4553	SELMShadowCR3Changed(pVM, pVCpu);
4554
4555	# ifdef IN_RC
4556	/* NOTE: The state is consistent again. */
4557	VMMRZCallRing3Enable(pVCpu);
4558	# endif
4559
4560	/* Clean up the old CR3 root. */
4561	if ( pOldShwPageCR3
4562	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4563	{
4564	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4565	# ifndef PGM_WITHOUT_MAPPINGS
4566	/* Remove the hypervisor mappings from the shadow page table. */
4567	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4568	# endif
4569	/* Mark the page as unlocked; allow flushing again. */
4570	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4571
4572	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4573	}
4574	pgmUnlock(pVM);
4575	# endif
4576
4577	return rc;
4578	}
4579
4580	/**
4581	* Unmaps the shadow CR3.
4582	*
4583	* @returns VBox status, no specials.
4584	* @param pVCpu The VMCPU handle.
4585	*/
4586	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4587	{
4588	LogFlow(("UnmapCR3\n"));
4589
4590	int rc = VINF_SUCCESS;
4591	PVM pVM = pVCpu->CTX_SUFF(pVM);
4592
4593	/*
4594	* Update guest paging info.
4595	*/
4596	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4597	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4598	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4599	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4600	# endif
4601	pVCpu->pgm.s.pGst32BitPdRC = 0;
4602
4603	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4604	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4605	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4606	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4607	# endif
4608	pVCpu->pgm.s.pGstPaePdptRC = 0;
4609	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4610	{
4611	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4612	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4613	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4614	# endif
4615	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4616	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4617	}
4618
4619	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4620	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4621	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4622	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4623	# endif
4624
4625	#else /* prot/real mode stub */
4626	/* nothing to do */
4627	#endif
4628
4629	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4630	/*
4631	* Update shadow paging info.
4632	*/
4633	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4634	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4635	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4636
4637	# if PGM_GST_TYPE != PGM_TYPE_REAL
4638	Assert(!pVM->pgm.s.fNestedPaging);
4639	# endif
4640
4641	pgmLock(pVM);
4642
4643	# ifndef PGM_WITHOUT_MAPPINGS
4644	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4645	/* Remove the hypervisor mappings from the shadow page table. */
4646	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4647	# endif
4648
4649	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4650	{
4651	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4652
4653	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4654
4655	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4656	if (pPool->cDirtyPages)
4657	pgmPoolResetDirtyPages(pVM);
4658	# endif
4659
4660	/* Mark the page as unlocked; allow flushing again. */
4661	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4662
4663	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4664	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4665	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4666	pVCpu->pgm.s.pShwPageCR3RC = 0;
4667	pVCpu->pgm.s.iShwUser = 0;
4668	pVCpu->pgm.s.iShwUserTable = 0;
4669	}
4670	pgmUnlock(pVM);
4671	# endif
4672	#endif /* !IN_RC*/
4673
4674	return rc;
4675	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 32560

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