PGMAllBth.h@ 33105

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1	/* $Id: PGMAllBth.h 32788 2010-09-28 10:08:26Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29
30	/*******************************************************************************
31	* Internal Functions *
32	*******************************************************************************/
33	RT_C_DECLS_BEGIN
34	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
35	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
36	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
37	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
38	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
39	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
40	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
41	#else
42	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
43	#endif
44	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
45	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
46	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
47	#ifdef VBOX_STRICT
48	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
49	#endif
50	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
51	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
52	RT_C_DECLS_END
53
54
55	/*
56	* Filter out some illegal combinations of guest and shadow paging, so we can
57	* remove redundant checks inside functions.
58	*/
59	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
60	# error "Invalid combination; PAE guest implies PAE shadow"
61	#endif
62
63	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
64	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
65	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
74	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
75	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
76	#endif
77
78	#ifndef IN_RING3
79
80	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
81	/**
82	* Deal with a guest page fault.
83	*
84	* @returns Strict VBox status code.
85	* @retval VINF_EM_RAW_GUEST_TRAP
86	* @retval VINF_EM_RAW_EMULATE_INSTR
87	*
88	* @param pVCpu The current CPU.
89	* @param pGstWalk The guest page table walk result.
90	* @param uErr The error code.
91	*/
92	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
93	{
94	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
95	/*
96	* Check for write conflicts with our hypervisor mapping.
97	*
98	* If the guest happens to access a non-present page, where our hypervisor
99	* is currently mapped, then we'll create a #PF storm in the guest.
100	*/
101	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
102	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
103	{
104	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
105	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
106	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
107	return VINF_EM_RAW_EMULATE_INSTR;
108	}
109	# endif
110
111	/*
112	* Calc the error code for the guest trap.
113	*/
114	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
115	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
116	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
117	if (pGstWalk->Core.fBadPhysAddr)
118	{
119	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
120	Assert(!pGstWalk->Core.fNotPresent);
121	}
122	else if (!pGstWalk->Core.fNotPresent)
123	uNewErr \|= X86_TRAP_PF_P;
124	TRPMSetErrorCode(pVCpu, uNewErr);
125
126	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
127	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
128	return VINF_EM_RAW_GUEST_TRAP;
129	}
130	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
131
132
133	/**
134	* Deal with a guest page fault.
135	*
136	* The caller has taken the PGM lock.
137	*
138	* @returns Strict VBox status code.
139	*
140	* @param pVCpu The current CPU.
141	* @param uErr The error code.
142	* @param pRegFrame The register frame.
143	* @param pvFault The fault address.
144	* @param pPage The guest page at @a pvFault.
145	* @param pGstWalk The guest page table walk result.
146	* @param pfLockTaken PGM lock taken here or not (out). This is true
147	* when we're called.
148	*/
149	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
150	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
151	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
152	, PGSTPTWALK pGstWalk
153	# endif
154	)
155	{
156	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
157	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
158	#endif
159	PVM pVM = pVCpu->CTX_SUFF(pVM);
160	int rc;
161
162	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
163	{
164	/*
165	* Physical page access handler.
166	*/
167	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
168	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
169	# else
170	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
171	# endif
172	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
173	if (pCur)
174	{
175	# ifdef PGM_SYNC_N_PAGES
176	/*
177	* If the region is write protected and we got a page not present fault, then sync
178	* the pages. If the fault was caused by a read, then restart the instruction.
179	* In case of write access continue to the GC write handler.
180	*
181	* ASSUMES that there is only one handler per page or that they have similar write properties.
182	*/
183	if ( !(uErr & X86_TRAP_PF_P)
184	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
185	{
186	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
187	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
188	# else
189	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
190	# endif
191	if ( RT_FAILURE(rc)
192	\|\| !(uErr & X86_TRAP_PF_RW)
193	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
194	{
195	AssertRC(rc);
196	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
197	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
198	return rc;
199	}
200	}
201	# endif
202	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
203	/*
204	* If the access was not thru a #PF(RSVD\|...) resync the page.
205	*/
206	if ( !(uErr & X86_TRAP_PF_RSVD)
207	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
208	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
209	&& pGstWalk->Core.fEffectiveRW
210	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
211	# endif
212	)
213	{
214	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
215	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
216	# else
217	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
218	# endif
219	if ( RT_FAILURE(rc)
220	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
221	{
222	AssertRC(rc);
223	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
224	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
225	return rc;
226	}
227	}
228	# endif
229
230	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
231	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
232	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
233	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
234	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
235	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
236	else
237	{
238	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
239	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
240	}
241
242	if (pCur->CTX_SUFF(pfnHandler))
243	{
244	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
245	void *pvUser = pCur->CTX_SUFF(pvUser);
246	# ifdef IN_RING0
247	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
248	# else
249	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
250	# endif
251
252	STAM_PROFILE_START(&pCur->Stat, h);
253	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
254	{
255	pgmUnlock(pVM);
256	*pfLockTaken = false;
257	}
258
259	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
260
261	# ifdef VBOX_WITH_STATISTICS
262	pgmLock(pVM);
263	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
264	if (pCur)
265	STAM_PROFILE_STOP(&pCur->Stat, h);
266	pgmUnlock(pVM);
267	# endif
268	}
269	else
270	rc = VINF_EM_RAW_EMULATE_INSTR;
271
272	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
273	return rc;
274	}
275	}
276	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
277	else
278	{
279	# ifdef PGM_SYNC_N_PAGES
280	/*
281	* If the region is write protected and we got a page not present fault, then sync
282	* the pages. If the fault was caused by a read, then restart the instruction.
283	* In case of write access continue to the GC write handler.
284	*/
285	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
286	&& !(uErr & X86_TRAP_PF_P))
287	{
288	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
289	if ( RT_FAILURE(rc)
290	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
291	\|\| !(uErr & X86_TRAP_PF_RW))
292	{
293	AssertRC(rc);
294	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
295	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
296	return rc;
297	}
298	}
299	# endif
300	/*
301	* Ok, it's an virtual page access handler.
302	*
303	* Since it's faster to search by address, we'll do that first
304	* and then retry by GCPhys if that fails.
305	*/
306	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
307	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
308	* out of sync, because the page was changed without us noticing it (not-present -> present
309	* without invlpg or mov cr3, xxx).
310	*/
311	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
312	if (pCur)
313	{
314	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
315	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
316	\|\| !(uErr & X86_TRAP_PF_P)
317	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
318	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
319	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
320
321	if ( pvFault - pCur->Core.Key < pCur->cb
322	&& ( uErr & X86_TRAP_PF_RW
323	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
324	{
325	# ifdef IN_RC
326	STAM_PROFILE_START(&pCur->Stat, h);
327	RTGCPTR GCPtrStart = pCur->Core.Key;
328	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
329	pgmUnlock(pVM);
330	*pfLockTaken = false;
331
332	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
333
334	# ifdef VBOX_WITH_STATISTICS
335	pgmLock(pVM);
336	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
337	if (pCur)
338	STAM_PROFILE_STOP(&pCur->Stat, h);
339	pgmUnlock(pVM);
340	# endif
341	# else
342	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
343	# endif
344	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
345	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
346	return rc;
347	}
348	/* Unhandled part of a monitored page */
349	}
350	else
351	{
352	/* Check by physical address. */
353	unsigned iPage;
354	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
355	Assert(RT_SUCCESS(rc) \|\| !pCur);
356	if ( pCur
357	&& ( uErr & X86_TRAP_PF_RW
358	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
359	{
360	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
361	# ifdef IN_RC
362	STAM_PROFILE_START(&pCur->Stat, h);
363	RTGCPTR GCPtrStart = pCur->Core.Key;
364	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
365	pgmUnlock(pVM);
366	*pfLockTaken = false;
367
368	RTGCPTR off = (iPage << PAGE_SHIFT)
369	+ (pvFault & PAGE_OFFSET_MASK)
370	- (GCPtrStart & PAGE_OFFSET_MASK);
371	Assert(off < pCur->cb);
372	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
373
374	# ifdef VBOX_WITH_STATISTICS
375	pgmLock(pVM);
376	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
377	if (pCur)
378	STAM_PROFILE_STOP(&pCur->Stat, h);
379	pgmUnlock(pVM);
380	# endif
381	# else
382	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
383	# endif
384	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
385	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
386	return rc;
387	}
388	}
389	}
390	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
391
392	/*
393	* There is a handled area of the page, but this fault doesn't belong to it.
394	* We must emulate the instruction.
395	*
396	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
397	* we first check if this was a page-not-present fault for a page with only
398	* write access handlers. Restart the instruction if it wasn't a write access.
399	*/
400	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
401
402	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
403	&& !(uErr & X86_TRAP_PF_P))
404	{
405	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
406	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
407	# else
408	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
409	# endif
410	if ( RT_FAILURE(rc)
411	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
412	\|\| !(uErr & X86_TRAP_PF_RW))
413	{
414	AssertRC(rc);
415	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
416	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
417	return rc;
418	}
419	}
420
421	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
422	* It's writing to an unhandled part of the LDT page several million times.
423	*/
424	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
425	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
426	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
427	return rc;
428	} /* if any kind of handler */
429
430
431	/**
432	* #PF Handler for raw-mode guest execution.
433	*
434	* @returns VBox status code (appropriate for trap handling and GC return).
435	*
436	* @param pVCpu VMCPU Handle.
437	* @param uErr The trap error code.
438	* @param pRegFrame Trap register frame.
439	* @param pvFault The fault address.
440	* @param pfLockTaken PGM lock taken here or not (out)
441	*/
442	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
443	{
444	PVM pVM = pVCpu->CTX_SUFF(pVM);
445
446	*pfLockTaken = false;
447
448	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
449	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
450	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
451	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
452	int rc;
453
454	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
455	/*
456	* Walk the guest page translation tables and check if it's a guest fault.
457	*/
458	GSTPTWALK GstWalk;
459	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
460	if (RT_FAILURE_NP(rc))
461	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
462
463	/* assert some GstWalk sanity. */
464	# if PGM_GST_TYPE == PGM_TYPE_AMD64
465	AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u));
466	# endif
467	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
468	AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u));
469	# endif
470	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
471	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
472	Assert(GstWalk.Core.fSucceeded);
473
474	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
475	{
476	if ( ( (uErr & X86_TRAP_PF_RW)
477	&& !GstWalk.Core.fEffectiveRW
478	&& ( (uErr & X86_TRAP_PF_US)
479	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
480	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
481	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
482	)
483	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
484	}
485
486	/*
487	* Set the accessed and dirty flags.
488	*/
489	# if PGM_GST_TYPE == PGM_TYPE_AMD64
490	GstWalk.Pml4e.u \|= X86_PML4E_A;
491	GstWalk.pPml4e->u \|= X86_PML4E_A;
492	GstWalk.Pdpe.u \|= X86_PDPE_A;
493	GstWalk.pPdpe->u \|= X86_PDPE_A;
494	# endif
495	if (GstWalk.Core.fBigPage)
496	{
497	Assert(GstWalk.Pde.b.u1Size);
498	if (uErr & X86_TRAP_PF_RW)
499	{
500	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
501	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
502	}
503	else
504	{
505	GstWalk.Pde.u \|= X86_PDE4M_A;
506	GstWalk.pPde->u \|= X86_PDE4M_A;
507	}
508	}
509	else
510	{
511	Assert(!GstWalk.Pde.b.u1Size);
512	GstWalk.Pde.u \|= X86_PDE_A;
513	GstWalk.pPde->u \|= X86_PDE_A;
514	if (uErr & X86_TRAP_PF_RW)
515	{
516	# ifdef VBOX_WITH_STATISTICS
517	if (!GstWalk.Pte.n.u1Dirty)
518	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
519	else
520	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
521	# endif
522	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
523	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
524	}
525	else
526	{
527	GstWalk.Pte.u \|= X86_PTE_A;
528	GstWalk.pPte->u \|= X86_PTE_A;
529	}
530	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
531	}
532	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
533	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
534	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
535	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
536	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
537
538	/* Take the big lock now. */
539	*pfLockTaken = true;
540	pgmLock(pVM);
541
542	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
543	/*
544	* If it is a reserved bit fault we know that it is an MMIO (access
545	* handler) related fault and can skip some 200 lines of code.
546	*/
547	if (uErr & X86_TRAP_PF_RSVD)
548	{
549	Assert(uErr & X86_TRAP_PF_P);
550	PPGMPAGE pPage;
551	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
552	rc = pgmPhysGetPageEx(&pVM->pgm.s, GstWalk.Core.GCPhys, &pPage);
553	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
554	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
555	pfLockTaken, &GstWalk));
556	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
557	# else
558	rc = pgmPhysGetPageEx(&pVM->pgm.s, (RTGCPHYS)pvFault, &pPage);
559	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
560	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
561	pfLockTaken));
562	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
563	# endif
564	AssertRC(rc);
565	PGM_INVL_PG(pVCpu, pvFault);
566	return rc; /* Restart with the corrected entry. */
567	}
568	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
569
570	/*
571	* Fetch the guest PDE, PDPE and PML4E.
572	*/
573	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
574	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
575	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
576
577	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
578	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
579	PX86PDPAE pPDDst;
580	# if PGM_GST_TYPE == PGM_TYPE_PAE
581	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
582	# else
583	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
584	# endif
585	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
588	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
591	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
592	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
593	# else
594	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
595	# endif
596	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
597
598	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
599	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
600	PEPTPD pPDDst;
601	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
602	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_INTERNAL_ERROR_4);
603	# endif
604	Assert(pPDDst);
605
606	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
607	/*
608	* Dirty page handling.
609	*
610	* If we successfully correct the write protection fault due to dirty bit
611	* tracking, then return immediately.
612	*/
613	if (uErr & X86_TRAP_PF_RW) /* write fault? */
614	{
615	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
616	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
617	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
618	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
619	{
620	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
621	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
622	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
623	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
624	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
625	return VINF_SUCCESS;
626	}
627	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u));
628	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u));
629	}
630
631	# if 0 /* rarely useful; leave for debugging. */
632	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
633	# endif
634	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
635
636	/*
637	* A common case is the not-present error caused by lazy page table syncing.
638	*
639	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
640	* here so we can safely assume that the shadow PT is present when calling
641	* SyncPage later.
642	*
643	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
644	* of mapping conflict and defer to SyncCR3 in R3.
645	* (Again, we do NOT support access handlers for non-present guest pages.)
646	*
647	*/
648	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
649	Assert(GstWalk.Pde.n.u1Present);
650	# endif
651	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
652	&& !pPDDst->a[iPDDst].n.u1Present)
653	{
654	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
655	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
656	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
657	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
658	# else
659	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
660	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
661	# endif
662	if (RT_SUCCESS(rc))
663	return rc;
664	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
665	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
666	return VINF_PGM_SYNC_CR3;
667	}
668
669	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
670	/*
671	* Check if this address is within any of our mappings.
672	*
673	* This is very fast and it's gonna save us a bit of effort below and prevent
674	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
675	* (BTW, it's impossible to have physical access handlers in a mapping.)
676	*/
677	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
678	{
679	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
680	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
681	{
682	if (pvFault < pMapping->GCPtr)
683	break;
684	if (pvFault - pMapping->GCPtr < pMapping->cb)
685	{
686	/*
687	* The first thing we check is if we've got an undetected conflict.
688	*/
689	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
690	{
691	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
692	while (iPT-- > 0)
693	if (GstWalk.pPde[iPT].n.u1Present)
694	{
695	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
696	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
697	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
698	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
699	return VINF_PGM_SYNC_CR3;
700	}
701	}
702
703	/*
704	* Check if the fault address is in a virtual page access handler range.
705	*/
706	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
707	if ( pCur
708	&& pvFault - pCur->Core.Key < pCur->cb
709	&& uErr & X86_TRAP_PF_RW)
710	{
711	# ifdef IN_RC
712	STAM_PROFILE_START(&pCur->Stat, h);
713	pgmUnlock(pVM);
714	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
715	pgmLock(pVM);
716	STAM_PROFILE_STOP(&pCur->Stat, h);
717	# else
718	AssertFailed();
719	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
720	# endif
721	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
722	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
723	return rc;
724	}
725
726	/*
727	* Pretend we're not here and let the guest handle the trap.
728	*/
729	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
730	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
731	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
732	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
733	return VINF_EM_RAW_GUEST_TRAP;
734	}
735	}
736	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
737	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
738
739	/*
740	* Check if this fault address is flagged for special treatment,
741	* which means we'll have to figure out the physical address and
742	* check flags associated with it.
743	*
744	* ASSUME that we can limit any special access handling to pages
745	* in page tables which the guest believes to be present.
746	*/
747	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
748	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
749	# else
750	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
751	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
752	PPGMPAGE pPage;
753	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
754	if (RT_FAILURE(rc))
755	{
756	/*
757	* When the guest accesses invalid physical memory (e.g. probing
758	* of RAM or accessing a remapped MMIO range), then we'll fall
759	* back to the recompiler to emulate the instruction.
760	*/
761	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
762	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
763	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
764	return VINF_EM_RAW_EMULATE_INSTR;
765	}
766
767	/*
768	* Any handlers for this page?
769	*/
770	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
771	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
772	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
773	&GstWalk));
774	# else
775	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
776	# endif
777
778	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
779
780	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
781	if (uErr & X86_TRAP_PF_P)
782	{
783	/*
784	* The page isn't marked, but it might still be monitored by a virtual page access handler.
785	* (ASSUMES no temporary disabling of virtual handlers.)
786	*/
787	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
788	* we should correct both the shadow page table and physical memory flags, and not only check for
789	* accesses within the handler region but for access to pages with virtual handlers. */
790	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
791	if (pCur)
792	{
793	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
794	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
795	\|\| !(uErr & X86_TRAP_PF_P)
796	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
797	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
798
799	if ( pvFault - pCur->Core.Key < pCur->cb
800	&& ( uErr & X86_TRAP_PF_RW
801	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
802	{
803	# ifdef IN_RC
804	STAM_PROFILE_START(&pCur->Stat, h);
805	pgmUnlock(pVM);
806	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
807	pgmLock(pVM);
808	STAM_PROFILE_STOP(&pCur->Stat, h);
809	# else
810	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
811	# endif
812	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
813	return rc;
814	}
815	}
816	}
817	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
818
819	/*
820	* We are here only if page is present in Guest page tables and
821	* trap is not handled by our handlers.
822	*
823	* Check it for page out-of-sync situation.
824	*/
825	if (!(uErr & X86_TRAP_PF_P))
826	{
827	/*
828	* Page is not present in our page tables. Try to sync it!
829	*/
830	if (uErr & X86_TRAP_PF_US)
831	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
832	else /* supervisor */
833	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
834
835	if (PGM_PAGE_IS_BALLOONED(pPage))
836	{
837	/* Emulate reads from ballooned pages as they are not present in
838	our shadow page tables. (Required for e.g. Solaris guests; soft
839	ecc, random nr generator.) */
840	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
841	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
842	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
843	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
844	return rc;
845	}
846
847	# if defined(LOG_ENABLED) && !defined(IN_RING0)
848	RTGCPHYS GCPhys2;
849	uint64_t fPageGst2;
850	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
851	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
852	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
853	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
854	# else
855	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
856	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
857	# endif
858	# endif /* LOG_ENABLED */
859
860	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
861	if ( !GstWalk.Core.fEffectiveUS
862	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
863	{
864	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
865	if ( pvFault == (RTGCPTR)pRegFrame->eip
866	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
867	# ifdef CSAM_DETECT_NEW_CODE_PAGES
868	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
869	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
870	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
871	)
872	{
873	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
874	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
875	if (rc != VINF_SUCCESS)
876	{
877	/*
878	* CSAM needs to perform a job in ring 3.
879	*
880	* Sync the page before going to the host context; otherwise we'll end up in a loop if
881	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
882	*/
883	LogFlow(("CSAM ring 3 job\n"));
884	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
885	AssertRC(rc2);
886
887	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
888	return rc;
889	}
890	}
891	# ifdef CSAM_DETECT_NEW_CODE_PAGES
892	else if ( uErr == X86_TRAP_PF_RW
893	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
894	&& pRegFrame->ecx < 0x10000)
895	{
896	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
897	* to detect loading of new code pages.
898	*/
899
900	/*
901	* Decode the instruction.
902	*/
903	RTGCPTR PC;
904	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
905	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
906	if (rc == VINF_SUCCESS)
907	{
908	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
909	uint32_t cbOp;
910	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
911
912	/* For now we'll restrict this to rep movsw/d instructions */
913	if ( rc == VINF_SUCCESS
914	&& pDis->pCurInstr->opcode == OP_MOVSWD
915	&& (pDis->prefix & PREFIX_REP))
916	{
917	CSAMMarkPossibleCodePage(pVM, pvFault);
918	}
919	}
920	}
921	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
922
923	/*
924	* Mark this page as safe.
925	*/
926	/** @todo not correct for pages that contain both code and data!! */
927	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
928	CSAMMarkPage(pVM, pvFault, true);
929	}
930	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
931	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
932	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
933	# else
934	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
935	# endif
936	if (RT_SUCCESS(rc))
937	{
938	/* The page was successfully synced, return to the guest. */
939	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
940	return VINF_SUCCESS;
941	}
942	}
943	else /* uErr & X86_TRAP_PF_P: */
944	{
945	/*
946	* Write protected pages are made writable when the guest makes the
947	* first write to it. This happens for pages that are shared, write
948	* monitored or not yet allocated.
949	*
950	* We may also end up here when CR0.WP=0 in the guest.
951	*
952	* Also, a side effect of not flushing global PDEs are out of sync
953	* pages due to physical monitored regions, that are no longer valid.
954	* Assume for now it only applies to the read/write flag.
955	*/
956	if (uErr & X86_TRAP_PF_RW)
957	{
958	/*
959	* Check if it is a read-only page.
960	*/
961	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
962	{
963	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
964	Assert(!PGM_PAGE_IS_ZERO(pPage));
965	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
966	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
967
968	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
969	if (rc != VINF_SUCCESS)
970	{
971	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
972	return rc;
973	}
974	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
975	return VINF_EM_NO_MEMORY;
976	}
977
978	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
979	/*
980	* Check to see if we need to emulate the instruction if CR0.WP=0.
981	*/
982	if ( !GstWalk.Core.fEffectiveRW
983	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
984	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
985	{
986	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
987	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
988	if (RT_SUCCESS(rc))
989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
990	else
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
992	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
993	return rc;
994	}
995	# endif
996	/// @todo count the above case; else
997	if (uErr & X86_TRAP_PF_US)
998	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
999	else /* supervisor */
1000	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1001
1002	/*
1003	* Sync the page.
1004	*
1005	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1006	* page is not present, which is not true in this case.
1007	*/
1008	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1009	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1010	# else
1011	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1012	# endif
1013	if (RT_SUCCESS(rc))
1014	{
1015	/*
1016	* Page was successfully synced, return to guest but invalidate
1017	* the TLB first as the page is very likely to be in it.
1018	*/
1019	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1020	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1021	# else
1022	PGM_INVL_PG(pVCpu, pvFault);
1023	# endif
1024	# ifdef VBOX_STRICT
1025	RTGCPHYS GCPhys2;
1026	uint64_t fPageGst;
1027	if (!pVM->pgm.s.fNestedPaging)
1028	{
1029	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1030	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1031	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1032	}
1033	uint64_t fPageShw;
1034	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1035	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1036	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1037	# endif /* VBOX_STRICT */
1038	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1039	return VINF_SUCCESS;
1040	}
1041	}
1042	/** @todo else: why are we here? */
1043
1044	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1045	/*
1046	* Check for VMM page flags vs. Guest page flags consistency.
1047	* Currently only for debug purposes.
1048	*/
1049	if (RT_SUCCESS(rc))
1050	{
1051	/* Get guest page flags. */
1052	uint64_t fPageGst;
1053	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1054	if (RT_SUCCESS(rc))
1055	{
1056	uint64_t fPageShw;
1057	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1058
1059	/*
1060	* Compare page flags.
1061	* Note: we have AVL, A, D bits desynched.
1062	*/
1063	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1064	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1065	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1066	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1067	}
1068	else
1069	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1070	}
1071	else
1072	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1073	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1074	}
1075
1076
1077	/*
1078	* If we get here it is because something failed above, i.e. most like guru
1079	* meditiation time.
1080	*/
1081	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1082	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1083	return rc;
1084
1085	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1086	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1087	return VERR_INTERNAL_ERROR;
1088	# endif
1089	}
1090	#endif /* !IN_RING3 */
1091
1092
1093	/**
1094	* Emulation of the invlpg instruction.
1095	*
1096	*
1097	* @returns VBox status code.
1098	*
1099	* @param pVCpu The VMCPU handle.
1100	* @param GCPtrPage Page to invalidate.
1101	*
1102	* @remark ASSUMES that the guest is updating before invalidating. This order
1103	* isn't required by the CPU, so this is speculative and could cause
1104	* trouble.
1105	* @remark No TLB shootdown is done on any other VCPU as we assume that
1106	* invlpg emulation is the only reason for calling this function.
1107	* (The guest has to shoot down TLB entries on other CPUs itself)
1108	* Currently true, but keep in mind!
1109	*
1110	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1111	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1112	*/
1113	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1114	{
1115	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1116	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1117	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1118	int rc;
1119	PVM pVM = pVCpu->CTX_SUFF(pVM);
1120	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1121
1122	Assert(PGMIsLockOwner(pVM));
1123
1124	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1125
1126	/*
1127	* Get the shadow PD entry and skip out if this PD isn't present.
1128	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1129	*/
1130	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1131	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1132	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1133
1134	/* Fetch the pgm pool shadow descriptor. */
1135	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1136	Assert(pShwPde);
1137
1138	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1139	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1140	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1141
1142	/* If the shadow PDPE isn't present, then skip the invalidate. */
1143	if (!pPdptDst->a[iPdpt].n.u1Present)
1144	{
1145	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1146	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1147	return VINF_SUCCESS;
1148	}
1149
1150	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1151	PPGMPOOLPAGE pShwPde = NULL;
1152	PX86PDPAE pPDDst;
1153
1154	/* Fetch the pgm pool shadow descriptor. */
1155	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1156	AssertRCSuccessReturn(rc, rc);
1157	Assert(pShwPde);
1158
1159	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1160	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1161
1162	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1163	/* PML4 */
1164	const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
1165	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1166	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1167	PX86PDPAE pPDDst;
1168	PX86PDPT pPdptDst;
1169	PX86PML4E pPml4eDst;
1170	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1171	if (rc != VINF_SUCCESS)
1172	{
1173	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1174	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1175	return VINF_SUCCESS;
1176	}
1177	Assert(pPDDst);
1178
1179	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1180	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1181
1182	if (!pPdpeDst->n.u1Present)
1183	{
1184	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1185	return VINF_SUCCESS;
1186	}
1187
1188	/* Fetch the pgm pool shadow descriptor. */
1189	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1190	Assert(pShwPde);
1191
1192	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1193
1194	const SHWPDE PdeDst = *pPdeDst;
1195	if (!PdeDst.n.u1Present)
1196	{
1197	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1198	return VINF_SUCCESS;
1199	}
1200
1201	/*
1202	* Get the guest PD entry and calc big page.
1203	*/
1204	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1205	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1206	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1207	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1208	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1209	unsigned iPDSrc = 0;
1210	# if PGM_GST_TYPE == PGM_TYPE_PAE
1211	X86PDPE PdpeSrcIgn;
1212	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1213	# else /* AMD64 */
1214	PX86PML4E pPml4eSrcIgn;
1215	X86PDPE PdpeSrcIgn;
1216	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1217	# endif
1218	GSTPDE PdeSrc;
1219
1220	if (pPDSrc)
1221	PdeSrc = pPDSrc->a[iPDSrc];
1222	else
1223	PdeSrc.u = 0;
1224	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1225	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1226
1227	# ifdef IN_RING3
1228	/*
1229	* If a CR3 Sync is pending we may ignore the invalidate page operation
1230	* depending on the kind of sync and if it's a global page or not.
1231	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1232	*/
1233	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1234	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1235	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1236	&& fIsBigPage
1237	&& PdeSrc.b.u1Global
1238	)
1239	)
1240	# else
1241	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1242	# endif
1243	{
1244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1245	return VINF_SUCCESS;
1246	}
1247	# endif /* IN_RING3 */
1248
1249	/*
1250	* Deal with the Guest PDE.
1251	*/
1252	rc = VINF_SUCCESS;
1253	if (PdeSrc.n.u1Present)
1254	{
1255	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1256	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1257	# ifndef PGM_WITHOUT_MAPPING
1258	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1259	{
1260	/*
1261	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1262	*/
1263	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1264	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1265	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1266	}
1267	else
1268	# endif /* !PGM_WITHOUT_MAPPING */
1269	if (!fIsBigPage)
1270	{
1271	/*
1272	* 4KB - page.
1273	*/
1274	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1275	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1276
1277	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1278	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1279	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1280	# endif
1281	if (pShwPage->GCPhys == GCPhys)
1282	{
1283	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1284	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1285
1286	PGSTPT pPTSrc;
1287	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1288	if (RT_SUCCESS(rc))
1289	{
1290	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1291	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1292	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1293	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1294	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1295	GCPtrPage, PteSrc.n.u1Present,
1296	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1297	PteSrc.n.u1User & PdeSrc.n.u1User,
1298	(uint64_t)PteSrc.u,
1299	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1300	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1301	}
1302	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1303	PGM_INVL_PG(pVCpu, GCPtrPage);
1304	}
1305	else
1306	{
1307	/*
1308	* The page table address changed.
1309	*/
1310	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1311	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1312	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1313	ASMAtomicWriteSize(pPdeDst, 0);
1314	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1315	PGM_INVL_VCPU_TLBS(pVCpu);
1316	}
1317	}
1318	else
1319	{
1320	/*
1321	* 2/4MB - page.
1322	*/
1323	/* Before freeing the page, check if anything really changed. */
1324	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1325	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1326	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1327	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1328	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1329	# endif
1330	if ( pShwPage->GCPhys == GCPhys
1331	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1332	{
1333	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1334	/** @todo This test is wrong as it cannot check the G bit!
1335	* FIXME */
1336	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1337	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1338	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1339	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1340	{
1341	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1342	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1343	return VINF_SUCCESS;
1344	}
1345	}
1346
1347	/*
1348	* Ok, the page table is present and it's been changed in the guest.
1349	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1350	* We could do this for some flushes in GC too, but we need an algorithm for
1351	* deciding which 4MB pages containing code likely to be executed very soon.
1352	*/
1353	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1354	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1355	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1356	ASMAtomicWriteSize(pPdeDst, 0);
1357	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1358	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1359	}
1360	}
1361	else
1362	{
1363	/*
1364	* Page directory is not present, mark shadow PDE not present.
1365	*/
1366	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1367	{
1368	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1369	ASMAtomicWriteSize(pPdeDst, 0);
1370	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1371	PGM_INVL_PG(pVCpu, GCPtrPage);
1372	}
1373	else
1374	{
1375	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1376	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1377	}
1378	}
1379	return rc;
1380
1381	#else /* guest real and protected mode */
1382	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1383	return VINF_SUCCESS;
1384	#endif
1385	}
1386
1387
1388	/**
1389	* Update the tracking of shadowed pages.
1390	*
1391	* @param pVCpu The VMCPU handle.
1392	* @param pShwPage The shadow page.
1393	* @param HCPhys The physical page we is being dereferenced.
1394	* @param iPte Shadow PTE index
1395	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1396	*/
1397	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte, RTGCPHYS GCPhysPage)
1398	{
1399	PVM pVM = pVCpu->CTX_SUFF(pVM);
1400
1401	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1402	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1403	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1404
1405	/* Use the hint we retrieved from the cached guest PT. */
1406	if (pShwPage->fDirty)
1407	{
1408	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1409
1410	Assert(pShwPage->cPresent);
1411	Assert(pPool->cPresent);
1412	pShwPage->cPresent--;
1413	pPool->cPresent--;
1414
1415	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysPage);
1416	AssertRelease(pPhysPage);
1417	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1418	return;
1419	}
1420	# endif
1421
1422	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1423	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1424
1425	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1426	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1427	* 2. write protect all shadowed pages. I.e. implement caching.
1428	*/
1429	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1430
1431	/*
1432	* Find the guest address.
1433	*/
1434	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
1435	pRam;
1436	pRam = pRam->CTX_SUFF(pNext))
1437	{
1438	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1439	while (iPage-- > 0)
1440	{
1441	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1442	{
1443	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1444
1445	Assert(pShwPage->cPresent);
1446	Assert(pPool->cPresent);
1447	pShwPage->cPresent--;
1448	pPool->cPresent--;
1449
1450	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1451	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1452	return;
1453	}
1454	}
1455	}
1456
1457	for (;;)
1458	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1459	}
1460
1461
1462	/**
1463	* Update the tracking of shadowed pages.
1464	*
1465	* @param pVCpu The VMCPU handle.
1466	* @param pShwPage The shadow page.
1467	* @param u16 The top 16-bit of the pPage->HCPhys.
1468	* @param pPage Pointer to the guest page. this will be modified.
1469	* @param iPTDst The index into the shadow table.
1470	*/
1471	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1472	{
1473	PVM pVM = pVCpu->CTX_SUFF(pVM);
1474
1475	/*
1476	* Just deal with the simple first time here.
1477	*/
1478	if (!u16)
1479	{
1480	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1481	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1482	/* Save the page table index. */
1483	PGM_PAGE_SET_PTE_INDEX(pPage, iPTDst);
1484	}
1485	else
1486	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1487
1488	/* write back */
1489	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1490	PGM_PAGE_SET_TRACKING(pPage, u16);
1491
1492	/* update statistics. */
1493	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1494	pShwPage->cPresent++;
1495	if (pShwPage->iFirstPresent > iPTDst)
1496	pShwPage->iFirstPresent = iPTDst;
1497	}
1498
1499
1500	/**
1501	* Modifies a shadow PTE to account for access handlers.
1502	*
1503	* @param pVM The VM handle.
1504	* @param pPage The page in question.
1505	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1506	* A (accessed) bit so it can be emulated correctly.
1507	* @param pPteDst The shadow PTE (output). This is temporary storage and
1508	* does not need to be set atomically.
1509	*/
1510	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1511	{
1512	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1513	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1514	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1515	{
1516	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1517	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1518	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1519	pPteDst->n.u1Present = 1;
1520	pPteDst->n.u1Execute = 1;
1521	pPteDst->n.u1IgnorePAT = 1;
1522	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1523	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1524	#else
1525	if (fPteSrc & X86_PTE_A)
1526	{
1527	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1528	SHW_PTE_SET_RO(*pPteDst);
1529	}
1530	else
1531	SHW_PTE_SET(*pPteDst, 0);
1532	#endif
1533	}
1534	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1535	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1536	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1537	&& ( BTH_IS_NP_ACTIVE(pVM)
1538	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1539	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1540	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1541	# endif
1542	)
1543	{
1544	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1545	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1546	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1547	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1548	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1549	pPteDst->n.u1Present = 0;
1550	pPteDst->n.u1Write = 1;
1551	pPteDst->n.u1Execute = 0;
1552	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1553	pPteDst->n.u3EMT = 7;
1554	# else
1555	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1556	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1557	# endif
1558	}
1559	# endif
1560	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1561	else
1562	{
1563	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1564	SHW_PTE_SET(*pPteDst, 0);
1565	}
1566	/** @todo count these kinds of entries. */
1567	}
1568
1569
1570	/**
1571	* Creates a 4K shadow page for a guest page.
1572	*
1573	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1574	* physical address. The PdeSrc argument only the flags are used. No page
1575	* structured will be mapped in this function.
1576	*
1577	* @param pVCpu The VMCPU handle.
1578	* @param pPteDst Destination page table entry.
1579	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1580	* Can safely assume that only the flags are being used.
1581	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1582	* @param pShwPage Pointer to the shadow page.
1583	* @param iPTDst The index into the shadow table.
1584	*
1585	* @remark Not used for 2/4MB pages!
1586	*/
1587	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1588	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1589	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1590	#else
1591	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1592	#endif
1593	{
1594	PVM pVM = pVCpu->CTX_SUFF(pVM);
1595	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1596
1597	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1598	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1599	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1600
1601	if (pShwPage->fDirty)
1602	{
1603	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1604	PGSTPT pGstPT;
1605
1606	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirty].aPage[0];
1607	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1608	pGstPT->a[iPTDst].u = PteSrc.u;
1609	}
1610	#else
1611	Assert(!pShwPage->fDirty);
1612	#endif
1613
1614	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1615	if ( PteSrc.n.u1Present
1616	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1617	#endif
1618	{
1619	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1620	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1621	# endif
1622	/*
1623	* Find the ram range.
1624	*/
1625	PPGMPAGE pPage;
1626	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhysPage, &pPage);
1627	if (RT_SUCCESS(rc))
1628	{
1629	/* Ignore ballooned pages.
1630	Don't return errors or use a fatal assert here as part of a
1631	shadow sync range might included ballooned pages. */
1632	if (PGM_PAGE_IS_BALLOONED(pPage))
1633	{
1634	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1635	return;
1636	}
1637
1638	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1639	/* Make the page writable if necessary. */
1640	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1641	&& ( PGM_PAGE_IS_ZERO(pPage)
1642	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1643	\|\| ( PteSrc.n.u1Write
1644	# else
1645	\|\| ( 1
1646	# endif
1647	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1648	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1649	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1650	# endif
1651	# ifdef VBOX_WITH_PAGE_SHARING
1652	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1653	# endif
1654	)
1655	)
1656	)
1657	{
1658	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1659	AssertRC(rc);
1660	}
1661	#endif
1662
1663	/*
1664	* Make page table entry.
1665	*/
1666	SHWPTE PteDst;
1667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1668	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1669	# else
1670	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1671	# endif
1672	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1673	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1674	else
1675	{
1676	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1677	/*
1678	* If the page or page directory entry is not marked accessed,
1679	* we mark the page not present.
1680	*/
1681	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1682	{
1683	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1684	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1685	SHW_PTE_SET(PteDst, 0);
1686	}
1687	/*
1688	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1689	* when the page is modified.
1690	*/
1691	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1692	{
1693	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1694	SHW_PTE_SET(PteDst,
1695	fGstShwPteFlags
1696	\| PGM_PAGE_GET_HCPHYS(pPage)
1697	\| PGM_PTFLAGS_TRACK_DIRTY);
1698	SHW_PTE_SET_RO(PteDst);
1699	}
1700	else
1701	#endif
1702	{
1703	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1704	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1705	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1706	PteDst.n.u1Present = 1;
1707	PteDst.n.u1Write = 1;
1708	PteDst.n.u1Execute = 1;
1709	PteDst.n.u1IgnorePAT = 1;
1710	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1711	/* PteDst.n.u1Size = 0 */
1712	#else
1713	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1714	#endif
1715	}
1716
1717	/*
1718	* Make sure only allocated pages are mapped writable.
1719	*/
1720	if ( SHW_PTE_IS_P_RW(PteDst)
1721	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1722	{
1723	/* Still applies to shared pages. */
1724	Assert(!PGM_PAGE_IS_ZERO(pPage));
1725	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1726	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1727	}
1728	}
1729
1730	/*
1731	* Keep user track up to date.
1732	*/
1733	if (SHW_PTE_IS_P(PteDst))
1734	{
1735	if (!SHW_PTE_IS_P(*pPteDst))
1736	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1737	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1738	{
1739	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1740	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1741	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1742	}
1743	}
1744	else if (SHW_PTE_IS_P(*pPteDst))
1745	{
1746	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1747	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1748	}
1749
1750	/*
1751	* Update statistics and commit the entry.
1752	*/
1753	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1754	if (!PteSrc.n.u1Global)
1755	pShwPage->fSeenNonGlobal = true;
1756	#endif
1757	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1758	return;
1759	}
1760
1761	/** @todo count these three different kinds. */
1762	Log2(("SyncPageWorker: invalid address in Pte\n"));
1763	}
1764	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1765	else if (!PteSrc.n.u1Present)
1766	Log2(("SyncPageWorker: page not present in Pte\n"));
1767	else
1768	Log2(("SyncPageWorker: invalid Pte\n"));
1769	#endif
1770
1771	/*
1772	* The page is not present or the PTE is bad. Replace the shadow PTE by
1773	* an empty entry, making sure to keep the user tracking up to date.
1774	*/
1775	if (SHW_PTE_IS_P(*pPteDst))
1776	{
1777	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1778	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1779	}
1780	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1781	}
1782
1783
1784	/**
1785	* Syncs a guest OS page.
1786	*
1787	* There are no conflicts at this point, neither is there any need for
1788	* page table allocations.
1789	*
1790	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1791	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1792	*
1793	* @returns VBox status code.
1794	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1795	* @param pVCpu The VMCPU handle.
1796	* @param PdeSrc Page directory entry of the guest.
1797	* @param GCPtrPage Guest context page address.
1798	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1799	* @param uErr Fault error (X86_TRAP_PF_*).
1800	*/
1801	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1802	{
1803	PVM pVM = pVCpu->CTX_SUFF(pVM);
1804	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1805	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1806
1807	Assert(PGMIsLockOwner(pVM));
1808
1809	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1810	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1811	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1812	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1813	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1814
1815	/*
1816	* Assert preconditions.
1817	*/
1818	Assert(PdeSrc.n.u1Present);
1819	Assert(cPages);
1820	# if 0 /* rarely useful; leave for debugging. */
1821	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1822	# endif
1823
1824	/*
1825	* Get the shadow PDE, find the shadow page table in the pool.
1826	*/
1827	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1828	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1829	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1830
1831	/* Fetch the pgm pool shadow descriptor. */
1832	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1833	Assert(pShwPde);
1834
1835	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1836	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1837	PPGMPOOLPAGE pShwPde = NULL;
1838	PX86PDPAE pPDDst;
1839
1840	/* Fetch the pgm pool shadow descriptor. */
1841	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1842	AssertRCSuccessReturn(rc2, rc2);
1843	Assert(pShwPde);
1844
1845	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1846	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1847
1848	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1849	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1850	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1851	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1852	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1853
1854	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1855	AssertRCSuccessReturn(rc2, rc2);
1856	Assert(pPDDst && pPdptDst);
1857	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1858	# endif
1859	SHWPDE PdeDst = *pPdeDst;
1860
1861	/*
1862	* - In the guest SMP case we could have blocked while another VCPU reused
1863	* this page table.
1864	* - With W7-64 we may also take this path when the the A bit is cleared on
1865	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1866	* relevant TLB entries. If we're write monitoring any page mapped by
1867	* the modified entry, we may end up here with a "stale" TLB entry.
1868	*/
1869	if (!PdeDst.n.u1Present)
1870	{
1871	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1872	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1873	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1874	if (uErr & X86_TRAP_PF_P)
1875	PGM_INVL_PG(pVCpu, GCPtrPage);
1876	return VINF_SUCCESS; /* force the instruction to be executed again. */
1877	}
1878
1879	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1880	Assert(pShwPage);
1881
1882	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1883	/* Fetch the pgm pool shadow descriptor. */
1884	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1885	Assert(pShwPde);
1886	# endif
1887
1888	/*
1889	* Check that the page is present and that the shadow PDE isn't out of sync.
1890	*/
1891	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1892	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1893	RTGCPHYS GCPhys;
1894	if (!fBigPage)
1895	{
1896	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1897	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1898	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1899	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1900	# endif
1901	}
1902	else
1903	{
1904	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1905	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1906	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1907	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1908	# endif
1909	}
1910	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1911	if ( fPdeValid
1912	&& pShwPage->GCPhys == GCPhys
1913	&& PdeSrc.n.u1Present
1914	&& PdeSrc.n.u1User == PdeDst.n.u1User
1915	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1916	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1917	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1918	# endif
1919	)
1920	{
1921	/*
1922	* Check that the PDE is marked accessed already.
1923	* Since we set the accessed bit before getting here on a #PF, this
1924	* check is only meant for dealing with non-#PF'ing paths.
1925	*/
1926	if (PdeSrc.n.u1Accessed)
1927	{
1928	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1929	if (!fBigPage)
1930	{
1931	/*
1932	* 4KB Page - Map the guest page table.
1933	*/
1934	PGSTPT pPTSrc;
1935	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1936	if (RT_SUCCESS(rc))
1937	{
1938	# ifdef PGM_SYNC_N_PAGES
1939	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1940	if ( cPages > 1
1941	&& !(uErr & X86_TRAP_PF_P)
1942	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1943	{
1944	/*
1945	* This code path is currently only taken when the caller is PGMTrap0eHandler
1946	* for non-present pages!
1947	*
1948	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1949	* deal with locality.
1950	*/
1951	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1952	const unsigned iPTDstPage = iPTDst;
1953	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1954	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1955	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1956	# else
1957	const unsigned offPTSrc = 0;
1958	# endif
1959	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1960	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1961	iPTDst = 0;
1962	else
1963	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1964
1965	for (; iPTDst < iPTDstEnd; iPTDst++)
1966	{
1967	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1968
1969	if ( pPteSrc->n.u1Present
1970	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1971	{
1972	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1973	NOREF(GCPtrCurPage);
1974	#ifndef IN_RING0
1975	/*
1976	* Assuming kernel code will be marked as supervisor - and not as user level
1977	* and executed using a conforming code selector - And marked as readonly.
1978	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1979	*/
1980	PPGMPAGE pPage;
1981	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1982	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1983	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1984	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK))
1985	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1986	)
1987	#endif /* else: CSAM not active */
1988	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1989	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1990	GCPtrCurPage, pPteSrc->n.u1Present,
1991	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
1992	pPteSrc->n.u1User & PdeSrc.n.u1User,
1993	(uint64_t)pPteSrc->u,
1994	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1995	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1996	}
1997	}
1998	}
1999	else
2000	# endif /* PGM_SYNC_N_PAGES */
2001	{
2002	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2003	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2004	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2005	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2006	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2007	GCPtrPage, PteSrc.n.u1Present,
2008	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2009	PteSrc.n.u1User & PdeSrc.n.u1User,
2010	(uint64_t)PteSrc.u,
2011	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2012	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2013	}
2014	}
2015	else /* MMIO or invalid page: emulated in #PF handler. */
2016	{
2017	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2018	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2019	}
2020	}
2021	else
2022	{
2023	/*
2024	* 4/2MB page - lazy syncing shadow 4K pages.
2025	* (There are many causes of getting here, it's no longer only CSAM.)
2026	*/
2027	/* Calculate the GC physical address of this 4KB shadow page. */
2028	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
2029	/* Find ram range. */
2030	PPGMPAGE pPage;
2031	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
2032	if (RT_SUCCESS(rc))
2033	{
2034	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2035
2036	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2037	/* Try to make the page writable if necessary. */
2038	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2039	&& ( PGM_PAGE_IS_ZERO(pPage)
2040	\|\| ( PdeSrc.n.u1Write
2041	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2042	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2043	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2044	# endif
2045	# ifdef VBOX_WITH_PAGE_SHARING
2046	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2047	# endif
2048	)
2049	)
2050	)
2051	{
2052	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2053	AssertRC(rc);
2054	}
2055	# endif
2056
2057	/*
2058	* Make shadow PTE entry.
2059	*/
2060	SHWPTE PteDst;
2061	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2062	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2063	else
2064	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2065
2066	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2067	if ( SHW_PTE_IS_P(PteDst)
2068	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2069	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2070
2071	/* Make sure only allocated pages are mapped writable. */
2072	if ( SHW_PTE_IS_P_RW(PteDst)
2073	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2074	{
2075	/* Still applies to shared pages. */
2076	Assert(!PGM_PAGE_IS_ZERO(pPage));
2077	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2078	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2079	}
2080
2081	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2082
2083	/*
2084	* If the page is not flagged as dirty and is writable, then make it read-only
2085	* at PD level, so we can set the dirty bit when the page is modified.
2086	*
2087	* ASSUMES that page access handlers are implemented on page table entry level.
2088	* Thus we will first catch the dirty access and set PDE.D and restart. If
2089	* there is an access handler, we'll trap again and let it work on the problem.
2090	*/
2091	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2092	* As for invlpg, it simply frees the whole shadow PT.
2093	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2094	if ( !PdeSrc.b.u1Dirty
2095	&& PdeSrc.b.u1Write)
2096	{
2097	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2098	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2099	PdeDst.n.u1Write = 0;
2100	}
2101	else
2102	{
2103	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2104	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2105	}
2106	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2107	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2108	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2109	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2110	}
2111	else
2112	{
2113	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2114	/** @todo must wipe the shadow page table entry in this
2115	* case. */
2116	}
2117	}
2118	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2119	return VINF_SUCCESS;
2120	}
2121
2122	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2123	}
2124	else if (fPdeValid)
2125	{
2126	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2127	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2128	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2129	}
2130	else
2131	{
2132	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2133	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2134	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2135	}
2136
2137	/*
2138	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2139	* Yea, I'm lazy.
2140	*/
2141	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2142	ASMAtomicWriteSize(pPdeDst, 0);
2143
2144	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2145	PGM_INVL_VCPU_TLBS(pVCpu);
2146	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2147
2148
2149	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2150	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2151	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2152	&& !defined(IN_RC)
2153
2154	# ifdef PGM_SYNC_N_PAGES
2155	/*
2156	* Get the shadow PDE, find the shadow page table in the pool.
2157	*/
2158	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2159	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2160
2161	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2162	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2163
2164	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2165	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2166	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2167	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2168	X86PDEPAE PdeDst;
2169	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2170
2171	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2172	AssertRCSuccessReturn(rc, rc);
2173	Assert(pPDDst && pPdptDst);
2174	PdeDst = pPDDst->a[iPDDst];
2175	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2176	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2177	PEPTPD pPDDst;
2178	EPTPDE PdeDst;
2179
2180	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2181	if (rc != VINF_SUCCESS)
2182	{
2183	AssertRC(rc);
2184	return rc;
2185	}
2186	Assert(pPDDst);
2187	PdeDst = pPDDst->a[iPDDst];
2188	# endif
2189	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2190	if (!PdeDst.n.u1Present)
2191	{
2192	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2193	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2194	return VINF_SUCCESS; /* force the instruction to be executed again. */
2195	}
2196
2197	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2198	if (PdeDst.n.u1Size)
2199	{
2200	Assert(pVM->pgm.s.fNestedPaging);
2201	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2202	return VINF_SUCCESS;
2203	}
2204
2205	/* Mask away the page offset. */
2206	GCPtrPage &= ~((RTGCPTR)0xfff);
2207
2208	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2209	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2210
2211	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2212	if ( cPages > 1
2213	&& !(uErr & X86_TRAP_PF_P)
2214	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2215	{
2216	/*
2217	* This code path is currently only taken when the caller is PGMTrap0eHandler
2218	* for non-present pages!
2219	*
2220	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2221	* deal with locality.
2222	*/
2223	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2224	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2225	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2226	iPTDst = 0;
2227	else
2228	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2229	for (; iPTDst < iPTDstEnd; iPTDst++)
2230	{
2231	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2232	{
2233	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2234
2235	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2236	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2237	GCPtrCurPage,
2238	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2239	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2240
2241	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2242	break;
2243	}
2244	else
2245	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2246	}
2247	}
2248	else
2249	# endif /* PGM_SYNC_N_PAGES */
2250	{
2251	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2252	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2253
2254	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2255
2256	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2257	GCPtrPage,
2258	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2259	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2260	}
2261	return VINF_SUCCESS;
2262
2263	#else
2264	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2265	return VERR_INTERNAL_ERROR;
2266	#endif
2267	}
2268
2269
2270	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2271
2272	/**
2273	* CheckPageFault helper for returning a page fault indicating a non-present
2274	* (NP) entry in the page translation structures.
2275	*
2276	* @returns VINF_EM_RAW_GUEST_TRAP.
2277	* @param pVCpu The virtual CPU to operate on.
2278	* @param uErr The error code of the shadow fault. Corrections to
2279	* TRPM's copy will be made if necessary.
2280	* @param GCPtrPage For logging.
2281	* @param uPageFaultLevel For logging.
2282	*/
2283	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2284	{
2285	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2286	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2287	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2288	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2289	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2290
2291	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2292	return VINF_EM_RAW_GUEST_TRAP;
2293	}
2294
2295
2296	/**
2297	* CheckPageFault helper for returning a page fault indicating a reserved bit
2298	* (RSVD) error in the page translation structures.
2299	*
2300	* @returns VINF_EM_RAW_GUEST_TRAP.
2301	* @param pVCpu The virtual CPU to operate on.
2302	* @param uErr The error code of the shadow fault. Corrections to
2303	* TRPM's copy will be made if necessary.
2304	* @param GCPtrPage For logging.
2305	* @param uPageFaultLevel For logging.
2306	*/
2307	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2308	{
2309	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2310	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2311	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2312
2313	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2314	return VINF_EM_RAW_GUEST_TRAP;
2315	}
2316
2317
2318	/**
2319	* CheckPageFault helper for returning a page protection fault (P).
2320	*
2321	* @returns VINF_EM_RAW_GUEST_TRAP.
2322	* @param pVCpu The virtual CPU to operate on.
2323	* @param uErr The error code of the shadow fault. Corrections to
2324	* TRPM's copy will be made if necessary.
2325	* @param GCPtrPage For logging.
2326	* @param uPageFaultLevel For logging.
2327	*/
2328	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2329	{
2330	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2331	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2332	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2333	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2334
2335	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2336	return VINF_EM_RAW_GUEST_TRAP;
2337	}
2338
2339
2340	/**
2341	* Handle dirty bit tracking faults.
2342	*
2343	* @returns VBox status code.
2344	* @param pVCpu The VMCPU handle.
2345	* @param uErr Page fault error code.
2346	* @param pPdeSrc Guest page directory entry.
2347	* @param pPdeDst Shadow page directory entry.
2348	* @param GCPtrPage Guest context page address.
2349	*/
2350	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage)
2351	{
2352	PVM pVM = pVCpu->CTX_SUFF(pVM);
2353	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2354
2355	Assert(PGMIsLockOwner(pVM));
2356
2357	/*
2358	* Handle big page.
2359	*/
2360	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2361	{
2362	if ( pPdeDst->n.u1Present
2363	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2364	{
2365	SHWPDE PdeDst = *pPdeDst;
2366
2367	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2368	Assert(pPdeSrc->b.u1Write);
2369
2370	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2371	* fault again and take this path to only invalidate the entry (see below).
2372	*/
2373	PdeDst.n.u1Write = 1;
2374	PdeDst.n.u1Accessed = 1;
2375	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2376	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2377	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2378	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2379	}
2380
2381	# ifdef IN_RING0
2382	/* Check for stale TLB entry; only applies to the SMP guest case. */
2383	if ( pVM->cCpus > 1
2384	&& pPdeDst->n.u1Write
2385	&& pPdeDst->n.u1Accessed)
2386	{
2387	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2388	if (pShwPage)
2389	{
2390	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2391	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2392	if (SHW_PTE_IS_P_RW(*pPteDst))
2393	{
2394	/* Stale TLB entry. */
2395	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2396	PGM_INVL_PG(pVCpu, GCPtrPage);
2397	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2398	}
2399	}
2400	}
2401	# endif /* IN_RING0 */
2402	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2403	}
2404
2405	/*
2406	* Map the guest page table.
2407	*/
2408	PGSTPT pPTSrc;
2409	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2410	if (RT_FAILURE(rc))
2411	{
2412	AssertRC(rc);
2413	return rc;
2414	}
2415
2416	if (pPdeDst->n.u1Present)
2417	{
2418	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2419	const GSTPTE PteSrc = *pPteSrc;
2420
2421	#ifndef IN_RING0
2422	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2423	* Our individual shadow handlers will provide more information and force a fatal exit.
2424	*/
2425	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2426	{
2427	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2428	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2429	}
2430	#endif
2431	/*
2432	* Map shadow page table.
2433	*/
2434	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2435	if (pShwPage)
2436	{
2437	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2438	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2439	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2440	{
2441	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2442	{
2443	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(*pPteSrc));
2444	SHWPTE PteDst = *pPteDst;
2445
2446	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2447	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2448
2449	Assert(pPteSrc->n.u1Write);
2450
2451	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2452	* entry will not harm; write access will simply fault again and
2453	* take this path to only invalidate the entry.
2454	*/
2455	if (RT_LIKELY(pPage))
2456	{
2457	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2458	{
2459	AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2460	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2461	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2462	SHW_PTE_SET_RO(PteDst);
2463	}
2464	else
2465	{
2466	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2467	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2468	{
2469	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(*pPteSrc));
2470	AssertRC(rc);
2471	}
2472	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2473	SHW_PTE_SET_RW(PteDst);
2474	else
2475	{
2476	/* Still applies to shared pages. */
2477	Assert(!PGM_PAGE_IS_ZERO(pPage));
2478	SHW_PTE_SET_RO(PteDst);
2479	}
2480	}
2481	}
2482	else
2483	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2484
2485	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2486	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2487	PGM_INVL_PG(pVCpu, GCPtrPage);
2488	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2489	}
2490
2491	# ifdef IN_RING0
2492	/* Check for stale TLB entry; only applies to the SMP guest case. */
2493	if ( pVM->cCpus > 1
2494	&& SHW_PTE_IS_RW(*pPteDst)
2495	&& SHW_PTE_IS_A(*pPteDst))
2496	{
2497	/* Stale TLB entry. */
2498	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2499	PGM_INVL_PG(pVCpu, GCPtrPage);
2500	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2501	}
2502	# endif
2503	}
2504	}
2505	else
2506	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2507	}
2508
2509	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2510	}
2511
2512	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2513
2514
2515	/**
2516	* Sync a shadow page table.
2517	*
2518	* The shadow page table is not present in the shadow PDE.
2519	*
2520	* Handles mapping conflicts.
2521	*
2522	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2523	* conflict), and Trap0eHandler.
2524	*
2525	* A precodition for this method is that the shadow PDE is not present. The
2526	* caller must take the PGM lock before checking this and continue to hold it
2527	* when calling this method.
2528	*
2529	* @returns VBox status code.
2530	* @param pVCpu The VMCPU handle.
2531	* @param iPD Page directory index.
2532	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2533	* Assume this is a temporary mapping.
2534	* @param GCPtrPage GC Pointer of the page that caused the fault
2535	*/
2536	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2537	{
2538	PVM pVM = pVCpu->CTX_SUFF(pVM);
2539	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2540
2541	#if 0 /* rarely useful; leave for debugging. */
2542	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2543	#endif
2544	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2545
2546	Assert(PGMIsLocked(pVM));
2547
2548	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2549	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2550	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2551	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2552	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2553
2554	int rc = VINF_SUCCESS;
2555
2556	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2557
2558	/*
2559	* Some input validation first.
2560	*/
2561	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2562
2563	/*
2564	* Get the relevant shadow PDE entry.
2565	*/
2566	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2567	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2568	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2569
2570	/* Fetch the pgm pool shadow descriptor. */
2571	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2572	Assert(pShwPde);
2573
2574	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2575	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2576	PPGMPOOLPAGE pShwPde = NULL;
2577	PX86PDPAE pPDDst;
2578	PSHWPDE pPdeDst;
2579
2580	/* Fetch the pgm pool shadow descriptor. */
2581	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2582	AssertRCSuccessReturn(rc, rc);
2583	Assert(pShwPde);
2584
2585	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2586	pPdeDst = &pPDDst->a[iPDDst];
2587
2588	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2589	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2590	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2591	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2592	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2593	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2594	AssertRCSuccessReturn(rc, rc);
2595	Assert(pPDDst);
2596	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2597	# endif
2598	SHWPDE PdeDst = *pPdeDst;
2599
2600	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2601	/* Fetch the pgm pool shadow descriptor. */
2602	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2603	Assert(pShwPde);
2604	# endif
2605
2606	# ifndef PGM_WITHOUT_MAPPINGS
2607	/*
2608	* Check for conflicts.
2609	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2610	* R3: Simply resolve the conflict.
2611	*/
2612	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2613	{
2614	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2615	# ifndef IN_RING3
2616	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2617	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2618	return VERR_ADDRESS_CONFLICT;
2619
2620	# else /* IN_RING3 */
2621	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2622	Assert(pMapping);
2623	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2624	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2625	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2626	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2627	# else
2628	AssertFailed(); /* can't happen for amd64 */
2629	# endif
2630	if (RT_FAILURE(rc))
2631	{
2632	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2633	return rc;
2634	}
2635	PdeDst = *pPdeDst;
2636	# endif /* IN_RING3 */
2637	}
2638	# endif /* !PGM_WITHOUT_MAPPINGS */
2639	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2640
2641	/*
2642	* Sync the page directory entry.
2643	*/
2644	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2645	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2646	if ( PdeSrc.n.u1Present
2647	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2648	{
2649	/*
2650	* Allocate & map the page table.
2651	*/
2652	PSHWPT pPTDst;
2653	PPGMPOOLPAGE pShwPage;
2654	RTGCPHYS GCPhys;
2655	if (fPageTable)
2656	{
2657	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2658	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2659	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2660	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2661	# endif
2662	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2663	}
2664	else
2665	{
2666	PGMPOOLACCESS enmAccess;
2667	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2668	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2669	# else
2670	const bool fNoExecute = false;
2671	# endif
2672
2673	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2674	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2675	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2676	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2677	# endif
2678	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2679	if (PdeSrc.n.u1User)
2680	{
2681	if (PdeSrc.n.u1Write)
2682	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2683	else
2684	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2685	}
2686	else
2687	{
2688	if (PdeSrc.n.u1Write)
2689	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2690	else
2691	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2692	}
2693	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2694	&pShwPage);
2695	}
2696	if (rc == VINF_SUCCESS)
2697	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2698	else if (rc == VINF_PGM_CACHED_PAGE)
2699	{
2700	/*
2701	* The PT was cached, just hook it up.
2702	*/
2703	if (fPageTable)
2704	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2705	else
2706	{
2707	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2708	/* (see explanation and assumptions further down.) */
2709	if ( !PdeSrc.b.u1Dirty
2710	&& PdeSrc.b.u1Write)
2711	{
2712	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2713	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2714	PdeDst.b.u1Write = 0;
2715	}
2716	}
2717	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2718	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2719	return VINF_SUCCESS;
2720	}
2721	else if (rc == VERR_PGM_POOL_FLUSHED)
2722	{
2723	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2724	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2725	return VINF_PGM_SYNC_CR3;
2726	}
2727	else
2728	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
2729	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2730	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2731	* irrelevant at this point. */
2732	PdeDst.u &= X86_PDE_AVL_MASK;
2733	PdeDst.u \|= pShwPage->Core.Key;
2734
2735	/*
2736	* Page directory has been accessed (this is a fault situation, remember).
2737	*/
2738	/** @todo
2739	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2740	* fault situation. What's more, the Trap0eHandler has already set the
2741	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2742	* might need setting the accessed flag.
2743	*
2744	* The best idea is to leave this change to the caller and add an
2745	* assertion that it's set already. */
2746	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2747	if (fPageTable)
2748	{
2749	/*
2750	* Page table - 4KB.
2751	*
2752	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2753	*/
2754	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2755	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2756	PGSTPT pPTSrc;
2757	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2758	if (RT_SUCCESS(rc))
2759	{
2760	/*
2761	* Start by syncing the page directory entry so CSAM's TLB trick works.
2762	*/
2763	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2764	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2765	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2766	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2767
2768	/*
2769	* Directory/page user or supervisor privilege: (same goes for read/write)
2770	*
2771	* Directory Page Combined
2772	* U/S U/S U/S
2773	* 0 0 0
2774	* 0 1 0
2775	* 1 0 0
2776	* 1 1 1
2777	*
2778	* Simple AND operation. Table listed for completeness.
2779	*
2780	*/
2781	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2782	# ifdef PGM_SYNC_N_PAGES
2783	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2784	unsigned iPTDst = iPTBase;
2785	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2786	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2787	iPTDst = 0;
2788	else
2789	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2790	# else /* !PGM_SYNC_N_PAGES */
2791	unsigned iPTDst = 0;
2792	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2793	# endif /* !PGM_SYNC_N_PAGES */
2794	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2795	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2796	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2797	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2798	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2799	# else
2800	const unsigned offPTSrc = 0;
2801	# endif
2802	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2803	{
2804	const unsigned iPTSrc = iPTDst + offPTSrc;
2805	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2806
2807	if (PteSrc.n.u1Present)
2808	{
2809	# ifndef IN_RING0
2810	/*
2811	* Assuming kernel code will be marked as supervisor - and not as user level
2812	* and executed using a conforming code selector - And marked as readonly.
2813	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2814	*/
2815	PPGMPAGE pPage;
2816	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2817	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2818	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, GST_GET_PTE_GCPHYS(PteSrc)))
2819	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2820	)
2821	# endif
2822	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2823	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2824	GCPtrCur,
2825	PteSrc.n.u1Present,
2826	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2827	PteSrc.n.u1User & PdeSrc.n.u1User,
2828	(uint64_t)PteSrc.u,
2829	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2830	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2831	}
2832	/* else: the page table was cleared by the pool */
2833	} /* for PTEs */
2834	}
2835	}
2836	else
2837	{
2838	/*
2839	* Big page - 2/4MB.
2840	*
2841	* We'll walk the ram range list in parallel and optimize lookups.
2842	* We will only sync on shadow page table at a time.
2843	*/
2844	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2845
2846	/**
2847	* @todo It might be more efficient to sync only a part of the 4MB
2848	* page (similar to what we do for 4KB PDs).
2849	*/
2850
2851	/*
2852	* Start by syncing the page directory entry.
2853	*/
2854	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2855	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2856
2857	/*
2858	* If the page is not flagged as dirty and is writable, then make it read-only
2859	* at PD level, so we can set the dirty bit when the page is modified.
2860	*
2861	* ASSUMES that page access handlers are implemented on page table entry level.
2862	* Thus we will first catch the dirty access and set PDE.D and restart. If
2863	* there is an access handler, we'll trap again and let it work on the problem.
2864	*/
2865	/** @todo move the above stuff to a section in the PGM documentation. */
2866	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2867	if ( !PdeSrc.b.u1Dirty
2868	&& PdeSrc.b.u1Write)
2869	{
2870	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2871	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2872	PdeDst.b.u1Write = 0;
2873	}
2874	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2875	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2876
2877	/*
2878	* Fill the shadow page table.
2879	*/
2880	/* Get address and flags from the source PDE. */
2881	SHWPTE PteDstBase;
2882	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2883
2884	/* Loop thru the entries in the shadow PT. */
2885	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2886	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2887	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2888	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2889	PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRanges);
2890	unsigned iPTDst = 0;
2891	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2892	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2893	{
2894	/* Advance ram range list. */
2895	while (pRam && GCPhys > pRam->GCPhysLast)
2896	pRam = pRam->CTX_SUFF(pNext);
2897	if (pRam && GCPhys >= pRam->GCPhys)
2898	{
2899	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2900	do
2901	{
2902	/* Make shadow PTE. */
2903	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2904	SHWPTE PteDst;
2905
2906	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2907	/* Try to make the page writable if necessary. */
2908	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2909	&& ( PGM_PAGE_IS_ZERO(pPage)
2910	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2911	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2912	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2913	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2914	# endif
2915	# ifdef VBOX_WITH_PAGE_SHARING
2916	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2917	# endif
2918	&& !PGM_PAGE_IS_BALLOONED(pPage))
2919	)
2920	)
2921	{
2922	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2923	AssertRCReturn(rc, rc);
2924	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2925	break;
2926	}
2927	# endif
2928
2929	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2930	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2931	else if (PGM_PAGE_IS_BALLOONED(pPage))
2932	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2933	# ifndef IN_RING0
2934	/*
2935	* Assuming kernel code will be marked as supervisor and not as user level and executed
2936	* using a conforming code selector. Don't check for readonly, as that implies the whole
2937	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2938	*/
2939	else if ( !PdeSrc.n.u1User
2940	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2941	SHW_PTE_SET(PteDst, 0);
2942	# endif
2943	else
2944	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2945
2946	/* Only map writable pages writable. */
2947	if ( SHW_PTE_IS_P_RW(PteDst)
2948	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2949	{
2950	/* Still applies to shared pages. */
2951	Assert(!PGM_PAGE_IS_ZERO(pPage));
2952	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2953	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2954	}
2955
2956	if (SHW_PTE_IS_P(PteDst))
2957	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2958
2959	/* commit it (not atomic, new table) */
2960	pPTDst->a[iPTDst] = PteDst;
2961	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2962	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2963	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2964
2965	/* advance */
2966	GCPhys += PAGE_SIZE;
2967	iHCPage++;
2968	iPTDst++;
2969	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2970	&& GCPhys <= pRam->GCPhysLast);
2971	}
2972	else if (pRam)
2973	{
2974	Log(("Invalid pages at %RGp\n", GCPhys));
2975	do
2976	{
2977	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2978	GCPhys += PAGE_SIZE;
2979	iPTDst++;
2980	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2981	&& GCPhys < pRam->GCPhys);
2982	}
2983	else
2984	{
2985	Log(("Invalid pages at %RGp (2)\n", GCPhys));
2986	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
2987	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2988	}
2989	} /* while more PTEs */
2990	} /* 4KB / 4MB */
2991	}
2992	else
2993	AssertRelease(!PdeDst.n.u1Present);
2994
2995	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2996	if (RT_FAILURE(rc))
2997	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
2998	return rc;
2999
3000	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3001	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3002	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3003	&& !defined(IN_RC)
3004
3005	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3006
3007	/*
3008	* Validate input a little bit.
3009	*/
3010	int rc = VINF_SUCCESS;
3011	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3012	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3013	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3014
3015	/* Fetch the pgm pool shadow descriptor. */
3016	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3017	Assert(pShwPde);
3018
3019	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3020	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3021	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3022	PX86PDPAE pPDDst;
3023	PSHWPDE pPdeDst;
3024
3025	/* Fetch the pgm pool shadow descriptor. */
3026	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3027	AssertRCSuccessReturn(rc, rc);
3028	Assert(pShwPde);
3029
3030	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3031	pPdeDst = &pPDDst->a[iPDDst];
3032
3033	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3034	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3035	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3036	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3037	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3038	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3039	AssertRCSuccessReturn(rc, rc);
3040	Assert(pPDDst);
3041	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3042
3043	/* Fetch the pgm pool shadow descriptor. */
3044	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3045	Assert(pShwPde);
3046
3047	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3048	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3049	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3050	PEPTPD pPDDst;
3051	PEPTPDPT pPdptDst;
3052
3053	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3054	if (rc != VINF_SUCCESS)
3055	{
3056	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3057	AssertRC(rc);
3058	return rc;
3059	}
3060	Assert(pPDDst);
3061	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3062
3063	/* Fetch the pgm pool shadow descriptor. */
3064	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3065	Assert(pShwPde);
3066	# endif
3067	SHWPDE PdeDst = *pPdeDst;
3068
3069	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3070	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3071
3072	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3073	if (BTH_IS_NP_ACTIVE(pVM))
3074	{
3075	PPGMPAGE pPage;
3076
3077	/* Check if we allocated a big page before for this 2 MB range. */
3078	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3079	if (RT_SUCCESS(rc))
3080	{
3081	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3082
3083	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3084	{
3085	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3086	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3087	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3088	}
3089	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3090	{
3091	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3092	rc = pgmPhysIsValidLargePage(pVM, GCPtrPage, pPage);
3093	if (RT_SUCCESS(rc))
3094	{
3095	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3096	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3097	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3098	}
3099	}
3100	else if (PGMIsUsingLargePages(pVM))
3101	{
3102	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3103	if (RT_SUCCESS(rc))
3104	{
3105	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3106	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3107	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3108	}
3109	else
3110	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3111	}
3112
3113	if (HCPhys != NIL_RTHCPHYS)
3114	{
3115	PdeDst.u &= X86_PDE_AVL_MASK;
3116	PdeDst.u \|= HCPhys;
3117	PdeDst.n.u1Present = 1;
3118	PdeDst.n.u1Write = 1;
3119	PdeDst.b.u1Size = 1;
3120	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3121	PdeDst.n.u1Execute = 1;
3122	PdeDst.b.u1IgnorePAT = 1;
3123	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3124	# else
3125	PdeDst.n.u1User = 1;
3126	# endif
3127	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3128
3129	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3130	/* Add a reference to the first page only. */
3131	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3132
3133	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3134	return VINF_SUCCESS;
3135	}
3136	}
3137	}
3138	# endif /* HC_ARCH_BITS == 64 */
3139
3140	/*
3141	* Allocate & map the page table.
3142	*/
3143	PSHWPT pPTDst;
3144	PPGMPOOLPAGE pShwPage;
3145	RTGCPHYS GCPhys;
3146
3147	/* Virtual address = physical address */
3148	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3149	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3150
3151	if ( rc == VINF_SUCCESS
3152	\|\| rc == VINF_PGM_CACHED_PAGE)
3153	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3154	else
3155	{
3156	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3157	AssertMsgFailedReturn(("rc=%Rrc\n", rc), VERR_INTERNAL_ERROR);
3158	}
3159
3160	if (rc == VINF_SUCCESS)
3161	{
3162	/* New page table; fully set it up. */
3163	Assert(pPTDst);
3164
3165	/* Mask away the page offset. */
3166	GCPtrPage &= ~((RTGCPTR)0xfff);
3167
3168	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3169	{
3170	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
3171
3172	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3173	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3174	GCPtrCurPage,
3175	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3176	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3177
3178	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3179	break;
3180	}
3181	}
3182	/* else cached entry; assume it's still fully valid. */
3183
3184	/* Save the new PDE. */
3185	PdeDst.u &= X86_PDE_AVL_MASK;
3186	PdeDst.u \|= pShwPage->Core.Key;
3187	PdeDst.n.u1Present = 1;
3188	PdeDst.n.u1Write = 1;
3189	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3190	PdeDst.n.u1Execute = 1;
3191	# else
3192	PdeDst.n.u1User = 1;
3193	PdeDst.n.u1Accessed = 1;
3194	# endif
3195	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3196
3197	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3198	if (RT_FAILURE(rc))
3199	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3200	return rc;
3201
3202	#else
3203	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3204	return VERR_INTERNAL_ERROR;
3205	#endif
3206	}
3207
3208
3209
3210	/**
3211	* Prefetch a page/set of pages.
3212	*
3213	* Typically used to sync commonly used pages before entering raw mode
3214	* after a CR3 reload.
3215	*
3216	* @returns VBox status code.
3217	* @param pVCpu The VMCPU handle.
3218	* @param GCPtrPage Page to invalidate.
3219	*/
3220	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3221	{
3222	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3223	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3224	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3225	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3226	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3227	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3228	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3229
3230	/*
3231	* Check that all Guest levels thru the PDE are present, getting the
3232	* PD and PDE in the processes.
3233	*/
3234	int rc = VINF_SUCCESS;
3235	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3236	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3237	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3238	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3239	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3240	unsigned iPDSrc;
3241	X86PDPE PdpeSrc;
3242	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3243	if (!pPDSrc)
3244	return VINF_SUCCESS; /* not present */
3245	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3246	unsigned iPDSrc;
3247	PX86PML4E pPml4eSrc;
3248	X86PDPE PdpeSrc;
3249	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3250	if (!pPDSrc)
3251	return VINF_SUCCESS; /* not present */
3252	# endif
3253	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3254	# else
3255	PGSTPD pPDSrc = NULL;
3256	const unsigned iPDSrc = 0;
3257	GSTPDE PdeSrc;
3258
3259	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3260	PdeSrc.n.u1Present = 1;
3261	PdeSrc.n.u1Write = 1;
3262	PdeSrc.n.u1Accessed = 1;
3263	PdeSrc.n.u1User = 1;
3264	# endif
3265
3266	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3267	{
3268	PVM pVM = pVCpu->CTX_SUFF(pVM);
3269	pgmLock(pVM);
3270
3271	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3272	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3273	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3274	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3275	PX86PDPAE pPDDst;
3276	X86PDEPAE PdeDst;
3277	# if PGM_GST_TYPE != PGM_TYPE_PAE
3278	X86PDPE PdpeSrc;
3279
3280	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3281	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3282	# endif
3283	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3284	if (rc != VINF_SUCCESS)
3285	{
3286	pgmUnlock(pVM);
3287	AssertRC(rc);
3288	return rc;
3289	}
3290	Assert(pPDDst);
3291	PdeDst = pPDDst->a[iPDDst];
3292
3293	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3294	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3295	PX86PDPAE pPDDst;
3296	X86PDEPAE PdeDst;
3297
3298	# if PGM_GST_TYPE == PGM_TYPE_PROT
3299	/* AMD-V nested paging */
3300	X86PML4E Pml4eSrc;
3301	X86PDPE PdpeSrc;
3302	PX86PML4E pPml4eSrc = &Pml4eSrc;
3303
3304	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3305	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3306	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3307	# endif
3308
3309	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3310	if (rc != VINF_SUCCESS)
3311	{
3312	pgmUnlock(pVM);
3313	AssertRC(rc);
3314	return rc;
3315	}
3316	Assert(pPDDst);
3317	PdeDst = pPDDst->a[iPDDst];
3318	# endif
3319	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3320	{
3321	if (!PdeDst.n.u1Present)
3322	{
3323	/** @todo r=bird: This guy will set the A bit on the PDE,
3324	* probably harmless. */
3325	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3326	}
3327	else
3328	{
3329	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3330	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3331	* makes no sense to prefetch more than one page.
3332	*/
3333	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3334	if (RT_SUCCESS(rc))
3335	rc = VINF_SUCCESS;
3336	}
3337	}
3338	pgmUnlock(pVM);
3339	}
3340	return rc;
3341
3342	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3343	return VINF_SUCCESS; /* ignore */
3344	#else
3345	AssertCompile(0);
3346	#endif
3347	}
3348
3349
3350
3351
3352	/**
3353	* Syncs a page during a PGMVerifyAccess() call.
3354	*
3355	* @returns VBox status code (informational included).
3356	* @param pVCpu The VMCPU handle.
3357	* @param GCPtrPage The address of the page to sync.
3358	* @param fPage The effective guest page flags.
3359	* @param uErr The trap error code.
3360	* @remarks This will normally never be called on invalid guest page
3361	* translation entries.
3362	*/
3363	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3364	{
3365	PVM pVM = pVCpu->CTX_SUFF(pVM);
3366
3367	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3368
3369	Assert(!pVM->pgm.s.fNestedPaging);
3370	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3371	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3372	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3373	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3374	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3375	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3376	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3377
3378	# ifndef IN_RING0
3379	if (!(fPage & X86_PTE_US))
3380	{
3381	/*
3382	* Mark this page as safe.
3383	*/
3384	/** @todo not correct for pages that contain both code and data!! */
3385	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3386	CSAMMarkPage(pVM, GCPtrPage, true);
3387	}
3388	# endif
3389
3390	/*
3391	* Get guest PD and index.
3392	*/
3393	/** @todo Performance: We've done all this a jiffy ago in the
3394	* PGMGstGetPage call. */
3395	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3396	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3397	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3398	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3399
3400	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3401	unsigned iPDSrc = 0;
3402	X86PDPE PdpeSrc;
3403	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3404	if (RT_UNLIKELY(!pPDSrc))
3405	{
3406	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3407	return VINF_EM_RAW_GUEST_TRAP;
3408	}
3409
3410	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3411	unsigned iPDSrc = 0; /* shut up gcc */
3412	PX86PML4E pPml4eSrc = NULL; /* ditto */
3413	X86PDPE PdpeSrc;
3414	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3415	if (RT_UNLIKELY(!pPDSrc))
3416	{
3417	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3418	return VINF_EM_RAW_GUEST_TRAP;
3419	}
3420	# endif
3421
3422	# else /* !PGM_WITH_PAGING */
3423	PGSTPD pPDSrc = NULL;
3424	const unsigned iPDSrc = 0;
3425	# endif /* !PGM_WITH_PAGING */
3426	int rc = VINF_SUCCESS;
3427
3428	pgmLock(pVM);
3429
3430	/*
3431	* First check if the shadow pd is present.
3432	*/
3433	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3434	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3435
3436	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3437	PX86PDEPAE pPdeDst;
3438	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3439	PX86PDPAE pPDDst;
3440	# if PGM_GST_TYPE != PGM_TYPE_PAE
3441	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3442	X86PDPE PdpeSrc;
3443	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3444	# endif
3445	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3446	if (rc != VINF_SUCCESS)
3447	{
3448	pgmUnlock(pVM);
3449	AssertRC(rc);
3450	return rc;
3451	}
3452	Assert(pPDDst);
3453	pPdeDst = &pPDDst->a[iPDDst];
3454
3455	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3456	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3457	PX86PDPAE pPDDst;
3458	PX86PDEPAE pPdeDst;
3459
3460	# if PGM_GST_TYPE == PGM_TYPE_PROT
3461	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3462	X86PML4E Pml4eSrc;
3463	X86PDPE PdpeSrc;
3464	PX86PML4E pPml4eSrc = &Pml4eSrc;
3465	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3466	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3467	# endif
3468
3469	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3470	if (rc != VINF_SUCCESS)
3471	{
3472	pgmUnlock(pVM);
3473	AssertRC(rc);
3474	return rc;
3475	}
3476	Assert(pPDDst);
3477	pPdeDst = &pPDDst->a[iPDDst];
3478	# endif
3479
3480	if (!pPdeDst->n.u1Present)
3481	{
3482	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3483	if (rc != VINF_SUCCESS)
3484	{
3485	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3486	pgmUnlock(pVM);
3487	AssertRC(rc);
3488	return rc;
3489	}
3490	}
3491
3492	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3493	/* Check for dirty bit fault */
3494	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3495	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3496	Log(("PGMVerifyAccess: success (dirty)\n"));
3497	else
3498	# endif
3499	{
3500	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3501	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3502	# else
3503	GSTPDE PdeSrc;
3504	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3505	PdeSrc.n.u1Present = 1;
3506	PdeSrc.n.u1Write = 1;
3507	PdeSrc.n.u1Accessed = 1;
3508	PdeSrc.n.u1User = 1;
3509	# endif
3510
3511	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3512	if (uErr & X86_TRAP_PF_US)
3513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3514	else /* supervisor */
3515	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3516
3517	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3518	if (RT_SUCCESS(rc))
3519	{
3520	/* Page was successfully synced */
3521	Log2(("PGMVerifyAccess: success (sync)\n"));
3522	rc = VINF_SUCCESS;
3523	}
3524	else
3525	{
3526	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3527	rc = VINF_EM_RAW_GUEST_TRAP;
3528	}
3529	}
3530	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3531	pgmUnlock(pVM);
3532	return rc;
3533
3534	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3535
3536	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3537	return VERR_INTERNAL_ERROR;
3538	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3539	}
3540
3541
3542	/**
3543	* Syncs the paging hierarchy starting at CR3.
3544	*
3545	* @returns VBox status code, no specials.
3546	* @param pVCpu The VMCPU handle.
3547	* @param cr0 Guest context CR0 register
3548	* @param cr3 Guest context CR3 register
3549	* @param cr4 Guest context CR4 register
3550	* @param fGlobal Including global page directories or not
3551	*/
3552	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3553	{
3554	PVM pVM = pVCpu->CTX_SUFF(pVM);
3555
3556	LogFlow(("SyncCR3 fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)));
3557
3558	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3559
3560	pgmLock(pVM);
3561
3562	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3563	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3564	if (pPool->cDirtyPages)
3565	pgmPoolResetDirtyPages(pVM);
3566	# endif
3567
3568	/*
3569	* Update page access handlers.
3570	* The virtual are always flushed, while the physical are only on demand.
3571	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3572	* have to look into that later because it will have a bad influence on the performance.
3573	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3574	* bird: Yes, but that won't work for aliases.
3575	*/
3576	/** @todo this MUST go away. See #1557. */
3577	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3578	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3579	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3580	pgmUnlock(pVM);
3581	#endif /* !NESTED && !EPT */
3582
3583	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3584	/*
3585	* Nested / EPT - almost no work.
3586	*/
3587	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3588	return VINF_SUCCESS;
3589
3590	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3591	/*
3592	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3593	* out the shadow parts when the guest modifies its tables.
3594	*/
3595	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3596	return VINF_SUCCESS;
3597
3598	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3599
3600	# ifndef PGM_WITHOUT_MAPPINGS
3601	/*
3602	* Check for and resolve conflicts with our guest mappings if they
3603	* are enabled and not fixed.
3604	*/
3605	if (pgmMapAreMappingsFloating(&pVM->pgm.s))
3606	{
3607	int rc = pgmMapResolveConflicts(pVM);
3608	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3609	if (rc == VINF_PGM_SYNC_CR3)
3610	{
3611	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3612	return VINF_PGM_SYNC_CR3;
3613	}
3614	}
3615	# else
3616	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3617	# endif
3618	return VINF_SUCCESS;
3619	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3620	}
3621
3622
3623
3624
3625	#ifdef VBOX_STRICT
3626	# ifdef IN_RC
3627	# undef AssertMsgFailed
3628	# define AssertMsgFailed Log
3629	# endif
3630
3631	/**
3632	* Checks that the shadow page table is in sync with the guest one.
3633	*
3634	* @returns The number of errors.
3635	* @param pVM The virtual machine.
3636	* @param pVCpu The VMCPU handle.
3637	* @param cr3 Guest context CR3 register
3638	* @param cr4 Guest context CR4 register
3639	* @param GCPtr Where to start. Defaults to 0.
3640	* @param cb How much to check. Defaults to everything.
3641	*/
3642	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3643	{
3644	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3645	return 0;
3646	#else
3647	unsigned cErrors = 0;
3648	PVM pVM = pVCpu->CTX_SUFF(pVM);
3649	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3650
3651	#if PGM_GST_TYPE == PGM_TYPE_PAE
3652	/** @todo currently broken; crashes below somewhere */
3653	AssertFailed();
3654	#endif
3655
3656	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3657	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3658	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3659
3660	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3661	PPGMCPU pPGM = &pVCpu->pgm.s;
3662	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3663	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3664	# ifndef IN_RING0
3665	RTHCPHYS HCPhys; /* general usage. */
3666	# endif
3667	int rc;
3668
3669	/*
3670	* Check that the Guest CR3 and all its mappings are correct.
3671	*/
3672	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3673	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3674	false);
3675	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3676	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3677	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3678	# else
3679	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3680	# endif
3681	AssertRCReturn(rc, 1);
3682	HCPhys = NIL_RTHCPHYS;
3683	rc = pgmRamGCPhys2HCPhys(&pVM->pgm.s, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3684	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3685	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3686	pgmGstGet32bitPDPtr(pVCpu);
3687	RTGCPHYS GCPhys;
3688	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3689	AssertRCReturn(rc, 1);
3690	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3691	# endif
3692	# endif /* !IN_RING0 */
3693
3694	/*
3695	* Get and check the Shadow CR3.
3696	*/
3697	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3698	unsigned cPDEs = X86_PG_ENTRIES;
3699	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3700	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3701	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3702	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3703	# else
3704	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3705	# endif
3706	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3707	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3708	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3709	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3710	# endif
3711	if (cb != ~(RTGCPTR)0)
3712	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3713
3714	/** @todo call the other two PGMAssert() functions. /
3715
3716	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3717	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3718
3719	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3720	{
3721	PPGMPOOLPAGE pShwPdpt = NULL;
3722	PX86PML4E pPml4eSrc;
3723	PX86PML4E pPml4eDst;
3724	RTGCPHYS GCPhysPdptSrc;
3725
3726	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3727	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3728
3729	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3730	if (!pPml4eDst->n.u1Present)
3731	{
3732	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3733	continue;
3734	}
3735
3736	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3737	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3738
3739	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3740	{
3741	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3742	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3743	cErrors++;
3744	continue;
3745	}
3746
3747	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3748	{
3749	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3750	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3751	cErrors++;
3752	continue;
3753	}
3754
3755	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3756	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3757	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3758	{
3759	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3760	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3761	cErrors++;
3762	continue;
3763	}
3764	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3765	{
3766	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3767
3768	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3769	/*
3770	* Check the PDPTEs too.
3771	*/
3772	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3773
3774	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3775	{
3776	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3777	PPGMPOOLPAGE pShwPde = NULL;
3778	PX86PDPE pPdpeDst;
3779	RTGCPHYS GCPhysPdeSrc;
3780	# if PGM_GST_TYPE == PGM_TYPE_PAE
3781	X86PDPE PdpeSrc;
3782	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3783	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3784	# else
3785	PX86PML4E pPml4eSrcIgn;
3786	X86PDPE PdpeSrc;
3787	PX86PDPT pPdptDst;
3788	PX86PDPAE pPDDst;
3789	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3790
3791	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3792	if (rc != VINF_SUCCESS)
3793	{
3794	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3795	GCPtr += 512 * _2M;
3796	continue; /* next PDPTE */
3797	}
3798	Assert(pPDDst);
3799	# endif
3800	Assert(iPDSrc == 0);
3801
3802	pPdpeDst = &pPdptDst->a[iPdpt];
3803
3804	if (!pPdpeDst->n.u1Present)
3805	{
3806	GCPtr += 512 * _2M;
3807	continue; /* next PDPTE */
3808	}
3809
3810	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3811	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3812
3813	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3814	{
3815	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3816	GCPtr += 512 * _2M;
3817	cErrors++;
3818	continue;
3819	}
3820
3821	if (GCPhysPdeSrc != pShwPde->GCPhys)
3822	{
3823	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3824	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3825	# else
3826	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3827	# endif
3828	GCPtr += 512 * _2M;
3829	cErrors++;
3830	continue;
3831	}
3832
3833	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3834	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3835	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3836	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3837	{
3838	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3839	GCPtr += 512 * _2M;
3840	cErrors++;
3841	continue;
3842	}
3843	# endif
3844
3845	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3846	{
3847	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3848	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3849	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3850	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3851	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3852	# endif
3853	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3854	/*
3855	* Iterate the shadow page directory.
3856	*/
3857	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3858	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3859
3860	for (;
3861	iPDDst < cPDEs;
3862	iPDDst++, GCPtr += cIncrement)
3863	{
3864	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3865	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3866	# else
3867	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3868	# endif
3869	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3870	{
3871	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3872	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3873	{
3874	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3875	cErrors++;
3876	continue;
3877	}
3878	}
3879	else if ( (PdeDst.u & X86_PDE_P)
3880	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3881	)
3882	{
3883	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3884	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3885	if (!pPoolPage)
3886	{
3887	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3888	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3889	cErrors++;
3890	continue;
3891	}
3892	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3893
3894	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3895	{
3896	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3897	GCPtr, (uint64_t)PdeDst.u));
3898	cErrors++;
3899	}
3900
3901	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3902	{
3903	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3904	GCPtr, (uint64_t)PdeDst.u));
3905	cErrors++;
3906	}
3907
3908	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3909	if (!PdeSrc.n.u1Present)
3910	{
3911	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3912	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3913	cErrors++;
3914	continue;
3915	}
3916
3917	if ( !PdeSrc.b.u1Size
3918	\|\| !fBigPagesSupported)
3919	{
3920	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3921	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3922	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3923	# endif
3924	}
3925	else
3926	{
3927	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3928	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3929	{
3930	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3931	GCPtr, (uint64_t)PdeSrc.u));
3932	cErrors++;
3933	continue;
3934	}
3935	# endif
3936	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3937	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3938	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3939	# endif
3940	}
3941
3942	if ( pPoolPage->enmKind
3943	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3944	{
3945	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3946	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3947	cErrors++;
3948	}
3949
3950	PPGMPAGE pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
3951	if (!pPhysPage)
3952	{
3953	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3954	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3955	cErrors++;
3956	continue;
3957	}
3958
3959	if (GCPhysGst != pPoolPage->GCPhys)
3960	{
3961	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3962	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3963	cErrors++;
3964	continue;
3965	}
3966
3967	if ( !PdeSrc.b.u1Size
3968	\|\| !fBigPagesSupported)
3969	{
3970	/*
3971	* Page Table.
3972	*/
3973	const GSTPT *pPTSrc;
3974	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3975	if (RT_FAILURE(rc))
3976	{
3977	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3978	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3979	cErrors++;
3980	continue;
3981	}
3982	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3983	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3984	{
3985	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3986	// (This problem will go away when/if we shadow multiple CR3s.)
3987	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3988	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3989	cErrors++;
3990	continue;
3991	}
3992	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3993	{
3994	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
3995	GCPtr, (uint64_t)PdeDst.u));
3996	cErrors++;
3997	continue;
3998	}
3999
4000	/* iterate the page table. */
4001	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4002	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4003	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4004	# else
4005	const unsigned offPTSrc = 0;
4006	# endif
4007	for (unsigned iPT = 0, off = 0;
4008	iPT < RT_ELEMENTS(pPTDst->a);
4009	iPT++, off += PAGE_SIZE)
4010	{
4011	const SHWPTE PteDst = pPTDst->a[iPT];
4012
4013	/* skip not-present and dirty tracked entries. */
4014	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4015	continue;
4016	Assert(SHW_PTE_IS_P(PteDst));
4017
4018	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4019	if (!PteSrc.n.u1Present)
4020	{
4021	# ifdef IN_RING3
4022	PGMAssertHandlerAndFlagsInSync(pVM);
4023	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4024	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4025	0, 0, UINT64_MAX, 99, NULL);
4026	# endif
4027	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4028	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4029	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
4030	cErrors++;
4031	continue;
4032	}
4033
4034	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4035	# if 1 /** @todo sync accessed bit properly... */
4036	fIgnoreFlags \|= X86_PTE_A;
4037	# endif
4038
4039	/* match the physical addresses */
4040	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4041	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4042
4043	# ifdef IN_RING3
4044	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4045	if (RT_FAILURE(rc))
4046	{
4047	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4048	{
4049	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4050	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4051	cErrors++;
4052	continue;
4053	}
4054	}
4055	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4056	{
4057	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4058	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4059	cErrors++;
4060	continue;
4061	}
4062	# endif
4063
4064	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4065	if (!pPhysPage)
4066	{
4067	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4068	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4069	{
4070	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4071	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4072	cErrors++;
4073	continue;
4074	}
4075	# endif
4076	if (SHW_PTE_IS_RW(PteDst))
4077	{
4078	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4079	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4080	cErrors++;
4081	}
4082	fIgnoreFlags \|= X86_PTE_RW;
4083	}
4084	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4085	{
4086	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4087	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4088	cErrors++;
4089	continue;
4090	}
4091
4092	/* flags */
4093	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4094	{
4095	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4096	{
4097	if (SHW_PTE_IS_RW(PteDst))
4098	{
4099	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4100	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4101	cErrors++;
4102	continue;
4103	}
4104	fIgnoreFlags \|= X86_PTE_RW;
4105	}
4106	else
4107	{
4108	if ( SHW_PTE_IS_P(PteDst)
4109	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4110	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4111	# endif
4112	)
4113	{
4114	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4115	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4116	cErrors++;
4117	continue;
4118	}
4119	fIgnoreFlags \|= X86_PTE_P;
4120	}
4121	}
4122	else
4123	{
4124	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4125	{
4126	if (SHW_PTE_IS_RW(PteDst))
4127	{
4128	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4129	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4130	cErrors++;
4131	continue;
4132	}
4133	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4134	{
4135	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4136	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4137	cErrors++;
4138	continue;
4139	}
4140	if (SHW_PTE_IS_D(PteDst))
4141	{
4142	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4143	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4144	cErrors++;
4145	}
4146	# if 0 /** @todo sync access bit properly... */
4147	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4148	{
4149	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4150	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4151	cErrors++;
4152	}
4153	fIgnoreFlags \|= X86_PTE_RW;
4154	# else
4155	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4156	# endif
4157	}
4158	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4159	{
4160	/* access bit emulation (not implemented). */
4161	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4162	{
4163	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4164	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4165	cErrors++;
4166	continue;
4167	}
4168	if (!SHW_PTE_IS_A(PteDst))
4169	{
4170	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4171	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4172	cErrors++;
4173	}
4174	fIgnoreFlags \|= X86_PTE_P;
4175	}
4176	# ifdef DEBUG_sandervl
4177	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4178	# endif
4179	}
4180
4181	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4182	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4183	)
4184	{
4185	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4186	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4187	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4188	cErrors++;
4189	continue;
4190	}
4191	} /* foreach PTE */
4192	}
4193	else
4194	{
4195	/*
4196	* Big Page.
4197	*/
4198	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4199	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4200	{
4201	if (PdeDst.n.u1Write)
4202	{
4203	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4204	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4205	cErrors++;
4206	continue;
4207	}
4208	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4209	{
4210	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4211	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4212	cErrors++;
4213	continue;
4214	}
4215	# if 0 /** @todo sync access bit properly... */
4216	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4217	{
4218	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4219	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4220	cErrors++;
4221	}
4222	fIgnoreFlags \|= X86_PTE_RW;
4223	# else
4224	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4225	# endif
4226	}
4227	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4228	{
4229	/* access bit emulation (not implemented). */
4230	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4231	{
4232	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4233	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4234	cErrors++;
4235	continue;
4236	}
4237	if (!PdeDst.n.u1Accessed)
4238	{
4239	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4240	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4241	cErrors++;
4242	}
4243	fIgnoreFlags \|= X86_PTE_P;
4244	}
4245
4246	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4247	{
4248	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4249	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4250	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4251	cErrors++;
4252	}
4253
4254	/* iterate the page table. */
4255	for (unsigned iPT = 0, off = 0;
4256	iPT < RT_ELEMENTS(pPTDst->a);
4257	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4258	{
4259	const SHWPTE PteDst = pPTDst->a[iPT];
4260
4261	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4262	{
4263	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4264	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4265	cErrors++;
4266	}
4267
4268	/* skip not-present entries. */
4269	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4270	continue;
4271
4272	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4273
4274	/* match the physical addresses */
4275	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4276
4277	# ifdef IN_RING3
4278	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4279	if (RT_FAILURE(rc))
4280	{
4281	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4282	{
4283	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4284	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4285	cErrors++;
4286	}
4287	}
4288	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4289	{
4290	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4291	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4292	cErrors++;
4293	continue;
4294	}
4295	# endif
4296	pPhysPage = pgmPhysGetPage(&pVM->pgm.s, GCPhysGst);
4297	if (!pPhysPage)
4298	{
4299	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4300	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4301	{
4302	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4303	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4304	cErrors++;
4305	continue;
4306	}
4307	# endif
4308	if (SHW_PTE_IS_RW(PteDst))
4309	{
4310	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4311	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4312	cErrors++;
4313	}
4314	fIgnoreFlags \|= X86_PTE_RW;
4315	}
4316	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4317	{
4318	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4319	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4320	cErrors++;
4321	continue;
4322	}
4323
4324	/* flags */
4325	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4326	{
4327	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4328	{
4329	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4330	{
4331	if (SHW_PTE_IS_RW(PteDst))
4332	{
4333	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4334	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4335	cErrors++;
4336	continue;
4337	}
4338	fIgnoreFlags \|= X86_PTE_RW;
4339	}
4340	}
4341	else
4342	{
4343	if ( SHW_PTE_IS_P(PteDst)
4344	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4345	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4346	# endif
4347	)
4348	{
4349	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4350	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4351	cErrors++;
4352	continue;
4353	}
4354	fIgnoreFlags \|= X86_PTE_P;
4355	}
4356	}
4357
4358	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4359	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4360	)
4361	{
4362	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4363	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4364	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4365	cErrors++;
4366	continue;
4367	}
4368	} /* for each PTE */
4369	}
4370	}
4371	/* not present */
4372
4373	} /* for each PDE */
4374
4375	} /* for each PDPTE */
4376
4377	} /* for each PML4E */
4378
4379	# ifdef DEBUG
4380	if (cErrors)
4381	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4382	# endif
4383
4384	#endif /* GST == 32BIT, PAE or AMD64 */
4385	return cErrors;
4386
4387	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4388	}
4389	#endif /* VBOX_STRICT */
4390
4391
4392	/**
4393	* Sets up the CR3 for shadow paging
4394	*
4395	* @returns Strict VBox status code.
4396	* @retval VINF_SUCCESS.
4397	*
4398	* @param pVCpu The VMCPU handle.
4399	* @param GCPhysCR3 The physical address in the CR3 register.
4400	*/
4401	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4402	{
4403	PVM pVM = pVCpu->CTX_SUFF(pVM);
4404
4405	/* Update guest paging info. */
4406	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4407	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4408	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4409
4410	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4411
4412	/*
4413	* Map the page CR3 points at.
4414	*/
4415	RTHCPTR HCPtrGuestCR3;
4416	RTHCPHYS HCPhysGuestCR3;
4417	pgmLock(pVM);
4418	PPGMPAGE pPageCR3 = pgmPhysGetPage(&pVM->pgm.s, GCPhysCR3);
4419	AssertReturn(pPageCR3, VERR_INTERNAL_ERROR_2);
4420	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4421	/** @todo this needs some reworking wrt. locking? */
4422	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4423	HCPtrGuestCR3 = NIL_RTHCPTR;
4424	int rc = VINF_SUCCESS;
4425	# else
4426	int rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4427	# endif
4428	pgmUnlock(pVM);
4429	if (RT_SUCCESS(rc))
4430	{
4431	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4432	if (RT_SUCCESS(rc))
4433	{
4434	# ifdef IN_RC
4435	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4436	# endif
4437	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4438	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4439	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4440	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4441	# endif
4442	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4443
4444	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4445	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4446	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4447	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4448	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4449	# endif
4450	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4451	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4452
4453	/*
4454	* Map the 4 PDs too.
4455	*/
4456	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4457	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4458	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4459	{
4460	if (pGuestPDPT->a[i].n.u1Present)
4461	{
4462	RTHCPTR HCPtr;
4463	RTHCPHYS HCPhys;
4464	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4465	pgmLock(pVM);
4466	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, GCPhys);
4467	AssertReturn(pPage, VERR_INTERNAL_ERROR_2);
4468	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4469	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4470	HCPtr = NIL_RTHCPTR;
4471	int rc2 = VINF_SUCCESS;
4472	# else
4473	int rc2 = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, (void **)&HCPtr);
4474	# endif
4475	pgmUnlock(pVM);
4476	if (RT_SUCCESS(rc2))
4477	{
4478	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4479	AssertRCReturn(rc, rc);
4480
4481	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4482	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4483	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4484	# endif
4485	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4486	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4487	# ifdef IN_RC
4488	PGM_INVL_PG(pVCpu, GCPtr);
4489	# endif
4490	continue;
4491	}
4492	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4493	}
4494
4495	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4496	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4497	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4498	# endif
4499	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4500	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4501	# ifdef IN_RC
4502	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4503	# endif
4504	}
4505
4506	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4507	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4508	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4509	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4510	# endif
4511	# endif
4512	}
4513	else
4514	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4515	}
4516	else
4517	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4518
4519	#else /* prot/real stub */
4520	int rc = VINF_SUCCESS;
4521	#endif
4522
4523	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4524	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4525	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4526	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4527	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4528	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4529
4530	Assert(!pVM->pgm.s.fNestedPaging);
4531
4532	/*
4533	* Update the shadow root page as well since that's not fixed.
4534	*/
4535	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4536	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4537	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4538	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4539	PPGMPOOLPAGE pNewShwPageCR3;
4540
4541	pgmLock(pVM);
4542
4543	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4544	if (pPool->cDirtyPages)
4545	pgmPoolResetDirtyPages(pVM);
4546	# endif
4547
4548	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4549	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4550	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4551	AssertFatalRC(rc);
4552	rc = VINF_SUCCESS;
4553
4554	# ifdef IN_RC
4555	/*
4556	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4557	* state will be inconsistent! Flush important things now while
4558	* we still can and then make sure there are no ring-3 calls.
4559	*/
4560	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4561	VMMRZCallRing3Disable(pVCpu);
4562	# endif
4563
4564	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4565	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4566	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4567	# ifdef IN_RING0
4568	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4569	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4570	# elif defined(IN_RC)
4571	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4572	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4573	# else
4574	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4575	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4576	# endif
4577
4578	# ifndef PGM_WITHOUT_MAPPINGS
4579	/*
4580	* Apply all hypervisor mappings to the new CR3.
4581	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4582	* make sure we check for conflicts in the new CR3 root.
4583	*/
4584	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4585	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4586	# endif
4587	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4588	AssertRCReturn(rc, rc);
4589	# endif
4590
4591	/* Set the current hypervisor CR3. */
4592	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4593	SELMShadowCR3Changed(pVM, pVCpu);
4594
4595	# ifdef IN_RC
4596	/* NOTE: The state is consistent again. */
4597	VMMRZCallRing3Enable(pVCpu);
4598	# endif
4599
4600	/* Clean up the old CR3 root. */
4601	if ( pOldShwPageCR3
4602	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4603	{
4604	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4605	# ifndef PGM_WITHOUT_MAPPINGS
4606	/* Remove the hypervisor mappings from the shadow page table. */
4607	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4608	# endif
4609	/* Mark the page as unlocked; allow flushing again. */
4610	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4611
4612	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4613	}
4614	pgmUnlock(pVM);
4615	# endif
4616
4617	return rc;
4618	}
4619
4620	/**
4621	* Unmaps the shadow CR3.
4622	*
4623	* @returns VBox status, no specials.
4624	* @param pVCpu The VMCPU handle.
4625	*/
4626	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4627	{
4628	LogFlow(("UnmapCR3\n"));
4629
4630	int rc = VINF_SUCCESS;
4631	PVM pVM = pVCpu->CTX_SUFF(pVM);
4632
4633	/*
4634	* Update guest paging info.
4635	*/
4636	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4637	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4638	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4639	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4640	# endif
4641	pVCpu->pgm.s.pGst32BitPdRC = 0;
4642
4643	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4644	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4645	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4646	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4647	# endif
4648	pVCpu->pgm.s.pGstPaePdptRC = 0;
4649	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4650	{
4651	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4652	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4653	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4654	# endif
4655	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4656	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4657	}
4658
4659	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4660	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4661	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4662	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4663	# endif
4664
4665	#else /* prot/real mode stub */
4666	/* nothing to do */
4667	#endif
4668
4669	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4670	/*
4671	* Update shadow paging info.
4672	*/
4673	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4674	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4675	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4676
4677	# if PGM_GST_TYPE != PGM_TYPE_REAL
4678	Assert(!pVM->pgm.s.fNestedPaging);
4679	# endif
4680
4681	pgmLock(pVM);
4682
4683	# ifndef PGM_WITHOUT_MAPPINGS
4684	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4685	/* Remove the hypervisor mappings from the shadow page table. */
4686	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4687	# endif
4688
4689	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4690	{
4691	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4692
4693	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4694
4695	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4696	if (pPool->cDirtyPages)
4697	pgmPoolResetDirtyPages(pVM);
4698	# endif
4699
4700	/* Mark the page as unlocked; allow flushing again. */
4701	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4702
4703	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4704	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4705	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4706	pVCpu->pgm.s.pShwPageCR3RC = 0;
4707	pVCpu->pgm.s.iShwUser = 0;
4708	pVCpu->pgm.s.iShwUserTable = 0;
4709	}
4710	pgmUnlock(pVM);
4711	# endif
4712	#endif /* !IN_RC*/
4713
4714	return rc;
4715	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 33105

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