PGMAllBth.h@ 40138

Last change on this file since 40138 was 39908, checked in by vboxsync, 13 years ago
Disabled seemingly harmless assertion.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 203.3 KB

Line
1	/* $Id: PGMAllBth.h 39908 2012-01-30 15:31:54Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2010 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
108	{
109	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
110	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
112	return VINF_EM_RAW_EMULATE_INSTR;
113	}
114	# endif
115
116	/*
117	* Calc the error code for the guest trap.
118	*/
119	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
120	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
121	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
122	if (pGstWalk->Core.fBadPhysAddr)
123	{
124	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
125	Assert(!pGstWalk->Core.fNotPresent);
126	}
127	else if (!pGstWalk->Core.fNotPresent)
128	uNewErr \|= X86_TRAP_PF_P;
129	TRPMSetErrorCode(pVCpu, uNewErr);
130
131	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
132	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
136
137
138	/**
139	* Deal with a guest page fault.
140	*
141	* The caller has taken the PGM lock.
142	*
143	* @returns Strict VBox status code.
144	*
145	* @param pVCpu The current CPU.
146	* @param uErr The error code.
147	* @param pRegFrame The register frame.
148	* @param pvFault The fault address.
149	* @param pPage The guest page at @a pvFault.
150	* @param pGstWalk The guest page table walk result.
151	* @param pfLockTaken PGM lock taken here or not (out). This is true
152	* when we're called.
153	*/
154	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
155	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
156	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
157	, PGSTPTWALK pGstWalk
158	# endif
159	)
160	{
161	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
162	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
163	#endif
164	PVM pVM = pVCpu->CTX_SUFF(pVM);
165	int rc;
166
167	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
168	{
169	/*
170	* Physical page access handler.
171	*/
172	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
173	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
174	# else
175	const RTGCPHYS GCPhysFault = (RTGCPHYS)pvFault;
176	# endif
177	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
178	if (pCur)
179	{
180	# ifdef PGM_SYNC_N_PAGES
181	/*
182	* If the region is write protected and we got a page not present fault, then sync
183	* the pages. If the fault was caused by a read, then restart the instruction.
184	* In case of write access continue to the GC write handler.
185	*
186	* ASSUMES that there is only one handler per page or that they have similar write properties.
187	*/
188	if ( !(uErr & X86_TRAP_PF_P)
189	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
190	{
191	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
192	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
193	# else
194	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
195	# endif
196	if ( RT_FAILURE(rc)
197	\|\| !(uErr & X86_TRAP_PF_RW)
198	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
199	{
200	AssertRC(rc);
201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
202	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
203	return rc;
204	}
205	}
206	# endif
207	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
208	/*
209	* If the access was not thru a #PF(RSVD\|...) resync the page.
210	*/
211	if ( !(uErr & X86_TRAP_PF_RSVD)
212	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
213	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
214	&& pGstWalk->Core.fEffectiveRW
215	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
216	# endif
217	)
218	{
219	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
220	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
221	# else
222	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
223	# endif
224	if ( RT_FAILURE(rc)
225	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
226	{
227	AssertRC(rc);
228	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
229	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
230	return rc;
231	}
232	}
233	# endif
234
235	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
236	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
237	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
238	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
239	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
241	else
242	{
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
244	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
245	}
246
247	if (pCur->CTX_SUFF(pfnHandler))
248	{
249	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
250	void *pvUser = pCur->CTX_SUFF(pvUser);
251	# ifdef IN_RING0
252	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
253	# else
254	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
255	# endif
256
257	STAM_PROFILE_START(&pCur->Stat, h);
258	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
259	{
260	pgmUnlock(pVM);
261	*pfLockTaken = false;
262	}
263
264	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
265
266	# ifdef VBOX_WITH_STATISTICS
267	pgmLock(pVM);
268	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
269	if (pCur)
270	STAM_PROFILE_STOP(&pCur->Stat, h);
271	pgmUnlock(pVM);
272	# endif
273	}
274	else
275	rc = VINF_EM_RAW_EMULATE_INSTR;
276
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
278	return rc;
279	}
280	}
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
282	else
283	{
284	# ifdef PGM_SYNC_N_PAGES
285	/*
286	* If the region is write protected and we got a page not present fault, then sync
287	* the pages. If the fault was caused by a read, then restart the instruction.
288	* In case of write access continue to the GC write handler.
289	*/
290	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
291	&& !(uErr & X86_TRAP_PF_P))
292	{
293	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
294	if ( RT_FAILURE(rc)
295	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
296	\|\| !(uErr & X86_TRAP_PF_RW))
297	{
298	AssertRC(rc);
299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
300	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
301	return rc;
302	}
303	}
304	# endif
305	/*
306	* Ok, it's an virtual page access handler.
307	*
308	* Since it's faster to search by address, we'll do that first
309	* and then retry by GCPhys if that fails.
310	*/
311	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
312	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
313	* out of sync, because the page was changed without us noticing it (not-present -> present
314	* without invlpg or mov cr3, xxx).
315	*/
316	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
317	if (pCur)
318	{
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rc;
352	}
353	/* Unhandled part of a monitored page */
354	}
355	else
356	{
357	/* Check by physical address. */
358	unsigned iPage;
359	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
360	Assert(RT_SUCCESS(rc) \|\| !pCur);
361	if ( pCur
362	&& ( uErr & X86_TRAP_PF_RW
363	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
364	{
365	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
366	# ifdef IN_RC
367	STAM_PROFILE_START(&pCur->Stat, h);
368	RTGCPTR GCPtrStart = pCur->Core.Key;
369	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
370	pgmUnlock(pVM);
371	*pfLockTaken = false;
372
373	RTGCPTR off = (iPage << PAGE_SHIFT)
374	+ (pvFault & PAGE_OFFSET_MASK)
375	- (GCPtrStart & PAGE_OFFSET_MASK);
376	Assert(off < pCur->cb);
377	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
378
379	# ifdef VBOX_WITH_STATISTICS
380	pgmLock(pVM);
381	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
382	if (pCur)
383	STAM_PROFILE_STOP(&pCur->Stat, h);
384	pgmUnlock(pVM);
385	# endif
386	# else
387	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
388	# endif
389	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
390	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
391	return rc;
392	}
393	}
394	}
395	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
396
397	/*
398	* There is a handled area of the page, but this fault doesn't belong to it.
399	* We must emulate the instruction.
400	*
401	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
402	* we first check if this was a page-not-present fault for a page with only
403	* write access handlers. Restart the instruction if it wasn't a write access.
404	*/
405	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
406
407	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
408	&& !(uErr & X86_TRAP_PF_P))
409	{
410	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
411	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
412	# else
413	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
414	# endif
415	if ( RT_FAILURE(rc)
416	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
417	\|\| !(uErr & X86_TRAP_PF_RW))
418	{
419	AssertRC(rc);
420	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
422	return rc;
423	}
424	}
425
426	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
427	* It's writing to an unhandled part of the LDT page several million times.
428	*/
429	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
430	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
431	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
432	return rc;
433	} /* if any kind of handler */
434
435
436	/**
437	* #PF Handler for raw-mode guest execution.
438	*
439	* @returns VBox status code (appropriate for trap handling and GC return).
440	*
441	* @param pVCpu VMCPU Handle.
442	* @param uErr The trap error code.
443	* @param pRegFrame Trap register frame.
444	* @param pvFault The fault address.
445	* @param pfLockTaken PGM lock taken here or not (out)
446	*/
447	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
448	{
449	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
450
451	*pfLockTaken = false;
452
453	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
454	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
455	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
456	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
457	int rc;
458
459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
460	/*
461	* Walk the guest page translation tables and check if it's a guest fault.
462	*/
463	GSTPTWALK GstWalk;
464	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
465	if (RT_FAILURE_NP(rc))
466	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
467
468	/* assert some GstWalk sanity. */
469	# if PGM_GST_TYPE == PGM_TYPE_AMD64
470	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
471	# endif
472	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
473	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
474	# endif
475	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
476	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
477	Assert(GstWalk.Core.fSucceeded);
478
479	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
480	{
481	if ( ( (uErr & X86_TRAP_PF_RW)
482	&& !GstWalk.Core.fEffectiveRW
483	&& ( (uErr & X86_TRAP_PF_US)
484	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
485	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
486	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
487	)
488	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
489	}
490
491	/*
492	* Set the accessed and dirty flags.
493	*/
494	# if PGM_GST_TYPE == PGM_TYPE_AMD64
495	GstWalk.Pml4e.u \|= X86_PML4E_A;
496	GstWalk.pPml4e->u \|= X86_PML4E_A;
497	GstWalk.Pdpe.u \|= X86_PDPE_A;
498	GstWalk.pPdpe->u \|= X86_PDPE_A;
499	# endif
500	if (GstWalk.Core.fBigPage)
501	{
502	Assert(GstWalk.Pde.b.u1Size);
503	if (uErr & X86_TRAP_PF_RW)
504	{
505	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
506	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
507	}
508	else
509	{
510	GstWalk.Pde.u \|= X86_PDE4M_A;
511	GstWalk.pPde->u \|= X86_PDE4M_A;
512	}
513	}
514	else
515	{
516	Assert(!GstWalk.Pde.b.u1Size);
517	GstWalk.Pde.u \|= X86_PDE_A;
518	GstWalk.pPde->u \|= X86_PDE_A;
519	if (uErr & X86_TRAP_PF_RW)
520	{
521	# ifdef VBOX_WITH_STATISTICS
522	if (!GstWalk.Pte.n.u1Dirty)
523	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
524	else
525	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
526	# endif
527	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
528	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
529	}
530	else
531	{
532	GstWalk.Pte.u \|= X86_PTE_A;
533	GstWalk.pPte->u \|= X86_PTE_A;
534	}
535	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
536	}
537	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
538	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
539	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
540	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
541	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
542
543	/* Take the big lock now. */
544	*pfLockTaken = true;
545	pgmLock(pVM);
546
547	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
548	/*
549	* If it is a reserved bit fault we know that it is an MMIO (access
550	* handler) related fault and can skip some 200 lines of code.
551	*/
552	if (uErr & X86_TRAP_PF_RSVD)
553	{
554	Assert(uErr & X86_TRAP_PF_P);
555	PPGMPAGE pPage;
556	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
557	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
558	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
559	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
560	pfLockTaken, &GstWalk));
561	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
562	# else
563	rc = pgmPhysGetPageEx(pVM, (RTGCPHYS)pvFault, &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
566	pfLockTaken));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
568	# endif
569	AssertRC(rc);
570	PGM_INVL_PG(pVCpu, pvFault);
571	return rc; /* Restart with the corrected entry. */
572	}
573	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
574
575	/*
576	* Fetch the guest PDE, PDPE and PML4E.
577	*/
578	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
579	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
580	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
583	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PAE
586	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
587	# else
588	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
589	# endif
590	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
591
592	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
593	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
594	PX86PDPAE pPDDst;
595	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
596	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
597	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
598	# else
599	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
600	# endif
601	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
602
603	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
604	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
605	PEPTPD pPDDst;
606	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
607	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
608	# endif
609	Assert(pPDDst);
610
611	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
612	/*
613	* Dirty page handling.
614	*
615	* If we successfully correct the write protection fault due to dirty bit
616	* tracking, then return immediately.
617	*/
618	if (uErr & X86_TRAP_PF_RW) /* write fault? */
619	{
620	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
621	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
622	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
623	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
624	{
625	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
626	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
627	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
628	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
629	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
630	return VINF_SUCCESS;
631	}
632	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
633	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
634	}
635
636	# if 0 /* rarely useful; leave for debugging. */
637	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
638	# endif
639	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
640
641	/*
642	* A common case is the not-present error caused by lazy page table syncing.
643	*
644	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
645	* here so we can safely assume that the shadow PT is present when calling
646	* SyncPage later.
647	*
648	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
649	* of mapping conflict and defer to SyncCR3 in R3.
650	* (Again, we do NOT support access handlers for non-present guest pages.)
651	*
652	*/
653	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
654	Assert(GstWalk.Pde.n.u1Present);
655	# endif
656	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
657	&& !pPDDst->a[iPDDst].n.u1Present)
658	{
659	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
662	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
663	# else
664	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
665	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
666	# endif
667	if (RT_SUCCESS(rc))
668	return rc;
669	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
670	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
671	return VINF_PGM_SYNC_CR3;
672	}
673
674	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
675	/*
676	* Check if this address is within any of our mappings.
677	*
678	* This is very fast and it's gonna save us a bit of effort below and prevent
679	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
680	* (BTW, it's impossible to have physical access handlers in a mapping.)
681	*/
682	if (pgmMapAreMappingsEnabled(pVM))
683	{
684	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
685	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
686	{
687	if (pvFault < pMapping->GCPtr)
688	break;
689	if (pvFault - pMapping->GCPtr < pMapping->cb)
690	{
691	/*
692	* The first thing we check is if we've got an undetected conflict.
693	*/
694	if (pgmMapAreMappingsFloating(pVM))
695	{
696	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
697	while (iPT-- > 0)
698	if (GstWalk.pPde[iPT].n.u1Present)
699	{
700	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
701	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
702	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
703	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
704	return VINF_PGM_SYNC_CR3;
705	}
706	}
707
708	/*
709	* Check if the fault address is in a virtual page access handler range.
710	*/
711	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
712	if ( pCur
713	&& pvFault - pCur->Core.Key < pCur->cb
714	&& uErr & X86_TRAP_PF_RW)
715	{
716	# ifdef IN_RC
717	STAM_PROFILE_START(&pCur->Stat, h);
718	pgmUnlock(pVM);
719	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
720	pgmLock(pVM);
721	STAM_PROFILE_STOP(&pCur->Stat, h);
722	# else
723	AssertFailed();
724	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
725	# endif
726	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return rc;
729	}
730
731	/*
732	* Pretend we're not here and let the guest handle the trap.
733	*/
734	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
736	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
737	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
738	return VINF_EM_RAW_GUEST_TRAP;
739	}
740	}
741	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
742	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
743
744	/*
745	* Check if this fault address is flagged for special treatment,
746	* which means we'll have to figure out the physical address and
747	* check flags associated with it.
748	*
749	* ASSUME that we can limit any special access handling to pages
750	* in page tables which the guest believes to be present.
751	*/
752	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
753	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
754	# else
755	RTGCPHYS GCPhys = (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK;
756	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
757	PPGMPAGE pPage;
758	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
759	if (RT_FAILURE(rc))
760	{
761	/*
762	* When the guest accesses invalid physical memory (e.g. probing
763	* of RAM or accessing a remapped MMIO range), then we'll fall
764	* back to the recompiler to emulate the instruction.
765	*/
766	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
767	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
768	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
769	return VINF_EM_RAW_EMULATE_INSTR;
770	}
771
772	/*
773	* Any handlers for this page?
774	*/
775	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
776	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
777	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
778	&GstWalk));
779	# else
780	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
781	# endif
782
783	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
784
785	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
786	if (uErr & X86_TRAP_PF_P)
787	{
788	/*
789	* The page isn't marked, but it might still be monitored by a virtual page access handler.
790	* (ASSUMES no temporary disabling of virtual handlers.)
791	*/
792	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
793	* we should correct both the shadow page table and physical memory flags, and not only check for
794	* accesses within the handler region but for access to pages with virtual handlers. */
795	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
796	if (pCur)
797	{
798	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
799	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
800	\|\| !(uErr & X86_TRAP_PF_P)
801	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
802	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
803
804	if ( pvFault - pCur->Core.Key < pCur->cb
805	&& ( uErr & X86_TRAP_PF_RW
806	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
807	{
808	# ifdef IN_RC
809	STAM_PROFILE_START(&pCur->Stat, h);
810	pgmUnlock(pVM);
811	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
812	pgmLock(pVM);
813	STAM_PROFILE_STOP(&pCur->Stat, h);
814	# else
815	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
816	# endif
817	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
818	return rc;
819	}
820	}
821	}
822	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
823
824	/*
825	* We are here only if page is present in Guest page tables and
826	* trap is not handled by our handlers.
827	*
828	* Check it for page out-of-sync situation.
829	*/
830	if (!(uErr & X86_TRAP_PF_P))
831	{
832	/*
833	* Page is not present in our page tables. Try to sync it!
834	*/
835	if (uErr & X86_TRAP_PF_US)
836	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
837	else /* supervisor */
838	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
839
840	if (PGM_PAGE_IS_BALLOONED(pPage))
841	{
842	/* Emulate reads from ballooned pages as they are not present in
843	our shadow page tables. (Required for e.g. Solaris guests; soft
844	ecc, random nr generator.) */
845	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
846	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
847	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
848	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
849	return rc;
850	}
851
852	# if defined(LOG_ENABLED) && !defined(IN_RING0)
853	RTGCPHYS GCPhys2;
854	uint64_t fPageGst2;
855	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
856	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
857	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
858	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
859	# else
860	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
861	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
862	# endif
863	# endif /* LOG_ENABLED */
864
865	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
866	if ( !GstWalk.Core.fEffectiveUS
867	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
868	{
869	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
870	if ( pvFault == (RTGCPTR)pRegFrame->eip
871	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
872	# ifdef CSAM_DETECT_NEW_CODE_PAGES
873	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
874	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
875	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
876	)
877	{
878	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
879	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
880	if (rc != VINF_SUCCESS)
881	{
882	/*
883	* CSAM needs to perform a job in ring 3.
884	*
885	* Sync the page before going to the host context; otherwise we'll end up in a loop if
886	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
887	*/
888	LogFlow(("CSAM ring 3 job\n"));
889	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
890	AssertRC(rc2);
891
892	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
893	return rc;
894	}
895	}
896	# ifdef CSAM_DETECT_NEW_CODE_PAGES
897	else if ( uErr == X86_TRAP_PF_RW
898	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
899	&& pRegFrame->ecx < 0x10000)
900	{
901	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
902	* to detect loading of new code pages.
903	*/
904
905	/*
906	* Decode the instruction.
907	*/
908	RTGCPTR PC;
909	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs,
910	&pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
911	if (rc == VINF_SUCCESS)
912	{
913	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
914	uint32_t cbOp;
915	rc = EMInterpretDisasOneEx(pVM, pVCpu, PC, pRegFrame, pDis, &cbOp);
916
917	/* For now we'll restrict this to rep movsw/d instructions */
918	if ( rc == VINF_SUCCESS
919	&& pDis->pCurInstr->opcode == OP_MOVSWD
920	&& (pDis->prefix & PREFIX_REP))
921	{
922	CSAMMarkPossibleCodePage(pVM, pvFault);
923	}
924	}
925	}
926	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
927
928	/*
929	* Mark this page as safe.
930	*/
931	/** @todo not correct for pages that contain both code and data!! */
932	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
933	CSAMMarkPage(pVM, pvFault, true);
934	}
935	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
936	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
937	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
938	# else
939	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
940	# endif
941	if (RT_SUCCESS(rc))
942	{
943	/* The page was successfully synced, return to the guest. */
944	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
945	return VINF_SUCCESS;
946	}
947	}
948	else /* uErr & X86_TRAP_PF_P: */
949	{
950	/*
951	* Write protected pages are made writable when the guest makes the
952	* first write to it. This happens for pages that are shared, write
953	* monitored or not yet allocated.
954	*
955	* We may also end up here when CR0.WP=0 in the guest.
956	*
957	* Also, a side effect of not flushing global PDEs are out of sync
958	* pages due to physical monitored regions, that are no longer valid.
959	* Assume for now it only applies to the read/write flag.
960	*/
961	if (uErr & X86_TRAP_PF_RW)
962	{
963	/*
964	* Check if it is a read-only page.
965	*/
966	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
967	{
968	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
969	Assert(!PGM_PAGE_IS_ZERO(pPage));
970	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
971	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
972
973	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
974	if (rc != VINF_SUCCESS)
975	{
976	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
977	return rc;
978	}
979	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
980	return VINF_EM_NO_MEMORY;
981	}
982
983	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
984	/*
985	* Check to see if we need to emulate the instruction if CR0.WP=0.
986	*/
987	if ( !GstWalk.Core.fEffectiveRW
988	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
989	&& CPUMGetGuestCPL(pVCpu, pRegFrame) == 0)
990	{
991	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
992	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
993	if (RT_SUCCESS(rc))
994	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
995	else
996	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
997	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
998	return rc;
999	}
1000	# endif
1001	/// @todo count the above case; else
1002	if (uErr & X86_TRAP_PF_US)
1003	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1004	else /* supervisor */
1005	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1006
1007	/*
1008	* Sync the page.
1009	*
1010	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1011	* page is not present, which is not true in this case.
1012	*/
1013	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1014	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1015	# else
1016	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1017	# endif
1018	if (RT_SUCCESS(rc))
1019	{
1020	/*
1021	* Page was successfully synced, return to guest but invalidate
1022	* the TLB first as the page is very likely to be in it.
1023	*/
1024	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1025	HWACCMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1026	# else
1027	PGM_INVL_PG(pVCpu, pvFault);
1028	# endif
1029	# ifdef VBOX_STRICT
1030	RTGCPHYS GCPhys2;
1031	uint64_t fPageGst;
1032	if (!pVM->pgm.s.fNestedPaging)
1033	{
1034	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1035	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1036	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1037	}
1038	uint64_t fPageShw;
1039	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1040	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1041	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1042	# endif /* VBOX_STRICT */
1043	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1044	return VINF_SUCCESS;
1045	}
1046	}
1047	/** @todo else: why are we here? */
1048
1049	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1050	/*
1051	* Check for VMM page flags vs. Guest page flags consistency.
1052	* Currently only for debug purposes.
1053	*/
1054	if (RT_SUCCESS(rc))
1055	{
1056	/* Get guest page flags. */
1057	uint64_t fPageGst;
1058	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1059	if (RT_SUCCESS(rc))
1060	{
1061	uint64_t fPageShw;
1062	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1063
1064	/*
1065	* Compare page flags.
1066	* Note: we have AVL, A, D bits desynced.
1067	*/
1068	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1069	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1070	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1071	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1072	}
1073	else
1074	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1075	}
1076	else
1077	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1078	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1079	}
1080
1081
1082	/*
1083	* If we get here it is because something failed above, i.e. most like guru
1084	* meditiation time.
1085	*/
1086	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1087	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs, pRegFrame->rip));
1088	return rc;
1089
1090	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1091	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1092	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1093	return VERR_PGM_NOT_USED_IN_MODE;
1094	# endif
1095	}
1096	#endif /* !IN_RING3 */
1097
1098
1099	/**
1100	* Emulation of the invlpg instruction.
1101	*
1102	*
1103	* @returns VBox status code.
1104	*
1105	* @param pVCpu The VMCPU handle.
1106	* @param GCPtrPage Page to invalidate.
1107	*
1108	* @remark ASSUMES that the guest is updating before invalidating. This order
1109	* isn't required by the CPU, so this is speculative and could cause
1110	* trouble.
1111	* @remark No TLB shootdown is done on any other VCPU as we assume that
1112	* invlpg emulation is the only reason for calling this function.
1113	* (The guest has to shoot down TLB entries on other CPUs itself)
1114	* Currently true, but keep in mind!
1115	*
1116	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1117	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1118	*/
1119	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1120	{
1121	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1122	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1123	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1124	int rc;
1125	PVM pVM = pVCpu->CTX_SUFF(pVM);
1126	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1127
1128	PGM_LOCK_ASSERT_OWNER(pVM);
1129
1130	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1131
1132	/*
1133	* Get the shadow PD entry and skip out if this PD isn't present.
1134	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1135	*/
1136	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1137	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1138	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1139
1140	/* Fetch the pgm pool shadow descriptor. */
1141	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1142	Assert(pShwPde);
1143
1144	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1145	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1146	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1147
1148	/* If the shadow PDPE isn't present, then skip the invalidate. */
1149	if (!pPdptDst->a[iPdpt].n.u1Present)
1150	{
1151	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1152	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1153	return VINF_SUCCESS;
1154	}
1155
1156	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1157	PPGMPOOLPAGE pShwPde = NULL;
1158	PX86PDPAE pPDDst;
1159
1160	/* Fetch the pgm pool shadow descriptor. */
1161	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1162	AssertRCSuccessReturn(rc, rc);
1163	Assert(pShwPde);
1164
1165	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1166	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1167
1168	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1169	/* PML4 */
1170	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1171	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1172	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1173	PX86PDPAE pPDDst;
1174	PX86PDPT pPdptDst;
1175	PX86PML4E pPml4eDst;
1176	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1177	if (rc != VINF_SUCCESS)
1178	{
1179	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1180	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1181	return VINF_SUCCESS;
1182	}
1183	Assert(pPDDst);
1184
1185	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1186	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1187
1188	if (!pPdpeDst->n.u1Present)
1189	{
1190	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1191	return VINF_SUCCESS;
1192	}
1193
1194	/* Fetch the pgm pool shadow descriptor. */
1195	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1196	Assert(pShwPde);
1197
1198	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1199
1200	const SHWPDE PdeDst = *pPdeDst;
1201	if (!PdeDst.n.u1Present)
1202	{
1203	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1204	return VINF_SUCCESS;
1205	}
1206
1207	/*
1208	* Get the guest PD entry and calc big page.
1209	*/
1210	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1211	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1212	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1213	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1214	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1215	unsigned iPDSrc = 0;
1216	# if PGM_GST_TYPE == PGM_TYPE_PAE
1217	X86PDPE PdpeSrcIgn;
1218	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1219	# else /* AMD64 */
1220	PX86PML4E pPml4eSrcIgn;
1221	X86PDPE PdpeSrcIgn;
1222	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1223	# endif
1224	GSTPDE PdeSrc;
1225
1226	if (pPDSrc)
1227	PdeSrc = pPDSrc->a[iPDSrc];
1228	else
1229	PdeSrc.u = 0;
1230	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1231	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1232
1233	# ifdef IN_RING3
1234	/*
1235	* If a CR3 Sync is pending we may ignore the invalidate page operation
1236	* depending on the kind of sync and if it's a global page or not.
1237	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1238	*/
1239	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1240	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1241	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1242	&& fIsBigPage
1243	&& PdeSrc.b.u1Global
1244	)
1245	)
1246	# else
1247	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1248	# endif
1249	{
1250	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1251	return VINF_SUCCESS;
1252	}
1253	# endif /* IN_RING3 */
1254
1255	/*
1256	* Deal with the Guest PDE.
1257	*/
1258	rc = VINF_SUCCESS;
1259	if (PdeSrc.n.u1Present)
1260	{
1261	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1262	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1263	# ifndef PGM_WITHOUT_MAPPING
1264	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1265	{
1266	/*
1267	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1268	*/
1269	Assert(pgmMapAreMappingsEnabled(pVM));
1270	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1271	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1272	}
1273	else
1274	# endif /* !PGM_WITHOUT_MAPPING */
1275	if (!fIsBigPage)
1276	{
1277	/*
1278	* 4KB - page.
1279	*/
1280	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1281	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1282
1283	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1284	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1285	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1286	# endif
1287	if (pShwPage->GCPhys == GCPhys)
1288	{
1289	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1290	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1291
1292	PGSTPT pPTSrc;
1293	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1294	if (RT_SUCCESS(rc))
1295	{
1296	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1297	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1298	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1299	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1300	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1301	GCPtrPage, PteSrc.n.u1Present,
1302	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1303	PteSrc.n.u1User & PdeSrc.n.u1User,
1304	(uint64_t)PteSrc.u,
1305	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1306	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1307	}
1308	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1309	PGM_INVL_PG(pVCpu, GCPtrPage);
1310	}
1311	else
1312	{
1313	/*
1314	* The page table address changed.
1315	*/
1316	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1317	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1318	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1319	ASMAtomicWriteSize(pPdeDst, 0);
1320	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1321	PGM_INVL_VCPU_TLBS(pVCpu);
1322	}
1323	}
1324	else
1325	{
1326	/*
1327	* 2/4MB - page.
1328	*/
1329	/* Before freeing the page, check if anything really changed. */
1330	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1331	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1332	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1333	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1334	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1335	# endif
1336	if ( pShwPage->GCPhys == GCPhys
1337	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1338	{
1339	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1340	/** @todo This test is wrong as it cannot check the G bit!
1341	* FIXME */
1342	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1343	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1344	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1345	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1346	{
1347	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1348	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1349	return VINF_SUCCESS;
1350	}
1351	}
1352
1353	/*
1354	* Ok, the page table is present and it's been changed in the guest.
1355	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1356	* We could do this for some flushes in GC too, but we need an algorithm for
1357	* deciding which 4MB pages containing code likely to be executed very soon.
1358	*/
1359	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1360	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1361	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1362	ASMAtomicWriteSize(pPdeDst, 0);
1363	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1364	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1365	}
1366	}
1367	else
1368	{
1369	/*
1370	* Page directory is not present, mark shadow PDE not present.
1371	*/
1372	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1373	{
1374	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1375	ASMAtomicWriteSize(pPdeDst, 0);
1376	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1377	PGM_INVL_PG(pVCpu, GCPtrPage);
1378	}
1379	else
1380	{
1381	Assert(pgmMapAreMappingsEnabled(pVM));
1382	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1383	}
1384	}
1385	return rc;
1386
1387	#else /* guest real and protected mode */
1388	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1389	NOREF(pVCpu); NOREF(GCPtrPage);
1390	return VINF_SUCCESS;
1391	#endif
1392	}
1393
1394
1395	/**
1396	* Update the tracking of shadowed pages.
1397	*
1398	* @param pVCpu The VMCPU handle.
1399	* @param pShwPage The shadow page.
1400	* @param HCPhys The physical page we is being dereferenced.
1401	* @param iPte Shadow PTE index
1402	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1403	*/
1404	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1405	RTGCPHYS GCPhysPage)
1406	{
1407	PVM pVM = pVCpu->CTX_SUFF(pVM);
1408
1409	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1410	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1411	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1412
1413	/* Use the hint we retrieved from the cached guest PT. */
1414	if (pShwPage->fDirty)
1415	{
1416	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1417
1418	Assert(pShwPage->cPresent);
1419	Assert(pPool->cPresent);
1420	pShwPage->cPresent--;
1421	pPool->cPresent--;
1422
1423	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1424	AssertRelease(pPhysPage);
1425	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1426	return;
1427	}
1428	# else
1429	NOREF(GCPhysPage);
1430	# endif
1431
1432	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1433	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1434
1435	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1436	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1437	* 2. write protect all shadowed pages. I.e. implement caching.
1438	*/
1439	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1440
1441	/*
1442	* Find the guest address.
1443	*/
1444	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1445	pRam;
1446	pRam = pRam->CTX_SUFF(pNext))
1447	{
1448	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1449	while (iPage-- > 0)
1450	{
1451	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1452	{
1453	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1454
1455	Assert(pShwPage->cPresent);
1456	Assert(pPool->cPresent);
1457	pShwPage->cPresent--;
1458	pPool->cPresent--;
1459
1460	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1461	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1462	return;
1463	}
1464	}
1465	}
1466
1467	for (;;)
1468	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1469	}
1470
1471
1472	/**
1473	* Update the tracking of shadowed pages.
1474	*
1475	* @param pVCpu The VMCPU handle.
1476	* @param pShwPage The shadow page.
1477	* @param u16 The top 16-bit of the pPage->HCPhys.
1478	* @param pPage Pointer to the guest page. this will be modified.
1479	* @param iPTDst The index into the shadow table.
1480	*/
1481	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1482	{
1483	PVM pVM = pVCpu->CTX_SUFF(pVM);
1484
1485	/*
1486	* Just deal with the simple first time here.
1487	*/
1488	if (!u16)
1489	{
1490	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1491	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1492	/* Save the page table index. */
1493	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1494	}
1495	else
1496	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1497
1498	/* write back */
1499	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1500	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1501
1502	/* update statistics. */
1503	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1504	pShwPage->cPresent++;
1505	if (pShwPage->iFirstPresent > iPTDst)
1506	pShwPage->iFirstPresent = iPTDst;
1507	}
1508
1509
1510	/**
1511	* Modifies a shadow PTE to account for access handlers.
1512	*
1513	* @param pVM The VM handle.
1514	* @param pPage The page in question.
1515	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1516	* A (accessed) bit so it can be emulated correctly.
1517	* @param pPteDst The shadow PTE (output). This is temporary storage and
1518	* does not need to be set atomically.
1519	*/
1520	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1521	{
1522	NOREF(pVM);
1523	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1524	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1525	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1526	{
1527	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1528	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1529	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1530	pPteDst->n.u1Present = 1;
1531	pPteDst->n.u1Execute = 1;
1532	pPteDst->n.u1IgnorePAT = 1;
1533	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1534	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1535	#else
1536	if (fPteSrc & X86_PTE_A)
1537	{
1538	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1539	SHW_PTE_SET_RO(*pPteDst);
1540	}
1541	else
1542	SHW_PTE_SET(*pPteDst, 0);
1543	#endif
1544	}
1545	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1546	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1547	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1548	&& ( BTH_IS_NP_ACTIVE(pVM)
1549	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1550	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1551	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1552	# endif
1553	)
1554	{
1555	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1556	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1557	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1558	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1559	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1560	pPteDst->n.u1Present = 0;
1561	pPteDst->n.u1Write = 1;
1562	pPteDst->n.u1Execute = 0;
1563	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1564	pPteDst->n.u3EMT = 7;
1565	# else
1566	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1567	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1568	# endif
1569	}
1570	# endif
1571	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1572	else
1573	{
1574	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1575	SHW_PTE_SET(*pPteDst, 0);
1576	}
1577	/** @todo count these kinds of entries. */
1578	}
1579
1580
1581	/**
1582	* Creates a 4K shadow page for a guest page.
1583	*
1584	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1585	* physical address. The PdeSrc argument only the flags are used. No page
1586	* structured will be mapped in this function.
1587	*
1588	* @param pVCpu The VMCPU handle.
1589	* @param pPteDst Destination page table entry.
1590	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1591	* Can safely assume that only the flags are being used.
1592	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1593	* @param pShwPage Pointer to the shadow page.
1594	* @param iPTDst The index into the shadow table.
1595	*
1596	* @remark Not used for 2/4MB pages!
1597	*/
1598	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1599	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1600	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1601	#else
1602	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1603	#endif
1604	{
1605	PVM pVM = pVCpu->CTX_SUFF(pVM);
1606	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1607
1608	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1609	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1610	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1611
1612	if (pShwPage->fDirty)
1613	{
1614	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1615	PGSTPT pGstPT;
1616
1617	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1618	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirty].aPage[0];
1619	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1620	pGstPT->a[iPTDst].u = PteSrc.u;
1621	}
1622	#else
1623	Assert(!pShwPage->fDirty);
1624	#endif
1625
1626	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1627	if ( PteSrc.n.u1Present
1628	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1629	#endif
1630	{
1631	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1632	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1633	# endif
1634	/*
1635	* Find the ram range.
1636	*/
1637	PPGMPAGE pPage;
1638	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1639	if (RT_SUCCESS(rc))
1640	{
1641	/* Ignore ballooned pages.
1642	Don't return errors or use a fatal assert here as part of a
1643	shadow sync range might included ballooned pages. */
1644	if (PGM_PAGE_IS_BALLOONED(pPage))
1645	{
1646	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1647	return;
1648	}
1649
1650	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1651	/* Make the page writable if necessary. */
1652	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1653	&& ( PGM_PAGE_IS_ZERO(pPage)
1654	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1655	\|\| ( PteSrc.n.u1Write
1656	# else
1657	\|\| ( 1
1658	# endif
1659	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1660	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1661	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1662	# endif
1663	# ifdef VBOX_WITH_PAGE_SHARING
1664	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1665	# endif
1666	)
1667	)
1668	)
1669	{
1670	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1671	AssertRC(rc);
1672	}
1673	#endif
1674
1675	/*
1676	* Make page table entry.
1677	*/
1678	SHWPTE PteDst;
1679	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1680	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1681	# else
1682	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1683	# endif
1684	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1685	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1686	else
1687	{
1688	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1689	/*
1690	* If the page or page directory entry is not marked accessed,
1691	* we mark the page not present.
1692	*/
1693	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1694	{
1695	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1696	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1697	SHW_PTE_SET(PteDst, 0);
1698	}
1699	/*
1700	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1701	* when the page is modified.
1702	*/
1703	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1704	{
1705	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1706	SHW_PTE_SET(PteDst,
1707	fGstShwPteFlags
1708	\| PGM_PAGE_GET_HCPHYS(pPage)
1709	\| PGM_PTFLAGS_TRACK_DIRTY);
1710	SHW_PTE_SET_RO(PteDst);
1711	}
1712	else
1713	#endif
1714	{
1715	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1716	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1717	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1718	PteDst.n.u1Present = 1;
1719	PteDst.n.u1Write = 1;
1720	PteDst.n.u1Execute = 1;
1721	PteDst.n.u1IgnorePAT = 1;
1722	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1723	/* PteDst.n.u1Size = 0 */
1724	#else
1725	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1726	#endif
1727	}
1728
1729	/*
1730	* Make sure only allocated pages are mapped writable.
1731	*/
1732	if ( SHW_PTE_IS_P_RW(PteDst)
1733	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1734	{
1735	/* Still applies to shared pages. */
1736	Assert(!PGM_PAGE_IS_ZERO(pPage));
1737	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1738	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1739	}
1740	}
1741
1742	/*
1743	* Keep user track up to date.
1744	*/
1745	if (SHW_PTE_IS_P(PteDst))
1746	{
1747	if (!SHW_PTE_IS_P(*pPteDst))
1748	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1749	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1750	{
1751	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1752	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1753	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1754	}
1755	}
1756	else if (SHW_PTE_IS_P(*pPteDst))
1757	{
1758	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1759	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1760	}
1761
1762	/*
1763	* Update statistics and commit the entry.
1764	*/
1765	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1766	if (!PteSrc.n.u1Global)
1767	pShwPage->fSeenNonGlobal = true;
1768	#endif
1769	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1770	return;
1771	}
1772
1773	/** @todo count these three different kinds. */
1774	Log2(("SyncPageWorker: invalid address in Pte\n"));
1775	}
1776	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1777	else if (!PteSrc.n.u1Present)
1778	Log2(("SyncPageWorker: page not present in Pte\n"));
1779	else
1780	Log2(("SyncPageWorker: invalid Pte\n"));
1781	#endif
1782
1783	/*
1784	* The page is not present or the PTE is bad. Replace the shadow PTE by
1785	* an empty entry, making sure to keep the user tracking up to date.
1786	*/
1787	if (SHW_PTE_IS_P(*pPteDst))
1788	{
1789	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1790	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1791	}
1792	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1793	}
1794
1795
1796	/**
1797	* Syncs a guest OS page.
1798	*
1799	* There are no conflicts at this point, neither is there any need for
1800	* page table allocations.
1801	*
1802	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1803	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1804	*
1805	* @returns VBox status code.
1806	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1807	* @param pVCpu The VMCPU handle.
1808	* @param PdeSrc Page directory entry of the guest.
1809	* @param GCPtrPage Guest context page address.
1810	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1811	* @param uErr Fault error (X86_TRAP_PF_*).
1812	*/
1813	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1814	{
1815	PVM pVM = pVCpu->CTX_SUFF(pVM);
1816	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1817	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1818
1819	PGM_LOCK_ASSERT_OWNER(pVM);
1820
1821	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1822	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1823	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1824	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1825	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1826
1827	/*
1828	* Assert preconditions.
1829	*/
1830	Assert(PdeSrc.n.u1Present);
1831	Assert(cPages);
1832	# if 0 /* rarely useful; leave for debugging. */
1833	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1834	# endif
1835
1836	/*
1837	* Get the shadow PDE, find the shadow page table in the pool.
1838	*/
1839	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1840	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1841	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1842
1843	/* Fetch the pgm pool shadow descriptor. */
1844	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1845	Assert(pShwPde);
1846
1847	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1848	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1849	PPGMPOOLPAGE pShwPde = NULL;
1850	PX86PDPAE pPDDst;
1851
1852	/* Fetch the pgm pool shadow descriptor. */
1853	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1854	AssertRCSuccessReturn(rc2, rc2);
1855	Assert(pShwPde);
1856
1857	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1858	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1859
1860	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1861	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1862	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1863	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1864	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1865
1866	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1867	AssertRCSuccessReturn(rc2, rc2);
1868	Assert(pPDDst && pPdptDst);
1869	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1870	# endif
1871	SHWPDE PdeDst = *pPdeDst;
1872
1873	/*
1874	* - In the guest SMP case we could have blocked while another VCPU reused
1875	* this page table.
1876	* - With W7-64 we may also take this path when the the A bit is cleared on
1877	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1878	* relevant TLB entries. If we're write monitoring any page mapped by
1879	* the modified entry, we may end up here with a "stale" TLB entry.
1880	*/
1881	if (!PdeDst.n.u1Present)
1882	{
1883	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1884	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1885	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1886	if (uErr & X86_TRAP_PF_P)
1887	PGM_INVL_PG(pVCpu, GCPtrPage);
1888	return VINF_SUCCESS; /* force the instruction to be executed again. */
1889	}
1890
1891	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1892	Assert(pShwPage);
1893
1894	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1895	/* Fetch the pgm pool shadow descriptor. */
1896	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1897	Assert(pShwPde);
1898	# endif
1899
1900	/*
1901	* Check that the page is present and that the shadow PDE isn't out of sync.
1902	*/
1903	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1904	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1905	RTGCPHYS GCPhys;
1906	if (!fBigPage)
1907	{
1908	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1909	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1910	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1911	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1912	# endif
1913	}
1914	else
1915	{
1916	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1917	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1918	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1919	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1920	# endif
1921	}
1922	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1923	if ( fPdeValid
1924	&& pShwPage->GCPhys == GCPhys
1925	&& PdeSrc.n.u1Present
1926	&& PdeSrc.n.u1User == PdeDst.n.u1User
1927	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1928	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1929	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1930	# endif
1931	)
1932	{
1933	/*
1934	* Check that the PDE is marked accessed already.
1935	* Since we set the accessed bit before getting here on a #PF, this
1936	* check is only meant for dealing with non-#PF'ing paths.
1937	*/
1938	if (PdeSrc.n.u1Accessed)
1939	{
1940	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1941	if (!fBigPage)
1942	{
1943	/*
1944	* 4KB Page - Map the guest page table.
1945	*/
1946	PGSTPT pPTSrc;
1947	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1948	if (RT_SUCCESS(rc))
1949	{
1950	# ifdef PGM_SYNC_N_PAGES
1951	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1952	if ( cPages > 1
1953	&& !(uErr & X86_TRAP_PF_P)
1954	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1955	{
1956	/*
1957	* This code path is currently only taken when the caller is PGMTrap0eHandler
1958	* for non-present pages!
1959	*
1960	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1961	* deal with locality.
1962	*/
1963	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1964	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1965	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1966	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1967	# else
1968	const unsigned offPTSrc = 0;
1969	# endif
1970	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1971	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1972	iPTDst = 0;
1973	else
1974	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1975
1976	for (; iPTDst < iPTDstEnd; iPTDst++)
1977	{
1978	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1979
1980	if ( pPteSrc->n.u1Present
1981	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1982	{
1983	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1984	NOREF(GCPtrCurPage);
1985	#ifndef IN_RING0
1986	/*
1987	* Assuming kernel code will be marked as supervisor - and not as user level
1988	* and executed using a conforming code selector - And marked as readonly.
1989	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1990	*/
1991	PPGMPAGE pPage;
1992	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1993	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1994	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1995	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
1996	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1997	)
1998	#endif /* else: CSAM not active */
1999	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2000	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2001	GCPtrCurPage, pPteSrc->n.u1Present,
2002	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2003	pPteSrc->n.u1User & PdeSrc.n.u1User,
2004	(uint64_t)pPteSrc->u,
2005	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2006	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2007	}
2008	}
2009	}
2010	else
2011	# endif /* PGM_SYNC_N_PAGES */
2012	{
2013	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2014	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2015	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2016	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2017	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2018	GCPtrPage, PteSrc.n.u1Present,
2019	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2020	PteSrc.n.u1User & PdeSrc.n.u1User,
2021	(uint64_t)PteSrc.u,
2022	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2023	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2024	}
2025	}
2026	else /* MMIO or invalid page: emulated in #PF handler. */
2027	{
2028	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2029	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2030	}
2031	}
2032	else
2033	{
2034	/*
2035	* 4/2MB page - lazy syncing shadow 4K pages.
2036	* (There are many causes of getting here, it's no longer only CSAM.)
2037	*/
2038	/* Calculate the GC physical address of this 4KB shadow page. */
2039	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
2040	/* Find ram range. */
2041	PPGMPAGE pPage;
2042	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2043	if (RT_SUCCESS(rc))
2044	{
2045	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2046
2047	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2048	/* Try to make the page writable if necessary. */
2049	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2050	&& ( PGM_PAGE_IS_ZERO(pPage)
2051	\|\| ( PdeSrc.n.u1Write
2052	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2053	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2054	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2055	# endif
2056	# ifdef VBOX_WITH_PAGE_SHARING
2057	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2058	# endif
2059	)
2060	)
2061	)
2062	{
2063	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2064	AssertRC(rc);
2065	}
2066	# endif
2067
2068	/*
2069	* Make shadow PTE entry.
2070	*/
2071	SHWPTE PteDst;
2072	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2073	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2074	else
2075	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2076
2077	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2078	if ( SHW_PTE_IS_P(PteDst)
2079	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2080	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2081
2082	/* Make sure only allocated pages are mapped writable. */
2083	if ( SHW_PTE_IS_P_RW(PteDst)
2084	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2085	{
2086	/* Still applies to shared pages. */
2087	Assert(!PGM_PAGE_IS_ZERO(pPage));
2088	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2089	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2090	}
2091
2092	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2093
2094	/*
2095	* If the page is not flagged as dirty and is writable, then make it read-only
2096	* at PD level, so we can set the dirty bit when the page is modified.
2097	*
2098	* ASSUMES that page access handlers are implemented on page table entry level.
2099	* Thus we will first catch the dirty access and set PDE.D and restart. If
2100	* there is an access handler, we'll trap again and let it work on the problem.
2101	*/
2102	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2103	* As for invlpg, it simply frees the whole shadow PT.
2104	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2105	if ( !PdeSrc.b.u1Dirty
2106	&& PdeSrc.b.u1Write)
2107	{
2108	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2109	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2110	PdeDst.n.u1Write = 0;
2111	}
2112	else
2113	{
2114	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2115	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2116	}
2117	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2118	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2119	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2120	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2121	}
2122	else
2123	{
2124	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2125	/** @todo must wipe the shadow page table entry in this
2126	* case. */
2127	}
2128	}
2129	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2130	return VINF_SUCCESS;
2131	}
2132
2133	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2134	}
2135	else if (fPdeValid)
2136	{
2137	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2138	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2139	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2140	}
2141	else
2142	{
2143	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2144	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2145	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2146	}
2147
2148	/*
2149	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2150	* Yea, I'm lazy.
2151	*/
2152	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2153	ASMAtomicWriteSize(pPdeDst, 0);
2154
2155	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2156	PGM_INVL_VCPU_TLBS(pVCpu);
2157	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2158
2159
2160	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2161	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2162	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2163	&& !defined(IN_RC)
2164	NOREF(PdeSrc);
2165
2166	# ifdef PGM_SYNC_N_PAGES
2167	/*
2168	* Get the shadow PDE, find the shadow page table in the pool.
2169	*/
2170	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2171	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2172
2173	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2174	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2175
2176	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2177	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2178	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2179	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2180	X86PDEPAE PdeDst;
2181	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2182
2183	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2184	AssertRCSuccessReturn(rc, rc);
2185	Assert(pPDDst && pPdptDst);
2186	PdeDst = pPDDst->a[iPDDst];
2187	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2188	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2189	PEPTPD pPDDst;
2190	EPTPDE PdeDst;
2191
2192	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2193	if (rc != VINF_SUCCESS)
2194	{
2195	AssertRC(rc);
2196	return rc;
2197	}
2198	Assert(pPDDst);
2199	PdeDst = pPDDst->a[iPDDst];
2200	# endif
2201	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2202	if (!PdeDst.n.u1Present)
2203	{
2204	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2205	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2206	return VINF_SUCCESS; /* force the instruction to be executed again. */
2207	}
2208
2209	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2210	if (PdeDst.n.u1Size)
2211	{
2212	Assert(pVM->pgm.s.fNestedPaging);
2213	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2214	return VINF_SUCCESS;
2215	}
2216
2217	/* Mask away the page offset. */
2218	GCPtrPage &= ~((RTGCPTR)0xfff);
2219
2220	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2221	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2222
2223	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2224	if ( cPages > 1
2225	&& !(uErr & X86_TRAP_PF_P)
2226	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2227	{
2228	/*
2229	* This code path is currently only taken when the caller is PGMTrap0eHandler
2230	* for non-present pages!
2231	*
2232	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2233	* deal with locality.
2234	*/
2235	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2236	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2237	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2238	iPTDst = 0;
2239	else
2240	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2241	for (; iPTDst < iPTDstEnd; iPTDst++)
2242	{
2243	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2244	{
2245	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2246
2247	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2248	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2249	GCPtrCurPage,
2250	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2251	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2252
2253	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2254	break;
2255	}
2256	else
2257	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2258	}
2259	}
2260	else
2261	# endif /* PGM_SYNC_N_PAGES */
2262	{
2263	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2264	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
2265
2266	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2267
2268	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2269	GCPtrPage,
2270	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2271	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2272	}
2273	return VINF_SUCCESS;
2274
2275	#else
2276	NOREF(PdeSrc);
2277	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2278	return VERR_PGM_NOT_USED_IN_MODE;
2279	#endif
2280	}
2281
2282
2283	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2284
2285	/**
2286	* CheckPageFault helper for returning a page fault indicating a non-present
2287	* (NP) entry in the page translation structures.
2288	*
2289	* @returns VINF_EM_RAW_GUEST_TRAP.
2290	* @param pVCpu The virtual CPU to operate on.
2291	* @param uErr The error code of the shadow fault. Corrections to
2292	* TRPM's copy will be made if necessary.
2293	* @param GCPtrPage For logging.
2294	* @param uPageFaultLevel For logging.
2295	*/
2296	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2297	{
2298	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2299	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2300	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2301	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2302	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2303
2304	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2305	return VINF_EM_RAW_GUEST_TRAP;
2306	}
2307
2308
2309	/**
2310	* CheckPageFault helper for returning a page fault indicating a reserved bit
2311	* (RSVD) error in the page translation structures.
2312	*
2313	* @returns VINF_EM_RAW_GUEST_TRAP.
2314	* @param pVCpu The virtual CPU to operate on.
2315	* @param uErr The error code of the shadow fault. Corrections to
2316	* TRPM's copy will be made if necessary.
2317	* @param GCPtrPage For logging.
2318	* @param uPageFaultLevel For logging.
2319	*/
2320	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2321	{
2322	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2323	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2324	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2325
2326	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2327	return VINF_EM_RAW_GUEST_TRAP;
2328	}
2329
2330
2331	/**
2332	* CheckPageFault helper for returning a page protection fault (P).
2333	*
2334	* @returns VINF_EM_RAW_GUEST_TRAP.
2335	* @param pVCpu The virtual CPU to operate on.
2336	* @param uErr The error code of the shadow fault. Corrections to
2337	* TRPM's copy will be made if necessary.
2338	* @param GCPtrPage For logging.
2339	* @param uPageFaultLevel For logging.
2340	*/
2341	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2342	{
2343	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2344	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2345	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2346	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2347
2348	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2349	return VINF_EM_RAW_GUEST_TRAP;
2350	}
2351
2352
2353	/**
2354	* Handle dirty bit tracking faults.
2355	*
2356	* @returns VBox status code.
2357	* @param pVCpu The VMCPU handle.
2358	* @param uErr Page fault error code.
2359	* @param pPdeSrc Guest page directory entry.
2360	* @param pPdeDst Shadow page directory entry.
2361	* @param GCPtrPage Guest context page address.
2362	*/
2363	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2364	RTGCPTR GCPtrPage)
2365	{
2366	PVM pVM = pVCpu->CTX_SUFF(pVM);
2367	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2368	NOREF(uErr);
2369
2370	PGM_LOCK_ASSERT_OWNER(pVM);
2371
2372	/*
2373	* Handle big page.
2374	*/
2375	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2376	{
2377	if ( pPdeDst->n.u1Present
2378	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2379	{
2380	SHWPDE PdeDst = *pPdeDst;
2381
2382	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2383	Assert(pPdeSrc->b.u1Write);
2384
2385	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2386	* fault again and take this path to only invalidate the entry (see below).
2387	*/
2388	PdeDst.n.u1Write = 1;
2389	PdeDst.n.u1Accessed = 1;
2390	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2391	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2392	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2393	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2394	}
2395
2396	# ifdef IN_RING0
2397	/* Check for stale TLB entry; only applies to the SMP guest case. */
2398	if ( pVM->cCpus > 1
2399	&& pPdeDst->n.u1Write
2400	&& pPdeDst->n.u1Accessed)
2401	{
2402	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2403	if (pShwPage)
2404	{
2405	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2406	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2407	if (SHW_PTE_IS_P_RW(*pPteDst))
2408	{
2409	/* Stale TLB entry. */
2410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2411	PGM_INVL_PG(pVCpu, GCPtrPage);
2412	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2413	}
2414	}
2415	}
2416	# endif /* IN_RING0 */
2417	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2418	}
2419
2420	/*
2421	* Map the guest page table.
2422	*/
2423	PGSTPT pPTSrc;
2424	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2425	if (RT_FAILURE(rc))
2426	{
2427	AssertRC(rc);
2428	return rc;
2429	}
2430
2431	if (pPdeDst->n.u1Present)
2432	{
2433	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2434	const GSTPTE PteSrc = *pPteSrc;
2435
2436	#ifndef IN_RING0
2437	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2438	* Our individual shadow handlers will provide more information and force a fatal exit.
2439	*/
2440	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2441	{
2442	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2443	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2444	}
2445	#endif
2446	/*
2447	* Map shadow page table.
2448	*/
2449	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2450	if (pShwPage)
2451	{
2452	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2453	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2454	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2455	{
2456	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2457	{
2458	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2459	SHWPTE PteDst = *pPteDst;
2460
2461	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2462	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2463
2464	Assert(PteSrc.n.u1Write);
2465
2466	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2467	* entry will not harm; write access will simply fault again and
2468	* take this path to only invalidate the entry.
2469	*/
2470	if (RT_LIKELY(pPage))
2471	{
2472	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2473	{
2474	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2475	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2476	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2477	SHW_PTE_SET_RO(PteDst);
2478	}
2479	else
2480	{
2481	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2482	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2483	{
2484	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2485	AssertRC(rc);
2486	}
2487	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2488	SHW_PTE_SET_RW(PteDst);
2489	else
2490	{
2491	/* Still applies to shared pages. */
2492	Assert(!PGM_PAGE_IS_ZERO(pPage));
2493	SHW_PTE_SET_RO(PteDst);
2494	}
2495	}
2496	}
2497	else
2498	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2499
2500	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2501	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2502	PGM_INVL_PG(pVCpu, GCPtrPage);
2503	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2504	}
2505
2506	# ifdef IN_RING0
2507	/* Check for stale TLB entry; only applies to the SMP guest case. */
2508	if ( pVM->cCpus > 1
2509	&& SHW_PTE_IS_RW(*pPteDst)
2510	&& SHW_PTE_IS_A(*pPteDst))
2511	{
2512	/* Stale TLB entry. */
2513	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2514	PGM_INVL_PG(pVCpu, GCPtrPage);
2515	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2516	}
2517	# endif
2518	}
2519	}
2520	else
2521	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2522	}
2523
2524	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2525	}
2526
2527	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2528
2529
2530	/**
2531	* Sync a shadow page table.
2532	*
2533	* The shadow page table is not present in the shadow PDE.
2534	*
2535	* Handles mapping conflicts.
2536	*
2537	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2538	* conflict), and Trap0eHandler.
2539	*
2540	* A precondition for this method is that the shadow PDE is not present. The
2541	* caller must take the PGM lock before checking this and continue to hold it
2542	* when calling this method.
2543	*
2544	* @returns VBox status code.
2545	* @param pVCpu The VMCPU handle.
2546	* @param iPD Page directory index.
2547	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2548	* Assume this is a temporary mapping.
2549	* @param GCPtrPage GC Pointer of the page that caused the fault
2550	*/
2551	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2552	{
2553	PVM pVM = pVCpu->CTX_SUFF(pVM);
2554	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2555
2556	#if 0 /* rarely useful; leave for debugging. */
2557	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2558	#endif
2559	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2560
2561	PGM_LOCK_ASSERT_OWNER(pVM);
2562
2563	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2564	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2565	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2566	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2567	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2568
2569	int rc = VINF_SUCCESS;
2570
2571	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2572
2573	/*
2574	* Some input validation first.
2575	*/
2576	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2577
2578	/*
2579	* Get the relevant shadow PDE entry.
2580	*/
2581	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2582	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2583	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2584
2585	/* Fetch the pgm pool shadow descriptor. */
2586	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2587	Assert(pShwPde);
2588
2589	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2590	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2591	PPGMPOOLPAGE pShwPde = NULL;
2592	PX86PDPAE pPDDst;
2593	PSHWPDE pPdeDst;
2594
2595	/* Fetch the pgm pool shadow descriptor. */
2596	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2597	AssertRCSuccessReturn(rc, rc);
2598	Assert(pShwPde);
2599
2600	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2601	pPdeDst = &pPDDst->a[iPDDst];
2602
2603	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2604	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2605	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2606	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2607	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2608	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2609	AssertRCSuccessReturn(rc, rc);
2610	Assert(pPDDst);
2611	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2612	# endif
2613	SHWPDE PdeDst = *pPdeDst;
2614
2615	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2616	/* Fetch the pgm pool shadow descriptor. */
2617	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2618	Assert(pShwPde);
2619	# endif
2620
2621	# ifndef PGM_WITHOUT_MAPPINGS
2622	/*
2623	* Check for conflicts.
2624	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2625	* R3: Simply resolve the conflict.
2626	*/
2627	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2628	{
2629	Assert(pgmMapAreMappingsEnabled(pVM));
2630	# ifndef IN_RING3
2631	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2632	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2633	return VERR_ADDRESS_CONFLICT;
2634
2635	# else /* IN_RING3 */
2636	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2637	Assert(pMapping);
2638	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2639	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2640	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2641	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2642	# else
2643	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2644	# endif
2645	if (RT_FAILURE(rc))
2646	{
2647	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2648	return rc;
2649	}
2650	PdeDst = *pPdeDst;
2651	# endif /* IN_RING3 */
2652	}
2653	# endif /* !PGM_WITHOUT_MAPPINGS */
2654	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2655
2656	/*
2657	* Sync the page directory entry.
2658	*/
2659	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2660	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2661	if ( PdeSrc.n.u1Present
2662	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2663	{
2664	/*
2665	* Allocate & map the page table.
2666	*/
2667	PSHWPT pPTDst;
2668	PPGMPOOLPAGE pShwPage;
2669	RTGCPHYS GCPhys;
2670	if (fPageTable)
2671	{
2672	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2673	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2674	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2675	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2676	# endif
2677	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
2678	}
2679	else
2680	{
2681	PGMPOOLACCESS enmAccess;
2682	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2683	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2684	# else
2685	const bool fNoExecute = false;
2686	# endif
2687
2688	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2689	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2690	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2691	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2692	# endif
2693	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2694	if (PdeSrc.n.u1User)
2695	{
2696	if (PdeSrc.n.u1Write)
2697	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2698	else
2699	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2700	}
2701	else
2702	{
2703	if (PdeSrc.n.u1Write)
2704	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2705	else
2706	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2707	}
2708	rc = pgmPoolAllocEx(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, pShwPde->idx, iPDDst, false /fLockPage/,
2709	&pShwPage);
2710	}
2711	if (rc == VINF_SUCCESS)
2712	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2713	else if (rc == VINF_PGM_CACHED_PAGE)
2714	{
2715	/*
2716	* The PT was cached, just hook it up.
2717	*/
2718	if (fPageTable)
2719	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2720	else
2721	{
2722	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2723	/* (see explanation and assumptions further down.) */
2724	if ( !PdeSrc.b.u1Dirty
2725	&& PdeSrc.b.u1Write)
2726	{
2727	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2728	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2729	PdeDst.b.u1Write = 0;
2730	}
2731	}
2732	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2733	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2734	return VINF_SUCCESS;
2735	}
2736	else if (rc == VERR_PGM_POOL_FLUSHED)
2737	{
2738	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2739	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2740	return VINF_PGM_SYNC_CR3;
2741	}
2742	else
2743	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2744	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2745	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2746	* irrelevant at this point. */
2747	PdeDst.u &= X86_PDE_AVL_MASK;
2748	PdeDst.u \|= pShwPage->Core.Key;
2749
2750	/*
2751	* Page directory has been accessed (this is a fault situation, remember).
2752	*/
2753	/** @todo
2754	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2755	* fault situation. What's more, the Trap0eHandler has already set the
2756	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2757	* might need setting the accessed flag.
2758	*
2759	* The best idea is to leave this change to the caller and add an
2760	* assertion that it's set already. */
2761	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2762	if (fPageTable)
2763	{
2764	/*
2765	* Page table - 4KB.
2766	*
2767	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2768	*/
2769	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2770	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2771	PGSTPT pPTSrc;
2772	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2773	if (RT_SUCCESS(rc))
2774	{
2775	/*
2776	* Start by syncing the page directory entry so CSAM's TLB trick works.
2777	*/
2778	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2779	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2780	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2781	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2782
2783	/*
2784	* Directory/page user or supervisor privilege: (same goes for read/write)
2785	*
2786	* Directory Page Combined
2787	* U/S U/S U/S
2788	* 0 0 0
2789	* 0 1 0
2790	* 1 0 0
2791	* 1 1 1
2792	*
2793	* Simple AND operation. Table listed for completeness.
2794	*
2795	*/
2796	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2797	# ifdef PGM_SYNC_N_PAGES
2798	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2799	unsigned iPTDst = iPTBase;
2800	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2801	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2802	iPTDst = 0;
2803	else
2804	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2805	# else /* !PGM_SYNC_N_PAGES */
2806	unsigned iPTDst = 0;
2807	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2808	# endif /* !PGM_SYNC_N_PAGES */
2809	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2810	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2811	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2812	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2813	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2814	# else
2815	const unsigned offPTSrc = 0;
2816	# endif
2817	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2818	{
2819	const unsigned iPTSrc = iPTDst + offPTSrc;
2820	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2821
2822	if (PteSrc.n.u1Present)
2823	{
2824	# ifndef IN_RING0
2825	/*
2826	* Assuming kernel code will be marked as supervisor - and not as user level
2827	* and executed using a conforming code selector - And marked as readonly.
2828	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2829	*/
2830	PPGMPAGE pPage;
2831	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2832	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2833	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2834	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2835	)
2836	# endif
2837	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2838	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2839	GCPtrCur,
2840	PteSrc.n.u1Present,
2841	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2842	PteSrc.n.u1User & PdeSrc.n.u1User,
2843	(uint64_t)PteSrc.u,
2844	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2845	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2846	}
2847	/* else: the page table was cleared by the pool */
2848	} /* for PTEs */
2849	}
2850	}
2851	else
2852	{
2853	/*
2854	* Big page - 2/4MB.
2855	*
2856	* We'll walk the ram range list in parallel and optimize lookups.
2857	* We will only sync one shadow page table at a time.
2858	*/
2859	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2860
2861	/**
2862	* @todo It might be more efficient to sync only a part of the 4MB
2863	* page (similar to what we do for 4KB PDs).
2864	*/
2865
2866	/*
2867	* Start by syncing the page directory entry.
2868	*/
2869	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2870	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2871
2872	/*
2873	* If the page is not flagged as dirty and is writable, then make it read-only
2874	* at PD level, so we can set the dirty bit when the page is modified.
2875	*
2876	* ASSUMES that page access handlers are implemented on page table entry level.
2877	* Thus we will first catch the dirty access and set PDE.D and restart. If
2878	* there is an access handler, we'll trap again and let it work on the problem.
2879	*/
2880	/** @todo move the above stuff to a section in the PGM documentation. */
2881	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2882	if ( !PdeSrc.b.u1Dirty
2883	&& PdeSrc.b.u1Write)
2884	{
2885	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2886	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2887	PdeDst.b.u1Write = 0;
2888	}
2889	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2890	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2891
2892	/*
2893	* Fill the shadow page table.
2894	*/
2895	/* Get address and flags from the source PDE. */
2896	SHWPTE PteDstBase;
2897	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2898
2899	/* Loop thru the entries in the shadow PT. */
2900	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2901	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2902	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2903	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2904	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2905	unsigned iPTDst = 0;
2906	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2907	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2908	{
2909	if (pRam && GCPhys >= pRam->GCPhys)
2910	{
2911	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2912	do
2913	{
2914	/* Make shadow PTE. */
2915	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2916	SHWPTE PteDst;
2917
2918	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2919	/* Try to make the page writable if necessary. */
2920	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2921	&& ( PGM_PAGE_IS_ZERO(pPage)
2922	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2923	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2924	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2925	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2926	# endif
2927	# ifdef VBOX_WITH_PAGE_SHARING
2928	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2929	# endif
2930	&& !PGM_PAGE_IS_BALLOONED(pPage))
2931	)
2932	)
2933	{
2934	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2935	AssertRCReturn(rc, rc);
2936	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2937	break;
2938	}
2939	# endif
2940
2941	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2942	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2943	else if (PGM_PAGE_IS_BALLOONED(pPage))
2944	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2945	# ifndef IN_RING0
2946	/*
2947	* Assuming kernel code will be marked as supervisor and not as user level and executed
2948	* using a conforming code selector. Don't check for readonly, as that implies the whole
2949	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2950	*/
2951	else if ( !PdeSrc.n.u1User
2952	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2953	SHW_PTE_SET(PteDst, 0);
2954	# endif
2955	else
2956	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2957
2958	/* Only map writable pages writable. */
2959	if ( SHW_PTE_IS_P_RW(PteDst)
2960	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2961	{
2962	/* Still applies to shared pages. */
2963	Assert(!PGM_PAGE_IS_ZERO(pPage));
2964	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2965	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2966	}
2967
2968	if (SHW_PTE_IS_P(PteDst))
2969	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2970
2971	/* commit it (not atomic, new table) */
2972	pPTDst->a[iPTDst] = PteDst;
2973	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2974	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2975	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2976
2977	/* advance */
2978	GCPhys += PAGE_SIZE;
2979	iHCPage++;
2980	iPTDst++;
2981	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2982	&& GCPhys <= pRam->GCPhysLast);
2983
2984	/* Advance ram range list. */
2985	while (pRam && GCPhys > pRam->GCPhysLast)
2986	pRam = pRam->CTX_SUFF(pNext);
2987	}
2988	else if (pRam)
2989	{
2990	Log(("Invalid pages at %RGp\n", GCPhys));
2991	do
2992	{
2993	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
2994	GCPhys += PAGE_SIZE;
2995	iPTDst++;
2996	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2997	&& GCPhys < pRam->GCPhys);
2998	}
2999	else
3000	{
3001	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3002	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3003	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3004	}
3005	} /* while more PTEs */
3006	} /* 4KB / 4MB */
3007	}
3008	else
3009	AssertRelease(!PdeDst.n.u1Present);
3010
3011	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3012	if (RT_FAILURE(rc))
3013	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3014	return rc;
3015
3016	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3017	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3018	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3019	&& !defined(IN_RC)
3020	NOREF(iPDSrc); NOREF(pPDSrc);
3021
3022	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3023
3024	/*
3025	* Validate input a little bit.
3026	*/
3027	int rc = VINF_SUCCESS;
3028	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3029	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3030	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3031
3032	/* Fetch the pgm pool shadow descriptor. */
3033	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3034	Assert(pShwPde);
3035
3036	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3037	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3038	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3039	PX86PDPAE pPDDst;
3040	PSHWPDE pPdeDst;
3041
3042	/* Fetch the pgm pool shadow descriptor. */
3043	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3044	AssertRCSuccessReturn(rc, rc);
3045	Assert(pShwPde);
3046
3047	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3048	pPdeDst = &pPDDst->a[iPDDst];
3049
3050	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3051	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3052	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3053	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3054	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3055	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3056	AssertRCSuccessReturn(rc, rc);
3057	Assert(pPDDst);
3058	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3059
3060	/* Fetch the pgm pool shadow descriptor. */
3061	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3062	Assert(pShwPde);
3063
3064	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3065	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3066	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3067	PEPTPD pPDDst;
3068	PEPTPDPT pPdptDst;
3069
3070	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3071	if (rc != VINF_SUCCESS)
3072	{
3073	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3074	AssertRC(rc);
3075	return rc;
3076	}
3077	Assert(pPDDst);
3078	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3079
3080	/* Fetch the pgm pool shadow descriptor. */
3081	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3082	Assert(pShwPde);
3083	# endif
3084	SHWPDE PdeDst = *pPdeDst;
3085
3086	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3087	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3088
3089	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3090	if (BTH_IS_NP_ACTIVE(pVM))
3091	{
3092	/* Check if we allocated a big page before for this 2 MB range. */
3093	PPGMPAGE pPage;
3094	rc = pgmPhysGetPageEx(pVM, GCPtrPage & X86_PDE2M_PAE_PG_MASK, &pPage);
3095	if (RT_SUCCESS(rc))
3096	{
3097	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3098	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3099	{
3100	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3101	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3102	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3103	}
3104	else if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED)
3105	{
3106	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3107	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3108	if (RT_SUCCESS(rc))
3109	{
3110	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3111	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3112	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3113	}
3114	}
3115	else if (PGMIsUsingLargePages(pVM))
3116	{
3117	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3118	if (RT_SUCCESS(rc))
3119	{
3120	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3121	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3122	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3123	}
3124	else
3125	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3126	}
3127
3128	if (HCPhys != NIL_RTHCPHYS)
3129	{
3130	PdeDst.u &= X86_PDE_AVL_MASK;
3131	PdeDst.u \|= HCPhys;
3132	PdeDst.n.u1Present = 1;
3133	PdeDst.n.u1Write = 1;
3134	PdeDst.b.u1Size = 1;
3135	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3136	PdeDst.n.u1Execute = 1;
3137	PdeDst.b.u1IgnorePAT = 1;
3138	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3139	# else
3140	PdeDst.n.u1User = 1;
3141	# endif
3142	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3143
3144	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3145	/* Add a reference to the first page only. */
3146	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3147
3148	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3149	return VINF_SUCCESS;
3150	}
3151	}
3152	}
3153	# endif /* HC_ARCH_BITS == 64 */
3154
3155	/*
3156	* Allocate & map the page table.
3157	*/
3158	PSHWPT pPTDst;
3159	PPGMPOOLPAGE pShwPage;
3160	RTGCPHYS GCPhys;
3161
3162	/* Virtual address = physical address */
3163	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK;
3164	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, pShwPde->idx, iPDDst, &pShwPage);
3165
3166	if ( rc == VINF_SUCCESS
3167	\|\| rc == VINF_PGM_CACHED_PAGE)
3168	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3169	else
3170	{
3171	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3172	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3173	}
3174
3175	if (rc == VINF_SUCCESS)
3176	{
3177	/* New page table; fully set it up. */
3178	Assert(pPTDst);
3179
3180	/* Mask away the page offset. */
3181	GCPtrPage &= ~((RTGCPTR)0xfff);
3182
3183	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3184	{
3185	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT);
3186
3187	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3188	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3189	GCPtrCurPage,
3190	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3191	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3192
3193	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3194	break;
3195	}
3196	}
3197	else
3198	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3199
3200	/* Save the new PDE. */
3201	PdeDst.u &= X86_PDE_AVL_MASK;
3202	PdeDst.u \|= pShwPage->Core.Key;
3203	PdeDst.n.u1Present = 1;
3204	PdeDst.n.u1Write = 1;
3205	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3206	PdeDst.n.u1Execute = 1;
3207	# else
3208	PdeDst.n.u1User = 1;
3209	PdeDst.n.u1Accessed = 1;
3210	# endif
3211	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3212
3213	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3214	if (RT_FAILURE(rc))
3215	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3216	return rc;
3217
3218	#else
3219	NOREF(iPDSrc); NOREF(pPDSrc);
3220	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3221	return VERR_PGM_NOT_USED_IN_MODE;
3222	#endif
3223	}
3224
3225
3226
3227	/**
3228	* Prefetch a page/set of pages.
3229	*
3230	* Typically used to sync commonly used pages before entering raw mode
3231	* after a CR3 reload.
3232	*
3233	* @returns VBox status code.
3234	* @param pVCpu The VMCPU handle.
3235	* @param GCPtrPage Page to invalidate.
3236	*/
3237	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3238	{
3239	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3240	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3241	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3242	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3243	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3244	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3245	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3246
3247	/*
3248	* Check that all Guest levels thru the PDE are present, getting the
3249	* PD and PDE in the processes.
3250	*/
3251	int rc = VINF_SUCCESS;
3252	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3253	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3254	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3255	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3256	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3257	unsigned iPDSrc;
3258	X86PDPE PdpeSrc;
3259	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3260	if (!pPDSrc)
3261	return VINF_SUCCESS; /* not present */
3262	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3263	unsigned iPDSrc;
3264	PX86PML4E pPml4eSrc;
3265	X86PDPE PdpeSrc;
3266	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3267	if (!pPDSrc)
3268	return VINF_SUCCESS; /* not present */
3269	# endif
3270	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3271	# else
3272	PGSTPD pPDSrc = NULL;
3273	const unsigned iPDSrc = 0;
3274	GSTPDE PdeSrc;
3275
3276	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3277	PdeSrc.n.u1Present = 1;
3278	PdeSrc.n.u1Write = 1;
3279	PdeSrc.n.u1Accessed = 1;
3280	PdeSrc.n.u1User = 1;
3281	# endif
3282
3283	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3284	{
3285	PVM pVM = pVCpu->CTX_SUFF(pVM);
3286	pgmLock(pVM);
3287
3288	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3289	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3290	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3291	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3292	PX86PDPAE pPDDst;
3293	X86PDEPAE PdeDst;
3294	# if PGM_GST_TYPE != PGM_TYPE_PAE
3295	X86PDPE PdpeSrc;
3296
3297	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3298	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3299	# endif
3300	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3301	if (rc != VINF_SUCCESS)
3302	{
3303	pgmUnlock(pVM);
3304	AssertRC(rc);
3305	return rc;
3306	}
3307	Assert(pPDDst);
3308	PdeDst = pPDDst->a[iPDDst];
3309
3310	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3311	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3312	PX86PDPAE pPDDst;
3313	X86PDEPAE PdeDst;
3314
3315	# if PGM_GST_TYPE == PGM_TYPE_PROT
3316	/* AMD-V nested paging */
3317	X86PML4E Pml4eSrc;
3318	X86PDPE PdpeSrc;
3319	PX86PML4E pPml4eSrc = &Pml4eSrc;
3320
3321	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3322	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3323	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3324	# endif
3325
3326	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3327	if (rc != VINF_SUCCESS)
3328	{
3329	pgmUnlock(pVM);
3330	AssertRC(rc);
3331	return rc;
3332	}
3333	Assert(pPDDst);
3334	PdeDst = pPDDst->a[iPDDst];
3335	# endif
3336	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3337	{
3338	if (!PdeDst.n.u1Present)
3339	{
3340	/** @todo r=bird: This guy will set the A bit on the PDE,
3341	* probably harmless. */
3342	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3343	}
3344	else
3345	{
3346	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3347	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3348	* makes no sense to prefetch more than one page.
3349	*/
3350	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3351	if (RT_SUCCESS(rc))
3352	rc = VINF_SUCCESS;
3353	}
3354	}
3355	pgmUnlock(pVM);
3356	}
3357	return rc;
3358
3359	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3360	NOREF(pVCpu); NOREF(GCPtrPage);
3361	return VINF_SUCCESS; /* ignore */
3362	#else
3363	AssertCompile(0);
3364	#endif
3365	}
3366
3367
3368
3369
3370	/**
3371	* Syncs a page during a PGMVerifyAccess() call.
3372	*
3373	* @returns VBox status code (informational included).
3374	* @param pVCpu The VMCPU handle.
3375	* @param GCPtrPage The address of the page to sync.
3376	* @param fPage The effective guest page flags.
3377	* @param uErr The trap error code.
3378	* @remarks This will normally never be called on invalid guest page
3379	* translation entries.
3380	*/
3381	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3382	{
3383	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3384
3385	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3386
3387	Assert(!pVM->pgm.s.fNestedPaging);
3388	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3389	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3390	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3391	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3392	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3393	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3394	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3395
3396	# ifndef IN_RING0
3397	if (!(fPage & X86_PTE_US))
3398	{
3399	/*
3400	* Mark this page as safe.
3401	*/
3402	/** @todo not correct for pages that contain both code and data!! */
3403	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3404	CSAMMarkPage(pVM, GCPtrPage, true);
3405	}
3406	# endif
3407
3408	/*
3409	* Get guest PD and index.
3410	*/
3411	/** @todo Performance: We've done all this a jiffy ago in the
3412	* PGMGstGetPage call. */
3413	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3414	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3415	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3416	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3417
3418	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3419	unsigned iPDSrc = 0;
3420	X86PDPE PdpeSrc;
3421	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3422	if (RT_UNLIKELY(!pPDSrc))
3423	{
3424	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3425	return VINF_EM_RAW_GUEST_TRAP;
3426	}
3427
3428	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3429	unsigned iPDSrc = 0; /* shut up gcc */
3430	PX86PML4E pPml4eSrc = NULL; /* ditto */
3431	X86PDPE PdpeSrc;
3432	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3433	if (RT_UNLIKELY(!pPDSrc))
3434	{
3435	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3436	return VINF_EM_RAW_GUEST_TRAP;
3437	}
3438	# endif
3439
3440	# else /* !PGM_WITH_PAGING */
3441	PGSTPD pPDSrc = NULL;
3442	const unsigned iPDSrc = 0;
3443	# endif /* !PGM_WITH_PAGING */
3444	int rc = VINF_SUCCESS;
3445
3446	pgmLock(pVM);
3447
3448	/*
3449	* First check if the shadow pd is present.
3450	*/
3451	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3452	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3453
3454	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3455	PX86PDEPAE pPdeDst;
3456	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3457	PX86PDPAE pPDDst;
3458	# if PGM_GST_TYPE != PGM_TYPE_PAE
3459	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3460	X86PDPE PdpeSrc;
3461	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3462	# endif
3463	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3464	if (rc != VINF_SUCCESS)
3465	{
3466	pgmUnlock(pVM);
3467	AssertRC(rc);
3468	return rc;
3469	}
3470	Assert(pPDDst);
3471	pPdeDst = &pPDDst->a[iPDDst];
3472
3473	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3474	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3475	PX86PDPAE pPDDst;
3476	PX86PDEPAE pPdeDst;
3477
3478	# if PGM_GST_TYPE == PGM_TYPE_PROT
3479	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3480	X86PML4E Pml4eSrc;
3481	X86PDPE PdpeSrc;
3482	PX86PML4E pPml4eSrc = &Pml4eSrc;
3483	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3484	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3485	# endif
3486
3487	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3488	if (rc != VINF_SUCCESS)
3489	{
3490	pgmUnlock(pVM);
3491	AssertRC(rc);
3492	return rc;
3493	}
3494	Assert(pPDDst);
3495	pPdeDst = &pPDDst->a[iPDDst];
3496	# endif
3497
3498	if (!pPdeDst->n.u1Present)
3499	{
3500	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3501	if (rc != VINF_SUCCESS)
3502	{
3503	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3504	pgmUnlock(pVM);
3505	AssertRC(rc);
3506	return rc;
3507	}
3508	}
3509
3510	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3511	/* Check for dirty bit fault */
3512	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3513	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3514	Log(("PGMVerifyAccess: success (dirty)\n"));
3515	else
3516	# endif
3517	{
3518	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3519	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3520	# else
3521	GSTPDE PdeSrc;
3522	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3523	PdeSrc.n.u1Present = 1;
3524	PdeSrc.n.u1Write = 1;
3525	PdeSrc.n.u1Accessed = 1;
3526	PdeSrc.n.u1User = 1;
3527	# endif
3528
3529	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3530	if (uErr & X86_TRAP_PF_US)
3531	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3532	else /* supervisor */
3533	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3534
3535	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3536	if (RT_SUCCESS(rc))
3537	{
3538	/* Page was successfully synced */
3539	Log2(("PGMVerifyAccess: success (sync)\n"));
3540	rc = VINF_SUCCESS;
3541	}
3542	else
3543	{
3544	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3545	rc = VINF_EM_RAW_GUEST_TRAP;
3546	}
3547	}
3548	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3549	pgmUnlock(pVM);
3550	return rc;
3551
3552	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3553
3554	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3555	return VERR_PGM_NOT_USED_IN_MODE;
3556	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3557	}
3558
3559
3560	/**
3561	* Syncs the paging hierarchy starting at CR3.
3562	*
3563	* @returns VBox status code, no specials.
3564	* @param pVCpu The VMCPU handle.
3565	* @param cr0 Guest context CR0 register
3566	* @param cr3 Guest context CR3 register
3567	* @param cr4 Guest context CR4 register
3568	* @param fGlobal Including global page directories or not
3569	*/
3570	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3571	{
3572	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3573	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3574
3575	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3576
3577	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3578
3579	pgmLock(pVM);
3580
3581	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3582	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3583	if (pPool->cDirtyPages)
3584	pgmPoolResetDirtyPages(pVM);
3585	# endif
3586
3587	/*
3588	* Update page access handlers.
3589	* The virtual are always flushed, while the physical are only on demand.
3590	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3591	* have to look into that later because it will have a bad influence on the performance.
3592	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3593	* bird: Yes, but that won't work for aliases.
3594	*/
3595	/** @todo this MUST go away. See #1557. */
3596	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3597	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3598	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3599	pgmUnlock(pVM);
3600	#endif /* !NESTED && !EPT */
3601
3602	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3603	/*
3604	* Nested / EPT - almost no work.
3605	*/
3606	Assert(!pgmMapAreMappingsEnabled(pVM));
3607	return VINF_SUCCESS;
3608
3609	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3610	/*
3611	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3612	* out the shadow parts when the guest modifies its tables.
3613	*/
3614	Assert(!pgmMapAreMappingsEnabled(pVM));
3615	return VINF_SUCCESS;
3616
3617	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3618
3619	# ifndef PGM_WITHOUT_MAPPINGS
3620	/*
3621	* Check for and resolve conflicts with our guest mappings if they
3622	* are enabled and not fixed.
3623	*/
3624	if (pgmMapAreMappingsFloating(pVM))
3625	{
3626	int rc = pgmMapResolveConflicts(pVM);
3627	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3628	if (rc == VINF_PGM_SYNC_CR3)
3629	{
3630	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3631	return VINF_PGM_SYNC_CR3;
3632	}
3633	}
3634	# else
3635	Assert(!pgmMapAreMappingsEnabled(pVM));
3636	# endif
3637	return VINF_SUCCESS;
3638	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3639	}
3640
3641
3642
3643
3644	#ifdef VBOX_STRICT
3645	# ifdef IN_RC
3646	# undef AssertMsgFailed
3647	# define AssertMsgFailed Log
3648	# endif
3649
3650	/**
3651	* Checks that the shadow page table is in sync with the guest one.
3652	*
3653	* @returns The number of errors.
3654	* @param pVM The virtual machine.
3655	* @param pVCpu The VMCPU handle.
3656	* @param cr3 Guest context CR3 register
3657	* @param cr4 Guest context CR4 register
3658	* @param GCPtr Where to start. Defaults to 0.
3659	* @param cb How much to check. Defaults to everything.
3660	*/
3661	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3662	{
3663	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3664	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3665	return 0;
3666	#else
3667	unsigned cErrors = 0;
3668	PVM pVM = pVCpu->CTX_SUFF(pVM);
3669	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3670
3671	# if PGM_GST_TYPE == PGM_TYPE_PAE
3672	/** @todo currently broken; crashes below somewhere */
3673	AssertFailed();
3674	# endif
3675
3676	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3677	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3678	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3679
3680	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3681	PPGMCPU pPGM = &pVCpu->pgm.s;
3682	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3683	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3684	# ifndef IN_RING0
3685	RTHCPHYS HCPhys; /* general usage. */
3686	# endif
3687	int rc;
3688
3689	/*
3690	* Check that the Guest CR3 and all its mappings are correct.
3691	*/
3692	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3693	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3694	false);
3695	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3696	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3697	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3698	# else
3699	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3700	# endif
3701	AssertRCReturn(rc, 1);
3702	HCPhys = NIL_RTHCPHYS;
3703	rc = pgmRamGCPhys2HCPhys(pVM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3704	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3705	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3706	pgmGstGet32bitPDPtr(pVCpu);
3707	RTGCPHYS GCPhys;
3708	rc = PGMR3DbgR3Ptr2GCPhys(pVM, pPGM->pGst32BitPdR3, &GCPhys);
3709	AssertRCReturn(rc, 1);
3710	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3711	# endif
3712	# endif /* !IN_RING0 */
3713
3714	/*
3715	* Get and check the Shadow CR3.
3716	*/
3717	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3718	unsigned cPDEs = X86_PG_ENTRIES;
3719	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3720	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3721	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3722	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3723	# else
3724	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3725	# endif
3726	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3727	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3728	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3729	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3730	# endif
3731	if (cb != ~(RTGCPTR)0)
3732	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3733
3734	/** @todo call the other two PGMAssert() functions. /
3735
3736	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3737	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3738
3739	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3740	{
3741	PPGMPOOLPAGE pShwPdpt = NULL;
3742	PX86PML4E pPml4eSrc;
3743	PX86PML4E pPml4eDst;
3744	RTGCPHYS GCPhysPdptSrc;
3745
3746	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3747	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3748
3749	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3750	if (!pPml4eDst->n.u1Present)
3751	{
3752	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3753	continue;
3754	}
3755
3756	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3757	GCPhysPdptSrc = pPml4eSrc->u & X86_PML4E_PG_MASK;
3758
3759	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3760	{
3761	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3762	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3763	cErrors++;
3764	continue;
3765	}
3766
3767	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3768	{
3769	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3770	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3771	cErrors++;
3772	continue;
3773	}
3774
3775	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3776	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3777	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3778	{
3779	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3780	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3781	cErrors++;
3782	continue;
3783	}
3784	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3785	{
3786	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3787
3788	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3789	/*
3790	* Check the PDPTEs too.
3791	*/
3792	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3793
3794	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3795	{
3796	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3797	PPGMPOOLPAGE pShwPde = NULL;
3798	PX86PDPE pPdpeDst;
3799	RTGCPHYS GCPhysPdeSrc;
3800	X86PDPE PdpeSrc;
3801	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3802	# if PGM_GST_TYPE == PGM_TYPE_PAE
3803	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3804	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3805	# else
3806	PX86PML4E pPml4eSrcIgn;
3807	PX86PDPT pPdptDst;
3808	PX86PDPAE pPDDst;
3809	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3810
3811	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3812	if (rc != VINF_SUCCESS)
3813	{
3814	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3815	GCPtr += 512 * _2M;
3816	continue; /* next PDPTE */
3817	}
3818	Assert(pPDDst);
3819	# endif
3820	Assert(iPDSrc == 0);
3821
3822	pPdpeDst = &pPdptDst->a[iPdpt];
3823
3824	if (!pPdpeDst->n.u1Present)
3825	{
3826	GCPtr += 512 * _2M;
3827	continue; /* next PDPTE */
3828	}
3829
3830	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3831	GCPhysPdeSrc = PdpeSrc.u & X86_PDPE_PG_MASK;
3832
3833	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3834	{
3835	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3836	GCPtr += 512 * _2M;
3837	cErrors++;
3838	continue;
3839	}
3840
3841	if (GCPhysPdeSrc != pShwPde->GCPhys)
3842	{
3843	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3844	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3845	# else
3846	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3847	# endif
3848	GCPtr += 512 * _2M;
3849	cErrors++;
3850	continue;
3851	}
3852
3853	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3854	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3855	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3856	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3857	{
3858	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3859	GCPtr += 512 * _2M;
3860	cErrors++;
3861	continue;
3862	}
3863	# endif
3864
3865	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3866	{
3867	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3868	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3869	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3870	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3871	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3872	# endif
3873	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3874	/*
3875	* Iterate the shadow page directory.
3876	*/
3877	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3878	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3879
3880	for (;
3881	iPDDst < cPDEs;
3882	iPDDst++, GCPtr += cIncrement)
3883	{
3884	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3885	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3886	# else
3887	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3888	# endif
3889	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3890	{
3891	Assert(pgmMapAreMappingsEnabled(pVM));
3892	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3893	{
3894	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3895	cErrors++;
3896	continue;
3897	}
3898	}
3899	else if ( (PdeDst.u & X86_PDE_P)
3900	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3901	)
3902	{
3903	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3904	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3905	if (!pPoolPage)
3906	{
3907	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3908	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3909	cErrors++;
3910	continue;
3911	}
3912	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3913
3914	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3915	{
3916	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3917	GCPtr, (uint64_t)PdeDst.u));
3918	cErrors++;
3919	}
3920
3921	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3922	{
3923	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3924	GCPtr, (uint64_t)PdeDst.u));
3925	cErrors++;
3926	}
3927
3928	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3929	if (!PdeSrc.n.u1Present)
3930	{
3931	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3932	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3933	cErrors++;
3934	continue;
3935	}
3936
3937	if ( !PdeSrc.b.u1Size
3938	\|\| !fBigPagesSupported)
3939	{
3940	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3941	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3942	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3943	# endif
3944	}
3945	else
3946	{
3947	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3948	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3949	{
3950	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3951	GCPtr, (uint64_t)PdeSrc.u));
3952	cErrors++;
3953	continue;
3954	}
3955	# endif
3956	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3957	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3958	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3959	# endif
3960	}
3961
3962	if ( pPoolPage->enmKind
3963	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3964	{
3965	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3966	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3967	cErrors++;
3968	}
3969
3970	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3971	if (!pPhysPage)
3972	{
3973	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3974	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3975	cErrors++;
3976	continue;
3977	}
3978
3979	if (GCPhysGst != pPoolPage->GCPhys)
3980	{
3981	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
3982	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3983	cErrors++;
3984	continue;
3985	}
3986
3987	if ( !PdeSrc.b.u1Size
3988	\|\| !fBigPagesSupported)
3989	{
3990	/*
3991	* Page Table.
3992	*/
3993	const GSTPT *pPTSrc;
3994	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3995	if (RT_FAILURE(rc))
3996	{
3997	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3998	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3999	cErrors++;
4000	continue;
4001	}
4002	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4003	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4004	{
4005	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4006	// (This problem will go away when/if we shadow multiple CR3s.)
4007	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4008	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4009	cErrors++;
4010	continue;
4011	}
4012	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4013	{
4014	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4015	GCPtr, (uint64_t)PdeDst.u));
4016	cErrors++;
4017	continue;
4018	}
4019
4020	/* iterate the page table. */
4021	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4022	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4023	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4024	# else
4025	const unsigned offPTSrc = 0;
4026	# endif
4027	for (unsigned iPT = 0, off = 0;
4028	iPT < RT_ELEMENTS(pPTDst->a);
4029	iPT++, off += PAGE_SIZE)
4030	{
4031	const SHWPTE PteDst = pPTDst->a[iPT];
4032
4033	/* skip not-present and dirty tracked entries. */
4034	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4035	continue;
4036	Assert(SHW_PTE_IS_P(PteDst));
4037
4038	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4039	if (!PteSrc.n.u1Present)
4040	{
4041	# ifdef IN_RING3
4042	PGMAssertHandlerAndFlagsInSync(pVM);
4043	DBGFR3PagingDumpEx(pVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4044	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4045	0, 0, UINT64_MAX, 99, NULL);
4046	# endif
4047	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4048	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4049	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc)*sizeof(PteSrc)));
4050	cErrors++;
4051	continue;
4052	}
4053
4054	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4055	# if 1 /** @todo sync accessed bit properly... */
4056	fIgnoreFlags \|= X86_PTE_A;
4057	# endif
4058
4059	/* match the physical addresses */
4060	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4061	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4062
4063	# ifdef IN_RING3
4064	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4065	if (RT_FAILURE(rc))
4066	{
4067	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4068	{
4069	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4070	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4071	cErrors++;
4072	continue;
4073	}
4074	}
4075	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4076	{
4077	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4078	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4079	cErrors++;
4080	continue;
4081	}
4082	# endif
4083
4084	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4085	if (!pPhysPage)
4086	{
4087	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4088	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4089	{
4090	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4091	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4092	cErrors++;
4093	continue;
4094	}
4095	# endif
4096	if (SHW_PTE_IS_RW(PteDst))
4097	{
4098	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4099	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4100	cErrors++;
4101	}
4102	fIgnoreFlags \|= X86_PTE_RW;
4103	}
4104	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4105	{
4106	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4107	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4108	cErrors++;
4109	continue;
4110	}
4111
4112	/* flags */
4113	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4114	{
4115	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4116	{
4117	if (SHW_PTE_IS_RW(PteDst))
4118	{
4119	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4120	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4121	cErrors++;
4122	continue;
4123	}
4124	fIgnoreFlags \|= X86_PTE_RW;
4125	}
4126	else
4127	{
4128	if ( SHW_PTE_IS_P(PteDst)
4129	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4130	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4131	# endif
4132	)
4133	{
4134	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4135	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4136	cErrors++;
4137	continue;
4138	}
4139	fIgnoreFlags \|= X86_PTE_P;
4140	}
4141	}
4142	else
4143	{
4144	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4145	{
4146	if (SHW_PTE_IS_RW(PteDst))
4147	{
4148	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4149	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4150	cErrors++;
4151	continue;
4152	}
4153	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4154	{
4155	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4156	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4157	cErrors++;
4158	continue;
4159	}
4160	if (SHW_PTE_IS_D(PteDst))
4161	{
4162	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4163	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4164	cErrors++;
4165	}
4166	# if 0 /** @todo sync access bit properly... */
4167	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4168	{
4169	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4170	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4171	cErrors++;
4172	}
4173	fIgnoreFlags \|= X86_PTE_RW;
4174	# else
4175	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4176	# endif
4177	}
4178	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4179	{
4180	/* access bit emulation (not implemented). */
4181	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4182	{
4183	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4184	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4185	cErrors++;
4186	continue;
4187	}
4188	if (!SHW_PTE_IS_A(PteDst))
4189	{
4190	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4191	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4192	cErrors++;
4193	}
4194	fIgnoreFlags \|= X86_PTE_P;
4195	}
4196	# ifdef DEBUG_sandervl
4197	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4198	# endif
4199	}
4200
4201	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4202	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4203	)
4204	{
4205	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4206	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4207	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4208	cErrors++;
4209	continue;
4210	}
4211	} /* foreach PTE */
4212	}
4213	else
4214	{
4215	/*
4216	* Big Page.
4217	*/
4218	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4219	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4220	{
4221	if (PdeDst.n.u1Write)
4222	{
4223	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4224	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4225	cErrors++;
4226	continue;
4227	}
4228	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4229	{
4230	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4232	cErrors++;
4233	continue;
4234	}
4235	# if 0 /** @todo sync access bit properly... */
4236	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4237	{
4238	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4239	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4240	cErrors++;
4241	}
4242	fIgnoreFlags \|= X86_PTE_RW;
4243	# else
4244	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4245	# endif
4246	}
4247	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4248	{
4249	/* access bit emulation (not implemented). */
4250	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4251	{
4252	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4253	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4254	cErrors++;
4255	continue;
4256	}
4257	if (!PdeDst.n.u1Accessed)
4258	{
4259	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4260	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4261	cErrors++;
4262	}
4263	fIgnoreFlags \|= X86_PTE_P;
4264	}
4265
4266	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4267	{
4268	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4269	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4270	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4271	cErrors++;
4272	}
4273
4274	/* iterate the page table. */
4275	for (unsigned iPT = 0, off = 0;
4276	iPT < RT_ELEMENTS(pPTDst->a);
4277	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
4278	{
4279	const SHWPTE PteDst = pPTDst->a[iPT];
4280
4281	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4282	{
4283	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4284	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4285	cErrors++;
4286	}
4287
4288	/* skip not-present entries. */
4289	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4290	continue;
4291
4292	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4293
4294	/* match the physical addresses */
4295	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4296
4297	# ifdef IN_RING3
4298	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4299	if (RT_FAILURE(rc))
4300	{
4301	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4302	{
4303	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4304	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4305	cErrors++;
4306	}
4307	}
4308	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4309	{
4310	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4311	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4312	cErrors++;
4313	continue;
4314	}
4315	# endif
4316	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4317	if (!pPhysPage)
4318	{
4319	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4320	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4321	{
4322	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4323	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4324	cErrors++;
4325	continue;
4326	}
4327	# endif
4328	if (SHW_PTE_IS_RW(PteDst))
4329	{
4330	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4331	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4332	cErrors++;
4333	}
4334	fIgnoreFlags \|= X86_PTE_RW;
4335	}
4336	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4337	{
4338	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4339	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4340	cErrors++;
4341	continue;
4342	}
4343
4344	/* flags */
4345	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4346	{
4347	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4348	{
4349	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4350	{
4351	if (SHW_PTE_IS_RW(PteDst))
4352	{
4353	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4354	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4355	cErrors++;
4356	continue;
4357	}
4358	fIgnoreFlags \|= X86_PTE_RW;
4359	}
4360	}
4361	else
4362	{
4363	if ( SHW_PTE_IS_P(PteDst)
4364	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4365	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4366	# endif
4367	)
4368	{
4369	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4370	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4371	cErrors++;
4372	continue;
4373	}
4374	fIgnoreFlags \|= X86_PTE_P;
4375	}
4376	}
4377
4378	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4379	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4380	)
4381	{
4382	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4383	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4384	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4385	cErrors++;
4386	continue;
4387	}
4388	} /* for each PTE */
4389	}
4390	}
4391	/* not present */
4392
4393	} /* for each PDE */
4394
4395	} /* for each PDPTE */
4396
4397	} /* for each PML4E */
4398
4399	# ifdef DEBUG
4400	if (cErrors)
4401	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4402	# endif
4403	# endif /* GST is in {32BIT, PAE, AMD64} */
4404	return cErrors;
4405	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4406	}
4407	#endif /* VBOX_STRICT */
4408
4409
4410	/**
4411	* Sets up the CR3 for shadow paging
4412	*
4413	* @returns Strict VBox status code.
4414	* @retval VINF_SUCCESS.
4415	*
4416	* @param pVCpu The VMCPU handle.
4417	* @param GCPhysCR3 The physical address in the CR3 register.
4418	*/
4419	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4420	{
4421	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4422
4423	/* Update guest paging info. */
4424	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4425	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4426	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4427
4428	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4429
4430	/*
4431	* Map the page CR3 points at.
4432	*/
4433	RTHCPTR HCPtrGuestCR3;
4434	RTHCPHYS HCPhysGuestCR3;
4435	pgmLock(pVM);
4436	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4437	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4438	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4439	/** @todo this needs some reworking wrt. locking? */
4440	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4441	HCPtrGuestCR3 = NIL_RTHCPTR;
4442	int rc = VINF_SUCCESS;
4443	# else
4444	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4445	# endif
4446	pgmUnlock(pVM);
4447	if (RT_SUCCESS(rc))
4448	{
4449	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4450	if (RT_SUCCESS(rc))
4451	{
4452	# ifdef IN_RC
4453	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4454	# endif
4455	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4456	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4457	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4458	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4459	# endif
4460	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4461
4462	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4463	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4464	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4465	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4466	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4467	# endif
4468	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4469	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4470
4471	/*
4472	* Map the 4 PDs too.
4473	*/
4474	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4475	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4476	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4477	{
4478	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4479	if (pGuestPDPT->a[i].n.u1Present)
4480	{
4481	RTHCPTR HCPtr;
4482	RTHCPHYS HCPhys;
4483	RTGCPHYS GCPhys = pGuestPDPT->a[i].u & X86_PDPE_PG_MASK;
4484	pgmLock(pVM);
4485	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4486	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4487	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4488	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4489	HCPtr = NIL_RTHCPTR;
4490	int rc2 = VINF_SUCCESS;
4491	# else
4492	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4493	# endif
4494	pgmUnlock(pVM);
4495	if (RT_SUCCESS(rc2))
4496	{
4497	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4498	AssertRCReturn(rc, rc);
4499
4500	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4501	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4502	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4503	# endif
4504	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4505	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4506	# ifdef IN_RC
4507	PGM_INVL_PG(pVCpu, GCPtr);
4508	# endif
4509	continue;
4510	}
4511	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4512	}
4513
4514	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4515	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4516	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4517	# endif
4518	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4519	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4520	# ifdef IN_RC
4521	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4522	# endif
4523	}
4524
4525	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4526	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4527	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4528	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4529	# endif
4530	# endif
4531	}
4532	else
4533	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4534	}
4535	else
4536	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4537
4538	#else /* prot/real stub */
4539	int rc = VINF_SUCCESS;
4540	#endif
4541
4542	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4543	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4544	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4545	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4546	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4547	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4548
4549	Assert(!pVM->pgm.s.fNestedPaging);
4550
4551	/*
4552	* Update the shadow root page as well since that's not fixed.
4553	*/
4554	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4555	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4556	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4557	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4558	PPGMPOOLPAGE pNewShwPageCR3;
4559
4560	pgmLock(pVM);
4561
4562	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4563	if (pPool->cDirtyPages)
4564	pgmPoolResetDirtyPages(pVM);
4565	# endif
4566
4567	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4568	rc = pgmPoolAllocEx(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, SHW_POOL_ROOT_IDX,
4569	GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/, &pNewShwPageCR3);
4570	AssertFatalRC(rc);
4571	rc = VINF_SUCCESS;
4572
4573	# ifdef IN_RC
4574	/*
4575	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4576	* state will be inconsistent! Flush important things now while
4577	* we still can and then make sure there are no ring-3 calls.
4578	*/
4579	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4580	VMMRZCallRing3Disable(pVCpu);
4581	# endif
4582
4583	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4584	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4585	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4586	# ifdef IN_RING0
4587	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4588	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4589	# elif defined(IN_RC)
4590	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4591	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4592	# else
4593	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4594	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4595	# endif
4596
4597	# ifndef PGM_WITHOUT_MAPPINGS
4598	/*
4599	* Apply all hypervisor mappings to the new CR3.
4600	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4601	* make sure we check for conflicts in the new CR3 root.
4602	*/
4603	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4604	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4605	# endif
4606	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4607	AssertRCReturn(rc, rc);
4608	# endif
4609
4610	/* Set the current hypervisor CR3. */
4611	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4612	SELMShadowCR3Changed(pVM, pVCpu);
4613
4614	# ifdef IN_RC
4615	/* NOTE: The state is consistent again. */
4616	VMMRZCallRing3Enable(pVCpu);
4617	# endif
4618
4619	/* Clean up the old CR3 root. */
4620	if ( pOldShwPageCR3
4621	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4622	{
4623	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4624	# ifndef PGM_WITHOUT_MAPPINGS
4625	/* Remove the hypervisor mappings from the shadow page table. */
4626	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4627	# endif
4628	/* Mark the page as unlocked; allow flushing again. */
4629	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4630
4631	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4632	}
4633	pgmUnlock(pVM);
4634	# else
4635	NOREF(GCPhysCR3);
4636	# endif
4637
4638	return rc;
4639	}
4640
4641	/**
4642	* Unmaps the shadow CR3.
4643	*
4644	* @returns VBox status, no specials.
4645	* @param pVCpu The VMCPU handle.
4646	*/
4647	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4648	{
4649	LogFlow(("UnmapCR3\n"));
4650
4651	int rc = VINF_SUCCESS;
4652	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4653
4654	/*
4655	* Update guest paging info.
4656	*/
4657	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4658	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4659	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4660	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4661	# endif
4662	pVCpu->pgm.s.pGst32BitPdRC = 0;
4663
4664	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4665	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4666	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4667	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4668	# endif
4669	pVCpu->pgm.s.pGstPaePdptRC = 0;
4670	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4671	{
4672	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4673	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4674	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4675	# endif
4676	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4677	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4678	}
4679
4680	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4681	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4682	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4683	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4684	# endif
4685
4686	#else /* prot/real mode stub */
4687	/* nothing to do */
4688	#endif
4689
4690	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4691	/*
4692	* Update shadow paging info.
4693	*/
4694	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4695	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4696	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4697
4698	# if PGM_GST_TYPE != PGM_TYPE_REAL
4699	Assert(!pVM->pgm.s.fNestedPaging);
4700	# endif
4701
4702	pgmLock(pVM);
4703
4704	# ifndef PGM_WITHOUT_MAPPINGS
4705	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4706	/* Remove the hypervisor mappings from the shadow page table. */
4707	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4708	# endif
4709
4710	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4711	{
4712	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4713
4714	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4715
4716	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4717	if (pPool->cDirtyPages)
4718	pgmPoolResetDirtyPages(pVM);
4719	# endif
4720
4721	/* Mark the page as unlocked; allow flushing again. */
4722	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4723
4724	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4725	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4726	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4727	pVCpu->pgm.s.pShwPageCR3RC = 0;
4728	pVCpu->pgm.s.iShwUser = 0;
4729	pVCpu->pgm.s.iShwUserTable = 0;
4730	}
4731	pgmUnlock(pVM);
4732	# endif
4733	#endif /* !IN_RC*/
4734
4735	return rc;
4736	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 40138

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