PGMAllBth.h@ 44577

Last change on this file since 44577 was 44528, checked in by vboxsync, 12 years ago
header (C) fixes
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1	/* $Id: PGMAllBth.h 44528 2013-02-04 14:27:54Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2013 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
108	{
109	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
110	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
112	return VINF_EM_RAW_EMULATE_INSTR;
113	}
114	# endif
115
116	/*
117	* Calc the error code for the guest trap.
118	*/
119	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
120	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
121	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
122	if (pGstWalk->Core.fBadPhysAddr)
123	{
124	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
125	Assert(!pGstWalk->Core.fNotPresent);
126	}
127	else if (!pGstWalk->Core.fNotPresent)
128	uNewErr \|= X86_TRAP_PF_P;
129	TRPMSetErrorCode(pVCpu, uNewErr);
130
131	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
132	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
136
137
138	/**
139	* Deal with a guest page fault.
140	*
141	* The caller has taken the PGM lock.
142	*
143	* @returns Strict VBox status code.
144	*
145	* @param pVCpu The current CPU.
146	* @param uErr The error code.
147	* @param pRegFrame The register frame.
148	* @param pvFault The fault address.
149	* @param pPage The guest page at @a pvFault.
150	* @param pGstWalk The guest page table walk result.
151	* @param pfLockTaken PGM lock taken here or not (out). This is true
152	* when we're called.
153	*/
154	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
155	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
156	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
157	, PGSTPTWALK pGstWalk
158	# endif
159	)
160	{
161	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
162	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
163	#endif
164	PVM pVM = pVCpu->CTX_SUFF(pVM);
165	int rc;
166
167	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
168	{
169	/*
170	* Physical page access handler.
171	*/
172	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
173	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
174	# else
175	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
176	# endif
177	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
178	if (pCur)
179	{
180	# ifdef PGM_SYNC_N_PAGES
181	/*
182	* If the region is write protected and we got a page not present fault, then sync
183	* the pages. If the fault was caused by a read, then restart the instruction.
184	* In case of write access continue to the GC write handler.
185	*
186	* ASSUMES that there is only one handler per page or that they have similar write properties.
187	*/
188	if ( !(uErr & X86_TRAP_PF_P)
189	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
190	{
191	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
192	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
193	# else
194	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
195	# endif
196	if ( RT_FAILURE(rc)
197	\|\| !(uErr & X86_TRAP_PF_RW)
198	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
199	{
200	AssertRC(rc);
201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
202	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
203	return rc;
204	}
205	}
206	# endif
207	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
208	/*
209	* If the access was not thru a #PF(RSVD\|...) resync the page.
210	*/
211	if ( !(uErr & X86_TRAP_PF_RSVD)
212	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
213	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
214	&& pGstWalk->Core.fEffectiveRW
215	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
216	# endif
217	)
218	{
219	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
220	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
221	# else
222	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
223	# endif
224	if ( RT_FAILURE(rc)
225	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
226	{
227	AssertRC(rc);
228	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
229	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
230	return rc;
231	}
232	}
233	# endif
234
235	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
236	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
237	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
238	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
239	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
241	else
242	{
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
244	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
245	}
246
247	if (pCur->CTX_SUFF(pfnHandler))
248	{
249	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
250	void *pvUser = pCur->CTX_SUFF(pvUser);
251	# ifdef IN_RING0
252	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
253	# else
254	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
255	# endif
256
257	STAM_PROFILE_START(&pCur->Stat, h);
258	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
259	{
260	pgmUnlock(pVM);
261	*pfLockTaken = false;
262	}
263
264	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
265
266	# ifdef VBOX_WITH_STATISTICS
267	pgmLock(pVM);
268	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
269	if (pCur)
270	STAM_PROFILE_STOP(&pCur->Stat, h);
271	pgmUnlock(pVM);
272	# endif
273	}
274	else
275	rc = VINF_EM_RAW_EMULATE_INSTR;
276
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
278	return rc;
279	}
280	}
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
282	else
283	{
284	# ifdef PGM_SYNC_N_PAGES
285	/*
286	* If the region is write protected and we got a page not present fault, then sync
287	* the pages. If the fault was caused by a read, then restart the instruction.
288	* In case of write access continue to the GC write handler.
289	*/
290	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
291	&& !(uErr & X86_TRAP_PF_P))
292	{
293	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
294	if ( RT_FAILURE(rc)
295	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
296	\|\| !(uErr & X86_TRAP_PF_RW))
297	{
298	AssertRC(rc);
299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
300	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
301	return rc;
302	}
303	}
304	# endif
305	/*
306	* Ok, it's an virtual page access handler.
307	*
308	* Since it's faster to search by address, we'll do that first
309	* and then retry by GCPhys if that fails.
310	*/
311	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
312	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
313	* out of sync, because the page was changed without us noticing it (not-present -> present
314	* without invlpg or mov cr3, xxx).
315	*/
316	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
317	if (pCur)
318	{
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rc;
352	}
353	/* Unhandled part of a monitored page */
354	}
355	else
356	{
357	/* Check by physical address. */
358	unsigned iPage;
359	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
360	Assert(RT_SUCCESS(rc) \|\| !pCur);
361	if ( pCur
362	&& ( uErr & X86_TRAP_PF_RW
363	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
364	{
365	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
366	# ifdef IN_RC
367	STAM_PROFILE_START(&pCur->Stat, h);
368	RTGCPTR GCPtrStart = pCur->Core.Key;
369	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
370	pgmUnlock(pVM);
371	*pfLockTaken = false;
372
373	RTGCPTR off = (iPage << PAGE_SHIFT)
374	+ (pvFault & PAGE_OFFSET_MASK)
375	- (GCPtrStart & PAGE_OFFSET_MASK);
376	Assert(off < pCur->cb);
377	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
378
379	# ifdef VBOX_WITH_STATISTICS
380	pgmLock(pVM);
381	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
382	if (pCur)
383	STAM_PROFILE_STOP(&pCur->Stat, h);
384	pgmUnlock(pVM);
385	# endif
386	# else
387	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
388	# endif
389	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
390	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
391	return rc;
392	}
393	}
394	}
395	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
396
397	/*
398	* There is a handled area of the page, but this fault doesn't belong to it.
399	* We must emulate the instruction.
400	*
401	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
402	* we first check if this was a page-not-present fault for a page with only
403	* write access handlers. Restart the instruction if it wasn't a write access.
404	*/
405	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
406
407	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
408	&& !(uErr & X86_TRAP_PF_P))
409	{
410	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
411	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
412	# else
413	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
414	# endif
415	if ( RT_FAILURE(rc)
416	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
417	\|\| !(uErr & X86_TRAP_PF_RW))
418	{
419	AssertRC(rc);
420	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
421	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
422	return rc;
423	}
424	}
425
426	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
427	* It's writing to an unhandled part of the LDT page several million times.
428	*/
429	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
430	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
431	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
432	return rc;
433	} /* if any kind of handler */
434
435
436	/**
437	* #PF Handler for raw-mode guest execution.
438	*
439	* @returns VBox status code (appropriate for trap handling and GC return).
440	*
441	* @param pVCpu Pointer to the VMCPU.
442	* @param uErr The trap error code.
443	* @param pRegFrame Trap register frame.
444	* @param pvFault The fault address.
445	* @param pfLockTaken PGM lock taken here or not (out)
446	*/
447	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
448	{
449	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
450
451	*pfLockTaken = false;
452
453	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
454	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
455	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
456	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
457	int rc;
458
459	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
460	/*
461	* Walk the guest page translation tables and check if it's a guest fault.
462	*/
463	GSTPTWALK GstWalk;
464	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
465	if (RT_FAILURE_NP(rc))
466	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
467
468	/* assert some GstWalk sanity. */
469	# if PGM_GST_TYPE == PGM_TYPE_AMD64
470	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
471	# endif
472	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
473	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
474	# endif
475	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
476	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
477	Assert(GstWalk.Core.fSucceeded);
478
479	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
480	{
481	if ( ( (uErr & X86_TRAP_PF_RW)
482	&& !GstWalk.Core.fEffectiveRW
483	&& ( (uErr & X86_TRAP_PF_US)
484	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
485	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
486	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
487	)
488	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
489	}
490
491	/*
492	* Set the accessed and dirty flags.
493	*/
494	# if PGM_GST_TYPE == PGM_TYPE_AMD64
495	GstWalk.Pml4e.u \|= X86_PML4E_A;
496	GstWalk.pPml4e->u \|= X86_PML4E_A;
497	GstWalk.Pdpe.u \|= X86_PDPE_A;
498	GstWalk.pPdpe->u \|= X86_PDPE_A;
499	# endif
500	if (GstWalk.Core.fBigPage)
501	{
502	Assert(GstWalk.Pde.b.u1Size);
503	if (uErr & X86_TRAP_PF_RW)
504	{
505	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
506	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
507	}
508	else
509	{
510	GstWalk.Pde.u \|= X86_PDE4M_A;
511	GstWalk.pPde->u \|= X86_PDE4M_A;
512	}
513	}
514	else
515	{
516	Assert(!GstWalk.Pde.b.u1Size);
517	GstWalk.Pde.u \|= X86_PDE_A;
518	GstWalk.pPde->u \|= X86_PDE_A;
519	if (uErr & X86_TRAP_PF_RW)
520	{
521	# ifdef VBOX_WITH_STATISTICS
522	if (!GstWalk.Pte.n.u1Dirty)
523	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
524	else
525	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
526	# endif
527	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
528	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
529	}
530	else
531	{
532	GstWalk.Pte.u \|= X86_PTE_A;
533	GstWalk.pPte->u \|= X86_PTE_A;
534	}
535	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
536	}
537	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
538	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
539	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
540	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
541	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
542
543	/* Take the big lock now. */
544	*pfLockTaken = true;
545	pgmLock(pVM);
546
547	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
548	/*
549	* If it is a reserved bit fault we know that it is an MMIO (access
550	* handler) related fault and can skip some 200 lines of code.
551	*/
552	if (uErr & X86_TRAP_PF_RSVD)
553	{
554	Assert(uErr & X86_TRAP_PF_P);
555	PPGMPAGE pPage;
556	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
557	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
558	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
559	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
560	pfLockTaken, &GstWalk));
561	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
562	# else
563	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
564	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
565	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
566	pfLockTaken));
567	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
568	# endif
569	AssertRC(rc);
570	PGM_INVL_PG(pVCpu, pvFault);
571	return rc; /* Restart with the corrected entry. */
572	}
573	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
574
575	/*
576	* Fetch the guest PDE, PDPE and PML4E.
577	*/
578	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
579	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
580	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
581
582	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
583	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
584	PX86PDPAE pPDDst;
585	# if PGM_GST_TYPE == PGM_TYPE_PAE
586	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
587	# else
588	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
589	# endif
590	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
591
592	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
593	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
594	PX86PDPAE pPDDst;
595	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
596	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
597	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
598	# else
599	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
600	# endif
601	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
602
603	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
604	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
605	PEPTPD pPDDst;
606	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
607	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
608	# endif
609	Assert(pPDDst);
610
611	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
612	/*
613	* Dirty page handling.
614	*
615	* If we successfully correct the write protection fault due to dirty bit
616	* tracking, then return immediately.
617	*/
618	if (uErr & X86_TRAP_PF_RW) /* write fault? */
619	{
620	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
621	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
622	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
623	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
624	{
625	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
626	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
627	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
628	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
629	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
630	return VINF_SUCCESS;
631	}
632	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
633	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
634	}
635
636	# if 0 /* rarely useful; leave for debugging. */
637	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
638	# endif
639	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
640
641	/*
642	* A common case is the not-present error caused by lazy page table syncing.
643	*
644	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
645	* here so we can safely assume that the shadow PT is present when calling
646	* SyncPage later.
647	*
648	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
649	* of mapping conflict and defer to SyncCR3 in R3.
650	* (Again, we do NOT support access handlers for non-present guest pages.)
651	*
652	*/
653	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
654	Assert(GstWalk.Pde.n.u1Present);
655	# endif
656	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
657	&& !pPDDst->a[iPDDst].n.u1Present)
658	{
659	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
662	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
663	# else
664	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
665	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
666	# endif
667	if (RT_SUCCESS(rc))
668	return rc;
669	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
670	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
671	return VINF_PGM_SYNC_CR3;
672	}
673
674	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
675	/*
676	* Check if this address is within any of our mappings.
677	*
678	* This is very fast and it's gonna save us a bit of effort below and prevent
679	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
680	* (BTW, it's impossible to have physical access handlers in a mapping.)
681	*/
682	if (pgmMapAreMappingsEnabled(pVM))
683	{
684	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
685	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
686	{
687	if (pvFault < pMapping->GCPtr)
688	break;
689	if (pvFault - pMapping->GCPtr < pMapping->cb)
690	{
691	/*
692	* The first thing we check is if we've got an undetected conflict.
693	*/
694	if (pgmMapAreMappingsFloating(pVM))
695	{
696	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
697	while (iPT-- > 0)
698	if (GstWalk.pPde[iPT].n.u1Present)
699	{
700	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
701	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
702	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
703	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
704	return VINF_PGM_SYNC_CR3;
705	}
706	}
707
708	/*
709	* Check if the fault address is in a virtual page access handler range.
710	*/
711	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
712	if ( pCur
713	&& pvFault - pCur->Core.Key < pCur->cb
714	&& uErr & X86_TRAP_PF_RW)
715	{
716	# ifdef IN_RC
717	STAM_PROFILE_START(&pCur->Stat, h);
718	pgmUnlock(pVM);
719	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
720	pgmLock(pVM);
721	STAM_PROFILE_STOP(&pCur->Stat, h);
722	# else
723	AssertFailed();
724	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
725	# endif
726	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
727	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
728	return rc;
729	}
730
731	/*
732	* Pretend we're not here and let the guest handle the trap.
733	*/
734	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
735	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
736	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
737	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
738	return VINF_EM_RAW_GUEST_TRAP;
739	}
740	}
741	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
742	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
743
744	/*
745	* Check if this fault address is flagged for special treatment,
746	* which means we'll have to figure out the physical address and
747	* check flags associated with it.
748	*
749	* ASSUME that we can limit any special access handling to pages
750	* in page tables which the guest believes to be present.
751	*/
752	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
753	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
754	# else
755	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
756	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
757	PPGMPAGE pPage;
758	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
759	if (RT_FAILURE(rc))
760	{
761	/*
762	* When the guest accesses invalid physical memory (e.g. probing
763	* of RAM or accessing a remapped MMIO range), then we'll fall
764	* back to the recompiler to emulate the instruction.
765	*/
766	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
767	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
768	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
769	return VINF_EM_RAW_EMULATE_INSTR;
770	}
771
772	/*
773	* Any handlers for this page?
774	*/
775	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
776	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
777	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
778	&GstWalk));
779	# else
780	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
781	# endif
782
783	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
784
785	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
786	if (uErr & X86_TRAP_PF_P)
787	{
788	/*
789	* The page isn't marked, but it might still be monitored by a virtual page access handler.
790	* (ASSUMES no temporary disabling of virtual handlers.)
791	*/
792	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
793	* we should correct both the shadow page table and physical memory flags, and not only check for
794	* accesses within the handler region but for access to pages with virtual handlers. */
795	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
796	if (pCur)
797	{
798	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
799	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
800	\|\| !(uErr & X86_TRAP_PF_P)
801	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
802	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
803
804	if ( pvFault - pCur->Core.Key < pCur->cb
805	&& ( uErr & X86_TRAP_PF_RW
806	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
807	{
808	# ifdef IN_RC
809	STAM_PROFILE_START(&pCur->Stat, h);
810	pgmUnlock(pVM);
811	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
812	pgmLock(pVM);
813	STAM_PROFILE_STOP(&pCur->Stat, h);
814	# else
815	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
816	# endif
817	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
818	return rc;
819	}
820	}
821	}
822	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
823
824	/*
825	* We are here only if page is present in Guest page tables and
826	* trap is not handled by our handlers.
827	*
828	* Check it for page out-of-sync situation.
829	*/
830	if (!(uErr & X86_TRAP_PF_P))
831	{
832	/*
833	* Page is not present in our page tables. Try to sync it!
834	*/
835	if (uErr & X86_TRAP_PF_US)
836	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
837	else /* supervisor */
838	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
839
840	if (PGM_PAGE_IS_BALLOONED(pPage))
841	{
842	/* Emulate reads from ballooned pages as they are not present in
843	our shadow page tables. (Required for e.g. Solaris guests; soft
844	ecc, random nr generator.) */
845	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
846	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
847	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
848	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
849	return rc;
850	}
851
852	# if defined(LOG_ENABLED) && !defined(IN_RING0)
853	RTGCPHYS GCPhys2;
854	uint64_t fPageGst2;
855	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
856	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
857	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
858	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
859	# else
860	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
861	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
862	# endif
863	# endif /* LOG_ENABLED */
864
865	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
866	if ( !GstWalk.Core.fEffectiveUS
867	&& CPUMGetGuestCPL(pVCpu) == 0)
868	{
869	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
870	if ( pvFault == (RTGCPTR)pRegFrame->eip
871	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
872	# ifdef CSAM_DETECT_NEW_CODE_PAGES
873	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
874	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
875	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
876	)
877	{
878	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
879	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
880	if (rc != VINF_SUCCESS)
881	{
882	/*
883	* CSAM needs to perform a job in ring 3.
884	*
885	* Sync the page before going to the host context; otherwise we'll end up in a loop if
886	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
887	*/
888	LogFlow(("CSAM ring 3 job\n"));
889	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
890	AssertRC(rc2);
891
892	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
893	return rc;
894	}
895	}
896	# ifdef CSAM_DETECT_NEW_CODE_PAGES
897	else if ( uErr == X86_TRAP_PF_RW
898	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
899	&& pRegFrame->ecx < 0x10000)
900	{
901	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
902	* to detect loading of new code pages.
903	*/
904
905	/*
906	* Decode the instruction.
907	*/
908	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
909	uint32_t cbOp;
910	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
911
912	/* For now we'll restrict this to rep movsw/d instructions */
913	if ( rc == VINF_SUCCESS
914	&& pDis->pCurInstr->opcode == OP_MOVSWD
915	&& (pDis->prefix & DISPREFIX_REP))
916	{
917	CSAMMarkPossibleCodePage(pVM, pvFault);
918	}
919	}
920	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
921
922	/*
923	* Mark this page as safe.
924	*/
925	/** @todo not correct for pages that contain both code and data!! */
926	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
927	CSAMMarkPage(pVM, pvFault, true);
928	}
929	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
930	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
931	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
932	# else
933	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
934	# endif
935	if (RT_SUCCESS(rc))
936	{
937	/* The page was successfully synced, return to the guest. */
938	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
939	return VINF_SUCCESS;
940	}
941	}
942	else /* uErr & X86_TRAP_PF_P: */
943	{
944	/*
945	* Write protected pages are made writable when the guest makes the
946	* first write to it. This happens for pages that are shared, write
947	* monitored or not yet allocated.
948	*
949	* We may also end up here when CR0.WP=0 in the guest.
950	*
951	* Also, a side effect of not flushing global PDEs are out of sync
952	* pages due to physical monitored regions, that are no longer valid.
953	* Assume for now it only applies to the read/write flag.
954	*/
955	if (uErr & X86_TRAP_PF_RW)
956	{
957	/*
958	* Check if it is a read-only page.
959	*/
960	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
961	{
962	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
963	Assert(!PGM_PAGE_IS_ZERO(pPage));
964	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
965	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
966
967	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
968	if (rc != VINF_SUCCESS)
969	{
970	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
971	return rc;
972	}
973	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
974	return VINF_EM_NO_MEMORY;
975	}
976
977	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
978	/*
979	* Check to see if we need to emulate the instruction if CR0.WP=0.
980	*/
981	if ( !GstWalk.Core.fEffectiveRW
982	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
983	&& CPUMGetGuestCPL(pVCpu) == 0)
984	{
985	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
986	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
987	if (RT_SUCCESS(rc))
988	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
989	else
990	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
991	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
992	return rc;
993	}
994	# endif
995	/// @todo count the above case; else
996	if (uErr & X86_TRAP_PF_US)
997	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
998	else /* supervisor */
999	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1000
1001	/*
1002	* Sync the page.
1003	*
1004	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1005	* page is not present, which is not true in this case.
1006	*/
1007	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1008	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1009	# else
1010	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1011	# endif
1012	if (RT_SUCCESS(rc))
1013	{
1014	/*
1015	* Page was successfully synced, return to guest but invalidate
1016	* the TLB first as the page is very likely to be in it.
1017	*/
1018	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1019	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1020	# else
1021	PGM_INVL_PG(pVCpu, pvFault);
1022	# endif
1023	# ifdef VBOX_STRICT
1024	RTGCPHYS GCPhys2;
1025	uint64_t fPageGst;
1026	if (!pVM->pgm.s.fNestedPaging)
1027	{
1028	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1029	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1030	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1031	}
1032	uint64_t fPageShw;
1033	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1034	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1035	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1036	# endif /* VBOX_STRICT */
1037	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1038	return VINF_SUCCESS;
1039	}
1040	}
1041	/** @todo else: why are we here? */
1042
1043	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1044	/*
1045	* Check for VMM page flags vs. Guest page flags consistency.
1046	* Currently only for debug purposes.
1047	*/
1048	if (RT_SUCCESS(rc))
1049	{
1050	/* Get guest page flags. */
1051	uint64_t fPageGst;
1052	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1053	if (RT_SUCCESS(rc))
1054	{
1055	uint64_t fPageShw;
1056	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1057
1058	/*
1059	* Compare page flags.
1060	* Note: we have AVL, A, D bits desynced.
1061	*/
1062	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1063	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1064	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1065	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1066	}
1067	else
1068	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1069	}
1070	else
1071	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1072	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1073	}
1074
1075
1076	/*
1077	* If we get here it is because something failed above, i.e. most like guru
1078	* meditiation time.
1079	*/
1080	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1081	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1082	return rc;
1083
1084	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1085	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1086	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1087	return VERR_PGM_NOT_USED_IN_MODE;
1088	# endif
1089	}
1090	#endif /* !IN_RING3 */
1091
1092
1093	/**
1094	* Emulation of the invlpg instruction.
1095	*
1096	*
1097	* @returns VBox status code.
1098	*
1099	* @param pVCpu Pointer to the VMCPU.
1100	* @param GCPtrPage Page to invalidate.
1101	*
1102	* @remark ASSUMES that the guest is updating before invalidating. This order
1103	* isn't required by the CPU, so this is speculative and could cause
1104	* trouble.
1105	* @remark No TLB shootdown is done on any other VCPU as we assume that
1106	* invlpg emulation is the only reason for calling this function.
1107	* (The guest has to shoot down TLB entries on other CPUs itself)
1108	* Currently true, but keep in mind!
1109	*
1110	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1111	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1112	*/
1113	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1114	{
1115	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1116	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1117	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1118	int rc;
1119	PVM pVM = pVCpu->CTX_SUFF(pVM);
1120	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1121
1122	PGM_LOCK_ASSERT_OWNER(pVM);
1123
1124	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1125
1126	/*
1127	* Get the shadow PD entry and skip out if this PD isn't present.
1128	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1129	*/
1130	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1131	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1132	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1133
1134	/* Fetch the pgm pool shadow descriptor. */
1135	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1136	Assert(pShwPde);
1137
1138	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1139	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1140	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1141
1142	/* If the shadow PDPE isn't present, then skip the invalidate. */
1143	if (!pPdptDst->a[iPdpt].n.u1Present)
1144	{
1145	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1146	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1147	return VINF_SUCCESS;
1148	}
1149
1150	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1151	PPGMPOOLPAGE pShwPde = NULL;
1152	PX86PDPAE pPDDst;
1153
1154	/* Fetch the pgm pool shadow descriptor. */
1155	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1156	AssertRCSuccessReturn(rc, rc);
1157	Assert(pShwPde);
1158
1159	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1160	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1161
1162	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1163	/* PML4 */
1164	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1165	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1166	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1167	PX86PDPAE pPDDst;
1168	PX86PDPT pPdptDst;
1169	PX86PML4E pPml4eDst;
1170	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1171	if (rc != VINF_SUCCESS)
1172	{
1173	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1174	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1175	return VINF_SUCCESS;
1176	}
1177	Assert(pPDDst);
1178
1179	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1180	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1181
1182	if (!pPdpeDst->n.u1Present)
1183	{
1184	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1185	return VINF_SUCCESS;
1186	}
1187
1188	/* Fetch the pgm pool shadow descriptor. */
1189	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1190	Assert(pShwPde);
1191
1192	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1193
1194	const SHWPDE PdeDst = *pPdeDst;
1195	if (!PdeDst.n.u1Present)
1196	{
1197	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1198	return VINF_SUCCESS;
1199	}
1200
1201	/*
1202	* Get the guest PD entry and calc big page.
1203	*/
1204	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1205	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1206	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1207	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1208	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1209	unsigned iPDSrc = 0;
1210	# if PGM_GST_TYPE == PGM_TYPE_PAE
1211	X86PDPE PdpeSrcIgn;
1212	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1213	# else /* AMD64 */
1214	PX86PML4E pPml4eSrcIgn;
1215	X86PDPE PdpeSrcIgn;
1216	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1217	# endif
1218	GSTPDE PdeSrc;
1219
1220	if (pPDSrc)
1221	PdeSrc = pPDSrc->a[iPDSrc];
1222	else
1223	PdeSrc.u = 0;
1224	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1225	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1226
1227	# ifdef IN_RING3
1228	/*
1229	* If a CR3 Sync is pending we may ignore the invalidate page operation
1230	* depending on the kind of sync and if it's a global page or not.
1231	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1232	*/
1233	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1234	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1235	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1236	&& fIsBigPage
1237	&& PdeSrc.b.u1Global
1238	)
1239	)
1240	# else
1241	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1242	# endif
1243	{
1244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1245	return VINF_SUCCESS;
1246	}
1247	# endif /* IN_RING3 */
1248
1249	/*
1250	* Deal with the Guest PDE.
1251	*/
1252	rc = VINF_SUCCESS;
1253	if (PdeSrc.n.u1Present)
1254	{
1255	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1256	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1257	# ifndef PGM_WITHOUT_MAPPING
1258	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1259	{
1260	/*
1261	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1262	*/
1263	Assert(pgmMapAreMappingsEnabled(pVM));
1264	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1265	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1266	}
1267	else
1268	# endif /* !PGM_WITHOUT_MAPPING */
1269	if (!fIsBigPage)
1270	{
1271	/*
1272	* 4KB - page.
1273	*/
1274	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1275	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1276
1277	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1278	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1279	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1280	# endif
1281	if (pShwPage->GCPhys == GCPhys)
1282	{
1283	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1284	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1285
1286	PGSTPT pPTSrc;
1287	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1288	if (RT_SUCCESS(rc))
1289	{
1290	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1291	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1292	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1293	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1294	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1295	GCPtrPage, PteSrc.n.u1Present,
1296	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1297	PteSrc.n.u1User & PdeSrc.n.u1User,
1298	(uint64_t)PteSrc.u,
1299	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1300	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1301	}
1302	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1303	PGM_INVL_PG(pVCpu, GCPtrPage);
1304	}
1305	else
1306	{
1307	/*
1308	* The page table address changed.
1309	*/
1310	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1311	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1312	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1313	ASMAtomicWriteSize(pPdeDst, 0);
1314	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1315	PGM_INVL_VCPU_TLBS(pVCpu);
1316	}
1317	}
1318	else
1319	{
1320	/*
1321	* 2/4MB - page.
1322	*/
1323	/* Before freeing the page, check if anything really changed. */
1324	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1325	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1326	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1327	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1328	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1329	# endif
1330	if ( pShwPage->GCPhys == GCPhys
1331	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1332	{
1333	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1334	/** @todo This test is wrong as it cannot check the G bit!
1335	* FIXME */
1336	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1337	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1338	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1339	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1340	{
1341	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1342	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1343	return VINF_SUCCESS;
1344	}
1345	}
1346
1347	/*
1348	* Ok, the page table is present and it's been changed in the guest.
1349	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1350	* We could do this for some flushes in GC too, but we need an algorithm for
1351	* deciding which 4MB pages containing code likely to be executed very soon.
1352	*/
1353	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1354	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1355	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1356	ASMAtomicWriteSize(pPdeDst, 0);
1357	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1358	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1359	}
1360	}
1361	else
1362	{
1363	/*
1364	* Page directory is not present, mark shadow PDE not present.
1365	*/
1366	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1367	{
1368	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1369	ASMAtomicWriteSize(pPdeDst, 0);
1370	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1371	PGM_INVL_PG(pVCpu, GCPtrPage);
1372	}
1373	else
1374	{
1375	Assert(pgmMapAreMappingsEnabled(pVM));
1376	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1377	}
1378	}
1379	return rc;
1380
1381	#else /* guest real and protected mode */
1382	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1383	NOREF(pVCpu); NOREF(GCPtrPage);
1384	return VINF_SUCCESS;
1385	#endif
1386	}
1387
1388
1389	/**
1390	* Update the tracking of shadowed pages.
1391	*
1392	* @param pVCpu Pointer to the VMCPU.
1393	* @param pShwPage The shadow page.
1394	* @param HCPhys The physical page we is being dereferenced.
1395	* @param iPte Shadow PTE index
1396	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1397	*/
1398	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1399	RTGCPHYS GCPhysPage)
1400	{
1401	PVM pVM = pVCpu->CTX_SUFF(pVM);
1402
1403	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1404	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1405	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1406
1407	/* Use the hint we retrieved from the cached guest PT. */
1408	if (pShwPage->fDirty)
1409	{
1410	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1411
1412	Assert(pShwPage->cPresent);
1413	Assert(pPool->cPresent);
1414	pShwPage->cPresent--;
1415	pPool->cPresent--;
1416
1417	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1418	AssertRelease(pPhysPage);
1419	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1420	return;
1421	}
1422	# else
1423	NOREF(GCPhysPage);
1424	# endif
1425
1426	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1427	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1428
1429	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1430	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1431	* 2. write protect all shadowed pages. I.e. implement caching.
1432	*/
1433	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1434
1435	/*
1436	* Find the guest address.
1437	*/
1438	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1439	pRam;
1440	pRam = pRam->CTX_SUFF(pNext))
1441	{
1442	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1443	while (iPage-- > 0)
1444	{
1445	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1446	{
1447	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1448
1449	Assert(pShwPage->cPresent);
1450	Assert(pPool->cPresent);
1451	pShwPage->cPresent--;
1452	pPool->cPresent--;
1453
1454	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1455	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1456	return;
1457	}
1458	}
1459	}
1460
1461	for (;;)
1462	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1463	}
1464
1465
1466	/**
1467	* Update the tracking of shadowed pages.
1468	*
1469	* @param pVCpu Pointer to the VMCPU.
1470	* @param pShwPage The shadow page.
1471	* @param u16 The top 16-bit of the pPage->HCPhys.
1472	* @param pPage Pointer to the guest page. this will be modified.
1473	* @param iPTDst The index into the shadow table.
1474	*/
1475	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1476	{
1477	PVM pVM = pVCpu->CTX_SUFF(pVM);
1478
1479	/*
1480	* Just deal with the simple first time here.
1481	*/
1482	if (!u16)
1483	{
1484	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1485	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1486	/* Save the page table index. */
1487	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1488	}
1489	else
1490	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1491
1492	/* write back */
1493	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1494	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1495
1496	/* update statistics. */
1497	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1498	pShwPage->cPresent++;
1499	if (pShwPage->iFirstPresent > iPTDst)
1500	pShwPage->iFirstPresent = iPTDst;
1501	}
1502
1503
1504	/**
1505	* Modifies a shadow PTE to account for access handlers.
1506	*
1507	* @param pVM Pointer to the VM.
1508	* @param pPage The page in question.
1509	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1510	* A (accessed) bit so it can be emulated correctly.
1511	* @param pPteDst The shadow PTE (output). This is temporary storage and
1512	* does not need to be set atomically.
1513	*/
1514	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1515	{
1516	NOREF(pVM);
1517	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1518	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1519	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1520	{
1521	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1522	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1523	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1524	pPteDst->n.u1Present = 1;
1525	pPteDst->n.u1Execute = 1;
1526	pPteDst->n.u1IgnorePAT = 1;
1527	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1528	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1529	#else
1530	if (fPteSrc & X86_PTE_A)
1531	{
1532	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1533	SHW_PTE_SET_RO(*pPteDst);
1534	}
1535	else
1536	SHW_PTE_SET(*pPteDst, 0);
1537	#endif
1538	}
1539	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1540	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1541	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1542	&& ( BTH_IS_NP_ACTIVE(pVM)
1543	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1544	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1545	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1546	# endif
1547	)
1548	{
1549	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1550	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1551	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1552	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1553	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1554	pPteDst->n.u1Present = 0;
1555	pPteDst->n.u1Write = 1;
1556	pPteDst->n.u1Execute = 0;
1557	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1558	pPteDst->n.u3EMT = 7;
1559	# else
1560	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1561	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1562	# endif
1563	}
1564	# endif
1565	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1566	else
1567	{
1568	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1569	SHW_PTE_SET(*pPteDst, 0);
1570	}
1571	/** @todo count these kinds of entries. */
1572	}
1573
1574
1575	/**
1576	* Creates a 4K shadow page for a guest page.
1577	*
1578	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1579	* physical address. The PdeSrc argument only the flags are used. No page
1580	* structured will be mapped in this function.
1581	*
1582	* @param pVCpu Pointer to the VMCPU.
1583	* @param pPteDst Destination page table entry.
1584	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1585	* Can safely assume that only the flags are being used.
1586	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1587	* @param pShwPage Pointer to the shadow page.
1588	* @param iPTDst The index into the shadow table.
1589	*
1590	* @remark Not used for 2/4MB pages!
1591	*/
1592	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1593	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1594	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1595	#else
1596	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1597	#endif
1598	{
1599	PVM pVM = pVCpu->CTX_SUFF(pVM);
1600	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1601
1602	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1603	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1604	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1605
1606	if (pShwPage->fDirty)
1607	{
1608	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1609	PGSTPT pGstPT;
1610
1611	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1612	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1613	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1614	pGstPT->a[iPTDst].u = PteSrc.u;
1615	}
1616	#else
1617	Assert(!pShwPage->fDirty);
1618	#endif
1619
1620	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1621	if ( PteSrc.n.u1Present
1622	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1623	#endif
1624	{
1625	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1626	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1627	# endif
1628	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1629
1630	/*
1631	* Find the ram range.
1632	*/
1633	PPGMPAGE pPage;
1634	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1635	if (RT_SUCCESS(rc))
1636	{
1637	/* Ignore ballooned pages.
1638	Don't return errors or use a fatal assert here as part of a
1639	shadow sync range might included ballooned pages. */
1640	if (PGM_PAGE_IS_BALLOONED(pPage))
1641	{
1642	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1643	return;
1644	}
1645
1646	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1647	/* Make the page writable if necessary. */
1648	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1649	&& ( PGM_PAGE_IS_ZERO(pPage)
1650	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1651	\|\| ( PteSrc.n.u1Write
1652	# else
1653	\|\| ( 1
1654	# endif
1655	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1656	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1657	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1658	# endif
1659	# ifdef VBOX_WITH_PAGE_SHARING
1660	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1661	# endif
1662	)
1663	)
1664	)
1665	{
1666	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1667	AssertRC(rc);
1668	}
1669	#endif
1670
1671	/*
1672	* Make page table entry.
1673	*/
1674	SHWPTE PteDst;
1675	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1676	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1677	# else
1678	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1679	# endif
1680	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1681	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1682	else
1683	{
1684	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1685	/*
1686	* If the page or page directory entry is not marked accessed,
1687	* we mark the page not present.
1688	*/
1689	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1690	{
1691	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1692	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1693	SHW_PTE_SET(PteDst, 0);
1694	}
1695	/*
1696	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1697	* when the page is modified.
1698	*/
1699	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1700	{
1701	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1702	SHW_PTE_SET(PteDst,
1703	fGstShwPteFlags
1704	\| PGM_PAGE_GET_HCPHYS(pPage)
1705	\| PGM_PTFLAGS_TRACK_DIRTY);
1706	SHW_PTE_SET_RO(PteDst);
1707	}
1708	else
1709	#endif
1710	{
1711	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1712	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1713	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1714	PteDst.n.u1Present = 1;
1715	PteDst.n.u1Write = 1;
1716	PteDst.n.u1Execute = 1;
1717	PteDst.n.u1IgnorePAT = 1;
1718	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1719	/* PteDst.n.u1Size = 0 */
1720	#else
1721	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1722	#endif
1723	}
1724
1725	/*
1726	* Make sure only allocated pages are mapped writable.
1727	*/
1728	if ( SHW_PTE_IS_P_RW(PteDst)
1729	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1730	{
1731	/* Still applies to shared pages. */
1732	Assert(!PGM_PAGE_IS_ZERO(pPage));
1733	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1734	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1735	}
1736	}
1737
1738	/*
1739	* Keep user track up to date.
1740	*/
1741	if (SHW_PTE_IS_P(PteDst))
1742	{
1743	if (!SHW_PTE_IS_P(*pPteDst))
1744	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1745	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1746	{
1747	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1748	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1749	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1750	}
1751	}
1752	else if (SHW_PTE_IS_P(*pPteDst))
1753	{
1754	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1755	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1756	}
1757
1758	/*
1759	* Update statistics and commit the entry.
1760	*/
1761	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1762	if (!PteSrc.n.u1Global)
1763	pShwPage->fSeenNonGlobal = true;
1764	#endif
1765	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1766	return;
1767	}
1768
1769	/** @todo count these three different kinds. */
1770	Log2(("SyncPageWorker: invalid address in Pte\n"));
1771	}
1772	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1773	else if (!PteSrc.n.u1Present)
1774	Log2(("SyncPageWorker: page not present in Pte\n"));
1775	else
1776	Log2(("SyncPageWorker: invalid Pte\n"));
1777	#endif
1778
1779	/*
1780	* The page is not present or the PTE is bad. Replace the shadow PTE by
1781	* an empty entry, making sure to keep the user tracking up to date.
1782	*/
1783	if (SHW_PTE_IS_P(*pPteDst))
1784	{
1785	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1786	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1787	}
1788	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1789	}
1790
1791
1792	/**
1793	* Syncs a guest OS page.
1794	*
1795	* There are no conflicts at this point, neither is there any need for
1796	* page table allocations.
1797	*
1798	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1799	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1800	*
1801	* @returns VBox status code.
1802	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1803	* @param pVCpu Pointer to the VMCPU.
1804	* @param PdeSrc Page directory entry of the guest.
1805	* @param GCPtrPage Guest context page address.
1806	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1807	* @param uErr Fault error (X86_TRAP_PF_*).
1808	*/
1809	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1810	{
1811	PVM pVM = pVCpu->CTX_SUFF(pVM);
1812	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1813	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1814
1815	PGM_LOCK_ASSERT_OWNER(pVM);
1816
1817	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1818	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1819	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1820	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1821	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1822
1823	/*
1824	* Assert preconditions.
1825	*/
1826	Assert(PdeSrc.n.u1Present);
1827	Assert(cPages);
1828	# if 0 /* rarely useful; leave for debugging. */
1829	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1830	# endif
1831
1832	/*
1833	* Get the shadow PDE, find the shadow page table in the pool.
1834	*/
1835	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1836	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1837	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1838
1839	/* Fetch the pgm pool shadow descriptor. */
1840	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1841	Assert(pShwPde);
1842
1843	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1844	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1845	PPGMPOOLPAGE pShwPde = NULL;
1846	PX86PDPAE pPDDst;
1847
1848	/* Fetch the pgm pool shadow descriptor. */
1849	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1850	AssertRCSuccessReturn(rc2, rc2);
1851	Assert(pShwPde);
1852
1853	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1854	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1855
1856	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1857	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1858	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1859	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1860	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1861
1862	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1863	AssertRCSuccessReturn(rc2, rc2);
1864	Assert(pPDDst && pPdptDst);
1865	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1866	# endif
1867	SHWPDE PdeDst = *pPdeDst;
1868
1869	/*
1870	* - In the guest SMP case we could have blocked while another VCPU reused
1871	* this page table.
1872	* - With W7-64 we may also take this path when the A bit is cleared on
1873	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1874	* relevant TLB entries. If we're write monitoring any page mapped by
1875	* the modified entry, we may end up here with a "stale" TLB entry.
1876	*/
1877	if (!PdeDst.n.u1Present)
1878	{
1879	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1880	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1881	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1882	if (uErr & X86_TRAP_PF_P)
1883	PGM_INVL_PG(pVCpu, GCPtrPage);
1884	return VINF_SUCCESS; /* force the instruction to be executed again. */
1885	}
1886
1887	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1888	Assert(pShwPage);
1889
1890	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1891	/* Fetch the pgm pool shadow descriptor. */
1892	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1893	Assert(pShwPde);
1894	# endif
1895
1896	/*
1897	* Check that the page is present and that the shadow PDE isn't out of sync.
1898	*/
1899	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1900	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1901	RTGCPHYS GCPhys;
1902	if (!fBigPage)
1903	{
1904	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1905	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1906	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1907	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1908	# endif
1909	}
1910	else
1911	{
1912	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1913	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1914	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1915	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1916	# endif
1917	}
1918	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1919	if ( fPdeValid
1920	&& pShwPage->GCPhys == GCPhys
1921	&& PdeSrc.n.u1Present
1922	&& PdeSrc.n.u1User == PdeDst.n.u1User
1923	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1924	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1925	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1926	# endif
1927	)
1928	{
1929	/*
1930	* Check that the PDE is marked accessed already.
1931	* Since we set the accessed bit before getting here on a #PF, this
1932	* check is only meant for dealing with non-#PF'ing paths.
1933	*/
1934	if (PdeSrc.n.u1Accessed)
1935	{
1936	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1937	if (!fBigPage)
1938	{
1939	/*
1940	* 4KB Page - Map the guest page table.
1941	*/
1942	PGSTPT pPTSrc;
1943	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1944	if (RT_SUCCESS(rc))
1945	{
1946	# ifdef PGM_SYNC_N_PAGES
1947	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1948	if ( cPages > 1
1949	&& !(uErr & X86_TRAP_PF_P)
1950	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1951	{
1952	/*
1953	* This code path is currently only taken when the caller is PGMTrap0eHandler
1954	* for non-present pages!
1955	*
1956	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1957	* deal with locality.
1958	*/
1959	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1960	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1961	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1962	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1963	# else
1964	const unsigned offPTSrc = 0;
1965	# endif
1966	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1967	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1968	iPTDst = 0;
1969	else
1970	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1971
1972	for (; iPTDst < iPTDstEnd; iPTDst++)
1973	{
1974	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1975
1976	if ( pPteSrc->n.u1Present
1977	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1978	{
1979	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1980	NOREF(GCPtrCurPage);
1981	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
1982	/*
1983	* Assuming kernel code will be marked as supervisor - and not as user level
1984	* and executed using a conforming code selector - And marked as readonly.
1985	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1986	*/
1987	PPGMPAGE pPage;
1988	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1989	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1990	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1991	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
1992	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1993	)
1994	# endif /* else: CSAM not active */
1995	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1996	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1997	GCPtrCurPage, pPteSrc->n.u1Present,
1998	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
1999	pPteSrc->n.u1User & PdeSrc.n.u1User,
2000	(uint64_t)pPteSrc->u,
2001	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2002	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2003	}
2004	}
2005	}
2006	else
2007	# endif /* PGM_SYNC_N_PAGES */
2008	{
2009	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2010	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2011	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2012	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2013	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2014	GCPtrPage, PteSrc.n.u1Present,
2015	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2016	PteSrc.n.u1User & PdeSrc.n.u1User,
2017	(uint64_t)PteSrc.u,
2018	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2019	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2020	}
2021	}
2022	else /* MMIO or invalid page: emulated in #PF handler. */
2023	{
2024	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2025	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2026	}
2027	}
2028	else
2029	{
2030	/*
2031	* 4/2MB page - lazy syncing shadow 4K pages.
2032	* (There are many causes of getting here, it's no longer only CSAM.)
2033	*/
2034	/* Calculate the GC physical address of this 4KB shadow page. */
2035	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2036	/* Find ram range. */
2037	PPGMPAGE pPage;
2038	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2039	if (RT_SUCCESS(rc))
2040	{
2041	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2042
2043	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2044	/* Try to make the page writable if necessary. */
2045	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2046	&& ( PGM_PAGE_IS_ZERO(pPage)
2047	\|\| ( PdeSrc.n.u1Write
2048	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2049	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2050	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2051	# endif
2052	# ifdef VBOX_WITH_PAGE_SHARING
2053	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2054	# endif
2055	)
2056	)
2057	)
2058	{
2059	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2060	AssertRC(rc);
2061	}
2062	# endif
2063
2064	/*
2065	* Make shadow PTE entry.
2066	*/
2067	SHWPTE PteDst;
2068	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2069	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2070	else
2071	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2072
2073	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2074	if ( SHW_PTE_IS_P(PteDst)
2075	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2076	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2077
2078	/* Make sure only allocated pages are mapped writable. */
2079	if ( SHW_PTE_IS_P_RW(PteDst)
2080	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2081	{
2082	/* Still applies to shared pages. */
2083	Assert(!PGM_PAGE_IS_ZERO(pPage));
2084	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2085	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2086	}
2087
2088	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2089
2090	/*
2091	* If the page is not flagged as dirty and is writable, then make it read-only
2092	* at PD level, so we can set the dirty bit when the page is modified.
2093	*
2094	* ASSUMES that page access handlers are implemented on page table entry level.
2095	* Thus we will first catch the dirty access and set PDE.D and restart. If
2096	* there is an access handler, we'll trap again and let it work on the problem.
2097	*/
2098	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2099	* As for invlpg, it simply frees the whole shadow PT.
2100	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2101	if ( !PdeSrc.b.u1Dirty
2102	&& PdeSrc.b.u1Write)
2103	{
2104	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2105	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2106	PdeDst.n.u1Write = 0;
2107	}
2108	else
2109	{
2110	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2111	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2112	}
2113	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2114	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2115	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2116	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2117	}
2118	else
2119	{
2120	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2121	/** @todo must wipe the shadow page table entry in this
2122	* case. */
2123	}
2124	}
2125	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2126	return VINF_SUCCESS;
2127	}
2128
2129	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2130	}
2131	else if (fPdeValid)
2132	{
2133	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2134	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2135	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2136	}
2137	else
2138	{
2139	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2140	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2141	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2142	}
2143
2144	/*
2145	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2146	* Yea, I'm lazy.
2147	*/
2148	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2149	ASMAtomicWriteSize(pPdeDst, 0);
2150
2151	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2152	PGM_INVL_VCPU_TLBS(pVCpu);
2153	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2154
2155
2156	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2157	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2158	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2159	&& !defined(IN_RC)
2160	NOREF(PdeSrc);
2161
2162	# ifdef PGM_SYNC_N_PAGES
2163	/*
2164	* Get the shadow PDE, find the shadow page table in the pool.
2165	*/
2166	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2167	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2168
2169	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2170	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2171
2172	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2173	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2174	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2175	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2176	X86PDEPAE PdeDst;
2177	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2178
2179	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2180	AssertRCSuccessReturn(rc, rc);
2181	Assert(pPDDst && pPdptDst);
2182	PdeDst = pPDDst->a[iPDDst];
2183	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2184	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2185	PEPTPD pPDDst;
2186	EPTPDE PdeDst;
2187
2188	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2189	if (rc != VINF_SUCCESS)
2190	{
2191	AssertRC(rc);
2192	return rc;
2193	}
2194	Assert(pPDDst);
2195	PdeDst = pPDDst->a[iPDDst];
2196	# endif
2197	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2198	if (!PdeDst.n.u1Present)
2199	{
2200	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2201	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2202	return VINF_SUCCESS; /* force the instruction to be executed again. */
2203	}
2204
2205	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2206	if (PdeDst.n.u1Size)
2207	{
2208	Assert(pVM->pgm.s.fNestedPaging);
2209	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2210	return VINF_SUCCESS;
2211	}
2212
2213	/* Mask away the page offset. */
2214	GCPtrPage &= ~((RTGCPTR)0xfff);
2215
2216	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2217	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2218
2219	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2220	if ( cPages > 1
2221	&& !(uErr & X86_TRAP_PF_P)
2222	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2223	{
2224	/*
2225	* This code path is currently only taken when the caller is PGMTrap0eHandler
2226	* for non-present pages!
2227	*
2228	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2229	* deal with locality.
2230	*/
2231	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2232	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2233	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2234	iPTDst = 0;
2235	else
2236	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2237	for (; iPTDst < iPTDstEnd; iPTDst++)
2238	{
2239	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2240	{
2241	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2242	\| (iPTDst << PAGE_SHIFT));
2243
2244	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2245	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2246	GCPtrCurPage,
2247	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2248	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2249
2250	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2251	break;
2252	}
2253	else
2254	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2255	}
2256	}
2257	else
2258	# endif /* PGM_SYNC_N_PAGES */
2259	{
2260	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2261	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2262	\| (iPTDst << PAGE_SHIFT));
2263
2264	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2265
2266	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2267	GCPtrPage,
2268	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2269	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2270	}
2271	return VINF_SUCCESS;
2272
2273	#else
2274	NOREF(PdeSrc);
2275	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2276	return VERR_PGM_NOT_USED_IN_MODE;
2277	#endif
2278	}
2279
2280
2281	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2282
2283	/**
2284	* CheckPageFault helper for returning a page fault indicating a non-present
2285	* (NP) entry in the page translation structures.
2286	*
2287	* @returns VINF_EM_RAW_GUEST_TRAP.
2288	* @param pVCpu Pointer to the VMCPU.
2289	* @param uErr The error code of the shadow fault. Corrections to
2290	* TRPM's copy will be made if necessary.
2291	* @param GCPtrPage For logging.
2292	* @param uPageFaultLevel For logging.
2293	*/
2294	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2295	{
2296	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2297	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2298	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2299	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2300	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2301
2302	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2303	return VINF_EM_RAW_GUEST_TRAP;
2304	}
2305
2306
2307	/**
2308	* CheckPageFault helper for returning a page fault indicating a reserved bit
2309	* (RSVD) error in the page translation structures.
2310	*
2311	* @returns VINF_EM_RAW_GUEST_TRAP.
2312	* @param pVCpu Pointer to the VMCPU.
2313	* @param uErr The error code of the shadow fault. Corrections to
2314	* TRPM's copy will be made if necessary.
2315	* @param GCPtrPage For logging.
2316	* @param uPageFaultLevel For logging.
2317	*/
2318	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2319	{
2320	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2321	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2322	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2323
2324	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2325	return VINF_EM_RAW_GUEST_TRAP;
2326	}
2327
2328
2329	/**
2330	* CheckPageFault helper for returning a page protection fault (P).
2331	*
2332	* @returns VINF_EM_RAW_GUEST_TRAP.
2333	* @param pVCpu Pointer to the VMCPU.
2334	* @param uErr The error code of the shadow fault. Corrections to
2335	* TRPM's copy will be made if necessary.
2336	* @param GCPtrPage For logging.
2337	* @param uPageFaultLevel For logging.
2338	*/
2339	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2340	{
2341	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2342	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2343	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2344	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2345
2346	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2347	return VINF_EM_RAW_GUEST_TRAP;
2348	}
2349
2350
2351	/**
2352	* Handle dirty bit tracking faults.
2353	*
2354	* @returns VBox status code.
2355	* @param pVCpu Pointer to the VMCPU.
2356	* @param uErr Page fault error code.
2357	* @param pPdeSrc Guest page directory entry.
2358	* @param pPdeDst Shadow page directory entry.
2359	* @param GCPtrPage Guest context page address.
2360	*/
2361	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2362	RTGCPTR GCPtrPage)
2363	{
2364	PVM pVM = pVCpu->CTX_SUFF(pVM);
2365	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2366	NOREF(uErr);
2367
2368	PGM_LOCK_ASSERT_OWNER(pVM);
2369
2370	/*
2371	* Handle big page.
2372	*/
2373	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2374	{
2375	if ( pPdeDst->n.u1Present
2376	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2377	{
2378	SHWPDE PdeDst = *pPdeDst;
2379
2380	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2381	Assert(pPdeSrc->b.u1Write);
2382
2383	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2384	* fault again and take this path to only invalidate the entry (see below).
2385	*/
2386	PdeDst.n.u1Write = 1;
2387	PdeDst.n.u1Accessed = 1;
2388	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2389	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2390	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2391	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2392	}
2393
2394	# ifdef IN_RING0
2395	/* Check for stale TLB entry; only applies to the SMP guest case. */
2396	if ( pVM->cCpus > 1
2397	&& pPdeDst->n.u1Write
2398	&& pPdeDst->n.u1Accessed)
2399	{
2400	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2401	if (pShwPage)
2402	{
2403	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2404	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2405	if (SHW_PTE_IS_P_RW(*pPteDst))
2406	{
2407	/* Stale TLB entry. */
2408	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2409	PGM_INVL_PG(pVCpu, GCPtrPage);
2410	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2411	}
2412	}
2413	}
2414	# endif /* IN_RING0 */
2415	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2416	}
2417
2418	/*
2419	* Map the guest page table.
2420	*/
2421	PGSTPT pPTSrc;
2422	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2423	if (RT_FAILURE(rc))
2424	{
2425	AssertRC(rc);
2426	return rc;
2427	}
2428
2429	if (pPdeDst->n.u1Present)
2430	{
2431	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2432	const GSTPTE PteSrc = *pPteSrc;
2433
2434	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2435	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2436	* Our individual shadow handlers will provide more information and force a fatal exit.
2437	*/
2438	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2439	{
2440	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2441	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2442	}
2443	#endif
2444	/*
2445	* Map shadow page table.
2446	*/
2447	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2448	if (pShwPage)
2449	{
2450	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2451	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2452	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2453	{
2454	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2455	{
2456	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2457	SHWPTE PteDst = *pPteDst;
2458
2459	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2460	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2461
2462	Assert(PteSrc.n.u1Write);
2463
2464	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2465	* entry will not harm; write access will simply fault again and
2466	* take this path to only invalidate the entry.
2467	*/
2468	if (RT_LIKELY(pPage))
2469	{
2470	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2471	{
2472	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2473	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2474	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2475	SHW_PTE_SET_RO(PteDst);
2476	}
2477	else
2478	{
2479	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2480	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2481	{
2482	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2483	AssertRC(rc);
2484	}
2485	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2486	SHW_PTE_SET_RW(PteDst);
2487	else
2488	{
2489	/* Still applies to shared pages. */
2490	Assert(!PGM_PAGE_IS_ZERO(pPage));
2491	SHW_PTE_SET_RO(PteDst);
2492	}
2493	}
2494	}
2495	else
2496	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2497
2498	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2499	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2500	PGM_INVL_PG(pVCpu, GCPtrPage);
2501	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2502	}
2503
2504	# ifdef IN_RING0
2505	/* Check for stale TLB entry; only applies to the SMP guest case. */
2506	if ( pVM->cCpus > 1
2507	&& SHW_PTE_IS_RW(*pPteDst)
2508	&& SHW_PTE_IS_A(*pPteDst))
2509	{
2510	/* Stale TLB entry. */
2511	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2512	PGM_INVL_PG(pVCpu, GCPtrPage);
2513	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2514	}
2515	# endif
2516	}
2517	}
2518	else
2519	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2520	}
2521
2522	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2523	}
2524
2525	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2526
2527
2528	/**
2529	* Sync a shadow page table.
2530	*
2531	* The shadow page table is not present in the shadow PDE.
2532	*
2533	* Handles mapping conflicts.
2534	*
2535	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2536	* conflict), and Trap0eHandler.
2537	*
2538	* A precondition for this method is that the shadow PDE is not present. The
2539	* caller must take the PGM lock before checking this and continue to hold it
2540	* when calling this method.
2541	*
2542	* @returns VBox status code.
2543	* @param pVCpu Pointer to the VMCPU.
2544	* @param iPD Page directory index.
2545	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2546	* Assume this is a temporary mapping.
2547	* @param GCPtrPage GC Pointer of the page that caused the fault
2548	*/
2549	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2550	{
2551	PVM pVM = pVCpu->CTX_SUFF(pVM);
2552	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2553
2554	#if 0 /* rarely useful; leave for debugging. */
2555	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2556	#endif
2557	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2558
2559	PGM_LOCK_ASSERT_OWNER(pVM);
2560
2561	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2562	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2563	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2564	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2565	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2566
2567	int rc = VINF_SUCCESS;
2568
2569	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2570
2571	/*
2572	* Some input validation first.
2573	*/
2574	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2575
2576	/*
2577	* Get the relevant shadow PDE entry.
2578	*/
2579	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2580	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2581	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2582
2583	/* Fetch the pgm pool shadow descriptor. */
2584	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2585	Assert(pShwPde);
2586
2587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2588	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2589	PPGMPOOLPAGE pShwPde = NULL;
2590	PX86PDPAE pPDDst;
2591	PSHWPDE pPdeDst;
2592
2593	/* Fetch the pgm pool shadow descriptor. */
2594	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2595	AssertRCSuccessReturn(rc, rc);
2596	Assert(pShwPde);
2597
2598	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2599	pPdeDst = &pPDDst->a[iPDDst];
2600
2601	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2602	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2603	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2604	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2605	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2606	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2607	AssertRCSuccessReturn(rc, rc);
2608	Assert(pPDDst);
2609	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2610	# endif
2611	SHWPDE PdeDst = *pPdeDst;
2612
2613	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2614	/* Fetch the pgm pool shadow descriptor. */
2615	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2616	Assert(pShwPde);
2617	# endif
2618
2619	# ifndef PGM_WITHOUT_MAPPINGS
2620	/*
2621	* Check for conflicts.
2622	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2623	* R3: Simply resolve the conflict.
2624	*/
2625	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2626	{
2627	Assert(pgmMapAreMappingsEnabled(pVM));
2628	# ifndef IN_RING3
2629	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2630	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2631	return VERR_ADDRESS_CONFLICT;
2632
2633	# else /* IN_RING3 */
2634	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2635	Assert(pMapping);
2636	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2637	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2638	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2639	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2640	# else
2641	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2642	# endif
2643	if (RT_FAILURE(rc))
2644	{
2645	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2646	return rc;
2647	}
2648	PdeDst = *pPdeDst;
2649	# endif /* IN_RING3 */
2650	}
2651	# endif /* !PGM_WITHOUT_MAPPINGS */
2652	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2653
2654	/*
2655	* Sync the page directory entry.
2656	*/
2657	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2658	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2659	if ( PdeSrc.n.u1Present
2660	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2661	{
2662	/*
2663	* Allocate & map the page table.
2664	*/
2665	PSHWPT pPTDst;
2666	PPGMPOOLPAGE pShwPage;
2667	RTGCPHYS GCPhys;
2668	if (fPageTable)
2669	{
2670	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2671	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2672	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2673	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2674	# endif
2675	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2676	pShwPde->idx, iPDDst, false /fLockPage/,
2677	&pShwPage);
2678	}
2679	else
2680	{
2681	PGMPOOLACCESS enmAccess;
2682	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2683	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2684	# else
2685	const bool fNoExecute = false;
2686	# endif
2687
2688	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2689	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2690	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2691	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2692	# endif
2693	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2694	if (PdeSrc.n.u1User)
2695	{
2696	if (PdeSrc.n.u1Write)
2697	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2698	else
2699	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2700	}
2701	else
2702	{
2703	if (PdeSrc.n.u1Write)
2704	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2705	else
2706	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2707	}
2708	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2709	pShwPde->idx, iPDDst, false /fLockPage/,
2710	&pShwPage);
2711	}
2712	if (rc == VINF_SUCCESS)
2713	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2714	else if (rc == VINF_PGM_CACHED_PAGE)
2715	{
2716	/*
2717	* The PT was cached, just hook it up.
2718	*/
2719	if (fPageTable)
2720	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2721	else
2722	{
2723	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2724	/* (see explanation and assumptions further down.) */
2725	if ( !PdeSrc.b.u1Dirty
2726	&& PdeSrc.b.u1Write)
2727	{
2728	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2729	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2730	PdeDst.b.u1Write = 0;
2731	}
2732	}
2733	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2734	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2735	return VINF_SUCCESS;
2736	}
2737	else if (rc == VERR_PGM_POOL_FLUSHED)
2738	{
2739	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2740	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2741	return VINF_PGM_SYNC_CR3;
2742	}
2743	else
2744	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2745	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2746	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2747	* irrelevant at this point. */
2748	PdeDst.u &= X86_PDE_AVL_MASK;
2749	PdeDst.u \|= pShwPage->Core.Key;
2750
2751	/*
2752	* Page directory has been accessed (this is a fault situation, remember).
2753	*/
2754	/** @todo
2755	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2756	* fault situation. What's more, the Trap0eHandler has already set the
2757	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2758	* might need setting the accessed flag.
2759	*
2760	* The best idea is to leave this change to the caller and add an
2761	* assertion that it's set already. */
2762	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2763	if (fPageTable)
2764	{
2765	/*
2766	* Page table - 4KB.
2767	*
2768	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2769	*/
2770	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2771	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2772	PGSTPT pPTSrc;
2773	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2774	if (RT_SUCCESS(rc))
2775	{
2776	/*
2777	* Start by syncing the page directory entry so CSAM's TLB trick works.
2778	*/
2779	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2780	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2781	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2782	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2783
2784	/*
2785	* Directory/page user or supervisor privilege: (same goes for read/write)
2786	*
2787	* Directory Page Combined
2788	* U/S U/S U/S
2789	* 0 0 0
2790	* 0 1 0
2791	* 1 0 0
2792	* 1 1 1
2793	*
2794	* Simple AND operation. Table listed for completeness.
2795	*
2796	*/
2797	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2798	# ifdef PGM_SYNC_N_PAGES
2799	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2800	unsigned iPTDst = iPTBase;
2801	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2802	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2803	iPTDst = 0;
2804	else
2805	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2806	# else /* !PGM_SYNC_N_PAGES */
2807	unsigned iPTDst = 0;
2808	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2809	# endif /* !PGM_SYNC_N_PAGES */
2810	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2811	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2812	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2813	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2814	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2815	# else
2816	const unsigned offPTSrc = 0;
2817	# endif
2818	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2819	{
2820	const unsigned iPTSrc = iPTDst + offPTSrc;
2821	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2822
2823	if (PteSrc.n.u1Present)
2824	{
2825	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2826	/*
2827	* Assuming kernel code will be marked as supervisor - and not as user level
2828	* and executed using a conforming code selector - And marked as readonly.
2829	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2830	*/
2831	PPGMPAGE pPage;
2832	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2833	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2834	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2835	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2836	)
2837	# endif
2838	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2839	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2840	GCPtrCur,
2841	PteSrc.n.u1Present,
2842	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2843	PteSrc.n.u1User & PdeSrc.n.u1User,
2844	(uint64_t)PteSrc.u,
2845	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2846	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2847	}
2848	/* else: the page table was cleared by the pool */
2849	} /* for PTEs */
2850	}
2851	}
2852	else
2853	{
2854	/*
2855	* Big page - 2/4MB.
2856	*
2857	* We'll walk the ram range list in parallel and optimize lookups.
2858	* We will only sync one shadow page table at a time.
2859	*/
2860	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2861
2862	/**
2863	* @todo It might be more efficient to sync only a part of the 4MB
2864	* page (similar to what we do for 4KB PDs).
2865	*/
2866
2867	/*
2868	* Start by syncing the page directory entry.
2869	*/
2870	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2871	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2872
2873	/*
2874	* If the page is not flagged as dirty and is writable, then make it read-only
2875	* at PD level, so we can set the dirty bit when the page is modified.
2876	*
2877	* ASSUMES that page access handlers are implemented on page table entry level.
2878	* Thus we will first catch the dirty access and set PDE.D and restart. If
2879	* there is an access handler, we'll trap again and let it work on the problem.
2880	*/
2881	/** @todo move the above stuff to a section in the PGM documentation. */
2882	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2883	if ( !PdeSrc.b.u1Dirty
2884	&& PdeSrc.b.u1Write)
2885	{
2886	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2887	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2888	PdeDst.b.u1Write = 0;
2889	}
2890	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2891	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2892
2893	/*
2894	* Fill the shadow page table.
2895	*/
2896	/* Get address and flags from the source PDE. */
2897	SHWPTE PteDstBase;
2898	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2899
2900	/* Loop thru the entries in the shadow PT. */
2901	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2902	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2903	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2904	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2905	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2906	unsigned iPTDst = 0;
2907	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2908	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2909	{
2910	if (pRam && GCPhys >= pRam->GCPhys)
2911	{
2912	# ifndef PGM_WITH_A20
2913	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2914	# endif
2915	do
2916	{
2917	/* Make shadow PTE. */
2918	# ifdef PGM_WITH_A20
2919	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2920	# else
2921	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2922	# endif
2923	SHWPTE PteDst;
2924
2925	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2926	/* Try to make the page writable if necessary. */
2927	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2928	&& ( PGM_PAGE_IS_ZERO(pPage)
2929	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2930	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2931	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2932	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2933	# endif
2934	# ifdef VBOX_WITH_PAGE_SHARING
2935	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2936	# endif
2937	&& !PGM_PAGE_IS_BALLOONED(pPage))
2938	)
2939	)
2940	{
2941	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2942	AssertRCReturn(rc, rc);
2943	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2944	break;
2945	}
2946	# endif
2947
2948	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2949	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2950	else if (PGM_PAGE_IS_BALLOONED(pPage))
2951	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2952	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2953	/*
2954	* Assuming kernel code will be marked as supervisor and not as user level and executed
2955	* using a conforming code selector. Don't check for readonly, as that implies the whole
2956	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2957	*/
2958	else if ( !PdeSrc.n.u1User
2959	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2960	SHW_PTE_SET(PteDst, 0);
2961	# endif
2962	else
2963	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2964
2965	/* Only map writable pages writable. */
2966	if ( SHW_PTE_IS_P_RW(PteDst)
2967	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2968	{
2969	/* Still applies to shared pages. */
2970	Assert(!PGM_PAGE_IS_ZERO(pPage));
2971	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2972	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2973	}
2974
2975	if (SHW_PTE_IS_P(PteDst))
2976	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2977
2978	/* commit it (not atomic, new table) */
2979	pPTDst->a[iPTDst] = PteDst;
2980	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2981	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2982	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2983
2984	/* advance */
2985	GCPhys += PAGE_SIZE;
2986	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
2987	# ifndef PGM_WITH_A20
2988	iHCPage++;
2989	# endif
2990	iPTDst++;
2991	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2992	&& GCPhys <= pRam->GCPhysLast);
2993
2994	/* Advance ram range list. */
2995	while (pRam && GCPhys > pRam->GCPhysLast)
2996	pRam = pRam->CTX_SUFF(pNext);
2997	}
2998	else if (pRam)
2999	{
3000	Log(("Invalid pages at %RGp\n", GCPhys));
3001	do
3002	{
3003	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3004	GCPhys += PAGE_SIZE;
3005	iPTDst++;
3006	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3007	&& GCPhys < pRam->GCPhys);
3008	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3009	}
3010	else
3011	{
3012	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3013	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3014	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3015	}
3016	} /* while more PTEs */
3017	} /* 4KB / 4MB */
3018	}
3019	else
3020	AssertRelease(!PdeDst.n.u1Present);
3021
3022	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3023	if (RT_FAILURE(rc))
3024	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3025	return rc;
3026
3027	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3028	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3029	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3030	&& !defined(IN_RC)
3031	NOREF(iPDSrc); NOREF(pPDSrc);
3032
3033	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3034
3035	/*
3036	* Validate input a little bit.
3037	*/
3038	int rc = VINF_SUCCESS;
3039	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3040	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3041	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3042
3043	/* Fetch the pgm pool shadow descriptor. */
3044	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3045	Assert(pShwPde);
3046
3047	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3048	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3049	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3050	PX86PDPAE pPDDst;
3051	PSHWPDE pPdeDst;
3052
3053	/* Fetch the pgm pool shadow descriptor. */
3054	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3055	AssertRCSuccessReturn(rc, rc);
3056	Assert(pShwPde);
3057
3058	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3059	pPdeDst = &pPDDst->a[iPDDst];
3060
3061	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3062	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3063	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3064	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3065	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3066	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3067	AssertRCSuccessReturn(rc, rc);
3068	Assert(pPDDst);
3069	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3070
3071	/* Fetch the pgm pool shadow descriptor. */
3072	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3073	Assert(pShwPde);
3074
3075	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3076	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3077	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3078	PEPTPD pPDDst;
3079	PEPTPDPT pPdptDst;
3080
3081	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3082	if (rc != VINF_SUCCESS)
3083	{
3084	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3085	AssertRC(rc);
3086	return rc;
3087	}
3088	Assert(pPDDst);
3089	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3090
3091	/* Fetch the pgm pool shadow descriptor. */
3092	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3093	Assert(pShwPde);
3094	# endif
3095	SHWPDE PdeDst = *pPdeDst;
3096
3097	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3098	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3099
3100	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3101	if (BTH_IS_NP_ACTIVE(pVM))
3102	{
3103	/* Check if we allocated a big page before for this 2 MB range. */
3104	PPGMPAGE pPage;
3105	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3106	if (RT_SUCCESS(rc))
3107	{
3108	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3109	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3110	{
3111	if (PGM_A20_IS_ENABLED(pVCpu))
3112	{
3113	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3114	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3115	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3116	}
3117	else
3118	{
3119	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3120	pVM->pgm.s.cLargePagesDisabled++;
3121	}
3122	}
3123	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3124	&& PGM_A20_IS_ENABLED(pVCpu))
3125	{
3126	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3127	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3128	if (RT_SUCCESS(rc))
3129	{
3130	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3131	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3132	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3133	}
3134	}
3135	else if ( PGMIsUsingLargePages(pVM)
3136	&& PGM_A20_IS_ENABLED(pVCpu))
3137	{
3138	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3139	if (RT_SUCCESS(rc))
3140	{
3141	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3142	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3143	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3144	}
3145	else
3146	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3147	}
3148
3149	if (HCPhys != NIL_RTHCPHYS)
3150	{
3151	PdeDst.u &= X86_PDE_AVL_MASK;
3152	PdeDst.u \|= HCPhys;
3153	PdeDst.n.u1Present = 1;
3154	PdeDst.n.u1Write = 1;
3155	PdeDst.b.u1Size = 1;
3156	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3157	PdeDst.n.u1Execute = 1;
3158	PdeDst.b.u1IgnorePAT = 1;
3159	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3160	# else
3161	PdeDst.n.u1User = 1;
3162	# endif
3163	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3164
3165	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3166	/* Add a reference to the first page only. */
3167	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3168
3169	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3170	return VINF_SUCCESS;
3171	}
3172	}
3173	}
3174	# endif /* HC_ARCH_BITS == 64 */
3175
3176	/*
3177	* Allocate & map the page table.
3178	*/
3179	PSHWPT pPTDst;
3180	PPGMPOOLPAGE pShwPage;
3181	RTGCPHYS GCPhys;
3182
3183	/* Virtual address = physical address */
3184	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3185	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3186	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3187	&pShwPage);
3188	if ( rc == VINF_SUCCESS
3189	\|\| rc == VINF_PGM_CACHED_PAGE)
3190	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3191	else
3192	{
3193	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3194	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3195	}
3196
3197	if (rc == VINF_SUCCESS)
3198	{
3199	/* New page table; fully set it up. */
3200	Assert(pPTDst);
3201
3202	/* Mask away the page offset. */
3203	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3204
3205	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3206	{
3207	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3208	\| (iPTDst << PAGE_SHIFT));
3209
3210	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3211	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3212	GCPtrCurPage,
3213	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3214	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3215
3216	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3217	break;
3218	}
3219	}
3220	else
3221	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3222
3223	/* Save the new PDE. */
3224	PdeDst.u &= X86_PDE_AVL_MASK;
3225	PdeDst.u \|= pShwPage->Core.Key;
3226	PdeDst.n.u1Present = 1;
3227	PdeDst.n.u1Write = 1;
3228	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3229	PdeDst.n.u1Execute = 1;
3230	# else
3231	PdeDst.n.u1User = 1;
3232	PdeDst.n.u1Accessed = 1;
3233	# endif
3234	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3235
3236	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3237	if (RT_FAILURE(rc))
3238	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3239	return rc;
3240
3241	#else
3242	NOREF(iPDSrc); NOREF(pPDSrc);
3243	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3244	return VERR_PGM_NOT_USED_IN_MODE;
3245	#endif
3246	}
3247
3248
3249
3250	/**
3251	* Prefetch a page/set of pages.
3252	*
3253	* Typically used to sync commonly used pages before entering raw mode
3254	* after a CR3 reload.
3255	*
3256	* @returns VBox status code.
3257	* @param pVCpu Pointer to the VMCPU.
3258	* @param GCPtrPage Page to invalidate.
3259	*/
3260	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3261	{
3262	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3263	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3264	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3265	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3266	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3267	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3268	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3269
3270	/*
3271	* Check that all Guest levels thru the PDE are present, getting the
3272	* PD and PDE in the processes.
3273	*/
3274	int rc = VINF_SUCCESS;
3275	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3276	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3277	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3278	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3279	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3280	unsigned iPDSrc;
3281	X86PDPE PdpeSrc;
3282	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3283	if (!pPDSrc)
3284	return VINF_SUCCESS; /* not present */
3285	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3286	unsigned iPDSrc;
3287	PX86PML4E pPml4eSrc;
3288	X86PDPE PdpeSrc;
3289	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3290	if (!pPDSrc)
3291	return VINF_SUCCESS; /* not present */
3292	# endif
3293	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3294	# else
3295	PGSTPD pPDSrc = NULL;
3296	const unsigned iPDSrc = 0;
3297	GSTPDE PdeSrc;
3298
3299	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3300	PdeSrc.n.u1Present = 1;
3301	PdeSrc.n.u1Write = 1;
3302	PdeSrc.n.u1Accessed = 1;
3303	PdeSrc.n.u1User = 1;
3304	# endif
3305
3306	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3307	{
3308	PVM pVM = pVCpu->CTX_SUFF(pVM);
3309	pgmLock(pVM);
3310
3311	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3312	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3313	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3314	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3315	PX86PDPAE pPDDst;
3316	X86PDEPAE PdeDst;
3317	# if PGM_GST_TYPE != PGM_TYPE_PAE
3318	X86PDPE PdpeSrc;
3319
3320	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3321	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3322	# endif
3323	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3324	if (rc != VINF_SUCCESS)
3325	{
3326	pgmUnlock(pVM);
3327	AssertRC(rc);
3328	return rc;
3329	}
3330	Assert(pPDDst);
3331	PdeDst = pPDDst->a[iPDDst];
3332
3333	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3334	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3335	PX86PDPAE pPDDst;
3336	X86PDEPAE PdeDst;
3337
3338	# if PGM_GST_TYPE == PGM_TYPE_PROT
3339	/* AMD-V nested paging */
3340	X86PML4E Pml4eSrc;
3341	X86PDPE PdpeSrc;
3342	PX86PML4E pPml4eSrc = &Pml4eSrc;
3343
3344	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3345	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3346	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3347	# endif
3348
3349	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3350	if (rc != VINF_SUCCESS)
3351	{
3352	pgmUnlock(pVM);
3353	AssertRC(rc);
3354	return rc;
3355	}
3356	Assert(pPDDst);
3357	PdeDst = pPDDst->a[iPDDst];
3358	# endif
3359	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3360	{
3361	if (!PdeDst.n.u1Present)
3362	{
3363	/** @todo r=bird: This guy will set the A bit on the PDE,
3364	* probably harmless. */
3365	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3366	}
3367	else
3368	{
3369	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3370	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3371	* makes no sense to prefetch more than one page.
3372	*/
3373	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3374	if (RT_SUCCESS(rc))
3375	rc = VINF_SUCCESS;
3376	}
3377	}
3378	pgmUnlock(pVM);
3379	}
3380	return rc;
3381
3382	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3383	NOREF(pVCpu); NOREF(GCPtrPage);
3384	return VINF_SUCCESS; /* ignore */
3385	#else
3386	AssertCompile(0);
3387	#endif
3388	}
3389
3390
3391
3392
3393	/**
3394	* Syncs a page during a PGMVerifyAccess() call.
3395	*
3396	* @returns VBox status code (informational included).
3397	* @param pVCpu Pointer to the VMCPU.
3398	* @param GCPtrPage The address of the page to sync.
3399	* @param fPage The effective guest page flags.
3400	* @param uErr The trap error code.
3401	* @remarks This will normally never be called on invalid guest page
3402	* translation entries.
3403	*/
3404	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3405	{
3406	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3407
3408	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3409
3410	Assert(!pVM->pgm.s.fNestedPaging);
3411	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3412	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3413	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3414	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3415	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3416	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3417	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3418
3419	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3420	if (!(fPage & X86_PTE_US))
3421	{
3422	/*
3423	* Mark this page as safe.
3424	*/
3425	/** @todo not correct for pages that contain both code and data!! */
3426	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3427	CSAMMarkPage(pVM, GCPtrPage, true);
3428	}
3429	# endif
3430
3431	/*
3432	* Get guest PD and index.
3433	*/
3434	/** @todo Performance: We've done all this a jiffy ago in the
3435	* PGMGstGetPage call. */
3436	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3437	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3438	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3439	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3440
3441	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3442	unsigned iPDSrc = 0;
3443	X86PDPE PdpeSrc;
3444	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3445	if (RT_UNLIKELY(!pPDSrc))
3446	{
3447	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3448	return VINF_EM_RAW_GUEST_TRAP;
3449	}
3450
3451	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3452	unsigned iPDSrc = 0; /* shut up gcc */
3453	PX86PML4E pPml4eSrc = NULL; /* ditto */
3454	X86PDPE PdpeSrc;
3455	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3456	if (RT_UNLIKELY(!pPDSrc))
3457	{
3458	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3459	return VINF_EM_RAW_GUEST_TRAP;
3460	}
3461	# endif
3462
3463	# else /* !PGM_WITH_PAGING */
3464	PGSTPD pPDSrc = NULL;
3465	const unsigned iPDSrc = 0;
3466	# endif /* !PGM_WITH_PAGING */
3467	int rc = VINF_SUCCESS;
3468
3469	pgmLock(pVM);
3470
3471	/*
3472	* First check if the shadow pd is present.
3473	*/
3474	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3475	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3476
3477	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3478	PX86PDEPAE pPdeDst;
3479	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3480	PX86PDPAE pPDDst;
3481	# if PGM_GST_TYPE != PGM_TYPE_PAE
3482	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3483	X86PDPE PdpeSrc;
3484	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3485	# endif
3486	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3487	if (rc != VINF_SUCCESS)
3488	{
3489	pgmUnlock(pVM);
3490	AssertRC(rc);
3491	return rc;
3492	}
3493	Assert(pPDDst);
3494	pPdeDst = &pPDDst->a[iPDDst];
3495
3496	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3497	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3498	PX86PDPAE pPDDst;
3499	PX86PDEPAE pPdeDst;
3500
3501	# if PGM_GST_TYPE == PGM_TYPE_PROT
3502	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3503	X86PML4E Pml4eSrc;
3504	X86PDPE PdpeSrc;
3505	PX86PML4E pPml4eSrc = &Pml4eSrc;
3506	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3507	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3508	# endif
3509
3510	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3511	if (rc != VINF_SUCCESS)
3512	{
3513	pgmUnlock(pVM);
3514	AssertRC(rc);
3515	return rc;
3516	}
3517	Assert(pPDDst);
3518	pPdeDst = &pPDDst->a[iPDDst];
3519	# endif
3520
3521	if (!pPdeDst->n.u1Present)
3522	{
3523	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3524	if (rc != VINF_SUCCESS)
3525	{
3526	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3527	pgmUnlock(pVM);
3528	AssertRC(rc);
3529	return rc;
3530	}
3531	}
3532
3533	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3534	/* Check for dirty bit fault */
3535	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3536	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3537	Log(("PGMVerifyAccess: success (dirty)\n"));
3538	else
3539	# endif
3540	{
3541	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3542	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3543	# else
3544	GSTPDE PdeSrc;
3545	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3546	PdeSrc.n.u1Present = 1;
3547	PdeSrc.n.u1Write = 1;
3548	PdeSrc.n.u1Accessed = 1;
3549	PdeSrc.n.u1User = 1;
3550	# endif
3551
3552	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3553	if (uErr & X86_TRAP_PF_US)
3554	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3555	else /* supervisor */
3556	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3557
3558	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3559	if (RT_SUCCESS(rc))
3560	{
3561	/* Page was successfully synced */
3562	Log2(("PGMVerifyAccess: success (sync)\n"));
3563	rc = VINF_SUCCESS;
3564	}
3565	else
3566	{
3567	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3568	rc = VINF_EM_RAW_GUEST_TRAP;
3569	}
3570	}
3571	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3572	pgmUnlock(pVM);
3573	return rc;
3574
3575	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3576
3577	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3578	return VERR_PGM_NOT_USED_IN_MODE;
3579	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3580	}
3581
3582
3583	/**
3584	* Syncs the paging hierarchy starting at CR3.
3585	*
3586	* @returns VBox status code, no specials.
3587	* @param pVCpu Pointer to the VMCPU.
3588	* @param cr0 Guest context CR0 register.
3589	* @param cr3 Guest context CR3 register. Not subjected to the A20
3590	* mask.
3591	* @param cr4 Guest context CR4 register.
3592	* @param fGlobal Including global page directories or not
3593	*/
3594	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3595	{
3596	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3597	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3598
3599	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3600
3601	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3602
3603	pgmLock(pVM);
3604
3605	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3606	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3607	if (pPool->cDirtyPages)
3608	pgmPoolResetDirtyPages(pVM);
3609	# endif
3610
3611	/*
3612	* Update page access handlers.
3613	* The virtual are always flushed, while the physical are only on demand.
3614	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3615	* have to look into that later because it will have a bad influence on the performance.
3616	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3617	* bird: Yes, but that won't work for aliases.
3618	*/
3619	/** @todo this MUST go away. See @bugref{1557}. */
3620	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3621	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3622	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3623	pgmUnlock(pVM);
3624	#endif /* !NESTED && !EPT */
3625
3626	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3627	/*
3628	* Nested / EPT - almost no work.
3629	*/
3630	Assert(!pgmMapAreMappingsEnabled(pVM));
3631	return VINF_SUCCESS;
3632
3633	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3634	/*
3635	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3636	* out the shadow parts when the guest modifies its tables.
3637	*/
3638	Assert(!pgmMapAreMappingsEnabled(pVM));
3639	return VINF_SUCCESS;
3640
3641	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3642
3643	# ifndef PGM_WITHOUT_MAPPINGS
3644	/*
3645	* Check for and resolve conflicts with our guest mappings if they
3646	* are enabled and not fixed.
3647	*/
3648	if (pgmMapAreMappingsFloating(pVM))
3649	{
3650	int rc = pgmMapResolveConflicts(pVM);
3651	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3652	if (rc == VINF_PGM_SYNC_CR3)
3653	{
3654	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3655	return VINF_PGM_SYNC_CR3;
3656	}
3657	}
3658	# else
3659	Assert(!pgmMapAreMappingsEnabled(pVM));
3660	# endif
3661	return VINF_SUCCESS;
3662	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3663	}
3664
3665
3666
3667
3668	#ifdef VBOX_STRICT
3669	# ifdef IN_RC
3670	# undef AssertMsgFailed
3671	# define AssertMsgFailed Log
3672	# endif
3673
3674	/**
3675	* Checks that the shadow page table is in sync with the guest one.
3676	*
3677	* @returns The number of errors.
3678	* @param pVM The virtual machine.
3679	* @param pVCpu Pointer to the VMCPU.
3680	* @param cr3 Guest context CR3 register.
3681	* @param cr4 Guest context CR4 register.
3682	* @param GCPtr Where to start. Defaults to 0.
3683	* @param cb How much to check. Defaults to everything.
3684	*/
3685	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3686	{
3687	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3688	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3689	return 0;
3690	#else
3691	unsigned cErrors = 0;
3692	PVM pVM = pVCpu->CTX_SUFF(pVM);
3693	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3694
3695	# if PGM_GST_TYPE == PGM_TYPE_PAE
3696	/** @todo currently broken; crashes below somewhere */
3697	AssertFailed();
3698	# endif
3699
3700	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3701	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3702	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3703
3704	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3705	PPGMCPU pPGM = &pVCpu->pgm.s;
3706	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3707	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3708	# ifndef IN_RING0
3709	RTHCPHYS HCPhys; /* general usage. */
3710	# endif
3711	int rc;
3712
3713	/*
3714	* Check that the Guest CR3 and all its mappings are correct.
3715	*/
3716	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3717	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3718	false);
3719	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3720	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3721	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3722	# else
3723	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3724	# endif
3725	AssertRCReturn(rc, 1);
3726	HCPhys = NIL_RTHCPHYS;
3727	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3728	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3729	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3730	pgmGstGet32bitPDPtr(pVCpu);
3731	RTGCPHYS GCPhys;
3732	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3733	AssertRCReturn(rc, 1);
3734	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3735	# endif
3736	# endif /* !IN_RING0 */
3737
3738	/*
3739	* Get and check the Shadow CR3.
3740	*/
3741	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3742	unsigned cPDEs = X86_PG_ENTRIES;
3743	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3744	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3745	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3746	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3747	# else
3748	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3749	# endif
3750	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3751	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3752	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3753	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3754	# endif
3755	if (cb != ~(RTGCPTR)0)
3756	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3757
3758	/** @todo call the other two PGMAssert() functions. /
3759
3760	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3761	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3762
3763	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3764	{
3765	PPGMPOOLPAGE pShwPdpt = NULL;
3766	PX86PML4E pPml4eSrc;
3767	PX86PML4E pPml4eDst;
3768	RTGCPHYS GCPhysPdptSrc;
3769
3770	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3771	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3772
3773	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3774	if (!pPml4eDst->n.u1Present)
3775	{
3776	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3777	continue;
3778	}
3779
3780	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3781	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3782
3783	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3784	{
3785	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3786	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3787	cErrors++;
3788	continue;
3789	}
3790
3791	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3792	{
3793	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3794	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3795	cErrors++;
3796	continue;
3797	}
3798
3799	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3800	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3801	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3802	{
3803	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3804	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3805	cErrors++;
3806	continue;
3807	}
3808	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3809	{
3810	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3811
3812	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3813	/*
3814	* Check the PDPTEs too.
3815	*/
3816	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3817
3818	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3819	{
3820	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3821	PPGMPOOLPAGE pShwPde = NULL;
3822	PX86PDPE pPdpeDst;
3823	RTGCPHYS GCPhysPdeSrc;
3824	X86PDPE PdpeSrc;
3825	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3826	# if PGM_GST_TYPE == PGM_TYPE_PAE
3827	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3828	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3829	# else
3830	PX86PML4E pPml4eSrcIgn;
3831	PX86PDPT pPdptDst;
3832	PX86PDPAE pPDDst;
3833	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3834
3835	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3836	if (rc != VINF_SUCCESS)
3837	{
3838	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3839	GCPtr += 512 * _2M;
3840	continue; /* next PDPTE */
3841	}
3842	Assert(pPDDst);
3843	# endif
3844	Assert(iPDSrc == 0);
3845
3846	pPdpeDst = &pPdptDst->a[iPdpt];
3847
3848	if (!pPdpeDst->n.u1Present)
3849	{
3850	GCPtr += 512 * _2M;
3851	continue; /* next PDPTE */
3852	}
3853
3854	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3855	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3856
3857	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3858	{
3859	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3860	GCPtr += 512 * _2M;
3861	cErrors++;
3862	continue;
3863	}
3864
3865	if (GCPhysPdeSrc != pShwPde->GCPhys)
3866	{
3867	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3868	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3869	# else
3870	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3871	# endif
3872	GCPtr += 512 * _2M;
3873	cErrors++;
3874	continue;
3875	}
3876
3877	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3878	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3879	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3880	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3881	{
3882	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3883	GCPtr += 512 * _2M;
3884	cErrors++;
3885	continue;
3886	}
3887	# endif
3888
3889	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3890	{
3891	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3892	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3893	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3894	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3895	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3896	# endif
3897	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3898	/*
3899	* Iterate the shadow page directory.
3900	*/
3901	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3902	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3903
3904	for (;
3905	iPDDst < cPDEs;
3906	iPDDst++, GCPtr += cIncrement)
3907	{
3908	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3909	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3910	# else
3911	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3912	# endif
3913	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3914	{
3915	Assert(pgmMapAreMappingsEnabled(pVM));
3916	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3917	{
3918	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3919	cErrors++;
3920	continue;
3921	}
3922	}
3923	else if ( (PdeDst.u & X86_PDE_P)
3924	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3925	)
3926	{
3927	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3928	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3929	if (!pPoolPage)
3930	{
3931	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3932	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3933	cErrors++;
3934	continue;
3935	}
3936	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3937
3938	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3939	{
3940	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3941	GCPtr, (uint64_t)PdeDst.u));
3942	cErrors++;
3943	}
3944
3945	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3946	{
3947	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3948	GCPtr, (uint64_t)PdeDst.u));
3949	cErrors++;
3950	}
3951
3952	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3953	if (!PdeSrc.n.u1Present)
3954	{
3955	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3956	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3957	cErrors++;
3958	continue;
3959	}
3960
3961	if ( !PdeSrc.b.u1Size
3962	\|\| !fBigPagesSupported)
3963	{
3964	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3965	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3966	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
3967	# endif
3968	}
3969	else
3970	{
3971	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3972	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3973	{
3974	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3975	GCPtr, (uint64_t)PdeSrc.u));
3976	cErrors++;
3977	continue;
3978	}
3979	# endif
3980	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3981	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3982	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
3983	# endif
3984	}
3985
3986	if ( pPoolPage->enmKind
3987	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3988	{
3989	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3990	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3991	cErrors++;
3992	}
3993
3994	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3995	if (!pPhysPage)
3996	{
3997	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3998	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3999	cErrors++;
4000	continue;
4001	}
4002
4003	if (GCPhysGst != pPoolPage->GCPhys)
4004	{
4005	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4006	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4007	cErrors++;
4008	continue;
4009	}
4010
4011	if ( !PdeSrc.b.u1Size
4012	\|\| !fBigPagesSupported)
4013	{
4014	/*
4015	* Page Table.
4016	*/
4017	const GSTPT *pPTSrc;
4018	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4019	&pPTSrc);
4020	if (RT_FAILURE(rc))
4021	{
4022	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4023	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4024	cErrors++;
4025	continue;
4026	}
4027	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4028	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4029	{
4030	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4031	// (This problem will go away when/if we shadow multiple CR3s.)
4032	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4033	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4034	cErrors++;
4035	continue;
4036	}
4037	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4038	{
4039	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4040	GCPtr, (uint64_t)PdeDst.u));
4041	cErrors++;
4042	continue;
4043	}
4044
4045	/* iterate the page table. */
4046	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4047	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4048	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4049	# else
4050	const unsigned offPTSrc = 0;
4051	# endif
4052	for (unsigned iPT = 0, off = 0;
4053	iPT < RT_ELEMENTS(pPTDst->a);
4054	iPT++, off += PAGE_SIZE)
4055	{
4056	const SHWPTE PteDst = pPTDst->a[iPT];
4057
4058	/* skip not-present and dirty tracked entries. */
4059	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4060	continue;
4061	Assert(SHW_PTE_IS_P(PteDst));
4062
4063	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4064	if (!PteSrc.n.u1Present)
4065	{
4066	# ifdef IN_RING3
4067	PGMAssertHandlerAndFlagsInSync(pVM);
4068	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4069	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4070	0, 0, UINT64_MAX, 99, NULL);
4071	# endif
4072	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4073	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4074	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4075	cErrors++;
4076	continue;
4077	}
4078
4079	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4080	# if 1 /** @todo sync accessed bit properly... */
4081	fIgnoreFlags \|= X86_PTE_A;
4082	# endif
4083
4084	/* match the physical addresses */
4085	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4086	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4087
4088	# ifdef IN_RING3
4089	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4090	if (RT_FAILURE(rc))
4091	{
4092	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4093	{
4094	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4095	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4096	cErrors++;
4097	continue;
4098	}
4099	}
4100	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4101	{
4102	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4103	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4104	cErrors++;
4105	continue;
4106	}
4107	# endif
4108
4109	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4110	if (!pPhysPage)
4111	{
4112	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4113	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4114	{
4115	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4116	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4117	cErrors++;
4118	continue;
4119	}
4120	# endif
4121	if (SHW_PTE_IS_RW(PteDst))
4122	{
4123	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4124	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4125	cErrors++;
4126	}
4127	fIgnoreFlags \|= X86_PTE_RW;
4128	}
4129	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4130	{
4131	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4132	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4133	cErrors++;
4134	continue;
4135	}
4136
4137	/* flags */
4138	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4139	{
4140	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4141	{
4142	if (SHW_PTE_IS_RW(PteDst))
4143	{
4144	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4145	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4146	cErrors++;
4147	continue;
4148	}
4149	fIgnoreFlags \|= X86_PTE_RW;
4150	}
4151	else
4152	{
4153	if ( SHW_PTE_IS_P(PteDst)
4154	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4155	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4156	# endif
4157	)
4158	{
4159	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4160	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4161	cErrors++;
4162	continue;
4163	}
4164	fIgnoreFlags \|= X86_PTE_P;
4165	}
4166	}
4167	else
4168	{
4169	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4170	{
4171	if (SHW_PTE_IS_RW(PteDst))
4172	{
4173	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4174	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4175	cErrors++;
4176	continue;
4177	}
4178	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4179	{
4180	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4181	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4182	cErrors++;
4183	continue;
4184	}
4185	if (SHW_PTE_IS_D(PteDst))
4186	{
4187	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4188	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4189	cErrors++;
4190	}
4191	# if 0 /** @todo sync access bit properly... */
4192	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4193	{
4194	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4195	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4196	cErrors++;
4197	}
4198	fIgnoreFlags \|= X86_PTE_RW;
4199	# else
4200	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4201	# endif
4202	}
4203	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4204	{
4205	/* access bit emulation (not implemented). */
4206	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4207	{
4208	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4209	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4210	cErrors++;
4211	continue;
4212	}
4213	if (!SHW_PTE_IS_A(PteDst))
4214	{
4215	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4216	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4217	cErrors++;
4218	}
4219	fIgnoreFlags \|= X86_PTE_P;
4220	}
4221	# ifdef DEBUG_sandervl
4222	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4223	# endif
4224	}
4225
4226	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4227	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4228	)
4229	{
4230	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4231	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4232	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4233	cErrors++;
4234	continue;
4235	}
4236	} /* foreach PTE */
4237	}
4238	else
4239	{
4240	/*
4241	* Big Page.
4242	*/
4243	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4244	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4245	{
4246	if (PdeDst.n.u1Write)
4247	{
4248	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4249	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4250	cErrors++;
4251	continue;
4252	}
4253	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4254	{
4255	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4256	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4257	cErrors++;
4258	continue;
4259	}
4260	# if 0 /** @todo sync access bit properly... */
4261	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4262	{
4263	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4264	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4265	cErrors++;
4266	}
4267	fIgnoreFlags \|= X86_PTE_RW;
4268	# else
4269	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4270	# endif
4271	}
4272	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4273	{
4274	/* access bit emulation (not implemented). */
4275	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4276	{
4277	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4278	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4279	cErrors++;
4280	continue;
4281	}
4282	if (!PdeDst.n.u1Accessed)
4283	{
4284	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4285	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4286	cErrors++;
4287	}
4288	fIgnoreFlags \|= X86_PTE_P;
4289	}
4290
4291	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4292	{
4293	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4294	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4295	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4296	cErrors++;
4297	}
4298
4299	/* iterate the page table. */
4300	for (unsigned iPT = 0, off = 0;
4301	iPT < RT_ELEMENTS(pPTDst->a);
4302	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4303	{
4304	const SHWPTE PteDst = pPTDst->a[iPT];
4305
4306	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4307	{
4308	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4309	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4310	cErrors++;
4311	}
4312
4313	/* skip not-present entries. */
4314	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4315	continue;
4316
4317	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4318
4319	/* match the physical addresses */
4320	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4321
4322	# ifdef IN_RING3
4323	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4324	if (RT_FAILURE(rc))
4325	{
4326	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4327	{
4328	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4329	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4330	cErrors++;
4331	}
4332	}
4333	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4334	{
4335	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4336	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4337	cErrors++;
4338	continue;
4339	}
4340	# endif
4341	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4342	if (!pPhysPage)
4343	{
4344	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4345	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4346	{
4347	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4348	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4349	cErrors++;
4350	continue;
4351	}
4352	# endif
4353	if (SHW_PTE_IS_RW(PteDst))
4354	{
4355	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4356	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4357	cErrors++;
4358	}
4359	fIgnoreFlags \|= X86_PTE_RW;
4360	}
4361	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4362	{
4363	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4364	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4365	cErrors++;
4366	continue;
4367	}
4368
4369	/* flags */
4370	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4371	{
4372	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4373	{
4374	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4375	{
4376	if (SHW_PTE_IS_RW(PteDst))
4377	{
4378	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4379	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4380	cErrors++;
4381	continue;
4382	}
4383	fIgnoreFlags \|= X86_PTE_RW;
4384	}
4385	}
4386	else
4387	{
4388	if ( SHW_PTE_IS_P(PteDst)
4389	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4390	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4391	# endif
4392	)
4393	{
4394	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4395	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4396	cErrors++;
4397	continue;
4398	}
4399	fIgnoreFlags \|= X86_PTE_P;
4400	}
4401	}
4402
4403	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4404	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4405	)
4406	{
4407	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4408	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4409	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4410	cErrors++;
4411	continue;
4412	}
4413	} /* for each PTE */
4414	}
4415	}
4416	/* not present */
4417
4418	} /* for each PDE */
4419
4420	} /* for each PDPTE */
4421
4422	} /* for each PML4E */
4423
4424	# ifdef DEBUG
4425	if (cErrors)
4426	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4427	# endif
4428	# endif /* GST is in {32BIT, PAE, AMD64} */
4429	return cErrors;
4430	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4431	}
4432	#endif /* VBOX_STRICT */
4433
4434
4435	/**
4436	* Sets up the CR3 for shadow paging
4437	*
4438	* @returns Strict VBox status code.
4439	* @retval VINF_SUCCESS.
4440	*
4441	* @param pVCpu Pointer to the VMCPU.
4442	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4443	* mask already applied.)
4444	*/
4445	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4446	{
4447	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4448
4449	/* Update guest paging info. */
4450	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4451	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4452	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4453
4454	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4455	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4456
4457	/*
4458	* Map the page CR3 points at.
4459	*/
4460	RTHCPTR HCPtrGuestCR3;
4461	RTHCPHYS HCPhysGuestCR3;
4462	pgmLock(pVM);
4463	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4464	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4465	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4466	/** @todo this needs some reworking wrt. locking? */
4467	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4468	HCPtrGuestCR3 = NIL_RTHCPTR;
4469	int rc = VINF_SUCCESS;
4470	# else
4471	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4472	# endif
4473	pgmUnlock(pVM);
4474	if (RT_SUCCESS(rc))
4475	{
4476	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4477	if (RT_SUCCESS(rc))
4478	{
4479	# ifdef IN_RC
4480	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4481	# endif
4482	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4483	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4484	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4485	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4486	# endif
4487	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4488
4489	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4490	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4491	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4492	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4493	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4494	# endif
4495	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4496	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4497
4498	/*
4499	* Map the 4 PDs too.
4500	*/
4501	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4502	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4503	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4504	{
4505	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4506	if (pGuestPDPT->a[i].n.u1Present)
4507	{
4508	RTHCPTR HCPtr;
4509	RTHCPHYS HCPhys;
4510	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4511	pgmLock(pVM);
4512	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4513	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4514	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4515	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4516	HCPtr = NIL_RTHCPTR;
4517	int rc2 = VINF_SUCCESS;
4518	# else
4519	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4520	# endif
4521	pgmUnlock(pVM);
4522	if (RT_SUCCESS(rc2))
4523	{
4524	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4525	AssertRCReturn(rc, rc);
4526
4527	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4528	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4529	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4530	# endif
4531	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4532	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4533	# ifdef IN_RC
4534	PGM_INVL_PG(pVCpu, GCPtr);
4535	# endif
4536	continue;
4537	}
4538	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4539	}
4540
4541	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4542	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4543	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4544	# endif
4545	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4546	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4547	# ifdef IN_RC
4548	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4549	# endif
4550	}
4551
4552	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4553	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4554	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4555	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4556	# endif
4557	# endif
4558	}
4559	else
4560	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4561	}
4562	else
4563	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4564
4565	#else /* prot/real stub */
4566	int rc = VINF_SUCCESS;
4567	#endif
4568
4569	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4570	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4571	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4572	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4573	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4574	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4575
4576	Assert(!pVM->pgm.s.fNestedPaging);
4577	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4578
4579	/*
4580	* Update the shadow root page as well since that's not fixed.
4581	*/
4582	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4583	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4584	uint32_t iOldShwUserTable = pVCpu->pgm.s.iShwUserTable;
4585	uint32_t iOldShwUser = pVCpu->pgm.s.iShwUser;
4586	PPGMPOOLPAGE pNewShwPageCR3;
4587
4588	pgmLock(pVM);
4589
4590	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4591	if (pPool->cDirtyPages)
4592	pgmPoolResetDirtyPages(pVM);
4593	# endif
4594
4595	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4596	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4597	SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, true /fLockPage/,
4598	&pNewShwPageCR3);
4599	AssertFatalRC(rc);
4600	rc = VINF_SUCCESS;
4601
4602	# ifdef IN_RC
4603	/*
4604	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4605	* state will be inconsistent! Flush important things now while
4606	* we still can and then make sure there are no ring-3 calls.
4607	*/
4608	# ifdef VBOX_WITH_REM
4609	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4610	# endif
4611	VMMRZCallRing3Disable(pVCpu);
4612	# endif
4613
4614	pVCpu->pgm.s.iShwUser = SHW_POOL_ROOT_IDX;
4615	pVCpu->pgm.s.iShwUserTable = GCPhysCR3 >> PAGE_SHIFT;
4616	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4617	# ifdef IN_RING0
4618	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4619	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4620	# elif defined(IN_RC)
4621	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4622	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4623	# else
4624	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4625	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4626	# endif
4627
4628	# ifndef PGM_WITHOUT_MAPPINGS
4629	/*
4630	* Apply all hypervisor mappings to the new CR3.
4631	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4632	* make sure we check for conflicts in the new CR3 root.
4633	*/
4634	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4635	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4636	# endif
4637	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4638	AssertRCReturn(rc, rc);
4639	# endif
4640
4641	/* Set the current hypervisor CR3. */
4642	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4643	SELMShadowCR3Changed(pVM, pVCpu);
4644
4645	# ifdef IN_RC
4646	/* NOTE: The state is consistent again. */
4647	VMMRZCallRing3Enable(pVCpu);
4648	# endif
4649
4650	/* Clean up the old CR3 root. */
4651	if ( pOldShwPageCR3
4652	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4653	{
4654	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4655	# ifndef PGM_WITHOUT_MAPPINGS
4656	/* Remove the hypervisor mappings from the shadow page table. */
4657	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4658	# endif
4659	/* Mark the page as unlocked; allow flushing again. */
4660	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4661
4662	pgmPoolFreeByPage(pPool, pOldShwPageCR3, iOldShwUser, iOldShwUserTable);
4663	}
4664	pgmUnlock(pVM);
4665	# else
4666	NOREF(GCPhysCR3);
4667	# endif
4668
4669	return rc;
4670	}
4671
4672	/**
4673	* Unmaps the shadow CR3.
4674	*
4675	* @returns VBox status, no specials.
4676	* @param pVCpu Pointer to the VMCPU.
4677	*/
4678	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4679	{
4680	LogFlow(("UnmapCR3\n"));
4681
4682	int rc = VINF_SUCCESS;
4683	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4684
4685	/*
4686	* Update guest paging info.
4687	*/
4688	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4689	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4690	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4691	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4692	# endif
4693	pVCpu->pgm.s.pGst32BitPdRC = 0;
4694
4695	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4696	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4697	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4698	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4699	# endif
4700	pVCpu->pgm.s.pGstPaePdptRC = 0;
4701	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4702	{
4703	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4704	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4705	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4706	# endif
4707	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4708	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4709	}
4710
4711	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4712	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4713	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4714	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4715	# endif
4716
4717	#else /* prot/real mode stub */
4718	/* nothing to do */
4719	#endif
4720
4721	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4722	/*
4723	* Update shadow paging info.
4724	*/
4725	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4726	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4727	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4728
4729	# if PGM_GST_TYPE != PGM_TYPE_REAL
4730	Assert(!pVM->pgm.s.fNestedPaging);
4731	# endif
4732
4733	pgmLock(pVM);
4734
4735	# ifndef PGM_WITHOUT_MAPPINGS
4736	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4737	/* Remove the hypervisor mappings from the shadow page table. */
4738	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4739	# endif
4740
4741	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4742	{
4743	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4744
4745	Assert(pVCpu->pgm.s.iShwUser != PGMPOOL_IDX_NESTED_ROOT);
4746
4747	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4748	if (pPool->cDirtyPages)
4749	pgmPoolResetDirtyPages(pVM);
4750	# endif
4751
4752	/* Mark the page as unlocked; allow flushing again. */
4753	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4754
4755	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), pVCpu->pgm.s.iShwUser, pVCpu->pgm.s.iShwUserTable);
4756	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4757	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4758	pVCpu->pgm.s.pShwPageCR3RC = 0;
4759	pVCpu->pgm.s.iShwUser = 0;
4760	pVCpu->pgm.s.iShwUserTable = 0;
4761	}
4762	pgmUnlock(pVM);
4763	# endif
4764	#endif /* !IN_RC*/
4765
4766	return rc;
4767	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 44577

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