PGMAllBth.h@ 45312

Last change on this file since 45312 was 45276, checked in by vboxsync, 12 years ago

Ring-1 compression patches, courtesy of trivirt AG:

main: diff to remove the hwvirt requirement for QNX
rem: diff for dealing with raw ring 0/1 selectors and general changes to allowed guest execution states
vmm: changes for using the guest's TSS selector index as our hypervisor TSS selector (makes str safe) (VBOX_WITH_SAFE_STR )
vmm: changes for dealing with guest ring 1 code (VBOX_WITH_RAW_RING1)
vmm: change to emulate smsw in RC/R0 (QNX uses this old style instruction a lot so going to qemu for emulation is very expensive)
vmm: change (hack) to kick out patm virtual handlers in case they conflict with guest GDT/TSS write monitors; we should allow multiple handlers per page, but that change would be rather invasive

Property svn:eol-style set to native
Property svn:keywords set to Id

File size: 204.9 KB

Line
1	/* $Id: PGMAllBth.h 45276 2013-04-02 08:17:11Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2013 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
108	{
109	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
110	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
111	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
112	return VINF_EM_RAW_EMULATE_INSTR;
113	}
114	# endif
115
116	/*
117	* Calc the error code for the guest trap.
118	*/
119	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
120	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
121	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
122	if (pGstWalk->Core.fBadPhysAddr)
123	{
124	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
125	Assert(!pGstWalk->Core.fNotPresent);
126	}
127	else if (!pGstWalk->Core.fNotPresent)
128	uNewErr \|= X86_TRAP_PF_P;
129	TRPMSetErrorCode(pVCpu, uNewErr);
130
131	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
132	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
133	return VINF_EM_RAW_GUEST_TRAP;
134	}
135	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
136
137
138	/**
139	* Deal with a guest page fault.
140	*
141	* The caller has taken the PGM lock.
142	*
143	* @returns Strict VBox status code.
144	*
145	* @param pVCpu The current CPU.
146	* @param uErr The error code.
147	* @param pRegFrame The register frame.
148	* @param pvFault The fault address.
149	* @param pPage The guest page at @a pvFault.
150	* @param pGstWalk The guest page table walk result.
151	* @param pfLockTaken PGM lock taken here or not (out). This is true
152	* when we're called.
153	*/
154	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
155	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
156	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
157	, PGSTPTWALK pGstWalk
158	# endif
159	)
160	{
161	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
162	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
163	#endif
164	PVM pVM = pVCpu->CTX_SUFF(pVM);
165	int rc;
166
167	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
168	{
169	/*
170	* Physical page access handler.
171	*/
172	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
173	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
174	# else
175	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
176	# endif
177	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
178	if (pCur)
179	{
180	# ifdef PGM_SYNC_N_PAGES
181	/*
182	* If the region is write protected and we got a page not present fault, then sync
183	* the pages. If the fault was caused by a read, then restart the instruction.
184	* In case of write access continue to the GC write handler.
185	*
186	* ASSUMES that there is only one handler per page or that they have similar write properties.
187	*/
188	if ( !(uErr & X86_TRAP_PF_P)
189	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
190	{
191	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
192	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
193	# else
194	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
195	# endif
196	if ( RT_FAILURE(rc)
197	\|\| !(uErr & X86_TRAP_PF_RW)
198	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
199	{
200	AssertRC(rc);
201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
202	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
203	return rc;
204	}
205	}
206	# endif
207	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
208	/*
209	* If the access was not thru a #PF(RSVD\|...) resync the page.
210	*/
211	if ( !(uErr & X86_TRAP_PF_RSVD)
212	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
213	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
214	&& pGstWalk->Core.fEffectiveRW
215	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
216	# endif
217	)
218	{
219	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
220	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
221	# else
222	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
223	# endif
224	if ( RT_FAILURE(rc)
225	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
226	{
227	AssertRC(rc);
228	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
229	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
230	return rc;
231	}
232	}
233	# endif
234
235	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
236	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
237	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
238	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
239	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
240	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
241	else
242	{
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
244	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
245	}
246
247	if (pCur->CTX_SUFF(pfnHandler))
248	{
249	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
250	void *pvUser = pCur->CTX_SUFF(pvUser);
251	# ifdef IN_RING0
252	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
253	# else
254	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
255	# endif
256
257	STAM_PROFILE_START(&pCur->Stat, h);
258	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
259	{
260	pgmUnlock(pVM);
261	*pfLockTaken = false;
262	}
263
264	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
265
266	# ifdef VBOX_WITH_STATISTICS
267	pgmLock(pVM);
268	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
269	if (pCur)
270	STAM_PROFILE_STOP(&pCur->Stat, h);
271	pgmUnlock(pVM);
272	# endif
273	}
274	else
275	rc = VINF_EM_RAW_EMULATE_INSTR;
276
277	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
278	return rc;
279	}
280	}
281	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
282	else
283	{
284	# ifdef PGM_SYNC_N_PAGES
285	/*
286	* If the region is write protected and we got a page not present fault, then sync
287	* the pages. If the fault was caused by a read, then restart the instruction.
288	* In case of write access continue to the GC write handler.
289	*/
290	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
291	&& !(uErr & X86_TRAP_PF_P))
292	{
293	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
294	if ( RT_FAILURE(rc)
295	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
296	\|\| !(uErr & X86_TRAP_PF_RW))
297	{
298	AssertRC(rc);
299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
300	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
301	return rc;
302	}
303	}
304	# endif
305	/*
306	* Ok, it's an virtual page access handler.
307	*
308	* Since it's faster to search by address, we'll do that first
309	* and then retry by GCPhys if that fails.
310	*/
311	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
312	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
313	* out of sync, because the page was changed without us noticing it (not-present -> present
314	* without invlpg or mov cr3, xxx).
315	*/
316	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
317	if (pCur)
318	{
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rc;
352	}
353	/* Unhandled part of a monitored page */
354	Log(("Unhandled part of monitored page %RGv\n", pvFault));
355	}
356	else
357	{
358	/* Check by physical address. */
359	unsigned iPage;
360	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
361	Assert(RT_SUCCESS(rc) \|\| !pCur);
362	if ( pCur
363	&& ( uErr & X86_TRAP_PF_RW
364	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
365	{
366	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
367	# ifdef IN_RC
368	STAM_PROFILE_START(&pCur->Stat, h);
369	RTGCPTR GCPtrStart = pCur->Core.Key;
370	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
371	pgmUnlock(pVM);
372	*pfLockTaken = false;
373
374	RTGCPTR off = (iPage << PAGE_SHIFT)
375	+ (pvFault & PAGE_OFFSET_MASK)
376	- (GCPtrStart & PAGE_OFFSET_MASK);
377	Assert(off < pCur->cb);
378	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
379
380	# ifdef VBOX_WITH_STATISTICS
381	pgmLock(pVM);
382	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
383	if (pCur)
384	STAM_PROFILE_STOP(&pCur->Stat, h);
385	pgmUnlock(pVM);
386	# endif
387	# else
388	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
389	# endif
390	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
391	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
392	return rc;
393	}
394	}
395	}
396	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
397
398	/*
399	* There is a handled area of the page, but this fault doesn't belong to it.
400	* We must emulate the instruction.
401	*
402	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
403	* we first check if this was a page-not-present fault for a page with only
404	* write access handlers. Restart the instruction if it wasn't a write access.
405	*/
406	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
407
408	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
409	&& !(uErr & X86_TRAP_PF_P))
410	{
411	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
412	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
413	# else
414	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
415	# endif
416	if ( RT_FAILURE(rc)
417	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
418	\|\| !(uErr & X86_TRAP_PF_RW))
419	{
420	AssertRC(rc);
421	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
422	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
423	return rc;
424	}
425	}
426
427	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
428	* It's writing to an unhandled part of the LDT page several million times.
429	*/
430	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
431	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
432	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
433	return rc;
434	} /* if any kind of handler */
435
436
437	/**
438	* #PF Handler for raw-mode guest execution.
439	*
440	* @returns VBox status code (appropriate for trap handling and GC return).
441	*
442	* @param pVCpu Pointer to the VMCPU.
443	* @param uErr The trap error code.
444	* @param pRegFrame Trap register frame.
445	* @param pvFault The fault address.
446	* @param pfLockTaken PGM lock taken here or not (out)
447	*/
448	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
449	{
450	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
451
452	*pfLockTaken = false;
453
454	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
455	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
456	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
457	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
458	int rc;
459
460	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
461	/*
462	* Walk the guest page translation tables and check if it's a guest fault.
463	*/
464	GSTPTWALK GstWalk;
465	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
466	if (RT_FAILURE_NP(rc))
467	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
468
469	/* assert some GstWalk sanity. */
470	# if PGM_GST_TYPE == PGM_TYPE_AMD64
471	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
472	# endif
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
474	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
475	# endif
476	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
477	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
478	Assert(GstWalk.Core.fSucceeded);
479
480	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
481	{
482	if ( ( (uErr & X86_TRAP_PF_RW)
483	&& !GstWalk.Core.fEffectiveRW
484	&& ( (uErr & X86_TRAP_PF_US)
485	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
486	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
487	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
488	)
489	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
490	}
491
492	/*
493	* Set the accessed and dirty flags.
494	*/
495	# if PGM_GST_TYPE == PGM_TYPE_AMD64
496	GstWalk.Pml4e.u \|= X86_PML4E_A;
497	GstWalk.pPml4e->u \|= X86_PML4E_A;
498	GstWalk.Pdpe.u \|= X86_PDPE_A;
499	GstWalk.pPdpe->u \|= X86_PDPE_A;
500	# endif
501	if (GstWalk.Core.fBigPage)
502	{
503	Assert(GstWalk.Pde.b.u1Size);
504	if (uErr & X86_TRAP_PF_RW)
505	{
506	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
507	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
508	}
509	else
510	{
511	GstWalk.Pde.u \|= X86_PDE4M_A;
512	GstWalk.pPde->u \|= X86_PDE4M_A;
513	}
514	}
515	else
516	{
517	Assert(!GstWalk.Pde.b.u1Size);
518	GstWalk.Pde.u \|= X86_PDE_A;
519	GstWalk.pPde->u \|= X86_PDE_A;
520	if (uErr & X86_TRAP_PF_RW)
521	{
522	# ifdef VBOX_WITH_STATISTICS
523	if (!GstWalk.Pte.n.u1Dirty)
524	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
525	else
526	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
527	# endif
528	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
529	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
530	}
531	else
532	{
533	GstWalk.Pte.u \|= X86_PTE_A;
534	GstWalk.pPte->u \|= X86_PTE_A;
535	}
536	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
537	}
538	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
539	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
540	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
541	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
542	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
543
544	/* Take the big lock now. */
545	*pfLockTaken = true;
546	pgmLock(pVM);
547
548	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
549	/*
550	* If it is a reserved bit fault we know that it is an MMIO (access
551	* handler) related fault and can skip some 200 lines of code.
552	*/
553	if (uErr & X86_TRAP_PF_RSVD)
554	{
555	Assert(uErr & X86_TRAP_PF_P);
556	PPGMPAGE pPage;
557	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
558	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
559	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
560	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
561	pfLockTaken, &GstWalk));
562	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
563	# else
564	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
565	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
566	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
567	pfLockTaken));
568	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
569	# endif
570	AssertRC(rc);
571	PGM_INVL_PG(pVCpu, pvFault);
572	return rc; /* Restart with the corrected entry. */
573	}
574	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
575
576	/*
577	* Fetch the guest PDE, PDPE and PML4E.
578	*/
579	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
580	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
581	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
582
583	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
584	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
585	PX86PDPAE pPDDst;
586	# if PGM_GST_TYPE == PGM_TYPE_PAE
587	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
588	# else
589	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
590	# endif
591	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
592
593	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
594	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
595	PX86PDPAE pPDDst;
596	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
597	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
598	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
599	# else
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
601	# endif
602	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
603
604	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
605	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
606	PEPTPD pPDDst;
607	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
608	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
609	# endif
610	Assert(pPDDst);
611
612	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
613	/*
614	* Dirty page handling.
615	*
616	* If we successfully correct the write protection fault due to dirty bit
617	* tracking, then return immediately.
618	*/
619	if (uErr & X86_TRAP_PF_RW) /* write fault? */
620	{
621	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
622	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
623	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
624	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
625	{
626	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
627	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
628	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
629	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
630	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
631	return VINF_SUCCESS;
632	}
633	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
634	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
635	}
636
637	# if 0 /* rarely useful; leave for debugging. */
638	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
639	# endif
640	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
641
642	/*
643	* A common case is the not-present error caused by lazy page table syncing.
644	*
645	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
646	* here so we can safely assume that the shadow PT is present when calling
647	* SyncPage later.
648	*
649	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
650	* of mapping conflict and defer to SyncCR3 in R3.
651	* (Again, we do NOT support access handlers for non-present guest pages.)
652	*
653	*/
654	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
655	Assert(GstWalk.Pde.n.u1Present);
656	# endif
657	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
658	&& !pPDDst->a[iPDDst].n.u1Present)
659	{
660	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
661	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
662	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
663	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
664	# else
665	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
666	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
667	# endif
668	if (RT_SUCCESS(rc))
669	return rc;
670	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
671	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
672	return VINF_PGM_SYNC_CR3;
673	}
674
675	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
676	/*
677	* Check if this address is within any of our mappings.
678	*
679	* This is very fast and it's gonna save us a bit of effort below and prevent
680	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
681	* (BTW, it's impossible to have physical access handlers in a mapping.)
682	*/
683	if (pgmMapAreMappingsEnabled(pVM))
684	{
685	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
686	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
687	{
688	if (pvFault < pMapping->GCPtr)
689	break;
690	if (pvFault - pMapping->GCPtr < pMapping->cb)
691	{
692	/*
693	* The first thing we check is if we've got an undetected conflict.
694	*/
695	if (pgmMapAreMappingsFloating(pVM))
696	{
697	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
698	while (iPT-- > 0)
699	if (GstWalk.pPde[iPT].n.u1Present)
700	{
701	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
702	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
703	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
704	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
705	return VINF_PGM_SYNC_CR3;
706	}
707	}
708
709	/*
710	* Check if the fault address is in a virtual page access handler range.
711	*/
712	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
713	if ( pCur
714	&& pvFault - pCur->Core.Key < pCur->cb
715	&& uErr & X86_TRAP_PF_RW)
716	{
717	# ifdef IN_RC
718	STAM_PROFILE_START(&pCur->Stat, h);
719	pgmUnlock(pVM);
720	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
721	pgmLock(pVM);
722	STAM_PROFILE_STOP(&pCur->Stat, h);
723	# else
724	AssertFailed();
725	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
726	# endif
727	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
728	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
729	return rc;
730	}
731
732	/*
733	* Pretend we're not here and let the guest handle the trap.
734	*/
735	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
736	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
737	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
738	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
739	return VINF_EM_RAW_GUEST_TRAP;
740	}
741	}
742	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
743	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
744
745	/*
746	* Check if this fault address is flagged for special treatment,
747	* which means we'll have to figure out the physical address and
748	* check flags associated with it.
749	*
750	* ASSUME that we can limit any special access handling to pages
751	* in page tables which the guest believes to be present.
752	*/
753	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
754	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
755	# else
756	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
757	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
758	PPGMPAGE pPage;
759	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
760	if (RT_FAILURE(rc))
761	{
762	/*
763	* When the guest accesses invalid physical memory (e.g. probing
764	* of RAM or accessing a remapped MMIO range), then we'll fall
765	* back to the recompiler to emulate the instruction.
766	*/
767	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
768	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
769	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
770	return VINF_EM_RAW_EMULATE_INSTR;
771	}
772
773	/*
774	* Any handlers for this page?
775	*/
776	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
777	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
778	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
779	&GstWalk));
780	# else
781	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
782	# endif
783
784	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
785
786	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
787	if (uErr & X86_TRAP_PF_P)
788	{
789	/*
790	* The page isn't marked, but it might still be monitored by a virtual page access handler.
791	* (ASSUMES no temporary disabling of virtual handlers.)
792	*/
793	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
794	* we should correct both the shadow page table and physical memory flags, and not only check for
795	* accesses within the handler region but for access to pages with virtual handlers. */
796	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
797	if (pCur)
798	{
799	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
800	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
801	\|\| !(uErr & X86_TRAP_PF_P)
802	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
803	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
804
805	if ( pvFault - pCur->Core.Key < pCur->cb
806	&& ( uErr & X86_TRAP_PF_RW
807	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
808	{
809	# ifdef IN_RC
810	STAM_PROFILE_START(&pCur->Stat, h);
811	pgmUnlock(pVM);
812	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
813	pgmLock(pVM);
814	STAM_PROFILE_STOP(&pCur->Stat, h);
815	# else
816	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
817	# endif
818	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
819	return rc;
820	}
821	}
822	}
823	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
824
825	/*
826	* We are here only if page is present in Guest page tables and
827	* trap is not handled by our handlers.
828	*
829	* Check it for page out-of-sync situation.
830	*/
831	if (!(uErr & X86_TRAP_PF_P))
832	{
833	/*
834	* Page is not present in our page tables. Try to sync it!
835	*/
836	if (uErr & X86_TRAP_PF_US)
837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
838	else /* supervisor */
839	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
840
841	if (PGM_PAGE_IS_BALLOONED(pPage))
842	{
843	/* Emulate reads from ballooned pages as they are not present in
844	our shadow page tables. (Required for e.g. Solaris guests; soft
845	ecc, random nr generator.) */
846	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
847	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
848	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
849	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
850	return rc;
851	}
852
853	# if defined(LOG_ENABLED) && !defined(IN_RING0)
854	RTGCPHYS GCPhys2;
855	uint64_t fPageGst2;
856	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
857	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
858	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
859	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
860	# else
861	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
862	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
863	# endif
864	# endif /* LOG_ENABLED */
865
866	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
867	if ( !GstWalk.Core.fEffectiveUS
868	&& CPUMGetGuestCPL(pVCpu) == 0)
869	{
870	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
871	if ( pvFault == (RTGCPTR)pRegFrame->eip
872	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
873	# ifdef CSAM_DETECT_NEW_CODE_PAGES
874	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
875	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
876	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
877	)
878	{
879	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
880	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
881	if (rc != VINF_SUCCESS)
882	{
883	/*
884	* CSAM needs to perform a job in ring 3.
885	*
886	* Sync the page before going to the host context; otherwise we'll end up in a loop if
887	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
888	*/
889	LogFlow(("CSAM ring 3 job\n"));
890	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
891	AssertRC(rc2);
892
893	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
894	return rc;
895	}
896	}
897	# ifdef CSAM_DETECT_NEW_CODE_PAGES
898	else if ( uErr == X86_TRAP_PF_RW
899	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
900	&& pRegFrame->ecx < 0x10000)
901	{
902	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
903	* to detect loading of new code pages.
904	*/
905
906	/*
907	* Decode the instruction.
908	*/
909	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
910	uint32_t cbOp;
911	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
912
913	/* For now we'll restrict this to rep movsw/d instructions */
914	if ( rc == VINF_SUCCESS
915	&& pDis->pCurInstr->opcode == OP_MOVSWD
916	&& (pDis->prefix & DISPREFIX_REP))
917	{
918	CSAMMarkPossibleCodePage(pVM, pvFault);
919	}
920	}
921	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
922
923	/*
924	* Mark this page as safe.
925	*/
926	/** @todo not correct for pages that contain both code and data!! */
927	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
928	CSAMMarkPage(pVM, pvFault, true);
929	}
930	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
931	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
932	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
933	# else
934	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
935	# endif
936	if (RT_SUCCESS(rc))
937	{
938	/* The page was successfully synced, return to the guest. */
939	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
940	return VINF_SUCCESS;
941	}
942	}
943	else /* uErr & X86_TRAP_PF_P: */
944	{
945	/*
946	* Write protected pages are made writable when the guest makes the
947	* first write to it. This happens for pages that are shared, write
948	* monitored or not yet allocated.
949	*
950	* We may also end up here when CR0.WP=0 in the guest.
951	*
952	* Also, a side effect of not flushing global PDEs are out of sync
953	* pages due to physical monitored regions, that are no longer valid.
954	* Assume for now it only applies to the read/write flag.
955	*/
956	if (uErr & X86_TRAP_PF_RW)
957	{
958	/*
959	* Check if it is a read-only page.
960	*/
961	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
962	{
963	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
964	Assert(!PGM_PAGE_IS_ZERO(pPage));
965	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
966	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
967
968	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
969	if (rc != VINF_SUCCESS)
970	{
971	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
972	return rc;
973	}
974	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
975	return VINF_EM_NO_MEMORY;
976	}
977
978	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
979	/*
980	* Check to see if we need to emulate the instruction if CR0.WP=0.
981	*/
982	if ( !GstWalk.Core.fEffectiveRW
983	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
984	&& CPUMGetGuestCPL(pVCpu) == 0)
985	{
986	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
987	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
988	if (RT_SUCCESS(rc))
989	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
990	else
991	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
992	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
993	return rc;
994	}
995	# endif
996	/// @todo count the above case; else
997	if (uErr & X86_TRAP_PF_US)
998	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
999	else /* supervisor */
1000	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1001
1002	/*
1003	* Sync the page.
1004	*
1005	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1006	* page is not present, which is not true in this case.
1007	*/
1008	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1009	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1010	# else
1011	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1012	# endif
1013	if (RT_SUCCESS(rc))
1014	{
1015	/*
1016	* Page was successfully synced, return to guest but invalidate
1017	* the TLB first as the page is very likely to be in it.
1018	*/
1019	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1020	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1021	# else
1022	PGM_INVL_PG(pVCpu, pvFault);
1023	# endif
1024	# ifdef VBOX_STRICT
1025	RTGCPHYS GCPhys2;
1026	uint64_t fPageGst;
1027	if (!pVM->pgm.s.fNestedPaging)
1028	{
1029	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1030	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1031	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1032	}
1033	uint64_t fPageShw;
1034	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1035	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1036	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1037	# endif /* VBOX_STRICT */
1038	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1039	return VINF_SUCCESS;
1040	}
1041	}
1042	/** @todo else: why are we here? */
1043
1044	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1045	/*
1046	* Check for VMM page flags vs. Guest page flags consistency.
1047	* Currently only for debug purposes.
1048	*/
1049	if (RT_SUCCESS(rc))
1050	{
1051	/* Get guest page flags. */
1052	uint64_t fPageGst;
1053	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1054	if (RT_SUCCESS(rc))
1055	{
1056	uint64_t fPageShw;
1057	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1058
1059	/*
1060	* Compare page flags.
1061	* Note: we have AVL, A, D bits desynced.
1062	*/
1063	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1064	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1065	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1066	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1067	}
1068	else
1069	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1070	}
1071	else
1072	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1073	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1074	}
1075
1076
1077	/*
1078	* If we get here it is because something failed above, i.e. most like guru
1079	* meditiation time.
1080	*/
1081	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1082	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1083	return rc;
1084
1085	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1086	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1087	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1088	return VERR_PGM_NOT_USED_IN_MODE;
1089	# endif
1090	}
1091	#endif /* !IN_RING3 */
1092
1093
1094	/**
1095	* Emulation of the invlpg instruction.
1096	*
1097	*
1098	* @returns VBox status code.
1099	*
1100	* @param pVCpu Pointer to the VMCPU.
1101	* @param GCPtrPage Page to invalidate.
1102	*
1103	* @remark ASSUMES that the guest is updating before invalidating. This order
1104	* isn't required by the CPU, so this is speculative and could cause
1105	* trouble.
1106	* @remark No TLB shootdown is done on any other VCPU as we assume that
1107	* invlpg emulation is the only reason for calling this function.
1108	* (The guest has to shoot down TLB entries on other CPUs itself)
1109	* Currently true, but keep in mind!
1110	*
1111	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1112	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1113	*/
1114	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1115	{
1116	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1117	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1118	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1119	int rc;
1120	PVM pVM = pVCpu->CTX_SUFF(pVM);
1121	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1122
1123	PGM_LOCK_ASSERT_OWNER(pVM);
1124
1125	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1126
1127	/*
1128	* Get the shadow PD entry and skip out if this PD isn't present.
1129	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1130	*/
1131	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1132	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1133	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1134
1135	/* Fetch the pgm pool shadow descriptor. */
1136	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1137	Assert(pShwPde);
1138
1139	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1140	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1141	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1142
1143	/* If the shadow PDPE isn't present, then skip the invalidate. */
1144	if (!pPdptDst->a[iPdpt].n.u1Present)
1145	{
1146	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1147	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1148	return VINF_SUCCESS;
1149	}
1150
1151	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1152	PPGMPOOLPAGE pShwPde = NULL;
1153	PX86PDPAE pPDDst;
1154
1155	/* Fetch the pgm pool shadow descriptor. */
1156	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1157	AssertRCSuccessReturn(rc, rc);
1158	Assert(pShwPde);
1159
1160	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1161	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1162
1163	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1164	/* PML4 */
1165	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1166	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1167	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1168	PX86PDPAE pPDDst;
1169	PX86PDPT pPdptDst;
1170	PX86PML4E pPml4eDst;
1171	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1172	if (rc != VINF_SUCCESS)
1173	{
1174	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1175	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1176	return VINF_SUCCESS;
1177	}
1178	Assert(pPDDst);
1179
1180	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1181	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1182
1183	if (!pPdpeDst->n.u1Present)
1184	{
1185	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1186	return VINF_SUCCESS;
1187	}
1188
1189	/* Fetch the pgm pool shadow descriptor. */
1190	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1191	Assert(pShwPde);
1192
1193	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1194
1195	const SHWPDE PdeDst = *pPdeDst;
1196	if (!PdeDst.n.u1Present)
1197	{
1198	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1199	return VINF_SUCCESS;
1200	}
1201
1202	/*
1203	* Get the guest PD entry and calc big page.
1204	*/
1205	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1206	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1207	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1208	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1209	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1210	unsigned iPDSrc = 0;
1211	# if PGM_GST_TYPE == PGM_TYPE_PAE
1212	X86PDPE PdpeSrcIgn;
1213	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1214	# else /* AMD64 */
1215	PX86PML4E pPml4eSrcIgn;
1216	X86PDPE PdpeSrcIgn;
1217	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1218	# endif
1219	GSTPDE PdeSrc;
1220
1221	if (pPDSrc)
1222	PdeSrc = pPDSrc->a[iPDSrc];
1223	else
1224	PdeSrc.u = 0;
1225	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1226	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1227
1228	# ifdef IN_RING3
1229	/*
1230	* If a CR3 Sync is pending we may ignore the invalidate page operation
1231	* depending on the kind of sync and if it's a global page or not.
1232	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1233	*/
1234	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1235	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1236	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1237	&& fIsBigPage
1238	&& PdeSrc.b.u1Global
1239	)
1240	)
1241	# else
1242	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1243	# endif
1244	{
1245	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1246	return VINF_SUCCESS;
1247	}
1248	# endif /* IN_RING3 */
1249
1250	/*
1251	* Deal with the Guest PDE.
1252	*/
1253	rc = VINF_SUCCESS;
1254	if (PdeSrc.n.u1Present)
1255	{
1256	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1257	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1258	# ifndef PGM_WITHOUT_MAPPING
1259	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1260	{
1261	/*
1262	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1263	*/
1264	Assert(pgmMapAreMappingsEnabled(pVM));
1265	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1266	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1267	}
1268	else
1269	# endif /* !PGM_WITHOUT_MAPPING */
1270	if (!fIsBigPage)
1271	{
1272	/*
1273	* 4KB - page.
1274	*/
1275	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1276	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1277
1278	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1279	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1280	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1281	# endif
1282	if (pShwPage->GCPhys == GCPhys)
1283	{
1284	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1285	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1286
1287	PGSTPT pPTSrc;
1288	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1289	if (RT_SUCCESS(rc))
1290	{
1291	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1292	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1293	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1294	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1295	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1296	GCPtrPage, PteSrc.n.u1Present,
1297	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1298	PteSrc.n.u1User & PdeSrc.n.u1User,
1299	(uint64_t)PteSrc.u,
1300	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1301	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1302	}
1303	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1304	PGM_INVL_PG(pVCpu, GCPtrPage);
1305	}
1306	else
1307	{
1308	/*
1309	* The page table address changed.
1310	*/
1311	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1312	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1313	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1314	ASMAtomicWriteSize(pPdeDst, 0);
1315	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1316	PGM_INVL_VCPU_TLBS(pVCpu);
1317	}
1318	}
1319	else
1320	{
1321	/*
1322	* 2/4MB - page.
1323	*/
1324	/* Before freeing the page, check if anything really changed. */
1325	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1326	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1327	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1328	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1329	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1330	# endif
1331	if ( pShwPage->GCPhys == GCPhys
1332	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1333	{
1334	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1335	/** @todo This test is wrong as it cannot check the G bit!
1336	* FIXME */
1337	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1338	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1339	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1340	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1341	{
1342	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1343	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1344	return VINF_SUCCESS;
1345	}
1346	}
1347
1348	/*
1349	* Ok, the page table is present and it's been changed in the guest.
1350	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1351	* We could do this for some flushes in GC too, but we need an algorithm for
1352	* deciding which 4MB pages containing code likely to be executed very soon.
1353	*/
1354	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1355	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1356	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1357	ASMAtomicWriteSize(pPdeDst, 0);
1358	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1359	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1360	}
1361	}
1362	else
1363	{
1364	/*
1365	* Page directory is not present, mark shadow PDE not present.
1366	*/
1367	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1368	{
1369	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1370	ASMAtomicWriteSize(pPdeDst, 0);
1371	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1372	PGM_INVL_PG(pVCpu, GCPtrPage);
1373	}
1374	else
1375	{
1376	Assert(pgmMapAreMappingsEnabled(pVM));
1377	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1378	}
1379	}
1380	return rc;
1381
1382	#else /* guest real and protected mode */
1383	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1384	NOREF(pVCpu); NOREF(GCPtrPage);
1385	return VINF_SUCCESS;
1386	#endif
1387	}
1388
1389
1390	/**
1391	* Update the tracking of shadowed pages.
1392	*
1393	* @param pVCpu Pointer to the VMCPU.
1394	* @param pShwPage The shadow page.
1395	* @param HCPhys The physical page we is being dereferenced.
1396	* @param iPte Shadow PTE index
1397	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1398	*/
1399	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1400	RTGCPHYS GCPhysPage)
1401	{
1402	PVM pVM = pVCpu->CTX_SUFF(pVM);
1403
1404	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1405	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1406	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1407
1408	/* Use the hint we retrieved from the cached guest PT. */
1409	if (pShwPage->fDirty)
1410	{
1411	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1412
1413	Assert(pShwPage->cPresent);
1414	Assert(pPool->cPresent);
1415	pShwPage->cPresent--;
1416	pPool->cPresent--;
1417
1418	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1419	AssertRelease(pPhysPage);
1420	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1421	return;
1422	}
1423	# else
1424	NOREF(GCPhysPage);
1425	# endif
1426
1427	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1428	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1429
1430	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1431	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1432	* 2. write protect all shadowed pages. I.e. implement caching.
1433	*/
1434	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1435
1436	/*
1437	* Find the guest address.
1438	*/
1439	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1440	pRam;
1441	pRam = pRam->CTX_SUFF(pNext))
1442	{
1443	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1444	while (iPage-- > 0)
1445	{
1446	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1447	{
1448	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1449
1450	Assert(pShwPage->cPresent);
1451	Assert(pPool->cPresent);
1452	pShwPage->cPresent--;
1453	pPool->cPresent--;
1454
1455	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1456	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1457	return;
1458	}
1459	}
1460	}
1461
1462	for (;;)
1463	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1464	}
1465
1466
1467	/**
1468	* Update the tracking of shadowed pages.
1469	*
1470	* @param pVCpu Pointer to the VMCPU.
1471	* @param pShwPage The shadow page.
1472	* @param u16 The top 16-bit of the pPage->HCPhys.
1473	* @param pPage Pointer to the guest page. this will be modified.
1474	* @param iPTDst The index into the shadow table.
1475	*/
1476	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1477	{
1478	PVM pVM = pVCpu->CTX_SUFF(pVM);
1479
1480	/*
1481	* Just deal with the simple first time here.
1482	*/
1483	if (!u16)
1484	{
1485	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1486	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1487	/* Save the page table index. */
1488	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1489	}
1490	else
1491	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1492
1493	/* write back */
1494	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1495	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1496
1497	/* update statistics. */
1498	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1499	pShwPage->cPresent++;
1500	if (pShwPage->iFirstPresent > iPTDst)
1501	pShwPage->iFirstPresent = iPTDst;
1502	}
1503
1504
1505	/**
1506	* Modifies a shadow PTE to account for access handlers.
1507	*
1508	* @param pVM Pointer to the VM.
1509	* @param pPage The page in question.
1510	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1511	* A (accessed) bit so it can be emulated correctly.
1512	* @param pPteDst The shadow PTE (output). This is temporary storage and
1513	* does not need to be set atomically.
1514	*/
1515	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1516	{
1517	NOREF(pVM);
1518	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1519	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1520	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1521	{
1522	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1523	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1524	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1525	pPteDst->n.u1Present = 1;
1526	pPteDst->n.u1Execute = 1;
1527	pPteDst->n.u1IgnorePAT = 1;
1528	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1529	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1530	#else
1531	if (fPteSrc & X86_PTE_A)
1532	{
1533	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1534	SHW_PTE_SET_RO(*pPteDst);
1535	}
1536	else
1537	SHW_PTE_SET(*pPteDst, 0);
1538	#endif
1539	}
1540	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1541	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1542	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1543	&& ( BTH_IS_NP_ACTIVE(pVM)
1544	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1545	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1546	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1547	# endif
1548	)
1549	{
1550	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1551	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1552	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1553	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1554	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1555	pPteDst->n.u1Present = 0;
1556	pPteDst->n.u1Write = 1;
1557	pPteDst->n.u1Execute = 0;
1558	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1559	pPteDst->n.u3EMT = 7;
1560	# else
1561	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1562	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1563	# endif
1564	}
1565	# endif
1566	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1567	else
1568	{
1569	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1570	SHW_PTE_SET(*pPteDst, 0);
1571	}
1572	/** @todo count these kinds of entries. */
1573	}
1574
1575
1576	/**
1577	* Creates a 4K shadow page for a guest page.
1578	*
1579	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1580	* physical address. The PdeSrc argument only the flags are used. No page
1581	* structured will be mapped in this function.
1582	*
1583	* @param pVCpu Pointer to the VMCPU.
1584	* @param pPteDst Destination page table entry.
1585	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1586	* Can safely assume that only the flags are being used.
1587	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1588	* @param pShwPage Pointer to the shadow page.
1589	* @param iPTDst The index into the shadow table.
1590	*
1591	* @remark Not used for 2/4MB pages!
1592	*/
1593	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1594	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1595	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1596	#else
1597	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1598	#endif
1599	{
1600	PVM pVM = pVCpu->CTX_SUFF(pVM);
1601	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1602
1603	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1604	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1605	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1606
1607	if (pShwPage->fDirty)
1608	{
1609	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1610	PGSTPT pGstPT;
1611
1612	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1613	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1614	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1615	pGstPT->a[iPTDst].u = PteSrc.u;
1616	}
1617	#else
1618	Assert(!pShwPage->fDirty);
1619	#endif
1620
1621	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1622	if ( PteSrc.n.u1Present
1623	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1624	#endif
1625	{
1626	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1627	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1628	# endif
1629	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1630
1631	/*
1632	* Find the ram range.
1633	*/
1634	PPGMPAGE pPage;
1635	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1636	if (RT_SUCCESS(rc))
1637	{
1638	/* Ignore ballooned pages.
1639	Don't return errors or use a fatal assert here as part of a
1640	shadow sync range might included ballooned pages. */
1641	if (PGM_PAGE_IS_BALLOONED(pPage))
1642	{
1643	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1644	return;
1645	}
1646
1647	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1648	/* Make the page writable if necessary. */
1649	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1650	&& ( PGM_PAGE_IS_ZERO(pPage)
1651	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1652	\|\| ( PteSrc.n.u1Write
1653	# else
1654	\|\| ( 1
1655	# endif
1656	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1657	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1658	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1659	# endif
1660	# ifdef VBOX_WITH_PAGE_SHARING
1661	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1662	# endif
1663	)
1664	)
1665	)
1666	{
1667	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1668	AssertRC(rc);
1669	}
1670	#endif
1671
1672	/*
1673	* Make page table entry.
1674	*/
1675	SHWPTE PteDst;
1676	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1677	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1678	# else
1679	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1680	# endif
1681	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1682	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1683	else
1684	{
1685	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1686	/*
1687	* If the page or page directory entry is not marked accessed,
1688	* we mark the page not present.
1689	*/
1690	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1691	{
1692	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1693	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1694	SHW_PTE_SET(PteDst, 0);
1695	}
1696	/*
1697	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1698	* when the page is modified.
1699	*/
1700	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1701	{
1702	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1703	SHW_PTE_SET(PteDst,
1704	fGstShwPteFlags
1705	\| PGM_PAGE_GET_HCPHYS(pPage)
1706	\| PGM_PTFLAGS_TRACK_DIRTY);
1707	SHW_PTE_SET_RO(PteDst);
1708	}
1709	else
1710	#endif
1711	{
1712	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1713	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1714	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1715	PteDst.n.u1Present = 1;
1716	PteDst.n.u1Write = 1;
1717	PteDst.n.u1Execute = 1;
1718	PteDst.n.u1IgnorePAT = 1;
1719	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1720	/* PteDst.n.u1Size = 0 */
1721	#else
1722	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1723	#endif
1724	}
1725
1726	/*
1727	* Make sure only allocated pages are mapped writable.
1728	*/
1729	if ( SHW_PTE_IS_P_RW(PteDst)
1730	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1731	{
1732	/* Still applies to shared pages. */
1733	Assert(!PGM_PAGE_IS_ZERO(pPage));
1734	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1735	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1736	}
1737	}
1738
1739	/*
1740	* Keep user track up to date.
1741	*/
1742	if (SHW_PTE_IS_P(PteDst))
1743	{
1744	if (!SHW_PTE_IS_P(*pPteDst))
1745	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1746	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1747	{
1748	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1749	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1750	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1751	}
1752	}
1753	else if (SHW_PTE_IS_P(*pPteDst))
1754	{
1755	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1756	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1757	}
1758
1759	/*
1760	* Update statistics and commit the entry.
1761	*/
1762	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1763	if (!PteSrc.n.u1Global)
1764	pShwPage->fSeenNonGlobal = true;
1765	#endif
1766	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1767	return;
1768	}
1769
1770	/** @todo count these three different kinds. */
1771	Log2(("SyncPageWorker: invalid address in Pte\n"));
1772	}
1773	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1774	else if (!PteSrc.n.u1Present)
1775	Log2(("SyncPageWorker: page not present in Pte\n"));
1776	else
1777	Log2(("SyncPageWorker: invalid Pte\n"));
1778	#endif
1779
1780	/*
1781	* The page is not present or the PTE is bad. Replace the shadow PTE by
1782	* an empty entry, making sure to keep the user tracking up to date.
1783	*/
1784	if (SHW_PTE_IS_P(*pPteDst))
1785	{
1786	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1787	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1788	}
1789	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1790	}
1791
1792
1793	/**
1794	* Syncs a guest OS page.
1795	*
1796	* There are no conflicts at this point, neither is there any need for
1797	* page table allocations.
1798	*
1799	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1800	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1801	*
1802	* @returns VBox status code.
1803	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1804	* @param pVCpu Pointer to the VMCPU.
1805	* @param PdeSrc Page directory entry of the guest.
1806	* @param GCPtrPage Guest context page address.
1807	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1808	* @param uErr Fault error (X86_TRAP_PF_*).
1809	*/
1810	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1811	{
1812	PVM pVM = pVCpu->CTX_SUFF(pVM);
1813	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1814	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1815
1816	PGM_LOCK_ASSERT_OWNER(pVM);
1817
1818	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1819	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1820	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1821	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1822	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1823
1824	/*
1825	* Assert preconditions.
1826	*/
1827	Assert(PdeSrc.n.u1Present);
1828	Assert(cPages);
1829	# if 0 /* rarely useful; leave for debugging. */
1830	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1831	# endif
1832
1833	/*
1834	* Get the shadow PDE, find the shadow page table in the pool.
1835	*/
1836	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1837	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1838	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1839
1840	/* Fetch the pgm pool shadow descriptor. */
1841	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1842	Assert(pShwPde);
1843
1844	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1845	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1846	PPGMPOOLPAGE pShwPde = NULL;
1847	PX86PDPAE pPDDst;
1848
1849	/* Fetch the pgm pool shadow descriptor. */
1850	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1851	AssertRCSuccessReturn(rc2, rc2);
1852	Assert(pShwPde);
1853
1854	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1855	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1856
1857	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1858	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1859	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1860	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1861	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1862
1863	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1864	AssertRCSuccessReturn(rc2, rc2);
1865	Assert(pPDDst && pPdptDst);
1866	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1867	# endif
1868	SHWPDE PdeDst = *pPdeDst;
1869
1870	/*
1871	* - In the guest SMP case we could have blocked while another VCPU reused
1872	* this page table.
1873	* - With W7-64 we may also take this path when the A bit is cleared on
1874	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1875	* relevant TLB entries. If we're write monitoring any page mapped by
1876	* the modified entry, we may end up here with a "stale" TLB entry.
1877	*/
1878	if (!PdeDst.n.u1Present)
1879	{
1880	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1881	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1882	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1883	if (uErr & X86_TRAP_PF_P)
1884	PGM_INVL_PG(pVCpu, GCPtrPage);
1885	return VINF_SUCCESS; /* force the instruction to be executed again. */
1886	}
1887
1888	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1889	Assert(pShwPage);
1890
1891	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1892	/* Fetch the pgm pool shadow descriptor. */
1893	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1894	Assert(pShwPde);
1895	# endif
1896
1897	/*
1898	* Check that the page is present and that the shadow PDE isn't out of sync.
1899	*/
1900	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1901	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1902	RTGCPHYS GCPhys;
1903	if (!fBigPage)
1904	{
1905	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1906	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1907	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1908	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1909	# endif
1910	}
1911	else
1912	{
1913	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1914	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1915	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1916	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1917	# endif
1918	}
1919	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1920	if ( fPdeValid
1921	&& pShwPage->GCPhys == GCPhys
1922	&& PdeSrc.n.u1Present
1923	&& PdeSrc.n.u1User == PdeDst.n.u1User
1924	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1925	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1926	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1927	# endif
1928	)
1929	{
1930	/*
1931	* Check that the PDE is marked accessed already.
1932	* Since we set the accessed bit before getting here on a #PF, this
1933	* check is only meant for dealing with non-#PF'ing paths.
1934	*/
1935	if (PdeSrc.n.u1Accessed)
1936	{
1937	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1938	if (!fBigPage)
1939	{
1940	/*
1941	* 4KB Page - Map the guest page table.
1942	*/
1943	PGSTPT pPTSrc;
1944	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1945	if (RT_SUCCESS(rc))
1946	{
1947	# ifdef PGM_SYNC_N_PAGES
1948	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1949	if ( cPages > 1
1950	&& !(uErr & X86_TRAP_PF_P)
1951	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1952	{
1953	/*
1954	* This code path is currently only taken when the caller is PGMTrap0eHandler
1955	* for non-present pages!
1956	*
1957	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1958	* deal with locality.
1959	*/
1960	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1961	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1962	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1963	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1964	# else
1965	const unsigned offPTSrc = 0;
1966	# endif
1967	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
1968	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1969	iPTDst = 0;
1970	else
1971	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1972
1973	for (; iPTDst < iPTDstEnd; iPTDst++)
1974	{
1975	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
1976
1977	if ( pPteSrc->n.u1Present
1978	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
1979	{
1980	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1981	NOREF(GCPtrCurPage);
1982	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
1983	/*
1984	* Assuming kernel code will be marked as supervisor - and not as user level
1985	* and executed using a conforming code selector - And marked as readonly.
1986	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1987	*/
1988	PPGMPAGE pPage;
1989	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
1990	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1991	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
1992	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
1993	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1994	)
1995	# endif /* else: CSAM not active */
1996	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
1997	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1998	GCPtrCurPage, pPteSrc->n.u1Present,
1999	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2000	pPteSrc->n.u1User & PdeSrc.n.u1User,
2001	(uint64_t)pPteSrc->u,
2002	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2003	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2004	}
2005	}
2006	}
2007	else
2008	# endif /* PGM_SYNC_N_PAGES */
2009	{
2010	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2011	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2012	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2013	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2014	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2015	GCPtrPage, PteSrc.n.u1Present,
2016	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2017	PteSrc.n.u1User & PdeSrc.n.u1User,
2018	(uint64_t)PteSrc.u,
2019	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2020	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2021	}
2022	}
2023	else /* MMIO or invalid page: emulated in #PF handler. */
2024	{
2025	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2026	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2027	}
2028	}
2029	else
2030	{
2031	/*
2032	* 4/2MB page - lazy syncing shadow 4K pages.
2033	* (There are many causes of getting here, it's no longer only CSAM.)
2034	*/
2035	/* Calculate the GC physical address of this 4KB shadow page. */
2036	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2037	/* Find ram range. */
2038	PPGMPAGE pPage;
2039	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2040	if (RT_SUCCESS(rc))
2041	{
2042	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2043
2044	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2045	/* Try to make the page writable if necessary. */
2046	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2047	&& ( PGM_PAGE_IS_ZERO(pPage)
2048	\|\| ( PdeSrc.n.u1Write
2049	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2050	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2051	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2052	# endif
2053	# ifdef VBOX_WITH_PAGE_SHARING
2054	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2055	# endif
2056	)
2057	)
2058	)
2059	{
2060	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2061	AssertRC(rc);
2062	}
2063	# endif
2064
2065	/*
2066	* Make shadow PTE entry.
2067	*/
2068	SHWPTE PteDst;
2069	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2070	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2071	else
2072	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2073
2074	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2075	if ( SHW_PTE_IS_P(PteDst)
2076	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2077	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2078
2079	/* Make sure only allocated pages are mapped writable. */
2080	if ( SHW_PTE_IS_P_RW(PteDst)
2081	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2082	{
2083	/* Still applies to shared pages. */
2084	Assert(!PGM_PAGE_IS_ZERO(pPage));
2085	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2086	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2087	}
2088
2089	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2090
2091	/*
2092	* If the page is not flagged as dirty and is writable, then make it read-only
2093	* at PD level, so we can set the dirty bit when the page is modified.
2094	*
2095	* ASSUMES that page access handlers are implemented on page table entry level.
2096	* Thus we will first catch the dirty access and set PDE.D and restart. If
2097	* there is an access handler, we'll trap again and let it work on the problem.
2098	*/
2099	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2100	* As for invlpg, it simply frees the whole shadow PT.
2101	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2102	if ( !PdeSrc.b.u1Dirty
2103	&& PdeSrc.b.u1Write)
2104	{
2105	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2106	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2107	PdeDst.n.u1Write = 0;
2108	}
2109	else
2110	{
2111	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2112	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2113	}
2114	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2115	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2116	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2117	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2118	}
2119	else
2120	{
2121	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2122	/** @todo must wipe the shadow page table entry in this
2123	* case. */
2124	}
2125	}
2126	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2127	return VINF_SUCCESS;
2128	}
2129
2130	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2131	}
2132	else if (fPdeValid)
2133	{
2134	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2135	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2136	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2137	}
2138	else
2139	{
2140	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2141	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2142	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2143	}
2144
2145	/*
2146	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2147	* Yea, I'm lazy.
2148	*/
2149	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2150	ASMAtomicWriteSize(pPdeDst, 0);
2151
2152	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2153	PGM_INVL_VCPU_TLBS(pVCpu);
2154	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2155
2156
2157	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2158	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2159	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2160	&& !defined(IN_RC)
2161	NOREF(PdeSrc);
2162
2163	# ifdef PGM_SYNC_N_PAGES
2164	/*
2165	* Get the shadow PDE, find the shadow page table in the pool.
2166	*/
2167	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2168	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2169
2170	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2171	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2172
2173	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2174	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2175	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2176	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2177	X86PDEPAE PdeDst;
2178	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2179
2180	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2181	AssertRCSuccessReturn(rc, rc);
2182	Assert(pPDDst && pPdptDst);
2183	PdeDst = pPDDst->a[iPDDst];
2184	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2185	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2186	PEPTPD pPDDst;
2187	EPTPDE PdeDst;
2188
2189	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2190	if (rc != VINF_SUCCESS)
2191	{
2192	AssertRC(rc);
2193	return rc;
2194	}
2195	Assert(pPDDst);
2196	PdeDst = pPDDst->a[iPDDst];
2197	# endif
2198	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2199	if (!PdeDst.n.u1Present)
2200	{
2201	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2202	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2203	return VINF_SUCCESS; /* force the instruction to be executed again. */
2204	}
2205
2206	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2207	if (PdeDst.n.u1Size)
2208	{
2209	Assert(pVM->pgm.s.fNestedPaging);
2210	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2211	return VINF_SUCCESS;
2212	}
2213
2214	/* Mask away the page offset. */
2215	GCPtrPage &= ~((RTGCPTR)0xfff);
2216
2217	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2218	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2219
2220	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2221	if ( cPages > 1
2222	&& !(uErr & X86_TRAP_PF_P)
2223	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2224	{
2225	/*
2226	* This code path is currently only taken when the caller is PGMTrap0eHandler
2227	* for non-present pages!
2228	*
2229	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2230	* deal with locality.
2231	*/
2232	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2233	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2234	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2235	iPTDst = 0;
2236	else
2237	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2238	for (; iPTDst < iPTDstEnd; iPTDst++)
2239	{
2240	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2241	{
2242	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2243	\| (iPTDst << PAGE_SHIFT));
2244
2245	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2246	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2247	GCPtrCurPage,
2248	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2249	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2250
2251	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2252	break;
2253	}
2254	else
2255	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2256	}
2257	}
2258	else
2259	# endif /* PGM_SYNC_N_PAGES */
2260	{
2261	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2262	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2263	\| (iPTDst << PAGE_SHIFT));
2264
2265	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2266
2267	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2268	GCPtrPage,
2269	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2270	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2271	}
2272	return VINF_SUCCESS;
2273
2274	#else
2275	NOREF(PdeSrc);
2276	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2277	return VERR_PGM_NOT_USED_IN_MODE;
2278	#endif
2279	}
2280
2281
2282	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2283
2284	/**
2285	* CheckPageFault helper for returning a page fault indicating a non-present
2286	* (NP) entry in the page translation structures.
2287	*
2288	* @returns VINF_EM_RAW_GUEST_TRAP.
2289	* @param pVCpu Pointer to the VMCPU.
2290	* @param uErr The error code of the shadow fault. Corrections to
2291	* TRPM's copy will be made if necessary.
2292	* @param GCPtrPage For logging.
2293	* @param uPageFaultLevel For logging.
2294	*/
2295	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2296	{
2297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2298	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2299	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2300	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2301	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2302
2303	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2304	return VINF_EM_RAW_GUEST_TRAP;
2305	}
2306
2307
2308	/**
2309	* CheckPageFault helper for returning a page fault indicating a reserved bit
2310	* (RSVD) error in the page translation structures.
2311	*
2312	* @returns VINF_EM_RAW_GUEST_TRAP.
2313	* @param pVCpu Pointer to the VMCPU.
2314	* @param uErr The error code of the shadow fault. Corrections to
2315	* TRPM's copy will be made if necessary.
2316	* @param GCPtrPage For logging.
2317	* @param uPageFaultLevel For logging.
2318	*/
2319	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2320	{
2321	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2322	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2323	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2324
2325	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2326	return VINF_EM_RAW_GUEST_TRAP;
2327	}
2328
2329
2330	/**
2331	* CheckPageFault helper for returning a page protection fault (P).
2332	*
2333	* @returns VINF_EM_RAW_GUEST_TRAP.
2334	* @param pVCpu Pointer to the VMCPU.
2335	* @param uErr The error code of the shadow fault. Corrections to
2336	* TRPM's copy will be made if necessary.
2337	* @param GCPtrPage For logging.
2338	* @param uPageFaultLevel For logging.
2339	*/
2340	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2341	{
2342	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2343	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2344	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2345	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2346
2347	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2348	return VINF_EM_RAW_GUEST_TRAP;
2349	}
2350
2351
2352	/**
2353	* Handle dirty bit tracking faults.
2354	*
2355	* @returns VBox status code.
2356	* @param pVCpu Pointer to the VMCPU.
2357	* @param uErr Page fault error code.
2358	* @param pPdeSrc Guest page directory entry.
2359	* @param pPdeDst Shadow page directory entry.
2360	* @param GCPtrPage Guest context page address.
2361	*/
2362	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2363	RTGCPTR GCPtrPage)
2364	{
2365	PVM pVM = pVCpu->CTX_SUFF(pVM);
2366	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2367	NOREF(uErr);
2368
2369	PGM_LOCK_ASSERT_OWNER(pVM);
2370
2371	/*
2372	* Handle big page.
2373	*/
2374	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2375	{
2376	if ( pPdeDst->n.u1Present
2377	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2378	{
2379	SHWPDE PdeDst = *pPdeDst;
2380
2381	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2382	Assert(pPdeSrc->b.u1Write);
2383
2384	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2385	* fault again and take this path to only invalidate the entry (see below).
2386	*/
2387	PdeDst.n.u1Write = 1;
2388	PdeDst.n.u1Accessed = 1;
2389	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2390	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2391	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2392	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2393	}
2394
2395	# ifdef IN_RING0
2396	/* Check for stale TLB entry; only applies to the SMP guest case. */
2397	if ( pVM->cCpus > 1
2398	&& pPdeDst->n.u1Write
2399	&& pPdeDst->n.u1Accessed)
2400	{
2401	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2402	if (pShwPage)
2403	{
2404	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2405	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2406	if (SHW_PTE_IS_P_RW(*pPteDst))
2407	{
2408	/* Stale TLB entry. */
2409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2410	PGM_INVL_PG(pVCpu, GCPtrPage);
2411	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2412	}
2413	}
2414	}
2415	# endif /* IN_RING0 */
2416	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2417	}
2418
2419	/*
2420	* Map the guest page table.
2421	*/
2422	PGSTPT pPTSrc;
2423	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2424	if (RT_FAILURE(rc))
2425	{
2426	AssertRC(rc);
2427	return rc;
2428	}
2429
2430	if (pPdeDst->n.u1Present)
2431	{
2432	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2433	const GSTPTE PteSrc = *pPteSrc;
2434
2435	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2436	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2437	* Our individual shadow handlers will provide more information and force a fatal exit.
2438	*/
2439	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2440	{
2441	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2442	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2443	}
2444	#endif
2445	/*
2446	* Map shadow page table.
2447	*/
2448	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2449	if (pShwPage)
2450	{
2451	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2452	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2453	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2454	{
2455	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2456	{
2457	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2458	SHWPTE PteDst = *pPteDst;
2459
2460	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2461	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2462
2463	Assert(PteSrc.n.u1Write);
2464
2465	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2466	* entry will not harm; write access will simply fault again and
2467	* take this path to only invalidate the entry.
2468	*/
2469	if (RT_LIKELY(pPage))
2470	{
2471	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2472	{
2473	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2474	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2475	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2476	SHW_PTE_SET_RO(PteDst);
2477	}
2478	else
2479	{
2480	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2481	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2482	{
2483	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2484	AssertRC(rc);
2485	}
2486	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2487	SHW_PTE_SET_RW(PteDst);
2488	else
2489	{
2490	/* Still applies to shared pages. */
2491	Assert(!PGM_PAGE_IS_ZERO(pPage));
2492	SHW_PTE_SET_RO(PteDst);
2493	}
2494	}
2495	}
2496	else
2497	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2498
2499	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2500	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2501	PGM_INVL_PG(pVCpu, GCPtrPage);
2502	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2503	}
2504
2505	# ifdef IN_RING0
2506	/* Check for stale TLB entry; only applies to the SMP guest case. */
2507	if ( pVM->cCpus > 1
2508	&& SHW_PTE_IS_RW(*pPteDst)
2509	&& SHW_PTE_IS_A(*pPteDst))
2510	{
2511	/* Stale TLB entry. */
2512	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2513	PGM_INVL_PG(pVCpu, GCPtrPage);
2514	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2515	}
2516	# endif
2517	}
2518	}
2519	else
2520	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2521	}
2522
2523	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2524	}
2525
2526	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2527
2528
2529	/**
2530	* Sync a shadow page table.
2531	*
2532	* The shadow page table is not present in the shadow PDE.
2533	*
2534	* Handles mapping conflicts.
2535	*
2536	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2537	* conflict), and Trap0eHandler.
2538	*
2539	* A precondition for this method is that the shadow PDE is not present. The
2540	* caller must take the PGM lock before checking this and continue to hold it
2541	* when calling this method.
2542	*
2543	* @returns VBox status code.
2544	* @param pVCpu Pointer to the VMCPU.
2545	* @param iPD Page directory index.
2546	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2547	* Assume this is a temporary mapping.
2548	* @param GCPtrPage GC Pointer of the page that caused the fault
2549	*/
2550	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2551	{
2552	PVM pVM = pVCpu->CTX_SUFF(pVM);
2553	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2554
2555	#if 0 /* rarely useful; leave for debugging. */
2556	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2557	#endif
2558	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2559
2560	PGM_LOCK_ASSERT_OWNER(pVM);
2561
2562	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2563	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2564	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2565	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2566	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2567
2568	int rc = VINF_SUCCESS;
2569
2570	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2571
2572	/*
2573	* Some input validation first.
2574	*/
2575	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2576
2577	/*
2578	* Get the relevant shadow PDE entry.
2579	*/
2580	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2581	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2582	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2583
2584	/* Fetch the pgm pool shadow descriptor. */
2585	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2586	Assert(pShwPde);
2587
2588	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2589	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2590	PPGMPOOLPAGE pShwPde = NULL;
2591	PX86PDPAE pPDDst;
2592	PSHWPDE pPdeDst;
2593
2594	/* Fetch the pgm pool shadow descriptor. */
2595	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2596	AssertRCSuccessReturn(rc, rc);
2597	Assert(pShwPde);
2598
2599	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2600	pPdeDst = &pPDDst->a[iPDDst];
2601
2602	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2603	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2604	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2605	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2606	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2607	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2608	AssertRCSuccessReturn(rc, rc);
2609	Assert(pPDDst);
2610	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2611	# endif
2612	SHWPDE PdeDst = *pPdeDst;
2613
2614	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2615	/* Fetch the pgm pool shadow descriptor. */
2616	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2617	Assert(pShwPde);
2618	# endif
2619
2620	# ifndef PGM_WITHOUT_MAPPINGS
2621	/*
2622	* Check for conflicts.
2623	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2624	* R3: Simply resolve the conflict.
2625	*/
2626	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2627	{
2628	Assert(pgmMapAreMappingsEnabled(pVM));
2629	# ifndef IN_RING3
2630	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2631	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2632	return VERR_ADDRESS_CONFLICT;
2633
2634	# else /* IN_RING3 */
2635	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2636	Assert(pMapping);
2637	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2638	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2639	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2640	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2641	# else
2642	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2643	# endif
2644	if (RT_FAILURE(rc))
2645	{
2646	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2647	return rc;
2648	}
2649	PdeDst = *pPdeDst;
2650	# endif /* IN_RING3 */
2651	}
2652	# endif /* !PGM_WITHOUT_MAPPINGS */
2653	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2654
2655	/*
2656	* Sync the page directory entry.
2657	*/
2658	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2659	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2660	if ( PdeSrc.n.u1Present
2661	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2662	{
2663	/*
2664	* Allocate & map the page table.
2665	*/
2666	PSHWPT pPTDst;
2667	PPGMPOOLPAGE pShwPage;
2668	RTGCPHYS GCPhys;
2669	if (fPageTable)
2670	{
2671	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2672	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2673	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2674	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2675	# endif
2676	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2677	pShwPde->idx, iPDDst, false /fLockPage/,
2678	&pShwPage);
2679	}
2680	else
2681	{
2682	PGMPOOLACCESS enmAccess;
2683	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2684	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2685	# else
2686	const bool fNoExecute = false;
2687	# endif
2688
2689	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2690	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2691	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2692	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2693	# endif
2694	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2695	if (PdeSrc.n.u1User)
2696	{
2697	if (PdeSrc.n.u1Write)
2698	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2699	else
2700	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2701	}
2702	else
2703	{
2704	if (PdeSrc.n.u1Write)
2705	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2706	else
2707	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2708	}
2709	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2710	pShwPde->idx, iPDDst, false /fLockPage/,
2711	&pShwPage);
2712	}
2713	if (rc == VINF_SUCCESS)
2714	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2715	else if (rc == VINF_PGM_CACHED_PAGE)
2716	{
2717	/*
2718	* The PT was cached, just hook it up.
2719	*/
2720	if (fPageTable)
2721	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2722	else
2723	{
2724	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2725	/* (see explanation and assumptions further down.) */
2726	if ( !PdeSrc.b.u1Dirty
2727	&& PdeSrc.b.u1Write)
2728	{
2729	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2730	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2731	PdeDst.b.u1Write = 0;
2732	}
2733	}
2734	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2735	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2736	return VINF_SUCCESS;
2737	}
2738	else if (rc == VERR_PGM_POOL_FLUSHED)
2739	{
2740	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2741	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2742	return VINF_PGM_SYNC_CR3;
2743	}
2744	else
2745	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2746	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2747	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2748	* irrelevant at this point. */
2749	PdeDst.u &= X86_PDE_AVL_MASK;
2750	PdeDst.u \|= pShwPage->Core.Key;
2751
2752	/*
2753	* Page directory has been accessed (this is a fault situation, remember).
2754	*/
2755	/** @todo
2756	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2757	* fault situation. What's more, the Trap0eHandler has already set the
2758	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2759	* might need setting the accessed flag.
2760	*
2761	* The best idea is to leave this change to the caller and add an
2762	* assertion that it's set already. */
2763	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2764	if (fPageTable)
2765	{
2766	/*
2767	* Page table - 4KB.
2768	*
2769	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2770	*/
2771	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2772	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2773	PGSTPT pPTSrc;
2774	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2775	if (RT_SUCCESS(rc))
2776	{
2777	/*
2778	* Start by syncing the page directory entry so CSAM's TLB trick works.
2779	*/
2780	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2781	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2782	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2783	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2784
2785	/*
2786	* Directory/page user or supervisor privilege: (same goes for read/write)
2787	*
2788	* Directory Page Combined
2789	* U/S U/S U/S
2790	* 0 0 0
2791	* 0 1 0
2792	* 1 0 0
2793	* 1 1 1
2794	*
2795	* Simple AND operation. Table listed for completeness.
2796	*
2797	*/
2798	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2799	# ifdef PGM_SYNC_N_PAGES
2800	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2801	unsigned iPTDst = iPTBase;
2802	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2803	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2804	iPTDst = 0;
2805	else
2806	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2807	# else /* !PGM_SYNC_N_PAGES */
2808	unsigned iPTDst = 0;
2809	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2810	# endif /* !PGM_SYNC_N_PAGES */
2811	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2812	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2813	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2814	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2815	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2816	# else
2817	const unsigned offPTSrc = 0;
2818	# endif
2819	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2820	{
2821	const unsigned iPTSrc = iPTDst + offPTSrc;
2822	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2823
2824	if (PteSrc.n.u1Present)
2825	{
2826	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2827	/*
2828	* Assuming kernel code will be marked as supervisor - and not as user level
2829	* and executed using a conforming code selector - And marked as readonly.
2830	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2831	*/
2832	PPGMPAGE pPage;
2833	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2834	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2835	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2836	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2837	)
2838	# endif
2839	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2840	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2841	GCPtrCur,
2842	PteSrc.n.u1Present,
2843	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2844	PteSrc.n.u1User & PdeSrc.n.u1User,
2845	(uint64_t)PteSrc.u,
2846	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2847	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2848	}
2849	/* else: the page table was cleared by the pool */
2850	} /* for PTEs */
2851	}
2852	}
2853	else
2854	{
2855	/*
2856	* Big page - 2/4MB.
2857	*
2858	* We'll walk the ram range list in parallel and optimize lookups.
2859	* We will only sync one shadow page table at a time.
2860	*/
2861	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2862
2863	/**
2864	* @todo It might be more efficient to sync only a part of the 4MB
2865	* page (similar to what we do for 4KB PDs).
2866	*/
2867
2868	/*
2869	* Start by syncing the page directory entry.
2870	*/
2871	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2872	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2873
2874	/*
2875	* If the page is not flagged as dirty and is writable, then make it read-only
2876	* at PD level, so we can set the dirty bit when the page is modified.
2877	*
2878	* ASSUMES that page access handlers are implemented on page table entry level.
2879	* Thus we will first catch the dirty access and set PDE.D and restart. If
2880	* there is an access handler, we'll trap again and let it work on the problem.
2881	*/
2882	/** @todo move the above stuff to a section in the PGM documentation. */
2883	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2884	if ( !PdeSrc.b.u1Dirty
2885	&& PdeSrc.b.u1Write)
2886	{
2887	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2888	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2889	PdeDst.b.u1Write = 0;
2890	}
2891	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2892	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2893
2894	/*
2895	* Fill the shadow page table.
2896	*/
2897	/* Get address and flags from the source PDE. */
2898	SHWPTE PteDstBase;
2899	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2900
2901	/* Loop thru the entries in the shadow PT. */
2902	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2903	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2904	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2905	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2906	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2907	unsigned iPTDst = 0;
2908	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2909	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2910	{
2911	if (pRam && GCPhys >= pRam->GCPhys)
2912	{
2913	# ifndef PGM_WITH_A20
2914	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2915	# endif
2916	do
2917	{
2918	/* Make shadow PTE. */
2919	# ifdef PGM_WITH_A20
2920	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2921	# else
2922	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2923	# endif
2924	SHWPTE PteDst;
2925
2926	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2927	/* Try to make the page writable if necessary. */
2928	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2929	&& ( PGM_PAGE_IS_ZERO(pPage)
2930	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2931	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2932	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2933	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2934	# endif
2935	# ifdef VBOX_WITH_PAGE_SHARING
2936	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2937	# endif
2938	&& !PGM_PAGE_IS_BALLOONED(pPage))
2939	)
2940	)
2941	{
2942	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2943	AssertRCReturn(rc, rc);
2944	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2945	break;
2946	}
2947	# endif
2948
2949	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2950	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
2951	else if (PGM_PAGE_IS_BALLOONED(pPage))
2952	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
2953	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2954	/*
2955	* Assuming kernel code will be marked as supervisor and not as user level and executed
2956	* using a conforming code selector. Don't check for readonly, as that implies the whole
2957	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2958	*/
2959	else if ( !PdeSrc.n.u1User
2960	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
2961	SHW_PTE_SET(PteDst, 0);
2962	# endif
2963	else
2964	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
2965
2966	/* Only map writable pages writable. */
2967	if ( SHW_PTE_IS_P_RW(PteDst)
2968	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2969	{
2970	/* Still applies to shared pages. */
2971	Assert(!PGM_PAGE_IS_ZERO(pPage));
2972	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2973	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
2974	}
2975
2976	if (SHW_PTE_IS_P(PteDst))
2977	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2978
2979	/* commit it (not atomic, new table) */
2980	pPTDst->a[iPTDst] = PteDst;
2981	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2982	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
2983	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
2984
2985	/* advance */
2986	GCPhys += PAGE_SIZE;
2987	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
2988	# ifndef PGM_WITH_A20
2989	iHCPage++;
2990	# endif
2991	iPTDst++;
2992	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2993	&& GCPhys <= pRam->GCPhysLast);
2994
2995	/* Advance ram range list. */
2996	while (pRam && GCPhys > pRam->GCPhysLast)
2997	pRam = pRam->CTX_SUFF(pNext);
2998	}
2999	else if (pRam)
3000	{
3001	Log(("Invalid pages at %RGp\n", GCPhys));
3002	do
3003	{
3004	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3005	GCPhys += PAGE_SIZE;
3006	iPTDst++;
3007	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3008	&& GCPhys < pRam->GCPhys);
3009	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3010	}
3011	else
3012	{
3013	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3014	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3015	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3016	}
3017	} /* while more PTEs */
3018	} /* 4KB / 4MB */
3019	}
3020	else
3021	AssertRelease(!PdeDst.n.u1Present);
3022
3023	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3024	if (RT_FAILURE(rc))
3025	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3026	return rc;
3027
3028	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3029	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3030	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3031	&& !defined(IN_RC)
3032	NOREF(iPDSrc); NOREF(pPDSrc);
3033
3034	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3035
3036	/*
3037	* Validate input a little bit.
3038	*/
3039	int rc = VINF_SUCCESS;
3040	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3041	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3042	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3043
3044	/* Fetch the pgm pool shadow descriptor. */
3045	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3046	Assert(pShwPde);
3047
3048	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3049	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3050	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3051	PX86PDPAE pPDDst;
3052	PSHWPDE pPdeDst;
3053
3054	/* Fetch the pgm pool shadow descriptor. */
3055	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3056	AssertRCSuccessReturn(rc, rc);
3057	Assert(pShwPde);
3058
3059	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3060	pPdeDst = &pPDDst->a[iPDDst];
3061
3062	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3063	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3064	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3065	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3066	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3067	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3068	AssertRCSuccessReturn(rc, rc);
3069	Assert(pPDDst);
3070	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3071
3072	/* Fetch the pgm pool shadow descriptor. */
3073	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3074	Assert(pShwPde);
3075
3076	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3077	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3078	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3079	PEPTPD pPDDst;
3080	PEPTPDPT pPdptDst;
3081
3082	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3083	if (rc != VINF_SUCCESS)
3084	{
3085	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3086	AssertRC(rc);
3087	return rc;
3088	}
3089	Assert(pPDDst);
3090	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3091
3092	/* Fetch the pgm pool shadow descriptor. */
3093	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3094	Assert(pShwPde);
3095	# endif
3096	SHWPDE PdeDst = *pPdeDst;
3097
3098	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3099	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3100
3101	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3102	if (BTH_IS_NP_ACTIVE(pVM))
3103	{
3104	/* Check if we allocated a big page before for this 2 MB range. */
3105	PPGMPAGE pPage;
3106	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3107	if (RT_SUCCESS(rc))
3108	{
3109	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3110	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3111	{
3112	if (PGM_A20_IS_ENABLED(pVCpu))
3113	{
3114	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3115	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3116	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3117	}
3118	else
3119	{
3120	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3121	pVM->pgm.s.cLargePagesDisabled++;
3122	}
3123	}
3124	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3125	&& PGM_A20_IS_ENABLED(pVCpu))
3126	{
3127	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3128	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3129	if (RT_SUCCESS(rc))
3130	{
3131	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3132	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3133	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3134	}
3135	}
3136	else if ( PGMIsUsingLargePages(pVM)
3137	&& PGM_A20_IS_ENABLED(pVCpu))
3138	{
3139	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3140	if (RT_SUCCESS(rc))
3141	{
3142	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3143	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3144	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3145	}
3146	else
3147	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3148	}
3149
3150	if (HCPhys != NIL_RTHCPHYS)
3151	{
3152	PdeDst.u &= X86_PDE_AVL_MASK;
3153	PdeDst.u \|= HCPhys;
3154	PdeDst.n.u1Present = 1;
3155	PdeDst.n.u1Write = 1;
3156	PdeDst.b.u1Size = 1;
3157	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3158	PdeDst.n.u1Execute = 1;
3159	PdeDst.b.u1IgnorePAT = 1;
3160	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3161	# else
3162	PdeDst.n.u1User = 1;
3163	# endif
3164	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3165
3166	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3167	/* Add a reference to the first page only. */
3168	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3169
3170	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3171	return VINF_SUCCESS;
3172	}
3173	}
3174	}
3175	# endif /* HC_ARCH_BITS == 64 */
3176
3177	/*
3178	* Allocate & map the page table.
3179	*/
3180	PSHWPT pPTDst;
3181	PPGMPOOLPAGE pShwPage;
3182	RTGCPHYS GCPhys;
3183
3184	/* Virtual address = physical address */
3185	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3186	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3187	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3188	&pShwPage);
3189	if ( rc == VINF_SUCCESS
3190	\|\| rc == VINF_PGM_CACHED_PAGE)
3191	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3192	else
3193	{
3194	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3195	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3196	}
3197
3198	if (rc == VINF_SUCCESS)
3199	{
3200	/* New page table; fully set it up. */
3201	Assert(pPTDst);
3202
3203	/* Mask away the page offset. */
3204	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3205
3206	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3207	{
3208	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3209	\| (iPTDst << PAGE_SHIFT));
3210
3211	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3212	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3213	GCPtrCurPage,
3214	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3215	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3216
3217	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3218	break;
3219	}
3220	}
3221	else
3222	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3223
3224	/* Save the new PDE. */
3225	PdeDst.u &= X86_PDE_AVL_MASK;
3226	PdeDst.u \|= pShwPage->Core.Key;
3227	PdeDst.n.u1Present = 1;
3228	PdeDst.n.u1Write = 1;
3229	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3230	PdeDst.n.u1Execute = 1;
3231	# else
3232	PdeDst.n.u1User = 1;
3233	PdeDst.n.u1Accessed = 1;
3234	# endif
3235	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3236
3237	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3238	if (RT_FAILURE(rc))
3239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3240	return rc;
3241
3242	#else
3243	NOREF(iPDSrc); NOREF(pPDSrc);
3244	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3245	return VERR_PGM_NOT_USED_IN_MODE;
3246	#endif
3247	}
3248
3249
3250
3251	/**
3252	* Prefetch a page/set of pages.
3253	*
3254	* Typically used to sync commonly used pages before entering raw mode
3255	* after a CR3 reload.
3256	*
3257	* @returns VBox status code.
3258	* @param pVCpu Pointer to the VMCPU.
3259	* @param GCPtrPage Page to invalidate.
3260	*/
3261	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3262	{
3263	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3264	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3265	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3266	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3267	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3268	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3269	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3270
3271	/*
3272	* Check that all Guest levels thru the PDE are present, getting the
3273	* PD and PDE in the processes.
3274	*/
3275	int rc = VINF_SUCCESS;
3276	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3277	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3278	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3279	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3280	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3281	unsigned iPDSrc;
3282	X86PDPE PdpeSrc;
3283	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3284	if (!pPDSrc)
3285	return VINF_SUCCESS; /* not present */
3286	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3287	unsigned iPDSrc;
3288	PX86PML4E pPml4eSrc;
3289	X86PDPE PdpeSrc;
3290	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3291	if (!pPDSrc)
3292	return VINF_SUCCESS; /* not present */
3293	# endif
3294	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3295	# else
3296	PGSTPD pPDSrc = NULL;
3297	const unsigned iPDSrc = 0;
3298	GSTPDE PdeSrc;
3299
3300	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3301	PdeSrc.n.u1Present = 1;
3302	PdeSrc.n.u1Write = 1;
3303	PdeSrc.n.u1Accessed = 1;
3304	PdeSrc.n.u1User = 1;
3305	# endif
3306
3307	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3308	{
3309	PVM pVM = pVCpu->CTX_SUFF(pVM);
3310	pgmLock(pVM);
3311
3312	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3313	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3314	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3315	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3316	PX86PDPAE pPDDst;
3317	X86PDEPAE PdeDst;
3318	# if PGM_GST_TYPE != PGM_TYPE_PAE
3319	X86PDPE PdpeSrc;
3320
3321	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3322	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3323	# endif
3324	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3325	if (rc != VINF_SUCCESS)
3326	{
3327	pgmUnlock(pVM);
3328	AssertRC(rc);
3329	return rc;
3330	}
3331	Assert(pPDDst);
3332	PdeDst = pPDDst->a[iPDDst];
3333
3334	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3335	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3336	PX86PDPAE pPDDst;
3337	X86PDEPAE PdeDst;
3338
3339	# if PGM_GST_TYPE == PGM_TYPE_PROT
3340	/* AMD-V nested paging */
3341	X86PML4E Pml4eSrc;
3342	X86PDPE PdpeSrc;
3343	PX86PML4E pPml4eSrc = &Pml4eSrc;
3344
3345	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3346	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3347	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3348	# endif
3349
3350	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3351	if (rc != VINF_SUCCESS)
3352	{
3353	pgmUnlock(pVM);
3354	AssertRC(rc);
3355	return rc;
3356	}
3357	Assert(pPDDst);
3358	PdeDst = pPDDst->a[iPDDst];
3359	# endif
3360	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3361	{
3362	if (!PdeDst.n.u1Present)
3363	{
3364	/** @todo r=bird: This guy will set the A bit on the PDE,
3365	* probably harmless. */
3366	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3367	}
3368	else
3369	{
3370	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3371	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3372	* makes no sense to prefetch more than one page.
3373	*/
3374	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3375	if (RT_SUCCESS(rc))
3376	rc = VINF_SUCCESS;
3377	}
3378	}
3379	pgmUnlock(pVM);
3380	}
3381	return rc;
3382
3383	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3384	NOREF(pVCpu); NOREF(GCPtrPage);
3385	return VINF_SUCCESS; /* ignore */
3386	#else
3387	AssertCompile(0);
3388	#endif
3389	}
3390
3391
3392
3393
3394	/**
3395	* Syncs a page during a PGMVerifyAccess() call.
3396	*
3397	* @returns VBox status code (informational included).
3398	* @param pVCpu Pointer to the VMCPU.
3399	* @param GCPtrPage The address of the page to sync.
3400	* @param fPage The effective guest page flags.
3401	* @param uErr The trap error code.
3402	* @remarks This will normally never be called on invalid guest page
3403	* translation entries.
3404	*/
3405	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3406	{
3407	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3408
3409	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3410
3411	Assert(!pVM->pgm.s.fNestedPaging);
3412	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3413	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3414	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3415	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3416	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3417	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3418	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3419
3420	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3421	if (!(fPage & X86_PTE_US))
3422	{
3423	/*
3424	* Mark this page as safe.
3425	*/
3426	/** @todo not correct for pages that contain both code and data!! */
3427	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3428	CSAMMarkPage(pVM, GCPtrPage, true);
3429	}
3430	# endif
3431
3432	/*
3433	* Get guest PD and index.
3434	*/
3435	/** @todo Performance: We've done all this a jiffy ago in the
3436	* PGMGstGetPage call. */
3437	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3438	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3439	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3440	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3441
3442	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3443	unsigned iPDSrc = 0;
3444	X86PDPE PdpeSrc;
3445	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3446	if (RT_UNLIKELY(!pPDSrc))
3447	{
3448	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3449	return VINF_EM_RAW_GUEST_TRAP;
3450	}
3451
3452	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3453	unsigned iPDSrc = 0; /* shut up gcc */
3454	PX86PML4E pPml4eSrc = NULL; /* ditto */
3455	X86PDPE PdpeSrc;
3456	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3457	if (RT_UNLIKELY(!pPDSrc))
3458	{
3459	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3460	return VINF_EM_RAW_GUEST_TRAP;
3461	}
3462	# endif
3463
3464	# else /* !PGM_WITH_PAGING */
3465	PGSTPD pPDSrc = NULL;
3466	const unsigned iPDSrc = 0;
3467	# endif /* !PGM_WITH_PAGING */
3468	int rc = VINF_SUCCESS;
3469
3470	pgmLock(pVM);
3471
3472	/*
3473	* First check if the shadow pd is present.
3474	*/
3475	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3476	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3477
3478	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3479	PX86PDEPAE pPdeDst;
3480	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3481	PX86PDPAE pPDDst;
3482	# if PGM_GST_TYPE != PGM_TYPE_PAE
3483	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3484	X86PDPE PdpeSrc;
3485	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3486	# endif
3487	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3488	if (rc != VINF_SUCCESS)
3489	{
3490	pgmUnlock(pVM);
3491	AssertRC(rc);
3492	return rc;
3493	}
3494	Assert(pPDDst);
3495	pPdeDst = &pPDDst->a[iPDDst];
3496
3497	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3498	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3499	PX86PDPAE pPDDst;
3500	PX86PDEPAE pPdeDst;
3501
3502	# if PGM_GST_TYPE == PGM_TYPE_PROT
3503	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3504	X86PML4E Pml4eSrc;
3505	X86PDPE PdpeSrc;
3506	PX86PML4E pPml4eSrc = &Pml4eSrc;
3507	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3508	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3509	# endif
3510
3511	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3512	if (rc != VINF_SUCCESS)
3513	{
3514	pgmUnlock(pVM);
3515	AssertRC(rc);
3516	return rc;
3517	}
3518	Assert(pPDDst);
3519	pPdeDst = &pPDDst->a[iPDDst];
3520	# endif
3521
3522	if (!pPdeDst->n.u1Present)
3523	{
3524	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3525	if (rc != VINF_SUCCESS)
3526	{
3527	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3528	pgmUnlock(pVM);
3529	AssertRC(rc);
3530	return rc;
3531	}
3532	}
3533
3534	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3535	/* Check for dirty bit fault */
3536	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3537	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3538	Log(("PGMVerifyAccess: success (dirty)\n"));
3539	else
3540	# endif
3541	{
3542	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3543	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3544	# else
3545	GSTPDE PdeSrc;
3546	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3547	PdeSrc.n.u1Present = 1;
3548	PdeSrc.n.u1Write = 1;
3549	PdeSrc.n.u1Accessed = 1;
3550	PdeSrc.n.u1User = 1;
3551	# endif
3552
3553	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3554	if (uErr & X86_TRAP_PF_US)
3555	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3556	else /* supervisor */
3557	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3558
3559	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3560	if (RT_SUCCESS(rc))
3561	{
3562	/* Page was successfully synced */
3563	Log2(("PGMVerifyAccess: success (sync)\n"));
3564	rc = VINF_SUCCESS;
3565	}
3566	else
3567	{
3568	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3569	rc = VINF_EM_RAW_GUEST_TRAP;
3570	}
3571	}
3572	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3573	pgmUnlock(pVM);
3574	return rc;
3575
3576	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3577
3578	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3579	return VERR_PGM_NOT_USED_IN_MODE;
3580	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3581	}
3582
3583
3584	/**
3585	* Syncs the paging hierarchy starting at CR3.
3586	*
3587	* @returns VBox status code, no specials.
3588	* @param pVCpu Pointer to the VMCPU.
3589	* @param cr0 Guest context CR0 register.
3590	* @param cr3 Guest context CR3 register. Not subjected to the A20
3591	* mask.
3592	* @param cr4 Guest context CR4 register.
3593	* @param fGlobal Including global page directories or not
3594	*/
3595	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3596	{
3597	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3598	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3599
3600	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3601
3602	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3603
3604	pgmLock(pVM);
3605
3606	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3607	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3608	if (pPool->cDirtyPages)
3609	pgmPoolResetDirtyPages(pVM);
3610	# endif
3611
3612	/*
3613	* Update page access handlers.
3614	* The virtual are always flushed, while the physical are only on demand.
3615	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3616	* have to look into that later because it will have a bad influence on the performance.
3617	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3618	* bird: Yes, but that won't work for aliases.
3619	*/
3620	/** @todo this MUST go away. See @bugref{1557}. */
3621	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3622	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3623	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3624	pgmUnlock(pVM);
3625	#endif /* !NESTED && !EPT */
3626
3627	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3628	/*
3629	* Nested / EPT - almost no work.
3630	*/
3631	Assert(!pgmMapAreMappingsEnabled(pVM));
3632	return VINF_SUCCESS;
3633
3634	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3635	/*
3636	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3637	* out the shadow parts when the guest modifies its tables.
3638	*/
3639	Assert(!pgmMapAreMappingsEnabled(pVM));
3640	return VINF_SUCCESS;
3641
3642	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3643
3644	# ifndef PGM_WITHOUT_MAPPINGS
3645	/*
3646	* Check for and resolve conflicts with our guest mappings if they
3647	* are enabled and not fixed.
3648	*/
3649	if (pgmMapAreMappingsFloating(pVM))
3650	{
3651	int rc = pgmMapResolveConflicts(pVM);
3652	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3653	if (rc == VINF_PGM_SYNC_CR3)
3654	{
3655	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3656	return VINF_PGM_SYNC_CR3;
3657	}
3658	}
3659	# else
3660	Assert(!pgmMapAreMappingsEnabled(pVM));
3661	# endif
3662	return VINF_SUCCESS;
3663	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3664	}
3665
3666
3667
3668
3669	#ifdef VBOX_STRICT
3670	# ifdef IN_RC
3671	# undef AssertMsgFailed
3672	# define AssertMsgFailed Log
3673	# endif
3674
3675	/**
3676	* Checks that the shadow page table is in sync with the guest one.
3677	*
3678	* @returns The number of errors.
3679	* @param pVM The virtual machine.
3680	* @param pVCpu Pointer to the VMCPU.
3681	* @param cr3 Guest context CR3 register.
3682	* @param cr4 Guest context CR4 register.
3683	* @param GCPtr Where to start. Defaults to 0.
3684	* @param cb How much to check. Defaults to everything.
3685	*/
3686	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3687	{
3688	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3689	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3690	return 0;
3691	#else
3692	unsigned cErrors = 0;
3693	PVM pVM = pVCpu->CTX_SUFF(pVM);
3694	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3695
3696	# if PGM_GST_TYPE == PGM_TYPE_PAE
3697	/** @todo currently broken; crashes below somewhere */
3698	AssertFailed();
3699	# endif
3700
3701	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3702	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3703	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3704
3705	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3706	PPGMCPU pPGM = &pVCpu->pgm.s;
3707	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3708	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3709	# ifndef IN_RING0
3710	RTHCPHYS HCPhys; /* general usage. */
3711	# endif
3712	int rc;
3713
3714	/*
3715	* Check that the Guest CR3 and all its mappings are correct.
3716	*/
3717	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3718	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3719	false);
3720	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3721	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3722	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3723	# else
3724	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3725	# endif
3726	AssertRCReturn(rc, 1);
3727	HCPhys = NIL_RTHCPHYS;
3728	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3729	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3730	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3731	pgmGstGet32bitPDPtr(pVCpu);
3732	RTGCPHYS GCPhys;
3733	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3734	AssertRCReturn(rc, 1);
3735	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3736	# endif
3737	# endif /* !IN_RING0 */
3738
3739	/*
3740	* Get and check the Shadow CR3.
3741	*/
3742	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3743	unsigned cPDEs = X86_PG_ENTRIES;
3744	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3745	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3746	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3747	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3748	# else
3749	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3750	# endif
3751	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3752	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3753	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3754	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3755	# endif
3756	if (cb != ~(RTGCPTR)0)
3757	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3758
3759	/** @todo call the other two PGMAssert() functions. /
3760
3761	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3762	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3763
3764	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3765	{
3766	PPGMPOOLPAGE pShwPdpt = NULL;
3767	PX86PML4E pPml4eSrc;
3768	PX86PML4E pPml4eDst;
3769	RTGCPHYS GCPhysPdptSrc;
3770
3771	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3772	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3773
3774	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3775	if (!pPml4eDst->n.u1Present)
3776	{
3777	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3778	continue;
3779	}
3780
3781	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3782	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3783
3784	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3785	{
3786	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3787	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3788	cErrors++;
3789	continue;
3790	}
3791
3792	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3793	{
3794	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3795	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3796	cErrors++;
3797	continue;
3798	}
3799
3800	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3801	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3802	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3803	{
3804	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3805	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3806	cErrors++;
3807	continue;
3808	}
3809	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3810	{
3811	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3812
3813	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3814	/*
3815	* Check the PDPTEs too.
3816	*/
3817	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3818
3819	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3820	{
3821	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3822	PPGMPOOLPAGE pShwPde = NULL;
3823	PX86PDPE pPdpeDst;
3824	RTGCPHYS GCPhysPdeSrc;
3825	X86PDPE PdpeSrc;
3826	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3827	# if PGM_GST_TYPE == PGM_TYPE_PAE
3828	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3829	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3830	# else
3831	PX86PML4E pPml4eSrcIgn;
3832	PX86PDPT pPdptDst;
3833	PX86PDPAE pPDDst;
3834	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3835
3836	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3837	if (rc != VINF_SUCCESS)
3838	{
3839	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3840	GCPtr += 512 * _2M;
3841	continue; /* next PDPTE */
3842	}
3843	Assert(pPDDst);
3844	# endif
3845	Assert(iPDSrc == 0);
3846
3847	pPdpeDst = &pPdptDst->a[iPdpt];
3848
3849	if (!pPdpeDst->n.u1Present)
3850	{
3851	GCPtr += 512 * _2M;
3852	continue; /* next PDPTE */
3853	}
3854
3855	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3856	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3857
3858	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3859	{
3860	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3861	GCPtr += 512 * _2M;
3862	cErrors++;
3863	continue;
3864	}
3865
3866	if (GCPhysPdeSrc != pShwPde->GCPhys)
3867	{
3868	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3869	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3870	# else
3871	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3872	# endif
3873	GCPtr += 512 * _2M;
3874	cErrors++;
3875	continue;
3876	}
3877
3878	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3879	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3880	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3881	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3882	{
3883	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3884	GCPtr += 512 * _2M;
3885	cErrors++;
3886	continue;
3887	}
3888	# endif
3889
3890	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3891	{
3892	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3893	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3894	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3895	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3896	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3897	# endif
3898	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3899	/*
3900	* Iterate the shadow page directory.
3901	*/
3902	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3903	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3904
3905	for (;
3906	iPDDst < cPDEs;
3907	iPDDst++, GCPtr += cIncrement)
3908	{
3909	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3910	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3911	# else
3912	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3913	# endif
3914	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3915	{
3916	Assert(pgmMapAreMappingsEnabled(pVM));
3917	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3918	{
3919	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3920	cErrors++;
3921	continue;
3922	}
3923	}
3924	else if ( (PdeDst.u & X86_PDE_P)
3925	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3926	)
3927	{
3928	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3929	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3930	if (!pPoolPage)
3931	{
3932	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
3933	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3934	cErrors++;
3935	continue;
3936	}
3937	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
3938
3939	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3940	{
3941	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
3942	GCPtr, (uint64_t)PdeDst.u));
3943	cErrors++;
3944	}
3945
3946	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3947	{
3948	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
3949	GCPtr, (uint64_t)PdeDst.u));
3950	cErrors++;
3951	}
3952
3953	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3954	if (!PdeSrc.n.u1Present)
3955	{
3956	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3957	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3958	cErrors++;
3959	continue;
3960	}
3961
3962	if ( !PdeSrc.b.u1Size
3963	\|\| !fBigPagesSupported)
3964	{
3965	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
3966	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3967	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
3968	# endif
3969	}
3970	else
3971	{
3972	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3973	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3974	{
3975	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3976	GCPtr, (uint64_t)PdeSrc.u));
3977	cErrors++;
3978	continue;
3979	}
3980	# endif
3981	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
3982	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3983	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
3984	# endif
3985	}
3986
3987	if ( pPoolPage->enmKind
3988	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3989	{
3990	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
3991	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3992	cErrors++;
3993	}
3994
3995	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
3996	if (!pPhysPage)
3997	{
3998	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
3999	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4000	cErrors++;
4001	continue;
4002	}
4003
4004	if (GCPhysGst != pPoolPage->GCPhys)
4005	{
4006	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4007	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4008	cErrors++;
4009	continue;
4010	}
4011
4012	if ( !PdeSrc.b.u1Size
4013	\|\| !fBigPagesSupported)
4014	{
4015	/*
4016	* Page Table.
4017	*/
4018	const GSTPT *pPTSrc;
4019	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4020	&pPTSrc);
4021	if (RT_FAILURE(rc))
4022	{
4023	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4024	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4025	cErrors++;
4026	continue;
4027	}
4028	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4029	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4030	{
4031	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4032	// (This problem will go away when/if we shadow multiple CR3s.)
4033	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4034	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4035	cErrors++;
4036	continue;
4037	}
4038	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4039	{
4040	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4041	GCPtr, (uint64_t)PdeDst.u));
4042	cErrors++;
4043	continue;
4044	}
4045
4046	/* iterate the page table. */
4047	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4048	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4049	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4050	# else
4051	const unsigned offPTSrc = 0;
4052	# endif
4053	for (unsigned iPT = 0, off = 0;
4054	iPT < RT_ELEMENTS(pPTDst->a);
4055	iPT++, off += PAGE_SIZE)
4056	{
4057	const SHWPTE PteDst = pPTDst->a[iPT];
4058
4059	/* skip not-present and dirty tracked entries. */
4060	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4061	continue;
4062	Assert(SHW_PTE_IS_P(PteDst));
4063
4064	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4065	if (!PteSrc.n.u1Present)
4066	{
4067	# ifdef IN_RING3
4068	PGMAssertHandlerAndFlagsInSync(pVM);
4069	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4070	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4071	0, 0, UINT64_MAX, 99, NULL);
4072	# endif
4073	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4074	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4075	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4076	cErrors++;
4077	continue;
4078	}
4079
4080	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4081	# if 1 /** @todo sync accessed bit properly... */
4082	fIgnoreFlags \|= X86_PTE_A;
4083	# endif
4084
4085	/* match the physical addresses */
4086	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4087	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4088
4089	# ifdef IN_RING3
4090	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4091	if (RT_FAILURE(rc))
4092	{
4093	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4094	{
4095	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4096	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4097	cErrors++;
4098	continue;
4099	}
4100	}
4101	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4102	{
4103	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4104	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4105	cErrors++;
4106	continue;
4107	}
4108	# endif
4109
4110	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4111	if (!pPhysPage)
4112	{
4113	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4114	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4115	{
4116	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4117	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4118	cErrors++;
4119	continue;
4120	}
4121	# endif
4122	if (SHW_PTE_IS_RW(PteDst))
4123	{
4124	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4125	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4126	cErrors++;
4127	}
4128	fIgnoreFlags \|= X86_PTE_RW;
4129	}
4130	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4131	{
4132	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4133	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4134	cErrors++;
4135	continue;
4136	}
4137
4138	/* flags */
4139	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4140	{
4141	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4142	{
4143	if (SHW_PTE_IS_RW(PteDst))
4144	{
4145	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4146	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4147	cErrors++;
4148	continue;
4149	}
4150	fIgnoreFlags \|= X86_PTE_RW;
4151	}
4152	else
4153	{
4154	if ( SHW_PTE_IS_P(PteDst)
4155	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4156	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4157	# endif
4158	)
4159	{
4160	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4161	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4162	cErrors++;
4163	continue;
4164	}
4165	fIgnoreFlags \|= X86_PTE_P;
4166	}
4167	}
4168	else
4169	{
4170	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4171	{
4172	if (SHW_PTE_IS_RW(PteDst))
4173	{
4174	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4175	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4176	cErrors++;
4177	continue;
4178	}
4179	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4180	{
4181	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4182	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4183	cErrors++;
4184	continue;
4185	}
4186	if (SHW_PTE_IS_D(PteDst))
4187	{
4188	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4189	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4190	cErrors++;
4191	}
4192	# if 0 /** @todo sync access bit properly... */
4193	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4194	{
4195	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4196	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4197	cErrors++;
4198	}
4199	fIgnoreFlags \|= X86_PTE_RW;
4200	# else
4201	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4202	# endif
4203	}
4204	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4205	{
4206	/* access bit emulation (not implemented). */
4207	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4208	{
4209	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4210	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4211	cErrors++;
4212	continue;
4213	}
4214	if (!SHW_PTE_IS_A(PteDst))
4215	{
4216	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4217	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4218	cErrors++;
4219	}
4220	fIgnoreFlags \|= X86_PTE_P;
4221	}
4222	# ifdef DEBUG_sandervl
4223	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4224	# endif
4225	}
4226
4227	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4228	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4229	)
4230	{
4231	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4232	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4233	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4234	cErrors++;
4235	continue;
4236	}
4237	} /* foreach PTE */
4238	}
4239	else
4240	{
4241	/*
4242	* Big Page.
4243	*/
4244	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4245	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4246	{
4247	if (PdeDst.n.u1Write)
4248	{
4249	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4250	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4251	cErrors++;
4252	continue;
4253	}
4254	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4255	{
4256	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4257	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4258	cErrors++;
4259	continue;
4260	}
4261	# if 0 /** @todo sync access bit properly... */
4262	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4263	{
4264	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4265	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4266	cErrors++;
4267	}
4268	fIgnoreFlags \|= X86_PTE_RW;
4269	# else
4270	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4271	# endif
4272	}
4273	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4274	{
4275	/* access bit emulation (not implemented). */
4276	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4277	{
4278	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4279	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4280	cErrors++;
4281	continue;
4282	}
4283	if (!PdeDst.n.u1Accessed)
4284	{
4285	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4286	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4287	cErrors++;
4288	}
4289	fIgnoreFlags \|= X86_PTE_P;
4290	}
4291
4292	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4293	{
4294	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4295	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4296	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4297	cErrors++;
4298	}
4299
4300	/* iterate the page table. */
4301	for (unsigned iPT = 0, off = 0;
4302	iPT < RT_ELEMENTS(pPTDst->a);
4303	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4304	{
4305	const SHWPTE PteDst = pPTDst->a[iPT];
4306
4307	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4308	{
4309	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4310	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4311	cErrors++;
4312	}
4313
4314	/* skip not-present entries. */
4315	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4316	continue;
4317
4318	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4319
4320	/* match the physical addresses */
4321	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4322
4323	# ifdef IN_RING3
4324	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4325	if (RT_FAILURE(rc))
4326	{
4327	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4328	{
4329	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4330	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4331	cErrors++;
4332	}
4333	}
4334	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4335	{
4336	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4337	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4338	cErrors++;
4339	continue;
4340	}
4341	# endif
4342	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4343	if (!pPhysPage)
4344	{
4345	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4346	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4347	{
4348	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4349	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4350	cErrors++;
4351	continue;
4352	}
4353	# endif
4354	if (SHW_PTE_IS_RW(PteDst))
4355	{
4356	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4357	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4358	cErrors++;
4359	}
4360	fIgnoreFlags \|= X86_PTE_RW;
4361	}
4362	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4363	{
4364	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4365	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4366	cErrors++;
4367	continue;
4368	}
4369
4370	/* flags */
4371	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4372	{
4373	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4374	{
4375	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4376	{
4377	if (SHW_PTE_IS_RW(PteDst))
4378	{
4379	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4380	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4381	cErrors++;
4382	continue;
4383	}
4384	fIgnoreFlags \|= X86_PTE_RW;
4385	}
4386	}
4387	else
4388	{
4389	if ( SHW_PTE_IS_P(PteDst)
4390	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4391	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4392	# endif
4393	)
4394	{
4395	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4396	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4397	cErrors++;
4398	continue;
4399	}
4400	fIgnoreFlags \|= X86_PTE_P;
4401	}
4402	}
4403
4404	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4405	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4406	)
4407	{
4408	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4409	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4410	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4411	cErrors++;
4412	continue;
4413	}
4414	} /* for each PTE */
4415	}
4416	}
4417	/* not present */
4418
4419	} /* for each PDE */
4420
4421	} /* for each PDPTE */
4422
4423	} /* for each PML4E */
4424
4425	# ifdef DEBUG
4426	if (cErrors)
4427	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4428	# endif
4429	# endif /* GST is in {32BIT, PAE, AMD64} */
4430	return cErrors;
4431	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4432	}
4433	#endif /* VBOX_STRICT */
4434
4435
4436	/**
4437	* Sets up the CR3 for shadow paging
4438	*
4439	* @returns Strict VBox status code.
4440	* @retval VINF_SUCCESS.
4441	*
4442	* @param pVCpu Pointer to the VMCPU.
4443	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4444	* mask already applied.)
4445	*/
4446	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4447	{
4448	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4449
4450	/* Update guest paging info. */
4451	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4452	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4453	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4454
4455	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4456	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4457
4458	/*
4459	* Map the page CR3 points at.
4460	*/
4461	RTHCPTR HCPtrGuestCR3;
4462	RTHCPHYS HCPhysGuestCR3;
4463	pgmLock(pVM);
4464	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4465	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4466	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4467	/** @todo this needs some reworking wrt. locking? */
4468	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4469	HCPtrGuestCR3 = NIL_RTHCPTR;
4470	int rc = VINF_SUCCESS;
4471	# else
4472	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4473	# endif
4474	pgmUnlock(pVM);
4475	if (RT_SUCCESS(rc))
4476	{
4477	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4478	if (RT_SUCCESS(rc))
4479	{
4480	# ifdef IN_RC
4481	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4482	# endif
4483	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4484	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4485	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4486	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4487	# endif
4488	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4489
4490	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4491	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4492	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4493	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4494	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4495	# endif
4496	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4497	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4498
4499	/*
4500	* Map the 4 PDs too.
4501	*/
4502	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4503	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4504	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4505	{
4506	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4507	if (pGuestPDPT->a[i].n.u1Present)
4508	{
4509	RTHCPTR HCPtr;
4510	RTHCPHYS HCPhys;
4511	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4512	pgmLock(pVM);
4513	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4514	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4515	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4516	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4517	HCPtr = NIL_RTHCPTR;
4518	int rc2 = VINF_SUCCESS;
4519	# else
4520	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4521	# endif
4522	pgmUnlock(pVM);
4523	if (RT_SUCCESS(rc2))
4524	{
4525	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4526	AssertRCReturn(rc, rc);
4527
4528	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4529	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4530	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4531	# endif
4532	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4533	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4534	# ifdef IN_RC
4535	PGM_INVL_PG(pVCpu, GCPtr);
4536	# endif
4537	continue;
4538	}
4539	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4540	}
4541
4542	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4543	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4544	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4545	# endif
4546	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4547	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4548	# ifdef IN_RC
4549	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4550	# endif
4551	}
4552
4553	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4554	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4555	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4556	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4557	# endif
4558	# endif
4559	}
4560	else
4561	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4562	}
4563	else
4564	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4565
4566	#else /* prot/real stub */
4567	int rc = VINF_SUCCESS;
4568	#endif
4569
4570	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4571	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4572	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4573	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4574	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4575	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4576
4577	Assert(!pVM->pgm.s.fNestedPaging);
4578	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4579
4580	/*
4581	* Update the shadow root page as well since that's not fixed.
4582	*/
4583	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4584	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4585	PPGMPOOLPAGE pNewShwPageCR3;
4586
4587	pgmLock(pVM);
4588
4589	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4590	if (pPool->cDirtyPages)
4591	pgmPoolResetDirtyPages(pVM);
4592	# endif
4593
4594	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4595	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4596	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4597	&pNewShwPageCR3);
4598	AssertFatalRC(rc);
4599	rc = VINF_SUCCESS;
4600
4601	# ifdef IN_RC
4602	/*
4603	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4604	* state will be inconsistent! Flush important things now while
4605	* we still can and then make sure there are no ring-3 calls.
4606	*/
4607	# ifdef VBOX_WITH_REM
4608	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4609	# endif
4610	VMMRZCallRing3Disable(pVCpu);
4611	# endif
4612
4613	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4614	# ifdef IN_RING0
4615	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4616	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4617	# elif defined(IN_RC)
4618	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4619	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4620	# else
4621	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4622	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4623	# endif
4624
4625	# ifndef PGM_WITHOUT_MAPPINGS
4626	/*
4627	* Apply all hypervisor mappings to the new CR3.
4628	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4629	* make sure we check for conflicts in the new CR3 root.
4630	*/
4631	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4632	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4633	# endif
4634	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4635	AssertRCReturn(rc, rc);
4636	# endif
4637
4638	/* Set the current hypervisor CR3. */
4639	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4640	SELMShadowCR3Changed(pVM, pVCpu);
4641
4642	# ifdef IN_RC
4643	/* NOTE: The state is consistent again. */
4644	VMMRZCallRing3Enable(pVCpu);
4645	# endif
4646
4647	/* Clean up the old CR3 root. */
4648	if ( pOldShwPageCR3
4649	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4650	{
4651	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4652	# ifndef PGM_WITHOUT_MAPPINGS
4653	/* Remove the hypervisor mappings from the shadow page table. */
4654	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4655	# endif
4656	/* Mark the page as unlocked; allow flushing again. */
4657	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4658
4659	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4660	}
4661	pgmUnlock(pVM);
4662	# else
4663	NOREF(GCPhysCR3);
4664	# endif
4665
4666	return rc;
4667	}
4668
4669	/**
4670	* Unmaps the shadow CR3.
4671	*
4672	* @returns VBox status, no specials.
4673	* @param pVCpu Pointer to the VMCPU.
4674	*/
4675	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4676	{
4677	LogFlow(("UnmapCR3\n"));
4678
4679	int rc = VINF_SUCCESS;
4680	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4681
4682	/*
4683	* Update guest paging info.
4684	*/
4685	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4686	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4687	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4688	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4689	# endif
4690	pVCpu->pgm.s.pGst32BitPdRC = 0;
4691
4692	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4693	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4694	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4695	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4696	# endif
4697	pVCpu->pgm.s.pGstPaePdptRC = 0;
4698	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4699	{
4700	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4701	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4702	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4703	# endif
4704	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4705	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4706	}
4707
4708	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4709	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4710	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4711	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4712	# endif
4713
4714	#else /* prot/real mode stub */
4715	/* nothing to do */
4716	#endif
4717
4718	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4719	/*
4720	* Update shadow paging info.
4721	*/
4722	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4723	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4724	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4725
4726	# if PGM_GST_TYPE != PGM_TYPE_REAL
4727	Assert(!pVM->pgm.s.fNestedPaging);
4728	# endif
4729
4730	pgmLock(pVM);
4731
4732	# ifndef PGM_WITHOUT_MAPPINGS
4733	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4734	/* Remove the hypervisor mappings from the shadow page table. */
4735	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4736	# endif
4737
4738	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4739	{
4740	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4741
4742	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4743	if (pPool->cDirtyPages)
4744	pgmPoolResetDirtyPages(pVM);
4745	# endif
4746
4747	/* Mark the page as unlocked; allow flushing again. */
4748	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4749
4750	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4751	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4752	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4753	pVCpu->pgm.s.pShwPageCR3RC = 0;
4754	}
4755	pgmUnlock(pVM);
4756	# endif
4757	#endif /* !IN_RC*/
4758
4759	return rc;
4760	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 45312

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