PGMAllBth.h@ 45798

Last change on this file since 45798 was 45798, checked in by vboxsync, 12 years ago
Fixed up and enabled Netware WP0+RO+US hack.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 208.4 KB

Line
1	/* $Id: PGMAllBth.h 45798 2013-04-29 03:40:54Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2013 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The current CPU.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if (pGstWalk->Core.fBadPhysAddr)
124	{
125	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
126	Assert(!pGstWalk->Core.fNotPresent);
127	}
128	else if (!pGstWalk->Core.fNotPresent)
129	uNewErr \|= X86_TRAP_PF_P;
130	TRPMSetErrorCode(pVCpu, uNewErr);
131
132	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134	return VINF_EM_RAW_GUEST_TRAP;
135	}
136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139	/**
140	* Deal with a guest page fault.
141	*
142	* The caller has taken the PGM lock.
143	*
144	* @returns Strict VBox status code.
145	*
146	* @param pVCpu The current CPU.
147	* @param uErr The error code.
148	* @param pRegFrame The register frame.
149	* @param pvFault The fault address.
150	* @param pPage The guest page at @a pvFault.
151	* @param pGstWalk The guest page table walk result.
152	* @param pfLockTaken PGM lock taken here or not (out). This is true
153	* when we're called.
154	*/
155	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
158	, PGSTPTWALK pGstWalk
159	# endif
160	)
161	{
162	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
164	#endif
165	PVM pVM = pVCpu->CTX_SUFF(pVM);
166	int rc;
167
168	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169	{
170	/*
171	* Physical page access handler.
172	*/
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175	# else
176	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177	# endif
178	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179	if (pCur)
180	{
181	# ifdef PGM_SYNC_N_PAGES
182	/*
183	* If the region is write protected and we got a page not present fault, then sync
184	* the pages. If the fault was caused by a read, then restart the instruction.
185	* In case of write access continue to the GC write handler.
186	*
187	* ASSUMES that there is only one handler per page or that they have similar write properties.
188	*/
189	if ( !(uErr & X86_TRAP_PF_P)
190	&& pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
191	{
192	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
193	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
194	# else
195	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
196	# endif
197	if ( RT_FAILURE(rc)
198	\|\| !(uErr & X86_TRAP_PF_RW)
199	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
200	{
201	AssertRC(rc);
202	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
203	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
204	return rc;
205	}
206	}
207	# endif
208	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
209	/*
210	* If the access was not thru a #PF(RSVD\|...) resync the page.
211	*/
212	if ( !(uErr & X86_TRAP_PF_RSVD)
213	&& pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
214	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
215	&& pGstWalk->Core.fEffectiveRW
216	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
217	# endif
218	)
219	{
220	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
221	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
222	# else
223	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
224	# endif
225	if ( RT_FAILURE(rc)
226	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
227	{
228	AssertRC(rc);
229	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
230	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
231	return rc;
232	}
233	}
234	# endif
235
236	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
237	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
238	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
239	pvFault, GCPhysFault, pPage, uErr, pCur->enmType));
240	if (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE)
241	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
242	else
243	{
244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
245	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
246	}
247
248	if (pCur->CTX_SUFF(pfnHandler))
249	{
250	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
251	void *pvUser = pCur->CTX_SUFF(pvUser);
252	# ifdef IN_RING0
253	PFNPGMR0PHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
254	# else
255	PFNPGMRCPHYSHANDLER pfnHandler = pCur->CTX_SUFF(pfnHandler);
256	# endif
257
258	STAM_PROFILE_START(&pCur->Stat, h);
259	if (pfnHandler != pPool->CTX_SUFF(pfnAccessHandler))
260	{
261	pgmUnlock(pVM);
262	*pfLockTaken = false;
263	}
264
265	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
266
267	# ifdef VBOX_WITH_STATISTICS
268	pgmLock(pVM);
269	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
270	if (pCur)
271	STAM_PROFILE_STOP(&pCur->Stat, h);
272	pgmUnlock(pVM);
273	# endif
274	}
275	else
276	rc = VINF_EM_RAW_EMULATE_INSTR;
277
278	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
279	return rc;
280	}
281	}
282	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
283	else
284	{
285	# ifdef PGM_SYNC_N_PAGES
286	/*
287	* If the region is write protected and we got a page not present fault, then sync
288	* the pages. If the fault was caused by a read, then restart the instruction.
289	* In case of write access continue to the GC write handler.
290	*/
291	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
292	&& !(uErr & X86_TRAP_PF_P))
293	{
294	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
295	if ( RT_FAILURE(rc)
296	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
297	\|\| !(uErr & X86_TRAP_PF_RW))
298	{
299	AssertRC(rc);
300	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
301	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
302	return rc;
303	}
304	}
305	# endif
306	/*
307	* Ok, it's an virtual page access handler.
308	*
309	* Since it's faster to search by address, we'll do that first
310	* and then retry by GCPhys if that fails.
311	*/
312	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
313	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
314	* out of sync, because the page was changed without us noticing it (not-present -> present
315	* without invlpg or mov cr3, xxx).
316	*/
317	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
318	if (pCur)
319	{
320	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
321	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
322	\|\| !(uErr & X86_TRAP_PF_P)
323	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
324	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enum=%d\n",
325	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCur->enmType));
326
327	if ( pvFault - pCur->Core.Key < pCur->cb
328	&& ( uErr & X86_TRAP_PF_RW
329	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
330	{
331	# ifdef IN_RC
332	STAM_PROFILE_START(&pCur->Stat, h);
333	RTGCPTR GCPtrStart = pCur->Core.Key;
334	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
335	pgmUnlock(pVM);
336	*pfLockTaken = false;
337
338	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, pvFault - GCPtrStart);
339
340	# ifdef VBOX_WITH_STATISTICS
341	pgmLock(pVM);
342	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
343	if (pCur)
344	STAM_PROFILE_STOP(&pCur->Stat, h);
345	pgmUnlock(pVM);
346	# endif
347	# else
348	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
349	# endif
350	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
351	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
352	return rc;
353	}
354	/* Unhandled part of a monitored page */
355	Log(("Unhandled part of monitored page %RGv\n", pvFault));
356	}
357	else
358	{
359	/* Check by physical address. */
360	unsigned iPage;
361	rc = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &pCur, &iPage);
362	Assert(RT_SUCCESS(rc) \|\| !pCur);
363	if ( pCur
364	&& ( uErr & X86_TRAP_PF_RW
365	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
366	{
367	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
368	# ifdef IN_RC
369	STAM_PROFILE_START(&pCur->Stat, h);
370	RTGCPTR GCPtrStart = pCur->Core.Key;
371	CTX_MID(PFNPGM,VIRTHANDLER) pfnHandler = pCur->CTX_SUFF(pfnHandler);
372	pgmUnlock(pVM);
373	*pfLockTaken = false;
374
375	RTGCPTR off = (iPage << PAGE_SHIFT)
376	+ (pvFault & PAGE_OFFSET_MASK)
377	- (GCPtrStart & PAGE_OFFSET_MASK);
378	Assert(off < pCur->cb);
379	rc = pfnHandler(pVM, uErr, pRegFrame, pvFault, GCPtrStart, off);
380
381	# ifdef VBOX_WITH_STATISTICS
382	pgmLock(pVM);
383	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
384	if (pCur)
385	STAM_PROFILE_STOP(&pCur->Stat, h);
386	pgmUnlock(pVM);
387	# endif
388	# else
389	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
390	# endif
391	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
392	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
393	return rc;
394	}
395	}
396	}
397	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
398
399	/*
400	* There is a handled area of the page, but this fault doesn't belong to it.
401	* We must emulate the instruction.
402	*
403	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
404	* we first check if this was a page-not-present fault for a page with only
405	* write access handlers. Restart the instruction if it wasn't a write access.
406	*/
407	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
408
409	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
410	&& !(uErr & X86_TRAP_PF_P))
411	{
412	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
413	rc = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
414	# else
415	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
416	# endif
417	if ( RT_FAILURE(rc)
418	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
419	\|\| !(uErr & X86_TRAP_PF_RW))
420	{
421	AssertRC(rc);
422	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
423	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
424	return rc;
425	}
426	}
427
428	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
429	* It's writing to an unhandled part of the LDT page several million times.
430	*/
431	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
432	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
433	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
434	return rc;
435	} /* if any kind of handler */
436
437
438	/**
439	* #PF Handler for raw-mode guest execution.
440	*
441	* @returns VBox status code (appropriate for trap handling and GC return).
442	*
443	* @param pVCpu Pointer to the VMCPU.
444	* @param uErr The trap error code.
445	* @param pRegFrame Trap register frame.
446	* @param pvFault The fault address.
447	* @param pfLockTaken PGM lock taken here or not (out)
448	*/
449	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
450	{
451	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
452
453	*pfLockTaken = false;
454
455	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
456	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
457	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
458	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
459	int rc;
460
461	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
462	/*
463	* Walk the guest page translation tables and check if it's a guest fault.
464	*/
465	GSTPTWALK GstWalk;
466	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
467	if (RT_FAILURE_NP(rc))
468	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
469
470	/* assert some GstWalk sanity. */
471	# if PGM_GST_TYPE == PGM_TYPE_AMD64
472	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
473	# endif
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
475	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
476	# endif
477	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
478	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
479	Assert(GstWalk.Core.fSucceeded);
480
481	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
482	{
483	if ( ( (uErr & X86_TRAP_PF_RW)
484	&& !GstWalk.Core.fEffectiveRW
485	&& ( (uErr & X86_TRAP_PF_US)
486	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
487	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
488	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
489	)
490	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
491	}
492
493	/*
494	* Set the accessed and dirty flags.
495	*/
496	# if PGM_GST_TYPE == PGM_TYPE_AMD64
497	GstWalk.Pml4e.u \|= X86_PML4E_A;
498	GstWalk.pPml4e->u \|= X86_PML4E_A;
499	GstWalk.Pdpe.u \|= X86_PDPE_A;
500	GstWalk.pPdpe->u \|= X86_PDPE_A;
501	# endif
502	if (GstWalk.Core.fBigPage)
503	{
504	Assert(GstWalk.Pde.b.u1Size);
505	if (uErr & X86_TRAP_PF_RW)
506	{
507	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
508	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
509	}
510	else
511	{
512	GstWalk.Pde.u \|= X86_PDE4M_A;
513	GstWalk.pPde->u \|= X86_PDE4M_A;
514	}
515	}
516	else
517	{
518	Assert(!GstWalk.Pde.b.u1Size);
519	GstWalk.Pde.u \|= X86_PDE_A;
520	GstWalk.pPde->u \|= X86_PDE_A;
521	if (uErr & X86_TRAP_PF_RW)
522	{
523	# ifdef VBOX_WITH_STATISTICS
524	if (!GstWalk.Pte.n.u1Dirty)
525	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
526	else
527	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
528	# endif
529	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
530	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
531	}
532	else
533	{
534	GstWalk.Pte.u \|= X86_PTE_A;
535	GstWalk.pPte->u \|= X86_PTE_A;
536	}
537	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
538	}
539	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
540	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
541	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
542	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
543	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544
545	/* Take the big lock now. */
546	*pfLockTaken = true;
547	pgmLock(pVM);
548
549	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
550	/*
551	* If it is a reserved bit fault we know that it is an MMIO (access
552	* handler) related fault and can skip some 200 lines of code.
553	*/
554	if (uErr & X86_TRAP_PF_RSVD)
555	{
556	Assert(uErr & X86_TRAP_PF_P);
557	PPGMPAGE pPage;
558	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
559	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
560	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
561	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
562	pfLockTaken, &GstWalk));
563	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
564	# else
565	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
566	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
567	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
568	pfLockTaken));
569	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
570	# endif
571	AssertRC(rc);
572	PGM_INVL_PG(pVCpu, pvFault);
573	return rc; /* Restart with the corrected entry. */
574	}
575	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
576
577	/*
578	* Fetch the guest PDE, PDPE and PML4E.
579	*/
580	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
581	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
582	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
583
584	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
585	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
586	PX86PDPAE pPDDst;
587	# if PGM_GST_TYPE == PGM_TYPE_PAE
588	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
589	# else
590	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
591	# endif
592	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
593
594	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
595	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
596	PX86PDPAE pPDDst;
597	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
598	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
599	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
600	# else
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
602	# endif
603	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
604
605	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
606	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
607	PEPTPD pPDDst;
608	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
609	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
610	# endif
611	Assert(pPDDst);
612
613	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
614	/*
615	* Dirty page handling.
616	*
617	* If we successfully correct the write protection fault due to dirty bit
618	* tracking, then return immediately.
619	*/
620	if (uErr & X86_TRAP_PF_RW) /* write fault? */
621	{
622	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
623	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
624	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
626	{
627	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
628	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
629	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
630	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
631	LogBird(("Trap0eHandler: returns VINF_SUCCESS\n"));
632	return VINF_SUCCESS;
633	}
634	//AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - triggers with smp w7 guests.
635	//AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto.
636	}
637
638	# if 0 /* rarely useful; leave for debugging. */
639	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
640	# endif
641	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
642
643	/*
644	* A common case is the not-present error caused by lazy page table syncing.
645	*
646	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
647	* here so we can safely assume that the shadow PT is present when calling
648	* SyncPage later.
649	*
650	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
651	* of mapping conflict and defer to SyncCR3 in R3.
652	* (Again, we do NOT support access handlers for non-present guest pages.)
653	*
654	*/
655	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
656	Assert(GstWalk.Pde.n.u1Present);
657	# endif
658	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
659	&& !pPDDst->a[iPDDst].n.u1Present)
660	{
661	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
662	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
663	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
664	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
665	# else
666	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
667	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
668	# endif
669	if (RT_SUCCESS(rc))
670	return rc;
671	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
672	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
673	return VINF_PGM_SYNC_CR3;
674	}
675
676	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
677	/*
678	* Check if this address is within any of our mappings.
679	*
680	* This is very fast and it's gonna save us a bit of effort below and prevent
681	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
682	* (BTW, it's impossible to have physical access handlers in a mapping.)
683	*/
684	if (pgmMapAreMappingsEnabled(pVM))
685	{
686	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
687	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
688	{
689	if (pvFault < pMapping->GCPtr)
690	break;
691	if (pvFault - pMapping->GCPtr < pMapping->cb)
692	{
693	/*
694	* The first thing we check is if we've got an undetected conflict.
695	*/
696	if (pgmMapAreMappingsFloating(pVM))
697	{
698	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
699	while (iPT-- > 0)
700	if (GstWalk.pPde[iPT].n.u1Present)
701	{
702	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
703	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
704	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
705	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
706	return VINF_PGM_SYNC_CR3;
707	}
708	}
709
710	/*
711	* Check if the fault address is in a virtual page access handler range.
712	*/
713	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers, pvFault);
714	if ( pCur
715	&& pvFault - pCur->Core.Key < pCur->cb
716	&& uErr & X86_TRAP_PF_RW)
717	{
718	# ifdef IN_RC
719	STAM_PROFILE_START(&pCur->Stat, h);
720	pgmUnlock(pVM);
721	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
722	pgmLock(pVM);
723	STAM_PROFILE_STOP(&pCur->Stat, h);
724	# else
725	AssertFailed();
726	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
727	# endif
728	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
729	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
730	return rc;
731	}
732
733	/*
734	* Pretend we're not here and let the guest handle the trap.
735	*/
736	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
737	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
738	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
739	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
740	return VINF_EM_RAW_GUEST_TRAP;
741	}
742	}
743	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
745
746	/*
747	* Check if this fault address is flagged for special treatment,
748	* which means we'll have to figure out the physical address and
749	* check flags associated with it.
750	*
751	* ASSUME that we can limit any special access handling to pages
752	* in page tables which the guest believes to be present.
753	*/
754	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
755	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
756	# else
757	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
758	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
759	PPGMPAGE pPage;
760	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
761	if (RT_FAILURE(rc))
762	{
763	/*
764	* When the guest accesses invalid physical memory (e.g. probing
765	* of RAM or accessing a remapped MMIO range), then we'll fall
766	* back to the recompiler to emulate the instruction.
767	*/
768	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
769	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
770	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
771	return VINF_EM_RAW_EMULATE_INSTR;
772	}
773
774	/*
775	* Any handlers for this page?
776	*/
777	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
778	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
779	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
780	&GstWalk));
781	# else
782	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
783	# endif
784
785	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTimeOutOfSync, c);
786
787	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
788	if (uErr & X86_TRAP_PF_P)
789	{
790	/*
791	* The page isn't marked, but it might still be monitored by a virtual page access handler.
792	* (ASSUMES no temporary disabling of virtual handlers.)
793	*/
794	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
795	* we should correct both the shadow page table and physical memory flags, and not only check for
796	* accesses within the handler region but for access to pages with virtual handlers. */
797	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
798	if (pCur)
799	{
800	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
801	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
802	\|\| !(uErr & X86_TRAP_PF_P)
803	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
804	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enum=%d\n", pvFault, GCPhys, pPage, uErr, pCur->enmType));
805
806	if ( pvFault - pCur->Core.Key < pCur->cb
807	&& ( uErr & X86_TRAP_PF_RW
808	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
809	{
810	# ifdef IN_RC
811	STAM_PROFILE_START(&pCur->Stat, h);
812	pgmUnlock(pVM);
813	rc = pCur->CTX_SUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->Core.Key, pvFault - pCur->Core.Key);
814	pgmLock(pVM);
815	STAM_PROFILE_STOP(&pCur->Stat, h);
816	# else
817	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
818	# endif
819	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
820	return rc;
821	}
822	}
823	}
824	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
825
826	/*
827	* We are here only if page is present in Guest page tables and
828	* trap is not handled by our handlers.
829	*
830	* Check it for page out-of-sync situation.
831	*/
832	if (!(uErr & X86_TRAP_PF_P))
833	{
834	/*
835	* Page is not present in our page tables. Try to sync it!
836	*/
837	if (uErr & X86_TRAP_PF_US)
838	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
839	else /* supervisor */
840	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
841
842	if (PGM_PAGE_IS_BALLOONED(pPage))
843	{
844	/* Emulate reads from ballooned pages as they are not present in
845	our shadow page tables. (Required for e.g. Solaris guests; soft
846	ecc, random nr generator.) */
847	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
848	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
849	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
850	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
851	return rc;
852	}
853
854	# if defined(LOG_ENABLED) && !defined(IN_RING0)
855	RTGCPHYS GCPhys2;
856	uint64_t fPageGst2;
857	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
858	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
859	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
860	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
861	# else
862	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
863	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
864	# endif
865	# endif /* LOG_ENABLED */
866
867	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
868	if ( !GstWalk.Core.fEffectiveUS
869	&& CSAMIsEnabled(pVM)
870	&& CPUMGetGuestCPL(pVCpu) == 0)
871	{
872	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
873	if ( pvFault == (RTGCPTR)pRegFrame->eip
874	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
875	# ifdef CSAM_DETECT_NEW_CODE_PAGES
876	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
877	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
878	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
879	)
880	{
881	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
882	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
883	if (rc != VINF_SUCCESS)
884	{
885	/*
886	* CSAM needs to perform a job in ring 3.
887	*
888	* Sync the page before going to the host context; otherwise we'll end up in a loop if
889	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
890	*/
891	LogFlow(("CSAM ring 3 job\n"));
892	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
893	AssertRC(rc2);
894
895	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
896	return rc;
897	}
898	}
899	# ifdef CSAM_DETECT_NEW_CODE_PAGES
900	else if ( uErr == X86_TRAP_PF_RW
901	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
902	&& pRegFrame->ecx < 0x10000)
903	{
904	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
905	* to detect loading of new code pages.
906	*/
907
908	/*
909	* Decode the instruction.
910	*/
911	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
912	uint32_t cbOp;
913	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
914
915	/* For now we'll restrict this to rep movsw/d instructions */
916	if ( rc == VINF_SUCCESS
917	&& pDis->pCurInstr->opcode == OP_MOVSWD
918	&& (pDis->prefix & DISPREFIX_REP))
919	{
920	CSAMMarkPossibleCodePage(pVM, pvFault);
921	}
922	}
923	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
924
925	/*
926	* Mark this page as safe.
927	*/
928	/** @todo not correct for pages that contain both code and data!! */
929	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
930	CSAMMarkPage(pVM, pvFault, true);
931	}
932	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
933	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
934	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
935	# else
936	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
937	# endif
938	if (RT_SUCCESS(rc))
939	{
940	/* The page was successfully synced, return to the guest. */
941	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
942	return VINF_SUCCESS;
943	}
944	}
945	else /* uErr & X86_TRAP_PF_P: */
946	{
947	/*
948	* Write protected pages are made writable when the guest makes the
949	* first write to it. This happens for pages that are shared, write
950	* monitored or not yet allocated.
951	*
952	* We may also end up here when CR0.WP=0 in the guest.
953	*
954	* Also, a side effect of not flushing global PDEs are out of sync
955	* pages due to physical monitored regions, that are no longer valid.
956	* Assume for now it only applies to the read/write flag.
957	*/
958	if (uErr & X86_TRAP_PF_RW)
959	{
960	/*
961	* Check if it is a read-only page.
962	*/
963	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
964	{
965	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
966	Assert(!PGM_PAGE_IS_ZERO(pPage));
967	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
968	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
969
970	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
971	if (rc != VINF_SUCCESS)
972	{
973	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
974	return rc;
975	}
976	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
977	return VINF_EM_NO_MEMORY;
978	}
979
980	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
981	/*
982	* Check to see if we need to emulate the instruction if CR0.WP=0.
983	*/
984	if ( !GstWalk.Core.fEffectiveRW
985	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
986	&& CPUMGetGuestCPL(pVCpu) < 3)
987	{
988	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
989
990	/*
991	* The Netware WP0+RO+US hack.
992	*
993	* Netware sometimes(/always?) runs with WP0. It has been observed doing
994	* accessive write accesses to pages which are mapped with US=1 and RW=0
995	* while WP=0. This causes a lot of exits and extremely slow execution.
996	* To avoid trapping and emulating every write here, we change the shadow
997	* page table entry to map it as US=0 and RW=1 until user mode tries to
998	* access it again (see further below). We count these shadow page table
999	* changes so we can avoid having to clear the page pool every time the WP
1000	* bit changes to 1 (see PGMCr0WpEnabled()).
1001	*/
1002	if ( GstWalk.Core.fEffectiveUS
1003	&& !GstWalk.Core.fBigPage
1004	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1005	{
1006	/* Temorarily change the page to a RW super visor page. We'll trap
1007	and switch it back when user mode tries to read from it again.
1008	(See further down.) */
1009	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1010	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, PGM_MK_PG_IS_WRITE_FAULT);
1011	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1012	{
1013	PGM_INVL_PG(pVCpu, pvFault);
1014	pVCpu->pgm.s.cNetwareWp0Hacks++;
1015	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1016	return rc;
1017	}
1018	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1019	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1020	}
1021
1022	/* Interpret the access. */
1023	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1024	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x)\n", pvFault, uErr));
1025	if (RT_SUCCESS(rc))
1026	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1027	else
1028	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1029	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1030	return rc;
1031	}
1032	# endif
1033	/// @todo count the above case; else
1034	if (uErr & X86_TRAP_PF_US)
1035	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1036	else /* supervisor */
1037	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1038
1039	/*
1040	* Sync the page.
1041	*
1042	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1043	* page is not present, which is not true in this case.
1044	*/
1045	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1046	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1047	# else
1048	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1049	# endif
1050	if (RT_SUCCESS(rc))
1051	{
1052	/*
1053	* Page was successfully synced, return to guest but invalidate
1054	* the TLB first as the page is very likely to be in it.
1055	*/
1056	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1057	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1058	# else
1059	PGM_INVL_PG(pVCpu, pvFault);
1060	# endif
1061	# ifdef VBOX_STRICT
1062	RTGCPHYS GCPhys2;
1063	uint64_t fPageGst;
1064	if (!pVM->pgm.s.fNestedPaging)
1065	{
1066	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1067	AssertMsg(RT_SUCCESS(rc) && (fPageGst & X86_PTE_RW), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1068	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1069	}
1070	uint64_t fPageShw;
1071	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1072	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1073	("rc=%Rrc fPageShw=%RX64\n", rc, fPageShw));
1074	# endif /* VBOX_STRICT */
1075	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1076	return VINF_SUCCESS;
1077	}
1078	}
1079	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1080	/*
1081	* Check for Netware WP0+RO+US hack from above and undo it when user
1082	* mode accesses the page again.
1083	*/
1084	else if ( !GstWalk.Core.fEffectiveRW
1085	&& GstWalk.Core.fEffectiveUS
1086	&& GstWalk.Core.fBigPage
1087	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1088	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1089	&& CPUMGetGuestCPL(pVCpu) == 3
1090	&& pVM->cCpus == 1
1091	)
1092	{
1093	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1094	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1095	if (RT_SUCCESS(rc))
1096	{
1097	PGM_INVL_PG(pVCpu, pvFault);
1098	pVCpu->pgm.s.cNetwareWp0Hacks--;
1099	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1100	return VINF_SUCCESS;
1101	}
1102	}
1103	# endif /* PGM_WITH_PAGING */
1104
1105	/** @todo else: why are we here? */
1106
1107	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1108	/*
1109	* Check for VMM page flags vs. Guest page flags consistency.
1110	* Currently only for debug purposes.
1111	*/
1112	if (RT_SUCCESS(rc))
1113	{
1114	/* Get guest page flags. */
1115	uint64_t fPageGst;
1116	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1117	if (RT_SUCCESS(rc))
1118	{
1119	uint64_t fPageShw;
1120	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1121
1122	/*
1123	* Compare page flags.
1124	* Note: we have AVL, A, D bits desynced.
1125	*/
1126	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1127	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
1128	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64\n",
1129	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst));
1130	}
1131	else
1132	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1133	}
1134	else
1135	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1137	}
1138
1139
1140	/*
1141	* If we get here it is because something failed above, i.e. most like guru
1142	* meditiation time.
1143	*/
1144	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1145	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1146	return rc;
1147
1148	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1149	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1150	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1151	return VERR_PGM_NOT_USED_IN_MODE;
1152	# endif
1153	}
1154	#endif /* !IN_RING3 */
1155
1156
1157	/**
1158	* Emulation of the invlpg instruction.
1159	*
1160	*
1161	* @returns VBox status code.
1162	*
1163	* @param pVCpu Pointer to the VMCPU.
1164	* @param GCPtrPage Page to invalidate.
1165	*
1166	* @remark ASSUMES that the guest is updating before invalidating. This order
1167	* isn't required by the CPU, so this is speculative and could cause
1168	* trouble.
1169	* @remark No TLB shootdown is done on any other VCPU as we assume that
1170	* invlpg emulation is the only reason for calling this function.
1171	* (The guest has to shoot down TLB entries on other CPUs itself)
1172	* Currently true, but keep in mind!
1173	*
1174	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1175	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1176	*/
1177	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1178	{
1179	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1180	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1181	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1182	int rc;
1183	PVM pVM = pVCpu->CTX_SUFF(pVM);
1184	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1185
1186	PGM_LOCK_ASSERT_OWNER(pVM);
1187
1188	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1189
1190	/*
1191	* Get the shadow PD entry and skip out if this PD isn't present.
1192	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1193	*/
1194	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1195	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1196	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1197
1198	/* Fetch the pgm pool shadow descriptor. */
1199	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1200	Assert(pShwPde);
1201
1202	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1203	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1204	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1205
1206	/* If the shadow PDPE isn't present, then skip the invalidate. */
1207	if (!pPdptDst->a[iPdpt].n.u1Present)
1208	{
1209	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1210	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1211	PGM_INVL_PG(pVCpu, GCPtrPage);
1212	return VINF_SUCCESS;
1213	}
1214
1215	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1216	PPGMPOOLPAGE pShwPde = NULL;
1217	PX86PDPAE pPDDst;
1218
1219	/* Fetch the pgm pool shadow descriptor. */
1220	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1221	AssertRCSuccessReturn(rc, rc);
1222	Assert(pShwPde);
1223
1224	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1225	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1226
1227	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1228	/* PML4 */
1229	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1230	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1231	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1232	PX86PDPAE pPDDst;
1233	PX86PDPT pPdptDst;
1234	PX86PML4E pPml4eDst;
1235	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1236	if (rc != VINF_SUCCESS)
1237	{
1238	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1240	PGM_INVL_PG(pVCpu, GCPtrPage);
1241	return VINF_SUCCESS;
1242	}
1243	Assert(pPDDst);
1244
1245	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1246	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1247
1248	if (!pPdpeDst->n.u1Present)
1249	{
1250	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1251	PGM_INVL_PG(pVCpu, GCPtrPage);
1252	return VINF_SUCCESS;
1253	}
1254
1255	/* Fetch the pgm pool shadow descriptor. */
1256	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1257	Assert(pShwPde);
1258
1259	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1260
1261	const SHWPDE PdeDst = *pPdeDst;
1262	if (!PdeDst.n.u1Present)
1263	{
1264	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1265	PGM_INVL_PG(pVCpu, GCPtrPage);
1266	return VINF_SUCCESS;
1267	}
1268
1269	/*
1270	* Get the guest PD entry and calc big page.
1271	*/
1272	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1273	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1274	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1275	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1276	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1277	unsigned iPDSrc = 0;
1278	# if PGM_GST_TYPE == PGM_TYPE_PAE
1279	X86PDPE PdpeSrcIgn;
1280	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1281	# else /* AMD64 */
1282	PX86PML4E pPml4eSrcIgn;
1283	X86PDPE PdpeSrcIgn;
1284	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1285	# endif
1286	GSTPDE PdeSrc;
1287
1288	if (pPDSrc)
1289	PdeSrc = pPDSrc->a[iPDSrc];
1290	else
1291	PdeSrc.u = 0;
1292	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1293	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1294
1295	# ifdef IN_RING3
1296	/*
1297	* If a CR3 Sync is pending we may ignore the invalidate page operation
1298	* depending on the kind of sync and if it's a global page or not.
1299	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1300	*/
1301	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1302	if ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1303	\|\| ( VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1304	&& fIsBigPage
1305	&& PdeSrc.b.u1Global
1306	)
1307	)
1308	# else
1309	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1310	# endif
1311	{
1312	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1313	return VINF_SUCCESS;
1314	}
1315	# endif /* IN_RING3 */
1316
1317	/*
1318	* Deal with the Guest PDE.
1319	*/
1320	rc = VINF_SUCCESS;
1321	if (PdeSrc.n.u1Present)
1322	{
1323	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1324	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write));
1325	# ifndef PGM_WITHOUT_MAPPING
1326	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1327	{
1328	/*
1329	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1330	*/
1331	Assert(pgmMapAreMappingsEnabled(pVM));
1332	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1333	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1334	}
1335	else
1336	# endif /* !PGM_WITHOUT_MAPPING */
1337	if (!fIsBigPage)
1338	{
1339	/*
1340	* 4KB - page.
1341	*/
1342	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1343	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1344
1345	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1346	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1347	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1348	# endif
1349	if (pShwPage->GCPhys == GCPhys)
1350	{
1351	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1352	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1353
1354	PGSTPT pPTSrc;
1355	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1356	if (RT_SUCCESS(rc))
1357	{
1358	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1359	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1360	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1361	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1362	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1363	GCPtrPage, PteSrc.n.u1Present,
1364	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1365	PteSrc.n.u1User & PdeSrc.n.u1User,
1366	(uint64_t)PteSrc.u,
1367	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1368	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1369	}
1370	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1371	PGM_INVL_PG(pVCpu, GCPtrPage);
1372	}
1373	else
1374	{
1375	/*
1376	* The page table address changed.
1377	*/
1378	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1379	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1380	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1381	ASMAtomicWriteSize(pPdeDst, 0);
1382	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1383	PGM_INVL_VCPU_TLBS(pVCpu);
1384	}
1385	}
1386	else
1387	{
1388	/*
1389	* 2/4MB - page.
1390	*/
1391	/* Before freeing the page, check if anything really changed. */
1392	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1393	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1394	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1395	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1396	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1397	# endif
1398	if ( pShwPage->GCPhys == GCPhys
1399	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1400	{
1401	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1402	/** @todo This test is wrong as it cannot check the G bit!
1403	* FIXME */
1404	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1405	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1406	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1407	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1408	{
1409	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1411	return VINF_SUCCESS;
1412	}
1413	}
1414
1415	/*
1416	* Ok, the page table is present and it's been changed in the guest.
1417	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1418	* We could do this for some flushes in GC too, but we need an algorithm for
1419	* deciding which 4MB pages containing code likely to be executed very soon.
1420	*/
1421	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1422	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1423	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1424	ASMAtomicWriteSize(pPdeDst, 0);
1425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1426	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1427	}
1428	}
1429	else
1430	{
1431	/*
1432	* Page directory is not present, mark shadow PDE not present.
1433	*/
1434	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1435	{
1436	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1437	ASMAtomicWriteSize(pPdeDst, 0);
1438	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1439	PGM_INVL_PG(pVCpu, GCPtrPage);
1440	}
1441	else
1442	{
1443	Assert(pgmMapAreMappingsEnabled(pVM));
1444	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1445	}
1446	}
1447	return rc;
1448
1449	#else /* guest real and protected mode */
1450	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1451	NOREF(pVCpu); NOREF(GCPtrPage);
1452	return VINF_SUCCESS;
1453	#endif
1454	}
1455
1456
1457	/**
1458	* Update the tracking of shadowed pages.
1459	*
1460	* @param pVCpu Pointer to the VMCPU.
1461	* @param pShwPage The shadow page.
1462	* @param HCPhys The physical page we is being dereferenced.
1463	* @param iPte Shadow PTE index
1464	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1465	*/
1466	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1467	RTGCPHYS GCPhysPage)
1468	{
1469	PVM pVM = pVCpu->CTX_SUFF(pVM);
1470
1471	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1472	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1473	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1474
1475	/* Use the hint we retrieved from the cached guest PT. */
1476	if (pShwPage->fDirty)
1477	{
1478	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1479
1480	Assert(pShwPage->cPresent);
1481	Assert(pPool->cPresent);
1482	pShwPage->cPresent--;
1483	pPool->cPresent--;
1484
1485	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1486	AssertRelease(pPhysPage);
1487	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1488	return;
1489	}
1490	# else
1491	NOREF(GCPhysPage);
1492	# endif
1493
1494	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1495	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1496
1497	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1498	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1499	* 2. write protect all shadowed pages. I.e. implement caching.
1500	*/
1501	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1502
1503	/*
1504	* Find the guest address.
1505	*/
1506	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1507	pRam;
1508	pRam = pRam->CTX_SUFF(pNext))
1509	{
1510	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1511	while (iPage-- > 0)
1512	{
1513	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1514	{
1515	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1516
1517	Assert(pShwPage->cPresent);
1518	Assert(pPool->cPresent);
1519	pShwPage->cPresent--;
1520	pPool->cPresent--;
1521
1522	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1523	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1524	return;
1525	}
1526	}
1527	}
1528
1529	for (;;)
1530	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1531	}
1532
1533
1534	/**
1535	* Update the tracking of shadowed pages.
1536	*
1537	* @param pVCpu Pointer to the VMCPU.
1538	* @param pShwPage The shadow page.
1539	* @param u16 The top 16-bit of the pPage->HCPhys.
1540	* @param pPage Pointer to the guest page. this will be modified.
1541	* @param iPTDst The index into the shadow table.
1542	*/
1543	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1544	{
1545	PVM pVM = pVCpu->CTX_SUFF(pVM);
1546
1547	/*
1548	* Just deal with the simple first time here.
1549	*/
1550	if (!u16)
1551	{
1552	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1553	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1554	/* Save the page table index. */
1555	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1556	}
1557	else
1558	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1559
1560	/* write back */
1561	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1562	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1563
1564	/* update statistics. */
1565	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1566	pShwPage->cPresent++;
1567	if (pShwPage->iFirstPresent > iPTDst)
1568	pShwPage->iFirstPresent = iPTDst;
1569	}
1570
1571
1572	/**
1573	* Modifies a shadow PTE to account for access handlers.
1574	*
1575	* @param pVM Pointer to the VM.
1576	* @param pPage The page in question.
1577	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1578	* A (accessed) bit so it can be emulated correctly.
1579	* @param pPteDst The shadow PTE (output). This is temporary storage and
1580	* does not need to be set atomically.
1581	*/
1582	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1583	{
1584	NOREF(pVM);
1585	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1586	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1587	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1588	{
1589	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1590	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1591	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1592	pPteDst->n.u1Present = 1;
1593	pPteDst->n.u1Execute = 1;
1594	pPteDst->n.u1IgnorePAT = 1;
1595	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1596	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1597	#else
1598	if (fPteSrc & X86_PTE_A)
1599	{
1600	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1601	SHW_PTE_SET_RO(*pPteDst);
1602	}
1603	else
1604	SHW_PTE_SET(*pPteDst, 0);
1605	#endif
1606	}
1607	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1608	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1609	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1610	&& ( BTH_IS_NP_ACTIVE(pVM)
1611	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1612	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1613	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1614	# endif
1615	)
1616	{
1617	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1618	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1619	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1620	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1621	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1622	pPteDst->n.u1Present = 0;
1623	pPteDst->n.u1Write = 1;
1624	pPteDst->n.u1Execute = 0;
1625	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1626	pPteDst->n.u3EMT = 7;
1627	# else
1628	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1629	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1630	# endif
1631	}
1632	# endif
1633	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1634	else
1635	{
1636	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1637	SHW_PTE_SET(*pPteDst, 0);
1638	}
1639	/** @todo count these kinds of entries. */
1640	}
1641
1642
1643	/**
1644	* Creates a 4K shadow page for a guest page.
1645	*
1646	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1647	* physical address. The PdeSrc argument only the flags are used. No page
1648	* structured will be mapped in this function.
1649	*
1650	* @param pVCpu Pointer to the VMCPU.
1651	* @param pPteDst Destination page table entry.
1652	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1653	* Can safely assume that only the flags are being used.
1654	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1655	* @param pShwPage Pointer to the shadow page.
1656	* @param iPTDst The index into the shadow table.
1657	*
1658	* @remark Not used for 2/4MB pages!
1659	*/
1660	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1661	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1662	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1663	#else
1664	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1665	#endif
1666	{
1667	PVM pVM = pVCpu->CTX_SUFF(pVM);
1668	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1669
1670	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1671	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1672	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1673
1674	if (pShwPage->fDirty)
1675	{
1676	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1677	PGSTPT pGstPT;
1678
1679	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1680	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1681	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1682	pGstPT->a[iPTDst].u = PteSrc.u;
1683	}
1684	#else
1685	Assert(!pShwPage->fDirty);
1686	#endif
1687
1688	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1689	if ( PteSrc.n.u1Present
1690	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1691	#endif
1692	{
1693	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1694	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1695	# endif
1696	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1697
1698	/*
1699	* Find the ram range.
1700	*/
1701	PPGMPAGE pPage;
1702	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1703	if (RT_SUCCESS(rc))
1704	{
1705	/* Ignore ballooned pages.
1706	Don't return errors or use a fatal assert here as part of a
1707	shadow sync range might included ballooned pages. */
1708	if (PGM_PAGE_IS_BALLOONED(pPage))
1709	{
1710	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1711	return;
1712	}
1713
1714	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1715	/* Make the page writable if necessary. */
1716	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1717	&& ( PGM_PAGE_IS_ZERO(pPage)
1718	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1719	\|\| ( PteSrc.n.u1Write
1720	# else
1721	\|\| ( 1
1722	# endif
1723	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1724	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1725	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1726	# endif
1727	# ifdef VBOX_WITH_PAGE_SHARING
1728	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1729	# endif
1730	)
1731	)
1732	)
1733	{
1734	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1735	AssertRC(rc);
1736	}
1737	#endif
1738
1739	/*
1740	* Make page table entry.
1741	*/
1742	SHWPTE PteDst;
1743	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1744	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1745	# else
1746	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1747	# endif
1748	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1749	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1750	else
1751	{
1752	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1753	/*
1754	* If the page or page directory entry is not marked accessed,
1755	* we mark the page not present.
1756	*/
1757	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1758	{
1759	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1760	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1761	SHW_PTE_SET(PteDst, 0);
1762	}
1763	/*
1764	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1765	* when the page is modified.
1766	*/
1767	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1768	{
1769	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1770	SHW_PTE_SET(PteDst,
1771	fGstShwPteFlags
1772	\| PGM_PAGE_GET_HCPHYS(pPage)
1773	\| PGM_PTFLAGS_TRACK_DIRTY);
1774	SHW_PTE_SET_RO(PteDst);
1775	}
1776	else
1777	#endif
1778	{
1779	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1780	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1781	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1782	PteDst.n.u1Present = 1;
1783	PteDst.n.u1Write = 1;
1784	PteDst.n.u1Execute = 1;
1785	PteDst.n.u1IgnorePAT = 1;
1786	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1787	/* PteDst.n.u1Size = 0 */
1788	#else
1789	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1790	#endif
1791	}
1792
1793	/*
1794	* Make sure only allocated pages are mapped writable.
1795	*/
1796	if ( SHW_PTE_IS_P_RW(PteDst)
1797	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1798	{
1799	/* Still applies to shared pages. */
1800	Assert(!PGM_PAGE_IS_ZERO(pPage));
1801	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1802	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1803	}
1804	}
1805
1806	/*
1807	* Keep user track up to date.
1808	*/
1809	if (SHW_PTE_IS_P(PteDst))
1810	{
1811	if (!SHW_PTE_IS_P(*pPteDst))
1812	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1813	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1814	{
1815	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1816	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1817	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1818	}
1819	}
1820	else if (SHW_PTE_IS_P(*pPteDst))
1821	{
1822	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1823	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1824	}
1825
1826	/*
1827	* Update statistics and commit the entry.
1828	*/
1829	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1830	if (!PteSrc.n.u1Global)
1831	pShwPage->fSeenNonGlobal = true;
1832	#endif
1833	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1834	return;
1835	}
1836
1837	/** @todo count these three different kinds. */
1838	Log2(("SyncPageWorker: invalid address in Pte\n"));
1839	}
1840	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1841	else if (!PteSrc.n.u1Present)
1842	Log2(("SyncPageWorker: page not present in Pte\n"));
1843	else
1844	Log2(("SyncPageWorker: invalid Pte\n"));
1845	#endif
1846
1847	/*
1848	* The page is not present or the PTE is bad. Replace the shadow PTE by
1849	* an empty entry, making sure to keep the user tracking up to date.
1850	*/
1851	if (SHW_PTE_IS_P(*pPteDst))
1852	{
1853	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1854	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1855	}
1856	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1857	}
1858
1859
1860	/**
1861	* Syncs a guest OS page.
1862	*
1863	* There are no conflicts at this point, neither is there any need for
1864	* page table allocations.
1865	*
1866	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1867	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1868	*
1869	* @returns VBox status code.
1870	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1871	* @param pVCpu Pointer to the VMCPU.
1872	* @param PdeSrc Page directory entry of the guest.
1873	* @param GCPtrPage Guest context page address.
1874	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1875	* @param uErr Fault error (X86_TRAP_PF_*).
1876	*/
1877	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1878	{
1879	PVM pVM = pVCpu->CTX_SUFF(pVM);
1880	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1881	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1882
1883	PGM_LOCK_ASSERT_OWNER(pVM);
1884
1885	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1886	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1887	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1888	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1889	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1890
1891	/*
1892	* Assert preconditions.
1893	*/
1894	Assert(PdeSrc.n.u1Present);
1895	Assert(cPages);
1896	# if 0 /* rarely useful; leave for debugging. */
1897	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1898	# endif
1899
1900	/*
1901	* Get the shadow PDE, find the shadow page table in the pool.
1902	*/
1903	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1904	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1905	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1906
1907	/* Fetch the pgm pool shadow descriptor. */
1908	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1909	Assert(pShwPde);
1910
1911	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1912	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1913	PPGMPOOLPAGE pShwPde = NULL;
1914	PX86PDPAE pPDDst;
1915
1916	/* Fetch the pgm pool shadow descriptor. */
1917	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1918	AssertRCSuccessReturn(rc2, rc2);
1919	Assert(pShwPde);
1920
1921	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1922	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1923
1924	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1925	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1926	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1927	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1928	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1929
1930	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1931	AssertRCSuccessReturn(rc2, rc2);
1932	Assert(pPDDst && pPdptDst);
1933	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1934	# endif
1935	SHWPDE PdeDst = *pPdeDst;
1936
1937	/*
1938	* - In the guest SMP case we could have blocked while another VCPU reused
1939	* this page table.
1940	* - With W7-64 we may also take this path when the A bit is cleared on
1941	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1942	* relevant TLB entries. If we're write monitoring any page mapped by
1943	* the modified entry, we may end up here with a "stale" TLB entry.
1944	*/
1945	if (!PdeDst.n.u1Present)
1946	{
1947	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1948	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1949	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1950	if (uErr & X86_TRAP_PF_P)
1951	PGM_INVL_PG(pVCpu, GCPtrPage);
1952	return VINF_SUCCESS; /* force the instruction to be executed again. */
1953	}
1954
1955	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1956	Assert(pShwPage);
1957
1958	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1959	/* Fetch the pgm pool shadow descriptor. */
1960	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1961	Assert(pShwPde);
1962	# endif
1963
1964	/*
1965	* Check that the page is present and that the shadow PDE isn't out of sync.
1966	*/
1967	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1968	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
1969	RTGCPHYS GCPhys;
1970	if (!fBigPage)
1971	{
1972	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1973	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1974	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1975	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1976	# endif
1977	}
1978	else
1979	{
1980	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1981	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1982	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1983	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1984	# endif
1985	}
1986	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
1987	if ( fPdeValid
1988	&& pShwPage->GCPhys == GCPhys
1989	&& PdeSrc.n.u1Present
1990	&& PdeSrc.n.u1User == PdeDst.n.u1User
1991	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1992	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
1993	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
1994	# endif
1995	)
1996	{
1997	/*
1998	* Check that the PDE is marked accessed already.
1999	* Since we set the accessed bit before getting here on a #PF, this
2000	* check is only meant for dealing with non-#PF'ing paths.
2001	*/
2002	if (PdeSrc.n.u1Accessed)
2003	{
2004	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2005	if (!fBigPage)
2006	{
2007	/*
2008	* 4KB Page - Map the guest page table.
2009	*/
2010	PGSTPT pPTSrc;
2011	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2012	if (RT_SUCCESS(rc))
2013	{
2014	# ifdef PGM_SYNC_N_PAGES
2015	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2016	if ( cPages > 1
2017	&& !(uErr & X86_TRAP_PF_P)
2018	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2019	{
2020	/*
2021	* This code path is currently only taken when the caller is PGMTrap0eHandler
2022	* for non-present pages!
2023	*
2024	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2025	* deal with locality.
2026	*/
2027	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2028	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2029	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2030	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2031	# else
2032	const unsigned offPTSrc = 0;
2033	# endif
2034	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2035	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2036	iPTDst = 0;
2037	else
2038	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2039
2040	for (; iPTDst < iPTDstEnd; iPTDst++)
2041	{
2042	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2043
2044	if ( pPteSrc->n.u1Present
2045	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2046	{
2047	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2048	NOREF(GCPtrCurPage);
2049	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2050	/*
2051	* Assuming kernel code will be marked as supervisor - and not as user level
2052	* and executed using a conforming code selector - And marked as readonly.
2053	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2054	*/
2055	PPGMPAGE pPage;
2056	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2057	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2058	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2059	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2060	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2061	)
2062	# endif /* else: CSAM not active */
2063	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2064	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2065	GCPtrCurPage, pPteSrc->n.u1Present,
2066	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2067	pPteSrc->n.u1User & PdeSrc.n.u1User,
2068	(uint64_t)pPteSrc->u,
2069	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2070	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2071	}
2072	}
2073	}
2074	else
2075	# endif /* PGM_SYNC_N_PAGES */
2076	{
2077	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2078	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2079	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2080	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2081	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2082	GCPtrPage, PteSrc.n.u1Present,
2083	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2084	PteSrc.n.u1User & PdeSrc.n.u1User,
2085	(uint64_t)PteSrc.u,
2086	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2087	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2088	}
2089	}
2090	else /* MMIO or invalid page: emulated in #PF handler. */
2091	{
2092	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2093	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2094	}
2095	}
2096	else
2097	{
2098	/*
2099	* 4/2MB page - lazy syncing shadow 4K pages.
2100	* (There are many causes of getting here, it's no longer only CSAM.)
2101	*/
2102	/* Calculate the GC physical address of this 4KB shadow page. */
2103	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2104	/* Find ram range. */
2105	PPGMPAGE pPage;
2106	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2107	if (RT_SUCCESS(rc))
2108	{
2109	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2110
2111	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2112	/* Try to make the page writable if necessary. */
2113	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2114	&& ( PGM_PAGE_IS_ZERO(pPage)
2115	\|\| ( PdeSrc.n.u1Write
2116	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2117	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2118	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2119	# endif
2120	# ifdef VBOX_WITH_PAGE_SHARING
2121	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2122	# endif
2123	)
2124	)
2125	)
2126	{
2127	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2128	AssertRC(rc);
2129	}
2130	# endif
2131
2132	/*
2133	* Make shadow PTE entry.
2134	*/
2135	SHWPTE PteDst;
2136	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2137	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2138	else
2139	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2140
2141	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2142	if ( SHW_PTE_IS_P(PteDst)
2143	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2144	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2145
2146	/* Make sure only allocated pages are mapped writable. */
2147	if ( SHW_PTE_IS_P_RW(PteDst)
2148	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2149	{
2150	/* Still applies to shared pages. */
2151	Assert(!PGM_PAGE_IS_ZERO(pPage));
2152	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2153	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2154	}
2155
2156	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2157
2158	/*
2159	* If the page is not flagged as dirty and is writable, then make it read-only
2160	* at PD level, so we can set the dirty bit when the page is modified.
2161	*
2162	* ASSUMES that page access handlers are implemented on page table entry level.
2163	* Thus we will first catch the dirty access and set PDE.D and restart. If
2164	* there is an access handler, we'll trap again and let it work on the problem.
2165	*/
2166	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2167	* As for invlpg, it simply frees the whole shadow PT.
2168	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2169	if ( !PdeSrc.b.u1Dirty
2170	&& PdeSrc.b.u1Write)
2171	{
2172	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2173	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2174	PdeDst.n.u1Write = 0;
2175	}
2176	else
2177	{
2178	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2179	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2180	}
2181	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2182	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2183	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2184	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2185	}
2186	else
2187	{
2188	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2189	/** @todo must wipe the shadow page table entry in this
2190	* case. */
2191	}
2192	}
2193	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2194	return VINF_SUCCESS;
2195	}
2196
2197	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2198	}
2199	else if (fPdeValid)
2200	{
2201	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2202	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2203	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2204	}
2205	else
2206	{
2207	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2208	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2209	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2210	}
2211
2212	/*
2213	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2214	* Yea, I'm lazy.
2215	*/
2216	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2217	ASMAtomicWriteSize(pPdeDst, 0);
2218
2219	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2220	PGM_INVL_VCPU_TLBS(pVCpu);
2221	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2222
2223
2224	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2225	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2226	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2227	&& !defined(IN_RC)
2228	NOREF(PdeSrc);
2229
2230	# ifdef PGM_SYNC_N_PAGES
2231	/*
2232	* Get the shadow PDE, find the shadow page table in the pool.
2233	*/
2234	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2235	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2236
2237	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2238	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2239
2240	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2241	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2242	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2243	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2244	X86PDEPAE PdeDst;
2245	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2246
2247	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2248	AssertRCSuccessReturn(rc, rc);
2249	Assert(pPDDst && pPdptDst);
2250	PdeDst = pPDDst->a[iPDDst];
2251	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2252	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2253	PEPTPD pPDDst;
2254	EPTPDE PdeDst;
2255
2256	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2257	if (rc != VINF_SUCCESS)
2258	{
2259	AssertRC(rc);
2260	return rc;
2261	}
2262	Assert(pPDDst);
2263	PdeDst = pPDDst->a[iPDDst];
2264	# endif
2265	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2266	if (!PdeDst.n.u1Present)
2267	{
2268	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2269	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2270	return VINF_SUCCESS; /* force the instruction to be executed again. */
2271	}
2272
2273	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2274	if (PdeDst.n.u1Size)
2275	{
2276	Assert(pVM->pgm.s.fNestedPaging);
2277	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2278	return VINF_SUCCESS;
2279	}
2280
2281	/* Mask away the page offset. */
2282	GCPtrPage &= ~((RTGCPTR)0xfff);
2283
2284	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2285	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2286
2287	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2288	if ( cPages > 1
2289	&& !(uErr & X86_TRAP_PF_P)
2290	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2291	{
2292	/*
2293	* This code path is currently only taken when the caller is PGMTrap0eHandler
2294	* for non-present pages!
2295	*
2296	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2297	* deal with locality.
2298	*/
2299	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2300	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2301	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2302	iPTDst = 0;
2303	else
2304	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2305	for (; iPTDst < iPTDstEnd; iPTDst++)
2306	{
2307	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2308	{
2309	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2310	\| (iPTDst << PAGE_SHIFT));
2311
2312	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2313	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2314	GCPtrCurPage,
2315	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2316	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2317
2318	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2319	break;
2320	}
2321	else
2322	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2323	}
2324	}
2325	else
2326	# endif /* PGM_SYNC_N_PAGES */
2327	{
2328	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2329	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2330	\| (iPTDst << PAGE_SHIFT));
2331
2332	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2333
2334	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2335	GCPtrPage,
2336	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2337	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2338	}
2339	return VINF_SUCCESS;
2340
2341	#else
2342	NOREF(PdeSrc);
2343	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2344	return VERR_PGM_NOT_USED_IN_MODE;
2345	#endif
2346	}
2347
2348
2349	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2350
2351	/**
2352	* CheckPageFault helper for returning a page fault indicating a non-present
2353	* (NP) entry in the page translation structures.
2354	*
2355	* @returns VINF_EM_RAW_GUEST_TRAP.
2356	* @param pVCpu Pointer to the VMCPU.
2357	* @param uErr The error code of the shadow fault. Corrections to
2358	* TRPM's copy will be made if necessary.
2359	* @param GCPtrPage For logging.
2360	* @param uPageFaultLevel For logging.
2361	*/
2362	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2363	{
2364	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2365	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2366	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2367	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2368	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2369
2370	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2371	return VINF_EM_RAW_GUEST_TRAP;
2372	}
2373
2374
2375	/**
2376	* CheckPageFault helper for returning a page fault indicating a reserved bit
2377	* (RSVD) error in the page translation structures.
2378	*
2379	* @returns VINF_EM_RAW_GUEST_TRAP.
2380	* @param pVCpu Pointer to the VMCPU.
2381	* @param uErr The error code of the shadow fault. Corrections to
2382	* TRPM's copy will be made if necessary.
2383	* @param GCPtrPage For logging.
2384	* @param uPageFaultLevel For logging.
2385	*/
2386	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2387	{
2388	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2389	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2390	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2391
2392	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2393	return VINF_EM_RAW_GUEST_TRAP;
2394	}
2395
2396
2397	/**
2398	* CheckPageFault helper for returning a page protection fault (P).
2399	*
2400	* @returns VINF_EM_RAW_GUEST_TRAP.
2401	* @param pVCpu Pointer to the VMCPU.
2402	* @param uErr The error code of the shadow fault. Corrections to
2403	* TRPM's copy will be made if necessary.
2404	* @param GCPtrPage For logging.
2405	* @param uPageFaultLevel For logging.
2406	*/
2407	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2408	{
2409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2410	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2411	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2412	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2413
2414	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2415	return VINF_EM_RAW_GUEST_TRAP;
2416	}
2417
2418
2419	/**
2420	* Handle dirty bit tracking faults.
2421	*
2422	* @returns VBox status code.
2423	* @param pVCpu Pointer to the VMCPU.
2424	* @param uErr Page fault error code.
2425	* @param pPdeSrc Guest page directory entry.
2426	* @param pPdeDst Shadow page directory entry.
2427	* @param GCPtrPage Guest context page address.
2428	*/
2429	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2430	RTGCPTR GCPtrPage)
2431	{
2432	PVM pVM = pVCpu->CTX_SUFF(pVM);
2433	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2434	NOREF(uErr);
2435
2436	PGM_LOCK_ASSERT_OWNER(pVM);
2437
2438	/*
2439	* Handle big page.
2440	*/
2441	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2442	{
2443	if ( pPdeDst->n.u1Present
2444	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2445	{
2446	SHWPDE PdeDst = *pPdeDst;
2447
2448	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2449	Assert(pPdeSrc->b.u1Write);
2450
2451	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2452	* fault again and take this path to only invalidate the entry (see below).
2453	*/
2454	PdeDst.n.u1Write = 1;
2455	PdeDst.n.u1Accessed = 1;
2456	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2457	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2458	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2459	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2460	}
2461
2462	# ifdef IN_RING0
2463	/* Check for stale TLB entry; only applies to the SMP guest case. */
2464	if ( pVM->cCpus > 1
2465	&& pPdeDst->n.u1Write
2466	&& pPdeDst->n.u1Accessed)
2467	{
2468	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2469	if (pShwPage)
2470	{
2471	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2472	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2473	if (SHW_PTE_IS_P_RW(*pPteDst))
2474	{
2475	/* Stale TLB entry. */
2476	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2477	PGM_INVL_PG(pVCpu, GCPtrPage);
2478	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2479	}
2480	}
2481	}
2482	# endif /* IN_RING0 */
2483	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2484	}
2485
2486	/*
2487	* Map the guest page table.
2488	*/
2489	PGSTPT pPTSrc;
2490	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2491	if (RT_FAILURE(rc))
2492	{
2493	AssertRC(rc);
2494	return rc;
2495	}
2496
2497	if (pPdeDst->n.u1Present)
2498	{
2499	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2500	const GSTPTE PteSrc = *pPteSrc;
2501
2502	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2503	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2504	* Our individual shadow handlers will provide more information and force a fatal exit.
2505	*/
2506	if ( !HMIsEnabled(pVM)
2507	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2508	{
2509	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2510	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2511	}
2512	#endif
2513	/*
2514	* Map shadow page table.
2515	*/
2516	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2517	if (pShwPage)
2518	{
2519	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2520	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2521	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2522	{
2523	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2524	{
2525	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2526	SHWPTE PteDst = *pPteDst;
2527
2528	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2530
2531	Assert(PteSrc.n.u1Write);
2532
2533	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2534	* entry will not harm; write access will simply fault again and
2535	* take this path to only invalidate the entry.
2536	*/
2537	if (RT_LIKELY(pPage))
2538	{
2539	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2540	{
2541	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2542	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2543	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2544	SHW_PTE_SET_RO(PteDst);
2545	}
2546	else
2547	{
2548	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2549	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2550	{
2551	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2552	AssertRC(rc);
2553	}
2554	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2555	SHW_PTE_SET_RW(PteDst);
2556	else
2557	{
2558	/* Still applies to shared pages. */
2559	Assert(!PGM_PAGE_IS_ZERO(pPage));
2560	SHW_PTE_SET_RO(PteDst);
2561	}
2562	}
2563	}
2564	else
2565	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2566
2567	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2568	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2569	PGM_INVL_PG(pVCpu, GCPtrPage);
2570	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2571	}
2572
2573	# ifdef IN_RING0
2574	/* Check for stale TLB entry; only applies to the SMP guest case. */
2575	if ( pVM->cCpus > 1
2576	&& SHW_PTE_IS_RW(*pPteDst)
2577	&& SHW_PTE_IS_A(*pPteDst))
2578	{
2579	/* Stale TLB entry. */
2580	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2581	PGM_INVL_PG(pVCpu, GCPtrPage);
2582	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2583	}
2584	# endif
2585	}
2586	}
2587	else
2588	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2589	}
2590
2591	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2592	}
2593
2594	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2595
2596
2597	/**
2598	* Sync a shadow page table.
2599	*
2600	* The shadow page table is not present in the shadow PDE.
2601	*
2602	* Handles mapping conflicts.
2603	*
2604	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2605	* conflict), and Trap0eHandler.
2606	*
2607	* A precondition for this method is that the shadow PDE is not present. The
2608	* caller must take the PGM lock before checking this and continue to hold it
2609	* when calling this method.
2610	*
2611	* @returns VBox status code.
2612	* @param pVCpu Pointer to the VMCPU.
2613	* @param iPD Page directory index.
2614	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2615	* Assume this is a temporary mapping.
2616	* @param GCPtrPage GC Pointer of the page that caused the fault
2617	*/
2618	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2619	{
2620	PVM pVM = pVCpu->CTX_SUFF(pVM);
2621	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2622
2623	#if 0 /* rarely useful; leave for debugging. */
2624	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2625	#endif
2626	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage));
2627
2628	PGM_LOCK_ASSERT_OWNER(pVM);
2629
2630	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2631	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2632	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2633	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2634	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2635
2636	int rc = VINF_SUCCESS;
2637
2638	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2639
2640	/*
2641	* Some input validation first.
2642	*/
2643	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2644
2645	/*
2646	* Get the relevant shadow PDE entry.
2647	*/
2648	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2649	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2650	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2651
2652	/* Fetch the pgm pool shadow descriptor. */
2653	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2654	Assert(pShwPde);
2655
2656	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2657	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2658	PPGMPOOLPAGE pShwPde = NULL;
2659	PX86PDPAE pPDDst;
2660	PSHWPDE pPdeDst;
2661
2662	/* Fetch the pgm pool shadow descriptor. */
2663	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2664	AssertRCSuccessReturn(rc, rc);
2665	Assert(pShwPde);
2666
2667	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2668	pPdeDst = &pPDDst->a[iPDDst];
2669
2670	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2671	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2672	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2673	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2674	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2675	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2676	AssertRCSuccessReturn(rc, rc);
2677	Assert(pPDDst);
2678	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2679	# endif
2680	SHWPDE PdeDst = *pPdeDst;
2681
2682	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2683	/* Fetch the pgm pool shadow descriptor. */
2684	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2685	Assert(pShwPde);
2686	# endif
2687
2688	# ifndef PGM_WITHOUT_MAPPINGS
2689	/*
2690	* Check for conflicts.
2691	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2692	* R3: Simply resolve the conflict.
2693	*/
2694	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2695	{
2696	Assert(pgmMapAreMappingsEnabled(pVM));
2697	# ifndef IN_RING3
2698	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2699	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2700	return VERR_ADDRESS_CONFLICT;
2701
2702	# else /* IN_RING3 */
2703	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2704	Assert(pMapping);
2705	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2706	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2707	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2708	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2709	# else
2710	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2711	# endif
2712	if (RT_FAILURE(rc))
2713	{
2714	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2715	return rc;
2716	}
2717	PdeDst = *pPdeDst;
2718	# endif /* IN_RING3 */
2719	}
2720	# endif /* !PGM_WITHOUT_MAPPINGS */
2721	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2722
2723	/*
2724	* Sync the page directory entry.
2725	*/
2726	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2727	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2728	if ( PdeSrc.n.u1Present
2729	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2730	{
2731	/*
2732	* Allocate & map the page table.
2733	*/
2734	PSHWPT pPTDst;
2735	PPGMPOOLPAGE pShwPage;
2736	RTGCPHYS GCPhys;
2737	if (fPageTable)
2738	{
2739	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2740	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2741	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2742	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2743	# endif
2744	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2745	pShwPde->idx, iPDDst, false /fLockPage/,
2746	&pShwPage);
2747	}
2748	else
2749	{
2750	PGMPOOLACCESS enmAccess;
2751	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2752	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2753	# else
2754	const bool fNoExecute = false;
2755	# endif
2756
2757	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2758	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2759	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2760	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2761	# endif
2762	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2763	if (PdeSrc.n.u1User)
2764	{
2765	if (PdeSrc.n.u1Write)
2766	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2767	else
2768	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2769	}
2770	else
2771	{
2772	if (PdeSrc.n.u1Write)
2773	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2774	else
2775	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2776	}
2777	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2778	pShwPde->idx, iPDDst, false /fLockPage/,
2779	&pShwPage);
2780	}
2781	if (rc == VINF_SUCCESS)
2782	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2783	else if (rc == VINF_PGM_CACHED_PAGE)
2784	{
2785	/*
2786	* The PT was cached, just hook it up.
2787	*/
2788	if (fPageTable)
2789	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2790	else
2791	{
2792	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2793	/* (see explanation and assumptions further down.) */
2794	if ( !PdeSrc.b.u1Dirty
2795	&& PdeSrc.b.u1Write)
2796	{
2797	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2798	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2799	PdeDst.b.u1Write = 0;
2800	}
2801	}
2802	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2803	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2804	return VINF_SUCCESS;
2805	}
2806	else if (rc == VERR_PGM_POOL_FLUSHED)
2807	{
2808	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2809	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2810	return VINF_PGM_SYNC_CR3;
2811	}
2812	else
2813	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2814	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2815	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2816	* irrelevant at this point. */
2817	PdeDst.u &= X86_PDE_AVL_MASK;
2818	PdeDst.u \|= pShwPage->Core.Key;
2819
2820	/*
2821	* Page directory has been accessed (this is a fault situation, remember).
2822	*/
2823	/** @todo
2824	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2825	* fault situation. What's more, the Trap0eHandler has already set the
2826	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2827	* might need setting the accessed flag.
2828	*
2829	* The best idea is to leave this change to the caller and add an
2830	* assertion that it's set already. */
2831	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2832	if (fPageTable)
2833	{
2834	/*
2835	* Page table - 4KB.
2836	*
2837	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2838	*/
2839	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2840	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2841	PGSTPT pPTSrc;
2842	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2843	if (RT_SUCCESS(rc))
2844	{
2845	/*
2846	* Start by syncing the page directory entry so CSAM's TLB trick works.
2847	*/
2848	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2849	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2850	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2851	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2852
2853	/*
2854	* Directory/page user or supervisor privilege: (same goes for read/write)
2855	*
2856	* Directory Page Combined
2857	* U/S U/S U/S
2858	* 0 0 0
2859	* 0 1 0
2860	* 1 0 0
2861	* 1 1 1
2862	*
2863	* Simple AND operation. Table listed for completeness.
2864	*
2865	*/
2866	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2867	# ifdef PGM_SYNC_N_PAGES
2868	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2869	unsigned iPTDst = iPTBase;
2870	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2871	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2872	iPTDst = 0;
2873	else
2874	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2875	# else /* !PGM_SYNC_N_PAGES */
2876	unsigned iPTDst = 0;
2877	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2878	# endif /* !PGM_SYNC_N_PAGES */
2879	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2880	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2881	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2882	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2883	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2884	# else
2885	const unsigned offPTSrc = 0;
2886	# endif
2887	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2888	{
2889	const unsigned iPTSrc = iPTDst + offPTSrc;
2890	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2891
2892	if (PteSrc.n.u1Present)
2893	{
2894	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2895	/*
2896	* Assuming kernel code will be marked as supervisor - and not as user level
2897	* and executed using a conforming code selector - And marked as readonly.
2898	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2899	*/
2900	PPGMPAGE pPage;
2901	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2902	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2903	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2904	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2905	)
2906	# endif
2907	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2908	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2909	GCPtrCur,
2910	PteSrc.n.u1Present,
2911	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2912	PteSrc.n.u1User & PdeSrc.n.u1User,
2913	(uint64_t)PteSrc.u,
2914	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2915	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2916	}
2917	/* else: the page table was cleared by the pool */
2918	} /* for PTEs */
2919	}
2920	}
2921	else
2922	{
2923	/*
2924	* Big page - 2/4MB.
2925	*
2926	* We'll walk the ram range list in parallel and optimize lookups.
2927	* We will only sync one shadow page table at a time.
2928	*/
2929	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2930
2931	/**
2932	* @todo It might be more efficient to sync only a part of the 4MB
2933	* page (similar to what we do for 4KB PDs).
2934	*/
2935
2936	/*
2937	* Start by syncing the page directory entry.
2938	*/
2939	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2940	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2941
2942	/*
2943	* If the page is not flagged as dirty and is writable, then make it read-only
2944	* at PD level, so we can set the dirty bit when the page is modified.
2945	*
2946	* ASSUMES that page access handlers are implemented on page table entry level.
2947	* Thus we will first catch the dirty access and set PDE.D and restart. If
2948	* there is an access handler, we'll trap again and let it work on the problem.
2949	*/
2950	/** @todo move the above stuff to a section in the PGM documentation. */
2951	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2952	if ( !PdeSrc.b.u1Dirty
2953	&& PdeSrc.b.u1Write)
2954	{
2955	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2956	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2957	PdeDst.b.u1Write = 0;
2958	}
2959	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2960	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2961
2962	/*
2963	* Fill the shadow page table.
2964	*/
2965	/* Get address and flags from the source PDE. */
2966	SHWPTE PteDstBase;
2967	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
2968
2969	/* Loop thru the entries in the shadow PT. */
2970	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2971	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
2972	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2973	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2974	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
2975	unsigned iPTDst = 0;
2976	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
2977	&& !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
2978	{
2979	if (pRam && GCPhys >= pRam->GCPhys)
2980	{
2981	# ifndef PGM_WITH_A20
2982	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2983	# endif
2984	do
2985	{
2986	/* Make shadow PTE. */
2987	# ifdef PGM_WITH_A20
2988	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
2989	# else
2990	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2991	# endif
2992	SHWPTE PteDst;
2993
2994	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2995	/* Try to make the page writable if necessary. */
2996	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2997	&& ( PGM_PAGE_IS_ZERO(pPage)
2998	\|\| ( SHW_PTE_IS_RW(PteDstBase)
2999	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3000	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3001	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3002	# endif
3003	# ifdef VBOX_WITH_PAGE_SHARING
3004	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3005	# endif
3006	&& !PGM_PAGE_IS_BALLOONED(pPage))
3007	)
3008	)
3009	{
3010	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3011	AssertRCReturn(rc, rc);
3012	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
3013	break;
3014	}
3015	# endif
3016
3017	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3018	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3019	else if (PGM_PAGE_IS_BALLOONED(pPage))
3020	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3021	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3022	/*
3023	* Assuming kernel code will be marked as supervisor and not as user level and executed
3024	* using a conforming code selector. Don't check for readonly, as that implies the whole
3025	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3026	*/
3027	else if ( !PdeSrc.n.u1User
3028	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3029	SHW_PTE_SET(PteDst, 0);
3030	# endif
3031	else
3032	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3033
3034	/* Only map writable pages writable. */
3035	if ( SHW_PTE_IS_P_RW(PteDst)
3036	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3037	{
3038	/* Still applies to shared pages. */
3039	Assert(!PGM_PAGE_IS_ZERO(pPage));
3040	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3041	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3042	}
3043
3044	if (SHW_PTE_IS_P(PteDst))
3045	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3046
3047	/* commit it (not atomic, new table) */
3048	pPTDst->a[iPTDst] = PteDst;
3049	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3050	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3051	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3052
3053	/* advance */
3054	GCPhys += PAGE_SIZE;
3055	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3056	# ifndef PGM_WITH_A20
3057	iHCPage++;
3058	# endif
3059	iPTDst++;
3060	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3061	&& GCPhys <= pRam->GCPhysLast);
3062
3063	/* Advance ram range list. */
3064	while (pRam && GCPhys > pRam->GCPhysLast)
3065	pRam = pRam->CTX_SUFF(pNext);
3066	}
3067	else if (pRam)
3068	{
3069	Log(("Invalid pages at %RGp\n", GCPhys));
3070	do
3071	{
3072	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3073	GCPhys += PAGE_SIZE;
3074	iPTDst++;
3075	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3076	&& GCPhys < pRam->GCPhys);
3077	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3078	}
3079	else
3080	{
3081	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3082	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3083	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3084	}
3085	} /* while more PTEs */
3086	} /* 4KB / 4MB */
3087	}
3088	else
3089	AssertRelease(!PdeDst.n.u1Present);
3090
3091	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3092	if (RT_FAILURE(rc))
3093	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3094	return rc;
3095
3096	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3097	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3098	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3099	&& !defined(IN_RC)
3100	NOREF(iPDSrc); NOREF(pPDSrc);
3101
3102	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3103
3104	/*
3105	* Validate input a little bit.
3106	*/
3107	int rc = VINF_SUCCESS;
3108	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3109	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3110	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3111
3112	/* Fetch the pgm pool shadow descriptor. */
3113	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3114	Assert(pShwPde);
3115
3116	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3117	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3118	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3119	PX86PDPAE pPDDst;
3120	PSHWPDE pPdeDst;
3121
3122	/* Fetch the pgm pool shadow descriptor. */
3123	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3124	AssertRCSuccessReturn(rc, rc);
3125	Assert(pShwPde);
3126
3127	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3128	pPdeDst = &pPDDst->a[iPDDst];
3129
3130	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3131	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3132	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3133	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3134	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3135	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3136	AssertRCSuccessReturn(rc, rc);
3137	Assert(pPDDst);
3138	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3139
3140	/* Fetch the pgm pool shadow descriptor. */
3141	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3142	Assert(pShwPde);
3143
3144	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3145	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3146	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3147	PEPTPD pPDDst;
3148	PEPTPDPT pPdptDst;
3149
3150	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3151	if (rc != VINF_SUCCESS)
3152	{
3153	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3154	AssertRC(rc);
3155	return rc;
3156	}
3157	Assert(pPDDst);
3158	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3159
3160	/* Fetch the pgm pool shadow descriptor. */
3161	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3162	Assert(pShwPde);
3163	# endif
3164	SHWPDE PdeDst = *pPdeDst;
3165
3166	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3167	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3168
3169	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3170	if (BTH_IS_NP_ACTIVE(pVM))
3171	{
3172	/* Check if we allocated a big page before for this 2 MB range. */
3173	PPGMPAGE pPage;
3174	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3175	if (RT_SUCCESS(rc))
3176	{
3177	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3178	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3179	{
3180	if (PGM_A20_IS_ENABLED(pVCpu))
3181	{
3182	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3183	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3184	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3185	}
3186	else
3187	{
3188	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3189	pVM->pgm.s.cLargePagesDisabled++;
3190	}
3191	}
3192	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3193	&& PGM_A20_IS_ENABLED(pVCpu))
3194	{
3195	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3196	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3197	if (RT_SUCCESS(rc))
3198	{
3199	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3200	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3201	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3202	}
3203	}
3204	else if ( PGMIsUsingLargePages(pVM)
3205	&& PGM_A20_IS_ENABLED(pVCpu))
3206	{
3207	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3208	if (RT_SUCCESS(rc))
3209	{
3210	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3211	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3212	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3213	}
3214	else
3215	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3216	}
3217
3218	if (HCPhys != NIL_RTHCPHYS)
3219	{
3220	PdeDst.u &= X86_PDE_AVL_MASK;
3221	PdeDst.u \|= HCPhys;
3222	PdeDst.n.u1Present = 1;
3223	PdeDst.n.u1Write = 1;
3224	PdeDst.b.u1Size = 1;
3225	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3226	PdeDst.n.u1Execute = 1;
3227	PdeDst.b.u1IgnorePAT = 1;
3228	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3229	# else
3230	PdeDst.n.u1User = 1;
3231	# endif
3232	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3233
3234	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3235	/* Add a reference to the first page only. */
3236	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3237
3238	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3239	return VINF_SUCCESS;
3240	}
3241	}
3242	}
3243	# endif /* HC_ARCH_BITS == 64 */
3244
3245	/*
3246	* Allocate & map the page table.
3247	*/
3248	PSHWPT pPTDst;
3249	PPGMPOOLPAGE pShwPage;
3250	RTGCPHYS GCPhys;
3251
3252	/* Virtual address = physical address */
3253	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3254	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3255	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3256	&pShwPage);
3257	if ( rc == VINF_SUCCESS
3258	\|\| rc == VINF_PGM_CACHED_PAGE)
3259	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3260	else
3261	{
3262	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3263	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3264	}
3265
3266	if (rc == VINF_SUCCESS)
3267	{
3268	/* New page table; fully set it up. */
3269	Assert(pPTDst);
3270
3271	/* Mask away the page offset. */
3272	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3273
3274	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3275	{
3276	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3277	\| (iPTDst << PAGE_SHIFT));
3278
3279	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3280	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3281	GCPtrCurPage,
3282	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3283	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3284
3285	if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3286	break;
3287	}
3288	}
3289	else
3290	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3291
3292	/* Save the new PDE. */
3293	PdeDst.u &= X86_PDE_AVL_MASK;
3294	PdeDst.u \|= pShwPage->Core.Key;
3295	PdeDst.n.u1Present = 1;
3296	PdeDst.n.u1Write = 1;
3297	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3298	PdeDst.n.u1Execute = 1;
3299	# else
3300	PdeDst.n.u1User = 1;
3301	PdeDst.n.u1Accessed = 1;
3302	# endif
3303	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3304
3305	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3306	if (RT_FAILURE(rc))
3307	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3308	return rc;
3309
3310	#else
3311	NOREF(iPDSrc); NOREF(pPDSrc);
3312	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3313	return VERR_PGM_NOT_USED_IN_MODE;
3314	#endif
3315	}
3316
3317
3318
3319	/**
3320	* Prefetch a page/set of pages.
3321	*
3322	* Typically used to sync commonly used pages before entering raw mode
3323	* after a CR3 reload.
3324	*
3325	* @returns VBox status code.
3326	* @param pVCpu Pointer to the VMCPU.
3327	* @param GCPtrPage Page to invalidate.
3328	*/
3329	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3330	{
3331	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3332	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3333	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3334	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3335	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3336	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3337	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3338
3339	/*
3340	* Check that all Guest levels thru the PDE are present, getting the
3341	* PD and PDE in the processes.
3342	*/
3343	int rc = VINF_SUCCESS;
3344	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3345	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3346	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3347	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3348	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3349	unsigned iPDSrc;
3350	X86PDPE PdpeSrc;
3351	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3352	if (!pPDSrc)
3353	return VINF_SUCCESS; /* not present */
3354	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3355	unsigned iPDSrc;
3356	PX86PML4E pPml4eSrc;
3357	X86PDPE PdpeSrc;
3358	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3359	if (!pPDSrc)
3360	return VINF_SUCCESS; /* not present */
3361	# endif
3362	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3363	# else
3364	PGSTPD pPDSrc = NULL;
3365	const unsigned iPDSrc = 0;
3366	GSTPDE PdeSrc;
3367
3368	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3369	PdeSrc.n.u1Present = 1;
3370	PdeSrc.n.u1Write = 1;
3371	PdeSrc.n.u1Accessed = 1;
3372	PdeSrc.n.u1User = 1;
3373	# endif
3374
3375	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3376	{
3377	PVM pVM = pVCpu->CTX_SUFF(pVM);
3378	pgmLock(pVM);
3379
3380	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3381	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3382	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3383	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3384	PX86PDPAE pPDDst;
3385	X86PDEPAE PdeDst;
3386	# if PGM_GST_TYPE != PGM_TYPE_PAE
3387	X86PDPE PdpeSrc;
3388
3389	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3390	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3391	# endif
3392	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3393	if (rc != VINF_SUCCESS)
3394	{
3395	pgmUnlock(pVM);
3396	AssertRC(rc);
3397	return rc;
3398	}
3399	Assert(pPDDst);
3400	PdeDst = pPDDst->a[iPDDst];
3401
3402	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3403	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3404	PX86PDPAE pPDDst;
3405	X86PDEPAE PdeDst;
3406
3407	# if PGM_GST_TYPE == PGM_TYPE_PROT
3408	/* AMD-V nested paging */
3409	X86PML4E Pml4eSrc;
3410	X86PDPE PdpeSrc;
3411	PX86PML4E pPml4eSrc = &Pml4eSrc;
3412
3413	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3414	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3415	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3416	# endif
3417
3418	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3419	if (rc != VINF_SUCCESS)
3420	{
3421	pgmUnlock(pVM);
3422	AssertRC(rc);
3423	return rc;
3424	}
3425	Assert(pPDDst);
3426	PdeDst = pPDDst->a[iPDDst];
3427	# endif
3428	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3429	{
3430	if (!PdeDst.n.u1Present)
3431	{
3432	/** @todo r=bird: This guy will set the A bit on the PDE,
3433	* probably harmless. */
3434	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3435	}
3436	else
3437	{
3438	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3439	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3440	* makes no sense to prefetch more than one page.
3441	*/
3442	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3443	if (RT_SUCCESS(rc))
3444	rc = VINF_SUCCESS;
3445	}
3446	}
3447	pgmUnlock(pVM);
3448	}
3449	return rc;
3450
3451	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3452	NOREF(pVCpu); NOREF(GCPtrPage);
3453	return VINF_SUCCESS; /* ignore */
3454	#else
3455	AssertCompile(0);
3456	#endif
3457	}
3458
3459
3460
3461
3462	/**
3463	* Syncs a page during a PGMVerifyAccess() call.
3464	*
3465	* @returns VBox status code (informational included).
3466	* @param pVCpu Pointer to the VMCPU.
3467	* @param GCPtrPage The address of the page to sync.
3468	* @param fPage The effective guest page flags.
3469	* @param uErr The trap error code.
3470	* @remarks This will normally never be called on invalid guest page
3471	* translation entries.
3472	*/
3473	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3474	{
3475	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3476
3477	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3478
3479	Assert(!pVM->pgm.s.fNestedPaging);
3480	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3481	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3482	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3483	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3484	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3485	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3486	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3487
3488	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3489	if (!(fPage & X86_PTE_US))
3490	{
3491	/*
3492	* Mark this page as safe.
3493	*/
3494	/** @todo not correct for pages that contain both code and data!! */
3495	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3496	CSAMMarkPage(pVM, GCPtrPage, true);
3497	}
3498	# endif
3499
3500	/*
3501	* Get guest PD and index.
3502	*/
3503	/** @todo Performance: We've done all this a jiffy ago in the
3504	* PGMGstGetPage call. */
3505	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3506	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3507	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3508	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3509
3510	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3511	unsigned iPDSrc = 0;
3512	X86PDPE PdpeSrc;
3513	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3514	if (RT_UNLIKELY(!pPDSrc))
3515	{
3516	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3517	return VINF_EM_RAW_GUEST_TRAP;
3518	}
3519
3520	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3521	unsigned iPDSrc = 0; /* shut up gcc */
3522	PX86PML4E pPml4eSrc = NULL; /* ditto */
3523	X86PDPE PdpeSrc;
3524	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3525	if (RT_UNLIKELY(!pPDSrc))
3526	{
3527	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3528	return VINF_EM_RAW_GUEST_TRAP;
3529	}
3530	# endif
3531
3532	# else /* !PGM_WITH_PAGING */
3533	PGSTPD pPDSrc = NULL;
3534	const unsigned iPDSrc = 0;
3535	# endif /* !PGM_WITH_PAGING */
3536	int rc = VINF_SUCCESS;
3537
3538	pgmLock(pVM);
3539
3540	/*
3541	* First check if the shadow pd is present.
3542	*/
3543	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3544	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3545
3546	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3547	PX86PDEPAE pPdeDst;
3548	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3549	PX86PDPAE pPDDst;
3550	# if PGM_GST_TYPE != PGM_TYPE_PAE
3551	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3552	X86PDPE PdpeSrc;
3553	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3554	# endif
3555	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3556	if (rc != VINF_SUCCESS)
3557	{
3558	pgmUnlock(pVM);
3559	AssertRC(rc);
3560	return rc;
3561	}
3562	Assert(pPDDst);
3563	pPdeDst = &pPDDst->a[iPDDst];
3564
3565	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3566	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3567	PX86PDPAE pPDDst;
3568	PX86PDEPAE pPdeDst;
3569
3570	# if PGM_GST_TYPE == PGM_TYPE_PROT
3571	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3572	X86PML4E Pml4eSrc;
3573	X86PDPE PdpeSrc;
3574	PX86PML4E pPml4eSrc = &Pml4eSrc;
3575	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3576	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3577	# endif
3578
3579	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3580	if (rc != VINF_SUCCESS)
3581	{
3582	pgmUnlock(pVM);
3583	AssertRC(rc);
3584	return rc;
3585	}
3586	Assert(pPDDst);
3587	pPdeDst = &pPDDst->a[iPDDst];
3588	# endif
3589
3590	if (!pPdeDst->n.u1Present)
3591	{
3592	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3593	if (rc != VINF_SUCCESS)
3594	{
3595	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3596	pgmUnlock(pVM);
3597	AssertRC(rc);
3598	return rc;
3599	}
3600	}
3601
3602	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3603	/* Check for dirty bit fault */
3604	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3605	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3606	Log(("PGMVerifyAccess: success (dirty)\n"));
3607	else
3608	# endif
3609	{
3610	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3611	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3612	# else
3613	GSTPDE PdeSrc;
3614	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3615	PdeSrc.n.u1Present = 1;
3616	PdeSrc.n.u1Write = 1;
3617	PdeSrc.n.u1Accessed = 1;
3618	PdeSrc.n.u1User = 1;
3619	# endif
3620
3621	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3622	if (uErr & X86_TRAP_PF_US)
3623	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3624	else /* supervisor */
3625	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3626
3627	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3628	if (RT_SUCCESS(rc))
3629	{
3630	/* Page was successfully synced */
3631	Log2(("PGMVerifyAccess: success (sync)\n"));
3632	rc = VINF_SUCCESS;
3633	}
3634	else
3635	{
3636	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3637	rc = VINF_EM_RAW_GUEST_TRAP;
3638	}
3639	}
3640	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3641	pgmUnlock(pVM);
3642	return rc;
3643
3644	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3645
3646	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3647	return VERR_PGM_NOT_USED_IN_MODE;
3648	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3649	}
3650
3651
3652	/**
3653	* Syncs the paging hierarchy starting at CR3.
3654	*
3655	* @returns VBox status code, no specials.
3656	* @param pVCpu Pointer to the VMCPU.
3657	* @param cr0 Guest context CR0 register.
3658	* @param cr3 Guest context CR3 register. Not subjected to the A20
3659	* mask.
3660	* @param cr4 Guest context CR4 register.
3661	* @param fGlobal Including global page directories or not
3662	*/
3663	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3664	{
3665	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3666	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3667
3668	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3669
3670	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3671
3672	pgmLock(pVM);
3673
3674	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3675	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3676	if (pPool->cDirtyPages)
3677	pgmPoolResetDirtyPages(pVM);
3678	# endif
3679
3680	/*
3681	* Update page access handlers.
3682	* The virtual are always flushed, while the physical are only on demand.
3683	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3684	* have to look into that later because it will have a bad influence on the performance.
3685	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3686	* bird: Yes, but that won't work for aliases.
3687	*/
3688	/** @todo this MUST go away. See @bugref{1557}. */
3689	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3690	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3691	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3692	pgmUnlock(pVM);
3693	#endif /* !NESTED && !EPT */
3694
3695	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3696	/*
3697	* Nested / EPT - almost no work.
3698	*/
3699	Assert(!pgmMapAreMappingsEnabled(pVM));
3700	return VINF_SUCCESS;
3701
3702	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3703	/*
3704	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3705	* out the shadow parts when the guest modifies its tables.
3706	*/
3707	Assert(!pgmMapAreMappingsEnabled(pVM));
3708	return VINF_SUCCESS;
3709
3710	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3711
3712	# ifndef PGM_WITHOUT_MAPPINGS
3713	/*
3714	* Check for and resolve conflicts with our guest mappings if they
3715	* are enabled and not fixed.
3716	*/
3717	if (pgmMapAreMappingsFloating(pVM))
3718	{
3719	int rc = pgmMapResolveConflicts(pVM);
3720	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3721	if (rc == VINF_PGM_SYNC_CR3)
3722	{
3723	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3724	return VINF_PGM_SYNC_CR3;
3725	}
3726	}
3727	# else
3728	Assert(!pgmMapAreMappingsEnabled(pVM));
3729	# endif
3730	return VINF_SUCCESS;
3731	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3732	}
3733
3734
3735
3736
3737	#ifdef VBOX_STRICT
3738	# ifdef IN_RC
3739	# undef AssertMsgFailed
3740	# define AssertMsgFailed Log
3741	# endif
3742
3743	/**
3744	* Checks that the shadow page table is in sync with the guest one.
3745	*
3746	* @returns The number of errors.
3747	* @param pVM The virtual machine.
3748	* @param pVCpu Pointer to the VMCPU.
3749	* @param cr3 Guest context CR3 register.
3750	* @param cr4 Guest context CR4 register.
3751	* @param GCPtr Where to start. Defaults to 0.
3752	* @param cb How much to check. Defaults to everything.
3753	*/
3754	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3755	{
3756	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3757	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3758	return 0;
3759	#else
3760	unsigned cErrors = 0;
3761	PVM pVM = pVCpu->CTX_SUFF(pVM);
3762	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3763
3764	# if PGM_GST_TYPE == PGM_TYPE_PAE
3765	/** @todo currently broken; crashes below somewhere */
3766	AssertFailed();
3767	# endif
3768
3769	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3770	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3771	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3772
3773	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3774	PPGMCPU pPGM = &pVCpu->pgm.s;
3775	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3776	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3777	# ifndef IN_RING0
3778	RTHCPHYS HCPhys; /* general usage. */
3779	# endif
3780	int rc;
3781
3782	/*
3783	* Check that the Guest CR3 and all its mappings are correct.
3784	*/
3785	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3786	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3787	false);
3788	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3789	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3790	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3791	# else
3792	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3793	# endif
3794	AssertRCReturn(rc, 1);
3795	HCPhys = NIL_RTHCPHYS;
3796	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3797	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3798	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3799	pgmGstGet32bitPDPtr(pVCpu);
3800	RTGCPHYS GCPhys;
3801	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3802	AssertRCReturn(rc, 1);
3803	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3804	# endif
3805	# endif /* !IN_RING0 */
3806
3807	/*
3808	* Get and check the Shadow CR3.
3809	*/
3810	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3811	unsigned cPDEs = X86_PG_ENTRIES;
3812	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3813	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3814	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3815	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3816	# else
3817	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3818	# endif
3819	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3820	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3821	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3822	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3823	# endif
3824	if (cb != ~(RTGCPTR)0)
3825	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3826
3827	/** @todo call the other two PGMAssert() functions. /
3828
3829	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3830	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3831
3832	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3833	{
3834	PPGMPOOLPAGE pShwPdpt = NULL;
3835	PX86PML4E pPml4eSrc;
3836	PX86PML4E pPml4eDst;
3837	RTGCPHYS GCPhysPdptSrc;
3838
3839	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3840	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3841
3842	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3843	if (!pPml4eDst->n.u1Present)
3844	{
3845	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3846	continue;
3847	}
3848
3849	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3850	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3851
3852	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3853	{
3854	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3855	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3856	cErrors++;
3857	continue;
3858	}
3859
3860	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3861	{
3862	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3863	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3864	cErrors++;
3865	continue;
3866	}
3867
3868	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3869	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3870	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3871	{
3872	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3873	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3874	cErrors++;
3875	continue;
3876	}
3877	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3878	{
3879	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3880
3881	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3882	/*
3883	* Check the PDPTEs too.
3884	*/
3885	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3886
3887	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3888	{
3889	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3890	PPGMPOOLPAGE pShwPde = NULL;
3891	PX86PDPE pPdpeDst;
3892	RTGCPHYS GCPhysPdeSrc;
3893	X86PDPE PdpeSrc;
3894	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3895	# if PGM_GST_TYPE == PGM_TYPE_PAE
3896	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3897	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3898	# else
3899	PX86PML4E pPml4eSrcIgn;
3900	PX86PDPT pPdptDst;
3901	PX86PDPAE pPDDst;
3902	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3903
3904	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3905	if (rc != VINF_SUCCESS)
3906	{
3907	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3908	GCPtr += 512 * _2M;
3909	continue; /* next PDPTE */
3910	}
3911	Assert(pPDDst);
3912	# endif
3913	Assert(iPDSrc == 0);
3914
3915	pPdpeDst = &pPdptDst->a[iPdpt];
3916
3917	if (!pPdpeDst->n.u1Present)
3918	{
3919	GCPtr += 512 * _2M;
3920	continue; /* next PDPTE */
3921	}
3922
3923	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3924	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3925
3926	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3927	{
3928	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3929	GCPtr += 512 * _2M;
3930	cErrors++;
3931	continue;
3932	}
3933
3934	if (GCPhysPdeSrc != pShwPde->GCPhys)
3935	{
3936	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3937	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3938	# else
3939	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3940	# endif
3941	GCPtr += 512 * _2M;
3942	cErrors++;
3943	continue;
3944	}
3945
3946	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3947	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3948	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3949	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3950	{
3951	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3952	GCPtr += 512 * _2M;
3953	cErrors++;
3954	continue;
3955	}
3956	# endif
3957
3958	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3959	{
3960	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
3961	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3962	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3963	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3964	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
3965	# endif
3966	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
3967	/*
3968	* Iterate the shadow page directory.
3969	*/
3970	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3971	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
3972
3973	for (;
3974	iPDDst < cPDEs;
3975	iPDDst++, GCPtr += cIncrement)
3976	{
3977	# if PGM_SHW_TYPE == PGM_TYPE_PAE
3978	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
3979	# else
3980	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3981	# endif
3982	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3983	{
3984	Assert(pgmMapAreMappingsEnabled(pVM));
3985	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3986	{
3987	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3988	cErrors++;
3989	continue;
3990	}
3991	}
3992	else if ( (PdeDst.u & X86_PDE_P)
3993	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3994	)
3995	{
3996	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3997	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
3998	if (!pPoolPage)
3999	{
4000	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4001	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4002	cErrors++;
4003	continue;
4004	}
4005	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4006
4007	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4008	{
4009	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4010	GCPtr, (uint64_t)PdeDst.u));
4011	cErrors++;
4012	}
4013
4014	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4015	{
4016	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4017	GCPtr, (uint64_t)PdeDst.u));
4018	cErrors++;
4019	}
4020
4021	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4022	if (!PdeSrc.n.u1Present)
4023	{
4024	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4025	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4026	cErrors++;
4027	continue;
4028	}
4029
4030	if ( !PdeSrc.b.u1Size
4031	\|\| !fBigPagesSupported)
4032	{
4033	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4034	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4035	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4036	# endif
4037	}
4038	else
4039	{
4040	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4041	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4042	{
4043	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4044	GCPtr, (uint64_t)PdeSrc.u));
4045	cErrors++;
4046	continue;
4047	}
4048	# endif
4049	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4050	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4051	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4052	# endif
4053	}
4054
4055	if ( pPoolPage->enmKind
4056	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4057	{
4058	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4059	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4060	cErrors++;
4061	}
4062
4063	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4064	if (!pPhysPage)
4065	{
4066	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4067	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4068	cErrors++;
4069	continue;
4070	}
4071
4072	if (GCPhysGst != pPoolPage->GCPhys)
4073	{
4074	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4075	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4076	cErrors++;
4077	continue;
4078	}
4079
4080	if ( !PdeSrc.b.u1Size
4081	\|\| !fBigPagesSupported)
4082	{
4083	/*
4084	* Page Table.
4085	*/
4086	const GSTPT *pPTSrc;
4087	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4088	&pPTSrc);
4089	if (RT_FAILURE(rc))
4090	{
4091	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4092	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4093	cErrors++;
4094	continue;
4095	}
4096	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4097	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4098	{
4099	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4100	// (This problem will go away when/if we shadow multiple CR3s.)
4101	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4102	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4103	cErrors++;
4104	continue;
4105	}
4106	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4107	{
4108	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4109	GCPtr, (uint64_t)PdeDst.u));
4110	cErrors++;
4111	continue;
4112	}
4113
4114	/* iterate the page table. */
4115	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4116	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4117	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4118	# else
4119	const unsigned offPTSrc = 0;
4120	# endif
4121	for (unsigned iPT = 0, off = 0;
4122	iPT < RT_ELEMENTS(pPTDst->a);
4123	iPT++, off += PAGE_SIZE)
4124	{
4125	const SHWPTE PteDst = pPTDst->a[iPT];
4126
4127	/* skip not-present and dirty tracked entries. */
4128	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4129	continue;
4130	Assert(SHW_PTE_IS_P(PteDst));
4131
4132	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4133	if (!PteSrc.n.u1Present)
4134	{
4135	# ifdef IN_RING3
4136	PGMAssertHandlerAndFlagsInSync(pVM);
4137	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4138	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4139	0, 0, UINT64_MAX, 99, NULL);
4140	# endif
4141	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4142	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4143	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4144	cErrors++;
4145	continue;
4146	}
4147
4148	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4149	# if 1 /** @todo sync accessed bit properly... */
4150	fIgnoreFlags \|= X86_PTE_A;
4151	# endif
4152
4153	/* match the physical addresses */
4154	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4155	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4156
4157	# ifdef IN_RING3
4158	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4159	if (RT_FAILURE(rc))
4160	{
4161	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4162	{
4163	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4164	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4165	cErrors++;
4166	continue;
4167	}
4168	}
4169	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4170	{
4171	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4172	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4173	cErrors++;
4174	continue;
4175	}
4176	# endif
4177
4178	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4179	if (!pPhysPage)
4180	{
4181	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4182	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4183	{
4184	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4185	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4186	cErrors++;
4187	continue;
4188	}
4189	# endif
4190	if (SHW_PTE_IS_RW(PteDst))
4191	{
4192	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4193	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4194	cErrors++;
4195	}
4196	fIgnoreFlags \|= X86_PTE_RW;
4197	}
4198	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4199	{
4200	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4201	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4202	cErrors++;
4203	continue;
4204	}
4205
4206	/* flags */
4207	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4208	{
4209	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4210	{
4211	if (SHW_PTE_IS_RW(PteDst))
4212	{
4213	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4214	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4215	cErrors++;
4216	continue;
4217	}
4218	fIgnoreFlags \|= X86_PTE_RW;
4219	}
4220	else
4221	{
4222	if ( SHW_PTE_IS_P(PteDst)
4223	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4224	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4225	# endif
4226	)
4227	{
4228	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4229	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4230	cErrors++;
4231	continue;
4232	}
4233	fIgnoreFlags \|= X86_PTE_P;
4234	}
4235	}
4236	else
4237	{
4238	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4239	{
4240	if (SHW_PTE_IS_RW(PteDst))
4241	{
4242	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4243	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4244	cErrors++;
4245	continue;
4246	}
4247	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4248	{
4249	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4250	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4251	cErrors++;
4252	continue;
4253	}
4254	if (SHW_PTE_IS_D(PteDst))
4255	{
4256	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4257	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4258	cErrors++;
4259	}
4260	# if 0 /** @todo sync access bit properly... */
4261	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4262	{
4263	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4264	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4265	cErrors++;
4266	}
4267	fIgnoreFlags \|= X86_PTE_RW;
4268	# else
4269	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4270	# endif
4271	}
4272	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4273	{
4274	/* access bit emulation (not implemented). */
4275	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4276	{
4277	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4278	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4279	cErrors++;
4280	continue;
4281	}
4282	if (!SHW_PTE_IS_A(PteDst))
4283	{
4284	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4285	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4286	cErrors++;
4287	}
4288	fIgnoreFlags \|= X86_PTE_P;
4289	}
4290	# ifdef DEBUG_sandervl
4291	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4292	# endif
4293	}
4294
4295	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4296	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4297	)
4298	{
4299	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4300	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4301	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4302	cErrors++;
4303	continue;
4304	}
4305	} /* foreach PTE */
4306	}
4307	else
4308	{
4309	/*
4310	* Big Page.
4311	*/
4312	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4313	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4314	{
4315	if (PdeDst.n.u1Write)
4316	{
4317	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4318	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4319	cErrors++;
4320	continue;
4321	}
4322	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4323	{
4324	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4325	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4326	cErrors++;
4327	continue;
4328	}
4329	# if 0 /** @todo sync access bit properly... */
4330	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4331	{
4332	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4333	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4334	cErrors++;
4335	}
4336	fIgnoreFlags \|= X86_PTE_RW;
4337	# else
4338	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4339	# endif
4340	}
4341	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4342	{
4343	/* access bit emulation (not implemented). */
4344	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4345	{
4346	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4347	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4348	cErrors++;
4349	continue;
4350	}
4351	if (!PdeDst.n.u1Accessed)
4352	{
4353	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4354	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4355	cErrors++;
4356	}
4357	fIgnoreFlags \|= X86_PTE_P;
4358	}
4359
4360	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4361	{
4362	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4363	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4364	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4365	cErrors++;
4366	}
4367
4368	/* iterate the page table. */
4369	for (unsigned iPT = 0, off = 0;
4370	iPT < RT_ELEMENTS(pPTDst->a);
4371	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4372	{
4373	const SHWPTE PteDst = pPTDst->a[iPT];
4374
4375	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4376	{
4377	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4378	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4379	cErrors++;
4380	}
4381
4382	/* skip not-present entries. */
4383	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4384	continue;
4385
4386	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4387
4388	/* match the physical addresses */
4389	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4390
4391	# ifdef IN_RING3
4392	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4393	if (RT_FAILURE(rc))
4394	{
4395	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4396	{
4397	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4398	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4399	cErrors++;
4400	}
4401	}
4402	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4403	{
4404	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4405	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4406	cErrors++;
4407	continue;
4408	}
4409	# endif
4410	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4411	if (!pPhysPage)
4412	{
4413	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4414	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4415	{
4416	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4417	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4418	cErrors++;
4419	continue;
4420	}
4421	# endif
4422	if (SHW_PTE_IS_RW(PteDst))
4423	{
4424	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4425	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4426	cErrors++;
4427	}
4428	fIgnoreFlags \|= X86_PTE_RW;
4429	}
4430	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4431	{
4432	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4433	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4434	cErrors++;
4435	continue;
4436	}
4437
4438	/* flags */
4439	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4440	{
4441	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4442	{
4443	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4444	{
4445	if (SHW_PTE_IS_RW(PteDst))
4446	{
4447	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4448	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4449	cErrors++;
4450	continue;
4451	}
4452	fIgnoreFlags \|= X86_PTE_RW;
4453	}
4454	}
4455	else
4456	{
4457	if ( SHW_PTE_IS_P(PteDst)
4458	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4459	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4460	# endif
4461	)
4462	{
4463	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4464	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4465	cErrors++;
4466	continue;
4467	}
4468	fIgnoreFlags \|= X86_PTE_P;
4469	}
4470	}
4471
4472	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4473	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4474	)
4475	{
4476	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4477	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4478	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4479	cErrors++;
4480	continue;
4481	}
4482	} /* for each PTE */
4483	}
4484	}
4485	/* not present */
4486
4487	} /* for each PDE */
4488
4489	} /* for each PDPTE */
4490
4491	} /* for each PML4E */
4492
4493	# ifdef DEBUG
4494	if (cErrors)
4495	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4496	# endif
4497	# endif /* GST is in {32BIT, PAE, AMD64} */
4498	return cErrors;
4499	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4500	}
4501	#endif /* VBOX_STRICT */
4502
4503
4504	/**
4505	* Sets up the CR3 for shadow paging
4506	*
4507	* @returns Strict VBox status code.
4508	* @retval VINF_SUCCESS.
4509	*
4510	* @param pVCpu Pointer to the VMCPU.
4511	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4512	* mask already applied.)
4513	*/
4514	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4515	{
4516	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4517
4518	/* Update guest paging info. */
4519	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4520	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4521	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4522
4523	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4524	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4525
4526	/*
4527	* Map the page CR3 points at.
4528	*/
4529	RTHCPTR HCPtrGuestCR3;
4530	RTHCPHYS HCPhysGuestCR3;
4531	pgmLock(pVM);
4532	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4533	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4534	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4535	/** @todo this needs some reworking wrt. locking? */
4536	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4537	HCPtrGuestCR3 = NIL_RTHCPTR;
4538	int rc = VINF_SUCCESS;
4539	# else
4540	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4541	# endif
4542	pgmUnlock(pVM);
4543	if (RT_SUCCESS(rc))
4544	{
4545	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4546	if (RT_SUCCESS(rc))
4547	{
4548	# ifdef IN_RC
4549	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4550	# endif
4551	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4552	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4553	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4554	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4555	# endif
4556	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4557
4558	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4559	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4560	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4561	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4562	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4563	# endif
4564	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4565	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4566
4567	/*
4568	* Map the 4 PDs too.
4569	*/
4570	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4571	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4572	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4573	{
4574	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4575	if (pGuestPDPT->a[i].n.u1Present)
4576	{
4577	RTHCPTR HCPtr;
4578	RTHCPHYS HCPhys;
4579	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4580	pgmLock(pVM);
4581	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4582	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4583	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4584	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4585	HCPtr = NIL_RTHCPTR;
4586	int rc2 = VINF_SUCCESS;
4587	# else
4588	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4589	# endif
4590	pgmUnlock(pVM);
4591	if (RT_SUCCESS(rc2))
4592	{
4593	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4594	AssertRCReturn(rc, rc);
4595
4596	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4597	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4598	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4599	# endif
4600	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4601	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4602	# ifdef IN_RC
4603	PGM_INVL_PG(pVCpu, GCPtr);
4604	# endif
4605	continue;
4606	}
4607	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4608	}
4609
4610	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4611	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4612	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4613	# endif
4614	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4615	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4616	# ifdef IN_RC
4617	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4618	# endif
4619	}
4620
4621	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4622	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4623	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4624	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4625	# endif
4626	# endif
4627	}
4628	else
4629	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4630	}
4631	else
4632	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4633
4634	#else /* prot/real stub */
4635	int rc = VINF_SUCCESS;
4636	#endif
4637
4638	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4639	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4640	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4641	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4642	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4643	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4644
4645	Assert(!pVM->pgm.s.fNestedPaging);
4646	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4647
4648	/*
4649	* Update the shadow root page as well since that's not fixed.
4650	*/
4651	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4652	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4653	PPGMPOOLPAGE pNewShwPageCR3;
4654
4655	pgmLock(pVM);
4656
4657	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4658	if (pPool->cDirtyPages)
4659	pgmPoolResetDirtyPages(pVM);
4660	# endif
4661
4662	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4663	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4664	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4665	&pNewShwPageCR3);
4666	AssertFatalRC(rc);
4667	rc = VINF_SUCCESS;
4668
4669	# ifdef IN_RC
4670	/*
4671	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4672	* state will be inconsistent! Flush important things now while
4673	* we still can and then make sure there are no ring-3 calls.
4674	*/
4675	# ifdef VBOX_WITH_REM
4676	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4677	# endif
4678	VMMRZCallRing3Disable(pVCpu);
4679	# endif
4680
4681	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4682	# ifdef IN_RING0
4683	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4684	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4685	# elif defined(IN_RC)
4686	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4687	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4688	# else
4689	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4690	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4691	# endif
4692
4693	# ifndef PGM_WITHOUT_MAPPINGS
4694	/*
4695	* Apply all hypervisor mappings to the new CR3.
4696	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4697	* make sure we check for conflicts in the new CR3 root.
4698	*/
4699	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4700	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4701	# endif
4702	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4703	AssertRCReturn(rc, rc);
4704	# endif
4705
4706	/* Set the current hypervisor CR3. */
4707	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4708	SELMShadowCR3Changed(pVM, pVCpu);
4709
4710	# ifdef IN_RC
4711	/* NOTE: The state is consistent again. */
4712	VMMRZCallRing3Enable(pVCpu);
4713	# endif
4714
4715	/* Clean up the old CR3 root. */
4716	if ( pOldShwPageCR3
4717	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4718	{
4719	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4720	# ifndef PGM_WITHOUT_MAPPINGS
4721	/* Remove the hypervisor mappings from the shadow page table. */
4722	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4723	# endif
4724	/* Mark the page as unlocked; allow flushing again. */
4725	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4726
4727	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4728	}
4729	pgmUnlock(pVM);
4730	# else
4731	NOREF(GCPhysCR3);
4732	# endif
4733
4734	return rc;
4735	}
4736
4737	/**
4738	* Unmaps the shadow CR3.
4739	*
4740	* @returns VBox status, no specials.
4741	* @param pVCpu Pointer to the VMCPU.
4742	*/
4743	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4744	{
4745	LogFlow(("UnmapCR3\n"));
4746
4747	int rc = VINF_SUCCESS;
4748	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4749
4750	/*
4751	* Update guest paging info.
4752	*/
4753	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4754	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4755	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4756	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4757	# endif
4758	pVCpu->pgm.s.pGst32BitPdRC = 0;
4759
4760	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4761	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4762	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4763	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4764	# endif
4765	pVCpu->pgm.s.pGstPaePdptRC = 0;
4766	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4767	{
4768	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4769	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4770	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4771	# endif
4772	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4773	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4774	}
4775
4776	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4777	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4778	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4779	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4780	# endif
4781
4782	#else /* prot/real mode stub */
4783	/* nothing to do */
4784	#endif
4785
4786	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4787	/*
4788	* Update shadow paging info.
4789	*/
4790	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4791	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4792	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4793
4794	# if PGM_GST_TYPE != PGM_TYPE_REAL
4795	Assert(!pVM->pgm.s.fNestedPaging);
4796	# endif
4797
4798	pgmLock(pVM);
4799
4800	# ifndef PGM_WITHOUT_MAPPINGS
4801	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4802	/* Remove the hypervisor mappings from the shadow page table. */
4803	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4804	# endif
4805
4806	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4807	{
4808	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4809
4810	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4811	if (pPool->cDirtyPages)
4812	pgmPoolResetDirtyPages(pVM);
4813	# endif
4814
4815	/* Mark the page as unlocked; allow flushing again. */
4816	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4817
4818	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4819	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4820	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4821	pVCpu->pgm.s.pShwPageCR3RC = 0;
4822	}
4823	pgmUnlock(pVM);
4824	# endif
4825	#endif /* !IN_RC*/
4826
4827	return rc;
4828	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 45798

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