PGMAllBth.h@ 65029

Last change on this file since 65029 was 64696, checked in by vboxsync, 8 years ago
DevPCI*,PDM: Get internal bus number from PDM.
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1	/* $Id: PGMAllBth.h 64696 2016-11-17 17:37:59Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2016 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if (pGstWalk->Core.fBadPhysAddr)
124	{
125	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
126	Assert(!pGstWalk->Core.fNotPresent);
127	}
128	else if (!pGstWalk->Core.fNotPresent)
129	uNewErr \|= X86_TRAP_PF_P;
130	TRPMSetErrorCode(pVCpu, uNewErr);
131
132	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
133	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
134	return VINF_EM_RAW_GUEST_TRAP;
135	}
136	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
137
138
139	/**
140	* Deal with a guest page fault.
141	*
142	* The caller has taken the PGM lock.
143	*
144	* @returns Strict VBox status code.
145	*
146	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
147	* @param uErr The error code.
148	* @param pRegFrame The register frame.
149	* @param pvFault The fault address.
150	* @param pPage The guest page at @a pvFault.
151	* @param pGstWalk The guest page table walk result.
152	* @param pfLockTaken PGM lock taken here or not (out). This is true
153	* when we're called.
154	*/
155	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
156	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
157	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
158	, PGSTPTWALK pGstWalk
159	# endif
160	)
161	{
162	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
163	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
164	#endif
165	PVM pVM = pVCpu->CTX_SUFF(pVM);
166	VBOXSTRICTRC rcStrict;
167
168	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
169	{
170	/*
171	* Physical page access handler.
172	*/
173	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
174	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
175	# else
176	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
177	# endif
178	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
179	if (pCur)
180	{
181	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
182
183	# ifdef PGM_SYNC_N_PAGES
184	/*
185	* If the region is write protected and we got a page not present fault, then sync
186	* the pages. If the fault was caused by a read, then restart the instruction.
187	* In case of write access continue to the GC write handler.
188	*
189	* ASSUMES that there is only one handler per page or that they have similar write properties.
190	*/
191	if ( !(uErr & X86_TRAP_PF_P)
192	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
193	{
194	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
195	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
196	# else
197	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
198	# endif
199	if ( RT_FAILURE(rcStrict)
200	\|\| !(uErr & X86_TRAP_PF_RW)
201	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
202	{
203	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
204	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
205	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
206	return rcStrict;
207	}
208	}
209	# endif
210	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
211	/*
212	* If the access was not thru a #PF(RSVD\|...) resync the page.
213	*/
214	if ( !(uErr & X86_TRAP_PF_RSVD)
215	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
216	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
217	&& pGstWalk->Core.fEffectiveRW
218	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
219	# endif
220	)
221	{
222	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
223	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
224	# else
225	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
226	# endif
227	if ( RT_FAILURE(rcStrict)
228	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
229	{
230	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
231	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
232	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
233	return rcStrict;
234	}
235	}
236	# endif
237
238	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
239	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
240	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
241	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
242	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
243	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
244	else
245	{
246	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
247	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
248	}
249
250	if (pCurType->CTX_SUFF(pfnPfHandler))
251	{
252	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
253	void *pvUser = pCur->CTX_SUFF(pvUser);
254
255	STAM_PROFILE_START(&pCur->Stat, h);
256	if (pCur->hType != pPool->hAccessHandlerType)
257	{
258	pgmUnlock(pVM);
259	*pfLockTaken = false;
260	}
261
262	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
263
264	# ifdef VBOX_WITH_STATISTICS
265	pgmLock(pVM);
266	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
267	if (pCur)
268	STAM_PROFILE_STOP(&pCur->Stat, h);
269	pgmUnlock(pVM);
270	# endif
271	}
272	else
273	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
274
275	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
276	return rcStrict;
277	}
278	}
279	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
280	else
281	{
282	# ifdef PGM_SYNC_N_PAGES
283	/*
284	* If the region is write protected and we got a page not present fault, then sync
285	* the pages. If the fault was caused by a read, then restart the instruction.
286	* In case of write access continue to the GC write handler.
287	*/
288	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
289	&& !(uErr & X86_TRAP_PF_P))
290	{
291	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
292	if ( RT_FAILURE(rcStrict)
293	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
294	\|\| !(uErr & X86_TRAP_PF_RW))
295	{
296	AssertRC(rcStrict);
297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
298	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
299	return rcStrict;
300	}
301	}
302	# endif
303	/*
304	* Ok, it's an virtual page access handler.
305	*
306	* Since it's faster to search by address, we'll do that first
307	* and then retry by GCPhys if that fails.
308	*/
309	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
310	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
311	* out of sync, because the page was changed without us noticing it (not-present -> present
312	* without invlpg or mov cr3, xxx).
313	*/
314	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
315	if (pCur)
316	{
317	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
318	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
319	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
320	\|\| !(uErr & X86_TRAP_PF_P)
321	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
322	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enumKind=%d\n",
323	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCurType->enmKind));
324
325	if ( pvFault - pCur->Core.Key < pCur->cb
326	&& ( uErr & X86_TRAP_PF_RW
327	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
328	{
329	# ifdef IN_RC
330	STAM_PROFILE_START(&pCur->Stat, h);
331	RTGCPTR GCPtrStart = pCur->Core.Key;
332	void *pvUser = pCur->CTX_SUFF(pvUser);
333	pgmUnlock(pVM);
334	*pfLockTaken = false;
335
336	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart,
337	pvFault - GCPtrStart, pvUser);
338
339	# ifdef VBOX_WITH_STATISTICS
340	pgmLock(pVM);
341	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
342	if (pCur)
343	STAM_PROFILE_STOP(&pCur->Stat, h);
344	pgmUnlock(pVM);
345	# endif
346	# else
347	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
348	# endif
349	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
350	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
351	return rcStrict;
352	}
353	/* Unhandled part of a monitored page */
354	Log(("Unhandled part of monitored page %RGv\n", pvFault));
355	}
356	else
357	{
358	/* Check by physical address. */
359	unsigned iPage;
360	pCur = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &iPage);
361	if (pCur)
362	{
363	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
364	if ( uErr & X86_TRAP_PF_RW
365	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE )
366	{
367	Assert( (pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK)
368	== (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
369	# ifdef IN_RC
370	STAM_PROFILE_START(&pCur->Stat, h);
371	RTGCPTR GCPtrStart = pCur->Core.Key;
372	void *pvUser = pCur->CTX_SUFF(pvUser);
373	pgmUnlock(pVM);
374	*pfLockTaken = false;
375
376	RTGCPTR off = (iPage << PAGE_SHIFT)
377	+ (pvFault & PAGE_OFFSET_MASK)
378	- (GCPtrStart & PAGE_OFFSET_MASK);
379	Assert(off < pCur->cb);
380	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart, off, pvUser);
381
382	# ifdef VBOX_WITH_STATISTICS
383	pgmLock(pVM);
384	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
385	if (pCur)
386	STAM_PROFILE_STOP(&pCur->Stat, h);
387	pgmUnlock(pVM);
388	# endif
389	# else
390	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
391	# endif
392	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
393	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
394	return rcStrict;
395	}
396	}
397	}
398	}
399	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
400
401	/*
402	* There is a handled area of the page, but this fault doesn't belong to it.
403	* We must emulate the instruction.
404	*
405	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
406	* we first check if this was a page-not-present fault for a page with only
407	* write access handlers. Restart the instruction if it wasn't a write access.
408	*/
409	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
410
411	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
412	&& !(uErr & X86_TRAP_PF_P))
413	{
414	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
415	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
416	# else
417	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
418	# endif
419	if ( RT_FAILURE(rcStrict)
420	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
421	\|\| !(uErr & X86_TRAP_PF_RW))
422	{
423	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
424	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
425	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
426	return rcStrict;
427	}
428	}
429
430	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
431	* It's writing to an unhandled part of the LDT page several million times.
432	*/
433	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
434	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
435	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
436	return rcStrict;
437	} /* if any kind of handler */
438
439
440	/**
441	* \#PF Handler for raw-mode guest execution.
442	*
443	* @returns VBox status code (appropriate for trap handling and GC return).
444	*
445	* @param pVCpu The cross context virtual CPU structure.
446	* @param uErr The trap error code.
447	* @param pRegFrame Trap register frame.
448	* @param pvFault The fault address.
449	* @param pfLockTaken PGM lock taken here or not (out)
450	*/
451	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
452	{
453	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
454
455	*pfLockTaken = false;
456
457	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
458	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
459	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
460	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
461	int rc;
462
463	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
464	/*
465	* Walk the guest page translation tables and check if it's a guest fault.
466	*/
467	GSTPTWALK GstWalk;
468	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
469	if (RT_FAILURE_NP(rc))
470	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
471
472	/* assert some GstWalk sanity. */
473	# if PGM_GST_TYPE == PGM_TYPE_AMD64
474	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
475	# endif
476	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
477	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
478	# endif
479	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
480	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
481	Assert(GstWalk.Core.fSucceeded);
482
483	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
484	{
485	if ( ( (uErr & X86_TRAP_PF_RW)
486	&& !GstWalk.Core.fEffectiveRW
487	&& ( (uErr & X86_TRAP_PF_US)
488	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
489	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
490	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
491	)
492	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
493	}
494
495	/*
496	* Set the accessed and dirty flags.
497	*/
498	# if PGM_GST_TYPE == PGM_TYPE_AMD64
499	GstWalk.Pml4e.u \|= X86_PML4E_A;
500	GstWalk.pPml4e->u \|= X86_PML4E_A;
501	GstWalk.Pdpe.u \|= X86_PDPE_A;
502	GstWalk.pPdpe->u \|= X86_PDPE_A;
503	# endif
504	if (GstWalk.Core.fBigPage)
505	{
506	Assert(GstWalk.Pde.b.u1Size);
507	if (uErr & X86_TRAP_PF_RW)
508	{
509	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
510	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	}
512	else
513	{
514	GstWalk.Pde.u \|= X86_PDE4M_A;
515	GstWalk.pPde->u \|= X86_PDE4M_A;
516	}
517	}
518	else
519	{
520	Assert(!GstWalk.Pde.b.u1Size);
521	GstWalk.Pde.u \|= X86_PDE_A;
522	GstWalk.pPde->u \|= X86_PDE_A;
523	if (uErr & X86_TRAP_PF_RW)
524	{
525	# ifdef VBOX_WITH_STATISTICS
526	if (!GstWalk.Pte.n.u1Dirty)
527	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
528	else
529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
530	# endif
531	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
532	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
533	}
534	else
535	{
536	GstWalk.Pte.u \|= X86_PTE_A;
537	GstWalk.pPte->u \|= X86_PTE_A;
538	}
539	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
540	}
541	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
542	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
543	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
544	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
545	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
546
547	/* Take the big lock now. */
548	*pfLockTaken = true;
549	pgmLock(pVM);
550
551	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
552	/*
553	* If it is a reserved bit fault we know that it is an MMIO (access
554	* handler) related fault and can skip some 200 lines of code.
555	*/
556	if (uErr & X86_TRAP_PF_RSVD)
557	{
558	Assert(uErr & X86_TRAP_PF_P);
559	PPGMPAGE pPage;
560	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
561	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
562	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
563	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
564	pfLockTaken, &GstWalk));
565	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
566	# else
567	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
568	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
569	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
570	pfLockTaken));
571	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
572	# endif
573	AssertRC(rc);
574	PGM_INVL_PG(pVCpu, pvFault);
575	return rc; /* Restart with the corrected entry. */
576	}
577	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
578
579	/*
580	* Fetch the guest PDE, PDPE and PML4E.
581	*/
582	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
583	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
584	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
585
586	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
587	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
588	PX86PDPAE pPDDst;
589	# if PGM_GST_TYPE == PGM_TYPE_PAE
590	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
591	# else
592	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
593	# endif
594	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
595
596	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
597	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
598	PX86PDPAE pPDDst;
599	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
600	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
601	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
602	# else
603	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
604	# endif
605	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
606
607	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
608	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
609	PEPTPD pPDDst;
610	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
611	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
612	# endif
613	Assert(pPDDst);
614
615	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
616	/*
617	* Dirty page handling.
618	*
619	* If we successfully correct the write protection fault due to dirty bit
620	* tracking, then return immediately.
621	*/
622	if (uErr & X86_TRAP_PF_RW) /* write fault? */
623	{
624	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
625	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
626	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
627	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
628	{
629	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
630	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
631	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
632	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
633	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
634	return VINF_SUCCESS;
635	}
636	#ifdef DEBUG_bird
637	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
638	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
639	#endif
640	}
641
642	# if 0 /* rarely useful; leave for debugging. */
643	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
644	# endif
645	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
646
647	/*
648	* A common case is the not-present error caused by lazy page table syncing.
649	*
650	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
651	* here so we can safely assume that the shadow PT is present when calling
652	* SyncPage later.
653	*
654	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
655	* of mapping conflict and defer to SyncCR3 in R3.
656	* (Again, we do NOT support access handlers for non-present guest pages.)
657	*
658	*/
659	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
660	Assert(GstWalk.Pde.n.u1Present);
661	# endif
662	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
663	&& !pPDDst->a[iPDDst].n.u1Present)
664	{
665	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
666	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
667	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
668	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
669	# else
670	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
671	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
672	# endif
673	if (RT_SUCCESS(rc))
674	return rc;
675	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
676	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
677	return VINF_PGM_SYNC_CR3;
678	}
679
680	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
681	/*
682	* Check if this address is within any of our mappings.
683	*
684	* This is very fast and it's gonna save us a bit of effort below and prevent
685	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
686	* (BTW, it's impossible to have physical access handlers in a mapping.)
687	*/
688	if (pgmMapAreMappingsEnabled(pVM))
689	{
690	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
691	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
692	{
693	if (pvFault < pMapping->GCPtr)
694	break;
695	if (pvFault - pMapping->GCPtr < pMapping->cb)
696	{
697	/*
698	* The first thing we check is if we've got an undetected conflict.
699	*/
700	if (pgmMapAreMappingsFloating(pVM))
701	{
702	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
703	while (iPT-- > 0)
704	if (GstWalk.pPde[iPT].n.u1Present)
705	{
706	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
707	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
708	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
709	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
710	return VINF_PGM_SYNC_CR3;
711	}
712	}
713
714	/*
715	* Check if the fault address is in a virtual page access handler range.
716	*/
717	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers,
718	pvFault);
719	if ( pCur
720	&& pvFault - pCur->Core.Key < pCur->cb
721	&& uErr & X86_TRAP_PF_RW)
722	{
723	VBOXSTRICTRC rcStrict;
724	# ifdef IN_RC
725	STAM_PROFILE_START(&pCur->Stat, h);
726	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
727	void *pvUser = pCur->CTX_SUFF(pvUser);
728	pgmUnlock(pVM);
729	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
730	pvFault - pCur->Core.Key, pvUser);
731	pgmLock(pVM);
732	STAM_PROFILE_STOP(&pCur->Stat, h);
733	# else
734	AssertFailed();
735	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
736	# endif
737	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
738	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
739	return VBOXSTRICTRC_TODO(rcStrict);
740	}
741
742	/*
743	* Pretend we're not here and let the guest handle the trap.
744	*/
745	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
746	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
747	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
748	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
749	return VINF_EM_RAW_GUEST_TRAP;
750	}
751	}
752	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
753	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
754
755	/*
756	* Check if this fault address is flagged for special treatment,
757	* which means we'll have to figure out the physical address and
758	* check flags associated with it.
759	*
760	* ASSUME that we can limit any special access handling to pages
761	* in page tables which the guest believes to be present.
762	*/
763	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
764	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
765	# else
766	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
767	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
768	PPGMPAGE pPage;
769	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
770	if (RT_FAILURE(rc))
771	{
772	/*
773	* When the guest accesses invalid physical memory (e.g. probing
774	* of RAM or accessing a remapped MMIO range), then we'll fall
775	* back to the recompiler to emulate the instruction.
776	*/
777	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
778	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
779	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
780	return VINF_EM_RAW_EMULATE_INSTR;
781	}
782
783	/*
784	* Any handlers for this page?
785	*/
786	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
787	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
788	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
789	&GstWalk));
790	# else
791	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
792	# endif
793
794	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
795	if (uErr & X86_TRAP_PF_P)
796	{
797	/*
798	* The page isn't marked, but it might still be monitored by a virtual page access handler.
799	* (ASSUMES no temporary disabling of virtual handlers.)
800	*/
801	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
802	* we should correct both the shadow page table and physical memory flags, and not only check for
803	* accesses within the handler region but for access to pages with virtual handlers. */
804	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
805	if (pCur)
806	{
807	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
808	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
809	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
810	\|\| !(uErr & X86_TRAP_PF_P)
811	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
812	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enumKind=%d\n",
813	pvFault, GCPhys, pPage, uErr, pCurType->enmKind));
814
815	if ( pvFault - pCur->Core.Key < pCur->cb
816	&& ( uErr & X86_TRAP_PF_RW
817	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
818	{
819	VBOXSTRICTRC rcStrict;
820	# ifdef IN_RC
821	STAM_PROFILE_START(&pCur->Stat, h);
822	void *pvUser = pCur->CTX_SUFF(pvUser);
823	pgmUnlock(pVM);
824	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
825	pvFault - pCur->Core.Key, pvUser);
826	pgmLock(pVM);
827	STAM_PROFILE_STOP(&pCur->Stat, h);
828	# else
829	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
830	# endif
831	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
832	return VBOXSTRICTRC_TODO(rcStrict);
833	}
834	}
835	}
836	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
837
838	/*
839	* We are here only if page is present in Guest page tables and
840	* trap is not handled by our handlers.
841	*
842	* Check it for page out-of-sync situation.
843	*/
844	if (!(uErr & X86_TRAP_PF_P))
845	{
846	/*
847	* Page is not present in our page tables. Try to sync it!
848	*/
849	if (uErr & X86_TRAP_PF_US)
850	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
851	else /* supervisor */
852	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
853
854	if (PGM_PAGE_IS_BALLOONED(pPage))
855	{
856	/* Emulate reads from ballooned pages as they are not present in
857	our shadow page tables. (Required for e.g. Solaris guests; soft
858	ecc, random nr generator.) */
859	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
860	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
861	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
862	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
863	return rc;
864	}
865
866	# if defined(LOG_ENABLED) && !defined(IN_RING0)
867	RTGCPHYS GCPhys2;
868	uint64_t fPageGst2;
869	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
870	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
871	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
872	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
873	# else
874	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
875	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
876	# endif
877	# endif /* LOG_ENABLED */
878
879	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
880	if ( !GstWalk.Core.fEffectiveUS
881	&& CSAMIsEnabled(pVM)
882	&& CPUMGetGuestCPL(pVCpu) == 0)
883	{
884	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
885	if ( pvFault == (RTGCPTR)pRegFrame->eip
886	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
887	# ifdef CSAM_DETECT_NEW_CODE_PAGES
888	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
889	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
890	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
891	)
892	{
893	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
894	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
895	if (rc != VINF_SUCCESS)
896	{
897	/*
898	* CSAM needs to perform a job in ring 3.
899	*
900	* Sync the page before going to the host context; otherwise we'll end up in a loop if
901	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
902	*/
903	LogFlow(("CSAM ring 3 job\n"));
904	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
905	AssertRC(rc2);
906
907	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
908	return rc;
909	}
910	}
911	# ifdef CSAM_DETECT_NEW_CODE_PAGES
912	else if ( uErr == X86_TRAP_PF_RW
913	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
914	&& pRegFrame->ecx < 0x10000)
915	{
916	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
917	* to detect loading of new code pages.
918	*/
919
920	/*
921	* Decode the instruction.
922	*/
923	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
924	uint32_t cbOp;
925	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
926
927	/* For now we'll restrict this to rep movsw/d instructions */
928	if ( rc == VINF_SUCCESS
929	&& pDis->pCurInstr->opcode == OP_MOVSWD
930	&& (pDis->prefix & DISPREFIX_REP))
931	{
932	CSAMMarkPossibleCodePage(pVM, pvFault);
933	}
934	}
935	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
936
937	/*
938	* Mark this page as safe.
939	*/
940	/** @todo not correct for pages that contain both code and data!! */
941	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
942	CSAMMarkPage(pVM, pvFault, true);
943	}
944	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
945	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
946	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
947	# else
948	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
949	# endif
950	if (RT_SUCCESS(rc))
951	{
952	/* The page was successfully synced, return to the guest. */
953	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
954	return VINF_SUCCESS;
955	}
956	}
957	else /* uErr & X86_TRAP_PF_P: */
958	{
959	/*
960	* Write protected pages are made writable when the guest makes the
961	* first write to it. This happens for pages that are shared, write
962	* monitored or not yet allocated.
963	*
964	* We may also end up here when CR0.WP=0 in the guest.
965	*
966	* Also, a side effect of not flushing global PDEs are out of sync
967	* pages due to physical monitored regions, that are no longer valid.
968	* Assume for now it only applies to the read/write flag.
969	*/
970	if (uErr & X86_TRAP_PF_RW)
971	{
972	/*
973	* Check if it is a read-only page.
974	*/
975	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
976	{
977	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
978	Assert(!PGM_PAGE_IS_ZERO(pPage));
979	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
980	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
981
982	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
983	if (rc != VINF_SUCCESS)
984	{
985	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
986	return rc;
987	}
988	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
989	return VINF_EM_NO_MEMORY;
990	}
991
992	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
993	/*
994	* Check to see if we need to emulate the instruction if CR0.WP=0.
995	*/
996	if ( !GstWalk.Core.fEffectiveRW
997	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
998	&& CPUMGetGuestCPL(pVCpu) < 3)
999	{
1000	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
1001
1002	/*
1003	* The Netware WP0+RO+US hack.
1004	*
1005	* Netware sometimes(/always?) runs with WP0. It has been observed doing
1006	* excessive write accesses to pages which are mapped with US=1 and RW=0
1007	* while WP=0. This causes a lot of exits and extremely slow execution.
1008	* To avoid trapping and emulating every write here, we change the shadow
1009	* page table entry to map it as US=0 and RW=1 until user mode tries to
1010	* access it again (see further below). We count these shadow page table
1011	* changes so we can avoid having to clear the page pool every time the WP
1012	* bit changes to 1 (see PGMCr0WpEnabled()).
1013	*/
1014	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1015	if ( GstWalk.Core.fEffectiveUS
1016	&& !GstWalk.Core.fEffectiveRW
1017	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1018	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1019	{
1020	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1021	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1022	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1023	{
1024	PGM_INVL_PG(pVCpu, pvFault);
1025	pVCpu->pgm.s.cNetwareWp0Hacks++;
1026	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1027	return rc;
1028	}
1029	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1030	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1031	}
1032	# endif
1033
1034	/* Interpret the access. */
1035	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1036	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1037	if (RT_SUCCESS(rc))
1038	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1039	else
1040	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1041	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1042	return rc;
1043	}
1044	# endif
1045	/// @todo count the above case; else
1046	if (uErr & X86_TRAP_PF_US)
1047	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1048	else /* supervisor */
1049	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1050
1051	/*
1052	* Sync the page.
1053	*
1054	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1055	* page is not present, which is not true in this case.
1056	*/
1057	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1058	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1059	# else
1060	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1061	# endif
1062	if (RT_SUCCESS(rc))
1063	{
1064	/*
1065	* Page was successfully synced, return to guest but invalidate
1066	* the TLB first as the page is very likely to be in it.
1067	*/
1068	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1069	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1070	# else
1071	PGM_INVL_PG(pVCpu, pvFault);
1072	# endif
1073	# ifdef VBOX_STRICT
1074	RTGCPHYS GCPhys2 = RTGCPHYS_MAX;
1075	uint64_t fPageGst = UINT64_MAX;
1076	if (!pVM->pgm.s.fNestedPaging)
1077	{
1078	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1079	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1080	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1081	}
1082	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
1083	uint64_t fPageShw = 0;
1084	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1085	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1086	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GCPhys2, fPageGst, pvFault));
1087	# endif
1088	# endif /* VBOX_STRICT */
1089	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1090	return VINF_SUCCESS;
1091	}
1092	}
1093	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1094	/*
1095	* Check for Netware WP0+RO+US hack from above and undo it when user
1096	* mode accesses the page again.
1097	*/
1098	else if ( GstWalk.Core.fEffectiveUS
1099	&& !GstWalk.Core.fEffectiveRW
1100	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1101	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1102	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1103	&& CPUMGetGuestCPL(pVCpu) == 3
1104	&& pVM->cCpus == 1
1105	)
1106	{
1107	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1108	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1109	if (RT_SUCCESS(rc))
1110	{
1111	PGM_INVL_PG(pVCpu, pvFault);
1112	pVCpu->pgm.s.cNetwareWp0Hacks--;
1113	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1114	return VINF_SUCCESS;
1115	}
1116	}
1117	# endif /* PGM_WITH_PAGING */
1118
1119	/** @todo else: why are we here? */
1120
1121	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1122	/*
1123	* Check for VMM page flags vs. Guest page flags consistency.
1124	* Currently only for debug purposes.
1125	*/
1126	if (RT_SUCCESS(rc))
1127	{
1128	/* Get guest page flags. */
1129	uint64_t fPageGst;
1130	int rc2 = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1131	if (RT_SUCCESS(rc2))
1132	{
1133	uint64_t fPageShw = 0;
1134	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1135
1136	#if 0
1137	/*
1138	* Compare page flags.
1139	* Note: we have AVL, A, D bits desynced.
1140	*/
1141	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1142	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1143	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1144	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1145	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1146	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1147	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1148	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
1149	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
1150	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
1151	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
1152
1153	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
1154	01:01:15.625516 00:08:43.268051 Location :
1155	e:\vbox\svn\trunk\srcPage flags mismatch!
1156	pvFault=fffff801b0d7b000
1157	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
1158	GCPhys=0000000019b52000
1159	fPageShw=0
1160	fPageGst=77b0000000000121
1161	rc=0
1162	#endif
1163
1164	}
1165	else
1166	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1167	}
1168	else
1169	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1170	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1171	}
1172
1173
1174	/*
1175	* If we get here it is because something failed above, i.e. most like guru
1176	* meditiation time.
1177	*/
1178	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1179	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1180	return rc;
1181
1182	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1183	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1184	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1185	return VERR_PGM_NOT_USED_IN_MODE;
1186	# endif
1187	}
1188	#endif /* !IN_RING3 */
1189
1190
1191	/**
1192	* Emulation of the invlpg instruction.
1193	*
1194	*
1195	* @returns VBox status code.
1196	*
1197	* @param pVCpu The cross context virtual CPU structure.
1198	* @param GCPtrPage Page to invalidate.
1199	*
1200	* @remark ASSUMES that the guest is updating before invalidating. This order
1201	* isn't required by the CPU, so this is speculative and could cause
1202	* trouble.
1203	* @remark No TLB shootdown is done on any other VCPU as we assume that
1204	* invlpg emulation is the only reason for calling this function.
1205	* (The guest has to shoot down TLB entries on other CPUs itself)
1206	* Currently true, but keep in mind!
1207	*
1208	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1209	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1210	*/
1211	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1212	{
1213	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1214	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1215	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1216	int rc;
1217	PVM pVM = pVCpu->CTX_SUFF(pVM);
1218	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1219
1220	PGM_LOCK_ASSERT_OWNER(pVM);
1221
1222	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1223
1224	/*
1225	* Get the shadow PD entry and skip out if this PD isn't present.
1226	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1227	*/
1228	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1229	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1230	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1231
1232	/* Fetch the pgm pool shadow descriptor. */
1233	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1234	Assert(pShwPde);
1235
1236	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1237	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1238	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1239
1240	/* If the shadow PDPE isn't present, then skip the invalidate. */
1241	if (!pPdptDst->a[iPdpt].n.u1Present)
1242	{
1243	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1245	PGM_INVL_PG(pVCpu, GCPtrPage);
1246	return VINF_SUCCESS;
1247	}
1248
1249	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1250	PPGMPOOLPAGE pShwPde = NULL;
1251	PX86PDPAE pPDDst;
1252
1253	/* Fetch the pgm pool shadow descriptor. */
1254	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1255	AssertRCSuccessReturn(rc, rc);
1256	Assert(pShwPde);
1257
1258	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1259	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1260
1261	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1262	/* PML4 */
1263	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1264	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1265	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1266	PX86PDPAE pPDDst;
1267	PX86PDPT pPdptDst;
1268	PX86PML4E pPml4eDst;
1269	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1270	if (rc != VINF_SUCCESS)
1271	{
1272	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1273	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1274	PGM_INVL_PG(pVCpu, GCPtrPage);
1275	return VINF_SUCCESS;
1276	}
1277	Assert(pPDDst);
1278
1279	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1280	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1281
1282	if (!pPdpeDst->n.u1Present)
1283	{
1284	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1285	PGM_INVL_PG(pVCpu, GCPtrPage);
1286	return VINF_SUCCESS;
1287	}
1288
1289	/* Fetch the pgm pool shadow descriptor. */
1290	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1291	Assert(pShwPde);
1292
1293	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1294
1295	const SHWPDE PdeDst = *pPdeDst;
1296	if (!PdeDst.n.u1Present)
1297	{
1298	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1299	PGM_INVL_PG(pVCpu, GCPtrPage);
1300	return VINF_SUCCESS;
1301	}
1302
1303	/*
1304	* Get the guest PD entry and calc big page.
1305	*/
1306	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1307	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1308	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1309	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1310	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1311	unsigned iPDSrc = 0;
1312	# if PGM_GST_TYPE == PGM_TYPE_PAE
1313	X86PDPE PdpeSrcIgn;
1314	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1315	# else /* AMD64 */
1316	PX86PML4E pPml4eSrcIgn;
1317	X86PDPE PdpeSrcIgn;
1318	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1319	# endif
1320	GSTPDE PdeSrc;
1321
1322	if (pPDSrc)
1323	PdeSrc = pPDSrc->a[iPDSrc];
1324	else
1325	PdeSrc.u = 0;
1326	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1327	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1328
1329	# ifdef IN_RING3
1330	/*
1331	* If a CR3 Sync is pending we may ignore the invalidate page operation
1332	* depending on the kind of sync and if it's a global page or not.
1333	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1334	*/
1335	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1336	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1337	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1338	&& fIsBigPage
1339	&& PdeSrc.b.u1Global
1340	)
1341	)
1342	# else
1343	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1344	# endif
1345	{
1346	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1347	return VINF_SUCCESS;
1348	}
1349	# endif /* IN_RING3 */
1350
1351	/*
1352	* Deal with the Guest PDE.
1353	*/
1354	rc = VINF_SUCCESS;
1355	if (PdeSrc.n.u1Present)
1356	{
1357	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1358	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1359	# ifndef PGM_WITHOUT_MAPPING
1360	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1361	{
1362	/*
1363	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1364	*/
1365	Assert(pgmMapAreMappingsEnabled(pVM));
1366	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1367	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1368	}
1369	else
1370	# endif /* !PGM_WITHOUT_MAPPING */
1371	if (!fIsBigPage)
1372	{
1373	/*
1374	* 4KB - page.
1375	*/
1376	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1377	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1378
1379	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1380	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1381	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1382	# endif
1383	if (pShwPage->GCPhys == GCPhys)
1384	{
1385	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1386	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1387
1388	PGSTPT pPTSrc;
1389	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1390	if (RT_SUCCESS(rc))
1391	{
1392	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1393	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1394	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1395	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1396	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1397	GCPtrPage, PteSrc.n.u1Present,
1398	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1399	PteSrc.n.u1User & PdeSrc.n.u1User,
1400	(uint64_t)PteSrc.u,
1401	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1402	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1403	}
1404	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1405	PGM_INVL_PG(pVCpu, GCPtrPage);
1406	}
1407	else
1408	{
1409	/*
1410	* The page table address changed.
1411	*/
1412	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1413	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1414	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1415	ASMAtomicWriteSize(pPdeDst, 0);
1416	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1417	PGM_INVL_VCPU_TLBS(pVCpu);
1418	}
1419	}
1420	else
1421	{
1422	/*
1423	* 2/4MB - page.
1424	*/
1425	/* Before freeing the page, check if anything really changed. */
1426	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1427	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1428	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1429	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1430	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1431	# endif
1432	if ( pShwPage->GCPhys == GCPhys
1433	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1434	{
1435	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1436	/** @todo This test is wrong as it cannot check the G bit!
1437	* FIXME */
1438	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1439	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1440	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1441	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1442	{
1443	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1444	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1445	return VINF_SUCCESS;
1446	}
1447	}
1448
1449	/*
1450	* Ok, the page table is present and it's been changed in the guest.
1451	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1452	* We could do this for some flushes in GC too, but we need an algorithm for
1453	* deciding which 4MB pages containing code likely to be executed very soon.
1454	*/
1455	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1456	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1457	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1458	ASMAtomicWriteSize(pPdeDst, 0);
1459	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1460	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1461	}
1462	}
1463	else
1464	{
1465	/*
1466	* Page directory is not present, mark shadow PDE not present.
1467	*/
1468	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1469	{
1470	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1471	ASMAtomicWriteSize(pPdeDst, 0);
1472	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1473	PGM_INVL_PG(pVCpu, GCPtrPage);
1474	}
1475	else
1476	{
1477	Assert(pgmMapAreMappingsEnabled(pVM));
1478	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1479	}
1480	}
1481	return rc;
1482
1483	#else /* guest real and protected mode */
1484	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1485	NOREF(pVCpu); NOREF(GCPtrPage);
1486	return VINF_SUCCESS;
1487	#endif
1488	}
1489
1490
1491	/**
1492	* Update the tracking of shadowed pages.
1493	*
1494	* @param pVCpu The cross context virtual CPU structure.
1495	* @param pShwPage The shadow page.
1496	* @param HCPhys The physical page we is being dereferenced.
1497	* @param iPte Shadow PTE index
1498	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1499	*/
1500	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1501	RTGCPHYS GCPhysPage)
1502	{
1503	PVM pVM = pVCpu->CTX_SUFF(pVM);
1504
1505	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1506	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1507	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1508
1509	/* Use the hint we retrieved from the cached guest PT. */
1510	if (pShwPage->fDirty)
1511	{
1512	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1513
1514	Assert(pShwPage->cPresent);
1515	Assert(pPool->cPresent);
1516	pShwPage->cPresent--;
1517	pPool->cPresent--;
1518
1519	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1520	AssertRelease(pPhysPage);
1521	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1522	return;
1523	}
1524	# else
1525	NOREF(GCPhysPage);
1526	# endif
1527
1528	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1529	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1530
1531	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1532	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1533	* 2. write protect all shadowed pages. I.e. implement caching.
1534	*/
1535	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1536
1537	/*
1538	* Find the guest address.
1539	*/
1540	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1541	pRam;
1542	pRam = pRam->CTX_SUFF(pNext))
1543	{
1544	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1545	while (iPage-- > 0)
1546	{
1547	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1548	{
1549	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1550
1551	Assert(pShwPage->cPresent);
1552	Assert(pPool->cPresent);
1553	pShwPage->cPresent--;
1554	pPool->cPresent--;
1555
1556	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1557	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1558	return;
1559	}
1560	}
1561	}
1562
1563	for (;;)
1564	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1565	}
1566
1567
1568	/**
1569	* Update the tracking of shadowed pages.
1570	*
1571	* @param pVCpu The cross context virtual CPU structure.
1572	* @param pShwPage The shadow page.
1573	* @param u16 The top 16-bit of the pPage->HCPhys.
1574	* @param pPage Pointer to the guest page. this will be modified.
1575	* @param iPTDst The index into the shadow table.
1576	*/
1577	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1578	{
1579	PVM pVM = pVCpu->CTX_SUFF(pVM);
1580
1581	/*
1582	* Just deal with the simple first time here.
1583	*/
1584	if (!u16)
1585	{
1586	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1587	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1588	/* Save the page table index. */
1589	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1590	}
1591	else
1592	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1593
1594	/* write back */
1595	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1596	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1597
1598	/* update statistics. */
1599	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1600	pShwPage->cPresent++;
1601	if (pShwPage->iFirstPresent > iPTDst)
1602	pShwPage->iFirstPresent = iPTDst;
1603	}
1604
1605
1606	/**
1607	* Modifies a shadow PTE to account for access handlers.
1608	*
1609	* @param pVM The cross context VM structure.
1610	* @param pPage The page in question.
1611	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1612	* A (accessed) bit so it can be emulated correctly.
1613	* @param pPteDst The shadow PTE (output). This is temporary storage and
1614	* does not need to be set atomically.
1615	*/
1616	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1617	{
1618	NOREF(pVM); RT_NOREF_PV(fPteSrc);
1619
1620	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1621	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1622	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1623	{
1624	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1625	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1626	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1627	pPteDst->n.u1Present = 1;
1628	pPteDst->n.u1Execute = 1;
1629	pPteDst->n.u1IgnorePAT = 1;
1630	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1631	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1632	#else
1633	if (fPteSrc & X86_PTE_A)
1634	{
1635	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1636	SHW_PTE_SET_RO(*pPteDst);
1637	}
1638	else
1639	SHW_PTE_SET(*pPteDst, 0);
1640	#endif
1641	}
1642	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1643	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1644	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1645	&& ( BTH_IS_NP_ACTIVE(pVM)
1646	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1647	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1648	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1649	# endif
1650	)
1651	{
1652	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1653	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1654	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1655	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1656	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1657	pPteDst->n.u1Present = 0;
1658	pPteDst->n.u1Write = 1;
1659	pPteDst->n.u1Execute = 0;
1660	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1661	pPteDst->n.u3EMT = 7;
1662	# else
1663	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1664	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1665	# endif
1666	}
1667	# endif
1668	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1669	else
1670	{
1671	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1672	SHW_PTE_SET(*pPteDst, 0);
1673	}
1674	/** @todo count these kinds of entries. */
1675	}
1676
1677
1678	/**
1679	* Creates a 4K shadow page for a guest page.
1680	*
1681	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1682	* physical address. The PdeSrc argument only the flags are used. No page
1683	* structured will be mapped in this function.
1684	*
1685	* @param pVCpu The cross context virtual CPU structure.
1686	* @param pPteDst Destination page table entry.
1687	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1688	* Can safely assume that only the flags are being used.
1689	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1690	* @param pShwPage Pointer to the shadow page.
1691	* @param iPTDst The index into the shadow table.
1692	*
1693	* @remark Not used for 2/4MB pages!
1694	*/
1695	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1696	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1697	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1698	#else
1699	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1700	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1701	#endif
1702	{
1703	PVM pVM = pVCpu->CTX_SUFF(pVM);
1704	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1705
1706	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1707	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1708	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1709
1710	if (pShwPage->fDirty)
1711	{
1712	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1713	PGSTPT pGstPT;
1714
1715	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1716	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1717	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1718	pGstPT->a[iPTDst].u = PteSrc.u;
1719	}
1720	#else
1721	Assert(!pShwPage->fDirty);
1722	#endif
1723
1724	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1725	if ( PteSrc.n.u1Present
1726	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1727	#endif
1728	{
1729	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1730	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1731	# endif
1732	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1733
1734	/*
1735	* Find the ram range.
1736	*/
1737	PPGMPAGE pPage;
1738	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1739	if (RT_SUCCESS(rc))
1740	{
1741	/* Ignore ballooned pages.
1742	Don't return errors or use a fatal assert here as part of a
1743	shadow sync range might included ballooned pages. */
1744	if (PGM_PAGE_IS_BALLOONED(pPage))
1745	{
1746	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1747	return;
1748	}
1749
1750	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1751	/* Make the page writable if necessary. */
1752	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1753	&& ( PGM_PAGE_IS_ZERO(pPage)
1754	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1755	\|\| ( PteSrc.n.u1Write
1756	# else
1757	\|\| ( 1
1758	# endif
1759	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1760	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1761	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1762	# endif
1763	# ifdef VBOX_WITH_PAGE_SHARING
1764	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1765	# endif
1766	)
1767	)
1768	)
1769	{
1770	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1771	AssertRC(rc);
1772	}
1773	#endif
1774
1775	/*
1776	* Make page table entry.
1777	*/
1778	SHWPTE PteDst;
1779	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1780	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1781	# else
1782	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1783	# endif
1784	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1785	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1786	else
1787	{
1788	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1789	/*
1790	* If the page or page directory entry is not marked accessed,
1791	* we mark the page not present.
1792	*/
1793	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1794	{
1795	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1796	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1797	SHW_PTE_SET(PteDst, 0);
1798	}
1799	/*
1800	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1801	* when the page is modified.
1802	*/
1803	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1804	{
1805	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1806	SHW_PTE_SET(PteDst,
1807	fGstShwPteFlags
1808	\| PGM_PAGE_GET_HCPHYS(pPage)
1809	\| PGM_PTFLAGS_TRACK_DIRTY);
1810	SHW_PTE_SET_RO(PteDst);
1811	}
1812	else
1813	#endif
1814	{
1815	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1816	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1817	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1818	PteDst.n.u1Present = 1;
1819	PteDst.n.u1Write = 1;
1820	PteDst.n.u1Execute = 1;
1821	PteDst.n.u1IgnorePAT = 1;
1822	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1823	/* PteDst.n.u1Size = 0 */
1824	#else
1825	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1826	#endif
1827	}
1828
1829	/*
1830	* Make sure only allocated pages are mapped writable.
1831	*/
1832	if ( SHW_PTE_IS_P_RW(PteDst)
1833	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1834	{
1835	/* Still applies to shared pages. */
1836	Assert(!PGM_PAGE_IS_ZERO(pPage));
1837	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1838	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1839	}
1840	}
1841
1842	/*
1843	* Keep user track up to date.
1844	*/
1845	if (SHW_PTE_IS_P(PteDst))
1846	{
1847	if (!SHW_PTE_IS_P(*pPteDst))
1848	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1849	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1850	{
1851	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1852	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1853	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1854	}
1855	}
1856	else if (SHW_PTE_IS_P(*pPteDst))
1857	{
1858	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1859	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1860	}
1861
1862	/*
1863	* Update statistics and commit the entry.
1864	*/
1865	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1866	if (!PteSrc.n.u1Global)
1867	pShwPage->fSeenNonGlobal = true;
1868	#endif
1869	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1870	return;
1871	}
1872
1873	/** @todo count these three different kinds. */
1874	Log2(("SyncPageWorker: invalid address in Pte\n"));
1875	}
1876	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1877	else if (!PteSrc.n.u1Present)
1878	Log2(("SyncPageWorker: page not present in Pte\n"));
1879	else
1880	Log2(("SyncPageWorker: invalid Pte\n"));
1881	#endif
1882
1883	/*
1884	* The page is not present or the PTE is bad. Replace the shadow PTE by
1885	* an empty entry, making sure to keep the user tracking up to date.
1886	*/
1887	if (SHW_PTE_IS_P(*pPteDst))
1888	{
1889	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1890	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1891	}
1892	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1893	}
1894
1895
1896	/**
1897	* Syncs a guest OS page.
1898	*
1899	* There are no conflicts at this point, neither is there any need for
1900	* page table allocations.
1901	*
1902	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1903	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1904	*
1905	* @returns VBox status code.
1906	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1907	* @param pVCpu The cross context virtual CPU structure.
1908	* @param PdeSrc Page directory entry of the guest.
1909	* @param GCPtrPage Guest context page address.
1910	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1911	* @param uErr Fault error (X86_TRAP_PF_*).
1912	*/
1913	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1914	{
1915	PVM pVM = pVCpu->CTX_SUFF(pVM);
1916	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1917	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1918	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
1919
1920	PGM_LOCK_ASSERT_OWNER(pVM);
1921
1922	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1923	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1924	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1925	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1926	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1927
1928	/*
1929	* Assert preconditions.
1930	*/
1931	Assert(PdeSrc.n.u1Present);
1932	Assert(cPages);
1933	# if 0 /* rarely useful; leave for debugging. */
1934	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1935	# endif
1936
1937	/*
1938	* Get the shadow PDE, find the shadow page table in the pool.
1939	*/
1940	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1941	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1942	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1943
1944	/* Fetch the pgm pool shadow descriptor. */
1945	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1946	Assert(pShwPde);
1947
1948	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1949	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1950	PPGMPOOLPAGE pShwPde = NULL;
1951	PX86PDPAE pPDDst;
1952
1953	/* Fetch the pgm pool shadow descriptor. */
1954	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1955	AssertRCSuccessReturn(rc2, rc2);
1956	Assert(pShwPde);
1957
1958	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1959	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1960
1961	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1962	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1963	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1964	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1965	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1966
1967	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1968	AssertRCSuccessReturn(rc2, rc2);
1969	Assert(pPDDst && pPdptDst);
1970	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1971	# endif
1972	SHWPDE PdeDst = *pPdeDst;
1973
1974	/*
1975	* - In the guest SMP case we could have blocked while another VCPU reused
1976	* this page table.
1977	* - With W7-64 we may also take this path when the A bit is cleared on
1978	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1979	* relevant TLB entries. If we're write monitoring any page mapped by
1980	* the modified entry, we may end up here with a "stale" TLB entry.
1981	*/
1982	if (!PdeDst.n.u1Present)
1983	{
1984	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1985	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1986	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1987	if (uErr & X86_TRAP_PF_P)
1988	PGM_INVL_PG(pVCpu, GCPtrPage);
1989	return VINF_SUCCESS; /* force the instruction to be executed again. */
1990	}
1991
1992	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1993	Assert(pShwPage);
1994
1995	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1996	/* Fetch the pgm pool shadow descriptor. */
1997	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1998	Assert(pShwPde);
1999	# endif
2000
2001	/*
2002	* Check that the page is present and that the shadow PDE isn't out of sync.
2003	*/
2004	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
2005	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2006	RTGCPHYS GCPhys;
2007	if (!fBigPage)
2008	{
2009	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2010	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2011	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2012	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2013	# endif
2014	}
2015	else
2016	{
2017	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2018	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2019	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2020	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2021	# endif
2022	}
2023	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2024	if ( fPdeValid
2025	&& pShwPage->GCPhys == GCPhys
2026	&& PdeSrc.n.u1Present
2027	&& PdeSrc.n.u1User == PdeDst.n.u1User
2028	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
2029	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2030	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2031	# endif
2032	)
2033	{
2034	/*
2035	* Check that the PDE is marked accessed already.
2036	* Since we set the accessed bit before getting here on a #PF, this
2037	* check is only meant for dealing with non-#PF'ing paths.
2038	*/
2039	if (PdeSrc.n.u1Accessed)
2040	{
2041	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2042	if (!fBigPage)
2043	{
2044	/*
2045	* 4KB Page - Map the guest page table.
2046	*/
2047	PGSTPT pPTSrc;
2048	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2049	if (RT_SUCCESS(rc))
2050	{
2051	# ifdef PGM_SYNC_N_PAGES
2052	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2053	if ( cPages > 1
2054	&& !(uErr & X86_TRAP_PF_P)
2055	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2056	{
2057	/*
2058	* This code path is currently only taken when the caller is PGMTrap0eHandler
2059	* for non-present pages!
2060	*
2061	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2062	* deal with locality.
2063	*/
2064	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2065	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2066	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2067	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2068	# else
2069	const unsigned offPTSrc = 0;
2070	# endif
2071	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2072	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2073	iPTDst = 0;
2074	else
2075	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2076
2077	for (; iPTDst < iPTDstEnd; iPTDst++)
2078	{
2079	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2080
2081	if ( pPteSrc->n.u1Present
2082	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2083	{
2084	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2085	NOREF(GCPtrCurPage);
2086	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2087	/*
2088	* Assuming kernel code will be marked as supervisor - and not as user level
2089	* and executed using a conforming code selector - And marked as readonly.
2090	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2091	*/
2092	PPGMPAGE pPage;
2093	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2094	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2095	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2096	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2097	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2098	)
2099	# endif /* else: CSAM not active */
2100	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2101	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2102	GCPtrCurPage, pPteSrc->n.u1Present,
2103	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2104	pPteSrc->n.u1User & PdeSrc.n.u1User,
2105	(uint64_t)pPteSrc->u,
2106	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2107	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2108	}
2109	}
2110	}
2111	else
2112	# endif /* PGM_SYNC_N_PAGES */
2113	{
2114	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2115	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2116	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2117	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2118	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2119	GCPtrPage, PteSrc.n.u1Present,
2120	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2121	PteSrc.n.u1User & PdeSrc.n.u1User,
2122	(uint64_t)PteSrc.u,
2123	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2124	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2125	}
2126	}
2127	else /* MMIO or invalid page: emulated in #PF handler. */
2128	{
2129	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2130	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2131	}
2132	}
2133	else
2134	{
2135	/*
2136	* 4/2MB page - lazy syncing shadow 4K pages.
2137	* (There are many causes of getting here, it's no longer only CSAM.)
2138	*/
2139	/* Calculate the GC physical address of this 4KB shadow page. */
2140	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2141	/* Find ram range. */
2142	PPGMPAGE pPage;
2143	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2144	if (RT_SUCCESS(rc))
2145	{
2146	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2147
2148	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2149	/* Try to make the page writable if necessary. */
2150	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2151	&& ( PGM_PAGE_IS_ZERO(pPage)
2152	\|\| ( PdeSrc.n.u1Write
2153	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2154	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2155	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2156	# endif
2157	# ifdef VBOX_WITH_PAGE_SHARING
2158	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2159	# endif
2160	)
2161	)
2162	)
2163	{
2164	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2165	AssertRC(rc);
2166	}
2167	# endif
2168
2169	/*
2170	* Make shadow PTE entry.
2171	*/
2172	SHWPTE PteDst;
2173	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2174	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2175	else
2176	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2177
2178	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2179	if ( SHW_PTE_IS_P(PteDst)
2180	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2181	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2182
2183	/* Make sure only allocated pages are mapped writable. */
2184	if ( SHW_PTE_IS_P_RW(PteDst)
2185	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2186	{
2187	/* Still applies to shared pages. */
2188	Assert(!PGM_PAGE_IS_ZERO(pPage));
2189	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2190	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2191	}
2192
2193	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2194
2195	/*
2196	* If the page is not flagged as dirty and is writable, then make it read-only
2197	* at PD level, so we can set the dirty bit when the page is modified.
2198	*
2199	* ASSUMES that page access handlers are implemented on page table entry level.
2200	* Thus we will first catch the dirty access and set PDE.D and restart. If
2201	* there is an access handler, we'll trap again and let it work on the problem.
2202	*/
2203	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2204	* As for invlpg, it simply frees the whole shadow PT.
2205	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2206	if ( !PdeSrc.b.u1Dirty
2207	&& PdeSrc.b.u1Write)
2208	{
2209	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2210	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2211	PdeDst.n.u1Write = 0;
2212	}
2213	else
2214	{
2215	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2216	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2217	}
2218	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2219	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2220	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2221	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2222	}
2223	else
2224	{
2225	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2226	/** @todo must wipe the shadow page table entry in this
2227	* case. */
2228	}
2229	}
2230	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2231	return VINF_SUCCESS;
2232	}
2233
2234	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2235	}
2236	else if (fPdeValid)
2237	{
2238	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2239	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2240	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2241	}
2242	else
2243	{
2244	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2245	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2246	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2247	}
2248
2249	/*
2250	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2251	* Yea, I'm lazy.
2252	*/
2253	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2254	ASMAtomicWriteSize(pPdeDst, 0);
2255
2256	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2257	PGM_INVL_VCPU_TLBS(pVCpu);
2258	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2259
2260
2261	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2262	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2263	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2264	&& !defined(IN_RC)
2265	NOREF(PdeSrc);
2266
2267	# ifdef PGM_SYNC_N_PAGES
2268	/*
2269	* Get the shadow PDE, find the shadow page table in the pool.
2270	*/
2271	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2272	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2273
2274	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2275	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2276
2277	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2278	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2279	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2280	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2281	X86PDEPAE PdeDst;
2282	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2283
2284	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2285	AssertRCSuccessReturn(rc, rc);
2286	Assert(pPDDst && pPdptDst);
2287	PdeDst = pPDDst->a[iPDDst];
2288	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2289	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2290	PEPTPD pPDDst;
2291	EPTPDE PdeDst;
2292
2293	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2294	if (rc != VINF_SUCCESS)
2295	{
2296	AssertRC(rc);
2297	return rc;
2298	}
2299	Assert(pPDDst);
2300	PdeDst = pPDDst->a[iPDDst];
2301	# endif
2302	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2303	if (!PdeDst.n.u1Present)
2304	{
2305	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2306	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2307	return VINF_SUCCESS; /* force the instruction to be executed again. */
2308	}
2309
2310	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2311	if (PdeDst.n.u1Size)
2312	{
2313	Assert(pVM->pgm.s.fNestedPaging);
2314	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2315	return VINF_SUCCESS;
2316	}
2317
2318	/* Mask away the page offset. */
2319	GCPtrPage &= ~((RTGCPTR)0xfff);
2320
2321	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2322	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2323
2324	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2325	if ( cPages > 1
2326	&& !(uErr & X86_TRAP_PF_P)
2327	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2328	{
2329	/*
2330	* This code path is currently only taken when the caller is PGMTrap0eHandler
2331	* for non-present pages!
2332	*
2333	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2334	* deal with locality.
2335	*/
2336	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2337	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2338	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2339	iPTDst = 0;
2340	else
2341	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2342	for (; iPTDst < iPTDstEnd; iPTDst++)
2343	{
2344	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2345	{
2346	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2347	\| (iPTDst << PAGE_SHIFT));
2348
2349	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2350	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2351	GCPtrCurPage,
2352	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2353	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2354
2355	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2356	break;
2357	}
2358	else
2359	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2360	}
2361	}
2362	else
2363	# endif /* PGM_SYNC_N_PAGES */
2364	{
2365	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2366	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2367	\| (iPTDst << PAGE_SHIFT));
2368
2369	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2370
2371	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2372	GCPtrPage,
2373	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2374	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2375	}
2376	return VINF_SUCCESS;
2377
2378	#else
2379	NOREF(PdeSrc);
2380	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2381	return VERR_PGM_NOT_USED_IN_MODE;
2382	#endif
2383	}
2384
2385
2386	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2387
2388	/**
2389	* CheckPageFault helper for returning a page fault indicating a non-present
2390	* (NP) entry in the page translation structures.
2391	*
2392	* @returns VINF_EM_RAW_GUEST_TRAP.
2393	* @param pVCpu The cross context virtual CPU structure.
2394	* @param uErr The error code of the shadow fault. Corrections to
2395	* TRPM's copy will be made if necessary.
2396	* @param GCPtrPage For logging.
2397	* @param uPageFaultLevel For logging.
2398	*/
2399	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2400	{
2401	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2402	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2403	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2404	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2405	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2406
2407	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2408	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2409	return VINF_EM_RAW_GUEST_TRAP;
2410	}
2411
2412
2413	/**
2414	* CheckPageFault helper for returning a page fault indicating a reserved bit
2415	* (RSVD) error in the page translation structures.
2416	*
2417	* @returns VINF_EM_RAW_GUEST_TRAP.
2418	* @param pVCpu The cross context virtual CPU structure.
2419	* @param uErr The error code of the shadow fault. Corrections to
2420	* TRPM's copy will be made if necessary.
2421	* @param GCPtrPage For logging.
2422	* @param uPageFaultLevel For logging.
2423	*/
2424	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2425	{
2426	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2427	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2428	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2429
2430	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2431	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2432	return VINF_EM_RAW_GUEST_TRAP;
2433	}
2434
2435
2436	/**
2437	* CheckPageFault helper for returning a page protection fault (P).
2438	*
2439	* @returns VINF_EM_RAW_GUEST_TRAP.
2440	* @param pVCpu The cross context virtual CPU structure.
2441	* @param uErr The error code of the shadow fault. Corrections to
2442	* TRPM's copy will be made if necessary.
2443	* @param GCPtrPage For logging.
2444	* @param uPageFaultLevel For logging.
2445	*/
2446	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2447	{
2448	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2449	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2450	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2451	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2452
2453	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2454	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2455	return VINF_EM_RAW_GUEST_TRAP;
2456	}
2457
2458
2459	/**
2460	* Handle dirty bit tracking faults.
2461	*
2462	* @returns VBox status code.
2463	* @param pVCpu The cross context virtual CPU structure.
2464	* @param uErr Page fault error code.
2465	* @param pPdeSrc Guest page directory entry.
2466	* @param pPdeDst Shadow page directory entry.
2467	* @param GCPtrPage Guest context page address.
2468	*/
2469	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2470	RTGCPTR GCPtrPage)
2471	{
2472	PVM pVM = pVCpu->CTX_SUFF(pVM);
2473	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2474	NOREF(uErr);
2475
2476	PGM_LOCK_ASSERT_OWNER(pVM);
2477
2478	/*
2479	* Handle big page.
2480	*/
2481	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2482	{
2483	if ( pPdeDst->n.u1Present
2484	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2485	{
2486	SHWPDE PdeDst = *pPdeDst;
2487
2488	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2489	Assert(pPdeSrc->b.u1Write);
2490
2491	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2492	* fault again and take this path to only invalidate the entry (see below).
2493	*/
2494	PdeDst.n.u1Write = 1;
2495	PdeDst.n.u1Accessed = 1;
2496	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2497	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2498	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2499	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2500	}
2501
2502	# ifdef IN_RING0
2503	/* Check for stale TLB entry; only applies to the SMP guest case. */
2504	if ( pVM->cCpus > 1
2505	&& pPdeDst->n.u1Write
2506	&& pPdeDst->n.u1Accessed)
2507	{
2508	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2509	if (pShwPage)
2510	{
2511	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2512	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2513	if (SHW_PTE_IS_P_RW(*pPteDst))
2514	{
2515	/* Stale TLB entry. */
2516	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2517	PGM_INVL_PG(pVCpu, GCPtrPage);
2518	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2519	}
2520	}
2521	}
2522	# endif /* IN_RING0 */
2523	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2524	}
2525
2526	/*
2527	* Map the guest page table.
2528	*/
2529	PGSTPT pPTSrc;
2530	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2531	if (RT_FAILURE(rc))
2532	{
2533	AssertRC(rc);
2534	return rc;
2535	}
2536
2537	if (pPdeDst->n.u1Present)
2538	{
2539	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2540	const GSTPTE PteSrc = *pPteSrc;
2541
2542	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2543	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2544	* Our individual shadow handlers will provide more information and force a fatal exit.
2545	*/
2546	if ( !HMIsEnabled(pVM)
2547	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2548	{
2549	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2550	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2551	}
2552	#endif
2553	/*
2554	* Map shadow page table.
2555	*/
2556	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2557	if (pShwPage)
2558	{
2559	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2560	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2561	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2562	{
2563	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2564	{
2565	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2566	SHWPTE PteDst = *pPteDst;
2567
2568	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2569	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2570
2571	Assert(PteSrc.n.u1Write);
2572
2573	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2574	* entry will not harm; write access will simply fault again and
2575	* take this path to only invalidate the entry.
2576	*/
2577	if (RT_LIKELY(pPage))
2578	{
2579	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2580	{
2581	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2582	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2583	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2584	SHW_PTE_SET_RO(PteDst);
2585	}
2586	else
2587	{
2588	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2589	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2590	{
2591	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2592	AssertRC(rc);
2593	}
2594	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2595	SHW_PTE_SET_RW(PteDst);
2596	else
2597	{
2598	/* Still applies to shared pages. */
2599	Assert(!PGM_PAGE_IS_ZERO(pPage));
2600	SHW_PTE_SET_RO(PteDst);
2601	}
2602	}
2603	}
2604	else
2605	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2606
2607	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2608	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2609	PGM_INVL_PG(pVCpu, GCPtrPage);
2610	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2611	}
2612
2613	# ifdef IN_RING0
2614	/* Check for stale TLB entry; only applies to the SMP guest case. */
2615	if ( pVM->cCpus > 1
2616	&& SHW_PTE_IS_RW(*pPteDst)
2617	&& SHW_PTE_IS_A(*pPteDst))
2618	{
2619	/* Stale TLB entry. */
2620	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2621	PGM_INVL_PG(pVCpu, GCPtrPage);
2622	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2623	}
2624	# endif
2625	}
2626	}
2627	else
2628	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2629	}
2630
2631	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2632	}
2633
2634	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2635
2636
2637	/**
2638	* Sync a shadow page table.
2639	*
2640	* The shadow page table is not present in the shadow PDE.
2641	*
2642	* Handles mapping conflicts.
2643	*
2644	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2645	* conflict), and Trap0eHandler.
2646	*
2647	* A precondition for this method is that the shadow PDE is not present. The
2648	* caller must take the PGM lock before checking this and continue to hold it
2649	* when calling this method.
2650	*
2651	* @returns VBox status code.
2652	* @param pVCpu The cross context virtual CPU structure.
2653	* @param iPDSrc Page directory index.
2654	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2655	* Assume this is a temporary mapping.
2656	* @param GCPtrPage GC Pointer of the page that caused the fault
2657	*/
2658	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2659	{
2660	PVM pVM = pVCpu->CTX_SUFF(pVM);
2661	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2662
2663	#if 0 /* rarely useful; leave for debugging. */
2664	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2665	#endif
2666	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
2667
2668	PGM_LOCK_ASSERT_OWNER(pVM);
2669
2670	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2671	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2672	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2673	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2674	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2675
2676	int rc = VINF_SUCCESS;
2677
2678	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2679
2680	/*
2681	* Some input validation first.
2682	*/
2683	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2684
2685	/*
2686	* Get the relevant shadow PDE entry.
2687	*/
2688	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2689	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2690	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2691
2692	/* Fetch the pgm pool shadow descriptor. */
2693	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2694	Assert(pShwPde);
2695
2696	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2697	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2698	PPGMPOOLPAGE pShwPde = NULL;
2699	PX86PDPAE pPDDst;
2700	PSHWPDE pPdeDst;
2701
2702	/* Fetch the pgm pool shadow descriptor. */
2703	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2704	AssertRCSuccessReturn(rc, rc);
2705	Assert(pShwPde);
2706
2707	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2708	pPdeDst = &pPDDst->a[iPDDst];
2709
2710	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2711	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2712	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2713	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2714	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2715	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2716	AssertRCSuccessReturn(rc, rc);
2717	Assert(pPDDst);
2718	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2719	# endif
2720	SHWPDE PdeDst = *pPdeDst;
2721
2722	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2723	/* Fetch the pgm pool shadow descriptor. */
2724	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2725	Assert(pShwPde);
2726	# endif
2727
2728	# ifndef PGM_WITHOUT_MAPPINGS
2729	/*
2730	* Check for conflicts.
2731	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2732	* R3: Simply resolve the conflict.
2733	*/
2734	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2735	{
2736	Assert(pgmMapAreMappingsEnabled(pVM));
2737	# ifndef IN_RING3
2738	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2739	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2740	return VERR_ADDRESS_CONFLICT;
2741
2742	# else /* IN_RING3 */
2743	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2744	Assert(pMapping);
2745	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2746	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2747	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2748	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2749	# else
2750	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2751	# endif
2752	if (RT_FAILURE(rc))
2753	{
2754	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2755	return rc;
2756	}
2757	PdeDst = *pPdeDst;
2758	# endif /* IN_RING3 */
2759	}
2760	# endif /* !PGM_WITHOUT_MAPPINGS */
2761	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2762
2763	/*
2764	* Sync the page directory entry.
2765	*/
2766	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2767	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2768	if ( PdeSrc.n.u1Present
2769	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2770	{
2771	/*
2772	* Allocate & map the page table.
2773	*/
2774	PSHWPT pPTDst;
2775	PPGMPOOLPAGE pShwPage;
2776	RTGCPHYS GCPhys;
2777	if (fPageTable)
2778	{
2779	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2780	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2781	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2782	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2783	# endif
2784	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2785	pShwPde->idx, iPDDst, false /fLockPage/,
2786	&pShwPage);
2787	}
2788	else
2789	{
2790	PGMPOOLACCESS enmAccess;
2791	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2792	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2793	# else
2794	const bool fNoExecute = false;
2795	# endif
2796
2797	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2798	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2799	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2800	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2801	# endif
2802	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2803	if (PdeSrc.n.u1User)
2804	{
2805	if (PdeSrc.n.u1Write)
2806	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2807	else
2808	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2809	}
2810	else
2811	{
2812	if (PdeSrc.n.u1Write)
2813	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2814	else
2815	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2816	}
2817	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2818	pShwPde->idx, iPDDst, false /fLockPage/,
2819	&pShwPage);
2820	}
2821	if (rc == VINF_SUCCESS)
2822	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2823	else if (rc == VINF_PGM_CACHED_PAGE)
2824	{
2825	/*
2826	* The PT was cached, just hook it up.
2827	*/
2828	if (fPageTable)
2829	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2830	else
2831	{
2832	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2833	/* (see explanation and assumptions further down.) */
2834	if ( !PdeSrc.b.u1Dirty
2835	&& PdeSrc.b.u1Write)
2836	{
2837	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2838	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2839	PdeDst.b.u1Write = 0;
2840	}
2841	}
2842	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2843	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2844	return VINF_SUCCESS;
2845	}
2846	else if (rc == VERR_PGM_POOL_FLUSHED)
2847	{
2848	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2849	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2850	return VINF_PGM_SYNC_CR3;
2851	}
2852	else
2853	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2854	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2855	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2856	* irrelevant at this point. */
2857	PdeDst.u &= X86_PDE_AVL_MASK;
2858	PdeDst.u \|= pShwPage->Core.Key;
2859
2860	/*
2861	* Page directory has been accessed (this is a fault situation, remember).
2862	*/
2863	/** @todo
2864	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2865	* fault situation. What's more, the Trap0eHandler has already set the
2866	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2867	* might need setting the accessed flag.
2868	*
2869	* The best idea is to leave this change to the caller and add an
2870	* assertion that it's set already. */
2871	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2872	if (fPageTable)
2873	{
2874	/*
2875	* Page table - 4KB.
2876	*
2877	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2878	*/
2879	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2880	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2881	PGSTPT pPTSrc;
2882	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2883	if (RT_SUCCESS(rc))
2884	{
2885	/*
2886	* Start by syncing the page directory entry so CSAM's TLB trick works.
2887	*/
2888	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2889	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2890	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2891	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2892
2893	/*
2894	* Directory/page user or supervisor privilege: (same goes for read/write)
2895	*
2896	* Directory Page Combined
2897	* U/S U/S U/S
2898	* 0 0 0
2899	* 0 1 0
2900	* 1 0 0
2901	* 1 1 1
2902	*
2903	* Simple AND operation. Table listed for completeness.
2904	*
2905	*/
2906	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2907	# ifdef PGM_SYNC_N_PAGES
2908	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2909	unsigned iPTDst = iPTBase;
2910	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2911	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2912	iPTDst = 0;
2913	else
2914	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2915	# else /* !PGM_SYNC_N_PAGES */
2916	unsigned iPTDst = 0;
2917	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2918	# endif /* !PGM_SYNC_N_PAGES */
2919	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2920	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2921	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2922	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2923	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2924	# else
2925	const unsigned offPTSrc = 0;
2926	# endif
2927	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2928	{
2929	const unsigned iPTSrc = iPTDst + offPTSrc;
2930	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2931
2932	if (PteSrc.n.u1Present)
2933	{
2934	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2935	/*
2936	* Assuming kernel code will be marked as supervisor - and not as user level
2937	* and executed using a conforming code selector - And marked as readonly.
2938	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2939	*/
2940	PPGMPAGE pPage;
2941	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2942	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2943	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2944	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2945	)
2946	# endif
2947	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2948	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2949	GCPtrCur,
2950	PteSrc.n.u1Present,
2951	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2952	PteSrc.n.u1User & PdeSrc.n.u1User,
2953	(uint64_t)PteSrc.u,
2954	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2955	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2956	}
2957	/* else: the page table was cleared by the pool */
2958	} /* for PTEs */
2959	}
2960	}
2961	else
2962	{
2963	/*
2964	* Big page - 2/4MB.
2965	*
2966	* We'll walk the ram range list in parallel and optimize lookups.
2967	* We will only sync one shadow page table at a time.
2968	*/
2969	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2970
2971	/**
2972	* @todo It might be more efficient to sync only a part of the 4MB
2973	* page (similar to what we do for 4KB PDs).
2974	*/
2975
2976	/*
2977	* Start by syncing the page directory entry.
2978	*/
2979	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2980	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2981
2982	/*
2983	* If the page is not flagged as dirty and is writable, then make it read-only
2984	* at PD level, so we can set the dirty bit when the page is modified.
2985	*
2986	* ASSUMES that page access handlers are implemented on page table entry level.
2987	* Thus we will first catch the dirty access and set PDE.D and restart. If
2988	* there is an access handler, we'll trap again and let it work on the problem.
2989	*/
2990	/** @todo move the above stuff to a section in the PGM documentation. */
2991	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2992	if ( !PdeSrc.b.u1Dirty
2993	&& PdeSrc.b.u1Write)
2994	{
2995	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2996	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2997	PdeDst.b.u1Write = 0;
2998	}
2999	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3000	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3001
3002	/*
3003	* Fill the shadow page table.
3004	*/
3005	/* Get address and flags from the source PDE. */
3006	SHWPTE PteDstBase;
3007	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3008
3009	/* Loop thru the entries in the shadow PT. */
3010	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3011	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3012	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
3013	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3014	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3015	unsigned iPTDst = 0;
3016	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3017	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3018	{
3019	if (pRam && GCPhys >= pRam->GCPhys)
3020	{
3021	# ifndef PGM_WITH_A20
3022	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3023	# endif
3024	do
3025	{
3026	/* Make shadow PTE. */
3027	# ifdef PGM_WITH_A20
3028	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3029	# else
3030	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3031	# endif
3032	SHWPTE PteDst;
3033
3034	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3035	/* Try to make the page writable if necessary. */
3036	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3037	&& ( PGM_PAGE_IS_ZERO(pPage)
3038	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3039	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3040	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3041	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3042	# endif
3043	# ifdef VBOX_WITH_PAGE_SHARING
3044	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3045	# endif
3046	&& !PGM_PAGE_IS_BALLOONED(pPage))
3047	)
3048	)
3049	{
3050	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3051	AssertRCReturn(rc, rc);
3052	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3053	break;
3054	}
3055	# endif
3056
3057	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3058	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3059	else if (PGM_PAGE_IS_BALLOONED(pPage))
3060	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3061	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3062	/*
3063	* Assuming kernel code will be marked as supervisor and not as user level and executed
3064	* using a conforming code selector. Don't check for readonly, as that implies the whole
3065	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3066	*/
3067	else if ( !PdeSrc.n.u1User
3068	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3069	SHW_PTE_SET(PteDst, 0);
3070	# endif
3071	else
3072	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3073
3074	/* Only map writable pages writable. */
3075	if ( SHW_PTE_IS_P_RW(PteDst)
3076	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3077	{
3078	/* Still applies to shared pages. */
3079	Assert(!PGM_PAGE_IS_ZERO(pPage));
3080	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3081	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3082	}
3083
3084	if (SHW_PTE_IS_P(PteDst))
3085	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3086
3087	/* commit it (not atomic, new table) */
3088	pPTDst->a[iPTDst] = PteDst;
3089	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3090	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3091	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3092
3093	/* advance */
3094	GCPhys += PAGE_SIZE;
3095	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3096	# ifndef PGM_WITH_A20
3097	iHCPage++;
3098	# endif
3099	iPTDst++;
3100	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3101	&& GCPhys <= pRam->GCPhysLast);
3102
3103	/* Advance ram range list. */
3104	while (pRam && GCPhys > pRam->GCPhysLast)
3105	pRam = pRam->CTX_SUFF(pNext);
3106	}
3107	else if (pRam)
3108	{
3109	Log(("Invalid pages at %RGp\n", GCPhys));
3110	do
3111	{
3112	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3113	GCPhys += PAGE_SIZE;
3114	iPTDst++;
3115	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3116	&& GCPhys < pRam->GCPhys);
3117	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3118	}
3119	else
3120	{
3121	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3122	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3123	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3124	}
3125	} /* while more PTEs */
3126	} /* 4KB / 4MB */
3127	}
3128	else
3129	AssertRelease(!PdeDst.n.u1Present);
3130
3131	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3132	if (RT_FAILURE(rc))
3133	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3134	return rc;
3135
3136	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3137	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3138	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3139	&& !defined(IN_RC)
3140	NOREF(iPDSrc); NOREF(pPDSrc);
3141
3142	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3143
3144	/*
3145	* Validate input a little bit.
3146	*/
3147	int rc = VINF_SUCCESS;
3148	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3149	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3150	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3151
3152	/* Fetch the pgm pool shadow descriptor. */
3153	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3154	Assert(pShwPde);
3155
3156	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3157	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3158	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3159	PX86PDPAE pPDDst;
3160	PSHWPDE pPdeDst;
3161
3162	/* Fetch the pgm pool shadow descriptor. */
3163	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3164	AssertRCSuccessReturn(rc, rc);
3165	Assert(pShwPde);
3166
3167	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3168	pPdeDst = &pPDDst->a[iPDDst];
3169
3170	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3171	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3172	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3173	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3174	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3175	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3176	AssertRCSuccessReturn(rc, rc);
3177	Assert(pPDDst);
3178	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3179
3180	/* Fetch the pgm pool shadow descriptor. */
3181	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3182	Assert(pShwPde);
3183
3184	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3185	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3186	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3187	PEPTPD pPDDst;
3188	PEPTPDPT pPdptDst;
3189
3190	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3191	if (rc != VINF_SUCCESS)
3192	{
3193	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3194	AssertRC(rc);
3195	return rc;
3196	}
3197	Assert(pPDDst);
3198	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3199
3200	/* Fetch the pgm pool shadow descriptor. */
3201	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3202	Assert(pShwPde);
3203	# endif
3204	SHWPDE PdeDst = *pPdeDst;
3205
3206	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3207	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3208
3209	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3210	if (BTH_IS_NP_ACTIVE(pVM))
3211	{
3212	/* Check if we allocated a big page before for this 2 MB range. */
3213	PPGMPAGE pPage;
3214	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3215	if (RT_SUCCESS(rc))
3216	{
3217	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3218	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3219	{
3220	if (PGM_A20_IS_ENABLED(pVCpu))
3221	{
3222	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3223	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3224	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3225	}
3226	else
3227	{
3228	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3229	pVM->pgm.s.cLargePagesDisabled++;
3230	}
3231	}
3232	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3233	&& PGM_A20_IS_ENABLED(pVCpu))
3234	{
3235	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3236	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3237	if (RT_SUCCESS(rc))
3238	{
3239	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3240	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3241	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3242	}
3243	}
3244	else if ( PGMIsUsingLargePages(pVM)
3245	&& PGM_A20_IS_ENABLED(pVCpu))
3246	{
3247	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3248	if (RT_SUCCESS(rc))
3249	{
3250	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3251	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3252	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3253	}
3254	else
3255	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3256	}
3257
3258	if (HCPhys != NIL_RTHCPHYS)
3259	{
3260	PdeDst.u &= X86_PDE_AVL_MASK;
3261	PdeDst.u \|= HCPhys;
3262	PdeDst.n.u1Present = 1;
3263	PdeDst.n.u1Write = 1;
3264	PdeDst.b.u1Size = 1;
3265	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3266	PdeDst.n.u1Execute = 1;
3267	PdeDst.b.u1IgnorePAT = 1;
3268	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3269	# else
3270	PdeDst.n.u1User = 1;
3271	# endif
3272	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3273
3274	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3275	/* Add a reference to the first page only. */
3276	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3277
3278	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3279	return VINF_SUCCESS;
3280	}
3281	}
3282	}
3283	# endif /* HC_ARCH_BITS == 64 */
3284
3285	/*
3286	* Allocate & map the page table.
3287	*/
3288	PSHWPT pPTDst;
3289	PPGMPOOLPAGE pShwPage;
3290	RTGCPHYS GCPhys;
3291
3292	/* Virtual address = physical address */
3293	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3294	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3295	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3296	&pShwPage);
3297	if ( rc == VINF_SUCCESS
3298	\|\| rc == VINF_PGM_CACHED_PAGE)
3299	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3300	else
3301	{
3302	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3303	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3304	}
3305
3306	if (rc == VINF_SUCCESS)
3307	{
3308	/* New page table; fully set it up. */
3309	Assert(pPTDst);
3310
3311	/* Mask away the page offset. */
3312	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3313
3314	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3315	{
3316	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3317	\| (iPTDst << PAGE_SHIFT));
3318
3319	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3320	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3321	GCPtrCurPage,
3322	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3323	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3324
3325	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3326	break;
3327	}
3328	}
3329	else
3330	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3331
3332	/* Save the new PDE. */
3333	PdeDst.u &= X86_PDE_AVL_MASK;
3334	PdeDst.u \|= pShwPage->Core.Key;
3335	PdeDst.n.u1Present = 1;
3336	PdeDst.n.u1Write = 1;
3337	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3338	PdeDst.n.u1Execute = 1;
3339	# else
3340	PdeDst.n.u1User = 1;
3341	PdeDst.n.u1Accessed = 1;
3342	# endif
3343	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3344
3345	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3346	if (RT_FAILURE(rc))
3347	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3348	return rc;
3349
3350	#else
3351	NOREF(iPDSrc); NOREF(pPDSrc);
3352	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3353	return VERR_PGM_NOT_USED_IN_MODE;
3354	#endif
3355	}
3356
3357
3358
3359	/**
3360	* Prefetch a page/set of pages.
3361	*
3362	* Typically used to sync commonly used pages before entering raw mode
3363	* after a CR3 reload.
3364	*
3365	* @returns VBox status code.
3366	* @param pVCpu The cross context virtual CPU structure.
3367	* @param GCPtrPage Page to invalidate.
3368	*/
3369	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3370	{
3371	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3372	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3373	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3374	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3375	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3376	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3377	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3378
3379	/*
3380	* Check that all Guest levels thru the PDE are present, getting the
3381	* PD and PDE in the processes.
3382	*/
3383	int rc = VINF_SUCCESS;
3384	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3385	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3386	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3387	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3388	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3389	unsigned iPDSrc;
3390	X86PDPE PdpeSrc;
3391	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3392	if (!pPDSrc)
3393	return VINF_SUCCESS; /* not present */
3394	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3395	unsigned iPDSrc;
3396	PX86PML4E pPml4eSrc;
3397	X86PDPE PdpeSrc;
3398	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3399	if (!pPDSrc)
3400	return VINF_SUCCESS; /* not present */
3401	# endif
3402	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3403	# else
3404	PGSTPD pPDSrc = NULL;
3405	const unsigned iPDSrc = 0;
3406	GSTPDE PdeSrc;
3407
3408	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3409	PdeSrc.n.u1Present = 1;
3410	PdeSrc.n.u1Write = 1;
3411	PdeSrc.n.u1Accessed = 1;
3412	PdeSrc.n.u1User = 1;
3413	# endif
3414
3415	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3416	{
3417	PVM pVM = pVCpu->CTX_SUFF(pVM);
3418	pgmLock(pVM);
3419
3420	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3421	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3422	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3423	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3424	PX86PDPAE pPDDst;
3425	X86PDEPAE PdeDst;
3426	# if PGM_GST_TYPE != PGM_TYPE_PAE
3427	X86PDPE PdpeSrc;
3428
3429	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3430	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3431	# endif
3432	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3433	if (rc != VINF_SUCCESS)
3434	{
3435	pgmUnlock(pVM);
3436	AssertRC(rc);
3437	return rc;
3438	}
3439	Assert(pPDDst);
3440	PdeDst = pPDDst->a[iPDDst];
3441
3442	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3443	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3444	PX86PDPAE pPDDst;
3445	X86PDEPAE PdeDst;
3446
3447	# if PGM_GST_TYPE == PGM_TYPE_PROT
3448	/* AMD-V nested paging */
3449	X86PML4E Pml4eSrc;
3450	X86PDPE PdpeSrc;
3451	PX86PML4E pPml4eSrc = &Pml4eSrc;
3452
3453	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3454	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3455	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3456	# endif
3457
3458	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3459	if (rc != VINF_SUCCESS)
3460	{
3461	pgmUnlock(pVM);
3462	AssertRC(rc);
3463	return rc;
3464	}
3465	Assert(pPDDst);
3466	PdeDst = pPDDst->a[iPDDst];
3467	# endif
3468	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3469	{
3470	if (!PdeDst.n.u1Present)
3471	{
3472	/** @todo r=bird: This guy will set the A bit on the PDE,
3473	* probably harmless. */
3474	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3475	}
3476	else
3477	{
3478	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3479	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3480	* makes no sense to prefetch more than one page.
3481	*/
3482	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3483	if (RT_SUCCESS(rc))
3484	rc = VINF_SUCCESS;
3485	}
3486	}
3487	pgmUnlock(pVM);
3488	}
3489	return rc;
3490
3491	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3492	NOREF(pVCpu); NOREF(GCPtrPage);
3493	return VINF_SUCCESS; /* ignore */
3494	#else
3495	AssertCompile(0);
3496	#endif
3497	}
3498
3499
3500
3501
3502	/**
3503	* Syncs a page during a PGMVerifyAccess() call.
3504	*
3505	* @returns VBox status code (informational included).
3506	* @param pVCpu The cross context virtual CPU structure.
3507	* @param GCPtrPage The address of the page to sync.
3508	* @param fPage The effective guest page flags.
3509	* @param uErr The trap error code.
3510	* @remarks This will normally never be called on invalid guest page
3511	* translation entries.
3512	*/
3513	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3514	{
3515	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3516
3517	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3518	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3519
3520	Assert(!pVM->pgm.s.fNestedPaging);
3521	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3522	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3523	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3524	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3525	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3526	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3527	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3528
3529	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3530	if (!(fPage & X86_PTE_US))
3531	{
3532	/*
3533	* Mark this page as safe.
3534	*/
3535	/** @todo not correct for pages that contain both code and data!! */
3536	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3537	CSAMMarkPage(pVM, GCPtrPage, true);
3538	}
3539	# endif
3540
3541	/*
3542	* Get guest PD and index.
3543	*/
3544	/** @todo Performance: We've done all this a jiffy ago in the
3545	* PGMGstGetPage call. */
3546	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3547	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3548	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3549	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3550
3551	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3552	unsigned iPDSrc = 0;
3553	X86PDPE PdpeSrc;
3554	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3555	if (RT_UNLIKELY(!pPDSrc))
3556	{
3557	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3558	return VINF_EM_RAW_GUEST_TRAP;
3559	}
3560
3561	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3562	unsigned iPDSrc = 0; /* shut up gcc */
3563	PX86PML4E pPml4eSrc = NULL; /* ditto */
3564	X86PDPE PdpeSrc;
3565	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3566	if (RT_UNLIKELY(!pPDSrc))
3567	{
3568	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3569	return VINF_EM_RAW_GUEST_TRAP;
3570	}
3571	# endif
3572
3573	# else /* !PGM_WITH_PAGING */
3574	PGSTPD pPDSrc = NULL;
3575	const unsigned iPDSrc = 0;
3576	# endif /* !PGM_WITH_PAGING */
3577	int rc = VINF_SUCCESS;
3578
3579	pgmLock(pVM);
3580
3581	/*
3582	* First check if the shadow pd is present.
3583	*/
3584	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3585	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3586
3587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3588	PX86PDEPAE pPdeDst;
3589	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3590	PX86PDPAE pPDDst;
3591	# if PGM_GST_TYPE != PGM_TYPE_PAE
3592	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3593	X86PDPE PdpeSrc;
3594	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3595	# endif
3596	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3597	if (rc != VINF_SUCCESS)
3598	{
3599	pgmUnlock(pVM);
3600	AssertRC(rc);
3601	return rc;
3602	}
3603	Assert(pPDDst);
3604	pPdeDst = &pPDDst->a[iPDDst];
3605
3606	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3607	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3608	PX86PDPAE pPDDst;
3609	PX86PDEPAE pPdeDst;
3610
3611	# if PGM_GST_TYPE == PGM_TYPE_PROT
3612	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3613	X86PML4E Pml4eSrc;
3614	X86PDPE PdpeSrc;
3615	PX86PML4E pPml4eSrc = &Pml4eSrc;
3616	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3617	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3618	# endif
3619
3620	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3621	if (rc != VINF_SUCCESS)
3622	{
3623	pgmUnlock(pVM);
3624	AssertRC(rc);
3625	return rc;
3626	}
3627	Assert(pPDDst);
3628	pPdeDst = &pPDDst->a[iPDDst];
3629	# endif
3630
3631	if (!pPdeDst->n.u1Present)
3632	{
3633	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3634	if (rc != VINF_SUCCESS)
3635	{
3636	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3637	pgmUnlock(pVM);
3638	AssertRC(rc);
3639	return rc;
3640	}
3641	}
3642
3643	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3644	/* Check for dirty bit fault */
3645	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3646	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3647	Log(("PGMVerifyAccess: success (dirty)\n"));
3648	else
3649	# endif
3650	{
3651	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3652	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3653	# else
3654	GSTPDE PdeSrc;
3655	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3656	PdeSrc.n.u1Present = 1;
3657	PdeSrc.n.u1Write = 1;
3658	PdeSrc.n.u1Accessed = 1;
3659	PdeSrc.n.u1User = 1;
3660	# endif
3661
3662	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3663	if (uErr & X86_TRAP_PF_US)
3664	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3665	else /* supervisor */
3666	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3667
3668	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3669	if (RT_SUCCESS(rc))
3670	{
3671	/* Page was successfully synced */
3672	Log2(("PGMVerifyAccess: success (sync)\n"));
3673	rc = VINF_SUCCESS;
3674	}
3675	else
3676	{
3677	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3678	rc = VINF_EM_RAW_GUEST_TRAP;
3679	}
3680	}
3681	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3682	pgmUnlock(pVM);
3683	return rc;
3684
3685	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3686
3687	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3688	return VERR_PGM_NOT_USED_IN_MODE;
3689	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3690	}
3691
3692
3693	/**
3694	* Syncs the paging hierarchy starting at CR3.
3695	*
3696	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
3697	* informational status codes.
3698	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
3699	* the VMM into guest context.
3700	* @param pVCpu The cross context virtual CPU structure.
3701	* @param cr0 Guest context CR0 register.
3702	* @param cr3 Guest context CR3 register. Not subjected to the A20
3703	* mask.
3704	* @param cr4 Guest context CR4 register.
3705	* @param fGlobal Including global page directories or not
3706	*/
3707	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3708	{
3709	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3710	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3711
3712	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3713
3714	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3715
3716	pgmLock(pVM);
3717
3718	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3719	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3720	if (pPool->cDirtyPages)
3721	pgmPoolResetDirtyPages(pVM);
3722	# endif
3723
3724	/*
3725	* Update page access handlers.
3726	* The virtual are always flushed, while the physical are only on demand.
3727	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3728	* have to look into that later because it will have a bad influence on the performance.
3729	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3730	* bird: Yes, but that won't work for aliases.
3731	*/
3732	/** @todo this MUST go away. See @bugref{1557}. */
3733	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3734	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3735	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3736	pgmUnlock(pVM);
3737	#endif /* !NESTED && !EPT */
3738
3739	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3740	/*
3741	* Nested / EPT - almost no work.
3742	*/
3743	Assert(!pgmMapAreMappingsEnabled(pVM));
3744	return VINF_SUCCESS;
3745
3746	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3747	/*
3748	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3749	* out the shadow parts when the guest modifies its tables.
3750	*/
3751	Assert(!pgmMapAreMappingsEnabled(pVM));
3752	return VINF_SUCCESS;
3753
3754	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3755
3756	# ifndef PGM_WITHOUT_MAPPINGS
3757	/*
3758	* Check for and resolve conflicts with our guest mappings if they
3759	* are enabled and not fixed.
3760	*/
3761	if (pgmMapAreMappingsFloating(pVM))
3762	{
3763	int rc = pgmMapResolveConflicts(pVM);
3764	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3765	if (rc == VINF_SUCCESS)
3766	{ /* likely */ }
3767	else if (rc == VINF_PGM_SYNC_CR3)
3768	{
3769	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3770	return VINF_PGM_SYNC_CR3;
3771	}
3772	else if (RT_FAILURE(rc))
3773	return rc;
3774	else
3775	AssertMsgFailed(("%Rrc\n", rc));
3776	}
3777	# else
3778	Assert(!pgmMapAreMappingsEnabled(pVM));
3779	# endif
3780	return VINF_SUCCESS;
3781	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3782	}
3783
3784
3785
3786
3787	#ifdef VBOX_STRICT
3788	# ifdef IN_RC
3789	# undef AssertMsgFailed
3790	# define AssertMsgFailed Log
3791	# endif
3792
3793	/**
3794	* Checks that the shadow page table is in sync with the guest one.
3795	*
3796	* @returns The number of errors.
3797	* @param pVCpu The cross context virtual CPU structure.
3798	* @param cr3 Guest context CR3 register.
3799	* @param cr4 Guest context CR4 register.
3800	* @param GCPtr Where to start. Defaults to 0.
3801	* @param cb How much to check. Defaults to everything.
3802	*/
3803	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3804	{
3805	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3806	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3807	return 0;
3808	#else
3809	unsigned cErrors = 0;
3810	PVM pVM = pVCpu->CTX_SUFF(pVM);
3811	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3812
3813	# if PGM_GST_TYPE == PGM_TYPE_PAE
3814	/** @todo currently broken; crashes below somewhere */
3815	AssertFailed();
3816	# endif
3817
3818	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3819	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3820	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3821
3822	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3823	PPGMCPU pPGM = &pVCpu->pgm.s;
3824	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3825	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3826	# ifndef IN_RING0
3827	RTHCPHYS HCPhys; /* general usage. */
3828	# endif
3829	int rc;
3830
3831	/*
3832	* Check that the Guest CR3 and all its mappings are correct.
3833	*/
3834	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3835	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3836	false);
3837	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3838	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3839	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3840	# else
3841	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3842	# endif
3843	AssertRCReturn(rc, 1);
3844	HCPhys = NIL_RTHCPHYS;
3845	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3846	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3847	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3848	pgmGstGet32bitPDPtr(pVCpu);
3849	RTGCPHYS GCPhys;
3850	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3851	AssertRCReturn(rc, 1);
3852	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3853	# endif
3854	# endif /* !IN_RING0 */
3855
3856	/*
3857	* Get and check the Shadow CR3.
3858	*/
3859	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3860	unsigned cPDEs = X86_PG_ENTRIES;
3861	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3862	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3863	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3864	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3865	# else
3866	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3867	# endif
3868	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3869	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3870	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3871	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3872	# endif
3873	if (cb != ~(RTGCPTR)0)
3874	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3875
3876	/** @todo call the other two PGMAssert() functions. /
3877
3878	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3879	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3880
3881	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3882	{
3883	PPGMPOOLPAGE pShwPdpt = NULL;
3884	PX86PML4E pPml4eSrc;
3885	PX86PML4E pPml4eDst;
3886	RTGCPHYS GCPhysPdptSrc;
3887
3888	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3889	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3890
3891	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3892	if (!pPml4eDst->n.u1Present)
3893	{
3894	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3895	continue;
3896	}
3897
3898	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3899	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3900
3901	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3902	{
3903	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3904	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3905	cErrors++;
3906	continue;
3907	}
3908
3909	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3910	{
3911	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3912	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3913	cErrors++;
3914	continue;
3915	}
3916
3917	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3918	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3919	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3920	{
3921	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3922	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3923	cErrors++;
3924	continue;
3925	}
3926	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3927	{
3928	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3929
3930	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3931	/*
3932	* Check the PDPTEs too.
3933	*/
3934	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3935
3936	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3937	{
3938	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3939	PPGMPOOLPAGE pShwPde = NULL;
3940	PX86PDPE pPdpeDst;
3941	RTGCPHYS GCPhysPdeSrc;
3942	X86PDPE PdpeSrc;
3943	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3944	# if PGM_GST_TYPE == PGM_TYPE_PAE
3945	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3946	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3947	# else
3948	PX86PML4E pPml4eSrcIgn;
3949	PX86PDPT pPdptDst;
3950	PX86PDPAE pPDDst;
3951	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3952
3953	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3954	if (rc != VINF_SUCCESS)
3955	{
3956	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3957	GCPtr += 512 * _2M;
3958	continue; /* next PDPTE */
3959	}
3960	Assert(pPDDst);
3961	# endif
3962	Assert(iPDSrc == 0);
3963
3964	pPdpeDst = &pPdptDst->a[iPdpt];
3965
3966	if (!pPdpeDst->n.u1Present)
3967	{
3968	GCPtr += 512 * _2M;
3969	continue; /* next PDPTE */
3970	}
3971
3972	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3973	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3974
3975	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3976	{
3977	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3978	GCPtr += 512 * _2M;
3979	cErrors++;
3980	continue;
3981	}
3982
3983	if (GCPhysPdeSrc != pShwPde->GCPhys)
3984	{
3985	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3986	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3987	# else
3988	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3989	# endif
3990	GCPtr += 512 * _2M;
3991	cErrors++;
3992	continue;
3993	}
3994
3995	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3996	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3997	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3998	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
3999	{
4000	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4001	GCPtr += 512 * _2M;
4002	cErrors++;
4003	continue;
4004	}
4005	# endif
4006
4007	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4008	{
4009	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4010	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4011	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4012	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4013	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4014	# endif
4015	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4016	/*
4017	* Iterate the shadow page directory.
4018	*/
4019	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4020	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4021
4022	for (;
4023	iPDDst < cPDEs;
4024	iPDDst++, GCPtr += cIncrement)
4025	{
4026	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4027	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4028	# else
4029	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4030	# endif
4031	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4032	{
4033	Assert(pgmMapAreMappingsEnabled(pVM));
4034	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4035	{
4036	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4037	cErrors++;
4038	continue;
4039	}
4040	}
4041	else if ( (PdeDst.u & X86_PDE_P)
4042	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4043	)
4044	{
4045	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4046	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4047	if (!pPoolPage)
4048	{
4049	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4050	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4051	cErrors++;
4052	continue;
4053	}
4054	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4055
4056	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4057	{
4058	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4059	GCPtr, (uint64_t)PdeDst.u));
4060	cErrors++;
4061	}
4062
4063	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4064	{
4065	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4066	GCPtr, (uint64_t)PdeDst.u));
4067	cErrors++;
4068	}
4069
4070	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4071	if (!PdeSrc.n.u1Present)
4072	{
4073	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4074	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4075	cErrors++;
4076	continue;
4077	}
4078
4079	if ( !PdeSrc.b.u1Size
4080	\|\| !fBigPagesSupported)
4081	{
4082	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4083	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4084	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4085	# endif
4086	}
4087	else
4088	{
4089	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4090	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4091	{
4092	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4093	GCPtr, (uint64_t)PdeSrc.u));
4094	cErrors++;
4095	continue;
4096	}
4097	# endif
4098	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4099	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4100	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4101	# endif
4102	}
4103
4104	if ( pPoolPage->enmKind
4105	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4106	{
4107	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4108	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4109	cErrors++;
4110	}
4111
4112	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4113	if (!pPhysPage)
4114	{
4115	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4116	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4117	cErrors++;
4118	continue;
4119	}
4120
4121	if (GCPhysGst != pPoolPage->GCPhys)
4122	{
4123	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4124	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4125	cErrors++;
4126	continue;
4127	}
4128
4129	if ( !PdeSrc.b.u1Size
4130	\|\| !fBigPagesSupported)
4131	{
4132	/*
4133	* Page Table.
4134	*/
4135	const GSTPT *pPTSrc;
4136	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4137	&pPTSrc);
4138	if (RT_FAILURE(rc))
4139	{
4140	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4141	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4142	cErrors++;
4143	continue;
4144	}
4145	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4146	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4147	{
4148	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4149	// (This problem will go away when/if we shadow multiple CR3s.)
4150	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4151	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4152	cErrors++;
4153	continue;
4154	}
4155	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4156	{
4157	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4158	GCPtr, (uint64_t)PdeDst.u));
4159	cErrors++;
4160	continue;
4161	}
4162
4163	/* iterate the page table. */
4164	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4165	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4166	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4167	# else
4168	const unsigned offPTSrc = 0;
4169	# endif
4170	for (unsigned iPT = 0, off = 0;
4171	iPT < RT_ELEMENTS(pPTDst->a);
4172	iPT++, off += PAGE_SIZE)
4173	{
4174	const SHWPTE PteDst = pPTDst->a[iPT];
4175
4176	/* skip not-present and dirty tracked entries. */
4177	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4178	continue;
4179	Assert(SHW_PTE_IS_P(PteDst));
4180
4181	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4182	if (!PteSrc.n.u1Present)
4183	{
4184	# ifdef IN_RING3
4185	PGMAssertHandlerAndFlagsInSync(pVM);
4186	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4187	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4188	0, 0, UINT64_MAX, 99, NULL);
4189	# endif
4190	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4191	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4192	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4193	cErrors++;
4194	continue;
4195	}
4196
4197	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4198	# if 1 /** @todo sync accessed bit properly... */
4199	fIgnoreFlags \|= X86_PTE_A;
4200	# endif
4201
4202	/* match the physical addresses */
4203	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4204	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4205
4206	# ifdef IN_RING3
4207	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4208	if (RT_FAILURE(rc))
4209	{
4210	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4211	{
4212	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4213	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4214	cErrors++;
4215	continue;
4216	}
4217	}
4218	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4219	{
4220	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4221	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4222	cErrors++;
4223	continue;
4224	}
4225	# endif
4226
4227	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4228	if (!pPhysPage)
4229	{
4230	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4231	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4232	{
4233	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4234	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4235	cErrors++;
4236	continue;
4237	}
4238	# endif
4239	if (SHW_PTE_IS_RW(PteDst))
4240	{
4241	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4242	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4243	cErrors++;
4244	}
4245	fIgnoreFlags \|= X86_PTE_RW;
4246	}
4247	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4248	{
4249	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4250	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4251	cErrors++;
4252	continue;
4253	}
4254
4255	/* flags */
4256	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4257	{
4258	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4259	{
4260	if (SHW_PTE_IS_RW(PteDst))
4261	{
4262	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4263	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4264	cErrors++;
4265	continue;
4266	}
4267	fIgnoreFlags \|= X86_PTE_RW;
4268	}
4269	else
4270	{
4271	if ( SHW_PTE_IS_P(PteDst)
4272	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4273	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4274	# endif
4275	)
4276	{
4277	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4278	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4279	cErrors++;
4280	continue;
4281	}
4282	fIgnoreFlags \|= X86_PTE_P;
4283	}
4284	}
4285	else
4286	{
4287	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4288	{
4289	if (SHW_PTE_IS_RW(PteDst))
4290	{
4291	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4292	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4293	cErrors++;
4294	continue;
4295	}
4296	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4297	{
4298	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4299	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4300	cErrors++;
4301	continue;
4302	}
4303	if (SHW_PTE_IS_D(PteDst))
4304	{
4305	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4306	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4307	cErrors++;
4308	}
4309	# if 0 /** @todo sync access bit properly... */
4310	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4311	{
4312	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4313	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4314	cErrors++;
4315	}
4316	fIgnoreFlags \|= X86_PTE_RW;
4317	# else
4318	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4319	# endif
4320	}
4321	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4322	{
4323	/* access bit emulation (not implemented). */
4324	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4325	{
4326	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4327	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4328	cErrors++;
4329	continue;
4330	}
4331	if (!SHW_PTE_IS_A(PteDst))
4332	{
4333	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4334	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4335	cErrors++;
4336	}
4337	fIgnoreFlags \|= X86_PTE_P;
4338	}
4339	# ifdef DEBUG_sandervl
4340	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4341	# endif
4342	}
4343
4344	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4345	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4346	)
4347	{
4348	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4349	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4350	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4351	cErrors++;
4352	continue;
4353	}
4354	} /* foreach PTE */
4355	}
4356	else
4357	{
4358	/*
4359	* Big Page.
4360	*/
4361	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4362	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4363	{
4364	if (PdeDst.n.u1Write)
4365	{
4366	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4367	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4368	cErrors++;
4369	continue;
4370	}
4371	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4372	{
4373	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4374	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4375	cErrors++;
4376	continue;
4377	}
4378	# if 0 /** @todo sync access bit properly... */
4379	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4380	{
4381	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4382	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4383	cErrors++;
4384	}
4385	fIgnoreFlags \|= X86_PTE_RW;
4386	# else
4387	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4388	# endif
4389	}
4390	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4391	{
4392	/* access bit emulation (not implemented). */
4393	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4394	{
4395	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4396	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4397	cErrors++;
4398	continue;
4399	}
4400	if (!PdeDst.n.u1Accessed)
4401	{
4402	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4403	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4404	cErrors++;
4405	}
4406	fIgnoreFlags \|= X86_PTE_P;
4407	}
4408
4409	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4410	{
4411	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4412	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4413	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4414	cErrors++;
4415	}
4416
4417	/* iterate the page table. */
4418	for (unsigned iPT = 0, off = 0;
4419	iPT < RT_ELEMENTS(pPTDst->a);
4420	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4421	{
4422	const SHWPTE PteDst = pPTDst->a[iPT];
4423
4424	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4425	{
4426	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4427	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4428	cErrors++;
4429	}
4430
4431	/* skip not-present entries. */
4432	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4433	continue;
4434
4435	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4436
4437	/* match the physical addresses */
4438	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4439
4440	# ifdef IN_RING3
4441	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4442	if (RT_FAILURE(rc))
4443	{
4444	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4445	{
4446	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4447	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4448	cErrors++;
4449	}
4450	}
4451	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4452	{
4453	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4454	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4455	cErrors++;
4456	continue;
4457	}
4458	# endif
4459	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4460	if (!pPhysPage)
4461	{
4462	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4463	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4464	{
4465	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4466	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4467	cErrors++;
4468	continue;
4469	}
4470	# endif
4471	if (SHW_PTE_IS_RW(PteDst))
4472	{
4473	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4474	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4475	cErrors++;
4476	}
4477	fIgnoreFlags \|= X86_PTE_RW;
4478	}
4479	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4480	{
4481	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4482	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4483	cErrors++;
4484	continue;
4485	}
4486
4487	/* flags */
4488	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4489	{
4490	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4491	{
4492	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4493	{
4494	if (SHW_PTE_IS_RW(PteDst))
4495	{
4496	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4497	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4498	cErrors++;
4499	continue;
4500	}
4501	fIgnoreFlags \|= X86_PTE_RW;
4502	}
4503	}
4504	else
4505	{
4506	if ( SHW_PTE_IS_P(PteDst)
4507	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4508	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4509	# endif
4510	)
4511	{
4512	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4513	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4514	cErrors++;
4515	continue;
4516	}
4517	fIgnoreFlags \|= X86_PTE_P;
4518	}
4519	}
4520
4521	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4522	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4523	)
4524	{
4525	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4526	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4527	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4528	cErrors++;
4529	continue;
4530	}
4531	} /* for each PTE */
4532	}
4533	}
4534	/* not present */
4535
4536	} /* for each PDE */
4537
4538	} /* for each PDPTE */
4539
4540	} /* for each PML4E */
4541
4542	# ifdef DEBUG
4543	if (cErrors)
4544	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4545	# endif
4546	# endif /* GST is in {32BIT, PAE, AMD64} */
4547	return cErrors;
4548	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4549	}
4550	#endif /* VBOX_STRICT */
4551
4552
4553	/**
4554	* Sets up the CR3 for shadow paging
4555	*
4556	* @returns Strict VBox status code.
4557	* @retval VINF_SUCCESS.
4558	*
4559	* @param pVCpu The cross context virtual CPU structure.
4560	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4561	* mask already applied.)
4562	*/
4563	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4564	{
4565	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4566
4567	/* Update guest paging info. */
4568	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4569	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4570	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4571
4572	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4573	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4574
4575	/*
4576	* Map the page CR3 points at.
4577	*/
4578	RTHCPTR HCPtrGuestCR3;
4579	RTHCPHYS HCPhysGuestCR3;
4580	pgmLock(pVM);
4581	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4582	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4583	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4584	/** @todo this needs some reworking wrt. locking? */
4585	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4586	HCPtrGuestCR3 = NIL_RTHCPTR;
4587	int rc = VINF_SUCCESS;
4588	# else
4589	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4590	# endif
4591	pgmUnlock(pVM);
4592	if (RT_SUCCESS(rc))
4593	{
4594	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4595	if (RT_SUCCESS(rc))
4596	{
4597	# ifdef IN_RC
4598	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4599	# endif
4600	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4601	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4602	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4603	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4604	# endif
4605	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4606
4607	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4608	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4609	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4610	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4611	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4612	# endif
4613	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4614	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4615
4616	/*
4617	* Map the 4 PDs too.
4618	*/
4619	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4620	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4621	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4622	{
4623	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4624	if (pGuestPDPT->a[i].n.u1Present)
4625	{
4626	RTHCPTR HCPtr;
4627	RTHCPHYS HCPhys;
4628	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4629	pgmLock(pVM);
4630	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4631	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4632	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4633	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4634	HCPtr = NIL_RTHCPTR;
4635	int rc2 = VINF_SUCCESS;
4636	# else
4637	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4638	# endif
4639	pgmUnlock(pVM);
4640	if (RT_SUCCESS(rc2))
4641	{
4642	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4643	AssertRCReturn(rc, rc);
4644
4645	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4646	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4647	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4648	# endif
4649	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4650	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4651	# ifdef IN_RC
4652	PGM_INVL_PG(pVCpu, GCPtr);
4653	# endif
4654	continue;
4655	}
4656	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4657	}
4658
4659	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4660	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4661	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4662	# endif
4663	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4664	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4665	# ifdef IN_RC
4666	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4667	# endif
4668	}
4669
4670	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4671	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4672	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4673	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4674	# endif
4675	# endif
4676	}
4677	else
4678	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4679	}
4680	else
4681	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4682
4683	#else /* prot/real stub */
4684	int rc = VINF_SUCCESS;
4685	#endif
4686
4687	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4688	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4689	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4690	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4691	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4692	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4693
4694	Assert(!pVM->pgm.s.fNestedPaging);
4695	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4696
4697	/*
4698	* Update the shadow root page as well since that's not fixed.
4699	*/
4700	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4701	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4702	PPGMPOOLPAGE pNewShwPageCR3;
4703
4704	pgmLock(pVM);
4705
4706	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4707	if (pPool->cDirtyPages)
4708	pgmPoolResetDirtyPages(pVM);
4709	# endif
4710
4711	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4712	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4713	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4714	&pNewShwPageCR3);
4715	AssertFatalRC(rc);
4716	rc = VINF_SUCCESS;
4717
4718	# ifdef IN_RC
4719	/*
4720	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4721	* state will be inconsistent! Flush important things now while
4722	* we still can and then make sure there are no ring-3 calls.
4723	*/
4724	# ifdef VBOX_WITH_REM
4725	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4726	# endif
4727	VMMRZCallRing3Disable(pVCpu);
4728	# endif
4729
4730	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4731	# ifdef IN_RING0
4732	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4733	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4734	# elif defined(IN_RC)
4735	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4736	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4737	# else
4738	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4739	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4740	# endif
4741
4742	# ifndef PGM_WITHOUT_MAPPINGS
4743	/*
4744	* Apply all hypervisor mappings to the new CR3.
4745	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4746	* make sure we check for conflicts in the new CR3 root.
4747	*/
4748	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4749	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4750	# endif
4751	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4752	AssertRCReturn(rc, rc);
4753	# endif
4754
4755	/* Set the current hypervisor CR3. */
4756	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4757	SELMShadowCR3Changed(pVM, pVCpu);
4758
4759	# ifdef IN_RC
4760	/* NOTE: The state is consistent again. */
4761	VMMRZCallRing3Enable(pVCpu);
4762	# endif
4763
4764	/* Clean up the old CR3 root. */
4765	if ( pOldShwPageCR3
4766	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4767	{
4768	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4769	# ifndef PGM_WITHOUT_MAPPINGS
4770	/* Remove the hypervisor mappings from the shadow page table. */
4771	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4772	# endif
4773	/* Mark the page as unlocked; allow flushing again. */
4774	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4775
4776	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4777	}
4778	pgmUnlock(pVM);
4779	# else
4780	NOREF(GCPhysCR3);
4781	# endif
4782
4783	return rc;
4784	}
4785
4786	/**
4787	* Unmaps the shadow CR3.
4788	*
4789	* @returns VBox status, no specials.
4790	* @param pVCpu The cross context virtual CPU structure.
4791	*/
4792	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4793	{
4794	LogFlow(("UnmapCR3\n"));
4795
4796	int rc = VINF_SUCCESS;
4797	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4798
4799	/*
4800	* Update guest paging info.
4801	*/
4802	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4803	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4804	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4805	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4806	# endif
4807	pVCpu->pgm.s.pGst32BitPdRC = 0;
4808
4809	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4810	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4811	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4812	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4813	# endif
4814	pVCpu->pgm.s.pGstPaePdptRC = 0;
4815	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4816	{
4817	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4818	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4819	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4820	# endif
4821	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4822	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4823	}
4824
4825	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4826	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4827	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4828	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4829	# endif
4830
4831	#else /* prot/real mode stub */
4832	/* nothing to do */
4833	#endif
4834
4835	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4836	/*
4837	* Update shadow paging info.
4838	*/
4839	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4840	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4841	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4842
4843	# if PGM_GST_TYPE != PGM_TYPE_REAL
4844	Assert(!pVM->pgm.s.fNestedPaging);
4845	# endif
4846
4847	pgmLock(pVM);
4848
4849	# ifndef PGM_WITHOUT_MAPPINGS
4850	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4851	/* Remove the hypervisor mappings from the shadow page table. */
4852	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4853	# endif
4854
4855	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4856	{
4857	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4858
4859	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4860	if (pPool->cDirtyPages)
4861	pgmPoolResetDirtyPages(pVM);
4862	# endif
4863
4864	/* Mark the page as unlocked; allow flushing again. */
4865	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4866
4867	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4868	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4869	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4870	pVCpu->pgm.s.pShwPageCR3RC = 0;
4871	}
4872	pgmUnlock(pVM);
4873	# endif
4874	#endif /* !IN_RC*/
4875
4876	return rc;
4877	}

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 65029

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