PGMAllBth.h@ 65398

Last change on this file since 65398 was 65398, checked in by vboxsync, 8 years ago
PGMAllBth.h: Trap0eHandlerGuestFault: Fixed missing X86_TRAP_RSVD flag for invalid entries in paging structures.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 213.2 KB

Line
1	/* $Id: PGMAllBth.h 65398 2017-01-22 11:55:51Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2016 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if ( pGstWalk->Core.fRsvdError
124	\|\| pGstWalk->Core.fBadPhysAddr)
125	{
126	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
127	Assert(!pGstWalk->Core.fNotPresent);
128	}
129	else if (!pGstWalk->Core.fNotPresent)
130	uNewErr \|= X86_TRAP_PF_P;
131	TRPMSetErrorCode(pVCpu, uNewErr);
132
133	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
134	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
135	return VINF_EM_RAW_GUEST_TRAP;
136	}
137	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
138
139
140	/**
141	* Deal with a guest page fault.
142	*
143	* The caller has taken the PGM lock.
144	*
145	* @returns Strict VBox status code.
146	*
147	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
148	* @param uErr The error code.
149	* @param pRegFrame The register frame.
150	* @param pvFault The fault address.
151	* @param pPage The guest page at @a pvFault.
152	* @param pGstWalk The guest page table walk result.
153	* @param pfLockTaken PGM lock taken here or not (out). This is true
154	* when we're called.
155	*/
156	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
157	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
158	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
159	, PGSTPTWALK pGstWalk
160	# endif
161	)
162	{
163	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
164	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
165	#endif
166	PVM pVM = pVCpu->CTX_SUFF(pVM);
167	VBOXSTRICTRC rcStrict;
168
169	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
170	{
171	/*
172	* Physical page access handler.
173	*/
174	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
175	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
176	# else
177	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
178	# endif
179	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
180	if (pCur)
181	{
182	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
183
184	# ifdef PGM_SYNC_N_PAGES
185	/*
186	* If the region is write protected and we got a page not present fault, then sync
187	* the pages. If the fault was caused by a read, then restart the instruction.
188	* In case of write access continue to the GC write handler.
189	*
190	* ASSUMES that there is only one handler per page or that they have similar write properties.
191	*/
192	if ( !(uErr & X86_TRAP_PF_P)
193	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
194	{
195	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
196	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
197	# else
198	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
199	# endif
200	if ( RT_FAILURE(rcStrict)
201	\|\| !(uErr & X86_TRAP_PF_RW)
202	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
203	{
204	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
205	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
206	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
207	return rcStrict;
208	}
209	}
210	# endif
211	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
212	/*
213	* If the access was not thru a #PF(RSVD\|...) resync the page.
214	*/
215	if ( !(uErr & X86_TRAP_PF_RSVD)
216	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
217	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
218	&& pGstWalk->Core.fEffectiveRW
219	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
220	# endif
221	)
222	{
223	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
224	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
225	# else
226	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
227	# endif
228	if ( RT_FAILURE(rcStrict)
229	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
230	{
231	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
232	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
233	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
234	return rcStrict;
235	}
236	}
237	# endif
238
239	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
240	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
241	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
242	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
243	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
245	else
246	{
247	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
248	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
249	}
250
251	if (pCurType->CTX_SUFF(pfnPfHandler))
252	{
253	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
254	void *pvUser = pCur->CTX_SUFF(pvUser);
255
256	STAM_PROFILE_START(&pCur->Stat, h);
257	if (pCur->hType != pPool->hAccessHandlerType)
258	{
259	pgmUnlock(pVM);
260	*pfLockTaken = false;
261	}
262
263	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
264
265	# ifdef VBOX_WITH_STATISTICS
266	pgmLock(pVM);
267	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
268	if (pCur)
269	STAM_PROFILE_STOP(&pCur->Stat, h);
270	pgmUnlock(pVM);
271	# endif
272	}
273	else
274	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
275
276	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
277	return rcStrict;
278	}
279	}
280	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
281	else
282	{
283	# ifdef PGM_SYNC_N_PAGES
284	/*
285	* If the region is write protected and we got a page not present fault, then sync
286	* the pages. If the fault was caused by a read, then restart the instruction.
287	* In case of write access continue to the GC write handler.
288	*/
289	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
290	&& !(uErr & X86_TRAP_PF_P))
291	{
292	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
293	if ( RT_FAILURE(rcStrict)
294	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
295	\|\| !(uErr & X86_TRAP_PF_RW))
296	{
297	AssertRC(rcStrict);
298	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
299	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
300	return rcStrict;
301	}
302	}
303	# endif
304	/*
305	* Ok, it's an virtual page access handler.
306	*
307	* Since it's faster to search by address, we'll do that first
308	* and then retry by GCPhys if that fails.
309	*/
310	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
311	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
312	* out of sync, because the page was changed without us noticing it (not-present -> present
313	* without invlpg or mov cr3, xxx).
314	*/
315	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
316	if (pCur)
317	{
318	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enumKind=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCurType->enmKind));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	void *pvUser = pCur->CTX_SUFF(pvUser);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart,
338	pvFault - GCPtrStart, pvUser);
339
340	# ifdef VBOX_WITH_STATISTICS
341	pgmLock(pVM);
342	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
343	if (pCur)
344	STAM_PROFILE_STOP(&pCur->Stat, h);
345	pgmUnlock(pVM);
346	# endif
347	# else
348	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
349	# endif
350	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
351	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
352	return rcStrict;
353	}
354	/* Unhandled part of a monitored page */
355	Log(("Unhandled part of monitored page %RGv\n", pvFault));
356	}
357	else
358	{
359	/* Check by physical address. */
360	unsigned iPage;
361	pCur = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &iPage);
362	if (pCur)
363	{
364	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
365	if ( uErr & X86_TRAP_PF_RW
366	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE )
367	{
368	Assert( (pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK)
369	== (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
370	# ifdef IN_RC
371	STAM_PROFILE_START(&pCur->Stat, h);
372	RTGCPTR GCPtrStart = pCur->Core.Key;
373	void *pvUser = pCur->CTX_SUFF(pvUser);
374	pgmUnlock(pVM);
375	*pfLockTaken = false;
376
377	RTGCPTR off = (iPage << PAGE_SHIFT)
378	+ (pvFault & PAGE_OFFSET_MASK)
379	- (GCPtrStart & PAGE_OFFSET_MASK);
380	Assert(off < pCur->cb);
381	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart, off, pvUser);
382
383	# ifdef VBOX_WITH_STATISTICS
384	pgmLock(pVM);
385	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
386	if (pCur)
387	STAM_PROFILE_STOP(&pCur->Stat, h);
388	pgmUnlock(pVM);
389	# endif
390	# else
391	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
392	# endif
393	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
394	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
395	return rcStrict;
396	}
397	}
398	}
399	}
400	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
401
402	/*
403	* There is a handled area of the page, but this fault doesn't belong to it.
404	* We must emulate the instruction.
405	*
406	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
407	* we first check if this was a page-not-present fault for a page with only
408	* write access handlers. Restart the instruction if it wasn't a write access.
409	*/
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
411
412	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
413	&& !(uErr & X86_TRAP_PF_P))
414	{
415	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
416	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
417	# else
418	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
419	# endif
420	if ( RT_FAILURE(rcStrict)
421	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
422	\|\| !(uErr & X86_TRAP_PF_RW))
423	{
424	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
426	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
427	return rcStrict;
428	}
429	}
430
431	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
432	* It's writing to an unhandled part of the LDT page several million times.
433	*/
434	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
435	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
436	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
437	return rcStrict;
438	} /* if any kind of handler */
439
440
441	/**
442	* \#PF Handler for raw-mode guest execution.
443	*
444	* @returns VBox status code (appropriate for trap handling and GC return).
445	*
446	* @param pVCpu The cross context virtual CPU structure.
447	* @param uErr The trap error code.
448	* @param pRegFrame Trap register frame.
449	* @param pvFault The fault address.
450	* @param pfLockTaken PGM lock taken here or not (out)
451	*/
452	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
453	{
454	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
455
456	*pfLockTaken = false;
457
458	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
459	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
460	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
461	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
462	int rc;
463
464	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
465	/*
466	* Walk the guest page translation tables and check if it's a guest fault.
467	*/
468	GSTPTWALK GstWalk;
469	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
470	if (RT_FAILURE_NP(rc))
471	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
472
473	/* assert some GstWalk sanity. */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
476	# endif
477	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
478	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
479	# endif
480	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
481	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
482	Assert(GstWalk.Core.fSucceeded);
483
484	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
485	{
486	if ( ( (uErr & X86_TRAP_PF_RW)
487	&& !GstWalk.Core.fEffectiveRW
488	&& ( (uErr & X86_TRAP_PF_US)
489	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
490	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
491	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
492	)
493	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
494	}
495
496	/*
497	* Set the accessed and dirty flags.
498	*/
499	# if PGM_GST_TYPE == PGM_TYPE_AMD64
500	GstWalk.Pml4e.u \|= X86_PML4E_A;
501	GstWalk.pPml4e->u \|= X86_PML4E_A;
502	GstWalk.Pdpe.u \|= X86_PDPE_A;
503	GstWalk.pPdpe->u \|= X86_PDPE_A;
504	# endif
505	if (GstWalk.Core.fBigPage)
506	{
507	Assert(GstWalk.Pde.b.u1Size);
508	if (uErr & X86_TRAP_PF_RW)
509	{
510	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
512	}
513	else
514	{
515	GstWalk.Pde.u \|= X86_PDE4M_A;
516	GstWalk.pPde->u \|= X86_PDE4M_A;
517	}
518	}
519	else
520	{
521	Assert(!GstWalk.Pde.b.u1Size);
522	GstWalk.Pde.u \|= X86_PDE_A;
523	GstWalk.pPde->u \|= X86_PDE_A;
524	if (uErr & X86_TRAP_PF_RW)
525	{
526	# ifdef VBOX_WITH_STATISTICS
527	if (!GstWalk.Pte.n.u1Dirty)
528	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
529	else
530	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
531	# endif
532	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
533	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
534	}
535	else
536	{
537	GstWalk.Pte.u \|= X86_PTE_A;
538	GstWalk.pPte->u \|= X86_PTE_A;
539	}
540	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
541	}
542	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
543	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
544	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
545	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
546	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	pgmLock(pVM);
551
552	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
553	/*
554	* If it is a reserved bit fault we know that it is an MMIO (access
555	* handler) related fault and can skip some 200 lines of code.
556	*/
557	if (uErr & X86_TRAP_PF_RSVD)
558	{
559	Assert(uErr & X86_TRAP_PF_P);
560	PPGMPAGE pPage;
561	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
562	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
563	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
564	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
565	pfLockTaken, &GstWalk));
566	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
567	# else
568	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
569	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
570	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
571	pfLockTaken));
572	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
573	# endif
574	AssertRC(rc);
575	PGM_INVL_PG(pVCpu, pvFault);
576	return rc; /* Restart with the corrected entry. */
577	}
578	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
579
580	/*
581	* Fetch the guest PDE, PDPE and PML4E.
582	*/
583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
584	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
585	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
588	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PAE
591	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
592	# else
593	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PX86PDPAE pPDDst;
600	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
602	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
603	# else
604	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
605	# endif
606	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
607
608	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
609	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
610	PEPTPD pPDDst;
611	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
612	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
613	# endif
614	Assert(pPDDst);
615
616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
617	/*
618	* Dirty page handling.
619	*
620	* If we successfully correct the write protection fault due to dirty bit
621	* tracking, then return immediately.
622	*/
623	if (uErr & X86_TRAP_PF_RW) /* write fault? */
624	{
625	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
626	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
628	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
629	{
630	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
631	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
632	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
633	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
634	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
635	return VINF_SUCCESS;
636	}
637	#ifdef DEBUG_bird
638	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
639	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
640	#endif
641	}
642
643	# if 0 /* rarely useful; leave for debugging. */
644	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
645	# endif
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647
648	/*
649	* A common case is the not-present error caused by lazy page table syncing.
650	*
651	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
652	* here so we can safely assume that the shadow PT is present when calling
653	* SyncPage later.
654	*
655	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
656	* of mapping conflict and defer to SyncCR3 in R3.
657	* (Again, we do NOT support access handlers for non-present guest pages.)
658	*
659	*/
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	Assert(GstWalk.Pde.n.u1Present);
662	# endif
663	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
664	&& !pPDDst->a[iPDDst].n.u1Present)
665	{
666	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
668	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
670	# else
671	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
672	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
673	# endif
674	if (RT_SUCCESS(rc))
675	return rc;
676	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
677	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
678	return VINF_PGM_SYNC_CR3;
679	}
680
681	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
682	/*
683	* Check if this address is within any of our mappings.
684	*
685	* This is very fast and it's gonna save us a bit of effort below and prevent
686	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
687	* (BTW, it's impossible to have physical access handlers in a mapping.)
688	*/
689	if (pgmMapAreMappingsEnabled(pVM))
690	{
691	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
692	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
693	{
694	if (pvFault < pMapping->GCPtr)
695	break;
696	if (pvFault - pMapping->GCPtr < pMapping->cb)
697	{
698	/*
699	* The first thing we check is if we've got an undetected conflict.
700	*/
701	if (pgmMapAreMappingsFloating(pVM))
702	{
703	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
704	while (iPT-- > 0)
705	if (GstWalk.pPde[iPT].n.u1Present)
706	{
707	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
708	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
709	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
710	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
711	return VINF_PGM_SYNC_CR3;
712	}
713	}
714
715	/*
716	* Check if the fault address is in a virtual page access handler range.
717	*/
718	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers,
719	pvFault);
720	if ( pCur
721	&& pvFault - pCur->Core.Key < pCur->cb
722	&& uErr & X86_TRAP_PF_RW)
723	{
724	VBOXSTRICTRC rcStrict;
725	# ifdef IN_RC
726	STAM_PROFILE_START(&pCur->Stat, h);
727	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
728	void *pvUser = pCur->CTX_SUFF(pvUser);
729	pgmUnlock(pVM);
730	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
731	pvFault - pCur->Core.Key, pvUser);
732	pgmLock(pVM);
733	STAM_PROFILE_STOP(&pCur->Stat, h);
734	# else
735	AssertFailed();
736	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
737	# endif
738	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
739	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
740	return VBOXSTRICTRC_TODO(rcStrict);
741	}
742
743	/*
744	* Pretend we're not here and let the guest handle the trap.
745	*/
746	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
747	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
748	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
749	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
750	return VINF_EM_RAW_GUEST_TRAP;
751	}
752	}
753	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
754	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
755
756	/*
757	* Check if this fault address is flagged for special treatment,
758	* which means we'll have to figure out the physical address and
759	* check flags associated with it.
760	*
761	* ASSUME that we can limit any special access handling to pages
762	* in page tables which the guest believes to be present.
763	*/
764	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
765	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
766	# else
767	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
768	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
769	PPGMPAGE pPage;
770	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
771	if (RT_FAILURE(rc))
772	{
773	/*
774	* When the guest accesses invalid physical memory (e.g. probing
775	* of RAM or accessing a remapped MMIO range), then we'll fall
776	* back to the recompiler to emulate the instruction.
777	*/
778	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
779	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
780	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
781	return VINF_EM_RAW_EMULATE_INSTR;
782	}
783
784	/*
785	* Any handlers for this page?
786	*/
787	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
788	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
789	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
790	&GstWalk));
791	# else
792	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
793	# endif
794
795	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
796	if (uErr & X86_TRAP_PF_P)
797	{
798	/*
799	* The page isn't marked, but it might still be monitored by a virtual page access handler.
800	* (ASSUMES no temporary disabling of virtual handlers.)
801	*/
802	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
803	* we should correct both the shadow page table and physical memory flags, and not only check for
804	* accesses within the handler region but for access to pages with virtual handlers. */
805	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
806	if (pCur)
807	{
808	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
809	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
810	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
811	\|\| !(uErr & X86_TRAP_PF_P)
812	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
813	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enumKind=%d\n",
814	pvFault, GCPhys, pPage, uErr, pCurType->enmKind));
815
816	if ( pvFault - pCur->Core.Key < pCur->cb
817	&& ( uErr & X86_TRAP_PF_RW
818	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
819	{
820	VBOXSTRICTRC rcStrict;
821	# ifdef IN_RC
822	STAM_PROFILE_START(&pCur->Stat, h);
823	void *pvUser = pCur->CTX_SUFF(pvUser);
824	pgmUnlock(pVM);
825	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
826	pvFault - pCur->Core.Key, pvUser);
827	pgmLock(pVM);
828	STAM_PROFILE_STOP(&pCur->Stat, h);
829	# else
830	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
831	# endif
832	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
833	return VBOXSTRICTRC_TODO(rcStrict);
834	}
835	}
836	}
837	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
838
839	/*
840	* We are here only if page is present in Guest page tables and
841	* trap is not handled by our handlers.
842	*
843	* Check it for page out-of-sync situation.
844	*/
845	if (!(uErr & X86_TRAP_PF_P))
846	{
847	/*
848	* Page is not present in our page tables. Try to sync it!
849	*/
850	if (uErr & X86_TRAP_PF_US)
851	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
852	else /* supervisor */
853	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
854
855	if (PGM_PAGE_IS_BALLOONED(pPage))
856	{
857	/* Emulate reads from ballooned pages as they are not present in
858	our shadow page tables. (Required for e.g. Solaris guests; soft
859	ecc, random nr generator.) */
860	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
861	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
862	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
863	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
864	return rc;
865	}
866
867	# if defined(LOG_ENABLED) && !defined(IN_RING0)
868	RTGCPHYS GCPhys2;
869	uint64_t fPageGst2;
870	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
871	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
872	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
873	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
874	# else
875	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
876	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
877	# endif
878	# endif /* LOG_ENABLED */
879
880	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
881	if ( !GstWalk.Core.fEffectiveUS
882	&& CSAMIsEnabled(pVM)
883	&& CPUMGetGuestCPL(pVCpu) == 0)
884	{
885	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
886	if ( pvFault == (RTGCPTR)pRegFrame->eip
887	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
888	# ifdef CSAM_DETECT_NEW_CODE_PAGES
889	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
890	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
891	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
892	)
893	{
894	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
895	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
896	if (rc != VINF_SUCCESS)
897	{
898	/*
899	* CSAM needs to perform a job in ring 3.
900	*
901	* Sync the page before going to the host context; otherwise we'll end up in a loop if
902	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
903	*/
904	LogFlow(("CSAM ring 3 job\n"));
905	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
906	AssertRC(rc2);
907
908	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
909	return rc;
910	}
911	}
912	# ifdef CSAM_DETECT_NEW_CODE_PAGES
913	else if ( uErr == X86_TRAP_PF_RW
914	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
915	&& pRegFrame->ecx < 0x10000)
916	{
917	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
918	* to detect loading of new code pages.
919	*/
920
921	/*
922	* Decode the instruction.
923	*/
924	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
925	uint32_t cbOp;
926	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
927
928	/* For now we'll restrict this to rep movsw/d instructions */
929	if ( rc == VINF_SUCCESS
930	&& pDis->pCurInstr->opcode == OP_MOVSWD
931	&& (pDis->prefix & DISPREFIX_REP))
932	{
933	CSAMMarkPossibleCodePage(pVM, pvFault);
934	}
935	}
936	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
937
938	/*
939	* Mark this page as safe.
940	*/
941	/** @todo not correct for pages that contain both code and data!! */
942	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
943	CSAMMarkPage(pVM, pvFault, true);
944	}
945	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
946	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
947	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
948	# else
949	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
950	# endif
951	if (RT_SUCCESS(rc))
952	{
953	/* The page was successfully synced, return to the guest. */
954	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
955	return VINF_SUCCESS;
956	}
957	}
958	else /* uErr & X86_TRAP_PF_P: */
959	{
960	/*
961	* Write protected pages are made writable when the guest makes the
962	* first write to it. This happens for pages that are shared, write
963	* monitored or not yet allocated.
964	*
965	* We may also end up here when CR0.WP=0 in the guest.
966	*
967	* Also, a side effect of not flushing global PDEs are out of sync
968	* pages due to physical monitored regions, that are no longer valid.
969	* Assume for now it only applies to the read/write flag.
970	*/
971	if (uErr & X86_TRAP_PF_RW)
972	{
973	/*
974	* Check if it is a read-only page.
975	*/
976	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
977	{
978	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
979	Assert(!PGM_PAGE_IS_ZERO(pPage));
980	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
981	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
982
983	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
984	if (rc != VINF_SUCCESS)
985	{
986	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
987	return rc;
988	}
989	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
990	return VINF_EM_NO_MEMORY;
991	}
992
993	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
994	/*
995	* Check to see if we need to emulate the instruction if CR0.WP=0.
996	*/
997	if ( !GstWalk.Core.fEffectiveRW
998	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
999	&& CPUMGetGuestCPL(pVCpu) < 3)
1000	{
1001	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
1002
1003	/*
1004	* The Netware WP0+RO+US hack.
1005	*
1006	* Netware sometimes(/always?) runs with WP0. It has been observed doing
1007	* excessive write accesses to pages which are mapped with US=1 and RW=0
1008	* while WP=0. This causes a lot of exits and extremely slow execution.
1009	* To avoid trapping and emulating every write here, we change the shadow
1010	* page table entry to map it as US=0 and RW=1 until user mode tries to
1011	* access it again (see further below). We count these shadow page table
1012	* changes so we can avoid having to clear the page pool every time the WP
1013	* bit changes to 1 (see PGMCr0WpEnabled()).
1014	*/
1015	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1016	if ( GstWalk.Core.fEffectiveUS
1017	&& !GstWalk.Core.fEffectiveRW
1018	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1019	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1020	{
1021	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1022	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1023	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1024	{
1025	PGM_INVL_PG(pVCpu, pvFault);
1026	pVCpu->pgm.s.cNetwareWp0Hacks++;
1027	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1028	return rc;
1029	}
1030	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1031	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1032	}
1033	# endif
1034
1035	/* Interpret the access. */
1036	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1037	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1038	if (RT_SUCCESS(rc))
1039	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1040	else
1041	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1042	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1043	return rc;
1044	}
1045	# endif
1046	/// @todo count the above case; else
1047	if (uErr & X86_TRAP_PF_US)
1048	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1049	else /* supervisor */
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1051
1052	/*
1053	* Sync the page.
1054	*
1055	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1056	* page is not present, which is not true in this case.
1057	*/
1058	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1059	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1060	# else
1061	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1062	# endif
1063	if (RT_SUCCESS(rc))
1064	{
1065	/*
1066	* Page was successfully synced, return to guest but invalidate
1067	* the TLB first as the page is very likely to be in it.
1068	*/
1069	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1070	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1071	# else
1072	PGM_INVL_PG(pVCpu, pvFault);
1073	# endif
1074	# ifdef VBOX_STRICT
1075	RTGCPHYS GCPhys2 = RTGCPHYS_MAX;
1076	uint64_t fPageGst = UINT64_MAX;
1077	if (!pVM->pgm.s.fNestedPaging)
1078	{
1079	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1080	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1081	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1082	}
1083	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
1084	uint64_t fPageShw = 0;
1085	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1086	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1087	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GCPhys2, fPageGst, pvFault));
1088	# endif
1089	# endif /* VBOX_STRICT */
1090	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1091	return VINF_SUCCESS;
1092	}
1093	}
1094	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1095	/*
1096	* Check for Netware WP0+RO+US hack from above and undo it when user
1097	* mode accesses the page again.
1098	*/
1099	else if ( GstWalk.Core.fEffectiveUS
1100	&& !GstWalk.Core.fEffectiveRW
1101	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1102	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1103	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1104	&& CPUMGetGuestCPL(pVCpu) == 3
1105	&& pVM->cCpus == 1
1106	)
1107	{
1108	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1109	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1110	if (RT_SUCCESS(rc))
1111	{
1112	PGM_INVL_PG(pVCpu, pvFault);
1113	pVCpu->pgm.s.cNetwareWp0Hacks--;
1114	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1115	return VINF_SUCCESS;
1116	}
1117	}
1118	# endif /* PGM_WITH_PAGING */
1119
1120	/** @todo else: why are we here? */
1121
1122	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1123	/*
1124	* Check for VMM page flags vs. Guest page flags consistency.
1125	* Currently only for debug purposes.
1126	*/
1127	if (RT_SUCCESS(rc))
1128	{
1129	/* Get guest page flags. */
1130	uint64_t fPageGst;
1131	int rc2 = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1132	if (RT_SUCCESS(rc2))
1133	{
1134	uint64_t fPageShw = 0;
1135	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1136
1137	#if 0
1138	/*
1139	* Compare page flags.
1140	* Note: we have AVL, A, D bits desynced.
1141	*/
1142	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1143	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1144	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1145	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1146	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1147	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1148	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1149	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
1150	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
1151	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
1152	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
1153
1154	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
1155	01:01:15.625516 00:08:43.268051 Location :
1156	e:\vbox\svn\trunk\srcPage flags mismatch!
1157	pvFault=fffff801b0d7b000
1158	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
1159	GCPhys=0000000019b52000
1160	fPageShw=0
1161	fPageGst=77b0000000000121
1162	rc=0
1163	#endif
1164
1165	}
1166	else
1167	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1168	}
1169	else
1170	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1171	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1172	}
1173
1174
1175	/*
1176	* If we get here it is because something failed above, i.e. most like guru
1177	* meditiation time.
1178	*/
1179	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1180	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1181	return rc;
1182
1183	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1184	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1185	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1186	return VERR_PGM_NOT_USED_IN_MODE;
1187	# endif
1188	}
1189	#endif /* !IN_RING3 */
1190
1191
1192	/**
1193	* Emulation of the invlpg instruction.
1194	*
1195	*
1196	* @returns VBox status code.
1197	*
1198	* @param pVCpu The cross context virtual CPU structure.
1199	* @param GCPtrPage Page to invalidate.
1200	*
1201	* @remark ASSUMES that the guest is updating before invalidating. This order
1202	* isn't required by the CPU, so this is speculative and could cause
1203	* trouble.
1204	* @remark No TLB shootdown is done on any other VCPU as we assume that
1205	* invlpg emulation is the only reason for calling this function.
1206	* (The guest has to shoot down TLB entries on other CPUs itself)
1207	* Currently true, but keep in mind!
1208	*
1209	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1210	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1211	*/
1212	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1213	{
1214	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1215	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1216	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1217	int rc;
1218	PVM pVM = pVCpu->CTX_SUFF(pVM);
1219	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1220
1221	PGM_LOCK_ASSERT_OWNER(pVM);
1222
1223	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1224
1225	/*
1226	* Get the shadow PD entry and skip out if this PD isn't present.
1227	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1228	*/
1229	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1230	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1231	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1232
1233	/* Fetch the pgm pool shadow descriptor. */
1234	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1235	Assert(pShwPde);
1236
1237	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1238	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1239	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1240
1241	/* If the shadow PDPE isn't present, then skip the invalidate. */
1242	if (!pPdptDst->a[iPdpt].n.u1Present)
1243	{
1244	Assert(!(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1245	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1246	PGM_INVL_PG(pVCpu, GCPtrPage);
1247	return VINF_SUCCESS;
1248	}
1249
1250	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1251	PPGMPOOLPAGE pShwPde = NULL;
1252	PX86PDPAE pPDDst;
1253
1254	/* Fetch the pgm pool shadow descriptor. */
1255	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1256	AssertRCSuccessReturn(rc, rc);
1257	Assert(pShwPde);
1258
1259	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1260	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1261
1262	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1263	/* PML4 */
1264	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1265	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1266	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1267	PX86PDPAE pPDDst;
1268	PX86PDPT pPdptDst;
1269	PX86PML4E pPml4eDst;
1270	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1271	if (rc != VINF_SUCCESS)
1272	{
1273	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1274	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1275	PGM_INVL_PG(pVCpu, GCPtrPage);
1276	return VINF_SUCCESS;
1277	}
1278	Assert(pPDDst);
1279
1280	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1281	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1282
1283	if (!pPdpeDst->n.u1Present)
1284	{
1285	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1286	PGM_INVL_PG(pVCpu, GCPtrPage);
1287	return VINF_SUCCESS;
1288	}
1289
1290	/* Fetch the pgm pool shadow descriptor. */
1291	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1292	Assert(pShwPde);
1293
1294	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1295
1296	const SHWPDE PdeDst = *pPdeDst;
1297	if (!PdeDst.n.u1Present)
1298	{
1299	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1300	PGM_INVL_PG(pVCpu, GCPtrPage);
1301	return VINF_SUCCESS;
1302	}
1303
1304	/*
1305	* Get the guest PD entry and calc big page.
1306	*/
1307	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1308	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1309	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1310	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1311	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1312	unsigned iPDSrc = 0;
1313	# if PGM_GST_TYPE == PGM_TYPE_PAE
1314	X86PDPE PdpeSrcIgn;
1315	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1316	# else /* AMD64 */
1317	PX86PML4E pPml4eSrcIgn;
1318	X86PDPE PdpeSrcIgn;
1319	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1320	# endif
1321	GSTPDE PdeSrc;
1322
1323	if (pPDSrc)
1324	PdeSrc = pPDSrc->a[iPDSrc];
1325	else
1326	PdeSrc.u = 0;
1327	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1328	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1329
1330	# ifdef IN_RING3
1331	/*
1332	* If a CR3 Sync is pending we may ignore the invalidate page operation
1333	* depending on the kind of sync and if it's a global page or not.
1334	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1335	*/
1336	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1337	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1338	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1339	&& fIsBigPage
1340	&& PdeSrc.b.u1Global
1341	)
1342	)
1343	# else
1344	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1345	# endif
1346	{
1347	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1348	return VINF_SUCCESS;
1349	}
1350	# endif /* IN_RING3 */
1351
1352	/*
1353	* Deal with the Guest PDE.
1354	*/
1355	rc = VINF_SUCCESS;
1356	if (PdeSrc.n.u1Present)
1357	{
1358	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1359	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1360	# ifndef PGM_WITHOUT_MAPPING
1361	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1362	{
1363	/*
1364	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1365	*/
1366	Assert(pgmMapAreMappingsEnabled(pVM));
1367	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1368	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1369	}
1370	else
1371	# endif /* !PGM_WITHOUT_MAPPING */
1372	if (!fIsBigPage)
1373	{
1374	/*
1375	* 4KB - page.
1376	*/
1377	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1378	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1379
1380	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1381	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1382	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1383	# endif
1384	if (pShwPage->GCPhys == GCPhys)
1385	{
1386	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1387	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1388
1389	PGSTPT pPTSrc;
1390	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1391	if (RT_SUCCESS(rc))
1392	{
1393	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1394	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1395	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1396	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1397	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1398	GCPtrPage, PteSrc.n.u1Present,
1399	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1400	PteSrc.n.u1User & PdeSrc.n.u1User,
1401	(uint64_t)PteSrc.u,
1402	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1403	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1404	}
1405	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1406	PGM_INVL_PG(pVCpu, GCPtrPage);
1407	}
1408	else
1409	{
1410	/*
1411	* The page table address changed.
1412	*/
1413	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1414	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1415	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1416	ASMAtomicWriteSize(pPdeDst, 0);
1417	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1418	PGM_INVL_VCPU_TLBS(pVCpu);
1419	}
1420	}
1421	else
1422	{
1423	/*
1424	* 2/4MB - page.
1425	*/
1426	/* Before freeing the page, check if anything really changed. */
1427	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1428	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1429	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1430	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1431	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1432	# endif
1433	if ( pShwPage->GCPhys == GCPhys
1434	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1435	{
1436	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1437	/** @todo This test is wrong as it cannot check the G bit!
1438	* FIXME */
1439	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1440	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1441	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1442	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1443	{
1444	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1445	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1446	return VINF_SUCCESS;
1447	}
1448	}
1449
1450	/*
1451	* Ok, the page table is present and it's been changed in the guest.
1452	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1453	* We could do this for some flushes in GC too, but we need an algorithm for
1454	* deciding which 4MB pages containing code likely to be executed very soon.
1455	*/
1456	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1457	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1458	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1459	ASMAtomicWriteSize(pPdeDst, 0);
1460	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1461	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1462	}
1463	}
1464	else
1465	{
1466	/*
1467	* Page directory is not present, mark shadow PDE not present.
1468	*/
1469	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1470	{
1471	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1472	ASMAtomicWriteSize(pPdeDst, 0);
1473	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1474	PGM_INVL_PG(pVCpu, GCPtrPage);
1475	}
1476	else
1477	{
1478	Assert(pgmMapAreMappingsEnabled(pVM));
1479	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1480	}
1481	}
1482	return rc;
1483
1484	#else /* guest real and protected mode */
1485	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1486	NOREF(pVCpu); NOREF(GCPtrPage);
1487	return VINF_SUCCESS;
1488	#endif
1489	}
1490
1491
1492	/**
1493	* Update the tracking of shadowed pages.
1494	*
1495	* @param pVCpu The cross context virtual CPU structure.
1496	* @param pShwPage The shadow page.
1497	* @param HCPhys The physical page we is being dereferenced.
1498	* @param iPte Shadow PTE index
1499	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1500	*/
1501	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1502	RTGCPHYS GCPhysPage)
1503	{
1504	PVM pVM = pVCpu->CTX_SUFF(pVM);
1505
1506	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1507	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1508	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1509
1510	/* Use the hint we retrieved from the cached guest PT. */
1511	if (pShwPage->fDirty)
1512	{
1513	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1514
1515	Assert(pShwPage->cPresent);
1516	Assert(pPool->cPresent);
1517	pShwPage->cPresent--;
1518	pPool->cPresent--;
1519
1520	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1521	AssertRelease(pPhysPage);
1522	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1523	return;
1524	}
1525	# else
1526	NOREF(GCPhysPage);
1527	# endif
1528
1529	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1530	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1531
1532	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1533	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1534	* 2. write protect all shadowed pages. I.e. implement caching.
1535	*/
1536	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1537
1538	/*
1539	* Find the guest address.
1540	*/
1541	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1542	pRam;
1543	pRam = pRam->CTX_SUFF(pNext))
1544	{
1545	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1546	while (iPage-- > 0)
1547	{
1548	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1549	{
1550	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1551
1552	Assert(pShwPage->cPresent);
1553	Assert(pPool->cPresent);
1554	pShwPage->cPresent--;
1555	pPool->cPresent--;
1556
1557	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1558	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1559	return;
1560	}
1561	}
1562	}
1563
1564	for (;;)
1565	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1566	}
1567
1568
1569	/**
1570	* Update the tracking of shadowed pages.
1571	*
1572	* @param pVCpu The cross context virtual CPU structure.
1573	* @param pShwPage The shadow page.
1574	* @param u16 The top 16-bit of the pPage->HCPhys.
1575	* @param pPage Pointer to the guest page. this will be modified.
1576	* @param iPTDst The index into the shadow table.
1577	*/
1578	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1579	{
1580	PVM pVM = pVCpu->CTX_SUFF(pVM);
1581
1582	/*
1583	* Just deal with the simple first time here.
1584	*/
1585	if (!u16)
1586	{
1587	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1588	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1589	/* Save the page table index. */
1590	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1591	}
1592	else
1593	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1594
1595	/* write back */
1596	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1597	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1598
1599	/* update statistics. */
1600	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1601	pShwPage->cPresent++;
1602	if (pShwPage->iFirstPresent > iPTDst)
1603	pShwPage->iFirstPresent = iPTDst;
1604	}
1605
1606
1607	/**
1608	* Modifies a shadow PTE to account for access handlers.
1609	*
1610	* @param pVM The cross context VM structure.
1611	* @param pPage The page in question.
1612	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1613	* A (accessed) bit so it can be emulated correctly.
1614	* @param pPteDst The shadow PTE (output). This is temporary storage and
1615	* does not need to be set atomically.
1616	*/
1617	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1618	{
1619	NOREF(pVM); RT_NOREF_PV(fPteSrc);
1620
1621	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1622	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1623	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1624	{
1625	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1626	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1627	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1628	pPteDst->n.u1Present = 1;
1629	pPteDst->n.u1Execute = 1;
1630	pPteDst->n.u1IgnorePAT = 1;
1631	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1632	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1633	#else
1634	if (fPteSrc & X86_PTE_A)
1635	{
1636	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1637	SHW_PTE_SET_RO(*pPteDst);
1638	}
1639	else
1640	SHW_PTE_SET(*pPteDst, 0);
1641	#endif
1642	}
1643	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1644	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1645	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1646	&& ( BTH_IS_NP_ACTIVE(pVM)
1647	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1648	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1649	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1650	# endif
1651	)
1652	{
1653	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1654	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1655	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1656	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1657	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1658	pPteDst->n.u1Present = 0;
1659	pPteDst->n.u1Write = 1;
1660	pPteDst->n.u1Execute = 0;
1661	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1662	pPteDst->n.u3EMT = 7;
1663	# else
1664	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1665	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1666	# endif
1667	}
1668	# endif
1669	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1670	else
1671	{
1672	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1673	SHW_PTE_SET(*pPteDst, 0);
1674	}
1675	/** @todo count these kinds of entries. */
1676	}
1677
1678
1679	/**
1680	* Creates a 4K shadow page for a guest page.
1681	*
1682	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1683	* physical address. The PdeSrc argument only the flags are used. No page
1684	* structured will be mapped in this function.
1685	*
1686	* @param pVCpu The cross context virtual CPU structure.
1687	* @param pPteDst Destination page table entry.
1688	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1689	* Can safely assume that only the flags are being used.
1690	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1691	* @param pShwPage Pointer to the shadow page.
1692	* @param iPTDst The index into the shadow table.
1693	*
1694	* @remark Not used for 2/4MB pages!
1695	*/
1696	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1697	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1698	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1699	#else
1700	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1701	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1702	#endif
1703	{
1704	PVM pVM = pVCpu->CTX_SUFF(pVM);
1705	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1706
1707	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1708	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1709	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1710
1711	if (pShwPage->fDirty)
1712	{
1713	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1714	PGSTPT pGstPT;
1715
1716	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1717	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1718	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1719	pGstPT->a[iPTDst].u = PteSrc.u;
1720	}
1721	#else
1722	Assert(!pShwPage->fDirty);
1723	#endif
1724
1725	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1726	if ( PteSrc.n.u1Present
1727	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1728	#endif
1729	{
1730	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1731	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1732	# endif
1733	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1734
1735	/*
1736	* Find the ram range.
1737	*/
1738	PPGMPAGE pPage;
1739	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1740	if (RT_SUCCESS(rc))
1741	{
1742	/* Ignore ballooned pages.
1743	Don't return errors or use a fatal assert here as part of a
1744	shadow sync range might included ballooned pages. */
1745	if (PGM_PAGE_IS_BALLOONED(pPage))
1746	{
1747	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1748	return;
1749	}
1750
1751	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1752	/* Make the page writable if necessary. */
1753	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1754	&& ( PGM_PAGE_IS_ZERO(pPage)
1755	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1756	\|\| ( PteSrc.n.u1Write
1757	# else
1758	\|\| ( 1
1759	# endif
1760	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1761	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1762	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1763	# endif
1764	# ifdef VBOX_WITH_PAGE_SHARING
1765	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1766	# endif
1767	)
1768	)
1769	)
1770	{
1771	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1772	AssertRC(rc);
1773	}
1774	#endif
1775
1776	/*
1777	* Make page table entry.
1778	*/
1779	SHWPTE PteDst;
1780	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1781	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1782	# else
1783	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1784	# endif
1785	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1786	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1787	else
1788	{
1789	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1790	/*
1791	* If the page or page directory entry is not marked accessed,
1792	* we mark the page not present.
1793	*/
1794	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1795	{
1796	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1797	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1798	SHW_PTE_SET(PteDst, 0);
1799	}
1800	/*
1801	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1802	* when the page is modified.
1803	*/
1804	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1805	{
1806	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1807	SHW_PTE_SET(PteDst,
1808	fGstShwPteFlags
1809	\| PGM_PAGE_GET_HCPHYS(pPage)
1810	\| PGM_PTFLAGS_TRACK_DIRTY);
1811	SHW_PTE_SET_RO(PteDst);
1812	}
1813	else
1814	#endif
1815	{
1816	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1817	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1818	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1819	PteDst.n.u1Present = 1;
1820	PteDst.n.u1Write = 1;
1821	PteDst.n.u1Execute = 1;
1822	PteDst.n.u1IgnorePAT = 1;
1823	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1824	/* PteDst.n.u1Size = 0 */
1825	#else
1826	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1827	#endif
1828	}
1829
1830	/*
1831	* Make sure only allocated pages are mapped writable.
1832	*/
1833	if ( SHW_PTE_IS_P_RW(PteDst)
1834	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1835	{
1836	/* Still applies to shared pages. */
1837	Assert(!PGM_PAGE_IS_ZERO(pPage));
1838	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1839	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1840	}
1841	}
1842
1843	/*
1844	* Keep user track up to date.
1845	*/
1846	if (SHW_PTE_IS_P(PteDst))
1847	{
1848	if (!SHW_PTE_IS_P(*pPteDst))
1849	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1850	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1851	{
1852	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1853	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1854	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1855	}
1856	}
1857	else if (SHW_PTE_IS_P(*pPteDst))
1858	{
1859	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1860	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1861	}
1862
1863	/*
1864	* Update statistics and commit the entry.
1865	*/
1866	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1867	if (!PteSrc.n.u1Global)
1868	pShwPage->fSeenNonGlobal = true;
1869	#endif
1870	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1871	return;
1872	}
1873
1874	/** @todo count these three different kinds. */
1875	Log2(("SyncPageWorker: invalid address in Pte\n"));
1876	}
1877	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1878	else if (!PteSrc.n.u1Present)
1879	Log2(("SyncPageWorker: page not present in Pte\n"));
1880	else
1881	Log2(("SyncPageWorker: invalid Pte\n"));
1882	#endif
1883
1884	/*
1885	* The page is not present or the PTE is bad. Replace the shadow PTE by
1886	* an empty entry, making sure to keep the user tracking up to date.
1887	*/
1888	if (SHW_PTE_IS_P(*pPteDst))
1889	{
1890	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1891	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1892	}
1893	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1894	}
1895
1896
1897	/**
1898	* Syncs a guest OS page.
1899	*
1900	* There are no conflicts at this point, neither is there any need for
1901	* page table allocations.
1902	*
1903	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1904	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1905	*
1906	* @returns VBox status code.
1907	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1908	* @param pVCpu The cross context virtual CPU structure.
1909	* @param PdeSrc Page directory entry of the guest.
1910	* @param GCPtrPage Guest context page address.
1911	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1912	* @param uErr Fault error (X86_TRAP_PF_*).
1913	*/
1914	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1915	{
1916	PVM pVM = pVCpu->CTX_SUFF(pVM);
1917	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1918	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1919	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
1920
1921	PGM_LOCK_ASSERT_OWNER(pVM);
1922
1923	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1924	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1925	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1926	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1927	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1928
1929	/*
1930	* Assert preconditions.
1931	*/
1932	Assert(PdeSrc.n.u1Present);
1933	Assert(cPages);
1934	# if 0 /* rarely useful; leave for debugging. */
1935	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1936	# endif
1937
1938	/*
1939	* Get the shadow PDE, find the shadow page table in the pool.
1940	*/
1941	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1942	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1943	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1944
1945	/* Fetch the pgm pool shadow descriptor. */
1946	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1947	Assert(pShwPde);
1948
1949	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1950	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1951	PPGMPOOLPAGE pShwPde = NULL;
1952	PX86PDPAE pPDDst;
1953
1954	/* Fetch the pgm pool shadow descriptor. */
1955	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1956	AssertRCSuccessReturn(rc2, rc2);
1957	Assert(pShwPde);
1958
1959	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1960	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1961
1962	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1963	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1964	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1965	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1966	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1967
1968	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1969	AssertRCSuccessReturn(rc2, rc2);
1970	Assert(pPDDst && pPdptDst);
1971	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1972	# endif
1973	SHWPDE PdeDst = *pPdeDst;
1974
1975	/*
1976	* - In the guest SMP case we could have blocked while another VCPU reused
1977	* this page table.
1978	* - With W7-64 we may also take this path when the A bit is cleared on
1979	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1980	* relevant TLB entries. If we're write monitoring any page mapped by
1981	* the modified entry, we may end up here with a "stale" TLB entry.
1982	*/
1983	if (!PdeDst.n.u1Present)
1984	{
1985	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1986	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1987	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1988	if (uErr & X86_TRAP_PF_P)
1989	PGM_INVL_PG(pVCpu, GCPtrPage);
1990	return VINF_SUCCESS; /* force the instruction to be executed again. */
1991	}
1992
1993	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1994	Assert(pShwPage);
1995
1996	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1997	/* Fetch the pgm pool shadow descriptor. */
1998	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
1999	Assert(pShwPde);
2000	# endif
2001
2002	/*
2003	* Check that the page is present and that the shadow PDE isn't out of sync.
2004	*/
2005	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
2006	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2007	RTGCPHYS GCPhys;
2008	if (!fBigPage)
2009	{
2010	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2011	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2012	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2013	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2014	# endif
2015	}
2016	else
2017	{
2018	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2019	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2020	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2021	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2022	# endif
2023	}
2024	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2025	if ( fPdeValid
2026	&& pShwPage->GCPhys == GCPhys
2027	&& PdeSrc.n.u1Present
2028	&& PdeSrc.n.u1User == PdeDst.n.u1User
2029	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
2030	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2031	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2032	# endif
2033	)
2034	{
2035	/*
2036	* Check that the PDE is marked accessed already.
2037	* Since we set the accessed bit before getting here on a #PF, this
2038	* check is only meant for dealing with non-#PF'ing paths.
2039	*/
2040	if (PdeSrc.n.u1Accessed)
2041	{
2042	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2043	if (!fBigPage)
2044	{
2045	/*
2046	* 4KB Page - Map the guest page table.
2047	*/
2048	PGSTPT pPTSrc;
2049	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2050	if (RT_SUCCESS(rc))
2051	{
2052	# ifdef PGM_SYNC_N_PAGES
2053	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2054	if ( cPages > 1
2055	&& !(uErr & X86_TRAP_PF_P)
2056	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2057	{
2058	/*
2059	* This code path is currently only taken when the caller is PGMTrap0eHandler
2060	* for non-present pages!
2061	*
2062	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2063	* deal with locality.
2064	*/
2065	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2066	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2067	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2068	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2069	# else
2070	const unsigned offPTSrc = 0;
2071	# endif
2072	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2073	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2074	iPTDst = 0;
2075	else
2076	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2077
2078	for (; iPTDst < iPTDstEnd; iPTDst++)
2079	{
2080	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2081
2082	if ( pPteSrc->n.u1Present
2083	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2084	{
2085	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2086	NOREF(GCPtrCurPage);
2087	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2088	/*
2089	* Assuming kernel code will be marked as supervisor - and not as user level
2090	* and executed using a conforming code selector - And marked as readonly.
2091	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2092	*/
2093	PPGMPAGE pPage;
2094	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2095	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2096	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2097	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2098	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2099	)
2100	# endif /* else: CSAM not active */
2101	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2102	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2103	GCPtrCurPage, pPteSrc->n.u1Present,
2104	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2105	pPteSrc->n.u1User & PdeSrc.n.u1User,
2106	(uint64_t)pPteSrc->u,
2107	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2108	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2109	}
2110	}
2111	}
2112	else
2113	# endif /* PGM_SYNC_N_PAGES */
2114	{
2115	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2116	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2117	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2118	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2119	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2120	GCPtrPage, PteSrc.n.u1Present,
2121	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2122	PteSrc.n.u1User & PdeSrc.n.u1User,
2123	(uint64_t)PteSrc.u,
2124	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2125	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2126	}
2127	}
2128	else /* MMIO or invalid page: emulated in #PF handler. */
2129	{
2130	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2131	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2132	}
2133	}
2134	else
2135	{
2136	/*
2137	* 4/2MB page - lazy syncing shadow 4K pages.
2138	* (There are many causes of getting here, it's no longer only CSAM.)
2139	*/
2140	/* Calculate the GC physical address of this 4KB shadow page. */
2141	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2142	/* Find ram range. */
2143	PPGMPAGE pPage;
2144	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2145	if (RT_SUCCESS(rc))
2146	{
2147	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2148
2149	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2150	/* Try to make the page writable if necessary. */
2151	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2152	&& ( PGM_PAGE_IS_ZERO(pPage)
2153	\|\| ( PdeSrc.n.u1Write
2154	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2155	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2156	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2157	# endif
2158	# ifdef VBOX_WITH_PAGE_SHARING
2159	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2160	# endif
2161	)
2162	)
2163	)
2164	{
2165	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2166	AssertRC(rc);
2167	}
2168	# endif
2169
2170	/*
2171	* Make shadow PTE entry.
2172	*/
2173	SHWPTE PteDst;
2174	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2175	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2176	else
2177	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2178
2179	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2180	if ( SHW_PTE_IS_P(PteDst)
2181	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2182	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2183
2184	/* Make sure only allocated pages are mapped writable. */
2185	if ( SHW_PTE_IS_P_RW(PteDst)
2186	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2187	{
2188	/* Still applies to shared pages. */
2189	Assert(!PGM_PAGE_IS_ZERO(pPage));
2190	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2191	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2192	}
2193
2194	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2195
2196	/*
2197	* If the page is not flagged as dirty and is writable, then make it read-only
2198	* at PD level, so we can set the dirty bit when the page is modified.
2199	*
2200	* ASSUMES that page access handlers are implemented on page table entry level.
2201	* Thus we will first catch the dirty access and set PDE.D and restart. If
2202	* there is an access handler, we'll trap again and let it work on the problem.
2203	*/
2204	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2205	* As for invlpg, it simply frees the whole shadow PT.
2206	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2207	if ( !PdeSrc.b.u1Dirty
2208	&& PdeSrc.b.u1Write)
2209	{
2210	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2211	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2212	PdeDst.n.u1Write = 0;
2213	}
2214	else
2215	{
2216	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2217	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2218	}
2219	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2220	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2221	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2222	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2223	}
2224	else
2225	{
2226	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2227	/** @todo must wipe the shadow page table entry in this
2228	* case. */
2229	}
2230	}
2231	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2232	return VINF_SUCCESS;
2233	}
2234
2235	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2236	}
2237	else if (fPdeValid)
2238	{
2239	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2240	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2241	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2242	}
2243	else
2244	{
2245	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2246	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2247	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2248	}
2249
2250	/*
2251	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2252	* Yea, I'm lazy.
2253	*/
2254	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2255	ASMAtomicWriteSize(pPdeDst, 0);
2256
2257	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2258	PGM_INVL_VCPU_TLBS(pVCpu);
2259	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2260
2261
2262	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2263	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2264	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2265	&& !defined(IN_RC)
2266	NOREF(PdeSrc);
2267
2268	# ifdef PGM_SYNC_N_PAGES
2269	/*
2270	* Get the shadow PDE, find the shadow page table in the pool.
2271	*/
2272	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2273	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2274
2275	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2276	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2277
2278	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2279	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2280	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2281	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2282	X86PDEPAE PdeDst;
2283	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2284
2285	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2286	AssertRCSuccessReturn(rc, rc);
2287	Assert(pPDDst && pPdptDst);
2288	PdeDst = pPDDst->a[iPDDst];
2289	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2290	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2291	PEPTPD pPDDst;
2292	EPTPDE PdeDst;
2293
2294	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2295	if (rc != VINF_SUCCESS)
2296	{
2297	AssertRC(rc);
2298	return rc;
2299	}
2300	Assert(pPDDst);
2301	PdeDst = pPDDst->a[iPDDst];
2302	# endif
2303	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2304	if (!PdeDst.n.u1Present)
2305	{
2306	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2307	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2308	return VINF_SUCCESS; /* force the instruction to be executed again. */
2309	}
2310
2311	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2312	if (PdeDst.n.u1Size)
2313	{
2314	Assert(pVM->pgm.s.fNestedPaging);
2315	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2316	return VINF_SUCCESS;
2317	}
2318
2319	/* Mask away the page offset. */
2320	GCPtrPage &= ~((RTGCPTR)0xfff);
2321
2322	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2323	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2324
2325	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2326	if ( cPages > 1
2327	&& !(uErr & X86_TRAP_PF_P)
2328	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2329	{
2330	/*
2331	* This code path is currently only taken when the caller is PGMTrap0eHandler
2332	* for non-present pages!
2333	*
2334	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2335	* deal with locality.
2336	*/
2337	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2338	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2339	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2340	iPTDst = 0;
2341	else
2342	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2343	for (; iPTDst < iPTDstEnd; iPTDst++)
2344	{
2345	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2346	{
2347	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2348	\| (iPTDst << PAGE_SHIFT));
2349
2350	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2351	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2352	GCPtrCurPage,
2353	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2354	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2355
2356	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2357	break;
2358	}
2359	else
2360	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2361	}
2362	}
2363	else
2364	# endif /* PGM_SYNC_N_PAGES */
2365	{
2366	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2367	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2368	\| (iPTDst << PAGE_SHIFT));
2369
2370	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2371
2372	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2373	GCPtrPage,
2374	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2375	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2376	}
2377	return VINF_SUCCESS;
2378
2379	#else
2380	NOREF(PdeSrc);
2381	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2382	return VERR_PGM_NOT_USED_IN_MODE;
2383	#endif
2384	}
2385
2386
2387	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2388
2389	/**
2390	* CheckPageFault helper for returning a page fault indicating a non-present
2391	* (NP) entry in the page translation structures.
2392	*
2393	* @returns VINF_EM_RAW_GUEST_TRAP.
2394	* @param pVCpu The cross context virtual CPU structure.
2395	* @param uErr The error code of the shadow fault. Corrections to
2396	* TRPM's copy will be made if necessary.
2397	* @param GCPtrPage For logging.
2398	* @param uPageFaultLevel For logging.
2399	*/
2400	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2401	{
2402	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2403	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2404	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2405	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2406	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2407
2408	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2409	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2410	return VINF_EM_RAW_GUEST_TRAP;
2411	}
2412
2413
2414	/**
2415	* CheckPageFault helper for returning a page fault indicating a reserved bit
2416	* (RSVD) error in the page translation structures.
2417	*
2418	* @returns VINF_EM_RAW_GUEST_TRAP.
2419	* @param pVCpu The cross context virtual CPU structure.
2420	* @param uErr The error code of the shadow fault. Corrections to
2421	* TRPM's copy will be made if necessary.
2422	* @param GCPtrPage For logging.
2423	* @param uPageFaultLevel For logging.
2424	*/
2425	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2426	{
2427	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2428	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2429	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2430
2431	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2432	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2433	return VINF_EM_RAW_GUEST_TRAP;
2434	}
2435
2436
2437	/**
2438	* CheckPageFault helper for returning a page protection fault (P).
2439	*
2440	* @returns VINF_EM_RAW_GUEST_TRAP.
2441	* @param pVCpu The cross context virtual CPU structure.
2442	* @param uErr The error code of the shadow fault. Corrections to
2443	* TRPM's copy will be made if necessary.
2444	* @param GCPtrPage For logging.
2445	* @param uPageFaultLevel For logging.
2446	*/
2447	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2448	{
2449	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2450	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2451	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2452	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2453
2454	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2455	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2456	return VINF_EM_RAW_GUEST_TRAP;
2457	}
2458
2459
2460	/**
2461	* Handle dirty bit tracking faults.
2462	*
2463	* @returns VBox status code.
2464	* @param pVCpu The cross context virtual CPU structure.
2465	* @param uErr Page fault error code.
2466	* @param pPdeSrc Guest page directory entry.
2467	* @param pPdeDst Shadow page directory entry.
2468	* @param GCPtrPage Guest context page address.
2469	*/
2470	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2471	RTGCPTR GCPtrPage)
2472	{
2473	PVM pVM = pVCpu->CTX_SUFF(pVM);
2474	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2475	NOREF(uErr);
2476
2477	PGM_LOCK_ASSERT_OWNER(pVM);
2478
2479	/*
2480	* Handle big page.
2481	*/
2482	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2483	{
2484	if ( pPdeDst->n.u1Present
2485	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2486	{
2487	SHWPDE PdeDst = *pPdeDst;
2488
2489	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2490	Assert(pPdeSrc->b.u1Write);
2491
2492	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2493	* fault again and take this path to only invalidate the entry (see below).
2494	*/
2495	PdeDst.n.u1Write = 1;
2496	PdeDst.n.u1Accessed = 1;
2497	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2498	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2499	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2500	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2501	}
2502
2503	# ifdef IN_RING0
2504	/* Check for stale TLB entry; only applies to the SMP guest case. */
2505	if ( pVM->cCpus > 1
2506	&& pPdeDst->n.u1Write
2507	&& pPdeDst->n.u1Accessed)
2508	{
2509	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2510	if (pShwPage)
2511	{
2512	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2513	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2514	if (SHW_PTE_IS_P_RW(*pPteDst))
2515	{
2516	/* Stale TLB entry. */
2517	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2518	PGM_INVL_PG(pVCpu, GCPtrPage);
2519	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2520	}
2521	}
2522	}
2523	# endif /* IN_RING0 */
2524	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2525	}
2526
2527	/*
2528	* Map the guest page table.
2529	*/
2530	PGSTPT pPTSrc;
2531	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2532	if (RT_FAILURE(rc))
2533	{
2534	AssertRC(rc);
2535	return rc;
2536	}
2537
2538	if (pPdeDst->n.u1Present)
2539	{
2540	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2541	const GSTPTE PteSrc = *pPteSrc;
2542
2543	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2544	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2545	* Our individual shadow handlers will provide more information and force a fatal exit.
2546	*/
2547	if ( !HMIsEnabled(pVM)
2548	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2549	{
2550	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2551	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2552	}
2553	#endif
2554	/*
2555	* Map shadow page table.
2556	*/
2557	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2558	if (pShwPage)
2559	{
2560	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2561	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2562	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2563	{
2564	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2565	{
2566	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2567	SHWPTE PteDst = *pPteDst;
2568
2569	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2570	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2571
2572	Assert(PteSrc.n.u1Write);
2573
2574	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2575	* entry will not harm; write access will simply fault again and
2576	* take this path to only invalidate the entry.
2577	*/
2578	if (RT_LIKELY(pPage))
2579	{
2580	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2581	{
2582	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2583	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2584	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2585	SHW_PTE_SET_RO(PteDst);
2586	}
2587	else
2588	{
2589	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2590	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2591	{
2592	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2593	AssertRC(rc);
2594	}
2595	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2596	SHW_PTE_SET_RW(PteDst);
2597	else
2598	{
2599	/* Still applies to shared pages. */
2600	Assert(!PGM_PAGE_IS_ZERO(pPage));
2601	SHW_PTE_SET_RO(PteDst);
2602	}
2603	}
2604	}
2605	else
2606	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2607
2608	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2609	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2610	PGM_INVL_PG(pVCpu, GCPtrPage);
2611	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2612	}
2613
2614	# ifdef IN_RING0
2615	/* Check for stale TLB entry; only applies to the SMP guest case. */
2616	if ( pVM->cCpus > 1
2617	&& SHW_PTE_IS_RW(*pPteDst)
2618	&& SHW_PTE_IS_A(*pPteDst))
2619	{
2620	/* Stale TLB entry. */
2621	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2622	PGM_INVL_PG(pVCpu, GCPtrPage);
2623	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2624	}
2625	# endif
2626	}
2627	}
2628	else
2629	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2630	}
2631
2632	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2633	}
2634
2635	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2636
2637
2638	/**
2639	* Sync a shadow page table.
2640	*
2641	* The shadow page table is not present in the shadow PDE.
2642	*
2643	* Handles mapping conflicts.
2644	*
2645	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2646	* conflict), and Trap0eHandler.
2647	*
2648	* A precondition for this method is that the shadow PDE is not present. The
2649	* caller must take the PGM lock before checking this and continue to hold it
2650	* when calling this method.
2651	*
2652	* @returns VBox status code.
2653	* @param pVCpu The cross context virtual CPU structure.
2654	* @param iPDSrc Page directory index.
2655	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2656	* Assume this is a temporary mapping.
2657	* @param GCPtrPage GC Pointer of the page that caused the fault
2658	*/
2659	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2660	{
2661	PVM pVM = pVCpu->CTX_SUFF(pVM);
2662	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2663
2664	#if 0 /* rarely useful; leave for debugging. */
2665	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2666	#endif
2667	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
2668
2669	PGM_LOCK_ASSERT_OWNER(pVM);
2670
2671	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2672	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2673	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2674	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2675	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2676
2677	int rc = VINF_SUCCESS;
2678
2679	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2680
2681	/*
2682	* Some input validation first.
2683	*/
2684	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2685
2686	/*
2687	* Get the relevant shadow PDE entry.
2688	*/
2689	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2690	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2691	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2692
2693	/* Fetch the pgm pool shadow descriptor. */
2694	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2695	Assert(pShwPde);
2696
2697	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2698	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2699	PPGMPOOLPAGE pShwPde = NULL;
2700	PX86PDPAE pPDDst;
2701	PSHWPDE pPdeDst;
2702
2703	/* Fetch the pgm pool shadow descriptor. */
2704	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2705	AssertRCSuccessReturn(rc, rc);
2706	Assert(pShwPde);
2707
2708	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2709	pPdeDst = &pPDDst->a[iPDDst];
2710
2711	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2712	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2713	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2714	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2715	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2716	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2717	AssertRCSuccessReturn(rc, rc);
2718	Assert(pPDDst);
2719	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2720	# endif
2721	SHWPDE PdeDst = *pPdeDst;
2722
2723	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2724	/* Fetch the pgm pool shadow descriptor. */
2725	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2726	Assert(pShwPde);
2727	# endif
2728
2729	# ifndef PGM_WITHOUT_MAPPINGS
2730	/*
2731	* Check for conflicts.
2732	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2733	* R3: Simply resolve the conflict.
2734	*/
2735	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2736	{
2737	Assert(pgmMapAreMappingsEnabled(pVM));
2738	# ifndef IN_RING3
2739	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2740	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2741	return VERR_ADDRESS_CONFLICT;
2742
2743	# else /* IN_RING3 */
2744	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2745	Assert(pMapping);
2746	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2747	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2748	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2749	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2750	# else
2751	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2752	# endif
2753	if (RT_FAILURE(rc))
2754	{
2755	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2756	return rc;
2757	}
2758	PdeDst = *pPdeDst;
2759	# endif /* IN_RING3 */
2760	}
2761	# endif /* !PGM_WITHOUT_MAPPINGS */
2762	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2763
2764	/*
2765	* Sync the page directory entry.
2766	*/
2767	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2768	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2769	if ( PdeSrc.n.u1Present
2770	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2771	{
2772	/*
2773	* Allocate & map the page table.
2774	*/
2775	PSHWPT pPTDst;
2776	PPGMPOOLPAGE pShwPage;
2777	RTGCPHYS GCPhys;
2778	if (fPageTable)
2779	{
2780	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2781	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2782	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2783	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2784	# endif
2785	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2786	pShwPde->idx, iPDDst, false /fLockPage/,
2787	&pShwPage);
2788	}
2789	else
2790	{
2791	PGMPOOLACCESS enmAccess;
2792	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2793	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2794	# else
2795	const bool fNoExecute = false;
2796	# endif
2797
2798	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2799	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2800	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2801	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2802	# endif
2803	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2804	if (PdeSrc.n.u1User)
2805	{
2806	if (PdeSrc.n.u1Write)
2807	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2808	else
2809	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2810	}
2811	else
2812	{
2813	if (PdeSrc.n.u1Write)
2814	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2815	else
2816	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2817	}
2818	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2819	pShwPde->idx, iPDDst, false /fLockPage/,
2820	&pShwPage);
2821	}
2822	if (rc == VINF_SUCCESS)
2823	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2824	else if (rc == VINF_PGM_CACHED_PAGE)
2825	{
2826	/*
2827	* The PT was cached, just hook it up.
2828	*/
2829	if (fPageTable)
2830	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2831	else
2832	{
2833	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2834	/* (see explanation and assumptions further down.) */
2835	if ( !PdeSrc.b.u1Dirty
2836	&& PdeSrc.b.u1Write)
2837	{
2838	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2839	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2840	PdeDst.b.u1Write = 0;
2841	}
2842	}
2843	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2844	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2845	return VINF_SUCCESS;
2846	}
2847	else if (rc == VERR_PGM_POOL_FLUSHED)
2848	{
2849	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2850	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2851	return VINF_PGM_SYNC_CR3;
2852	}
2853	else
2854	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2855	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2856	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2857	* irrelevant at this point. */
2858	PdeDst.u &= X86_PDE_AVL_MASK;
2859	PdeDst.u \|= pShwPage->Core.Key;
2860
2861	/*
2862	* Page directory has been accessed (this is a fault situation, remember).
2863	*/
2864	/** @todo
2865	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2866	* fault situation. What's more, the Trap0eHandler has already set the
2867	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2868	* might need setting the accessed flag.
2869	*
2870	* The best idea is to leave this change to the caller and add an
2871	* assertion that it's set already. */
2872	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2873	if (fPageTable)
2874	{
2875	/*
2876	* Page table - 4KB.
2877	*
2878	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2879	*/
2880	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2881	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2882	PGSTPT pPTSrc;
2883	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2884	if (RT_SUCCESS(rc))
2885	{
2886	/*
2887	* Start by syncing the page directory entry so CSAM's TLB trick works.
2888	*/
2889	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2890	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2891	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2892	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2893
2894	/*
2895	* Directory/page user or supervisor privilege: (same goes for read/write)
2896	*
2897	* Directory Page Combined
2898	* U/S U/S U/S
2899	* 0 0 0
2900	* 0 1 0
2901	* 1 0 0
2902	* 1 1 1
2903	*
2904	* Simple AND operation. Table listed for completeness.
2905	*
2906	*/
2907	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2908	# ifdef PGM_SYNC_N_PAGES
2909	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2910	unsigned iPTDst = iPTBase;
2911	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2912	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2913	iPTDst = 0;
2914	else
2915	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2916	# else /* !PGM_SYNC_N_PAGES */
2917	unsigned iPTDst = 0;
2918	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2919	# endif /* !PGM_SYNC_N_PAGES */
2920	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2921	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2922	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2923	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2924	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2925	# else
2926	const unsigned offPTSrc = 0;
2927	# endif
2928	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2929	{
2930	const unsigned iPTSrc = iPTDst + offPTSrc;
2931	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2932
2933	if (PteSrc.n.u1Present)
2934	{
2935	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2936	/*
2937	* Assuming kernel code will be marked as supervisor - and not as user level
2938	* and executed using a conforming code selector - And marked as readonly.
2939	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2940	*/
2941	PPGMPAGE pPage;
2942	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2943	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2944	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2945	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2946	)
2947	# endif
2948	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2949	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2950	GCPtrCur,
2951	PteSrc.n.u1Present,
2952	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2953	PteSrc.n.u1User & PdeSrc.n.u1User,
2954	(uint64_t)PteSrc.u,
2955	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2956	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2957	}
2958	/* else: the page table was cleared by the pool */
2959	} /* for PTEs */
2960	}
2961	}
2962	else
2963	{
2964	/*
2965	* Big page - 2/4MB.
2966	*
2967	* We'll walk the ram range list in parallel and optimize lookups.
2968	* We will only sync one shadow page table at a time.
2969	*/
2970	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2971
2972	/**
2973	* @todo It might be more efficient to sync only a part of the 4MB
2974	* page (similar to what we do for 4KB PDs).
2975	*/
2976
2977	/*
2978	* Start by syncing the page directory entry.
2979	*/
2980	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2981	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2982
2983	/*
2984	* If the page is not flagged as dirty and is writable, then make it read-only
2985	* at PD level, so we can set the dirty bit when the page is modified.
2986	*
2987	* ASSUMES that page access handlers are implemented on page table entry level.
2988	* Thus we will first catch the dirty access and set PDE.D and restart. If
2989	* there is an access handler, we'll trap again and let it work on the problem.
2990	*/
2991	/** @todo move the above stuff to a section in the PGM documentation. */
2992	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2993	if ( !PdeSrc.b.u1Dirty
2994	&& PdeSrc.b.u1Write)
2995	{
2996	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2997	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2998	PdeDst.b.u1Write = 0;
2999	}
3000	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3001	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3002
3003	/*
3004	* Fill the shadow page table.
3005	*/
3006	/* Get address and flags from the source PDE. */
3007	SHWPTE PteDstBase;
3008	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3009
3010	/* Loop thru the entries in the shadow PT. */
3011	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3012	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3013	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
3014	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3015	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3016	unsigned iPTDst = 0;
3017	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3018	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3019	{
3020	if (pRam && GCPhys >= pRam->GCPhys)
3021	{
3022	# ifndef PGM_WITH_A20
3023	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3024	# endif
3025	do
3026	{
3027	/* Make shadow PTE. */
3028	# ifdef PGM_WITH_A20
3029	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3030	# else
3031	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3032	# endif
3033	SHWPTE PteDst;
3034
3035	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3036	/* Try to make the page writable if necessary. */
3037	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3038	&& ( PGM_PAGE_IS_ZERO(pPage)
3039	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3040	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3041	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3042	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3043	# endif
3044	# ifdef VBOX_WITH_PAGE_SHARING
3045	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3046	# endif
3047	&& !PGM_PAGE_IS_BALLOONED(pPage))
3048	)
3049	)
3050	{
3051	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3052	AssertRCReturn(rc, rc);
3053	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3054	break;
3055	}
3056	# endif
3057
3058	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3059	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3060	else if (PGM_PAGE_IS_BALLOONED(pPage))
3061	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3062	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3063	/*
3064	* Assuming kernel code will be marked as supervisor and not as user level and executed
3065	* using a conforming code selector. Don't check for readonly, as that implies the whole
3066	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3067	*/
3068	else if ( !PdeSrc.n.u1User
3069	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3070	SHW_PTE_SET(PteDst, 0);
3071	# endif
3072	else
3073	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3074
3075	/* Only map writable pages writable. */
3076	if ( SHW_PTE_IS_P_RW(PteDst)
3077	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3078	{
3079	/* Still applies to shared pages. */
3080	Assert(!PGM_PAGE_IS_ZERO(pPage));
3081	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3082	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3083	}
3084
3085	if (SHW_PTE_IS_P(PteDst))
3086	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3087
3088	/* commit it (not atomic, new table) */
3089	pPTDst->a[iPTDst] = PteDst;
3090	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3091	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3092	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3093
3094	/* advance */
3095	GCPhys += PAGE_SIZE;
3096	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3097	# ifndef PGM_WITH_A20
3098	iHCPage++;
3099	# endif
3100	iPTDst++;
3101	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3102	&& GCPhys <= pRam->GCPhysLast);
3103
3104	/* Advance ram range list. */
3105	while (pRam && GCPhys > pRam->GCPhysLast)
3106	pRam = pRam->CTX_SUFF(pNext);
3107	}
3108	else if (pRam)
3109	{
3110	Log(("Invalid pages at %RGp\n", GCPhys));
3111	do
3112	{
3113	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3114	GCPhys += PAGE_SIZE;
3115	iPTDst++;
3116	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3117	&& GCPhys < pRam->GCPhys);
3118	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3119	}
3120	else
3121	{
3122	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3123	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3124	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3125	}
3126	} /* while more PTEs */
3127	} /* 4KB / 4MB */
3128	}
3129	else
3130	AssertRelease(!PdeDst.n.u1Present);
3131
3132	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3133	if (RT_FAILURE(rc))
3134	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3135	return rc;
3136
3137	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3138	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3139	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3140	&& !defined(IN_RC)
3141	NOREF(iPDSrc); NOREF(pPDSrc);
3142
3143	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3144
3145	/*
3146	* Validate input a little bit.
3147	*/
3148	int rc = VINF_SUCCESS;
3149	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3150	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3151	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3152
3153	/* Fetch the pgm pool shadow descriptor. */
3154	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3155	Assert(pShwPde);
3156
3157	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3158	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3159	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3160	PX86PDPAE pPDDst;
3161	PSHWPDE pPdeDst;
3162
3163	/* Fetch the pgm pool shadow descriptor. */
3164	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3165	AssertRCSuccessReturn(rc, rc);
3166	Assert(pShwPde);
3167
3168	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3169	pPdeDst = &pPDDst->a[iPDDst];
3170
3171	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3172	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3173	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3174	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3175	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3176	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3177	AssertRCSuccessReturn(rc, rc);
3178	Assert(pPDDst);
3179	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3180
3181	/* Fetch the pgm pool shadow descriptor. */
3182	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3183	Assert(pShwPde);
3184
3185	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3186	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3187	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3188	PEPTPD pPDDst;
3189	PEPTPDPT pPdptDst;
3190
3191	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3192	if (rc != VINF_SUCCESS)
3193	{
3194	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3195	AssertRC(rc);
3196	return rc;
3197	}
3198	Assert(pPDDst);
3199	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3200
3201	/* Fetch the pgm pool shadow descriptor. */
3202	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3203	Assert(pShwPde);
3204	# endif
3205	SHWPDE PdeDst = *pPdeDst;
3206
3207	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3208	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3209
3210	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3211	if (BTH_IS_NP_ACTIVE(pVM))
3212	{
3213	/* Check if we allocated a big page before for this 2 MB range. */
3214	PPGMPAGE pPage;
3215	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3216	if (RT_SUCCESS(rc))
3217	{
3218	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3219	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3220	{
3221	if (PGM_A20_IS_ENABLED(pVCpu))
3222	{
3223	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3224	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3225	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3226	}
3227	else
3228	{
3229	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3230	pVM->pgm.s.cLargePagesDisabled++;
3231	}
3232	}
3233	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3234	&& PGM_A20_IS_ENABLED(pVCpu))
3235	{
3236	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3237	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3238	if (RT_SUCCESS(rc))
3239	{
3240	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3241	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3242	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3243	}
3244	}
3245	else if ( PGMIsUsingLargePages(pVM)
3246	&& PGM_A20_IS_ENABLED(pVCpu))
3247	{
3248	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3249	if (RT_SUCCESS(rc))
3250	{
3251	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3252	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3253	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3254	}
3255	else
3256	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3257	}
3258
3259	if (HCPhys != NIL_RTHCPHYS)
3260	{
3261	PdeDst.u &= X86_PDE_AVL_MASK;
3262	PdeDst.u \|= HCPhys;
3263	PdeDst.n.u1Present = 1;
3264	PdeDst.n.u1Write = 1;
3265	PdeDst.b.u1Size = 1;
3266	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3267	PdeDst.n.u1Execute = 1;
3268	PdeDst.b.u1IgnorePAT = 1;
3269	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3270	# else
3271	PdeDst.n.u1User = 1;
3272	# endif
3273	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3274
3275	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3276	/* Add a reference to the first page only. */
3277	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3278
3279	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3280	return VINF_SUCCESS;
3281	}
3282	}
3283	}
3284	# endif /* HC_ARCH_BITS == 64 */
3285
3286	/*
3287	* Allocate & map the page table.
3288	*/
3289	PSHWPT pPTDst;
3290	PPGMPOOLPAGE pShwPage;
3291	RTGCPHYS GCPhys;
3292
3293	/* Virtual address = physical address */
3294	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3295	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3296	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3297	&pShwPage);
3298	if ( rc == VINF_SUCCESS
3299	\|\| rc == VINF_PGM_CACHED_PAGE)
3300	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3301	else
3302	{
3303	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3304	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3305	}
3306
3307	if (rc == VINF_SUCCESS)
3308	{
3309	/* New page table; fully set it up. */
3310	Assert(pPTDst);
3311
3312	/* Mask away the page offset. */
3313	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3314
3315	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3316	{
3317	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3318	\| (iPTDst << PAGE_SHIFT));
3319
3320	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3321	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3322	GCPtrCurPage,
3323	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3324	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3325
3326	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3327	break;
3328	}
3329	}
3330	else
3331	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3332
3333	/* Save the new PDE. */
3334	PdeDst.u &= X86_PDE_AVL_MASK;
3335	PdeDst.u \|= pShwPage->Core.Key;
3336	PdeDst.n.u1Present = 1;
3337	PdeDst.n.u1Write = 1;
3338	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3339	PdeDst.n.u1Execute = 1;
3340	# else
3341	PdeDst.n.u1User = 1;
3342	PdeDst.n.u1Accessed = 1;
3343	# endif
3344	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3345
3346	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3347	if (RT_FAILURE(rc))
3348	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3349	return rc;
3350
3351	#else
3352	NOREF(iPDSrc); NOREF(pPDSrc);
3353	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3354	return VERR_PGM_NOT_USED_IN_MODE;
3355	#endif
3356	}
3357
3358
3359
3360	/**
3361	* Prefetch a page/set of pages.
3362	*
3363	* Typically used to sync commonly used pages before entering raw mode
3364	* after a CR3 reload.
3365	*
3366	* @returns VBox status code.
3367	* @param pVCpu The cross context virtual CPU structure.
3368	* @param GCPtrPage Page to invalidate.
3369	*/
3370	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3371	{
3372	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3373	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3374	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3375	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3376	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3377	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3378	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3379
3380	/*
3381	* Check that all Guest levels thru the PDE are present, getting the
3382	* PD and PDE in the processes.
3383	*/
3384	int rc = VINF_SUCCESS;
3385	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3386	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3387	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3388	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3389	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3390	unsigned iPDSrc;
3391	X86PDPE PdpeSrc;
3392	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3393	if (!pPDSrc)
3394	return VINF_SUCCESS; /* not present */
3395	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3396	unsigned iPDSrc;
3397	PX86PML4E pPml4eSrc;
3398	X86PDPE PdpeSrc;
3399	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3400	if (!pPDSrc)
3401	return VINF_SUCCESS; /* not present */
3402	# endif
3403	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3404	# else
3405	PGSTPD pPDSrc = NULL;
3406	const unsigned iPDSrc = 0;
3407	GSTPDE PdeSrc;
3408
3409	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3410	PdeSrc.n.u1Present = 1;
3411	PdeSrc.n.u1Write = 1;
3412	PdeSrc.n.u1Accessed = 1;
3413	PdeSrc.n.u1User = 1;
3414	# endif
3415
3416	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3417	{
3418	PVM pVM = pVCpu->CTX_SUFF(pVM);
3419	pgmLock(pVM);
3420
3421	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3422	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3423	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3424	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3425	PX86PDPAE pPDDst;
3426	X86PDEPAE PdeDst;
3427	# if PGM_GST_TYPE != PGM_TYPE_PAE
3428	X86PDPE PdpeSrc;
3429
3430	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3431	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3432	# endif
3433	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3434	if (rc != VINF_SUCCESS)
3435	{
3436	pgmUnlock(pVM);
3437	AssertRC(rc);
3438	return rc;
3439	}
3440	Assert(pPDDst);
3441	PdeDst = pPDDst->a[iPDDst];
3442
3443	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3444	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3445	PX86PDPAE pPDDst;
3446	X86PDEPAE PdeDst;
3447
3448	# if PGM_GST_TYPE == PGM_TYPE_PROT
3449	/* AMD-V nested paging */
3450	X86PML4E Pml4eSrc;
3451	X86PDPE PdpeSrc;
3452	PX86PML4E pPml4eSrc = &Pml4eSrc;
3453
3454	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3455	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3456	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3457	# endif
3458
3459	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3460	if (rc != VINF_SUCCESS)
3461	{
3462	pgmUnlock(pVM);
3463	AssertRC(rc);
3464	return rc;
3465	}
3466	Assert(pPDDst);
3467	PdeDst = pPDDst->a[iPDDst];
3468	# endif
3469	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3470	{
3471	if (!PdeDst.n.u1Present)
3472	{
3473	/** @todo r=bird: This guy will set the A bit on the PDE,
3474	* probably harmless. */
3475	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3476	}
3477	else
3478	{
3479	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3480	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3481	* makes no sense to prefetch more than one page.
3482	*/
3483	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3484	if (RT_SUCCESS(rc))
3485	rc = VINF_SUCCESS;
3486	}
3487	}
3488	pgmUnlock(pVM);
3489	}
3490	return rc;
3491
3492	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3493	NOREF(pVCpu); NOREF(GCPtrPage);
3494	return VINF_SUCCESS; /* ignore */
3495	#else
3496	AssertCompile(0);
3497	#endif
3498	}
3499
3500
3501
3502
3503	/**
3504	* Syncs a page during a PGMVerifyAccess() call.
3505	*
3506	* @returns VBox status code (informational included).
3507	* @param pVCpu The cross context virtual CPU structure.
3508	* @param GCPtrPage The address of the page to sync.
3509	* @param fPage The effective guest page flags.
3510	* @param uErr The trap error code.
3511	* @remarks This will normally never be called on invalid guest page
3512	* translation entries.
3513	*/
3514	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3515	{
3516	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3517
3518	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3519	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3520
3521	Assert(!pVM->pgm.s.fNestedPaging);
3522	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3523	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3524	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3525	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3526	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3527	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3528	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3529
3530	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3531	if (!(fPage & X86_PTE_US))
3532	{
3533	/*
3534	* Mark this page as safe.
3535	*/
3536	/** @todo not correct for pages that contain both code and data!! */
3537	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3538	CSAMMarkPage(pVM, GCPtrPage, true);
3539	}
3540	# endif
3541
3542	/*
3543	* Get guest PD and index.
3544	*/
3545	/** @todo Performance: We've done all this a jiffy ago in the
3546	* PGMGstGetPage call. */
3547	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3548	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3549	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3550	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3551
3552	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3553	unsigned iPDSrc = 0;
3554	X86PDPE PdpeSrc;
3555	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3556	if (RT_UNLIKELY(!pPDSrc))
3557	{
3558	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3559	return VINF_EM_RAW_GUEST_TRAP;
3560	}
3561
3562	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3563	unsigned iPDSrc = 0; /* shut up gcc */
3564	PX86PML4E pPml4eSrc = NULL; /* ditto */
3565	X86PDPE PdpeSrc;
3566	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3567	if (RT_UNLIKELY(!pPDSrc))
3568	{
3569	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3570	return VINF_EM_RAW_GUEST_TRAP;
3571	}
3572	# endif
3573
3574	# else /* !PGM_WITH_PAGING */
3575	PGSTPD pPDSrc = NULL;
3576	const unsigned iPDSrc = 0;
3577	# endif /* !PGM_WITH_PAGING */
3578	int rc = VINF_SUCCESS;
3579
3580	pgmLock(pVM);
3581
3582	/*
3583	* First check if the shadow pd is present.
3584	*/
3585	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3586	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3587
3588	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3589	PX86PDEPAE pPdeDst;
3590	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3591	PX86PDPAE pPDDst;
3592	# if PGM_GST_TYPE != PGM_TYPE_PAE
3593	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3594	X86PDPE PdpeSrc;
3595	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3596	# endif
3597	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3598	if (rc != VINF_SUCCESS)
3599	{
3600	pgmUnlock(pVM);
3601	AssertRC(rc);
3602	return rc;
3603	}
3604	Assert(pPDDst);
3605	pPdeDst = &pPDDst->a[iPDDst];
3606
3607	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3608	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3609	PX86PDPAE pPDDst;
3610	PX86PDEPAE pPdeDst;
3611
3612	# if PGM_GST_TYPE == PGM_TYPE_PROT
3613	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3614	X86PML4E Pml4eSrc;
3615	X86PDPE PdpeSrc;
3616	PX86PML4E pPml4eSrc = &Pml4eSrc;
3617	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3618	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3619	# endif
3620
3621	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3622	if (rc != VINF_SUCCESS)
3623	{
3624	pgmUnlock(pVM);
3625	AssertRC(rc);
3626	return rc;
3627	}
3628	Assert(pPDDst);
3629	pPdeDst = &pPDDst->a[iPDDst];
3630	# endif
3631
3632	if (!pPdeDst->n.u1Present)
3633	{
3634	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3635	if (rc != VINF_SUCCESS)
3636	{
3637	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3638	pgmUnlock(pVM);
3639	AssertRC(rc);
3640	return rc;
3641	}
3642	}
3643
3644	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3645	/* Check for dirty bit fault */
3646	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3647	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3648	Log(("PGMVerifyAccess: success (dirty)\n"));
3649	else
3650	# endif
3651	{
3652	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3653	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3654	# else
3655	GSTPDE PdeSrc;
3656	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3657	PdeSrc.n.u1Present = 1;
3658	PdeSrc.n.u1Write = 1;
3659	PdeSrc.n.u1Accessed = 1;
3660	PdeSrc.n.u1User = 1;
3661	# endif
3662
3663	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3664	if (uErr & X86_TRAP_PF_US)
3665	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3666	else /* supervisor */
3667	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3668
3669	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3670	if (RT_SUCCESS(rc))
3671	{
3672	/* Page was successfully synced */
3673	Log2(("PGMVerifyAccess: success (sync)\n"));
3674	rc = VINF_SUCCESS;
3675	}
3676	else
3677	{
3678	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3679	rc = VINF_EM_RAW_GUEST_TRAP;
3680	}
3681	}
3682	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3683	pgmUnlock(pVM);
3684	return rc;
3685
3686	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3687
3688	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3689	return VERR_PGM_NOT_USED_IN_MODE;
3690	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3691	}
3692
3693
3694	/**
3695	* Syncs the paging hierarchy starting at CR3.
3696	*
3697	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
3698	* informational status codes.
3699	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
3700	* the VMM into guest context.
3701	* @param pVCpu The cross context virtual CPU structure.
3702	* @param cr0 Guest context CR0 register.
3703	* @param cr3 Guest context CR3 register. Not subjected to the A20
3704	* mask.
3705	* @param cr4 Guest context CR4 register.
3706	* @param fGlobal Including global page directories or not
3707	*/
3708	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3709	{
3710	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3711	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3712
3713	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3714
3715	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3716
3717	pgmLock(pVM);
3718
3719	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3720	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3721	if (pPool->cDirtyPages)
3722	pgmPoolResetDirtyPages(pVM);
3723	# endif
3724
3725	/*
3726	* Update page access handlers.
3727	* The virtual are always flushed, while the physical are only on demand.
3728	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3729	* have to look into that later because it will have a bad influence on the performance.
3730	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3731	* bird: Yes, but that won't work for aliases.
3732	*/
3733	/** @todo this MUST go away. See @bugref{1557}. */
3734	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3735	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3736	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3737	pgmUnlock(pVM);
3738	#endif /* !NESTED && !EPT */
3739
3740	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3741	/*
3742	* Nested / EPT - almost no work.
3743	*/
3744	Assert(!pgmMapAreMappingsEnabled(pVM));
3745	return VINF_SUCCESS;
3746
3747	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3748	/*
3749	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3750	* out the shadow parts when the guest modifies its tables.
3751	*/
3752	Assert(!pgmMapAreMappingsEnabled(pVM));
3753	return VINF_SUCCESS;
3754
3755	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3756
3757	# ifndef PGM_WITHOUT_MAPPINGS
3758	/*
3759	* Check for and resolve conflicts with our guest mappings if they
3760	* are enabled and not fixed.
3761	*/
3762	if (pgmMapAreMappingsFloating(pVM))
3763	{
3764	int rc = pgmMapResolveConflicts(pVM);
3765	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3766	if (rc == VINF_SUCCESS)
3767	{ /* likely */ }
3768	else if (rc == VINF_PGM_SYNC_CR3)
3769	{
3770	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3771	return VINF_PGM_SYNC_CR3;
3772	}
3773	else if (RT_FAILURE(rc))
3774	return rc;
3775	else
3776	AssertMsgFailed(("%Rrc\n", rc));
3777	}
3778	# else
3779	Assert(!pgmMapAreMappingsEnabled(pVM));
3780	# endif
3781	return VINF_SUCCESS;
3782	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3783	}
3784
3785
3786
3787
3788	#ifdef VBOX_STRICT
3789	# ifdef IN_RC
3790	# undef AssertMsgFailed
3791	# define AssertMsgFailed Log
3792	# endif
3793
3794	/**
3795	* Checks that the shadow page table is in sync with the guest one.
3796	*
3797	* @returns The number of errors.
3798	* @param pVCpu The cross context virtual CPU structure.
3799	* @param cr3 Guest context CR3 register.
3800	* @param cr4 Guest context CR4 register.
3801	* @param GCPtr Where to start. Defaults to 0.
3802	* @param cb How much to check. Defaults to everything.
3803	*/
3804	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3805	{
3806	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3807	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3808	return 0;
3809	#else
3810	unsigned cErrors = 0;
3811	PVM pVM = pVCpu->CTX_SUFF(pVM);
3812	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3813
3814	# if PGM_GST_TYPE == PGM_TYPE_PAE
3815	/** @todo currently broken; crashes below somewhere */
3816	AssertFailed();
3817	# endif
3818
3819	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3820	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3821	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3822
3823	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3824	PPGMCPU pPGM = &pVCpu->pgm.s;
3825	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3826	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3827	# ifndef IN_RING0
3828	RTHCPHYS HCPhys; /* general usage. */
3829	# endif
3830	int rc;
3831
3832	/*
3833	* Check that the Guest CR3 and all its mappings are correct.
3834	*/
3835	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3836	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3837	false);
3838	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3839	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3840	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3841	# else
3842	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3843	# endif
3844	AssertRCReturn(rc, 1);
3845	HCPhys = NIL_RTHCPHYS;
3846	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3847	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3848	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3849	pgmGstGet32bitPDPtr(pVCpu);
3850	RTGCPHYS GCPhys;
3851	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3852	AssertRCReturn(rc, 1);
3853	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3854	# endif
3855	# endif /* !IN_RING0 */
3856
3857	/*
3858	* Get and check the Shadow CR3.
3859	*/
3860	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3861	unsigned cPDEs = X86_PG_ENTRIES;
3862	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3863	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3864	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3865	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3866	# else
3867	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3868	# endif
3869	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3870	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3871	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3872	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3873	# endif
3874	if (cb != ~(RTGCPTR)0)
3875	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3876
3877	/** @todo call the other two PGMAssert() functions. /
3878
3879	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3880	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3881
3882	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3883	{
3884	PPGMPOOLPAGE pShwPdpt = NULL;
3885	PX86PML4E pPml4eSrc;
3886	PX86PML4E pPml4eDst;
3887	RTGCPHYS GCPhysPdptSrc;
3888
3889	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3890	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3891
3892	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3893	if (!pPml4eDst->n.u1Present)
3894	{
3895	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3896	continue;
3897	}
3898
3899	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3900	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3901
3902	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3903	{
3904	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3905	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3906	cErrors++;
3907	continue;
3908	}
3909
3910	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3911	{
3912	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3913	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3914	cErrors++;
3915	continue;
3916	}
3917
3918	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3919	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3920	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3921	{
3922	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3923	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3924	cErrors++;
3925	continue;
3926	}
3927	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3928	{
3929	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3930
3931	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3932	/*
3933	* Check the PDPTEs too.
3934	*/
3935	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3936
3937	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3938	{
3939	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3940	PPGMPOOLPAGE pShwPde = NULL;
3941	PX86PDPE pPdpeDst;
3942	RTGCPHYS GCPhysPdeSrc;
3943	X86PDPE PdpeSrc;
3944	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3945	# if PGM_GST_TYPE == PGM_TYPE_PAE
3946	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3947	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3948	# else
3949	PX86PML4E pPml4eSrcIgn;
3950	PX86PDPT pPdptDst;
3951	PX86PDPAE pPDDst;
3952	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3953
3954	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3955	if (rc != VINF_SUCCESS)
3956	{
3957	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3958	GCPtr += 512 * _2M;
3959	continue; /* next PDPTE */
3960	}
3961	Assert(pPDDst);
3962	# endif
3963	Assert(iPDSrc == 0);
3964
3965	pPdpeDst = &pPdptDst->a[iPdpt];
3966
3967	if (!pPdpeDst->n.u1Present)
3968	{
3969	GCPtr += 512 * _2M;
3970	continue; /* next PDPTE */
3971	}
3972
3973	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3974	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3975
3976	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3977	{
3978	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3979	GCPtr += 512 * _2M;
3980	cErrors++;
3981	continue;
3982	}
3983
3984	if (GCPhysPdeSrc != pShwPde->GCPhys)
3985	{
3986	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3987	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3988	# else
3989	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
3990	# endif
3991	GCPtr += 512 * _2M;
3992	cErrors++;
3993	continue;
3994	}
3995
3996	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3997	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
3998	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
3999	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
4000	{
4001	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4002	GCPtr += 512 * _2M;
4003	cErrors++;
4004	continue;
4005	}
4006	# endif
4007
4008	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4009	{
4010	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4011	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4012	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4013	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4014	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4015	# endif
4016	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4017	/*
4018	* Iterate the shadow page directory.
4019	*/
4020	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4021	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4022
4023	for (;
4024	iPDDst < cPDEs;
4025	iPDDst++, GCPtr += cIncrement)
4026	{
4027	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4028	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4029	# else
4030	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4031	# endif
4032	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4033	{
4034	Assert(pgmMapAreMappingsEnabled(pVM));
4035	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4036	{
4037	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4038	cErrors++;
4039	continue;
4040	}
4041	}
4042	else if ( (PdeDst.u & X86_PDE_P)
4043	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4044	)
4045	{
4046	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4047	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4048	if (!pPoolPage)
4049	{
4050	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4051	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4052	cErrors++;
4053	continue;
4054	}
4055	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4056
4057	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4058	{
4059	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4060	GCPtr, (uint64_t)PdeDst.u));
4061	cErrors++;
4062	}
4063
4064	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4065	{
4066	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4067	GCPtr, (uint64_t)PdeDst.u));
4068	cErrors++;
4069	}
4070
4071	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4072	if (!PdeSrc.n.u1Present)
4073	{
4074	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4075	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4076	cErrors++;
4077	continue;
4078	}
4079
4080	if ( !PdeSrc.b.u1Size
4081	\|\| !fBigPagesSupported)
4082	{
4083	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4084	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4085	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4086	# endif
4087	}
4088	else
4089	{
4090	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4091	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4092	{
4093	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4094	GCPtr, (uint64_t)PdeSrc.u));
4095	cErrors++;
4096	continue;
4097	}
4098	# endif
4099	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4100	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4101	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4102	# endif
4103	}
4104
4105	if ( pPoolPage->enmKind
4106	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4107	{
4108	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4109	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4110	cErrors++;
4111	}
4112
4113	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4114	if (!pPhysPage)
4115	{
4116	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4117	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4118	cErrors++;
4119	continue;
4120	}
4121
4122	if (GCPhysGst != pPoolPage->GCPhys)
4123	{
4124	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4125	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4126	cErrors++;
4127	continue;
4128	}
4129
4130	if ( !PdeSrc.b.u1Size
4131	\|\| !fBigPagesSupported)
4132	{
4133	/*
4134	* Page Table.
4135	*/
4136	const GSTPT *pPTSrc;
4137	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4138	&pPTSrc);
4139	if (RT_FAILURE(rc))
4140	{
4141	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4142	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4143	cErrors++;
4144	continue;
4145	}
4146	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4147	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4148	{
4149	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4150	// (This problem will go away when/if we shadow multiple CR3s.)
4151	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4152	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4153	cErrors++;
4154	continue;
4155	}
4156	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4157	{
4158	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4159	GCPtr, (uint64_t)PdeDst.u));
4160	cErrors++;
4161	continue;
4162	}
4163
4164	/* iterate the page table. */
4165	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4166	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4167	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4168	# else
4169	const unsigned offPTSrc = 0;
4170	# endif
4171	for (unsigned iPT = 0, off = 0;
4172	iPT < RT_ELEMENTS(pPTDst->a);
4173	iPT++, off += PAGE_SIZE)
4174	{
4175	const SHWPTE PteDst = pPTDst->a[iPT];
4176
4177	/* skip not-present and dirty tracked entries. */
4178	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4179	continue;
4180	Assert(SHW_PTE_IS_P(PteDst));
4181
4182	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4183	if (!PteSrc.n.u1Present)
4184	{
4185	# ifdef IN_RING3
4186	PGMAssertHandlerAndFlagsInSync(pVM);
4187	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4188	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4189	0, 0, UINT64_MAX, 99, NULL);
4190	# endif
4191	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4192	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4193	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4194	cErrors++;
4195	continue;
4196	}
4197
4198	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4199	# if 1 /** @todo sync accessed bit properly... */
4200	fIgnoreFlags \|= X86_PTE_A;
4201	# endif
4202
4203	/* match the physical addresses */
4204	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4205	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4206
4207	# ifdef IN_RING3
4208	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4209	if (RT_FAILURE(rc))
4210	{
4211	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4212	{
4213	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4214	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4215	cErrors++;
4216	continue;
4217	}
4218	}
4219	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4220	{
4221	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4222	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4223	cErrors++;
4224	continue;
4225	}
4226	# endif
4227
4228	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4229	if (!pPhysPage)
4230	{
4231	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4232	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4233	{
4234	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4235	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4236	cErrors++;
4237	continue;
4238	}
4239	# endif
4240	if (SHW_PTE_IS_RW(PteDst))
4241	{
4242	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4243	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4244	cErrors++;
4245	}
4246	fIgnoreFlags \|= X86_PTE_RW;
4247	}
4248	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4249	{
4250	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4251	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4252	cErrors++;
4253	continue;
4254	}
4255
4256	/* flags */
4257	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4258	{
4259	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4260	{
4261	if (SHW_PTE_IS_RW(PteDst))
4262	{
4263	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4264	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4265	cErrors++;
4266	continue;
4267	}
4268	fIgnoreFlags \|= X86_PTE_RW;
4269	}
4270	else
4271	{
4272	if ( SHW_PTE_IS_P(PteDst)
4273	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4274	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4275	# endif
4276	)
4277	{
4278	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4279	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4280	cErrors++;
4281	continue;
4282	}
4283	fIgnoreFlags \|= X86_PTE_P;
4284	}
4285	}
4286	else
4287	{
4288	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4289	{
4290	if (SHW_PTE_IS_RW(PteDst))
4291	{
4292	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4293	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4294	cErrors++;
4295	continue;
4296	}
4297	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4298	{
4299	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4300	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4301	cErrors++;
4302	continue;
4303	}
4304	if (SHW_PTE_IS_D(PteDst))
4305	{
4306	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4307	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4308	cErrors++;
4309	}
4310	# if 0 /** @todo sync access bit properly... */
4311	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4312	{
4313	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4314	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4315	cErrors++;
4316	}
4317	fIgnoreFlags \|= X86_PTE_RW;
4318	# else
4319	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4320	# endif
4321	}
4322	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4323	{
4324	/* access bit emulation (not implemented). */
4325	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4326	{
4327	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4328	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4329	cErrors++;
4330	continue;
4331	}
4332	if (!SHW_PTE_IS_A(PteDst))
4333	{
4334	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4335	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4336	cErrors++;
4337	}
4338	fIgnoreFlags \|= X86_PTE_P;
4339	}
4340	# ifdef DEBUG_sandervl
4341	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4342	# endif
4343	}
4344
4345	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4346	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4347	)
4348	{
4349	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4350	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4351	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4352	cErrors++;
4353	continue;
4354	}
4355	} /* foreach PTE */
4356	}
4357	else
4358	{
4359	/*
4360	* Big Page.
4361	*/
4362	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4363	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4364	{
4365	if (PdeDst.n.u1Write)
4366	{
4367	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4368	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4369	cErrors++;
4370	continue;
4371	}
4372	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4373	{
4374	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4375	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4376	cErrors++;
4377	continue;
4378	}
4379	# if 0 /** @todo sync access bit properly... */
4380	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4381	{
4382	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4383	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4384	cErrors++;
4385	}
4386	fIgnoreFlags \|= X86_PTE_RW;
4387	# else
4388	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4389	# endif
4390	}
4391	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4392	{
4393	/* access bit emulation (not implemented). */
4394	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4395	{
4396	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4397	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4398	cErrors++;
4399	continue;
4400	}
4401	if (!PdeDst.n.u1Accessed)
4402	{
4403	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4404	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4405	cErrors++;
4406	}
4407	fIgnoreFlags \|= X86_PTE_P;
4408	}
4409
4410	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4411	{
4412	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4413	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4414	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4415	cErrors++;
4416	}
4417
4418	/* iterate the page table. */
4419	for (unsigned iPT = 0, off = 0;
4420	iPT < RT_ELEMENTS(pPTDst->a);
4421	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4422	{
4423	const SHWPTE PteDst = pPTDst->a[iPT];
4424
4425	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4426	{
4427	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4428	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4429	cErrors++;
4430	}
4431
4432	/* skip not-present entries. */
4433	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4434	continue;
4435
4436	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4437
4438	/* match the physical addresses */
4439	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4440
4441	# ifdef IN_RING3
4442	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4443	if (RT_FAILURE(rc))
4444	{
4445	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4446	{
4447	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4448	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4449	cErrors++;
4450	}
4451	}
4452	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4453	{
4454	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4455	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4456	cErrors++;
4457	continue;
4458	}
4459	# endif
4460	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4461	if (!pPhysPage)
4462	{
4463	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4464	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4465	{
4466	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4467	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4468	cErrors++;
4469	continue;
4470	}
4471	# endif
4472	if (SHW_PTE_IS_RW(PteDst))
4473	{
4474	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4475	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4476	cErrors++;
4477	}
4478	fIgnoreFlags \|= X86_PTE_RW;
4479	}
4480	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4481	{
4482	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4483	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4484	cErrors++;
4485	continue;
4486	}
4487
4488	/* flags */
4489	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4490	{
4491	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4492	{
4493	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4494	{
4495	if (SHW_PTE_IS_RW(PteDst))
4496	{
4497	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4498	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4499	cErrors++;
4500	continue;
4501	}
4502	fIgnoreFlags \|= X86_PTE_RW;
4503	}
4504	}
4505	else
4506	{
4507	if ( SHW_PTE_IS_P(PteDst)
4508	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4509	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4510	# endif
4511	)
4512	{
4513	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4514	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4515	cErrors++;
4516	continue;
4517	}
4518	fIgnoreFlags \|= X86_PTE_P;
4519	}
4520	}
4521
4522	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4523	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4524	)
4525	{
4526	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4527	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4528	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4529	cErrors++;
4530	continue;
4531	}
4532	} /* for each PTE */
4533	}
4534	}
4535	/* not present */
4536
4537	} /* for each PDE */
4538
4539	} /* for each PDPTE */
4540
4541	} /* for each PML4E */
4542
4543	# ifdef DEBUG
4544	if (cErrors)
4545	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4546	# endif
4547	# endif /* GST is in {32BIT, PAE, AMD64} */
4548	return cErrors;
4549	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4550	}
4551	#endif /* VBOX_STRICT */
4552
4553
4554	/**
4555	* Sets up the CR3 for shadow paging
4556	*
4557	* @returns Strict VBox status code.
4558	* @retval VINF_SUCCESS.
4559	*
4560	* @param pVCpu The cross context virtual CPU structure.
4561	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4562	* mask already applied.)
4563	*/
4564	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4565	{
4566	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4567
4568	/* Update guest paging info. */
4569	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4570	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4571	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4572
4573	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4574	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4575
4576	/*
4577	* Map the page CR3 points at.
4578	*/
4579	RTHCPTR HCPtrGuestCR3;
4580	RTHCPHYS HCPhysGuestCR3;
4581	pgmLock(pVM);
4582	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4583	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4584	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4585	/** @todo this needs some reworking wrt. locking? */
4586	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4587	HCPtrGuestCR3 = NIL_RTHCPTR;
4588	int rc = VINF_SUCCESS;
4589	# else
4590	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4591	# endif
4592	pgmUnlock(pVM);
4593	if (RT_SUCCESS(rc))
4594	{
4595	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4596	if (RT_SUCCESS(rc))
4597	{
4598	# ifdef IN_RC
4599	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4600	# endif
4601	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4602	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4603	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4604	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4605	# endif
4606	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4607
4608	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4609	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4610	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4611	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4612	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4613	# endif
4614	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4615	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4616
4617	/*
4618	* Map the 4 PDs too.
4619	*/
4620	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4621	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4622	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4623	{
4624	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4625	if (pGuestPDPT->a[i].n.u1Present)
4626	{
4627	RTHCPTR HCPtr;
4628	RTHCPHYS HCPhys;
4629	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4630	pgmLock(pVM);
4631	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4632	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4633	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4634	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4635	HCPtr = NIL_RTHCPTR;
4636	int rc2 = VINF_SUCCESS;
4637	# else
4638	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4639	# endif
4640	pgmUnlock(pVM);
4641	if (RT_SUCCESS(rc2))
4642	{
4643	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4644	AssertRCReturn(rc, rc);
4645
4646	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4647	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4648	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4649	# endif
4650	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4651	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4652	# ifdef IN_RC
4653	PGM_INVL_PG(pVCpu, GCPtr);
4654	# endif
4655	continue;
4656	}
4657	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4658	}
4659
4660	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4661	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4662	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4663	# endif
4664	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4665	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4666	# ifdef IN_RC
4667	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4668	# endif
4669	}
4670
4671	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4672	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4673	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4674	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4675	# endif
4676	# endif
4677	}
4678	else
4679	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4680	}
4681	else
4682	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4683
4684	#else /* prot/real stub */
4685	int rc = VINF_SUCCESS;
4686	#endif
4687
4688	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4689	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4690	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4691	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4692	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4693	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4694
4695	Assert(!pVM->pgm.s.fNestedPaging);
4696	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4697
4698	/*
4699	* Update the shadow root page as well since that's not fixed.
4700	*/
4701	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4702	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4703	PPGMPOOLPAGE pNewShwPageCR3;
4704
4705	pgmLock(pVM);
4706
4707	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4708	if (pPool->cDirtyPages)
4709	pgmPoolResetDirtyPages(pVM);
4710	# endif
4711
4712	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4713	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4714	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4715	&pNewShwPageCR3);
4716	AssertFatalRC(rc);
4717	rc = VINF_SUCCESS;
4718
4719	# ifdef IN_RC
4720	/*
4721	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4722	* state will be inconsistent! Flush important things now while
4723	* we still can and then make sure there are no ring-3 calls.
4724	*/
4725	# ifdef VBOX_WITH_REM
4726	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4727	# endif
4728	VMMRZCallRing3Disable(pVCpu);
4729	# endif
4730
4731	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4732	# ifdef IN_RING0
4733	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4734	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4735	# elif defined(IN_RC)
4736	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4737	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4738	# else
4739	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4740	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4741	# endif
4742
4743	# ifndef PGM_WITHOUT_MAPPINGS
4744	/*
4745	* Apply all hypervisor mappings to the new CR3.
4746	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4747	* make sure we check for conflicts in the new CR3 root.
4748	*/
4749	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4750	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4751	# endif
4752	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4753	AssertRCReturn(rc, rc);
4754	# endif
4755
4756	/* Set the current hypervisor CR3. */
4757	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4758	SELMShadowCR3Changed(pVM, pVCpu);
4759
4760	# ifdef IN_RC
4761	/* NOTE: The state is consistent again. */
4762	VMMRZCallRing3Enable(pVCpu);
4763	# endif
4764
4765	/* Clean up the old CR3 root. */
4766	if ( pOldShwPageCR3
4767	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4768	{
4769	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4770	# ifndef PGM_WITHOUT_MAPPINGS
4771	/* Remove the hypervisor mappings from the shadow page table. */
4772	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4773	# endif
4774	/* Mark the page as unlocked; allow flushing again. */
4775	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4776
4777	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4778	}
4779	pgmUnlock(pVM);
4780	# else
4781	NOREF(GCPhysCR3);
4782	# endif
4783
4784	return rc;
4785	}
4786
4787	/**
4788	* Unmaps the shadow CR3.
4789	*
4790	* @returns VBox status, no specials.
4791	* @param pVCpu The cross context virtual CPU structure.
4792	*/
4793	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4794	{
4795	LogFlow(("UnmapCR3\n"));
4796
4797	int rc = VINF_SUCCESS;
4798	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4799
4800	/*
4801	* Update guest paging info.
4802	*/
4803	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4804	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4805	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4806	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4807	# endif
4808	pVCpu->pgm.s.pGst32BitPdRC = 0;
4809
4810	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4811	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4812	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4813	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4814	# endif
4815	pVCpu->pgm.s.pGstPaePdptRC = 0;
4816	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4817	{
4818	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4819	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4820	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4821	# endif
4822	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4823	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4824	}
4825
4826	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4827	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4828	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4829	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4830	# endif
4831
4832	#else /* prot/real mode stub */
4833	/* nothing to do */
4834	#endif
4835
4836	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4837	/*
4838	* Update shadow paging info.
4839	*/
4840	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4841	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4842	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4843
4844	# if PGM_GST_TYPE != PGM_TYPE_REAL
4845	Assert(!pVM->pgm.s.fNestedPaging);
4846	# endif
4847
4848	pgmLock(pVM);
4849
4850	# ifndef PGM_WITHOUT_MAPPINGS
4851	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4852	/* Remove the hypervisor mappings from the shadow page table. */
4853	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4854	# endif
4855
4856	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4857	{
4858	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4859
4860	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4861	if (pPool->cDirtyPages)
4862	pgmPoolResetDirtyPages(pVM);
4863	# endif
4864
4865	/* Mark the page as unlocked; allow flushing again. */
4866	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4867
4868	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4869	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4870	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4871	pVCpu->pgm.s.pShwPageCR3RC = 0;
4872	}
4873	pgmUnlock(pVM);
4874	# endif
4875	#endif /* !IN_RC*/
4876
4877	return rc;
4878	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 65398

Download in other formats: