PGMAllBth.h@ 65452

Last change on this file since 65452 was 65452, checked in by vboxsync, 8 years ago

PGMAllBth.h: InvalidatePage: Skip if pgmShwGet32BitPDEPtr or pgmShwGetPaePDPTPtr returns NULL. bugref:8509

Looks like it's possible for REM to executing without triggering the MapCR3 code.

Property svn:eol-style set to native
Property svn:keywords set to Id

File size: 213.6 KB

Line
1	/* $Id: PGMAllBth.h 65452 2017-01-26 12:45:16Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* @remarks The nested page tables on AMD makes use of PGM_SHW_TYPE in
6	* {PGM_TYPE_AMD64, PGM_TYPE_PAE and PGM_TYPE_32BIT} and PGM_GST_TYPE
7	* set to PGM_TYPE_PROT. Half of the code in this file is not
8	* exercised with PGM_SHW_TYPE set to PGM_TYPE_NESTED.
9	*
10	* @remarks Extended page tables (intel) are built with PGM_GST_TYPE set to
11	* PGM_TYPE_PROT (and PGM_SHW_TYPE set to PGM_TYPE_EPT).
12	*
13	* @remarks This file is one big \#ifdef-orgy!
14	*
15	*/
16
17	/*
18	* Copyright (C) 2006-2016 Oracle Corporation
19	*
20	* This file is part of VirtualBox Open Source Edition (OSE), as
21	* available from http://www.virtualbox.org. This file is free software;
22	* you can redistribute it and/or modify it under the terms of the GNU
23	* General Public License (GPL) as published by the Free Software
24	* Foundation, in version 2 as it comes in the "COPYING" file of the
25	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
26	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
27	*/
28
29	#ifdef _MSC_VER
30	/** @todo we're generating unnecessary code in nested/ept shadow mode and for
31	* real/prot-guest+RC mode. */
32	# pragma warning(disable: 4505)
33	#endif
34
35	/*******************************************************************************
36	* Internal Functions *
37	*******************************************************************************/
38	RT_C_DECLS_BEGIN
39	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
40	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
41	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr);
42	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc, RTGCPTR GCPtrPage);
43	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPD, PGSTPD pPDSrc, RTGCPTR GCPtrPage);
44	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
45	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
46	# else
47	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage, PPGMPOOLPAGE pShwPage, unsigned iPTDst);
48	#endif
49	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR Addr, unsigned fPage, unsigned uErr);
50	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
51	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
52	#ifdef VBOX_STRICT
53	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr = 0, RTGCPTR cb = ~(RTGCPTR)0);
54	#endif
55	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
56	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu);
57	RT_C_DECLS_END
58
59
60	/*
61	* Filter out some illegal combinations of guest and shadow paging, so we can
62	* remove redundant checks inside functions.
63	*/
64	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
65	# error "Invalid combination; PAE guest implies PAE shadow"
66	#endif
67
68	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
69	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
70	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
71	#endif
72
73	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
74	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT)
75	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
76	#endif
77
78	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT) \
79	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
80	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
81	#endif
82
83	#ifndef IN_RING3
84
85	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
86	/**
87	* Deal with a guest page fault.
88	*
89	* @returns Strict VBox status code.
90	* @retval VINF_EM_RAW_GUEST_TRAP
91	* @retval VINF_EM_RAW_EMULATE_INSTR
92	*
93	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
94	* @param pGstWalk The guest page table walk result.
95	* @param uErr The error code.
96	*/
97	PGM_BTH_DECL(VBOXSTRICTRC, Trap0eHandlerGuestFault)(PVMCPU pVCpu, PGSTPTWALK pGstWalk, RTGCUINT uErr)
98	{
99	# if !defined(PGM_WITHOUT_MAPPINGS) && (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE)
100	/*
101	* Check for write conflicts with our hypervisor mapping.
102	*
103	* If the guest happens to access a non-present page, where our hypervisor
104	* is currently mapped, then we'll create a #PF storm in the guest.
105	*/
106	if ( (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW)
107	&& pgmMapAreMappingsEnabled(pVCpu->CTX_SUFF(pVM))
108	&& MMHyperIsInsideArea(pVCpu->CTX_SUFF(pVM), pGstWalk->Core.GCPtr))
109	{
110	/* Force a CR3 sync to check for conflicts and emulate the instruction. */
111	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
112	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
113	return VINF_EM_RAW_EMULATE_INSTR;
114	}
115	# endif
116
117	/*
118	* Calc the error code for the guest trap.
119	*/
120	uint32_t uNewErr = GST_IS_NX_ACTIVE(pVCpu)
121	? uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID)
122	: uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US);
123	if ( pGstWalk->Core.fRsvdError
124	\|\| pGstWalk->Core.fBadPhysAddr)
125	{
126	uNewErr \|= X86_TRAP_PF_RSVD \| X86_TRAP_PF_P;
127	Assert(!pGstWalk->Core.fNotPresent);
128	}
129	else if (!pGstWalk->Core.fNotPresent)
130	uNewErr \|= X86_TRAP_PF_P;
131	TRPMSetErrorCode(pVCpu, uNewErr);
132
133	LogFlow(("Guest trap; cr2=%RGv uErr=%RGv lvl=%d\n", pGstWalk->Core.GCPtr, uErr, pGstWalk->Core.uLevel));
134	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
135	return VINF_EM_RAW_GUEST_TRAP;
136	}
137	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
138
139
140	/**
141	* Deal with a guest page fault.
142	*
143	* The caller has taken the PGM lock.
144	*
145	* @returns Strict VBox status code.
146	*
147	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
148	* @param uErr The error code.
149	* @param pRegFrame The register frame.
150	* @param pvFault The fault address.
151	* @param pPage The guest page at @a pvFault.
152	* @param pGstWalk The guest page table walk result.
153	* @param pfLockTaken PGM lock taken here or not (out). This is true
154	* when we're called.
155	*/
156	static VBOXSTRICTRC PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame,
157	RTGCPTR pvFault, PPGMPAGE pPage, bool *pfLockTaken
158	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
159	, PGSTPTWALK pGstWalk
160	# endif
161	)
162	{
163	# if !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
164	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A };
165	#endif
166	PVM pVM = pVCpu->CTX_SUFF(pVM);
167	VBOXSTRICTRC rcStrict;
168
169	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
170	{
171	/*
172	* Physical page access handler.
173	*/
174	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
175	const RTGCPHYS GCPhysFault = pGstWalk->Core.GCPhys;
176	# else
177	const RTGCPHYS GCPhysFault = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault);
178	# endif
179	PPGMPHYSHANDLER pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
180	if (pCur)
181	{
182	PPGMPHYSHANDLERTYPEINT pCurType = PGMPHYSHANDLER_GET_TYPE(pVM, pCur);
183
184	# ifdef PGM_SYNC_N_PAGES
185	/*
186	* If the region is write protected and we got a page not present fault, then sync
187	* the pages. If the fault was caused by a read, then restart the instruction.
188	* In case of write access continue to the GC write handler.
189	*
190	* ASSUMES that there is only one handler per page or that they have similar write properties.
191	*/
192	if ( !(uErr & X86_TRAP_PF_P)
193	&& pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
194	{
195	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
196	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
197	# else
198	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
199	# endif
200	if ( RT_FAILURE(rcStrict)
201	\|\| !(uErr & X86_TRAP_PF_RW)
202	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
203	{
204	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
205	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
206	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
207	return rcStrict;
208	}
209	}
210	# endif
211	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
212	/*
213	* If the access was not thru a #PF(RSVD\|...) resync the page.
214	*/
215	if ( !(uErr & X86_TRAP_PF_RSVD)
216	&& pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
217	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
218	&& pGstWalk->Core.fEffectiveRW
219	&& !pGstWalk->Core.fEffectiveUS /** @todo Remove pGstWalk->Core.fEffectiveUS and X86_PTE_US further down in the sync code. */
220	# endif
221	)
222	{
223	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
224	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
225	# else
226	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
227	# endif
228	if ( RT_FAILURE(rcStrict)
229	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
230	{
231	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
232	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
233	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
234	return rcStrict;
235	}
236	}
237	# endif
238
239	AssertMsg( pCurType->enmKind != PGMPHYSHANDLERKIND_WRITE
240	\|\| (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW)),
241	("Unexpected trap for physical handler: %08X (phys=%08x) pPage=%R[pgmpage] uErr=%X, enmKind=%d\n",
242	pvFault, GCPhysFault, pPage, uErr, pCurType->enmKind));
243	if (pCurType->enmKind == PGMPHYSHANDLERKIND_WRITE)
244	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysWrite);
245	else
246	{
247	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAll);
248	if (uErr & X86_TRAP_PF_RSVD) STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersPhysAllOpt);
249	}
250
251	if (pCurType->CTX_SUFF(pfnPfHandler))
252	{
253	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
254	void *pvUser = pCur->CTX_SUFF(pvUser);
255
256	STAM_PROFILE_START(&pCur->Stat, h);
257	if (pCur->hType != pPool->hAccessHandlerType)
258	{
259	pgmUnlock(pVM);
260	*pfLockTaken = false;
261	}
262
263	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPhysFault, pvUser);
264
265	# ifdef VBOX_WITH_STATISTICS
266	pgmLock(pVM);
267	pCur = pgmHandlerPhysicalLookup(pVM, GCPhysFault);
268	if (pCur)
269	STAM_PROFILE_STOP(&pCur->Stat, h);
270	pgmUnlock(pVM);
271	# endif
272	}
273	else
274	rcStrict = VINF_EM_RAW_EMULATE_INSTR;
275
276	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndPhys; });
277	return rcStrict;
278	}
279	}
280	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
281	else
282	{
283	# ifdef PGM_SYNC_N_PAGES
284	/*
285	* If the region is write protected and we got a page not present fault, then sync
286	* the pages. If the fault was caused by a read, then restart the instruction.
287	* In case of write access continue to the GC write handler.
288	*/
289	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
290	&& !(uErr & X86_TRAP_PF_P))
291	{
292	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
293	if ( RT_FAILURE(rcStrict)
294	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
295	\|\| !(uErr & X86_TRAP_PF_RW))
296	{
297	AssertRC(rcStrict);
298	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
299	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndVirt; });
300	return rcStrict;
301	}
302	}
303	# endif
304	/*
305	* Ok, it's an virtual page access handler.
306	*
307	* Since it's faster to search by address, we'll do that first
308	* and then retry by GCPhys if that fails.
309	*/
310	/** @todo r=bird: perhaps we should consider looking up by physical address directly now?
311	* r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be
312	* out of sync, because the page was changed without us noticing it (not-present -> present
313	* without invlpg or mov cr3, xxx).
314	*/
315	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
316	if (pCur)
317	{
318	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
319	AssertMsg(!(pvFault - pCur->Core.Key < pCur->cb)
320	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
321	\|\| !(uErr & X86_TRAP_PF_P)
322	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
323	("Unexpected trap for virtual handler: %RGv (phys=%RGp) pPage=%R[pgmpage] uErr=%X, enumKind=%d\n",
324	pvFault, pGstWalk->Core.GCPhys, pPage, uErr, pCurType->enmKind));
325
326	if ( pvFault - pCur->Core.Key < pCur->cb
327	&& ( uErr & X86_TRAP_PF_RW
328	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
329	{
330	# ifdef IN_RC
331	STAM_PROFILE_START(&pCur->Stat, h);
332	RTGCPTR GCPtrStart = pCur->Core.Key;
333	void *pvUser = pCur->CTX_SUFF(pvUser);
334	pgmUnlock(pVM);
335	*pfLockTaken = false;
336
337	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart,
338	pvFault - GCPtrStart, pvUser);
339
340	# ifdef VBOX_WITH_STATISTICS
341	pgmLock(pVM);
342	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
343	if (pCur)
344	STAM_PROFILE_STOP(&pCur->Stat, h);
345	pgmUnlock(pVM);
346	# endif
347	# else
348	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
349	# endif
350	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtual);
351	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
352	return rcStrict;
353	}
354	/* Unhandled part of a monitored page */
355	Log(("Unhandled part of monitored page %RGv\n", pvFault));
356	}
357	else
358	{
359	/* Check by physical address. */
360	unsigned iPage;
361	pCur = pgmHandlerVirtualFindByPhysAddr(pVM, pGstWalk->Core.GCPhys, &iPage);
362	if (pCur)
363	{
364	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
365	if ( uErr & X86_TRAP_PF_RW
366	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE )
367	{
368	Assert( (pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK)
369	== (pGstWalk->Core.GCPhys & X86_PTE_PAE_PG_MASK));
370	# ifdef IN_RC
371	STAM_PROFILE_START(&pCur->Stat, h);
372	RTGCPTR GCPtrStart = pCur->Core.Key;
373	void *pvUser = pCur->CTX_SUFF(pvUser);
374	pgmUnlock(pVM);
375	*pfLockTaken = false;
376
377	RTGCPTR off = (iPage << PAGE_SHIFT)
378	+ (pvFault & PAGE_OFFSET_MASK)
379	- (GCPtrStart & PAGE_OFFSET_MASK);
380	Assert(off < pCur->cb);
381	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, GCPtrStart, off, pvUser);
382
383	# ifdef VBOX_WITH_STATISTICS
384	pgmLock(pVM);
385	pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, GCPtrStart);
386	if (pCur)
387	STAM_PROFILE_STOP(&pCur->Stat, h);
388	pgmUnlock(pVM);
389	# endif
390	# else
391	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
392	# endif
393	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersVirtualByPhys);
394	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
395	return rcStrict;
396	}
397	}
398	}
399	}
400	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
401
402	/*
403	* There is a handled area of the page, but this fault doesn't belong to it.
404	* We must emulate the instruction.
405	*
406	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
407	* we first check if this was a page-not-present fault for a page with only
408	* write access handlers. Restart the instruction if it wasn't a write access.
409	*/
410	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersUnhandled);
411
412	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
413	&& !(uErr & X86_TRAP_PF_P))
414	{
415	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
416	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, pGstWalk->Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
417	# else
418	rcStrict = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
419	# endif
420	if ( RT_FAILURE(rcStrict)
421	\|\| rcStrict == VINF_PGM_SYNCPAGE_MODIFIED_PDE
422	\|\| !(uErr & X86_TRAP_PF_RW))
423	{
424	AssertMsgRC(rcStrict, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
425	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersOutOfSync);
426	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndPhys; });
427	return rcStrict;
428	}
429	}
430
431	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
432	* It's writing to an unhandled part of the LDT page several million times.
433	*/
434	rcStrict = PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault);
435	LogFlow(("PGM: PGMInterpretInstruction -> rcStrict=%d pPage=%R[pgmpage]\n", VBOXSTRICTRC_VAL(rcStrict), pPage));
436	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndUnhandled; });
437	return rcStrict;
438	} /* if any kind of handler */
439
440
441	/**
442	* \#PF Handler for raw-mode guest execution.
443	*
444	* @returns VBox status code (appropriate for trap handling and GC return).
445	*
446	* @param pVCpu The cross context virtual CPU structure.
447	* @param uErr The trap error code.
448	* @param pRegFrame Trap register frame.
449	* @param pvFault The fault address.
450	* @param pfLockTaken PGM lock taken here or not (out)
451	*/
452	PGM_BTH_DECL(int, Trap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken)
453	{
454	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
455
456	*pfLockTaken = false;
457
458	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \
459	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
460	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
461	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT)
462	int rc;
463
464	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
465	/*
466	* Walk the guest page translation tables and check if it's a guest fault.
467	*/
468	GSTPTWALK GstWalk;
469	rc = PGM_GST_NAME(Walk)(pVCpu, pvFault, &GstWalk);
470	if (RT_FAILURE_NP(rc))
471	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
472
473	/* assert some GstWalk sanity. */
474	# if PGM_GST_TYPE == PGM_TYPE_AMD64
475	/AssertMsg(GstWalk.Pml4e.u == GstWalk.pPml4e->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pml4e.u, (uint64_t)GstWalk.pPml4e->u)); - not always true with SMP guests. /
476	# endif
477	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
478	/AssertMsg(GstWalk.Pdpe.u == GstWalk.pPdpe->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pdpe.u, (uint64_t)GstWalk.pPdpe->u)); - ditto /
479	# endif
480	/AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); - ditto /
481	/AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); - ditto /
482	Assert(GstWalk.Core.fSucceeded);
483
484	if (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID))
485	{
486	if ( ( (uErr & X86_TRAP_PF_RW)
487	&& !GstWalk.Core.fEffectiveRW
488	&& ( (uErr & X86_TRAP_PF_US)
489	\|\| CPUMIsGuestR0WriteProtEnabled(pVCpu)) )
490	\|\| ((uErr & X86_TRAP_PF_US) && !GstWalk.Core.fEffectiveUS)
491	\|\| ((uErr & X86_TRAP_PF_ID) && GstWalk.Core.fEffectiveNX)
492	)
493	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerGuestFault)(pVCpu, &GstWalk, uErr));
494	}
495
496	/*
497	* Set the accessed and dirty flags.
498	*/
499	# if PGM_GST_TYPE == PGM_TYPE_AMD64
500	GstWalk.Pml4e.u \|= X86_PML4E_A;
501	GstWalk.pPml4e->u \|= X86_PML4E_A;
502	GstWalk.Pdpe.u \|= X86_PDPE_A;
503	GstWalk.pPdpe->u \|= X86_PDPE_A;
504	# endif
505	if (GstWalk.Core.fBigPage)
506	{
507	Assert(GstWalk.Pde.b.u1Size);
508	if (uErr & X86_TRAP_PF_RW)
509	{
510	GstWalk.Pde.u \|= X86_PDE4M_A \| X86_PDE4M_D;
511	GstWalk.pPde->u \|= X86_PDE4M_A \| X86_PDE4M_D;
512	}
513	else
514	{
515	GstWalk.Pde.u \|= X86_PDE4M_A;
516	GstWalk.pPde->u \|= X86_PDE4M_A;
517	}
518	}
519	else
520	{
521	Assert(!GstWalk.Pde.b.u1Size);
522	GstWalk.Pde.u \|= X86_PDE_A;
523	GstWalk.pPde->u \|= X86_PDE_A;
524	if (uErr & X86_TRAP_PF_RW)
525	{
526	# ifdef VBOX_WITH_STATISTICS
527	if (!GstWalk.Pte.n.u1Dirty)
528	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtiedPage));
529	else
530	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageAlreadyDirty));
531	# endif
532	GstWalk.Pte.u \|= X86_PTE_A \| X86_PTE_D;
533	GstWalk.pPte->u \|= X86_PTE_A \| X86_PTE_D;
534	}
535	else
536	{
537	GstWalk.Pte.u \|= X86_PTE_A;
538	GstWalk.pPte->u \|= X86_PTE_A;
539	}
540	Assert(GstWalk.Pte.u == GstWalk.pPte->u);
541	}
542	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u,
543	("%RX64 %RX64 pPte=%p pPde=%p Pte=%RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u, GstWalk.pPte, GstWalk.pPde, (uint64_t)GstWalk.pPte->u));
544	# else /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
545	GSTPDE const PdeSrcDummy = { X86_PDE_P \| X86_PDE_US \| X86_PDE_RW \| X86_PDE_A}; /** @todo eliminate this */
546	# endif /* !PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
547
548	/* Take the big lock now. */
549	*pfLockTaken = true;
550	pgmLock(pVM);
551
552	# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
553	/*
554	* If it is a reserved bit fault we know that it is an MMIO (access
555	* handler) related fault and can skip some 200 lines of code.
556	*/
557	if (uErr & X86_TRAP_PF_RSVD)
558	{
559	Assert(uErr & X86_TRAP_PF_P);
560	PPGMPAGE pPage;
561	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
562	rc = pgmPhysGetPageEx(pVM, GstWalk.Core.GCPhys, &pPage);
563	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
564	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
565	pfLockTaken, &GstWalk));
566	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
567	# else
568	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault), &pPage);
569	if (RT_SUCCESS(rc) && PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
570	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage,
571	pfLockTaken));
572	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
573	# endif
574	AssertRC(rc);
575	PGM_INVL_PG(pVCpu, pvFault);
576	return rc; /* Restart with the corrected entry. */
577	}
578	# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
579
580	/*
581	* Fetch the guest PDE, PDPE and PML4E.
582	*/
583	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
584	const unsigned iPDDst = pvFault >> SHW_PD_SHIFT;
585	PX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
586
587	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
588	const unsigned iPDDst = (pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK; /* pPDDst index, not used with the pool. */
589	PX86PDPAE pPDDst;
590	# if PGM_GST_TYPE == PGM_TYPE_PAE
591	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, GstWalk.Pdpe.u, &pPDDst);
592	# else
593	rc = pgmShwSyncPaePDPtr(pVCpu, pvFault, X86_PDPE_P, &pPDDst); /* RW, US and A are reserved in PAE mode. */
594	# endif
595	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
596
597	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
598	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
599	PX86PDPAE pPDDst;
600	# if PGM_GST_TYPE == PGM_TYPE_PROT /* (AMD-V nested paging) */
601	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A,
602	X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A, &pPDDst);
603	# else
604	rc = pgmShwSyncLongModePDPtr(pVCpu, pvFault, GstWalk.Pml4e.u, GstWalk.Pdpe.u, &pPDDst);
605	# endif
606	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
607
608	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
609	const unsigned iPDDst = ((pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
610	PEPTPD pPDDst;
611	rc = pgmShwGetEPTPDPtr(pVCpu, pvFault, NULL, &pPDDst);
612	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
613	# endif
614	Assert(pPDDst);
615
616	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
617	/*
618	* Dirty page handling.
619	*
620	* If we successfully correct the write protection fault due to dirty bit
621	* tracking, then return immediately.
622	*/
623	if (uErr & X86_TRAP_PF_RW) /* write fault? */
624	{
625	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
626	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, &pPDDst->a[iPDDst], GstWalk.pPde, pvFault);
627	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyBitTracking), a);
628	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
629	{
630	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution)
631	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
632	? &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2DirtyAndAccessed
633	: &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2GuestTrap; });
634	Log8(("Trap0eHandler: returns VINF_SUCCESS\n"));
635	return VINF_SUCCESS;
636	}
637	#ifdef DEBUG_bird
638	AssertMsg(GstWalk.Pde.u == GstWalk.pPde->u \|\| GstWalk.pPte->u == GstWalk.pPde->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pde.u, (uint64_t)GstWalk.pPde->u)); // - triggers with smp w7 guests.
639	AssertMsg(GstWalk.Core.fBigPage \|\| GstWalk.Pte.u == GstWalk.pPte->u \|\| pVM->cCpus > 1, ("%RX64 %RX64\n", (uint64_t)GstWalk.Pte.u, (uint64_t)GstWalk.pPte->u)); // - ditto.
640	#endif
641	}
642
643	# if 0 /* rarely useful; leave for debugging. */
644	STAM_COUNTER_INC(&pVCpu->pgm.s.StatRZTrap0ePD[iPDSrc]);
645	# endif
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
647
648	/*
649	* A common case is the not-present error caused by lazy page table syncing.
650	*
651	* It is IMPORTANT that we weed out any access to non-present shadow PDEs
652	* here so we can safely assume that the shadow PT is present when calling
653	* SyncPage later.
654	*
655	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
656	* of mapping conflict and defer to SyncCR3 in R3.
657	* (Again, we do NOT support access handlers for non-present guest pages.)
658	*
659	*/
660	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
661	Assert(GstWalk.Pde.n.u1Present);
662	# endif
663	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
664	&& !pPDDst->a[iPDDst].n.u1Present)
665	{
666	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2SyncPT; });
667	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
668	LogFlow(("=>SyncPT %04x = %08RX64\n", (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, (uint64_t)GstWalk.Pde.u));
669	rc = PGM_BTH_NAME(SyncPT)(pVCpu, (pvFault >> GST_PD_SHIFT) & GST_PD_MASK, GstWalk.pPd, pvFault);
670	# else
671	LogFlow(("=>SyncPT pvFault=%RGv\n", pvFault));
672	rc = PGM_BTH_NAME(SyncPT)(pVCpu, 0, NULL, pvFault);
673	# endif
674	if (RT_SUCCESS(rc))
675	return rc;
676	Log(("SyncPT: %RGv failed!! rc=%Rrc\n", pvFault, rc));
677	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
678	return VINF_PGM_SYNC_CR3;
679	}
680
681	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(PGM_WITHOUT_MAPPINGS)
682	/*
683	* Check if this address is within any of our mappings.
684	*
685	* This is very fast and it's gonna save us a bit of effort below and prevent
686	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
687	* (BTW, it's impossible to have physical access handlers in a mapping.)
688	*/
689	if (pgmMapAreMappingsEnabled(pVM))
690	{
691	PPGMMAPPING pMapping = pVM->pgm.s.CTX_SUFF(pMappings);
692	for ( ; pMapping; pMapping = pMapping->CTX_SUFF(pNext))
693	{
694	if (pvFault < pMapping->GCPtr)
695	break;
696	if (pvFault - pMapping->GCPtr < pMapping->cb)
697	{
698	/*
699	* The first thing we check is if we've got an undetected conflict.
700	*/
701	if (pgmMapAreMappingsFloating(pVM))
702	{
703	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
704	while (iPT-- > 0)
705	if (GstWalk.pPde[iPT].n.u1Present)
706	{
707	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eConflicts);
708	Log(("Trap0e: Detected Conflict %RGv-%RGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
709	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
710	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
711	return VINF_PGM_SYNC_CR3;
712	}
713	}
714
715	/*
716	* Check if the fault address is in a virtual page access handler range.
717	*/
718	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->HyperVirtHandlers,
719	pvFault);
720	if ( pCur
721	&& pvFault - pCur->Core.Key < pCur->cb
722	&& uErr & X86_TRAP_PF_RW)
723	{
724	VBOXSTRICTRC rcStrict;
725	# ifdef IN_RC
726	STAM_PROFILE_START(&pCur->Stat, h);
727	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
728	void *pvUser = pCur->CTX_SUFF(pvUser);
729	pgmUnlock(pVM);
730	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
731	pvFault - pCur->Core.Key, pvUser);
732	pgmLock(pVM);
733	STAM_PROFILE_STOP(&pCur->Stat, h);
734	# else
735	AssertFailed();
736	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
737	# endif
738	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersMapping);
739	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
740	return VBOXSTRICTRC_TODO(rcStrict);
741	}
742
743	/*
744	* Pretend we're not here and let the guest handle the trap.
745	*/
746	TRPMSetErrorCode(pVCpu, uErr & ~X86_TRAP_PF_P);
747	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eGuestPFMapping);
748	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
749	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Mapping; });
750	return VINF_EM_RAW_GUEST_TRAP;
751	}
752	}
753	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
754	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
755
756	/*
757	* Check if this fault address is flagged for special treatment,
758	* which means we'll have to figure out the physical address and
759	* check flags associated with it.
760	*
761	* ASSUME that we can limit any special access handling to pages
762	* in page tables which the guest believes to be present.
763	*/
764	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
765	RTGCPHYS GCPhys = GstWalk.Core.GCPhys & ~(RTGCPHYS)PAGE_OFFSET_MASK;
766	# else
767	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, (RTGCPHYS)pvFault & ~(RTGCPHYS)PAGE_OFFSET_MASK);
768	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
769	PPGMPAGE pPage;
770	rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
771	if (RT_FAILURE(rc))
772	{
773	/*
774	* When the guest accesses invalid physical memory (e.g. probing
775	* of RAM or accessing a remapped MMIO range), then we'll fall
776	* back to the recompiler to emulate the instruction.
777	*/
778	LogFlow(("PGM #PF: pgmPhysGetPageEx(%RGp) failed with %Rrc\n", GCPhys, rc));
779	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eHandlersInvalid);
780	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2InvalidPhys; });
781	return VINF_EM_RAW_EMULATE_INSTR;
782	}
783
784	/*
785	* Any handlers for this page?
786	*/
787	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
788	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
789	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken,
790	&GstWalk));
791	# else
792	return VBOXSTRICTRC_TODO(PGM_BTH_NAME(Trap0eHandlerDoAccessHandlers)(pVCpu, uErr, pRegFrame, pvFault, pPage, pfLockTaken));
793	# endif
794
795	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
796	if (uErr & X86_TRAP_PF_P)
797	{
798	/*
799	* The page isn't marked, but it might still be monitored by a virtual page access handler.
800	* (ASSUMES no temporary disabling of virtual handlers.)
801	*/
802	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
803	* we should correct both the shadow page table and physical memory flags, and not only check for
804	* accesses within the handler region but for access to pages with virtual handlers. */
805	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&pVM->pgm.s.CTX_SUFF(pTrees)->VirtHandlers, pvFault);
806	if (pCur)
807	{
808	PPGMVIRTHANDLERTYPEINT pCurType = PGMVIRTANDLER_GET_TYPE(pVM, pCur);
809	AssertMsg( !(pvFault - pCur->Core.Key < pCur->cb)
810	\|\| ( pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE
811	\|\| !(uErr & X86_TRAP_PF_P)
812	\|\| (pCurType->enmKind == PGMVIRTHANDLERKIND_WRITE && (uErr & X86_TRAP_PF_RW))),
813	("Unexpected trap for virtual handler: %08X (phys=%08x) %R[pgmpage] uErr=%X, enumKind=%d\n",
814	pvFault, GCPhys, pPage, uErr, pCurType->enmKind));
815
816	if ( pvFault - pCur->Core.Key < pCur->cb
817	&& ( uErr & X86_TRAP_PF_RW
818	\|\| pCurType->enmKind != PGMVIRTHANDLERKIND_WRITE ) )
819	{
820	VBOXSTRICTRC rcStrict;
821	# ifdef IN_RC
822	STAM_PROFILE_START(&pCur->Stat, h);
823	void *pvUser = pCur->CTX_SUFF(pvUser);
824	pgmUnlock(pVM);
825	rcStrict = pCurType->CTX_SUFF(pfnPfHandler)(pVM, pVCpu, uErr, pRegFrame, pvFault, pCur->Core.Key,
826	pvFault - pCur->Core.Key, pvUser);
827	pgmLock(pVM);
828	STAM_PROFILE_STOP(&pCur->Stat, h);
829	# else
830	rcStrict = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
831	# endif
832	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2HndVirt; });
833	return VBOXSTRICTRC_TODO(rcStrict);
834	}
835	}
836	}
837	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
838
839	/*
840	* We are here only if page is present in Guest page tables and
841	* trap is not handled by our handlers.
842	*
843	* Check it for page out-of-sync situation.
844	*/
845	if (!(uErr & X86_TRAP_PF_P))
846	{
847	/*
848	* Page is not present in our page tables. Try to sync it!
849	*/
850	if (uErr & X86_TRAP_PF_US)
851	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
852	else /* supervisor */
853	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
854
855	if (PGM_PAGE_IS_BALLOONED(pPage))
856	{
857	/* Emulate reads from ballooned pages as they are not present in
858	our shadow page tables. (Required for e.g. Solaris guests; soft
859	ecc, random nr generator.) */
860	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
861	LogFlow(("PGM: PGMInterpretInstruction balloon -> rc=%d pPage=%R[pgmpage]\n", rc, pPage));
862	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncBallloon));
863	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Ballooned; });
864	return rc;
865	}
866
867	# if defined(LOG_ENABLED) && !defined(IN_RING0)
868	RTGCPHYS GCPhys2;
869	uint64_t fPageGst2;
870	PGMGstGetPage(pVCpu, pvFault, &fPageGst2, &GCPhys2);
871	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
872	Log(("Page out of sync: %RGv eip=%08x PdeSrc.US=%d fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
873	pvFault, pRegFrame->eip, GstWalk.Pde.n.u1User, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
874	# else
875	Log(("Page out of sync: %RGv eip=%08x fPageGst2=%08llx GCPhys2=%RGp scan=%d\n",
876	pvFault, pRegFrame->eip, fPageGst2, GCPhys2, CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)));
877	# endif
878	# endif /* LOG_ENABLED */
879
880	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0)
881	if ( !GstWalk.Core.fEffectiveUS
882	&& CSAMIsEnabled(pVM)
883	&& CPUMGetGuestCPL(pVCpu) == 0)
884	{
885	/* Note: Can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU. */
886	if ( pvFault == (RTGCPTR)pRegFrame->eip
887	\|\| pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
888	# ifdef CSAM_DETECT_NEW_CODE_PAGES
889	\|\| ( !PATMIsPatchGCAddr(pVM, pRegFrame->eip)
890	&& CSAMDoesPageNeedScanning(pVM, pRegFrame->eip)) /* any new code we encounter here */
891	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
892	)
893	{
894	LogFlow(("CSAMExecFault %RX32\n", pRegFrame->eip));
895	rc = CSAMExecFault(pVM, (RTRCPTR)pRegFrame->eip);
896	if (rc != VINF_SUCCESS)
897	{
898	/*
899	* CSAM needs to perform a job in ring 3.
900	*
901	* Sync the page before going to the host context; otherwise we'll end up in a loop if
902	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
903	*/
904	LogFlow(("CSAM ring 3 job\n"));
905	int rc2 = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
906	AssertRC(rc2);
907
908	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2CSAM; });
909	return rc;
910	}
911	}
912	# ifdef CSAM_DETECT_NEW_CODE_PAGES
913	else if ( uErr == X86_TRAP_PF_RW
914	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
915	&& pRegFrame->ecx < 0x10000)
916	{
917	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
918	* to detect loading of new code pages.
919	*/
920
921	/*
922	* Decode the instruction.
923	*/
924	PDISCPUSTATE pDis = &pVCpu->pgm.s.DisState;
925	uint32_t cbOp;
926	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
927
928	/* For now we'll restrict this to rep movsw/d instructions */
929	if ( rc == VINF_SUCCESS
930	&& pDis->pCurInstr->opcode == OP_MOVSWD
931	&& (pDis->prefix & DISPREFIX_REP))
932	{
933	CSAMMarkPossibleCodePage(pVM, pvFault);
934	}
935	}
936	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
937
938	/*
939	* Mark this page as safe.
940	*/
941	/** @todo not correct for pages that contain both code and data!! */
942	Log2(("CSAMMarkPage %RGv; scanned=%d\n", pvFault, true));
943	CSAMMarkPage(pVM, pvFault, true);
944	}
945	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && !defined(IN_RING0) */
946	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
947	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, PGM_SYNC_NR_PAGES, uErr);
948	# else
949	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, PGM_SYNC_NR_PAGES, uErr);
950	# endif
951	if (RT_SUCCESS(rc))
952	{
953	/* The page was successfully synced, return to the guest. */
954	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSync; });
955	return VINF_SUCCESS;
956	}
957	}
958	else /* uErr & X86_TRAP_PF_P: */
959	{
960	/*
961	* Write protected pages are made writable when the guest makes the
962	* first write to it. This happens for pages that are shared, write
963	* monitored or not yet allocated.
964	*
965	* We may also end up here when CR0.WP=0 in the guest.
966	*
967	* Also, a side effect of not flushing global PDEs are out of sync
968	* pages due to physical monitored regions, that are no longer valid.
969	* Assume for now it only applies to the read/write flag.
970	*/
971	if (uErr & X86_TRAP_PF_RW)
972	{
973	/*
974	* Check if it is a read-only page.
975	*/
976	if (PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
977	{
978	Log(("PGM #PF: Make writable: %RGp %R[pgmpage] pvFault=%RGp uErr=%#x\n", GCPhys, pPage, pvFault, uErr));
979	Assert(!PGM_PAGE_IS_ZERO(pPage));
980	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
981	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2MakeWritable; });
982
983	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
984	if (rc != VINF_SUCCESS)
985	{
986	AssertMsg(rc == VINF_PGM_SYNC_CR3 \|\| RT_FAILURE(rc), ("%Rrc\n", rc));
987	return rc;
988	}
989	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
990	return VINF_EM_NO_MEMORY;
991	}
992
993	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
994	/*
995	* Check to see if we need to emulate the instruction if CR0.WP=0.
996	*/
997	if ( !GstWalk.Core.fEffectiveRW
998	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
999	&& CPUMGetGuestCPL(pVCpu) < 3)
1000	{
1001	Assert((uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P));
1002
1003	/*
1004	* The Netware WP0+RO+US hack.
1005	*
1006	* Netware sometimes(/always?) runs with WP0. It has been observed doing
1007	* excessive write accesses to pages which are mapped with US=1 and RW=0
1008	* while WP=0. This causes a lot of exits and extremely slow execution.
1009	* To avoid trapping and emulating every write here, we change the shadow
1010	* page table entry to map it as US=0 and RW=1 until user mode tries to
1011	* access it again (see further below). We count these shadow page table
1012	* changes so we can avoid having to clear the page pool every time the WP
1013	* bit changes to 1 (see PGMCr0WpEnabled()).
1014	*/
1015	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && 1
1016	if ( GstWalk.Core.fEffectiveUS
1017	&& !GstWalk.Core.fEffectiveRW
1018	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1019	&& pVM->cCpus == 1 /* Sorry, no go on SMP. Add CFGM option? */)
1020	{
1021	Log(("PGM #PF: Netware WP0+RO+US hack: pvFault=%RGp uErr=%#x (big=%d)\n", pvFault, uErr, GstWalk.Core.fBigPage));
1022	rc = pgmShwMakePageSupervisorAndWritable(pVCpu, pvFault, GstWalk.Core.fBigPage, PGM_MK_PG_IS_WRITE_FAULT);
1023	if (rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3)
1024	{
1025	PGM_INVL_PG(pVCpu, pvFault);
1026	pVCpu->pgm.s.cNetwareWp0Hacks++;
1027	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsHack; });
1028	return rc;
1029	}
1030	AssertMsg(RT_FAILURE_NP(rc), ("%Rrc\n", rc));
1031	Log(("pgmShwMakePageSupervisorAndWritable(%RGv) failed with rc=%Rrc - ignored\n", pvFault, rc));
1032	}
1033	# endif
1034
1035	/* Interpret the access. */
1036	rc = VBOXSTRICTRC_TODO(PGMInterpretInstruction(pVM, pVCpu, pRegFrame, pvFault));
1037	Log(("PGM #PF: WP0 emulation (pvFault=%RGp uErr=%#x cpl=%d fBig=%d fEffUs=%d)\n", pvFault, uErr, CPUMGetGuestCPL(pVCpu), GstWalk.Core.fBigPage, GstWalk.Core.fEffectiveUS));
1038	if (RT_SUCCESS(rc))
1039	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulInRZ);
1040	else
1041	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eWPEmulToR3);
1042	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2WPEmulation; });
1043	return rc;
1044	}
1045	# endif
1046	/// @todo count the above case; else
1047	if (uErr & X86_TRAP_PF_US)
1048	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUserWrite));
1049	else /* supervisor */
1050	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisorWrite));
1051
1052	/*
1053	* Sync the page.
1054	*
1055	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the
1056	* page is not present, which is not true in this case.
1057	*/
1058	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1059	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1060	# else
1061	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrcDummy, pvFault, 1, uErr);
1062	# endif
1063	if (RT_SUCCESS(rc))
1064	{
1065	/*
1066	* Page was successfully synced, return to guest but invalidate
1067	* the TLB first as the page is very likely to be in it.
1068	*/
1069	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1070	HMInvalidatePhysPage(pVM, (RTGCPHYS)pvFault);
1071	# else
1072	PGM_INVL_PG(pVCpu, pvFault);
1073	# endif
1074	# ifdef VBOX_STRICT
1075	RTGCPHYS GCPhys2 = RTGCPHYS_MAX;
1076	uint64_t fPageGst = UINT64_MAX;
1077	if (!pVM->pgm.s.fNestedPaging)
1078	{
1079	rc = PGMGstGetPage(pVCpu, pvFault, &fPageGst, &GCPhys2);
1080	AssertMsg(RT_SUCCESS(rc) && ((fPageGst & X86_PTE_RW) \|\| ((CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG && CPUMGetGuestCPL(pVCpu) < 3)), ("rc=%Rrc fPageGst=%RX64\n", rc, fPageGst));
1081	LogFlow(("Obsolete physical monitor page out of sync %RGv - phys %RGp flags=%08llx\n", pvFault, GCPhys2, (uint64_t)fPageGst));
1082	}
1083	# if 0 /* Bogus! Triggers incorrectly with w7-64 and later for the SyncPage case: "Pde at %RGv changed behind our back?" */
1084	uint64_t fPageShw = 0;
1085	rc = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1086	AssertMsg((RT_SUCCESS(rc) && (fPageShw & X86_PTE_RW)) \|\| pVM->cCpus > 1 /* new monitor can be installed/page table flushed between the trap exit and PGMTrap0eHandler */,
1087	("rc=%Rrc fPageShw=%RX64 GCPhys2=%RGp fPageGst=%RX64 pvFault=%RGv\n", rc, fPageShw, GCPhys2, fPageGst, pvFault));
1088	# endif
1089	# endif /* VBOX_STRICT */
1090	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2OutOfSyncHndObs; });
1091	return VINF_SUCCESS;
1092	}
1093	}
1094	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1095	/*
1096	* Check for Netware WP0+RO+US hack from above and undo it when user
1097	* mode accesses the page again.
1098	*/
1099	else if ( GstWalk.Core.fEffectiveUS
1100	&& !GstWalk.Core.fEffectiveRW
1101	&& (GstWalk.Core.fBigPage \|\| GstWalk.Pde.n.u1Write)
1102	&& pVCpu->pgm.s.cNetwareWp0Hacks > 0
1103	&& (CPUMGetGuestCR0(pVCpu) & (X86_CR0_WP \| X86_CR0_PG)) == X86_CR0_PG
1104	&& CPUMGetGuestCPL(pVCpu) == 3
1105	&& pVM->cCpus == 1
1106	)
1107	{
1108	Log(("PGM #PF: Undo netware WP0+RO+US hack: pvFault=%RGp uErr=%#x\n", pvFault, uErr));
1109	rc = PGM_BTH_NAME(SyncPage)(pVCpu, GstWalk.Pde, pvFault, 1, uErr);
1110	if (RT_SUCCESS(rc))
1111	{
1112	PGM_INVL_PG(pVCpu, pvFault);
1113	pVCpu->pgm.s.cNetwareWp0Hacks--;
1114	STAM_STATS({ pVCpu->pgm.s.CTX_SUFF(pStatTrap0eAttribution) = &pVCpu->pgm.s.CTX_SUFF(pStats)->StatRZTrap0eTime2Wp0RoUsUnhack; });
1115	return VINF_SUCCESS;
1116	}
1117	}
1118	# endif /* PGM_WITH_PAGING */
1119
1120	/** @todo else: why are we here? */
1121
1122	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && defined(VBOX_STRICT)
1123	/*
1124	* Check for VMM page flags vs. Guest page flags consistency.
1125	* Currently only for debug purposes.
1126	*/
1127	if (RT_SUCCESS(rc))
1128	{
1129	/* Get guest page flags. */
1130	uint64_t fPageGst;
1131	int rc2 = PGMGstGetPage(pVCpu, pvFault, &fPageGst, NULL);
1132	if (RT_SUCCESS(rc2))
1133	{
1134	uint64_t fPageShw = 0;
1135	rc2 = PGMShwGetPage(pVCpu, pvFault, &fPageShw, NULL);
1136
1137	#if 0
1138	/*
1139	* Compare page flags.
1140	* Note: we have AVL, A, D bits desynced.
1141	*/
1142	AssertMsg( (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1143	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK))
1144	\|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0
1145	&& (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1146	== (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US))
1147	&& (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW
1148	&& (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US),
1149	("Page flags mismatch! pvFault=%RGv uErr=%x GCPhys=%RGp fPageShw=%RX64 fPageGst=%RX64 rc=%d\n",
1150	pvFault, (uint32_t)uErr, GCPhys, fPageShw, fPageGst, rc));
1151	01:01:15.623511 00:08:43.266063 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
1152	01:01:15.623511 00:08:43.266064 Location : e:\vbox\svn\trunk\srcPage flags mismatch! pvFault=fffff801b0d7b000 uErr=11 GCPhys=0000000019b52000 fPageShw=0 fPageGst=77b0000000000121 rc=0
1153
1154	01:01:15.625516 00:08:43.268051 Expression: (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) \|\| ( pVCpu->pgm.s.cNetwareWp0Hacks > 0 && (fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK \| X86_PTE_RW \| X86_PTE_US)) && (fPageShw & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW && (fPageGst & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_US)
1155	01:01:15.625516 00:08:43.268051 Location :
1156	e:\vbox\svn\trunk\srcPage flags mismatch!
1157	pvFault=fffff801b0d7b000
1158	uErr=11 X86_TRAP_PF_ID \| X86_TRAP_PF_P
1159	GCPhys=0000000019b52000
1160	fPageShw=0
1161	fPageGst=77b0000000000121
1162	rc=0
1163	#endif
1164
1165	}
1166	else
1167	AssertMsgFailed(("PGMGstGetPage rc=%Rrc\n", rc));
1168	}
1169	else
1170	AssertMsgFailed(("PGMGCGetPage rc=%Rrc\n", rc));
1171	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && VBOX_STRICT */
1172	}
1173
1174
1175	/*
1176	* If we get here it is because something failed above, i.e. most like guru
1177	* meditiation time.
1178	*/
1179	LogRel(("%s: returns rc=%Rrc pvFault=%RGv uErr=%RX64 cs:rip=%04x:%08RX64\n",
1180	__PRETTY_FUNCTION__, rc, pvFault, (uint64_t)uErr, pRegFrame->cs.Sel, pRegFrame->rip));
1181	return rc;
1182
1183	# else /* Nested paging, EPT except PGM_GST_TYPE = PROT */
1184	NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
1185	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1186	return VERR_PGM_NOT_USED_IN_MODE;
1187	# endif
1188	}
1189	#endif /* !IN_RING3 */
1190
1191
1192	/**
1193	* Emulation of the invlpg instruction.
1194	*
1195	*
1196	* @returns VBox status code.
1197	*
1198	* @param pVCpu The cross context virtual CPU structure.
1199	* @param GCPtrPage Page to invalidate.
1200	*
1201	* @remark ASSUMES that the guest is updating before invalidating. This order
1202	* isn't required by the CPU, so this is speculative and could cause
1203	* trouble.
1204	* @remark No TLB shootdown is done on any other VCPU as we assume that
1205	* invlpg emulation is the only reason for calling this function.
1206	* (The guest has to shoot down TLB entries on other CPUs itself)
1207	* Currently true, but keep in mind!
1208	*
1209	* @todo Clean this up! Most of it is (or should be) no longer necessary as we catch all page table accesses.
1210	* Should only be required when PGMPOOL_WITH_OPTIMIZED_DIRTY_PT is active (PAE or AMD64 (for now))
1211	*/
1212	PGM_BTH_DECL(int, InvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
1213	{
1214	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1215	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1216	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1217	int rc;
1218	PVM pVM = pVCpu->CTX_SUFF(pVM);
1219	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1220
1221	PGM_LOCK_ASSERT_OWNER(pVM);
1222
1223	LogFlow(("InvalidatePage %RGv\n", GCPtrPage));
1224
1225	/*
1226	* Get the shadow PD entry and skip out if this PD isn't present.
1227	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
1228	*/
1229	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1230	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1231	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1232
1233	/* Fetch the pgm pool shadow descriptor. */
1234	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1235	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1236	if (!pShwPde)
1237	{
1238	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1239	return VINF_SUCCESS;
1240	}
1241	# else
1242	Assert(pShwPde);
1243	# endif
1244
1245	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1246	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT);
1247	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
1248
1249	/* If the shadow PDPE isn't present, then skip the invalidate. */
1250	# ifdef IN_RING3 /* Possible we didn't resync yet when called from REM. */
1251	if (!pPdptDst \|\| !pPdptDst->a[iPdpt].n.u1Present)
1252	# else
1253	if (!pPdptDst->a[iPdpt].n.u1Present)
1254	# endif
1255	{
1256	Assert(!pPdptDst \|\| !(pPdptDst->a[iPdpt].u & PGM_PLXFLAGS_MAPPING));
1257	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1258	PGM_INVL_PG(pVCpu, GCPtrPage);
1259	return VINF_SUCCESS;
1260	}
1261
1262	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1263	PPGMPOOLPAGE pShwPde = NULL;
1264	PX86PDPAE pPDDst;
1265
1266	/* Fetch the pgm pool shadow descriptor. */
1267	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1268	AssertRCSuccessReturn(rc, rc);
1269	Assert(pShwPde);
1270
1271	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1272	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1273
1274	# else /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1275	/* PML4 */
1276	/const unsigned iPml4 = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;/
1277	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1278	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1279	PX86PDPAE pPDDst;
1280	PX86PDPT pPdptDst;
1281	PX86PML4E pPml4eDst;
1282	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eDst, &pPdptDst, &pPDDst);
1283	if (rc != VINF_SUCCESS)
1284	{
1285	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT \|\| rc == VERR_PAGE_MAP_LEVEL4_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
1286	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1287	PGM_INVL_PG(pVCpu, GCPtrPage);
1288	return VINF_SUCCESS;
1289	}
1290	Assert(pPDDst);
1291
1292	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1293	PX86PDPE pPdpeDst = &pPdptDst->a[iPdpt];
1294
1295	if (!pPdpeDst->n.u1Present)
1296	{
1297	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1298	PGM_INVL_PG(pVCpu, GCPtrPage);
1299	return VINF_SUCCESS;
1300	}
1301
1302	/* Fetch the pgm pool shadow descriptor. */
1303	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & SHW_PDPE_PG_MASK);
1304	Assert(pShwPde);
1305
1306	# endif /* PGM_SHW_TYPE == PGM_TYPE_AMD64 */
1307
1308	const SHWPDE PdeDst = *pPdeDst;
1309	if (!PdeDst.n.u1Present)
1310	{
1311	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1312	PGM_INVL_PG(pVCpu, GCPtrPage);
1313	return VINF_SUCCESS;
1314	}
1315
1316	/*
1317	* Get the guest PD entry and calc big page.
1318	*/
1319	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1320	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
1321	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
1322	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1323	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1324	unsigned iPDSrc = 0;
1325	# if PGM_GST_TYPE == PGM_TYPE_PAE
1326	X86PDPE PdpeSrcIgn;
1327	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrcIgn);
1328	# else /* AMD64 */
1329	PX86PML4E pPml4eSrcIgn;
1330	X86PDPE PdpeSrcIgn;
1331	PX86PDPAE pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrcIgn, &PdpeSrcIgn, &iPDSrc);
1332	# endif
1333	GSTPDE PdeSrc;
1334
1335	if (pPDSrc)
1336	PdeSrc = pPDSrc->a[iPDSrc];
1337	else
1338	PdeSrc.u = 0;
1339	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1340	const bool fIsBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
1341
1342	# ifdef IN_RING3
1343	/*
1344	* If a CR3 Sync is pending we may ignore the invalidate page operation
1345	* depending on the kind of sync and if it's a global page or not.
1346	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
1347	*/
1348	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
1349	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1350	\|\| ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1351	&& fIsBigPage
1352	&& PdeSrc.b.u1Global
1353	)
1354	)
1355	# else
1356	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
1357	# endif
1358	{
1359	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePageSkipped));
1360	return VINF_SUCCESS;
1361	}
1362	# endif /* IN_RING3 */
1363
1364	/*
1365	* Deal with the Guest PDE.
1366	*/
1367	rc = VINF_SUCCESS;
1368	if (PdeSrc.n.u1Present)
1369	{
1370	Assert( PdeSrc.n.u1User == PdeDst.n.u1User
1371	&& (PdeSrc.n.u1Write \|\| !PdeDst.n.u1Write \|\| pVCpu->pgm.s.cNetwareWp0Hacks > 0));
1372	# ifndef PGM_WITHOUT_MAPPING
1373	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1374	{
1375	/*
1376	* Conflict - Let SyncPT deal with it to avoid duplicate code.
1377	*/
1378	Assert(pgmMapAreMappingsEnabled(pVM));
1379	Assert(PGMGetGuestMode(pVCpu) <= PGMMODE_PAE);
1380	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
1381	}
1382	else
1383	# endif /* !PGM_WITHOUT_MAPPING */
1384	if (!fIsBigPage)
1385	{
1386	/*
1387	* 4KB - page.
1388	*/
1389	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1390	RTGCPHYS GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
1391
1392	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1393	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1394	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
1395	# endif
1396	if (pShwPage->GCPhys == GCPhys)
1397	{
1398	/* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
1399	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
1400
1401	PGSTPT pPTSrc;
1402	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
1403	if (RT_SUCCESS(rc))
1404	{
1405	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1406	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1407	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1408	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1409	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
1410	GCPtrPage, PteSrc.n.u1Present,
1411	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1412	PteSrc.n.u1User & PdeSrc.n.u1User,
1413	(uint64_t)PteSrc.u,
1414	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
1415	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
1416	}
1417	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4KBPages));
1418	PGM_INVL_PG(pVCpu, GCPtrPage);
1419	}
1420	else
1421	{
1422	/*
1423	* The page table address changed.
1424	*/
1425	LogFlow(("InvalidatePage: Out-of-sync at %RGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%RGp iPDDst=%#x\n",
1426	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
1427	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1428	ASMAtomicWriteSize(pPdeDst, 0);
1429	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDOutOfSync));
1430	PGM_INVL_VCPU_TLBS(pVCpu);
1431	}
1432	}
1433	else
1434	{
1435	/*
1436	* 2/4MB - page.
1437	*/
1438	/* Before freeing the page, check if anything really changed. */
1439	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
1440	RTGCPHYS GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
1441	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1442	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1443	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
1444	# endif
1445	if ( pShwPage->GCPhys == GCPhys
1446	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1447	{
1448	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1449	/** @todo This test is wrong as it cannot check the G bit!
1450	* FIXME */
1451	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1452	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US))
1453	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1454	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1455	{
1456	LogFlow(("Skipping flush for big page containing %RGv (PD=%X .u=%RX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1457	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPagesSkip));
1458	return VINF_SUCCESS;
1459	}
1460	}
1461
1462	/*
1463	* Ok, the page table is present and it's been changed in the guest.
1464	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1465	* We could do this for some flushes in GC too, but we need an algorithm for
1466	* deciding which 4MB pages containing code likely to be executed very soon.
1467	*/
1468	LogFlow(("InvalidatePage: Out-of-sync PD at %RGp PdeSrc=%RX64 PdeDst=%RX64\n",
1469	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1470	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1471	ASMAtomicWriteSize(pPdeDst, 0);
1472	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePage4MBPages));
1473	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
1474	}
1475	}
1476	else
1477	{
1478	/*
1479	* Page directory is not present, mark shadow PDE not present.
1480	*/
1481	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1482	{
1483	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, pShwPde->idx, iPDDst);
1484	ASMAtomicWriteSize(pPdeDst, 0);
1485	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDNPs));
1486	PGM_INVL_PG(pVCpu, GCPtrPage);
1487	}
1488	else
1489	{
1490	Assert(pgmMapAreMappingsEnabled(pVM));
1491	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,InvalidatePagePDMappings));
1492	}
1493	}
1494	return rc;
1495
1496	#else /* guest real and protected mode */
1497	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1498	NOREF(pVCpu); NOREF(GCPtrPage);
1499	return VINF_SUCCESS;
1500	#endif
1501	}
1502
1503
1504	/**
1505	* Update the tracking of shadowed pages.
1506	*
1507	* @param pVCpu The cross context virtual CPU structure.
1508	* @param pShwPage The shadow page.
1509	* @param HCPhys The physical page we is being dereferenced.
1510	* @param iPte Shadow PTE index
1511	* @param GCPhysPage Guest physical address (only valid if pShwPage->fDirty is set)
1512	*/
1513	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys, uint16_t iPte,
1514	RTGCPHYS GCPhysPage)
1515	{
1516	PVM pVM = pVCpu->CTX_SUFF(pVM);
1517
1518	# if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1519	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1520	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1521
1522	/* Use the hint we retrieved from the cached guest PT. */
1523	if (pShwPage->fDirty)
1524	{
1525	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1526
1527	Assert(pShwPage->cPresent);
1528	Assert(pPool->cPresent);
1529	pShwPage->cPresent--;
1530	pPool->cPresent--;
1531
1532	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysPage);
1533	AssertRelease(pPhysPage);
1534	pgmTrackDerefGCPhys(pPool, pShwPage, pPhysPage, iPte);
1535	return;
1536	}
1537	# else
1538	NOREF(GCPhysPage);
1539	# endif
1540
1541	STAM_PROFILE_START(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1542	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%RHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1543
1544	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1545	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1546	* 2. write protect all shadowed pages. I.e. implement caching.
1547	*/
1548	/** @todo duplicated in the 2nd half of pgmPoolTracDerefGCPhysHint */
1549
1550	/*
1551	* Find the guest address.
1552	*/
1553	for (PPGMRAMRANGE pRam = pVM->pgm.s.CTX_SUFF(pRamRangesX);
1554	pRam;
1555	pRam = pRam->CTX_SUFF(pNext))
1556	{
1557	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1558	while (iPage-- > 0)
1559	{
1560	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1561	{
1562	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1563
1564	Assert(pShwPage->cPresent);
1565	Assert(pPool->cPresent);
1566	pShwPage->cPresent--;
1567	pPool->cPresent--;
1568
1569	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage], iPte);
1570	STAM_PROFILE_STOP(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackDeref, a);
1571	return;
1572	}
1573	}
1574	}
1575
1576	for (;;)
1577	AssertReleaseMsgFailed(("HCPhys=%RHp wasn't found!\n", HCPhys));
1578	}
1579
1580
1581	/**
1582	* Update the tracking of shadowed pages.
1583	*
1584	* @param pVCpu The cross context virtual CPU structure.
1585	* @param pShwPage The shadow page.
1586	* @param u16 The top 16-bit of the pPage->HCPhys.
1587	* @param pPage Pointer to the guest page. this will be modified.
1588	* @param iPTDst The index into the shadow table.
1589	*/
1590	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVMCPU pVCpu, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1591	{
1592	PVM pVM = pVCpu->CTX_SUFF(pVM);
1593
1594	/*
1595	* Just deal with the simple first time here.
1596	*/
1597	if (!u16)
1598	{
1599	STAM_COUNTER_INC(&pVM->pgm.s.CTX_SUFF(pStats)->StatTrackVirgin);
1600	u16 = PGMPOOL_TD_MAKE(1, pShwPage->idx);
1601	/* Save the page table index. */
1602	PGM_PAGE_SET_PTE_INDEX(pVM, pPage, iPTDst);
1603	}
1604	else
1605	u16 = pgmPoolTrackPhysExtAddref(pVM, pPage, u16, pShwPage->idx, iPTDst);
1606
1607	/* write back */
1608	Log2(("SyncPageWorkerTrackAddRef: u16=%#x->%#x iPTDst=%#x\n", u16, PGM_PAGE_GET_TRACKING(pPage), iPTDst));
1609	PGM_PAGE_SET_TRACKING(pVM, pPage, u16);
1610
1611	/* update statistics. */
1612	pVM->pgm.s.CTX_SUFF(pPool)->cPresent++;
1613	pShwPage->cPresent++;
1614	if (pShwPage->iFirstPresent > iPTDst)
1615	pShwPage->iFirstPresent = iPTDst;
1616	}
1617
1618
1619	/**
1620	* Modifies a shadow PTE to account for access handlers.
1621	*
1622	* @param pVM The cross context VM structure.
1623	* @param pPage The page in question.
1624	* @param fPteSrc The shadowed flags of the source PTE. Must include the
1625	* A (accessed) bit so it can be emulated correctly.
1626	* @param pPteDst The shadow PTE (output). This is temporary storage and
1627	* does not need to be set atomically.
1628	*/
1629	DECLINLINE(void) PGM_BTH_NAME(SyncHandlerPte)(PVM pVM, PCPGMPAGE pPage, uint64_t fPteSrc, PSHWPTE pPteDst)
1630	{
1631	NOREF(pVM); RT_NOREF_PV(fPteSrc);
1632
1633	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No.
1634	* Update: \#PF should deal with this before or after calling the handlers. It has all the info to do the job efficiently. */
1635	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1636	{
1637	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
1638	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1639	pPteDst->u = PGM_PAGE_GET_HCPHYS(pPage);
1640	pPteDst->n.u1Present = 1;
1641	pPteDst->n.u1Execute = 1;
1642	pPteDst->n.u1IgnorePAT = 1;
1643	pPteDst->n.u3EMT = VMX_EPT_MEMTYPE_WB;
1644	/* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
1645	#else
1646	if (fPteSrc & X86_PTE_A)
1647	{
1648	SHW_PTE_SET(*pPteDst, fPteSrc \| PGM_PAGE_GET_HCPHYS(pPage));
1649	SHW_PTE_SET_RO(*pPteDst);
1650	}
1651	else
1652	SHW_PTE_SET(*pPteDst, 0);
1653	#endif
1654	}
1655	#ifdef PGM_WITH_MMIO_OPTIMIZATIONS
1656	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
1657	else if ( PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
1658	&& ( BTH_IS_NP_ACTIVE(pVM)
1659	\|\| (fPteSrc & (X86_PTE_RW \| X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
1660	# if PGM_SHW_TYPE == PGM_TYPE_AMD64
1661	&& pVM->pgm.s.fLessThan52PhysicalAddressBits
1662	# endif
1663	)
1664	{
1665	LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
1666	# if PGM_SHW_TYPE == PGM_TYPE_EPT
1667	/* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
1668	pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
1669	/* 25.2.3.1: bits 2:0 = 010b -> EPT Misconfiguration (exit 49) */
1670	pPteDst->n.u1Present = 0;
1671	pPteDst->n.u1Write = 1;
1672	pPteDst->n.u1Execute = 0;
1673	/* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
1674	pPteDst->n.u3EMT = 7;
1675	# else
1676	/* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64). */
1677	SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg \| X86_PTE_PAE_MBZ_MASK_NO_NX \| X86_PTE_P);
1678	# endif
1679	}
1680	# endif
1681	#endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
1682	else
1683	{
1684	LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark not present\n", pPage));
1685	SHW_PTE_SET(*pPteDst, 0);
1686	}
1687	/** @todo count these kinds of entries. */
1688	}
1689
1690
1691	/**
1692	* Creates a 4K shadow page for a guest page.
1693	*
1694	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1695	* physical address. The PdeSrc argument only the flags are used. No page
1696	* structured will be mapped in this function.
1697	*
1698	* @param pVCpu The cross context virtual CPU structure.
1699	* @param pPteDst Destination page table entry.
1700	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1701	* Can safely assume that only the flags are being used.
1702	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1703	* @param pShwPage Pointer to the shadow page.
1704	* @param iPTDst The index into the shadow table.
1705	*
1706	* @remark Not used for 2/4MB pages!
1707	*/
1708	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \|\| defined(DOXYGEN_RUNNING)
1709	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
1710	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1711	#else
1712	static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
1713	PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1714	#endif
1715	{
1716	PVM pVM = pVCpu->CTX_SUFF(pVM);
1717	RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
1718
1719	#if defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
1720	&& PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
1721	&& (PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
1722
1723	if (pShwPage->fDirty)
1724	{
1725	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
1726	PGSTPT pGstPT;
1727
1728	/* Note that iPTDst can be used to index the guest PT even in the pae/32bit combo as we copy only half the table; see pgmPoolAddDirtyPage. */
1729	pGstPT = (PGSTPT)&pPool->aDirtyPages[pShwPage->idxDirtyEntry].aPage[0];
1730	GCPhysOldPage = GST_GET_PTE_GCPHYS(pGstPT->a[iPTDst]);
1731	pGstPT->a[iPTDst].u = PteSrc.u;
1732	}
1733	#else
1734	Assert(!pShwPage->fDirty);
1735	#endif
1736
1737	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1738	if ( PteSrc.n.u1Present
1739	&& GST_IS_PTE_VALID(pVCpu, PteSrc))
1740	#endif
1741	{
1742	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1743	RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
1744	# endif
1745	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
1746
1747	/*
1748	* Find the ram range.
1749	*/
1750	PPGMPAGE pPage;
1751	int rc = pgmPhysGetPageEx(pVM, GCPhysPage, &pPage);
1752	if (RT_SUCCESS(rc))
1753	{
1754	/* Ignore ballooned pages.
1755	Don't return errors or use a fatal assert here as part of a
1756	shadow sync range might included ballooned pages. */
1757	if (PGM_PAGE_IS_BALLOONED(pPage))
1758	{
1759	Assert(!SHW_PTE_IS_P(pPteDst)); /* @todo user tracking needs updating if this triggers. */
1760	return;
1761	}
1762
1763	#ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
1764	/* Make the page writable if necessary. */
1765	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
1766	&& ( PGM_PAGE_IS_ZERO(pPage)
1767	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1768	\|\| ( PteSrc.n.u1Write
1769	# else
1770	\|\| ( 1
1771	# endif
1772	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
1773	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
1774	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
1775	# endif
1776	# ifdef VBOX_WITH_PAGE_SHARING
1777	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
1778	# endif
1779	)
1780	)
1781	)
1782	{
1783	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhysPage);
1784	AssertRC(rc);
1785	}
1786	#endif
1787
1788	/*
1789	* Make page table entry.
1790	*/
1791	SHWPTE PteDst;
1792	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1793	uint64_t fGstShwPteFlags = GST_GET_PTE_SHW_FLAGS(pVCpu, PteSrc);
1794	# else
1795	uint64_t fGstShwPteFlags = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_A \| X86_PTE_D;
1796	# endif
1797	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1798	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, fGstShwPteFlags, &PteDst);
1799	else
1800	{
1801	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1802	/*
1803	* If the page or page directory entry is not marked accessed,
1804	* we mark the page not present.
1805	*/
1806	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1807	{
1808	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1809	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,AccessedPage));
1810	SHW_PTE_SET(PteDst, 0);
1811	}
1812	/*
1813	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1814	* when the page is modified.
1815	*/
1816	else if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1817	{
1818	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPage));
1819	SHW_PTE_SET(PteDst,
1820	fGstShwPteFlags
1821	\| PGM_PAGE_GET_HCPHYS(pPage)
1822	\| PGM_PTFLAGS_TRACK_DIRTY);
1823	SHW_PTE_SET_RO(PteDst);
1824	}
1825	else
1826	#endif
1827	{
1828	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
1829	#if PGM_SHW_TYPE == PGM_TYPE_EPT
1830	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage);
1831	PteDst.n.u1Present = 1;
1832	PteDst.n.u1Write = 1;
1833	PteDst.n.u1Execute = 1;
1834	PteDst.n.u1IgnorePAT = 1;
1835	PteDst.n.u3EMT = VMX_EPT_MEMTYPE_WB;
1836	/* PteDst.n.u1Size = 0 */
1837	#else
1838	SHW_PTE_SET(PteDst, fGstShwPteFlags \| PGM_PAGE_GET_HCPHYS(pPage));
1839	#endif
1840	}
1841
1842	/*
1843	* Make sure only allocated pages are mapped writable.
1844	*/
1845	if ( SHW_PTE_IS_P_RW(PteDst)
1846	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
1847	{
1848	/* Still applies to shared pages. */
1849	Assert(!PGM_PAGE_IS_ZERO(pPage));
1850	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet. Why, isn't it? */
1851	Log3(("SyncPageWorker: write-protecting %RGp pPage=%R[pgmpage]at iPTDst=%d\n", GCPhysPage, pPage, iPTDst));
1852	}
1853	}
1854
1855	/*
1856	* Keep user track up to date.
1857	*/
1858	if (SHW_PTE_IS_P(PteDst))
1859	{
1860	if (!SHW_PTE_IS_P(*pPteDst))
1861	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1862	else if (SHW_PTE_GET_HCPHYS(*pPteDst) != SHW_PTE_GET_HCPHYS(PteDst))
1863	{
1864	Log2(("SyncPageWorker: deref! pPteDst=%RX64 PteDst=%RX64\n", SHW_PTE_LOG64(pPteDst), SHW_PTE_LOG64(PteDst)));
1865	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1866	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
1867	}
1868	}
1869	else if (SHW_PTE_IS_P(*pPteDst))
1870	{
1871	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1872	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1873	}
1874
1875	/*
1876	* Update statistics and commit the entry.
1877	*/
1878	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1879	if (!PteSrc.n.u1Global)
1880	pShwPage->fSeenNonGlobal = true;
1881	#endif
1882	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
1883	return;
1884	}
1885
1886	/** @todo count these three different kinds. */
1887	Log2(("SyncPageWorker: invalid address in Pte\n"));
1888	}
1889	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
1890	else if (!PteSrc.n.u1Present)
1891	Log2(("SyncPageWorker: page not present in Pte\n"));
1892	else
1893	Log2(("SyncPageWorker: invalid Pte\n"));
1894	#endif
1895
1896	/*
1897	* The page is not present or the PTE is bad. Replace the shadow PTE by
1898	* an empty entry, making sure to keep the user tracking up to date.
1899	*/
1900	if (SHW_PTE_IS_P(*pPteDst))
1901	{
1902	Log2(("SyncPageWorker: deref! pPteDst=%RX64\n", SHW_PTE_LOG64(pPteDst)));
1903	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVCpu, pShwPage, SHW_PTE_GET_HCPHYS(*pPteDst), iPTDst, GCPhysOldPage);
1904	}
1905	SHW_PTE_ATOMIC_SET(*pPteDst, 0);
1906	}
1907
1908
1909	/**
1910	* Syncs a guest OS page.
1911	*
1912	* There are no conflicts at this point, neither is there any need for
1913	* page table allocations.
1914	*
1915	* When called in PAE or AMD64 guest mode, the guest PDPE shall be valid.
1916	* When called in AMD64 guest mode, the guest PML4E shall be valid.
1917	*
1918	* @returns VBox status code.
1919	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1920	* @param pVCpu The cross context virtual CPU structure.
1921	* @param PdeSrc Page directory entry of the guest.
1922	* @param GCPtrPage Guest context page address.
1923	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1924	* @param uErr Fault error (X86_TRAP_PF_*).
1925	*/
1926	static int PGM_BTH_NAME(SyncPage)(PVMCPU pVCpu, GSTPDE PdeSrc, RTGCPTR GCPtrPage, unsigned cPages, unsigned uErr)
1927	{
1928	PVM pVM = pVCpu->CTX_SUFF(pVM);
1929	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
1930	LogFlow(("SyncPage: GCPtrPage=%RGv cPages=%u uErr=%#x\n", GCPtrPage, cPages, uErr));
1931	RT_NOREF_PV(uErr); RT_NOREF_PV(cPages); RT_NOREF_PV(GCPtrPage);
1932
1933	PGM_LOCK_ASSERT_OWNER(pVM);
1934
1935	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
1936	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
1937	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
1938	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
1939	&& PGM_SHW_TYPE != PGM_TYPE_EPT
1940
1941	/*
1942	* Assert preconditions.
1943	*/
1944	Assert(PdeSrc.n.u1Present);
1945	Assert(cPages);
1946	# if 0 /* rarely useful; leave for debugging. */
1947	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1948	# endif
1949
1950	/*
1951	* Get the shadow PDE, find the shadow page table in the pool.
1952	*/
1953	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1954	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1955	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
1956
1957	/* Fetch the pgm pool shadow descriptor. */
1958	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
1959	Assert(pShwPde);
1960
1961	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
1962	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1963	PPGMPOOLPAGE pShwPde = NULL;
1964	PX86PDPAE pPDDst;
1965
1966	/* Fetch the pgm pool shadow descriptor. */
1967	int rc2 = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
1968	AssertRCSuccessReturn(rc2, rc2);
1969	Assert(pShwPde);
1970
1971	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
1972	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1973
1974	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
1975	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
1976	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
1977	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
1978	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
1979
1980	int rc2 = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
1981	AssertRCSuccessReturn(rc2, rc2);
1982	Assert(pPDDst && pPdptDst);
1983	PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
1984	# endif
1985	SHWPDE PdeDst = *pPdeDst;
1986
1987	/*
1988	* - In the guest SMP case we could have blocked while another VCPU reused
1989	* this page table.
1990	* - With W7-64 we may also take this path when the A bit is cleared on
1991	* higher level tables (PDPE/PML4E). The guest does not invalidate the
1992	* relevant TLB entries. If we're write monitoring any page mapped by
1993	* the modified entry, we may end up here with a "stale" TLB entry.
1994	*/
1995	if (!PdeDst.n.u1Present)
1996	{
1997	Log(("CPU%u: SyncPage: Pde at %RGv changed behind our back? (pPdeDst=%p/%RX64) uErr=%#x\n", pVCpu->idCpu, GCPtrPage, pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
1998	AssertMsg(pVM->cCpus > 1 \|\| (uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RW)) == (X86_TRAP_PF_P \| X86_TRAP_PF_RW),
1999	("Unexpected missing PDE p=%p/%RX64 uErr=%#x\n", pPdeDst, (uint64_t)PdeDst.u, (uint32_t)uErr));
2000	if (uErr & X86_TRAP_PF_P)
2001	PGM_INVL_PG(pVCpu, GCPtrPage);
2002	return VINF_SUCCESS; /* force the instruction to be executed again. */
2003	}
2004
2005	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2006	Assert(pShwPage);
2007
2008	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2009	/* Fetch the pgm pool shadow descriptor. */
2010	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2011	Assert(pShwPde);
2012	# endif
2013
2014	/*
2015	* Check that the page is present and that the shadow PDE isn't out of sync.
2016	*/
2017	const bool fBigPage = PdeSrc.b.u1Size && GST_IS_PSE_ACTIVE(pVCpu);
2018	const bool fPdeValid = !fBigPage ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc);
2019	RTGCPHYS GCPhys;
2020	if (!fBigPage)
2021	{
2022	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2023	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2024	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2025	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2026	# endif
2027	}
2028	else
2029	{
2030	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2031	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2032	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2033	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2034	# endif
2035	}
2036	/** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
2037	if ( fPdeValid
2038	&& pShwPage->GCPhys == GCPhys
2039	&& PdeSrc.n.u1Present
2040	&& PdeSrc.n.u1User == PdeDst.n.u1User
2041	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
2042	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2043	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute \|\| !GST_IS_NX_ACTIVE(pVCpu))
2044	# endif
2045	)
2046	{
2047	/*
2048	* Check that the PDE is marked accessed already.
2049	* Since we set the accessed bit before getting here on a #PF, this
2050	* check is only meant for dealing with non-#PF'ing paths.
2051	*/
2052	if (PdeSrc.n.u1Accessed)
2053	{
2054	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2055	if (!fBigPage)
2056	{
2057	/*
2058	* 4KB Page - Map the guest page table.
2059	*/
2060	PGSTPT pPTSrc;
2061	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2062	if (RT_SUCCESS(rc))
2063	{
2064	# ifdef PGM_SYNC_N_PAGES
2065	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2066	if ( cPages > 1
2067	&& !(uErr & X86_TRAP_PF_P)
2068	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2069	{
2070	/*
2071	* This code path is currently only taken when the caller is PGMTrap0eHandler
2072	* for non-present pages!
2073	*
2074	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2075	* deal with locality.
2076	*/
2077	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2078	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2079	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2080	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2081	# else
2082	const unsigned offPTSrc = 0;
2083	# endif
2084	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2085	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2086	iPTDst = 0;
2087	else
2088	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2089
2090	for (; iPTDst < iPTDstEnd; iPTDst++)
2091	{
2092	const PGSTPTE pPteSrc = &pPTSrc->a[offPTSrc + iPTDst];
2093
2094	if ( pPteSrc->n.u1Present
2095	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2096	{
2097	RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
2098	NOREF(GCPtrCurPage);
2099	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2100	/*
2101	* Assuming kernel code will be marked as supervisor - and not as user level
2102	* and executed using a conforming code selector - And marked as readonly.
2103	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2104	*/
2105	PPGMPAGE pPage;
2106	if ( ((PdeSrc.u & pPteSrc->u) & (X86_PTE_RW \| X86_PTE_US))
2107	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
2108	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCurPage)
2109	\|\| ( (pPage = pgmPhysGetPage(pVM, pPteSrc->u & GST_PTE_PG_MASK))
2110	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2111	)
2112	# endif /* else: CSAM not active */
2113	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
2114	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
2115	GCPtrCurPage, pPteSrc->n.u1Present,
2116	pPteSrc->n.u1Write & PdeSrc.n.u1Write,
2117	pPteSrc->n.u1User & PdeSrc.n.u1User,
2118	(uint64_t)pPteSrc->u,
2119	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2120	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2121	}
2122	}
2123	}
2124	else
2125	# endif /* PGM_SYNC_N_PAGES */
2126	{
2127	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
2128	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2129	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2130	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2131	Log2(("SyncPage: 4K %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx %s\n",
2132	GCPtrPage, PteSrc.n.u1Present,
2133	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2134	PteSrc.n.u1User & PdeSrc.n.u1User,
2135	(uint64_t)PteSrc.u,
2136	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2137	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2138	}
2139	}
2140	else /* MMIO or invalid page: emulated in #PF handler. */
2141	{
2142	LogFlow(("PGM_GCPHYS_2_PTR %RGp failed with %Rrc\n", GCPhys, rc));
2143	Assert(!SHW_PTE_IS_P(pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK]));
2144	}
2145	}
2146	else
2147	{
2148	/*
2149	* 4/2MB page - lazy syncing shadow 4K pages.
2150	* (There are many causes of getting here, it's no longer only CSAM.)
2151	*/
2152	/* Calculate the GC physical address of this 4KB shadow page. */
2153	GCPhys = PGM_A20_APPLY(pVCpu, GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc) \| (GCPtrPage & GST_BIG_PAGE_OFFSET_MASK));
2154	/* Find ram range. */
2155	PPGMPAGE pPage;
2156	int rc = pgmPhysGetPageEx(pVM, GCPhys, &pPage);
2157	if (RT_SUCCESS(rc))
2158	{
2159	AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
2160
2161	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
2162	/* Try to make the page writable if necessary. */
2163	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
2164	&& ( PGM_PAGE_IS_ZERO(pPage)
2165	\|\| ( PdeSrc.n.u1Write
2166	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
2167	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
2168	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
2169	# endif
2170	# ifdef VBOX_WITH_PAGE_SHARING
2171	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
2172	# endif
2173	)
2174	)
2175	)
2176	{
2177	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
2178	AssertRC(rc);
2179	}
2180	# endif
2181
2182	/*
2183	* Make shadow PTE entry.
2184	*/
2185	SHWPTE PteDst;
2186	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2187	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc), &PteDst);
2188	else
2189	SHW_PTE_SET(PteDst, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc) \| PGM_PAGE_GET_HCPHYS(pPage));
2190
2191	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2192	if ( SHW_PTE_IS_P(PteDst)
2193	&& !SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2194	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
2195
2196	/* Make sure only allocated pages are mapped writable. */
2197	if ( SHW_PTE_IS_P_RW(PteDst)
2198	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
2199	{
2200	/* Still applies to shared pages. */
2201	Assert(!PGM_PAGE_IS_ZERO(pPage));
2202	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
2203	Log3(("SyncPage: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, GCPtrPage));
2204	}
2205
2206	SHW_PTE_ATOMIC_SET2(pPTDst->a[iPTDst], PteDst);
2207
2208	/*
2209	* If the page is not flagged as dirty and is writable, then make it read-only
2210	* at PD level, so we can set the dirty bit when the page is modified.
2211	*
2212	* ASSUMES that page access handlers are implemented on page table entry level.
2213	* Thus we will first catch the dirty access and set PDE.D and restart. If
2214	* there is an access handler, we'll trap again and let it work on the problem.
2215	*/
2216	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
2217	* As for invlpg, it simply frees the whole shadow PT.
2218	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
2219	if ( !PdeSrc.b.u1Dirty
2220	&& PdeSrc.b.u1Write)
2221	{
2222	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2223	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2224	PdeDst.n.u1Write = 0;
2225	}
2226	else
2227	{
2228	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2229	PdeDst.n.u1Write = PdeSrc.n.u1Write;
2230	}
2231	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2232	Log2(("SyncPage: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%RGp%s\n",
2233	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
2234	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2235	}
2236	else
2237	{
2238	LogFlow(("PGM_GCPHYS_2_PTR %RGp (big) failed with %Rrc\n", GCPhys, rc));
2239	/** @todo must wipe the shadow page table entry in this
2240	* case. */
2241	}
2242	}
2243	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2244	return VINF_SUCCESS;
2245	}
2246
2247	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDNAs));
2248	}
2249	else if (fPdeValid)
2250	{
2251	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPagePDOutOfSync));
2252	Log2(("SyncPage: Out-Of-Sync PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2253	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2254	}
2255	else
2256	{
2257	/// @todo STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_MID_Z(Stat,SyncPagePDOutOfSyncAndInvalid));
2258	Log2(("SyncPage: Bad PDE at %RGp PdeSrc=%RX64 PdeDst=%RX64 (GCPhys %RGp vs %RGp)\n",
2259	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, GCPhys));
2260	}
2261
2262	/*
2263	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
2264	* Yea, I'm lazy.
2265	*/
2266	pgmPoolFreeByPage(pPool, pShwPage, pShwPde->idx, iPDDst);
2267	ASMAtomicWriteSize(pPdeDst, 0);
2268
2269	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2270	PGM_INVL_VCPU_TLBS(pVCpu);
2271	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
2272
2273
2274	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2275	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2276	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
2277	&& !defined(IN_RC)
2278	NOREF(PdeSrc);
2279
2280	# ifdef PGM_SYNC_N_PAGES
2281	/*
2282	* Get the shadow PDE, find the shadow page table in the pool.
2283	*/
2284	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2285	X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
2286
2287	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2288	X86PDEPAE PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
2289
2290	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2291	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2292	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
2293	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2294	X86PDEPAE PdeDst;
2295	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2296
2297	int rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2298	AssertRCSuccessReturn(rc, rc);
2299	Assert(pPDDst && pPdptDst);
2300	PdeDst = pPDDst->a[iPDDst];
2301	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
2302	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
2303	PEPTPD pPDDst;
2304	EPTPDE PdeDst;
2305
2306	int rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, NULL, &pPDDst);
2307	if (rc != VINF_SUCCESS)
2308	{
2309	AssertRC(rc);
2310	return rc;
2311	}
2312	Assert(pPDDst);
2313	PdeDst = pPDDst->a[iPDDst];
2314	# endif
2315	/* In the guest SMP case we could have blocked while another VCPU reused this page table. */
2316	if (!PdeDst.n.u1Present)
2317	{
2318	AssertMsg(pVM->cCpus > 1, ("Unexpected missing PDE %RX64\n", (uint64_t)PdeDst.u));
2319	Log(("CPU%d: SyncPage: Pde at %RGv changed behind our back!\n", pVCpu->idCpu, GCPtrPage));
2320	return VINF_SUCCESS; /* force the instruction to be executed again. */
2321	}
2322
2323	/* Can happen in the guest SMP case; other VCPU activated this PDE while we were blocking to handle the page fault. */
2324	if (PdeDst.n.u1Size)
2325	{
2326	Assert(pVM->pgm.s.fNestedPaging);
2327	Log(("CPU%d: SyncPage: Pde (big:%RX64) at %RGv changed behind our back!\n", pVCpu->idCpu, PdeDst.u, GCPtrPage));
2328	return VINF_SUCCESS;
2329	}
2330
2331	/* Mask away the page offset. */
2332	GCPtrPage &= ~((RTGCPTR)0xfff);
2333
2334	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2335	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2336
2337	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
2338	if ( cPages > 1
2339	&& !(uErr & X86_TRAP_PF_P)
2340	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
2341	{
2342	/*
2343	* This code path is currently only taken when the caller is PGMTrap0eHandler
2344	* for non-present pages!
2345	*
2346	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
2347	* deal with locality.
2348	*/
2349	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2350	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2351	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
2352	iPTDst = 0;
2353	else
2354	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2355	for (; iPTDst < iPTDstEnd; iPTDst++)
2356	{
2357	if (!SHW_PTE_IS_P(pPTDst->a[iPTDst]))
2358	{
2359	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2360	\| (iPTDst << PAGE_SHIFT));
2361
2362	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2363	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
2364	GCPtrCurPage,
2365	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2366	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2367
2368	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
2369	break;
2370	}
2371	else
2372	Log4(("%RGv iPTDst=%x pPTDst->a[iPTDst] %RX64\n", (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT)) \| (iPTDst << PAGE_SHIFT), iPTDst, SHW_PTE_LOG64(pPTDst->a[iPTDst]) ));
2373	}
2374	}
2375	else
2376	# endif /* PGM_SYNC_N_PAGES */
2377	{
2378	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2379	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
2380	\| (iPTDst << PAGE_SHIFT));
2381
2382	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
2383
2384	Log2(("SyncPage: 4K %RGv PteSrc:{P=1 RW=1 U=1}PteDst=%08llx%s\n",
2385	GCPtrPage,
2386	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
2387	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
2388	}
2389	return VINF_SUCCESS;
2390
2391	#else
2392	NOREF(PdeSrc);
2393	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2394	return VERR_PGM_NOT_USED_IN_MODE;
2395	#endif
2396	}
2397
2398
2399	#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
2400
2401	/**
2402	* CheckPageFault helper for returning a page fault indicating a non-present
2403	* (NP) entry in the page translation structures.
2404	*
2405	* @returns VINF_EM_RAW_GUEST_TRAP.
2406	* @param pVCpu The cross context virtual CPU structure.
2407	* @param uErr The error code of the shadow fault. Corrections to
2408	* TRPM's copy will be made if necessary.
2409	* @param GCPtrPage For logging.
2410	* @param uPageFaultLevel For logging.
2411	*/
2412	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnNP)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2413	{
2414	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2415	AssertMsg(!(uErr & X86_TRAP_PF_P), ("%#x\n", uErr));
2416	AssertMsg(!(uErr & X86_TRAP_PF_RSVD), ("%#x\n", uErr));
2417	if (uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2418	TRPMSetErrorCode(pVCpu, uErr & ~(X86_TRAP_PF_RSVD \| X86_TRAP_PF_P));
2419
2420	Log(("CheckPageFault: real page fault (notp) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2421	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2422	return VINF_EM_RAW_GUEST_TRAP;
2423	}
2424
2425
2426	/**
2427	* CheckPageFault helper for returning a page fault indicating a reserved bit
2428	* (RSVD) error in the page translation structures.
2429	*
2430	* @returns VINF_EM_RAW_GUEST_TRAP.
2431	* @param pVCpu The cross context virtual CPU structure.
2432	* @param uErr The error code of the shadow fault. Corrections to
2433	* TRPM's copy will be made if necessary.
2434	* @param GCPtrPage For logging.
2435	* @param uPageFaultLevel For logging.
2436	*/
2437	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnRSVD)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2438	{
2439	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2440	if ((uErr & (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P)) != (X86_TRAP_PF_RSVD \| X86_TRAP_PF_P))
2441	TRPMSetErrorCode(pVCpu, uErr \| X86_TRAP_PF_RSVD \| X86_TRAP_PF_P);
2442
2443	Log(("CheckPageFault: real page fault (rsvd) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2444	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2445	return VINF_EM_RAW_GUEST_TRAP;
2446	}
2447
2448
2449	/**
2450	* CheckPageFault helper for returning a page protection fault (P).
2451	*
2452	* @returns VINF_EM_RAW_GUEST_TRAP.
2453	* @param pVCpu The cross context virtual CPU structure.
2454	* @param uErr The error code of the shadow fault. Corrections to
2455	* TRPM's copy will be made if necessary.
2456	* @param GCPtrPage For logging.
2457	* @param uPageFaultLevel For logging.
2458	*/
2459	DECLINLINE(int) PGM_BTH_NAME(CheckPageFaultReturnProt)(PVMCPU pVCpu, uint32_t uErr, RTGCPTR GCPtrPage, unsigned uPageFaultLevel)
2460	{
2461	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyTrackRealPF));
2462	AssertMsg(uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_US \| X86_TRAP_PF_ID), ("%#x\n", uErr));
2463	if ((uErr & (X86_TRAP_PF_P \| X86_TRAP_PF_RSVD)) != X86_TRAP_PF_P)
2464	TRPMSetErrorCode(pVCpu, (uErr & ~X86_TRAP_PF_RSVD) \| X86_TRAP_PF_P);
2465
2466	Log(("CheckPageFault: real page fault (prot) at %RGv (%d)\n", GCPtrPage, uPageFaultLevel));
2467	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(uPageFaultLevel);
2468	return VINF_EM_RAW_GUEST_TRAP;
2469	}
2470
2471
2472	/**
2473	* Handle dirty bit tracking faults.
2474	*
2475	* @returns VBox status code.
2476	* @param pVCpu The cross context virtual CPU structure.
2477	* @param uErr Page fault error code.
2478	* @param pPdeSrc Guest page directory entry.
2479	* @param pPdeDst Shadow page directory entry.
2480	* @param GCPtrPage Guest context page address.
2481	*/
2482	static int PGM_BTH_NAME(CheckDirtyPageFault)(PVMCPU pVCpu, uint32_t uErr, PSHWPDE pPdeDst, GSTPDE const *pPdeSrc,
2483	RTGCPTR GCPtrPage)
2484	{
2485	PVM pVM = pVCpu->CTX_SUFF(pVM);
2486	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
2487	NOREF(uErr);
2488
2489	PGM_LOCK_ASSERT_OWNER(pVM);
2490
2491	/*
2492	* Handle big page.
2493	*/
2494	if (pPdeSrc->b.u1Size && GST_IS_PSE_ACTIVE(pVCpu))
2495	{
2496	if ( pPdeDst->n.u1Present
2497	&& (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
2498	{
2499	SHWPDE PdeDst = *pPdeDst;
2500
2501	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2502	Assert(pPdeSrc->b.u1Write);
2503
2504	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB entry will not harm; write access will simply
2505	* fault again and take this path to only invalidate the entry (see below).
2506	*/
2507	PdeDst.n.u1Write = 1;
2508	PdeDst.n.u1Accessed = 1;
2509	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
2510	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2511	PGM_INVL_BIG_PG(pVCpu, GCPtrPage);
2512	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2513	}
2514
2515	# ifdef IN_RING0
2516	/* Check for stale TLB entry; only applies to the SMP guest case. */
2517	if ( pVM->cCpus > 1
2518	&& pPdeDst->n.u1Write
2519	&& pPdeDst->n.u1Accessed)
2520	{
2521	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2522	if (pShwPage)
2523	{
2524	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2525	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2526	if (SHW_PTE_IS_P_RW(*pPteDst))
2527	{
2528	/* Stale TLB entry. */
2529	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2530	PGM_INVL_PG(pVCpu, GCPtrPage);
2531	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2532	}
2533	}
2534	}
2535	# endif /* IN_RING0 */
2536	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2537	}
2538
2539	/*
2540	* Map the guest page table.
2541	*/
2542	PGSTPT pPTSrc;
2543	int rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GST_GET_PDE_GCPHYS(*pPdeSrc), &pPTSrc);
2544	if (RT_FAILURE(rc))
2545	{
2546	AssertRC(rc);
2547	return rc;
2548	}
2549
2550	if (pPdeDst->n.u1Present)
2551	{
2552	GSTPTE const *pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
2553	const GSTPTE PteSrc = *pPteSrc;
2554
2555	#ifdef VBOX_WITH_RAW_MODE_NOT_R0
2556	/* Bail out here as pgmPoolGetPage will return NULL and we'll crash below.
2557	* Our individual shadow handlers will provide more information and force a fatal exit.
2558	*/
2559	if ( !HMIsEnabled(pVM)
2560	&& MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
2561	{
2562	LogRel(("CheckPageFault: write to hypervisor region %RGv\n", GCPtrPage));
2563	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2564	}
2565	#endif
2566	/*
2567	* Map shadow page table.
2568	*/
2569	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, pPdeDst->u & SHW_PDE_PG_MASK);
2570	if (pShwPage)
2571	{
2572	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2573	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
2574	if (SHW_PTE_IS_P(pPteDst)) /* @todo Optimize accessed bit emulation? */
2575	{
2576	if (SHW_PTE_IS_TRACK_DIRTY(*pPteDst))
2577	{
2578	PPGMPAGE pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc));
2579	SHWPTE PteDst = *pPteDst;
2580
2581	LogFlow(("DIRTY page trap addr=%RGv\n", GCPtrPage));
2582	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageTrap));
2583
2584	Assert(PteSrc.n.u1Write);
2585
2586	/* Note: No need to invalidate this entry on other VCPUs as a stale TLB
2587	* entry will not harm; write access will simply fault again and
2588	* take this path to only invalidate the entry.
2589	*/
2590	if (RT_LIKELY(pPage))
2591	{
2592	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2593	{
2594	//AssertMsgFailed(("%R[pgmpage] - we don't set PGM_PTFLAGS_TRACK_DIRTY for these pages\n", pPage));
2595	Assert(!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage));
2596	/* Assuming write handlers here as the PTE is present (otherwise we wouldn't be here). */
2597	SHW_PTE_SET_RO(PteDst);
2598	}
2599	else
2600	{
2601	if ( PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_WRITE_MONITORED
2602	&& PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM)
2603	{
2604	rc = pgmPhysPageMakeWritable(pVM, pPage, GST_GET_PTE_GCPHYS(PteSrc));
2605	AssertRC(rc);
2606	}
2607	if (PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED)
2608	SHW_PTE_SET_RW(PteDst);
2609	else
2610	{
2611	/* Still applies to shared pages. */
2612	Assert(!PGM_PAGE_IS_ZERO(pPage));
2613	SHW_PTE_SET_RO(PteDst);
2614	}
2615	}
2616	}
2617	else
2618	SHW_PTE_SET_RW(PteDst); /** @todo r=bird: This doesn't make sense to me. */
2619
2620	SHW_PTE_SET(PteDst, (SHW_PTE_GET_U(PteDst) \| X86_PTE_D \| X86_PTE_A) & ~(uint64_t)PGM_PTFLAGS_TRACK_DIRTY);
2621	SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
2622	PGM_INVL_PG(pVCpu, GCPtrPage);
2623	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2624	}
2625
2626	# ifdef IN_RING0
2627	/* Check for stale TLB entry; only applies to the SMP guest case. */
2628	if ( pVM->cCpus > 1
2629	&& SHW_PTE_IS_RW(*pPteDst)
2630	&& SHW_PTE_IS_A(*pPteDst))
2631	{
2632	/* Stale TLB entry. */
2633	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageStale));
2634	PGM_INVL_PG(pVCpu, GCPtrPage);
2635	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT; /* restarts the instruction. */
2636	}
2637	# endif
2638	}
2639	}
2640	else
2641	AssertMsgFailed(("pgmPoolGetPageByHCPhys %RGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
2642	}
2643
2644	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
2645	}
2646
2647	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
2648
2649
2650	/**
2651	* Sync a shadow page table.
2652	*
2653	* The shadow page table is not present in the shadow PDE.
2654	*
2655	* Handles mapping conflicts.
2656	*
2657	* This is called by VerifyAccessSyncPage, PrefetchPage, InvalidatePage (on
2658	* conflict), and Trap0eHandler.
2659	*
2660	* A precondition for this method is that the shadow PDE is not present. The
2661	* caller must take the PGM lock before checking this and continue to hold it
2662	* when calling this method.
2663	*
2664	* @returns VBox status code.
2665	* @param pVCpu The cross context virtual CPU structure.
2666	* @param iPDSrc Page directory index.
2667	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
2668	* Assume this is a temporary mapping.
2669	* @param GCPtrPage GC Pointer of the page that caused the fault
2670	*/
2671	static int PGM_BTH_NAME(SyncPT)(PVMCPU pVCpu, unsigned iPDSrc, PGSTPD pPDSrc, RTGCPTR GCPtrPage)
2672	{
2673	PVM pVM = pVCpu->CTX_SUFF(pVM);
2674	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
2675
2676	#if 0 /* rarely useful; leave for debugging. */
2677	STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPtPD[iPDSrc]);
2678	#endif
2679	LogFlow(("SyncPT: GCPtrPage=%RGv\n", GCPtrPage)); RT_NOREF_PV(GCPtrPage);
2680
2681	PGM_LOCK_ASSERT_OWNER(pVM);
2682
2683	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2684	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
2685	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64) \
2686	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
2687	&& PGM_SHW_TYPE != PGM_TYPE_EPT
2688
2689	int rc = VINF_SUCCESS;
2690
2691	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2692
2693	/*
2694	* Some input validation first.
2695	*/
2696	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%RGv\n", iPDSrc, GCPtrPage));
2697
2698	/*
2699	* Get the relevant shadow PDE entry.
2700	*/
2701	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2702	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2703	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
2704
2705	/* Fetch the pgm pool shadow descriptor. */
2706	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
2707	Assert(pShwPde);
2708
2709	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
2710	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2711	PPGMPOOLPAGE pShwPde = NULL;
2712	PX86PDPAE pPDDst;
2713	PSHWPDE pPdeDst;
2714
2715	/* Fetch the pgm pool shadow descriptor. */
2716	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
2717	AssertRCSuccessReturn(rc, rc);
2718	Assert(pShwPde);
2719
2720	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
2721	pPdeDst = &pPDDst->a[iPDDst];
2722
2723	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2724	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
2725	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
2726	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
2727	PX86PDPT pPdptDst = NULL; /* initialized to shut up gcc */
2728	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
2729	AssertRCSuccessReturn(rc, rc);
2730	Assert(pPDDst);
2731	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2732	# endif
2733	SHWPDE PdeDst = *pPdeDst;
2734
2735	# if PGM_GST_TYPE == PGM_TYPE_AMD64
2736	/* Fetch the pgm pool shadow descriptor. */
2737	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
2738	Assert(pShwPde);
2739	# endif
2740
2741	# ifndef PGM_WITHOUT_MAPPINGS
2742	/*
2743	* Check for conflicts.
2744	* RC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2745	* R3: Simply resolve the conflict.
2746	*/
2747	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2748	{
2749	Assert(pgmMapAreMappingsEnabled(pVM));
2750	# ifndef IN_RING3
2751	Log(("SyncPT: Conflict at %RGv\n", GCPtrPage));
2752	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2753	return VERR_ADDRESS_CONFLICT;
2754
2755	# else /* IN_RING3 */
2756	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2757	Assert(pMapping);
2758	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2759	rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2760	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2761	rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2762	# else
2763	AssertFailed(); NOREF(pMapping); /* can't happen for amd64 */
2764	# endif
2765	if (RT_FAILURE(rc))
2766	{
2767	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
2768	return rc;
2769	}
2770	PdeDst = *pPdeDst;
2771	# endif /* IN_RING3 */
2772	}
2773	# endif /* !PGM_WITHOUT_MAPPINGS */
2774	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2775
2776	/*
2777	* Sync the page directory entry.
2778	*/
2779	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2780	const bool fPageTable = !PdeSrc.b.u1Size \|\| !GST_IS_PSE_ACTIVE(pVCpu);
2781	if ( PdeSrc.n.u1Present
2782	&& (fPageTable ? GST_IS_PDE_VALID(pVCpu, PdeSrc) : GST_IS_BIG_PDE_VALID(pVCpu, PdeSrc)) )
2783	{
2784	/*
2785	* Allocate & map the page table.
2786	*/
2787	PSHWPT pPTDst;
2788	PPGMPOOLPAGE pShwPage;
2789	RTGCPHYS GCPhys;
2790	if (fPageTable)
2791	{
2792	GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
2793	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2794	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2795	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
2796	# endif
2797	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
2798	pShwPde->idx, iPDDst, false /fLockPage/,
2799	&pShwPage);
2800	}
2801	else
2802	{
2803	PGMPOOLACCESS enmAccess;
2804	# if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
2805	const bool fNoExecute = PdeSrc.n.u1NoExecute && GST_IS_NX_ACTIVE(pVCpu);
2806	# else
2807	const bool fNoExecute = false;
2808	# endif
2809
2810	GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
2811	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2812	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2813	GCPhys = PGM_A20_APPLY(pVCpu, GCPhys \| (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
2814	# endif
2815	/* Determine the right kind of large page to avoid incorrect cached entry reuse. */
2816	if (PdeSrc.n.u1User)
2817	{
2818	if (PdeSrc.n.u1Write)
2819	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_RW_NX : PGMPOOLACCESS_USER_RW;
2820	else
2821	enmAccess = (fNoExecute) ? PGMPOOLACCESS_USER_R_NX : PGMPOOLACCESS_USER_R;
2822	}
2823	else
2824	{
2825	if (PdeSrc.n.u1Write)
2826	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_RW_NX : PGMPOOLACCESS_SUPERVISOR_RW;
2827	else
2828	enmAccess = (fNoExecute) ? PGMPOOLACCESS_SUPERVISOR_R_NX : PGMPOOLACCESS_SUPERVISOR_R;
2829	}
2830	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, enmAccess, PGM_A20_IS_ENABLED(pVCpu),
2831	pShwPde->idx, iPDDst, false /fLockPage/,
2832	&pShwPage);
2833	}
2834	if (rc == VINF_SUCCESS)
2835	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
2836	else if (rc == VINF_PGM_CACHED_PAGE)
2837	{
2838	/*
2839	* The PT was cached, just hook it up.
2840	*/
2841	if (fPageTable)
2842	PdeDst.u = pShwPage->Core.Key \| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2843	else
2844	{
2845	PdeDst.u = pShwPage->Core.Key \| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2846	/* (see explanation and assumptions further down.) */
2847	if ( !PdeSrc.b.u1Dirty
2848	&& PdeSrc.b.u1Write)
2849	{
2850	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
2851	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2852	PdeDst.b.u1Write = 0;
2853	}
2854	}
2855	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2856	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2857	return VINF_SUCCESS;
2858	}
2859	else if (rc == VERR_PGM_POOL_FLUSHED)
2860	{
2861	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2862	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2863	return VINF_PGM_SYNC_CR3;
2864	}
2865	else
2866	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
2867	/** @todo Why do we bother preserving X86_PDE_AVL_MASK here?
2868	* Both PGM_PDFLAGS_MAPPING and PGM_PDFLAGS_TRACK_DIRTY should be
2869	* irrelevant at this point. */
2870	PdeDst.u &= X86_PDE_AVL_MASK;
2871	PdeDst.u \|= pShwPage->Core.Key;
2872
2873	/*
2874	* Page directory has been accessed (this is a fault situation, remember).
2875	*/
2876	/** @todo
2877	* Well, when the caller is PrefetchPage or InvalidatePage is isn't a
2878	* fault situation. What's more, the Trap0eHandler has already set the
2879	* accessed bit. So, it's actually just VerifyAccessSyncPage which
2880	* might need setting the accessed flag.
2881	*
2882	* The best idea is to leave this change to the caller and add an
2883	* assertion that it's set already. */
2884	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2885	if (fPageTable)
2886	{
2887	/*
2888	* Page table - 4KB.
2889	*
2890	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2891	*/
2892	Log2(("SyncPT: 4K %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2893	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2894	PGSTPT pPTSrc;
2895	rc = PGM_GCPHYS_2_PTR(pVM, GST_GET_PDE_GCPHYS(PdeSrc), &pPTSrc);
2896	if (RT_SUCCESS(rc))
2897	{
2898	/*
2899	* Start by syncing the page directory entry so CSAM's TLB trick works.
2900	*/
2901	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2902	\| GST_GET_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2903	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
2904	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
2905
2906	/*
2907	* Directory/page user or supervisor privilege: (same goes for read/write)
2908	*
2909	* Directory Page Combined
2910	* U/S U/S U/S
2911	* 0 0 0
2912	* 0 1 0
2913	* 1 0 0
2914	* 1 1 1
2915	*
2916	* Simple AND operation. Table listed for completeness.
2917	*
2918	*/
2919	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4K));
2920	# ifdef PGM_SYNC_N_PAGES
2921	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2922	unsigned iPTDst = iPTBase;
2923	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
2924	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2925	iPTDst = 0;
2926	else
2927	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2928	# else /* !PGM_SYNC_N_PAGES */
2929	unsigned iPTDst = 0;
2930	const unsigned iPTDstEnd = RT_ELEMENTS(pPTDst->a);
2931	# endif /* !PGM_SYNC_N_PAGES */
2932	RTGCPTR GCPtrCur = (GCPtrPage & ~(RTGCPTR)((1 << SHW_PD_SHIFT) - 1))
2933	\| ((RTGCPTR)iPTDst << PAGE_SHIFT);
2934	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2935	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2936	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2937	# else
2938	const unsigned offPTSrc = 0;
2939	# endif
2940	for (; iPTDst < iPTDstEnd; iPTDst++, GCPtrCur += PAGE_SIZE)
2941	{
2942	const unsigned iPTSrc = iPTDst + offPTSrc;
2943	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2944
2945	if (PteSrc.n.u1Present)
2946	{
2947	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2948	/*
2949	* Assuming kernel code will be marked as supervisor - and not as user level
2950	* and executed using a conforming code selector - And marked as readonly.
2951	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2952	*/
2953	PPGMPAGE pPage;
2954	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2955	\|\| !CSAMDoesPageNeedScanning(pVM, GCPtrCur)
2956	\|\| ( (pPage = pgmPhysGetPage(pVM, GST_GET_PTE_GCPHYS(PteSrc)))
2957	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2958	)
2959	# endif
2960	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2961	Log2(("SyncPT: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%RGp\n",
2962	GCPtrCur,
2963	PteSrc.n.u1Present,
2964	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2965	PteSrc.n.u1User & PdeSrc.n.u1User,
2966	(uint64_t)PteSrc.u,
2967	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : "", SHW_PTE_LOG64(pPTDst->a[iPTDst]), iPTSrc, PdeSrc.au32[0],
2968	(RTGCPHYS)(GST_GET_PDE_GCPHYS(PdeSrc) + iPTSrc*sizeof(PteSrc)) ));
2969	}
2970	/* else: the page table was cleared by the pool */
2971	} /* for PTEs */
2972	}
2973	}
2974	else
2975	{
2976	/*
2977	* Big page - 2/4MB.
2978	*
2979	* We'll walk the ram range list in parallel and optimize lookups.
2980	* We will only sync one shadow page table at a time.
2981	*/
2982	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT4M));
2983
2984	/**
2985	* @todo It might be more efficient to sync only a part of the 4MB
2986	* page (similar to what we do for 4KB PDs).
2987	*/
2988
2989	/*
2990	* Start by syncing the page directory entry.
2991	*/
2992	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2993	\| GST_GET_BIG_PDE_SHW_FLAGS(pVCpu, PdeSrc);
2994
2995	/*
2996	* If the page is not flagged as dirty and is writable, then make it read-only
2997	* at PD level, so we can set the dirty bit when the page is modified.
2998	*
2999	* ASSUMES that page access handlers are implemented on page table entry level.
3000	* Thus we will first catch the dirty access and set PDE.D and restart. If
3001	* there is an access handler, we'll trap again and let it work on the problem.
3002	*/
3003	/** @todo move the above stuff to a section in the PGM documentation. */
3004	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
3005	if ( !PdeSrc.b.u1Dirty
3006	&& PdeSrc.b.u1Write)
3007	{
3008	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageBig));
3009	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
3010	PdeDst.b.u1Write = 0;
3011	}
3012	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3013	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3014
3015	/*
3016	* Fill the shadow page table.
3017	*/
3018	/* Get address and flags from the source PDE. */
3019	SHWPTE PteDstBase;
3020	SHW_PTE_SET(PteDstBase, GST_GET_BIG_PDE_SHW_FLAGS_4_PTE(pVCpu, PdeSrc));
3021
3022	/* Loop thru the entries in the shadow PT. */
3023	const RTGCPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
3024	Log2(("SyncPT: BIG %RGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%RGv GCPhys=%RGp %s\n",
3025	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
3026	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
3027	PPGMRAMRANGE pRam = pgmPhysGetRangeAtOrAbove(pVM, GCPhys);
3028	unsigned iPTDst = 0;
3029	while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3030	&& !VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3031	{
3032	if (pRam && GCPhys >= pRam->GCPhys)
3033	{
3034	# ifndef PGM_WITH_A20
3035	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
3036	# endif
3037	do
3038	{
3039	/* Make shadow PTE. */
3040	# ifdef PGM_WITH_A20
3041	PPGMPAGE pPage = &pRam->aPages[(GCPhys - pRam->GCPhys) >> PAGE_SHIFT];
3042	# else
3043	PPGMPAGE pPage = &pRam->aPages[iHCPage];
3044	# endif
3045	SHWPTE PteDst;
3046
3047	# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
3048	/* Try to make the page writable if necessary. */
3049	if ( PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_RAM
3050	&& ( PGM_PAGE_IS_ZERO(pPage)
3051	\|\| ( SHW_PTE_IS_RW(PteDstBase)
3052	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
3053	# ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
3054	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
3055	# endif
3056	# ifdef VBOX_WITH_PAGE_SHARING
3057	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
3058	# endif
3059	&& !PGM_PAGE_IS_BALLOONED(pPage))
3060	)
3061	)
3062	{
3063	rc = pgmPhysPageMakeWritable(pVM, pPage, GCPhys);
3064	AssertRCReturn(rc, rc);
3065	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
3066	break;
3067	}
3068	# endif
3069
3070	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
3071	PGM_BTH_NAME(SyncHandlerPte)(pVM, pPage, SHW_PTE_GET_U(PteDstBase), &PteDst);
3072	else if (PGM_PAGE_IS_BALLOONED(pPage))
3073	SHW_PTE_SET(PteDst, 0); /* Handle ballooned pages at #PF time. */
3074	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3075	/*
3076	* Assuming kernel code will be marked as supervisor and not as user level and executed
3077	* using a conforming code selector. Don't check for readonly, as that implies the whole
3078	* 4MB can be code or readonly data. Linux enables write access for its large pages.
3079	*/
3080	else if ( !PdeSrc.n.u1User
3081	&& CSAMDoesPageNeedScanning(pVM, GCPtr \| (iPTDst << SHW_PT_SHIFT)))
3082	SHW_PTE_SET(PteDst, 0);
3083	# endif
3084	else
3085	SHW_PTE_SET(PteDst, PGM_PAGE_GET_HCPHYS(pPage) \| SHW_PTE_GET_U(PteDstBase));
3086
3087	/* Only map writable pages writable. */
3088	if ( SHW_PTE_IS_P_RW(PteDst)
3089	&& PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED)
3090	{
3091	/* Still applies to shared pages. */
3092	Assert(!PGM_PAGE_IS_ZERO(pPage));
3093	SHW_PTE_SET_RO(PteDst); /** @todo this isn't quite working yet... */
3094	Log3(("SyncPT: write-protecting %RGp pPage=%R[pgmpage] at %RGv\n", GCPhys, pPage, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))));
3095	}
3096
3097	if (SHW_PTE_IS_P(PteDst))
3098	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPage, PGM_PAGE_GET_TRACKING(pPage), pPage, iPTDst);
3099
3100	/* commit it (not atomic, new table) */
3101	pPTDst->a[iPTDst] = PteDst;
3102	Log4(("SyncPT: BIG %RGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
3103	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), SHW_PTE_IS_P(PteDst), SHW_PTE_IS_RW(PteDst), SHW_PTE_IS_US(PteDst), SHW_PTE_LOG64(PteDst),
3104	SHW_PTE_IS_TRACK_DIRTY(PteDst) ? " Track-Dirty" : ""));
3105
3106	/* advance */
3107	GCPhys += PAGE_SIZE;
3108	PGM_A20_APPLY_TO_VAR(pVCpu, GCPhys);
3109	# ifndef PGM_WITH_A20
3110	iHCPage++;
3111	# endif
3112	iPTDst++;
3113	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3114	&& GCPhys <= pRam->GCPhysLast);
3115
3116	/* Advance ram range list. */
3117	while (pRam && GCPhys > pRam->GCPhysLast)
3118	pRam = pRam->CTX_SUFF(pNext);
3119	}
3120	else if (pRam)
3121	{
3122	Log(("Invalid pages at %RGp\n", GCPhys));
3123	do
3124	{
3125	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3126	GCPhys += PAGE_SIZE;
3127	iPTDst++;
3128	} while ( iPTDst < RT_ELEMENTS(pPTDst->a)
3129	&& GCPhys < pRam->GCPhys);
3130	PGM_A20_APPLY_TO_VAR(pVCpu,GCPhys);
3131	}
3132	else
3133	{
3134	Log(("Invalid pages at %RGp (2)\n", GCPhys));
3135	for ( ; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3136	SHW_PTE_SET(pPTDst->a[iPTDst], 0); /* Invalid page, we must handle them manually. */
3137	}
3138	} /* while more PTEs */
3139	} /* 4KB / 4MB */
3140	}
3141	else
3142	AssertRelease(!PdeDst.n.u1Present);
3143
3144	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3145	if (RT_FAILURE(rc))
3146	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3147	return rc;
3148
3149	#elif (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3150	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3151	&& (PGM_SHW_TYPE != PGM_TYPE_EPT \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
3152	&& !defined(IN_RC)
3153	NOREF(iPDSrc); NOREF(pPDSrc);
3154
3155	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3156
3157	/*
3158	* Validate input a little bit.
3159	*/
3160	int rc = VINF_SUCCESS;
3161	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3162	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3163	PSHWPDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3164
3165	/* Fetch the pgm pool shadow descriptor. */
3166	PPGMPOOLPAGE pShwPde = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
3167	Assert(pShwPde);
3168
3169	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3170	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3171	PPGMPOOLPAGE pShwPde = NULL; /* initialized to shut up gcc */
3172	PX86PDPAE pPDDst;
3173	PSHWPDE pPdeDst;
3174
3175	/* Fetch the pgm pool shadow descriptor. */
3176	rc = pgmShwGetPaePoolPagePD(pVCpu, GCPtrPage, &pShwPde);
3177	AssertRCSuccessReturn(rc, rc);
3178	Assert(pShwPde);
3179
3180	pPDDst = (PX86PDPAE)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPde);
3181	pPdeDst = &pPDDst->a[iPDDst];
3182
3183	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3184	const unsigned iPdpt = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
3185	const unsigned iPDDst = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
3186	PX86PDPAE pPDDst = NULL; /* initialized to shut up gcc */
3187	PX86PDPT pPdptDst= NULL; /* initialized to shut up gcc */
3188	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtrPage, NULL, &pPdptDst, &pPDDst);
3189	AssertRCSuccessReturn(rc, rc);
3190	Assert(pPDDst);
3191	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3192
3193	/* Fetch the pgm pool shadow descriptor. */
3194	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
3195	Assert(pShwPde);
3196
3197	# elif PGM_SHW_TYPE == PGM_TYPE_EPT
3198	const unsigned iPdpt = (GCPtrPage >> EPT_PDPT_SHIFT) & EPT_PDPT_MASK;
3199	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3200	PEPTPD pPDDst;
3201	PEPTPDPT pPdptDst;
3202
3203	rc = pgmShwGetEPTPDPtr(pVCpu, GCPtrPage, &pPdptDst, &pPDDst);
3204	if (rc != VINF_SUCCESS)
3205	{
3206	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3207	AssertRC(rc);
3208	return rc;
3209	}
3210	Assert(pPDDst);
3211	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
3212
3213	/* Fetch the pgm pool shadow descriptor. */
3214	PPGMPOOLPAGE pShwPde = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & EPT_PDPTE_PG_MASK);
3215	Assert(pShwPde);
3216	# endif
3217	SHWPDE PdeDst = *pPdeDst;
3218
3219	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
3220	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
3221
3222	# if defined(PGM_WITH_LARGE_PAGES) && PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
3223	if (BTH_IS_NP_ACTIVE(pVM))
3224	{
3225	/* Check if we allocated a big page before for this 2 MB range. */
3226	PPGMPAGE pPage;
3227	rc = pgmPhysGetPageEx(pVM, PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PDE2M_PAE_PG_MASK), &pPage);
3228	if (RT_SUCCESS(rc))
3229	{
3230	RTHCPHYS HCPhys = NIL_RTHCPHYS;
3231	if (PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE)
3232	{
3233	if (PGM_A20_IS_ENABLED(pVCpu))
3234	{
3235	STAM_REL_COUNTER_INC(&pVM->pgm.s.StatLargePageReused);
3236	AssertRelease(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3237	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3238	}
3239	else
3240	{
3241	PGM_PAGE_SET_PDE_TYPE(pVM, pPage, PGM_PAGE_PDE_TYPE_PDE_DISABLED);
3242	pVM->pgm.s.cLargePagesDisabled++;
3243	}
3244	}
3245	else if ( PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE_DISABLED
3246	&& PGM_A20_IS_ENABLED(pVCpu))
3247	{
3248	/* Recheck the entire 2 MB range to see if we can use it again as a large page. */
3249	rc = pgmPhysRecheckLargePage(pVM, GCPtrPage, pPage);
3250	if (RT_SUCCESS(rc))
3251	{
3252	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3253	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3254	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3255	}
3256	}
3257	else if ( PGMIsUsingLargePages(pVM)
3258	&& PGM_A20_IS_ENABLED(pVCpu))
3259	{
3260	rc = pgmPhysAllocLargePage(pVM, GCPtrPage);
3261	if (RT_SUCCESS(rc))
3262	{
3263	Assert(PGM_PAGE_GET_STATE(pPage) == PGM_PAGE_STATE_ALLOCATED);
3264	Assert(PGM_PAGE_GET_PDE_TYPE(pPage) == PGM_PAGE_PDE_TYPE_PDE);
3265	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
3266	}
3267	else
3268	LogFlow(("pgmPhysAllocLargePage failed with %Rrc\n", rc));
3269	}
3270
3271	if (HCPhys != NIL_RTHCPHYS)
3272	{
3273	PdeDst.u &= X86_PDE_AVL_MASK;
3274	PdeDst.u \|= HCPhys;
3275	PdeDst.n.u1Present = 1;
3276	PdeDst.n.u1Write = 1;
3277	PdeDst.b.u1Size = 1;
3278	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3279	PdeDst.n.u1Execute = 1;
3280	PdeDst.b.u1IgnorePAT = 1;
3281	PdeDst.b.u3EMT = VMX_EPT_MEMTYPE_WB;
3282	# else
3283	PdeDst.n.u1User = 1;
3284	# endif
3285	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3286
3287	Log(("SyncPT: Use large page at %RGp PDE=%RX64\n", GCPtrPage, PdeDst.u));
3288	/* Add a reference to the first page only. */
3289	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVCpu, pShwPde, PGM_PAGE_GET_TRACKING(pPage), pPage, iPDDst);
3290
3291	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3292	return VINF_SUCCESS;
3293	}
3294	}
3295	}
3296	# endif /* HC_ARCH_BITS == 64 */
3297
3298	/*
3299	* Allocate & map the page table.
3300	*/
3301	PSHWPT pPTDst;
3302	PPGMPOOLPAGE pShwPage;
3303	RTGCPHYS GCPhys;
3304
3305	/* Virtual address = physical address */
3306	GCPhys = PGM_A20_APPLY(pVCpu, GCPtrPage & X86_PAGE_4K_BASE_MASK);
3307	rc = pgmPoolAlloc(pVM, GCPhys & ~(RT_BIT_64(SHW_PD_SHIFT) - 1), BTH_PGMPOOLKIND_PT_FOR_PT, PGMPOOLACCESS_DONTCARE,
3308	PGM_A20_IS_ENABLED(pVCpu), pShwPde->idx, iPDDst, false /fLockPage/,
3309	&pShwPage);
3310	if ( rc == VINF_SUCCESS
3311	\|\| rc == VINF_PGM_CACHED_PAGE)
3312	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pShwPage);
3313	else
3314	{
3315	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3316	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_IPE_UNEXPECTED_INFO_STATUS);
3317	}
3318
3319	if (rc == VINF_SUCCESS)
3320	{
3321	/* New page table; fully set it up. */
3322	Assert(pPTDst);
3323
3324	/* Mask away the page offset. */
3325	GCPtrPage &= ~(RTGCPTR)PAGE_OFFSET_MASK;
3326
3327	for (unsigned iPTDst = 0; iPTDst < RT_ELEMENTS(pPTDst->a); iPTDst++)
3328	{
3329	RTGCPTR GCPtrCurPage = PGM_A20_APPLY(pVCpu, (GCPtrPage & ~(RTGCPTR)(SHW_PT_MASK << SHW_PT_SHIFT))
3330	\| (iPTDst << PAGE_SHIFT));
3331
3332	PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], GCPtrCurPage, pShwPage, iPTDst);
3333	Log2(("SyncPage: 4K+ %RGv PteSrc:{P=1 RW=1 U=1} PteDst=%08llx%s\n",
3334	GCPtrCurPage,
3335	SHW_PTE_LOG64(pPTDst->a[iPTDst]),
3336	SHW_PTE_IS_TRACK_DIRTY(pPTDst->a[iPTDst]) ? " Track-Dirty" : ""));
3337
3338	if (RT_UNLIKELY(VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY)))
3339	break;
3340	}
3341	}
3342	else
3343	rc = VINF_SUCCESS; /* Cached entry; assume it's still fully valid. */
3344
3345	/* Save the new PDE. */
3346	PdeDst.u &= X86_PDE_AVL_MASK;
3347	PdeDst.u \|= pShwPage->Core.Key;
3348	PdeDst.n.u1Present = 1;
3349	PdeDst.n.u1Write = 1;
3350	# if PGM_SHW_TYPE == PGM_TYPE_EPT
3351	PdeDst.n.u1Execute = 1;
3352	# else
3353	PdeDst.n.u1User = 1;
3354	PdeDst.n.u1Accessed = 1;
3355	# endif
3356	ASMAtomicWriteSize(pPdeDst, PdeDst.u);
3357
3358	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPT), a);
3359	if (RT_FAILURE(rc))
3360	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncPTFailed));
3361	return rc;
3362
3363	#else
3364	NOREF(iPDSrc); NOREF(pPDSrc);
3365	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
3366	return VERR_PGM_NOT_USED_IN_MODE;
3367	#endif
3368	}
3369
3370
3371
3372	/**
3373	* Prefetch a page/set of pages.
3374	*
3375	* Typically used to sync commonly used pages before entering raw mode
3376	* after a CR3 reload.
3377	*
3378	* @returns VBox status code.
3379	* @param pVCpu The cross context virtual CPU structure.
3380	* @param GCPtrPage Page to invalidate.
3381	*/
3382	PGM_BTH_DECL(int, PrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage)
3383	{
3384	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3385	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3386	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3387	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3388	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3389	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3390	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3391
3392	/*
3393	* Check that all Guest levels thru the PDE are present, getting the
3394	* PD and PDE in the processes.
3395	*/
3396	int rc = VINF_SUCCESS;
3397	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3398	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3399	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3400	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3401	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3402	unsigned iPDSrc;
3403	X86PDPE PdpeSrc;
3404	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3405	if (!pPDSrc)
3406	return VINF_SUCCESS; /* not present */
3407	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3408	unsigned iPDSrc;
3409	PX86PML4E pPml4eSrc;
3410	X86PDPE PdpeSrc;
3411	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3412	if (!pPDSrc)
3413	return VINF_SUCCESS; /* not present */
3414	# endif
3415	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3416	# else
3417	PGSTPD pPDSrc = NULL;
3418	const unsigned iPDSrc = 0;
3419	GSTPDE PdeSrc;
3420
3421	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3422	PdeSrc.n.u1Present = 1;
3423	PdeSrc.n.u1Write = 1;
3424	PdeSrc.n.u1Accessed = 1;
3425	PdeSrc.n.u1User = 1;
3426	# endif
3427
3428	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
3429	{
3430	PVM pVM = pVCpu->CTX_SUFF(pVM);
3431	pgmLock(pVM);
3432
3433	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3434	const X86PDE PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
3435	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3436	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3437	PX86PDPAE pPDDst;
3438	X86PDEPAE PdeDst;
3439	# if PGM_GST_TYPE != PGM_TYPE_PAE
3440	X86PDPE PdpeSrc;
3441
3442	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3443	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3444	# endif
3445	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3446	if (rc != VINF_SUCCESS)
3447	{
3448	pgmUnlock(pVM);
3449	AssertRC(rc);
3450	return rc;
3451	}
3452	Assert(pPDDst);
3453	PdeDst = pPDDst->a[iPDDst];
3454
3455	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3456	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3457	PX86PDPAE pPDDst;
3458	X86PDEPAE PdeDst;
3459
3460	# if PGM_GST_TYPE == PGM_TYPE_PROT
3461	/* AMD-V nested paging */
3462	X86PML4E Pml4eSrc;
3463	X86PDPE PdpeSrc;
3464	PX86PML4E pPml4eSrc = &Pml4eSrc;
3465
3466	/* Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3467	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3468	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3469	# endif
3470
3471	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3472	if (rc != VINF_SUCCESS)
3473	{
3474	pgmUnlock(pVM);
3475	AssertRC(rc);
3476	return rc;
3477	}
3478	Assert(pPDDst);
3479	PdeDst = pPDDst->a[iPDDst];
3480	# endif
3481	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
3482	{
3483	if (!PdeDst.n.u1Present)
3484	{
3485	/** @todo r=bird: This guy will set the A bit on the PDE,
3486	* probably harmless. */
3487	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3488	}
3489	else
3490	{
3491	/* Note! We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
3492	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
3493	* makes no sense to prefetch more than one page.
3494	*/
3495	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3496	if (RT_SUCCESS(rc))
3497	rc = VINF_SUCCESS;
3498	}
3499	}
3500	pgmUnlock(pVM);
3501	}
3502	return rc;
3503
3504	#elif PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3505	NOREF(pVCpu); NOREF(GCPtrPage);
3506	return VINF_SUCCESS; /* ignore */
3507	#else
3508	AssertCompile(0);
3509	#endif
3510	}
3511
3512
3513
3514
3515	/**
3516	* Syncs a page during a PGMVerifyAccess() call.
3517	*
3518	* @returns VBox status code (informational included).
3519	* @param pVCpu The cross context virtual CPU structure.
3520	* @param GCPtrPage The address of the page to sync.
3521	* @param fPage The effective guest page flags.
3522	* @param uErr The trap error code.
3523	* @remarks This will normally never be called on invalid guest page
3524	* translation entries.
3525	*/
3526	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fPage, unsigned uErr)
3527	{
3528	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3529
3530	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%RGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
3531	RT_NOREF_PV(GCPtrPage); RT_NOREF_PV(fPage); RT_NOREF_PV(uErr);
3532
3533	Assert(!pVM->pgm.s.fNestedPaging);
3534	#if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
3535	\|\| PGM_GST_TYPE == PGM_TYPE_REAL \
3536	\|\| PGM_GST_TYPE == PGM_TYPE_PROT \
3537	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3538	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
3539	&& PGM_SHW_TYPE != PGM_TYPE_NESTED \
3540	&& PGM_SHW_TYPE != PGM_TYPE_EPT
3541
3542	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3543	if (!(fPage & X86_PTE_US))
3544	{
3545	/*
3546	* Mark this page as safe.
3547	*/
3548	/** @todo not correct for pages that contain both code and data!! */
3549	Log(("CSAMMarkPage %RGv; scanned=%d\n", GCPtrPage, true));
3550	CSAMMarkPage(pVM, GCPtrPage, true);
3551	}
3552	# endif
3553
3554	/*
3555	* Get guest PD and index.
3556	*/
3557	/** @todo Performance: We've done all this a jiffy ago in the
3558	* PGMGstGetPage call. */
3559	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3560	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3561	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
3562	PGSTPD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
3563
3564	# elif PGM_GST_TYPE == PGM_TYPE_PAE
3565	unsigned iPDSrc = 0;
3566	X86PDPE PdpeSrc;
3567	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtrPage, &iPDSrc, &PdpeSrc);
3568	if (RT_UNLIKELY(!pPDSrc))
3569	{
3570	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3571	return VINF_EM_RAW_GUEST_TRAP;
3572	}
3573
3574	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
3575	unsigned iPDSrc = 0; /* shut up gcc */
3576	PX86PML4E pPml4eSrc = NULL; /* ditto */
3577	X86PDPE PdpeSrc;
3578	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtrPage, &pPml4eSrc, &PdpeSrc, &iPDSrc);
3579	if (RT_UNLIKELY(!pPDSrc))
3580	{
3581	Log(("PGMVerifyAccess: access violation for %RGv due to non-present PDPTR\n", GCPtrPage));
3582	return VINF_EM_RAW_GUEST_TRAP;
3583	}
3584	# endif
3585
3586	# else /* !PGM_WITH_PAGING */
3587	PGSTPD pPDSrc = NULL;
3588	const unsigned iPDSrc = 0;
3589	# endif /* !PGM_WITH_PAGING */
3590	int rc = VINF_SUCCESS;
3591
3592	pgmLock(pVM);
3593
3594	/*
3595	* First check if the shadow pd is present.
3596	*/
3597	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3598	PX86PDE pPdeDst = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
3599
3600	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3601	PX86PDEPAE pPdeDst;
3602	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3603	PX86PDPAE pPDDst;
3604	# if PGM_GST_TYPE != PGM_TYPE_PAE
3605	/* Fake PDPT entry; access control handled on the page table level, so allow everything. */
3606	X86PDPE PdpeSrc;
3607	PdpeSrc.u = X86_PDPE_P; /* rw/us are reserved for PAE pdpte's; accessed bit causes invalid VT-x guest state errors */
3608	# endif
3609	rc = pgmShwSyncPaePDPtr(pVCpu, GCPtrPage, PdpeSrc.u, &pPDDst);
3610	if (rc != VINF_SUCCESS)
3611	{
3612	pgmUnlock(pVM);
3613	AssertRC(rc);
3614	return rc;
3615	}
3616	Assert(pPDDst);
3617	pPdeDst = &pPDDst->a[iPDDst];
3618
3619	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3620	const unsigned iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
3621	PX86PDPAE pPDDst;
3622	PX86PDEPAE pPdeDst;
3623
3624	# if PGM_GST_TYPE == PGM_TYPE_PROT
3625	/* AMD-V nested paging: Fake PML4 & PDPT entry; access control handled on the page table level, so allow everything. */
3626	X86PML4E Pml4eSrc;
3627	X86PDPE PdpeSrc;
3628	PX86PML4E pPml4eSrc = &Pml4eSrc;
3629	Pml4eSrc.u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
3630	PdpeSrc.u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
3631	# endif
3632
3633	rc = pgmShwSyncLongModePDPtr(pVCpu, GCPtrPage, pPml4eSrc->u, PdpeSrc.u, &pPDDst);
3634	if (rc != VINF_SUCCESS)
3635	{
3636	pgmUnlock(pVM);
3637	AssertRC(rc);
3638	return rc;
3639	}
3640	Assert(pPDDst);
3641	pPdeDst = &pPDDst->a[iPDDst];
3642	# endif
3643
3644	if (!pPdeDst->n.u1Present)
3645	{
3646	rc = PGM_BTH_NAME(SyncPT)(pVCpu, iPDSrc, pPDSrc, GCPtrPage);
3647	if (rc != VINF_SUCCESS)
3648	{
3649	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3650	pgmUnlock(pVM);
3651	AssertRC(rc);
3652	return rc;
3653	}
3654	}
3655
3656	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3657	/* Check for dirty bit fault */
3658	rc = PGM_BTH_NAME(CheckDirtyPageFault)(pVCpu, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
3659	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
3660	Log(("PGMVerifyAccess: success (dirty)\n"));
3661	else
3662	# endif
3663	{
3664	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
3665	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
3666	# else
3667	GSTPDE PdeSrc;
3668	PdeSrc.u = 0; /* faked so we don't have to #ifdef everything */
3669	PdeSrc.n.u1Present = 1;
3670	PdeSrc.n.u1Write = 1;
3671	PdeSrc.n.u1Accessed = 1;
3672	PdeSrc.n.u1User = 1;
3673	# endif
3674
3675	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
3676	if (uErr & X86_TRAP_PF_US)
3677	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncUser));
3678	else /* supervisor */
3679	STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,PageOutOfSyncSupervisor));
3680
3681	rc = PGM_BTH_NAME(SyncPage)(pVCpu, PdeSrc, GCPtrPage, 1, 0);
3682	if (RT_SUCCESS(rc))
3683	{
3684	/* Page was successfully synced */
3685	Log2(("PGMVerifyAccess: success (sync)\n"));
3686	rc = VINF_SUCCESS;
3687	}
3688	else
3689	{
3690	Log(("PGMVerifyAccess: access violation for %RGv rc=%Rrc\n", GCPtrPage, rc));
3691	rc = VINF_EM_RAW_GUEST_TRAP;
3692	}
3693	}
3694	PGM_DYNMAP_UNUSED_HINT(pVCpu, pPdeDst);
3695	pgmUnlock(pVM);
3696	return rc;
3697
3698	#else /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3699
3700	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
3701	return VERR_PGM_NOT_USED_IN_MODE;
3702	#endif /* PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_NESTED */
3703	}
3704
3705
3706	/**
3707	* Syncs the paging hierarchy starting at CR3.
3708	*
3709	* @returns VBox status code, R0/RC may return VINF_PGM_SYNC_CR3, no other
3710	* informational status codes.
3711	* @retval VERR_PGM_NO_HYPERVISOR_ADDRESS in raw-mode when we're unable to map
3712	* the VMM into guest context.
3713	* @param pVCpu The cross context virtual CPU structure.
3714	* @param cr0 Guest context CR0 register.
3715	* @param cr3 Guest context CR3 register. Not subjected to the A20
3716	* mask.
3717	* @param cr4 Guest context CR4 register.
3718	* @param fGlobal Including global page directories or not
3719	*/
3720	PGM_BTH_DECL(int, SyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
3721	{
3722	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
3723	NOREF(cr0); NOREF(cr3); NOREF(cr4); NOREF(fGlobal);
3724
3725	LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
3726
3727	#if PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT
3728
3729	pgmLock(pVM);
3730
3731	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
3732	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
3733	if (pPool->cDirtyPages)
3734	pgmPoolResetDirtyPages(pVM);
3735	# endif
3736
3737	/*
3738	* Update page access handlers.
3739	* The virtual are always flushed, while the physical are only on demand.
3740	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
3741	* have to look into that later because it will have a bad influence on the performance.
3742	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
3743	* bird: Yes, but that won't work for aliases.
3744	*/
3745	/** @todo this MUST go away. See @bugref{1557}. */
3746	STAM_PROFILE_START(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3747	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
3748	STAM_PROFILE_STOP(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,SyncCR3Handlers), h);
3749	pgmUnlock(pVM);
3750	#endif /* !NESTED && !EPT */
3751
3752	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3753	/*
3754	* Nested / EPT - almost no work.
3755	*/
3756	Assert(!pgmMapAreMappingsEnabled(pVM));
3757	return VINF_SUCCESS;
3758
3759	#elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3760	/*
3761	* AMD64 (Shw & Gst) - No need to check all paging levels; we zero
3762	* out the shadow parts when the guest modifies its tables.
3763	*/
3764	Assert(!pgmMapAreMappingsEnabled(pVM));
3765	return VINF_SUCCESS;
3766
3767	#else /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3768
3769	# ifndef PGM_WITHOUT_MAPPINGS
3770	/*
3771	* Check for and resolve conflicts with our guest mappings if they
3772	* are enabled and not fixed.
3773	*/
3774	if (pgmMapAreMappingsFloating(pVM))
3775	{
3776	int rc = pgmMapResolveConflicts(pVM);
3777	Assert(rc == VINF_SUCCESS \|\| rc == VINF_PGM_SYNC_CR3);
3778	if (rc == VINF_SUCCESS)
3779	{ /* likely */ }
3780	else if (rc == VINF_PGM_SYNC_CR3)
3781	{
3782	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
3783	return VINF_PGM_SYNC_CR3;
3784	}
3785	else if (RT_FAILURE(rc))
3786	return rc;
3787	else
3788	AssertMsgFailed(("%Rrc\n", rc));
3789	}
3790	# else
3791	Assert(!pgmMapAreMappingsEnabled(pVM));
3792	# endif
3793	return VINF_SUCCESS;
3794	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT && PGM_SHW_TYPE != PGM_TYPE_AMD64 */
3795	}
3796
3797
3798
3799
3800	#ifdef VBOX_STRICT
3801	# ifdef IN_RC
3802	# undef AssertMsgFailed
3803	# define AssertMsgFailed Log
3804	# endif
3805
3806	/**
3807	* Checks that the shadow page table is in sync with the guest one.
3808	*
3809	* @returns The number of errors.
3810	* @param pVCpu The cross context virtual CPU structure.
3811	* @param cr3 Guest context CR3 register.
3812	* @param cr4 Guest context CR4 register.
3813	* @param GCPtr Where to start. Defaults to 0.
3814	* @param cb How much to check. Defaults to everything.
3815	*/
3816	PGM_BTH_DECL(unsigned, AssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb)
3817	{
3818	NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
3819	#if PGM_SHW_TYPE == PGM_TYPE_NESTED \|\| PGM_SHW_TYPE == PGM_TYPE_EPT
3820	return 0;
3821	#else
3822	unsigned cErrors = 0;
3823	PVM pVM = pVCpu->CTX_SUFF(pVM);
3824	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool); NOREF(pPool);
3825
3826	# if PGM_GST_TYPE == PGM_TYPE_PAE
3827	/** @todo currently broken; crashes below somewhere */
3828	AssertFailed();
3829	# endif
3830
3831	# if PGM_GST_TYPE == PGM_TYPE_32BIT \
3832	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
3833	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
3834
3835	bool fBigPagesSupported = GST_IS_PSE_ACTIVE(pVCpu);
3836	PPGMCPU pPGM = &pVCpu->pgm.s;
3837	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3838	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3839	# ifndef IN_RING0
3840	RTHCPHYS HCPhys; /* general usage. */
3841	# endif
3842	int rc;
3843
3844	/*
3845	* Check that the Guest CR3 and all its mappings are correct.
3846	*/
3847	AssertMsgReturn(pPGM->GCPhysCR3 == PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK),
3848	("Invalid GCPhysCR3=%RGp cr3=%RGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3849	false);
3850	# if !defined(IN_RING0) && PGM_GST_TYPE != PGM_TYPE_AMD64
3851	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3852	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGst32BitPdRC, NULL, &HCPhysShw);
3853	# else
3854	rc = PGMShwGetPage(pVCpu, (RTRCUINTPTR)pPGM->pGstPaePdptRC, NULL, &HCPhysShw);
3855	# endif
3856	AssertRCReturn(rc, 1);
3857	HCPhys = NIL_RTHCPHYS;
3858	rc = pgmRamGCPhys2HCPhys(pVM, PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK), &HCPhys);
3859	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%RHp HCPhyswShw=%RHp (cr3)\n", HCPhys, HCPhysShw), false);
3860	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3861	pgmGstGet32bitPDPtr(pVCpu);
3862	RTGCPHYS GCPhys;
3863	rc = PGMR3DbgR3Ptr2GCPhys(pVM->pUVM, pPGM->pGst32BitPdR3, &GCPhys);
3864	AssertRCReturn(rc, 1);
3865	AssertMsgReturn(PGM_A20_APPLY(pVCpu, cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%RGp cr3=%RGp\n", GCPhys, (RTGCPHYS)cr3), false);
3866	# endif
3867	# endif /* !IN_RING0 */
3868
3869	/*
3870	* Get and check the Shadow CR3.
3871	*/
3872	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3873	unsigned cPDEs = X86_PG_ENTRIES;
3874	unsigned cIncrement = X86_PG_ENTRIES * PAGE_SIZE;
3875	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
3876	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3877	unsigned cPDEs = X86_PG_PAE_ENTRIES * 4; /* treat it as a 2048 entry table. */
3878	# else
3879	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3880	# endif
3881	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3882	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
3883	unsigned cPDEs = X86_PG_PAE_ENTRIES;
3884	unsigned cIncrement = X86_PG_PAE_ENTRIES * PAGE_SIZE;
3885	# endif
3886	if (cb != ~(RTGCPTR)0)
3887	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3888
3889	/** @todo call the other two PGMAssert() functions. /
3890
3891	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3892	unsigned iPml4 = (GCPtr >> X86_PML4_SHIFT) & X86_PML4_MASK;
3893
3894	for (; iPml4 < X86_PG_PAE_ENTRIES; iPml4++)
3895	{
3896	PPGMPOOLPAGE pShwPdpt = NULL;
3897	PX86PML4E pPml4eSrc;
3898	PX86PML4E pPml4eDst;
3899	RTGCPHYS GCPhysPdptSrc;
3900
3901	pPml4eSrc = pgmGstGetLongModePML4EPtr(pVCpu, iPml4);
3902	pPml4eDst = pgmShwGetLongModePML4EPtr(pVCpu, iPml4);
3903
3904	/* Fetch the pgm pool shadow descriptor if the shadow pml4e is present. */
3905	if (!pPml4eDst->n.u1Present)
3906	{
3907	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3908	continue;
3909	}
3910
3911	pShwPdpt = pgmPoolGetPage(pPool, pPml4eDst->u & X86_PML4E_PG_MASK);
3912	GCPhysPdptSrc = PGM_A20_APPLY(pVCpu, pPml4eSrc->u & X86_PML4E_PG_MASK);
3913
3914	if (pPml4eSrc->n.u1Present != pPml4eDst->n.u1Present)
3915	{
3916	AssertMsgFailed(("Present bit doesn't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3917	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3918	cErrors++;
3919	continue;
3920	}
3921
3922	if (GCPhysPdptSrc != pShwPdpt->GCPhys)
3923	{
3924	AssertMsgFailed(("Physical address doesn't match! iPml4 %d pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, pPml4eDst->u, pPml4eSrc->u, pShwPdpt->GCPhys, GCPhysPdptSrc));
3925	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3926	cErrors++;
3927	continue;
3928	}
3929
3930	if ( pPml4eDst->n.u1User != pPml4eSrc->n.u1User
3931	\|\| pPml4eDst->n.u1Write != pPml4eSrc->n.u1Write
3932	\|\| pPml4eDst->n.u1NoExecute != pPml4eSrc->n.u1NoExecute)
3933	{
3934	AssertMsgFailed(("User/Write/NoExec bits don't match! pPml4eDst.u=%#RX64 pPml4eSrc.u=%RX64\n", pPml4eDst->u, pPml4eSrc->u));
3935	GCPtr += _2M * UINT64_C(512) * UINT64_C(512);
3936	cErrors++;
3937	continue;
3938	}
3939	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3940	{
3941	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 */
3942
3943	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
3944	/*
3945	* Check the PDPTEs too.
3946	*/
3947	unsigned iPdpt = (GCPtr >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
3948
3949	for (;iPdpt <= SHW_PDPT_MASK; iPdpt++)
3950	{
3951	unsigned iPDSrc = 0; /* initialized to shut up gcc */
3952	PPGMPOOLPAGE pShwPde = NULL;
3953	PX86PDPE pPdpeDst;
3954	RTGCPHYS GCPhysPdeSrc;
3955	X86PDPE PdpeSrc;
3956	PdpeSrc.u = 0; /* initialized to shut up gcc 4.5 */
3957	# if PGM_GST_TYPE == PGM_TYPE_PAE
3958	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pVCpu, GCPtr, &iPDSrc, &PdpeSrc);
3959	PX86PDPT pPdptDst = pgmShwGetPaePDPTPtr(pVCpu);
3960	# else
3961	PX86PML4E pPml4eSrcIgn;
3962	PX86PDPT pPdptDst;
3963	PX86PDPAE pPDDst;
3964	PGSTPD pPDSrc = pgmGstGetLongModePDPtr(pVCpu, GCPtr, &pPml4eSrcIgn, &PdpeSrc, &iPDSrc);
3965
3966	rc = pgmShwGetLongModePDPtr(pVCpu, GCPtr, NULL, &pPdptDst, &pPDDst);
3967	if (rc != VINF_SUCCESS)
3968	{
3969	AssertMsg(rc == VERR_PAGE_DIRECTORY_PTR_NOT_PRESENT, ("Unexpected rc=%Rrc\n", rc));
3970	GCPtr += 512 * _2M;
3971	continue; /* next PDPTE */
3972	}
3973	Assert(pPDDst);
3974	# endif
3975	Assert(iPDSrc == 0);
3976
3977	pPdpeDst = &pPdptDst->a[iPdpt];
3978
3979	if (!pPdpeDst->n.u1Present)
3980	{
3981	GCPtr += 512 * _2M;
3982	continue; /* next PDPTE */
3983	}
3984
3985	pShwPde = pgmPoolGetPage(pPool, pPdpeDst->u & X86_PDPE_PG_MASK);
3986	GCPhysPdeSrc = PGM_A20_APPLY(pVCpu, PdpeSrc.u & X86_PDPE_PG_MASK);
3987
3988	if (pPdpeDst->n.u1Present != PdpeSrc.n.u1Present)
3989	{
3990	AssertMsgFailed(("Present bit doesn't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
3991	GCPtr += 512 * _2M;
3992	cErrors++;
3993	continue;
3994	}
3995
3996	if (GCPhysPdeSrc != pShwPde->GCPhys)
3997	{
3998	# if PGM_GST_TYPE == PGM_TYPE_AMD64
3999	AssertMsgFailed(("Physical address doesn't match! iPml4 %d iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPml4, iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4000	# else
4001	AssertMsgFailed(("Physical address doesn't match! iPdpt %d pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64 Phys %RX64 vs %RX64\n", iPdpt, pPdpeDst->u, PdpeSrc.u, pShwPde->GCPhys, GCPhysPdeSrc));
4002	# endif
4003	GCPtr += 512 * _2M;
4004	cErrors++;
4005	continue;
4006	}
4007
4008	# if PGM_GST_TYPE == PGM_TYPE_AMD64
4009	if ( pPdpeDst->lm.u1User != PdpeSrc.lm.u1User
4010	\|\| pPdpeDst->lm.u1Write != PdpeSrc.lm.u1Write
4011	\|\| pPdpeDst->lm.u1NoExecute != PdpeSrc.lm.u1NoExecute)
4012	{
4013	AssertMsgFailed(("User/Write/NoExec bits don't match! pPdpeDst.u=%#RX64 pPdpeSrc.u=%RX64\n", pPdpeDst->u, PdpeSrc.u));
4014	GCPtr += 512 * _2M;
4015	cErrors++;
4016	continue;
4017	}
4018	# endif
4019
4020	# else /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4021	{
4022	# endif /* PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PAE */
4023	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4024	GSTPD const *pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
4025	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
4026	PCX86PD pPDDst = pgmShwGet32BitPDPtr(pVCpu);
4027	# endif
4028	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
4029	/*
4030	* Iterate the shadow page directory.
4031	*/
4032	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
4033	unsigned iPDDst = (GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK;
4034
4035	for (;
4036	iPDDst < cPDEs;
4037	iPDDst++, GCPtr += cIncrement)
4038	{
4039	# if PGM_SHW_TYPE == PGM_TYPE_PAE
4040	const SHWPDE PdeDst = *pgmShwGetPaePDEPtr(pVCpu, GCPtr);
4041	# else
4042	const SHWPDE PdeDst = pPDDst->a[iPDDst];
4043	# endif
4044	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
4045	{
4046	Assert(pgmMapAreMappingsEnabled(pVM));
4047	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
4048	{
4049	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
4050	cErrors++;
4051	continue;
4052	}
4053	}
4054	else if ( (PdeDst.u & X86_PDE_P)
4055	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
4056	)
4057	{
4058	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
4059	PPGMPOOLPAGE pPoolPage = pgmPoolGetPage(pPool, HCPhysShw);
4060	if (!pPoolPage)
4061	{
4062	AssertMsgFailed(("Invalid page table address %RHp at %RGv! PdeDst=%#RX64\n",
4063	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
4064	cErrors++;
4065	continue;
4066	}
4067	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPoolPage);
4068
4069	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
4070	{
4071	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %RGv! These flags are not virtualized! PdeDst=%#RX64\n",
4072	GCPtr, (uint64_t)PdeDst.u));
4073	cErrors++;
4074	}
4075
4076	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
4077	{
4078	AssertMsgFailed(("4K PDE reserved flags at %RGv! PdeDst=%#RX64\n",
4079	GCPtr, (uint64_t)PdeDst.u));
4080	cErrors++;
4081	}
4082
4083	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
4084	if (!PdeSrc.n.u1Present)
4085	{
4086	AssertMsgFailed(("Guest PDE at %RGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
4087	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
4088	cErrors++;
4089	continue;
4090	}
4091
4092	if ( !PdeSrc.b.u1Size
4093	\|\| !fBigPagesSupported)
4094	{
4095	GCPhysGst = GST_GET_PDE_GCPHYS(PdeSrc);
4096	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4097	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| ((iPDDst & 1) * (PAGE_SIZE / 2)));
4098	# endif
4099	}
4100	else
4101	{
4102	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4103	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
4104	{
4105	AssertMsgFailed(("Guest PDE at %RGv is using PSE36 or similar! PdeSrc=%#RX64\n",
4106	GCPtr, (uint64_t)PdeSrc.u));
4107	cErrors++;
4108	continue;
4109	}
4110	# endif
4111	GCPhysGst = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
4112	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4113	GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst \| (GCPtr & RT_BIT(X86_PAGE_2M_SHIFT)));
4114	# endif
4115	}
4116
4117	if ( pPoolPage->enmKind
4118	!= (!PdeSrc.b.u1Size \|\| !fBigPagesSupported ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
4119	{
4120	AssertMsgFailed(("Invalid shadow page table kind %d at %RGv! PdeSrc=%#RX64\n",
4121	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
4122	cErrors++;
4123	}
4124
4125	PPGMPAGE pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4126	if (!pPhysPage)
4127	{
4128	AssertMsgFailed(("Cannot find guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4129	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4130	cErrors++;
4131	continue;
4132	}
4133
4134	if (GCPhysGst != pPoolPage->GCPhys)
4135	{
4136	AssertMsgFailed(("GCPhysGst=%RGp != pPage->GCPhys=%RGp at %RGv\n",
4137	GCPhysGst, pPoolPage->GCPhys, GCPtr));
4138	cErrors++;
4139	continue;
4140	}
4141
4142	if ( !PdeSrc.b.u1Size
4143	\|\| !fBigPagesSupported)
4144	{
4145	/*
4146	* Page Table.
4147	*/
4148	const GSTPT *pPTSrc;
4149	rc = PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, PGM_A20_APPLY(pVCpu, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1)),
4150	&pPTSrc);
4151	if (RT_FAILURE(rc))
4152	{
4153	AssertMsgFailed(("Cannot map/convert guest physical address %RGp in the PDE at %RGv! PdeSrc=%#RX64\n",
4154	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
4155	cErrors++;
4156	continue;
4157	}
4158	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
4159	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
4160	{
4161	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
4162	// (This problem will go away when/if we shadow multiple CR3s.)
4163	AssertMsgFailed(("4K PDE flags mismatch at %RGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4164	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4165	cErrors++;
4166	continue;
4167	}
4168	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4169	{
4170	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%RGv PdeDst=%#RX64\n",
4171	GCPtr, (uint64_t)PdeDst.u));
4172	cErrors++;
4173	continue;
4174	}
4175
4176	/* iterate the page table. */
4177	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
4178	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
4179	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
4180	# else
4181	const unsigned offPTSrc = 0;
4182	# endif
4183	for (unsigned iPT = 0, off = 0;
4184	iPT < RT_ELEMENTS(pPTDst->a);
4185	iPT++, off += PAGE_SIZE)
4186	{
4187	const SHWPTE PteDst = pPTDst->a[iPT];
4188
4189	/* skip not-present and dirty tracked entries. */
4190	if (!(SHW_PTE_GET_U(PteDst) & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
4191	continue;
4192	Assert(SHW_PTE_IS_P(PteDst));
4193
4194	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
4195	if (!PteSrc.n.u1Present)
4196	{
4197	# ifdef IN_RING3
4198	PGMAssertHandlerAndFlagsInSync(pVM);
4199	DBGFR3PagingDumpEx(pVM->pUVM, pVCpu->idCpu, DBGFPGDMP_FLAGS_CURRENT_CR3 \| DBGFPGDMP_FLAGS_CURRENT_MODE
4200	\| DBGFPGDMP_FLAGS_GUEST \| DBGFPGDMP_FLAGS_HEADER \| DBGFPGDMP_FLAGS_PRINT_CR3,
4201	0, 0, UINT64_MAX, 99, NULL);
4202	# endif
4203	AssertMsgFailed(("Out of sync (!P) PTE at %RGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%RGv iPTSrc=%x PdeSrc=%x physpte=%RGp\n",
4204	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst), pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
4205	(uint64_t)GST_GET_PDE_GCPHYS(PdeSrc) + (iPT + offPTSrc) * sizeof(PteSrc)));
4206	cErrors++;
4207	continue;
4208	}
4209
4210	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
4211	# if 1 /** @todo sync accessed bit properly... */
4212	fIgnoreFlags \|= X86_PTE_A;
4213	# endif
4214
4215	/* match the physical addresses */
4216	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4217	GCPhysGst = GST_GET_PTE_GCPHYS(PteSrc);
4218
4219	# ifdef IN_RING3
4220	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4221	if (RT_FAILURE(rc))
4222	{
4223	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4224	{
4225	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4226	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4227	cErrors++;
4228	continue;
4229	}
4230	}
4231	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
4232	{
4233	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4234	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4235	cErrors++;
4236	continue;
4237	}
4238	# endif
4239
4240	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4241	if (!pPhysPage)
4242	{
4243	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4244	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4245	{
4246	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PteSrc=%#RX64 PteDst=%#RX64\n",
4247	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4248	cErrors++;
4249	continue;
4250	}
4251	# endif
4252	if (SHW_PTE_IS_RW(PteDst))
4253	{
4254	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4255	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4256	cErrors++;
4257	}
4258	fIgnoreFlags \|= X86_PTE_RW;
4259	}
4260	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4261	{
4262	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage:%R[pgmpage] GCPhysGst=%RGp PteSrc=%#RX64 PteDst=%#RX64\n",
4263	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4264	cErrors++;
4265	continue;
4266	}
4267
4268	/* flags */
4269	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4270	{
4271	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4272	{
4273	if (SHW_PTE_IS_RW(PteDst))
4274	{
4275	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4276	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4277	cErrors++;
4278	continue;
4279	}
4280	fIgnoreFlags \|= X86_PTE_RW;
4281	}
4282	else
4283	{
4284	if ( SHW_PTE_IS_P(PteDst)
4285	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4286	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4287	# endif
4288	)
4289	{
4290	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PteSrc=%#RX64 PteDst=%#RX64\n",
4291	GCPtr + off, pPhysPage, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4292	cErrors++;
4293	continue;
4294	}
4295	fIgnoreFlags \|= X86_PTE_P;
4296	}
4297	}
4298	else
4299	{
4300	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
4301	{
4302	if (SHW_PTE_IS_RW(PteDst))
4303	{
4304	AssertMsgFailed(("!DIRTY page at %RGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
4305	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4306	cErrors++;
4307	continue;
4308	}
4309	if (!SHW_PTE_IS_TRACK_DIRTY(PteDst))
4310	{
4311	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4312	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4313	cErrors++;
4314	continue;
4315	}
4316	if (SHW_PTE_IS_D(PteDst))
4317	{
4318	AssertMsgFailed(("!DIRTY page at %RGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4319	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4320	cErrors++;
4321	}
4322	# if 0 /** @todo sync access bit properly... */
4323	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
4324	{
4325	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4326	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4327	cErrors++;
4328	}
4329	fIgnoreFlags \|= X86_PTE_RW;
4330	# else
4331	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4332	# endif
4333	}
4334	else if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4335	{
4336	/* access bit emulation (not implemented). */
4337	if (PteSrc.n.u1Accessed \|\| SHW_PTE_IS_P(PteDst))
4338	{
4339	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
4340	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4341	cErrors++;
4342	continue;
4343	}
4344	if (!SHW_PTE_IS_A(PteDst))
4345	{
4346	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
4347	GCPtr + off, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4348	cErrors++;
4349	}
4350	fIgnoreFlags \|= X86_PTE_P;
4351	}
4352	# ifdef DEBUG_sandervl
4353	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
4354	# endif
4355	}
4356
4357	if ( (PteSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4358	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4359	)
4360	{
4361	AssertMsgFailed(("Flags mismatch at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
4362	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4363	fIgnoreFlags, (uint64_t)PteSrc.u, SHW_PTE_LOG64(PteDst)));
4364	cErrors++;
4365	continue;
4366	}
4367	} /* foreach PTE */
4368	}
4369	else
4370	{
4371	/*
4372	* Big Page.
4373	*/
4374	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
4375	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
4376	{
4377	if (PdeDst.n.u1Write)
4378	{
4379	AssertMsgFailed(("!DIRTY page at %RGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4380	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4381	cErrors++;
4382	continue;
4383	}
4384	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
4385	{
4386	AssertMsgFailed(("!DIRTY page at %RGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
4387	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4388	cErrors++;
4389	continue;
4390	}
4391	# if 0 /** @todo sync access bit properly... */
4392	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
4393	{
4394	AssertMsgFailed(("!DIRTY page at %RGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
4395	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4396	cErrors++;
4397	}
4398	fIgnoreFlags \|= X86_PTE_RW;
4399	# else
4400	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
4401	# endif
4402	}
4403	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
4404	{
4405	/* access bit emulation (not implemented). */
4406	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
4407	{
4408	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %RGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4409	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4410	cErrors++;
4411	continue;
4412	}
4413	if (!PdeDst.n.u1Accessed)
4414	{
4415	AssertMsgFailed(("!ACCESSED page at %RGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
4416	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4417	cErrors++;
4418	}
4419	fIgnoreFlags \|= X86_PTE_P;
4420	}
4421
4422	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
4423	{
4424	AssertMsgFailed(("Flags mismatch (B) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
4425	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
4426	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
4427	cErrors++;
4428	}
4429
4430	/* iterate the page table. */
4431	for (unsigned iPT = 0, off = 0;
4432	iPT < RT_ELEMENTS(pPTDst->a);
4433	iPT++, off += PAGE_SIZE, GCPhysGst = PGM_A20_APPLY(pVCpu, GCPhysGst + PAGE_SIZE))
4434	{
4435	const SHWPTE PteDst = pPTDst->a[iPT];
4436
4437	if (SHW_PTE_IS_TRACK_DIRTY(PteDst))
4438	{
4439	AssertMsgFailed(("The PTE at %RGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
4440	GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4441	cErrors++;
4442	}
4443
4444	/* skip not-present entries. */
4445	if (!SHW_PTE_IS_P(PteDst)) /** @todo deal with ALL handlers and CSAM !P pages! */
4446	continue;
4447
4448	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT \| X86_PTE_D \| X86_PTE_A \| X86_PTE_G \| X86_PTE_PAE_NX;
4449
4450	/* match the physical addresses */
4451	HCPhysShw = SHW_PTE_GET_HCPHYS(PteDst);
4452
4453	# ifdef IN_RING3
4454	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
4455	if (RT_FAILURE(rc))
4456	{
4457	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4458	{
4459	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4460	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4461	cErrors++;
4462	}
4463	}
4464	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
4465	{
4466	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp HCPhys=%RHp GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4467	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4468	cErrors++;
4469	continue;
4470	}
4471	# endif
4472	pPhysPage = pgmPhysGetPage(pVM, GCPhysGst);
4473	if (!pPhysPage)
4474	{
4475	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
4476	if (HCPhysShw != MMR3PageDummyHCPhys(pVM)) /** @todo this is wrong. */
4477	{
4478	AssertMsgFailed(("Cannot find guest physical address %RGp at %RGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
4479	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4480	cErrors++;
4481	continue;
4482	}
4483	# endif
4484	if (SHW_PTE_IS_RW(PteDst))
4485	{
4486	AssertMsgFailed(("Invalid guest page at %RGv is writable! GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4487	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4488	cErrors++;
4489	}
4490	fIgnoreFlags \|= X86_PTE_RW;
4491	}
4492	else if (HCPhysShw != PGM_PAGE_GET_HCPHYS(pPhysPage))
4493	{
4494	AssertMsgFailed(("Out of sync (phys) at %RGv! HCPhysShw=%RHp pPhysPage=%R[pgmpage] GCPhysGst=%RGp PdeSrc=%#RX64 PteDst=%#RX64\n",
4495	GCPtr + off, HCPhysShw, pPhysPage, GCPhysGst, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4496	cErrors++;
4497	continue;
4498	}
4499
4500	/* flags */
4501	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
4502	{
4503	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
4504	{
4505	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
4506	{
4507	if (SHW_PTE_IS_RW(PteDst))
4508	{
4509	AssertMsgFailed(("WRITE access flagged at %RGv but the page is writable! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4510	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4511	cErrors++;
4512	continue;
4513	}
4514	fIgnoreFlags \|= X86_PTE_RW;
4515	}
4516	}
4517	else
4518	{
4519	if ( SHW_PTE_IS_P(PteDst)
4520	# if PGM_SHW_TYPE == PGM_TYPE_EPT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE \|\| PGM_SHW_TYPE == PGM_TYPE_AMD64
4521	&& !PGM_PAGE_IS_MMIO(pPhysPage)
4522	# endif
4523	)
4524	{
4525	AssertMsgFailed(("ALL access flagged at %RGv but the page is present! pPhysPage=%R[pgmpage] PdeSrc=%#RX64 PteDst=%#RX64\n",
4526	GCPtr + off, pPhysPage, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4527	cErrors++;
4528	continue;
4529	}
4530	fIgnoreFlags \|= X86_PTE_P;
4531	}
4532	}
4533
4534	if ( (PdeSrc.u & ~fIgnoreFlags) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags)
4535	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (SHW_PTE_GET_U(PteDst) & ~fIgnoreFlags) /* lazy phys handler dereg. */
4536	)
4537	{
4538	AssertMsgFailed(("Flags mismatch (BT) at %RGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
4539	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, SHW_PTE_LOG64(PteDst) & ~fIgnoreFlags,
4540	fIgnoreFlags, (uint64_t)PdeSrc.u, SHW_PTE_LOG64(PteDst)));
4541	cErrors++;
4542	continue;
4543	}
4544	} /* for each PTE */
4545	}
4546	}
4547	/* not present */
4548
4549	} /* for each PDE */
4550
4551	} /* for each PDPTE */
4552
4553	} /* for each PML4E */
4554
4555	# ifdef DEBUG
4556	if (cErrors)
4557	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
4558	# endif
4559	# endif /* GST is in {32BIT, PAE, AMD64} */
4560	return cErrors;
4561	#endif /* PGM_SHW_TYPE != PGM_TYPE_NESTED && PGM_SHW_TYPE != PGM_TYPE_EPT */
4562	}
4563	#endif /* VBOX_STRICT */
4564
4565
4566	/**
4567	* Sets up the CR3 for shadow paging
4568	*
4569	* @returns Strict VBox status code.
4570	* @retval VINF_SUCCESS.
4571	*
4572	* @param pVCpu The cross context virtual CPU structure.
4573	* @param GCPhysCR3 The physical address in the CR3 register. (A20
4574	* mask already applied.)
4575	*/
4576	PGM_BTH_DECL(int, MapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3)
4577	{
4578	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4579
4580	/* Update guest paging info. */
4581	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
4582	\|\| PGM_GST_TYPE == PGM_TYPE_PAE \
4583	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
4584
4585	LogFlow(("MapCR3: %RGp\n", GCPhysCR3));
4586	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4587
4588	/*
4589	* Map the page CR3 points at.
4590	*/
4591	RTHCPTR HCPtrGuestCR3;
4592	RTHCPHYS HCPhysGuestCR3;
4593	pgmLock(pVM);
4594	PPGMPAGE pPageCR3 = pgmPhysGetPage(pVM, GCPhysCR3);
4595	AssertReturn(pPageCR3, VERR_PGM_INVALID_CR3_ADDR);
4596	HCPhysGuestCR3 = PGM_PAGE_GET_HCPHYS(pPageCR3);
4597	/** @todo this needs some reworking wrt. locking? */
4598	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4599	HCPtrGuestCR3 = NIL_RTHCPTR;
4600	int rc = VINF_SUCCESS;
4601	# else
4602	int rc = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPageCR3, GCPhysCR3 & GST_CR3_PAGE_MASK, (void )&HCPtrGuestCR3); / @todo r=bird: This GCPhysCR3 masking isn't necessary. */
4603	# endif
4604	pgmUnlock(pVM);
4605	if (RT_SUCCESS(rc))
4606	{
4607	rc = PGMMap(pVM, (RTGCPTR)pVM->pgm.s.GCPtrCR3Mapping, HCPhysGuestCR3, PAGE_SIZE, 0);
4608	if (RT_SUCCESS(rc))
4609	{
4610	# ifdef IN_RC
4611	PGM_INVL_PG(pVCpu, pVM->pgm.s.GCPtrCR3Mapping);
4612	# endif
4613	# if PGM_GST_TYPE == PGM_TYPE_32BIT
4614	pVCpu->pgm.s.pGst32BitPdR3 = (R3PTRTYPE(PX86PD))HCPtrGuestCR3;
4615	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4616	pVCpu->pgm.s.pGst32BitPdR0 = (R0PTRTYPE(PX86PD))HCPtrGuestCR3;
4617	# endif
4618	pVCpu->pgm.s.pGst32BitPdRC = (RCPTRTYPE(PX86PD))(RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping;
4619
4620	# elif PGM_GST_TYPE == PGM_TYPE_PAE
4621	unsigned off = GCPhysCR3 & GST_CR3_PAGE_MASK & PAGE_OFFSET_MASK;
4622	pVCpu->pgm.s.pGstPaePdptR3 = (R3PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4623	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4624	pVCpu->pgm.s.pGstPaePdptR0 = (R0PTRTYPE(PX86PDPT))HCPtrGuestCR3;
4625	# endif
4626	pVCpu->pgm.s.pGstPaePdptRC = (RCPTRTYPE(PX86PDPT))((RTRCUINTPTR)pVM->pgm.s.GCPtrCR3Mapping + off);
4627	LogFlow(("Cached mapping %RRv\n", pVCpu->pgm.s.pGstPaePdptRC));
4628
4629	/*
4630	* Map the 4 PDs too.
4631	*/
4632	PX86PDPT pGuestPDPT = pgmGstGetPaePDPTPtr(pVCpu);
4633	RTGCPTR GCPtr = pVM->pgm.s.GCPtrCR3Mapping + PAGE_SIZE;
4634	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++, GCPtr += PAGE_SIZE)
4635	{
4636	pVCpu->pgm.s.aGstPaePdpeRegs[i].u = pGuestPDPT->a[i].u;
4637	if (pGuestPDPT->a[i].n.u1Present)
4638	{
4639	RTHCPTR HCPtr;
4640	RTHCPHYS HCPhys;
4641	RTGCPHYS GCPhys = PGM_A20_APPLY(pVCpu, pGuestPDPT->a[i].u & X86_PDPE_PG_MASK);
4642	pgmLock(pVM);
4643	PPGMPAGE pPage = pgmPhysGetPage(pVM, GCPhys);
4644	AssertReturn(pPage, VERR_PGM_INVALID_PDPE_ADDR);
4645	HCPhys = PGM_PAGE_GET_HCPHYS(pPage);
4646	# if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
4647	HCPtr = NIL_RTHCPTR;
4648	int rc2 = VINF_SUCCESS;
4649	# else
4650	int rc2 = pgmPhysGCPhys2CCPtrInternalDepr(pVM, pPage, GCPhys, (void **)&HCPtr);
4651	# endif
4652	pgmUnlock(pVM);
4653	if (RT_SUCCESS(rc2))
4654	{
4655	rc = PGMMap(pVM, GCPtr, HCPhys, PAGE_SIZE, 0);
4656	AssertRCReturn(rc, rc);
4657
4658	pVCpu->pgm.s.apGstPaePDsR3[i] = (R3PTRTYPE(PX86PDPAE))HCPtr;
4659	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4660	pVCpu->pgm.s.apGstPaePDsR0[i] = (R0PTRTYPE(PX86PDPAE))HCPtr;
4661	# endif
4662	pVCpu->pgm.s.apGstPaePDsRC[i] = (RCPTRTYPE(PX86PDPAE))(RTRCUINTPTR)GCPtr;
4663	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = GCPhys;
4664	# ifdef IN_RC
4665	PGM_INVL_PG(pVCpu, GCPtr);
4666	# endif
4667	continue;
4668	}
4669	AssertMsgFailed(("pgmR3Gst32BitMapCR3: rc2=%d GCPhys=%RGp i=%d\n", rc2, GCPhys, i));
4670	}
4671
4672	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4673	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4674	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4675	# endif
4676	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4677	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4678	# ifdef IN_RC
4679	PGM_INVL_PG(pVCpu, GCPtr); /** @todo this shouldn't be necessary? */
4680	# endif
4681	}
4682
4683	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
4684	pVCpu->pgm.s.pGstAmd64Pml4R3 = (R3PTRTYPE(PX86PML4))HCPtrGuestCR3;
4685	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4686	pVCpu->pgm.s.pGstAmd64Pml4R0 = (R0PTRTYPE(PX86PML4))HCPtrGuestCR3;
4687	# endif
4688	# endif
4689	}
4690	else
4691	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4692	}
4693	else
4694	AssertMsgFailed(("rc=%Rrc GCPhysGuestPD=%RGp\n", rc, GCPhysCR3));
4695
4696	#else /* prot/real stub */
4697	int rc = VINF_SUCCESS;
4698	#endif
4699
4700	/* Update shadow paging info for guest modes with paging (32, pae, 64). */
4701	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4702	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4703	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64) \
4704	&& ( PGM_GST_TYPE != PGM_TYPE_REAL \
4705	&& PGM_GST_TYPE != PGM_TYPE_PROT))
4706
4707	Assert(!pVM->pgm.s.fNestedPaging);
4708	PGM_A20_ASSERT_MASKED(pVCpu, GCPhysCR3);
4709
4710	/*
4711	* Update the shadow root page as well since that's not fixed.
4712	*/
4713	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4714	PPGMPOOLPAGE pOldShwPageCR3 = pVCpu->pgm.s.CTX_SUFF(pShwPageCR3);
4715	PPGMPOOLPAGE pNewShwPageCR3;
4716
4717	pgmLock(pVM);
4718
4719	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4720	if (pPool->cDirtyPages)
4721	pgmPoolResetDirtyPages(pVM);
4722	# endif
4723
4724	Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
4725	rc = pgmPoolAlloc(pVM, GCPhysCR3 & GST_CR3_PAGE_MASK, BTH_PGMPOOLKIND_ROOT, PGMPOOLACCESS_DONTCARE, PGM_A20_IS_ENABLED(pVCpu),
4726	NIL_PGMPOOL_IDX, UINT32_MAX, true /fLockPage/,
4727	&pNewShwPageCR3);
4728	AssertFatalRC(rc);
4729	rc = VINF_SUCCESS;
4730
4731	# ifdef IN_RC
4732	/*
4733	* WARNING! We can't deal with jumps to ring 3 in the code below as the
4734	* state will be inconsistent! Flush important things now while
4735	* we still can and then make sure there are no ring-3 calls.
4736	*/
4737	# ifdef VBOX_WITH_REM
4738	REMNotifyHandlerPhysicalFlushIfAlmostFull(pVM, pVCpu);
4739	# endif
4740	VMMRZCallRing3Disable(pVCpu);
4741	# endif
4742
4743	pVCpu->pgm.s.CTX_SUFF(pShwPageCR3) = pNewShwPageCR3;
4744	# ifdef IN_RING0
4745	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4746	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4747	# elif defined(IN_RC)
4748	pVCpu->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4749	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4750	# else
4751	pVCpu->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4752	pVCpu->pgm.s.pShwPageCR3RC = MMHyperCCToRC(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4753	# endif
4754
4755	# ifndef PGM_WITHOUT_MAPPINGS
4756	/*
4757	* Apply all hypervisor mappings to the new CR3.
4758	* Note that SyncCR3 will be executed in case CR3 is changed in a guest paging mode; this will
4759	* make sure we check for conflicts in the new CR3 root.
4760	*/
4761	# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
4762	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL) \|\| VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4763	# endif
4764	rc = pgmMapActivateCR3(pVM, pNewShwPageCR3);
4765	AssertRCReturn(rc, rc);
4766	# endif
4767
4768	/* Set the current hypervisor CR3. */
4769	CPUMSetHyperCR3(pVCpu, PGMGetHyperCR3(pVCpu));
4770	SELMShadowCR3Changed(pVM, pVCpu);
4771
4772	# ifdef IN_RC
4773	/* NOTE: The state is consistent again. */
4774	VMMRZCallRing3Enable(pVCpu);
4775	# endif
4776
4777	/* Clean up the old CR3 root. */
4778	if ( pOldShwPageCR3
4779	&& pOldShwPageCR3 != pNewShwPageCR3 /* @todo can happen due to incorrect syncing between REM & PGM; find the real cause */)
4780	{
4781	Assert(pOldShwPageCR3->enmKind != PGMPOOLKIND_FREE);
4782	# ifndef PGM_WITHOUT_MAPPINGS
4783	/* Remove the hypervisor mappings from the shadow page table. */
4784	pgmMapDeactivateCR3(pVM, pOldShwPageCR3);
4785	# endif
4786	/* Mark the page as unlocked; allow flushing again. */
4787	pgmPoolUnlockPage(pPool, pOldShwPageCR3);
4788
4789	pgmPoolFreeByPage(pPool, pOldShwPageCR3, NIL_PGMPOOL_IDX, UINT32_MAX);
4790	}
4791	pgmUnlock(pVM);
4792	# else
4793	NOREF(GCPhysCR3);
4794	# endif
4795
4796	return rc;
4797	}
4798
4799	/**
4800	* Unmaps the shadow CR3.
4801	*
4802	* @returns VBox status, no specials.
4803	* @param pVCpu The cross context virtual CPU structure.
4804	*/
4805	PGM_BTH_DECL(int, UnmapCR3)(PVMCPU pVCpu)
4806	{
4807	LogFlow(("UnmapCR3\n"));
4808
4809	int rc = VINF_SUCCESS;
4810	PVM pVM = pVCpu->CTX_SUFF(pVM); NOREF(pVM);
4811
4812	/*
4813	* Update guest paging info.
4814	*/
4815	#if PGM_GST_TYPE == PGM_TYPE_32BIT
4816	pVCpu->pgm.s.pGst32BitPdR3 = 0;
4817	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4818	pVCpu->pgm.s.pGst32BitPdR0 = 0;
4819	# endif
4820	pVCpu->pgm.s.pGst32BitPdRC = 0;
4821
4822	#elif PGM_GST_TYPE == PGM_TYPE_PAE
4823	pVCpu->pgm.s.pGstPaePdptR3 = 0;
4824	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4825	pVCpu->pgm.s.pGstPaePdptR0 = 0;
4826	# endif
4827	pVCpu->pgm.s.pGstPaePdptRC = 0;
4828	for (unsigned i = 0; i < X86_PG_PAE_PDPE_ENTRIES; i++)
4829	{
4830	pVCpu->pgm.s.apGstPaePDsR3[i] = 0;
4831	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4832	pVCpu->pgm.s.apGstPaePDsR0[i] = 0;
4833	# endif
4834	pVCpu->pgm.s.apGstPaePDsRC[i] = 0;
4835	pVCpu->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
4836	}
4837
4838	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
4839	pVCpu->pgm.s.pGstAmd64Pml4R3 = 0;
4840	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4841	pVCpu->pgm.s.pGstAmd64Pml4R0 = 0;
4842	# endif
4843
4844	#else /* prot/real mode stub */
4845	/* nothing to do */
4846	#endif
4847
4848	#if !defined(IN_RC) /* In RC we rely on MapCR3 to do the shadow part for us at a safe time */
4849	/*
4850	* Update shadow paging info.
4851	*/
4852	# if ( ( PGM_SHW_TYPE == PGM_TYPE_32BIT \
4853	\|\| PGM_SHW_TYPE == PGM_TYPE_PAE \
4854	\|\| PGM_SHW_TYPE == PGM_TYPE_AMD64))
4855
4856	# if PGM_GST_TYPE != PGM_TYPE_REAL
4857	Assert(!pVM->pgm.s.fNestedPaging);
4858	# endif
4859
4860	pgmLock(pVM);
4861
4862	# ifndef PGM_WITHOUT_MAPPINGS
4863	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4864	/* Remove the hypervisor mappings from the shadow page table. */
4865	pgmMapDeactivateCR3(pVM, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4866	# endif
4867
4868	if (pVCpu->pgm.s.CTX_SUFF(pShwPageCR3))
4869	{
4870	PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
4871
4872	# ifdef PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
4873	if (pPool->cDirtyPages)
4874	pgmPoolResetDirtyPages(pVM);
4875	# endif
4876
4877	/* Mark the page as unlocked; allow flushing again. */
4878	pgmPoolUnlockPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3));
4879
4880	pgmPoolFreeByPage(pPool, pVCpu->pgm.s.CTX_SUFF(pShwPageCR3), NIL_PGMPOOL_IDX, UINT32_MAX);
4881	pVCpu->pgm.s.pShwPageCR3R3 = 0;
4882	pVCpu->pgm.s.pShwPageCR3R0 = 0;
4883	pVCpu->pgm.s.pShwPageCR3RC = 0;
4884	}
4885	pgmUnlock(pVM);
4886	# endif
4887	#endif /* !IN_RC*/
4888
4889	return rc;
4890	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 65452

Download in other formats: