VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7664

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1/* $Id: PGMAllBth.h 7664 2008-03-31 14:40:29Z vboxsync $ */
2/** @file
3 * VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4 *
5 * This file is a big challenge!
6 */
7
8/*
9 * Copyright (C) 2006-2007 innotek GmbH
10 *
11 * This file is part of VirtualBox Open Source Edition (OSE), as
12 * available from http://www.virtualbox.org. This file is free software;
13 * you can redistribute it and/or modify it under the terms of the GNU
14 * General Public License (GPL) as published by the Free Software
15 * Foundation, in version 2 as it comes in the "COPYING" file of the
16 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18 */
19
20/*******************************************************************************
21* Internal Functions *
22*******************************************************************************/
23__BEGIN_DECLS
24PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32#ifdef VBOX_STRICT
33PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34#endif
35#ifdef PGMPOOL_WITH_USER_TRACKING
36DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37#endif
38__END_DECLS
39
40
41/**
42 * #PF Handler for raw-mode guest execution.
43 *
44 * @returns VBox status code (appropriate for trap handling and GC return).
45 * @param pVM VM Handle.
46 * @param uErr The trap error code.
47 * @param pRegFrame Trap register frame.
48 * @param pvFault The fault address.
49 */
50PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
51{
52#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
53
54# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
55# error "32-bit guest mode is only implemented for 32-bit and PAE shadow modes."
56# endif
57
58# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
59 /*
60 * Hide the instruction fetch trap indicator for now.
61 */
62 /** @todo NXE will change this and we must fix NXE in the switcher too! */
63 if (uErr & X86_TRAP_PF_ID)
64 {
65 uErr &= ~X86_TRAP_PF_ID;
66 TRPMSetErrorCode(pVM, uErr);
67 }
68# endif
69
70 /*
71 * Get PDs.
72 */
73 int rc;
74# if PGM_WITH_PAGING(PGM_GST_TYPE)
75# if PGM_GST_TYPE == PGM_TYPE_32BIT
76 const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
77 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
78# else /* PAE */
79 unsigned iPDSrc;
80 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
81# endif
82# else
83 PGSTPD pPDSrc = NULL;
84 const unsigned iPDSrc = 0;
85# endif
86
87 const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
88# if PGM_SHW_TYPE == PGM_TYPE_32BIT
89 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
90# else /* PAE */
91 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
92# endif
93
94# if PGM_WITH_PAGING(PGM_GST_TYPE)
95# ifdef PGM_SYNC_DIRTY_BIT
96 /*
97 * If we successfully correct the write protection fault due to dirty bit
98 * tracking, or this page fault is a genuine one, then return immediately.
99 */
100 STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
101 rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
102 STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
103 if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
104 || rc == VINF_EM_RAW_GUEST_TRAP)
105 {
106 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
107 = rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
108 LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
109 return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
110 }
111# endif
112
113 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
114# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
115
116 /*
117 * A common case is the not-present error caused by lazy page table syncing.
118 *
119 * It is IMPORTANT that we weed out any access to non-present shadow PDEs here
120 * so we can safely assume that the shadow PT is present when calling SyncPage later.
121 *
122 * On failure, we ASSUME that SyncPT is out of memory or detected some kind
123 * of mapping conflict and defer to SyncCR3 in R3.
124 * (Again, we do NOT support access handlers for non-present guest pages.)
125 *
126 */
127# if PGM_WITH_PAGING(PGM_GST_TYPE)
128 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
129# else
130 GSTPDE PdeSrc;
131 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
132 PdeSrc.n.u1Present = 1;
133 PdeSrc.n.u1Write = 1;
134 PdeSrc.n.u1Accessed = 1;
135 PdeSrc.n.u1User = 1;
136# endif
137 if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
138 && !pPDDst->a[iPDDst].n.u1Present
139 && PdeSrc.n.u1Present
140 )
141
142 {
143 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
144 STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
145 LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
146 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
147 if (VBOX_SUCCESS(rc))
148 {
149 STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
150 return rc;
151 }
152 Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
153 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
154 STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
155 return VINF_PGM_SYNC_CR3;
156 }
157
158# if PGM_WITH_PAGING(PGM_GST_TYPE)
159 /*
160 * Check if this address is within any of our mappings.
161 *
162 * This is *very* fast and it's gonna save us a bit of effort below and prevent
163 * us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
164 * (BTW, it's impossible to have physical access handlers in a mapping.)
165 */
166 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
167 {
168 STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
169 PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
170 for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
171 {
172 if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
173 break;
174 if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
175 {
176 /*
177 * The first thing we check is if we've got an undetected conflict.
178 */
179 if (!pVM->pgm.s.fMappingsFixed)
180 {
181 unsigned iPT = pMapping->cPTs;
182 while (iPT-- > 0)
183 if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
184 {
185 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
186 Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
187 VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
188 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
189 return VINF_PGM_SYNC_CR3;
190 }
191 }
192
193 /*
194 * Check if the fault address is in a virtual page access handler range.
195 */
196 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
197 if ( pCur
198 && (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
199 && uErr & X86_TRAP_PF_RW)
200 {
201# ifdef IN_GC
202 STAM_PROFILE_START(&pCur->Stat, h);
203 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
204 STAM_PROFILE_STOP(&pCur->Stat, h);
205# else
206 AssertFailed();
207 rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
208# endif
209 STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
210 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
211 return rc;
212 }
213
214 /*
215 * Pretend we're not here and let the guest handle the trap.
216 */
217 TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
218 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
219 LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
220 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
221 return VINF_EM_RAW_GUEST_TRAP;
222 }
223 }
224 STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
225 } /* pgmAreMappingsEnabled(&pVM->pgm.s) */
226# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
227
228 /*
229 * Check if this fault address is flagged for special treatment,
230 * which means we'll have to figure out the physical address and
231 * check flags associated with it.
232 *
233 * ASSUME that we can limit any special access handling to pages
234 * in page tables which the guest believes to be present.
235 */
236 if (PdeSrc.n.u1Present)
237 {
238 RTGCPHYS GCPhys = NIL_RTGCPHYS;
239
240# if PGM_WITH_PAGING(PGM_GST_TYPE)
241 uint32_t cr4 = CPUMGetGuestCR4(pVM);
242 if ( PdeSrc.b.u1Size
243 && (cr4 & X86_CR4_PSE))
244 GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
245 | ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
246 else
247 {
248 PX86PT pPTSrc;
249# ifdef IN_GC
250 rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & GST_PDE_PG_MASK, (void **)&pPTSrc);
251# else
252 pPTSrc = (PX86PT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & GST_PDE_PG_MASK, sizeof(*pPTSrc));
253 if (pPTSrc == 0)
254 rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
255# endif
256 if (VBOX_SUCCESS(rc))
257 {
258 unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & GST_PT_MASK;
259 if (pPTSrc->a[iPTESrc].n.u1Present)
260 GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
261 }
262 }
263# else
264 /* No paging so the fault address is the physical address */
265 GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
266# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
267
268 /*
269 * If we have a GC address we'll check if it has any flags set.
270 */
271 if (GCPhys != NIL_RTGCPHYS)
272 {
273 STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
274
275 PPGMPAGE pPage;
276 rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
277 if (VBOX_SUCCESS(rc))
278 {
279 if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
280 {
281 if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
282 {
283 /*
284 * Physical page access handler.
285 */
286 const RTGCPHYS GCPhysFault = GCPhys | ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
287 PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
288 if (pCur)
289 {
290# ifdef PGM_SYNC_N_PAGES
291 /*
292 * If the region is write protected and we got a page not present fault, then sync
293 * the pages. If the fault was caused by a read, then restart the instruction.
294 * In case of write access continue to the GC write handler.
295 *
296 * ASSUMES that there is only one handler per page or that they have similar write properties.
297 */
298 if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
299 && !(uErr & X86_TRAP_PF_P))
300 {
301 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
302 if ( VBOX_FAILURE(rc)
303 || !(uErr & X86_TRAP_PF_RW)
304 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
305 {
306 AssertRC(rc);
307 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
308 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
309 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
310 return rc;
311 }
312 }
313# endif
314
315 AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
316 || (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
317 ("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
318
319#if defined(IN_GC) || defined(IN_RING0)
320 if (CTXALLSUFF(pCur->pfnHandler))
321 {
322 STAM_PROFILE_START(&pCur->Stat, h);
323 rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
324 STAM_PROFILE_STOP(&pCur->Stat, h);
325 }
326 else
327#endif
328 rc = VINF_EM_RAW_EMULATE_INSTR;
329 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
330 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
331 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
332 return rc;
333 }
334 }
335# if PGM_WITH_PAGING(PGM_GST_TYPE)
336 else
337 {
338# ifdef PGM_SYNC_N_PAGES
339 /*
340 * If the region is write protected and we got a page not present fault, then sync
341 * the pages. If the fault was caused by a read, then restart the instruction.
342 * In case of write access continue to the GC write handler.
343 */
344 if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
345 && !(uErr & X86_TRAP_PF_P))
346 {
347 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
348 if ( VBOX_FAILURE(rc)
349 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
350 || !(uErr & X86_TRAP_PF_RW))
351 {
352 AssertRC(rc);
353 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
354 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
355 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
356 return rc;
357 }
358 }
359# endif
360 /*
361 * Ok, it's an virtual page access handler.
362 *
363 * Since it's faster to search by address, we'll do that first
364 * and then retry by GCPhys if that fails.
365 */
366 /** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
367 /** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
368 * page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
369 */
370 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
371 if (pCur)
372 {
373 AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
374 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
375 || !(uErr & X86_TRAP_PF_P)
376 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
377 ("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
378
379 if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
380 && ( uErr & X86_TRAP_PF_RW
381 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
382 {
383# ifdef IN_GC
384 STAM_PROFILE_START(&pCur->Stat, h);
385 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
386 STAM_PROFILE_STOP(&pCur->Stat, h);
387# else
388 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
389# endif
390 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
391 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
392 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
393 return rc;
394 }
395 /* Unhandled part of a monitored page */
396 }
397 else
398 {
399 /* Check by physical address. */
400 PPGMVIRTHANDLER pCur;
401 unsigned iPage;
402 rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
403 &pCur, &iPage);
404 Assert(VBOX_SUCCESS(rc) || !pCur);
405 if ( pCur
406 && ( uErr & X86_TRAP_PF_RW
407 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
408 {
409 Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
410# ifdef IN_GC
411 RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
412 Assert(off < pCur->cb);
413 STAM_PROFILE_START(&pCur->Stat, h);
414 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
415 STAM_PROFILE_STOP(&pCur->Stat, h);
416# else
417 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
418# endif
419 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
420 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
421 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
422 return rc;
423 }
424 }
425 }
426# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
427
428 /*
429 * There is a handled area of the page, but this fault doesn't belong to it.
430 * We must emulate the instruction.
431 *
432 * To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
433 * we first check if this was a page-not-present fault for a page with only
434 * write access handlers. Restart the instruction if it wasn't a write access.
435 */
436 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
437
438 if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
439 && !(uErr & X86_TRAP_PF_P))
440 {
441 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
442 if ( VBOX_FAILURE(rc)
443 || rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
444 || !(uErr & X86_TRAP_PF_RW))
445 {
446 AssertRC(rc);
447 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
448 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
449 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
450 return rc;
451 }
452 }
453
454 /** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
455 * It's writing to an unhandled part of the LDT page several million times.
456 */
457 rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
458 LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
459 rc, pPage->HCPhys,
460 PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
461 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
462 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
463 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
464 return rc;
465 } /* if any kind of handler */
466
467# if PGM_WITH_PAGING(PGM_GST_TYPE)
468 if (uErr & X86_TRAP_PF_P)
469 {
470 /*
471 * The page isn't marked, but it might still be monitored by a virtual page access handler.
472 * (ASSUMES no temporary disabling of virtual handlers.)
473 */
474 /** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
475 * we should correct both the shadow page table and physical memory flags, and not only check for
476 * accesses within the handler region but for access to pages with virtual handlers. */
477 PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
478 if (pCur)
479 {
480 AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
481 || ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
482 || !(uErr & X86_TRAP_PF_P)
483 || (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
484 ("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
485
486 if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
487 && ( uErr & X86_TRAP_PF_RW
488 || pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
489 {
490# ifdef IN_GC
491 STAM_PROFILE_START(&pCur->Stat, h);
492 rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
493 STAM_PROFILE_STOP(&pCur->Stat, h);
494# else
495 rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
496# endif
497 STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
498 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
499 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
500 return rc;
501 }
502 }
503 }
504# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
505 }
506 STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
507
508# ifdef PGM_OUT_OF_SYNC_IN_GC
509 /*
510 * We are here only if page is present in Guest page tables and trap is not handled
511 * by our handlers.
512 * Check it for page out-of-sync situation.
513 */
514 STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
515
516 if (!(uErr & X86_TRAP_PF_P))
517 {
518 /*
519 * Page is not present in our page tables.
520 * Try to sync it!
521 * BTW, fPageShw is invalid in this branch!
522 */
523 if (uErr & X86_TRAP_PF_US)
524 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
525 else /* supervisor */
526 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
527
528# if defined(LOG_ENABLED) && !defined(IN_RING0)
529 RTGCPHYS GCPhys;
530 uint64_t fPageGst;
531 PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
532 Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
533 pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
534# endif /* LOG_ENABLED */
535
536# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
537 if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
538 {
539 uint64_t fPageGst;
540 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
541 if ( VBOX_SUCCESS(rc)
542 && !(fPageGst & X86_PTE_US))
543 {
544 /* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
545 if ( pvFault == (RTGCPTR)pRegFrame->eip
546 || (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
547# ifdef CSAM_DETECT_NEW_CODE_PAGES
548 || ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
549 && CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
550# endif /* CSAM_DETECT_NEW_CODE_PAGES */
551 )
552 {
553 LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
554 rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
555 if (rc != VINF_SUCCESS)
556 {
557 /*
558 * CSAM needs to perform a job in ring 3.
559 *
560 * Sync the page before going to the host context; otherwise we'll end up in a loop if
561 * CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
562 */
563 LogFlow(("CSAM ring 3 job\n"));
564 int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
565 AssertRC(rc2);
566
567 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
568 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
569 return rc;
570 }
571 }
572# ifdef CSAM_DETECT_NEW_CODE_PAGES
573 else
574 if ( uErr == X86_TRAP_PF_RW
575 && pRegFrame->ecx >= 0x100 /* early check for movswd count */
576 && pRegFrame->ecx < 0x10000
577 )
578 {
579 /* In case of a write to a non-present supervisor shadow page, we'll take special precautions
580 * to detect loading of new code pages.
581 */
582
583 /*
584 * Decode the instruction.
585 */
586 RTGCPTR PC;
587 rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
588 if (rc == VINF_SUCCESS)
589 {
590 DISCPUSTATE Cpu;
591 uint32_t cbOp;
592 rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
593
594 /* For now we'll restrict this to rep movsw/d instructions */
595 if ( rc == VINF_SUCCESS
596 && Cpu.pCurInstr->opcode == OP_MOVSWD
597 && (Cpu.prefix & PREFIX_REP))
598 {
599 CSAMMarkPossibleCodePage(pVM, pvFault);
600 }
601 }
602 }
603# endif /* CSAM_DETECT_NEW_CODE_PAGES */
604
605 /*
606 * Mark this page as safe.
607 */
608 /** @todo not correct for pages that contain both code and data!! */
609 Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
610 CSAMMarkPage(pVM, pvFault, true);
611 }
612 }
613# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
614 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
615 if (VBOX_SUCCESS(rc))
616 {
617 /* The page was successfully synced, return to the guest. */
618 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
619 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
620 return VINF_SUCCESS;
621 }
622 }
623 else
624 {
625 /*
626 * A side effect of not flushing global PDEs are out of sync pages due
627 * to physical monitored regions, that are no longer valid.
628 * Assume for now it only applies to the read/write flag
629 */
630 if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
631 {
632 if (uErr & X86_TRAP_PF_US)
633 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
634 else /* supervisor */
635 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
636
637
638 /*
639 * Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
640 */
641 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
642 if (VBOX_SUCCESS(rc))
643 {
644 /*
645 * Page was successfully synced, return to guest.
646 */
647# ifdef VBOX_STRICT
648 RTGCPHYS GCPhys;
649 uint64_t fPageGst;
650 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
651 Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
652 LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
653
654 uint64_t fPageShw;
655 rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
656 Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
657# endif /* VBOX_STRICT */
658 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
659 STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
660 return VINF_SUCCESS;
661 }
662 }
663
664# if PGM_WITH_PAGING(PGM_GST_TYPE)
665# ifdef VBOX_STRICT
666 /*
667 * Check for VMM page flags vs. Guest page flags consistency.
668 * Currently only for debug purposes.
669 */
670 if (VBOX_SUCCESS(rc))
671 {
672 /* Get guest page flags. */
673 uint64_t fPageGst;
674 rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
675 if (VBOX_SUCCESS(rc))
676 {
677 uint64_t fPageShw;
678 rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
679
680 /*
681 * Compare page flags.
682 * Note: we have AVL, A, D bits desynched.
683 */
684 AssertMsg((fPageShw & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A | X86_PTE_D | X86_PTE_AVL_MASK)),
685 ("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
686 }
687 else
688 AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
689 }
690 else
691 AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
692# endif /* VBOX_STRICT */
693# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
694 }
695 STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
696# endif /* PGM_OUT_OF_SYNC_IN_GC */
697 }
698 else
699 {
700 /*
701 * Page not present in Guest OS or invalid page table address.
702 * This is potential virtual page access handler food.
703 *
704 * For the present we'll say that our access handlers don't
705 * work for this case - we've already discarded the page table
706 * not present case which is identical to this.
707 *
708 * When we perchance find we need this, we will probably have AVL
709 * trees (offset based) to operate on and we can measure their speed
710 * agains mapping a page table and probably rearrange this handling
711 * a bit. (Like, searching virtual ranges before checking the
712 * physical address.)
713 */
714 }
715 }
716
717
718# if PGM_WITH_PAGING(PGM_GST_TYPE)
719 /*
720 * Conclusion, this is a guest trap.
721 */
722 LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
723 STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
724 return VINF_EM_RAW_GUEST_TRAP;
725# else
726 /* present, but not a monitored page; perhaps the guest is probing physical memory */
727 return VINF_EM_RAW_EMULATE_INSTR;
728# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
729
730
731#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
732
733 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
734 return VERR_INTERNAL_ERROR;
735#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
736}
737
738
739/**
740 * Emulation of the invlpg instruction.
741 *
742 *
743 * @returns VBox status code.
744 *
745 * @param pVM VM handle.
746 * @param GCPtrPage Page to invalidate.
747 *
748 * @remark ASSUMES that the guest is updating before invalidating. This order
749 * isn't required by the CPU, so this is speculative and could cause
750 * trouble.
751 *
752 * @todo Flush page or page directory only if necessary!
753 * @todo Add a #define for simply invalidating the page.
754 */
755PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
756{
757#if PGM_GST_TYPE == PGM_TYPE_32BIT \
758 || PGM_GST_TYPE == PGM_TYPE_PAE
759
760 LogFlow(("InvalidatePage %x\n", GCPtrPage));
761# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
762 /*
763 * Get the shadow PD entry and skip out if this PD isn't present.
764 * (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
765 */
766 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
767# if PGM_SHW_TYPE == PGM_TYPE_32BIT
768 PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
769# else
770 PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
771# endif
772 const SHWPDE PdeDst = *pPdeDst;
773 if (!PdeDst.n.u1Present)
774 {
775 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
776 return VINF_SUCCESS;
777 }
778
779 /*
780 * Get the guest PD entry and calc big page.
781 */
782# if PGM_GST_TYPE == PGM_TYPE_32BIT
783 PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
784 const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
785 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
786# else /* PAE */
787 unsigned iPDSrc;
788 PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
789 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
790# endif
791
792 const uint32_t cr4 = CPUMGetGuestCR4(pVM);
793 const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
794
795# ifdef IN_RING3
796 /*
797 * If a CR3 Sync is pending we may ignore the invalidate page operation
798 * depending on the kind of sync and if it's a global page or not.
799 * This doesn't make sense in GC/R0 so we'll skip it entirely there.
800 */
801# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
802 if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
803 || ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
804 && fIsBigPage
805 && PdeSrc.b.u1Global
806 && (cr4 & X86_CR4_PGE)
807 )
808 )
809# else
810 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 | VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
811# endif
812 {
813 STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
814 return VINF_SUCCESS;
815 }
816# endif /* IN_RING3 */
817
818
819 /*
820 * Deal with the Guest PDE.
821 */
822 int rc = VINF_SUCCESS;
823 if (PdeSrc.n.u1Present)
824 {
825 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
826 {
827 /*
828 * Conflict - Let SyncPT deal with it to avoid duplicate code.
829 */
830 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
831 Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
832 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
833 }
834 else if ( PdeSrc.n.u1User != PdeDst.n.u1User
835 || (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
836 {
837 /*
838 * Mark not present so we can resync the PDE when it's used.
839 */
840 LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
841 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
842 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
843 pPdeDst->u = 0;
844 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
845 PGM_INVL_GUEST_TLBS();
846 }
847# ifdef PGM_SYNC_ACCESSED_BIT
848 else if (!PdeSrc.n.u1Accessed)
849 {
850 /*
851 * Mark not present so we can set the accessed bit.
852 */
853 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
854 pPdeDst->u = 0;
855 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
856 PGM_INVL_GUEST_TLBS();
857 }
858# endif
859 else if (!fIsBigPage)
860 {
861 /*
862 * 4KB - page.
863 */
864 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
865 RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
866# if PGM_SHW_TYPE != PGM_TYPE_32BIT
867 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
868# endif
869 if (pShwPage->GCPhys == GCPhys)
870 {
871#if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
872 const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
873 PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
874 if (pPT->a[iPTEDst].n.u1Present)
875 {
876# ifdef PGMPOOL_WITH_USER_TRACKING
877 /* This is very unlikely with caching/monitoring enabled. */
878 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
879# endif
880 pPT->a[iPTEDst].u = 0;
881 }
882#else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
883 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
884 if (VBOX_SUCCESS(rc))
885 rc = VINF_SUCCESS;
886#endif
887 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
888 PGM_INVL_PG(GCPtrPage);
889 }
890 else
891 {
892 /*
893 * The page table address changed.
894 */
895 LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
896 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
897 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
898 pPdeDst->u = 0;
899 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
900 PGM_INVL_GUEST_TLBS();
901 }
902 }
903 else
904 {
905 /*
906 * 4MB - page.
907 */
908 /* Before freeing the page, check if anything really changed. */
909 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
910 RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
911# if PGM_SHW_TYPE != PGM_TYPE_32BIT \
912 && PGM_GST_TYPE == PGM_TYPE_32BIT
913 /* Select the right PDE as we're emulating a 4MB page with two 2 MB shadow PDEs */
914 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
915# endif
916 if ( pShwPage->GCPhys == GCPhys
917 && pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
918 {
919 /* ASSUMES a the given bits are identical for 4M and normal PDEs */
920 /** @todo PAT */
921# ifdef PGM_SYNC_DIRTY_BIT
922 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
923 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
924 && ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
925 || (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
926# else
927 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD))
928 == (PdeDst.u & (X86_PDE_P | X86_PDE_RW | X86_PDE_US | X86_PDE_PWT | X86_PDE_PCD)))
929# endif
930 {
931 LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
932 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
933 return VINF_SUCCESS;
934 }
935 }
936
937 /*
938 * Ok, the page table is present and it's been changed in the guest.
939 * If we're in host context, we'll just mark it as not present taking the lazy approach.
940 * We could do this for some flushes in GC too, but we need an algorithm for
941 * deciding which 4MB pages containing code likely to be executed very soon.
942 */
943 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
944 pPdeDst->u = 0;
945 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
946 PGM_INVL_BIG_PG(GCPtrPage);
947 }
948 }
949 else
950 {
951 /*
952 * Page directory is not present, mark shadow PDE not present.
953 */
954 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
955 {
956 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
957 pPdeDst->u = 0;
958 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
959 PGM_INVL_PG(GCPtrPage);
960 }
961 else
962 {
963 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
964 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
965 }
966 }
967
968 return rc;
969
970# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
971# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
972# endif
973 return VINF_SUCCESS;
974
975#elif PGM_GST_TYPE == PGM_TYPE_AMD64
976# if PGM_SHW_TYPE == PGM_TYPE_AMD64
977//# error not implemented
978 return VERR_INTERNAL_ERROR;
979
980# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
981# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
982# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
983
984#else /* guest real and protected mode */
985 /* There's no such thing when paging is disabled. */
986 return VINF_SUCCESS;
987#endif
988}
989
990
991#ifdef PGMPOOL_WITH_USER_TRACKING
992/**
993 * Update the tracking of shadowed pages.
994 *
995 * @param pVM The VM handle.
996 * @param pShwPage The shadow page.
997 * @param HCPhys The physical page we is being dereferenced.
998 */
999DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1000{
1001# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1002 STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1003 LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1004
1005 /** @todo If this turns out to be a bottle neck (*very* likely) two things can be done:
1006 * 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1007 * 2. write protect all shadowed pages. I.e. implement caching.
1008 */
1009 /*
1010 * Find the guest address.
1011 */
1012 for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1013 pRam;
1014 pRam = CTXALLSUFF(pRam->pNext))
1015 {
1016 unsigned iPage = pRam->cb >> PAGE_SHIFT;
1017 while (iPage-- > 0)
1018 {
1019 if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1020 {
1021 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1022 pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1023 pShwPage->cPresent--;
1024 pPool->cPresent--;
1025 STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1026 return;
1027 }
1028 }
1029 }
1030
1031 for (;;)
1032 AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1033# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1034 pShwPage->cPresent--;
1035 pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1036# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1037}
1038
1039
1040/**
1041 * Update the tracking of shadowed pages.
1042 *
1043 * @param pVM The VM handle.
1044 * @param pShwPage The shadow page.
1045 * @param u16 The top 16-bit of the pPage->HCPhys.
1046 * @param pPage Pointer to the guest page. this will be modified.
1047 * @param iPTDst The index into the shadow table.
1048 */
1049DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1050{
1051# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1052 /*
1053 * We're making certain assumptions about the placement of cRef and idx.
1054 */
1055 Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1056 Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1057
1058 /*
1059 * Just deal with the simple first time here.
1060 */
1061 if (!u16)
1062 {
1063 STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1064 u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) | pShwPage->idx;
1065 }
1066 else
1067 u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1068
1069 /* write back, trying to be clever... */
1070 Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1071 u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) | ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1072 *((uint16_t *)&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1073# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1074
1075 /* update statistics. */
1076 pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1077 pShwPage->cPresent++;
1078 if (pShwPage->iFirstPresent > iPTDst)
1079 pShwPage->iFirstPresent = iPTDst;
1080}
1081#endif /* PGMPOOL_WITH_USER_TRACKING */
1082
1083
1084/**
1085 * Creates a 4K shadow page for a guest page.
1086 *
1087 * For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1088 * physical address. The PdeSrc argument only the flags are used. No page structured
1089 * will be mapped in this function.
1090 *
1091 * @param pVM VM handle.
1092 * @param pPteDst Destination page table entry.
1093 * @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1094 * Can safely assume that only the flags are being used.
1095 * @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1096 * @param pShwPage Pointer to the shadow page.
1097 * @param iPTDst The index into the shadow table.
1098 *
1099 * @remark Not used for 2/4MB pages!
1100 */
1101DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1102{
1103 if (PteSrc.n.u1Present)
1104 {
1105 /*
1106 * Find the ram range.
1107 */
1108 PPGMPAGE pPage;
1109 int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1110 if (VBOX_SUCCESS(rc))
1111 {
1112 /** @todo investiage PWT, PCD and PAT. */
1113 /*
1114 * Make page table entry.
1115 */
1116 const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1117 SHWPTE PteDst;
1118 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1119 {
1120 /** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1121 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1122 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1123 | (HCPhys & X86_PTE_PAE_PG_MASK);
1124 else
1125 {
1126 LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1127 PteDst.u = 0;
1128 }
1129 /** @todo count these two kinds. */
1130 }
1131 else
1132 {
1133#ifdef PGM_SYNC_DIRTY_BIT
1134# ifdef PGM_SYNC_ACCESSED_BIT
1135 /*
1136 * If the page or page directory entry is not marked accessed,
1137 * we mark the page not present.
1138 */
1139 if (!PteSrc.n.u1Accessed || !PdeSrc.n.u1Accessed)
1140 {
1141 LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1142 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1143 PteDst.u = 0;
1144 }
1145 else
1146# endif
1147 /*
1148 * If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1149 * when the page is modified.
1150 */
1151 if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1152 {
1153 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1154 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT | X86_PTE_RW))
1155 | (HCPhys & X86_PTE_PAE_PG_MASK)
1156 | PGM_PTFLAGS_TRACK_DIRTY;
1157 }
1158 else
1159 {
1160 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1161 PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1162 | (HCPhys & X86_PTE_PAE_PG_MASK);
1163 }
1164#endif
1165 }
1166
1167#ifdef PGMPOOL_WITH_USER_TRACKING
1168 /*
1169 * Keep user track up to date.
1170 */
1171 if (PteDst.n.u1Present)
1172 {
1173 if (!pPteDst->n.u1Present)
1174 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1175 else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1176 {
1177 Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1178 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1179 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1180 }
1181 }
1182 else if (pPteDst->n.u1Present)
1183 {
1184 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1185 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1186 }
1187#endif /* PGMPOOL_WITH_USER_TRACKING */
1188
1189 /*
1190 * Update statistics and commit the entry.
1191 */
1192 if (!PteSrc.n.u1Global)
1193 pShwPage->fSeenNonGlobal = true;
1194 *pPteDst = PteDst;
1195 }
1196 /* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1197 /** @todo count these. */
1198 }
1199 else
1200 {
1201 /*
1202 * Page not-present.
1203 */
1204 LogFlow(("SyncPageWorker: page not present in Pte\n"));
1205#ifdef PGMPOOL_WITH_USER_TRACKING
1206 /* Keep user track up to date. */
1207 if (pPteDst->n.u1Present)
1208 {
1209 Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1210 PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1211 }
1212#endif /* PGMPOOL_WITH_USER_TRACKING */
1213 pPteDst->u = 0;
1214 /** @todo count these. */
1215 }
1216}
1217
1218
1219/**
1220 * Syncs a guest OS page.
1221 *
1222 * There are no conflicts at this point, neither is there any need for
1223 * page table allocations.
1224 *
1225 * @returns VBox status code.
1226 * @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1227 * @param pVM VM handle.
1228 * @param PdeSrc Page directory entry of the guest.
1229 * @param GCPtrPage Guest context page address.
1230 * @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1231 * @param uErr Fault error (X86_TRAP_PF_*).
1232 */
1233PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1234{
1235 LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1236
1237#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1238 || PGM_GST_TYPE == PGM_TYPE_PAE
1239
1240# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1241# error "Invalid shadow mode for 32-bit guest mode!"
1242# endif
1243
1244 /*
1245 * Assert preconditions.
1246 */
1247 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1248 Assert(PdeSrc.n.u1Present);
1249 Assert(cPages);
1250
1251 /*
1252 * Get the shadow PDE, find the shadow page table in the pool.
1253 */
1254 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1255# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1256 X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1257# else /* PAE */
1258 X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1259# endif
1260 Assert(PdeDst.n.u1Present);
1261 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1262
1263 /*
1264 * Check that the page is present and that the shadow PDE isn't out of sync.
1265 */
1266 const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1267 RTGCPHYS GCPhys;
1268 if (!fBigPage)
1269 {
1270 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1271# if PGM_SHW_TYPE != PGM_TYPE_32BIT
1272 GCPhys |= (iPDDst & 1) * (PAGE_SIZE/2);
1273# endif
1274 }
1275 else
1276 {
1277 GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1278# if PGM_SHW_TYPE != PGM_TYPE_32BIT \
1279 && PGM_GST_TYPE == PGM_TYPE_32BIT
1280 /* Select the right PDE as we're emulating a 4MB page with two 2 MB shadow PDEs */
1281 GCPhys |= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1282# endif
1283 }
1284 if ( pShwPage->GCPhys == GCPhys
1285 && PdeSrc.n.u1Present
1286 && (PdeSrc.n.u1User == PdeDst.n.u1User)
1287 && (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
1288# if PGM_GST_TYPE == PGM_TYPE_PAE
1289 && (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1290# endif
1291 )
1292 {
1293# ifdef PGM_SYNC_ACCESSED_BIT
1294 /*
1295 * Check that the PDE is marked accessed already.
1296 * Since we set the accessed bit *before* getting here on a #PF, this
1297 * check is only meant for dealing with non-#PF'ing paths.
1298 */
1299 if (PdeSrc.n.u1Accessed)
1300# endif
1301 {
1302 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1303 if (!fBigPage)
1304 {
1305 /*
1306 * 4KB Page - Map the guest page table.
1307 */
1308 PGSTPT pPTSrc;
1309 int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1310 if (VBOX_SUCCESS(rc))
1311 {
1312# ifdef PGM_SYNC_N_PAGES
1313 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1314 if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1315 {
1316 /*
1317 * This code path is currently only taken when the caller is PGMTrap0eHandler
1318 * for non-present pages!
1319 *
1320 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1321 * deal with locality.
1322 */
1323 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1324# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1325 const unsigned offPTSrc = 0;
1326# else
1327 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1328# endif
1329 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1330 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1331 iPTDst = 0;
1332 else
1333 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1334 for (; iPTDst < iPTDstEnd; iPTDst++)
1335 {
1336 if (!pPTDst->a[iPTDst].n.u1Present)
1337 {
1338 GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1339 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1340 NOREF(GCPtrCurPage);
1341#ifndef IN_RING0
1342 /*
1343 * Assuming kernel code will be marked as supervisor - and not as user level
1344 * and executed using a conforming code selector - And marked as readonly.
1345 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
1346 */
1347 PPGMPAGE pPage;
1348 if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW | X86_PTE_US))
1349 || iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1350 || !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1351 || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1352 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1353 )
1354#endif /* else: CSAM not active */
1355 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1356 Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1357 GCPtrCurPage, PteSrc.n.u1Present,
1358 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1359 PteSrc.n.u1User & PdeSrc.n.u1User,
1360 (uint64_t)PteSrc.u,
1361 (uint64_t)pPTDst->a[iPTDst].u,
1362 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1363 }
1364 }
1365 }
1366 else
1367# endif /* PGM_SYNC_N_PAGES */
1368 {
1369 const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1370 GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1371 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1372 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1373 Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1374 GCPtrPage, PteSrc.n.u1Present,
1375 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1376 PteSrc.n.u1User & PdeSrc.n.u1User,
1377 (uint64_t)PteSrc.u,
1378 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1379 }
1380 }
1381 else /* MMIO or invalid page: emulated in #PF handler. */
1382 {
1383 LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1384 Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1385 }
1386 }
1387 else
1388 {
1389 /*
1390 * 4/2MB page - lazy syncing shadow 4K pages.
1391 * (There are many causes of getting here, it's no longer only CSAM.)
1392 */
1393 /* Calculate the GC physical address of this 4KB shadow page. */
1394 RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1395 /* Find ram range. */
1396 PPGMPAGE pPage;
1397 int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1398 if (VBOX_SUCCESS(rc))
1399 {
1400 /*
1401 * Make shadow PTE entry.
1402 */
1403 const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1404 SHWPTE PteDst;
1405 PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT))
1406 | (HCPhys & X86_PTE_PAE_PG_MASK);
1407 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1408 {
1409 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1410 PteDst.n.u1Write = 0;
1411 else
1412 PteDst.u = 0;
1413 }
1414 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1415# ifdef PGMPOOL_WITH_USER_TRACKING
1416 if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1417 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1418# endif
1419 pPTDst->a[iPTDst] = PteDst;
1420
1421
1422# ifdef PGM_SYNC_DIRTY_BIT
1423 /*
1424 * If the page is not flagged as dirty and is writable, then make it read-only
1425 * at PD level, so we can set the dirty bit when the page is modified.
1426 *
1427 * ASSUMES that page access handlers are implemented on page table entry level.
1428 * Thus we will first catch the dirty access and set PDE.D and restart. If
1429 * there is an access handler, we'll trap again and let it work on the problem.
1430 */
1431 /** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1432 * As for invlpg, it simply frees the whole shadow PT.
1433 * ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1434 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1435 {
1436 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1437 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1438 PdeDst.n.u1Write = 0;
1439 }
1440 else
1441 {
1442 PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1443 PdeDst.n.u1Write = PdeSrc.n.u1Write;
1444 }
1445# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1446 pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1447# else /* PAE */
1448 pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1449# endif
1450# endif /* PGM_SYNC_DIRTY_BIT */
1451 Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1452 GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1453 PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1454 }
1455 else
1456 LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1457 }
1458 return VINF_SUCCESS;
1459 }
1460# ifdef PGM_SYNC_ACCESSED_BIT
1461 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1462#endif
1463 }
1464 else
1465 {
1466 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1467 Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1468 GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1469 }
1470
1471 /*
1472 * Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1473 * Yea, I'm lazy.
1474 */
1475 pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1476# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1477 pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1478# else /* PAE */
1479 pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1480# endif
1481 PGM_INVL_GUEST_TLBS();
1482 return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1483
1484#elif PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT
1485
1486# ifdef PGM_SYNC_N_PAGES
1487 /*
1488 * Get the shadow PDE, find the shadow page table in the pool.
1489 */
1490 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1491# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1492 X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1493# else /* PAE */
1494 X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1495# endif
1496 Assert(PdeDst.n.u1Present);
1497 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1498 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1499
1500# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1501 const unsigned offPTSrc = 0;
1502# else
1503 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1504# endif
1505
1506 Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
1507 if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1508 {
1509 /*
1510 * This code path is currently only taken when the caller is PGMTrap0eHandler
1511 * for non-present pages!
1512 *
1513 * We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1514 * deal with locality.
1515 */
1516 unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1517 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1518 if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1519 iPTDst = 0;
1520 else
1521 iPTDst -= PGM_SYNC_NR_PAGES / 2;
1522 for (; iPTDst < iPTDstEnd; iPTDst++)
1523 {
1524 if (!pPTDst->a[iPTDst].n.u1Present)
1525 {
1526 GSTPTE PteSrc;
1527
1528 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1529
1530 /* Fake the page table entry */
1531 PteSrc.u = GCPtrCurPage;
1532 PteSrc.n.u1Present = 1;
1533 PteSrc.n.u1Dirty = 1;
1534 PteSrc.n.u1Accessed = 1;
1535 PteSrc.n.u1Write = 1;
1536 PteSrc.n.u1User = 1;
1537
1538 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1539
1540 Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1541 GCPtrCurPage, PteSrc.n.u1Present,
1542 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1543 PteSrc.n.u1User & PdeSrc.n.u1User,
1544 (uint64_t)PteSrc.u,
1545 (uint64_t)pPTDst->a[iPTDst].u,
1546 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1547 }
1548 }
1549 }
1550 else
1551# endif /* PGM_SYNC_N_PAGES */
1552 {
1553 GSTPTE PteSrc;
1554 const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1555 RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
1556
1557 /* Fake the page table entry */
1558 PteSrc.u = GCPtrCurPage;
1559 PteSrc.n.u1Present = 1;
1560 PteSrc.n.u1Dirty = 1;
1561 PteSrc.n.u1Accessed = 1;
1562 PteSrc.n.u1Write = 1;
1563 PteSrc.n.u1User = 1;
1564 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1565
1566 Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1567 GCPtrPage, PteSrc.n.u1Present,
1568 PteSrc.n.u1Write & PdeSrc.n.u1Write,
1569 PteSrc.n.u1User & PdeSrc.n.u1User,
1570 (uint64_t)PteSrc.u,
1571 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1572 }
1573 return VINF_SUCCESS;
1574
1575#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1576 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1577 return VERR_INTERNAL_ERROR;
1578#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
1579}
1580
1581
1582
1583#if PGM_WITH_PAGING(PGM_GST_TYPE)
1584
1585# ifdef PGM_SYNC_DIRTY_BIT
1586
1587/**
1588 * Investigate page fault and handle write protection page faults caused by
1589 * dirty bit tracking.
1590 *
1591 * @returns VBox status code.
1592 * @param pVM VM handle.
1593 * @param uErr Page fault error code.
1594 * @param pPdeDst Shadow page directory entry.
1595 * @param pPdeSrc Guest page directory entry.
1596 * @param GCPtrPage Guest context page address.
1597 */
1598PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1599{
1600 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1601 LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1602
1603 /*
1604 * Real page fault?
1605 */
1606 if ( (uErr & X86_TRAP_PF_RSVD)
1607 || !pPdeSrc->n.u1Present
1608# if PGM_WITH_NX(PGM_GST_TYPE)
1609 || ((uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1610# endif
1611 || ((uErr & X86_TRAP_PF_RW) && !pPdeSrc->n.u1Write)
1612 || ((uErr & X86_TRAP_PF_US) && !pPdeSrc->n.u1User) )
1613 {
1614# ifdef IN_GC
1615 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1616# endif
1617 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1618 LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1619
1620 if (pPdeSrc->n.u1Present)
1621 {
1622 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1623 * See the 2nd case below as well.
1624 */
1625 if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1626 {
1627 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1628 }
1629 else
1630 {
1631 /*
1632 * Map the guest page table.
1633 */
1634 PGSTPT pPTSrc;
1635 int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1636 if (VBOX_SUCCESS(rc))
1637 {
1638 PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1639 const GSTPTE PteSrc = *pPteSrc;
1640 if (pPteSrc->n.u1Present)
1641 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1642 }
1643 AssertRC(rc);
1644 }
1645 }
1646 return VINF_EM_RAW_GUEST_TRAP;
1647 }
1648
1649 /*
1650 * First check the easy case where the page directory has been marked read-only to track
1651 * the dirty bit of an emulated BIG page
1652 */
1653 if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1654 {
1655 /* Mark guest page directory as accessed */
1656 pPdeSrc->b.u1Accessed = 1;
1657
1658 /*
1659 * Only write protection page faults are relevant here.
1660 */
1661 if (uErr & X86_TRAP_PF_RW)
1662 {
1663 /* Mark guest page directory as dirty (BIG page only). */
1664 pPdeSrc->b.u1Dirty = 1;
1665
1666 if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1667 {
1668 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1669
1670 Assert(pPdeSrc->b.u1Write);
1671
1672 pPdeDst->n.u1Write = 1;
1673 pPdeDst->n.u1Accessed = 1;
1674 pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1675 PGM_INVL_BIG_PG(GCPtrPage);
1676 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1677 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1678 }
1679 }
1680 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1681 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1682 }
1683 /* else: 4KB page table */
1684
1685 /*
1686 * Map the guest page table.
1687 */
1688 PGSTPT pPTSrc;
1689 int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1690 if (VBOX_SUCCESS(rc))
1691 {
1692 /*
1693 * Real page fault?
1694 */
1695 PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1696 const GSTPTE PteSrc = *pPteSrc;
1697 if ( !PteSrc.n.u1Present
1698# if PGM_WITH_NX(PGM_GST_TYPE)
1699 || ((uErr & X86_TRAP_PF_ID) && !PteSrc.n.u1NoExecute)
1700# endif
1701 || ((uErr & X86_TRAP_PF_RW) && !PteSrc.n.u1Write)
1702 || ((uErr & X86_TRAP_PF_US) && !PteSrc.n.u1User)
1703 )
1704 {
1705# ifdef IN_GC
1706 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1707# endif
1708 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1709 LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1710
1711 /* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1712 * See the 2nd case above as well.
1713 */
1714 if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1715 TRPMSetErrorCode(pVM, uErr | X86_TRAP_PF_P); /* page-level protection violation */
1716
1717 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1718 return VINF_EM_RAW_GUEST_TRAP;
1719 }
1720 LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1721
1722 /*
1723 * Set the accessed bits in the page directory and the page table.
1724 */
1725 pPdeSrc->n.u1Accessed = 1;
1726 pPteSrc->n.u1Accessed = 1;
1727
1728 /*
1729 * Only write protection page faults are relevant here.
1730 */
1731 if (uErr & X86_TRAP_PF_RW)
1732 {
1733 /* Write access, so mark guest entry as dirty. */
1734# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1735 if (!pPteSrc->n.u1Dirty)
1736 STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1737 else
1738 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1739# endif
1740 pPteSrc->n.u1Dirty = 1;
1741
1742 if (pPdeDst->n.u1Present)
1743 {
1744 /* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1745 * Our individual shadow handlers will provide more information and force a fatal exit.
1746 */
1747 if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1748 {
1749 LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1750 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1751 return VINF_SUCCESS;
1752 }
1753
1754 /*
1755 * Map shadow page table.
1756 */
1757 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1758 if (pShwPage)
1759 {
1760 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1761 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1762 if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1763 && (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1764 {
1765 LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1766# ifdef VBOX_STRICT
1767 PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1768 if (pPage)
1769 AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1770 ("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1771# endif
1772 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1773
1774 Assert(pPteSrc->n.u1Write);
1775
1776 pPteDst->n.u1Write = 1;
1777 pPteDst->n.u1Dirty = 1;
1778 pPteDst->n.u1Accessed = 1;
1779 pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1780 PGM_INVL_PG(GCPtrPage);
1781
1782 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1783 return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1784 }
1785 }
1786 else
1787 AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1788 }
1789 }
1790/** @todo Optimize accessed bit emulation? */
1791# ifdef VBOX_STRICT
1792 /*
1793 * Sanity check.
1794 */
1795 else if ( !pPteSrc->n.u1Dirty
1796 && (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1797 && pPdeDst->n.u1Present)
1798 {
1799 PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1800 PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1801 PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1802 if ( pPteDst->n.u1Present
1803 && pPteDst->n.u1Write)
1804 LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1805 }
1806# endif /* VBOX_STRICT */
1807 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1808 return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1809 }
1810 AssertRC(rc);
1811 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1812 return rc;
1813}
1814
1815# endif
1816
1817#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1818
1819
1820/**
1821 * Sync a shadow page table.
1822 *
1823 * The shadow page table is not present. This includes the case where
1824 * there is a conflict with a mapping.
1825 *
1826 * @returns VBox status code.
1827 * @param pVM VM handle.
1828 * @param iPD Page directory index.
1829 * @param pPDSrc Source page directory (i.e. Guest OS page directory).
1830 * Assume this is a temporary mapping.
1831 * @param GCPtrPage GC Pointer of the page that caused the fault
1832 */
1833PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1834{
1835 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1836 STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1837 LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1838
1839#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1840 || PGM_GST_TYPE == PGM_TYPE_PAE
1841
1842# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
1843# error "Invalid shadow mode for 32-bit guest mode!"
1844# endif
1845
1846 /*
1847 * Validate input a little bit.
1848 */
1849 Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1850# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1851 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1852# else
1853 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1854# endif
1855 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1856 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1857 SHWPDE PdeDst = *pPdeDst;
1858
1859# if PGM_GST_TYPE == PGM_TYPE_32BIT
1860 /*
1861 * Check for conflicts.
1862 * GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1863 * HC: Simply resolve the conflict.
1864 */
1865 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1866 {
1867 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1868# ifndef IN_RING3
1869 Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1870 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1871 return VERR_ADDRESS_CONFLICT;
1872# else
1873 PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1874 Assert(pMapping);
1875 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1876 if (VBOX_FAILURE(rc))
1877 {
1878 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1879 return rc;
1880 }
1881 PdeDst = *pPdeDst;
1882# endif
1883 }
1884# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1885 /* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1886 Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1887# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1888 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1889
1890 /*
1891 * Sync page directory entry.
1892 */
1893 int rc = VINF_SUCCESS;
1894 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1895 if (PdeSrc.n.u1Present)
1896 {
1897 /*
1898 * Allocate & map the page table.
1899 */
1900 PSHWPT pPTDst;
1901 const bool fPageTable = !PdeSrc.b.u1Size || !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1902 PPGMPOOLPAGE pShwPage;
1903 RTGCPHYS GCPhys;
1904 if (fPageTable)
1905 {
1906 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1907# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1908 GCPhys |= (iPDDst & 1) * (PAGE_SIZE / 2);
1909# endif
1910 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1911 }
1912 else
1913 {
1914 GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1915# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1916 GCPhys |= GCPtrPage & RT_BIT(X86_PAGE_2M_SHIFT);
1917# endif
1918 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1919 }
1920 if (rc == VINF_SUCCESS)
1921 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1922 else if (rc == VINF_PGM_CACHED_PAGE)
1923 {
1924 /*
1925 * The PT was cached, just hook it up.
1926 */
1927 if (fPageTable)
1928 PdeDst.u = pShwPage->Core.Key
1929 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1930 else
1931 {
1932 PdeDst.u = pShwPage->Core.Key
1933 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1934# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumtions further down.) */
1935 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1936 {
1937 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1938 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
1939 PdeDst.b.u1Write = 0;
1940 }
1941# endif
1942 }
1943 *pPdeDst = PdeDst;
1944 return VINF_SUCCESS;
1945 }
1946 else if (rc == VERR_PGM_POOL_FLUSHED)
1947 return VINF_PGM_SYNC_CR3;
1948 else
1949 AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1950 PdeDst.u &= X86_PDE_AVL_MASK;
1951 PdeDst.u |= pShwPage->Core.Key;
1952
1953# ifdef PGM_SYNC_DIRTY_BIT
1954 /*
1955 * Page directory has been accessed (this is a fault situation, remember).
1956 */
1957 pPDSrc->a[iPDSrc].n.u1Accessed = 1;
1958# endif
1959 if (fPageTable)
1960 {
1961 /*
1962 * Page table - 4KB.
1963 *
1964 * Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
1965 */
1966 Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
1967 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
1968 PGSTPT pPTSrc;
1969 rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1970 if (VBOX_SUCCESS(rc))
1971 {
1972 /*
1973 * Start by syncing the page directory entry so CSAM's TLB trick works.
1974 */
1975 PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK))
1976 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
1977 *pPdeDst = PdeDst;
1978
1979 /*
1980 * Directory/page user or supervisor privilege: (same goes for read/write)
1981 *
1982 * Directory Page Combined
1983 * U/S U/S U/S
1984 * 0 0 0
1985 * 0 1 0
1986 * 1 0 0
1987 * 1 1 1
1988 *
1989 * Simple AND operation. Table listed for completeness.
1990 *
1991 */
1992 STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
1993# ifdef PGM_SYNC_N_PAGES
1994 unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1995 unsigned iPTDst = iPTBase;
1996 const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1997 if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
1998 iPTDst = 0;
1999 else
2000 iPTDst -= PGM_SYNC_NR_PAGES / 2;
2001# else /* !PGM_SYNC_N_PAGES */
2002 unsigned iPTDst = 0;
2003 const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2004# endif /* !PGM_SYNC_N_PAGES */
2005# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2006 const unsigned offPTSrc = 0;
2007# else
2008 const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2009# endif
2010 for (; iPTDst < iPTDstEnd; iPTDst++)
2011 {
2012 const unsigned iPTSrc = iPTDst + offPTSrc;
2013 const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2014
2015 if (PteSrc.n.u1Present) /* we've already cleared it above */
2016 {
2017#ifndef IN_RING0
2018 /*
2019 * Assuming kernel code will be marked as supervisor - and not as user level
2020 * and executed using a conforming code selector - And marked as readonly.
2021 * Also assume that if we're monitoring a page, it's of no interest to CSAM.
2022 */
2023 PPGMPAGE pPage;
2024 if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW | X86_PTE_US))
2025 || !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)))
2026 || ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2027 && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2028 )
2029#endif
2030 PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2031 Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2032 (RTGCPTR)((iPDSrc << GST_PD_SHIFT) | (iPTSrc << PAGE_SHIFT)),
2033 PteSrc.n.u1Present,
2034 PteSrc.n.u1Write & PdeSrc.n.u1Write,
2035 PteSrc.n.u1User & PdeSrc.n.u1User,
2036 (uint64_t)PteSrc.u,
2037 pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2038 (PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2039 }
2040 } /* for PTEs */
2041 }
2042 }
2043 else
2044 {
2045 /*
2046 * Big page - 2/4MB.
2047 *
2048 * We'll walk the ram range list in parallel and optimize lookups.
2049 * We will only sync on shadow page table at a time.
2050 */
2051 STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2052
2053 /**
2054 * @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2055 */
2056
2057 /*
2058 * Start by syncing the page directory entry.
2059 */
2060 PdeDst.u = (PdeDst.u & (X86_PDE_PAE_PG_MASK | (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2061 | (PdeSrc.u & ~(X86_PDE_PAE_PG_MASK | X86_PDE_AVL_MASK | X86_PDE_PCD | X86_PDE_PWT | X86_PDE_PS | X86_PDE4M_G | X86_PDE4M_D));
2062
2063# ifdef PGM_SYNC_DIRTY_BIT
2064 /*
2065 * If the page is not flagged as dirty and is writable, then make it read-only
2066 * at PD level, so we can set the dirty bit when the page is modified.
2067 *
2068 * ASSUMES that page access handlers are implemented on page table entry level.
2069 * Thus we will first catch the dirty access and set PDE.D and restart. If
2070 * there is an access handler, we'll trap again and let it work on the problem.
2071 */
2072 /** @todo move the above stuff to a section in the PGM documentation. */
2073 Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2074 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2075 {
2076 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2077 PdeDst.u |= PGM_PDFLAGS_TRACK_DIRTY;
2078 PdeDst.b.u1Write = 0;
2079 }
2080# endif /* PGM_SYNC_DIRTY_BIT */
2081 *pPdeDst = PdeDst;
2082
2083 /*
2084 * Fill the shadow page table.
2085 */
2086 /* Get address and flags from the source PDE. */
2087 SHWPTE PteDstBase;
2088 PteDstBase.u = PdeSrc.u & ~(X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT);
2089
2090 /* Loop thru the entries in the shadow PT. */
2091 const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2092 Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2093 GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2094 GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2095 PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2096 unsigned iPTDst = 0;
2097 while (iPTDst < ELEMENTS(pPTDst->a))
2098 {
2099 /* Advance ram range list. */
2100 while (pRam && GCPhys > pRam->GCPhysLast)
2101 pRam = CTXALLSUFF(pRam->pNext);
2102 if (pRam && GCPhys >= pRam->GCPhys)
2103 {
2104 unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2105 do
2106 {
2107 /* Make shadow PTE. */
2108 PPGMPAGE pPage = &pRam->aPages[iHCPage];
2109 SHWPTE PteDst;
2110
2111 /* Make sure the RAM has already been allocated. */
2112 if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2113 {
2114 if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2115 {
2116# ifdef IN_RING3
2117 int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2118# else
2119 int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2120# endif
2121 if (rc != VINF_SUCCESS)
2122 return rc;
2123 }
2124 }
2125
2126 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2127 {
2128 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2129 {
2130 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
2131 PteDst.n.u1Write = 0;
2132 }
2133 else
2134 PteDst.u = 0;
2135 }
2136# ifndef IN_RING0
2137 /*
2138 * Assuming kernel code will be marked as supervisor and not as user level and executed
2139 * using a conforming code selector. Don't check for readonly, as that implies the whole
2140 * 4MB can be code or readonly data. Linux enables write access for its large pages.
2141 */
2142 else if ( !PdeSrc.n.u1User
2143 && CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT))))
2144 PteDst.u = 0;
2145# endif
2146 else
2147 PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) | PteDstBase.u;
2148# ifdef PGMPOOL_WITH_USER_TRACKING
2149 if (PteDst.n.u1Present)
2150 PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2151# endif
2152 /* commit it */
2153 pPTDst->a[iPTDst] = PteDst;
2154 Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2155 (RTGCPTR)(GCPtr | (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2156 PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2157
2158 /* advance */
2159 GCPhys += PAGE_SIZE;
2160 iHCPage++;
2161 iPTDst++;
2162 } while ( iPTDst < ELEMENTS(pPTDst->a)
2163 && GCPhys <= pRam->GCPhysLast);
2164 }
2165 else if (pRam)
2166 {
2167 Log(("Invalid pages at %VGp\n", GCPhys));
2168 do
2169 {
2170 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2171 GCPhys += PAGE_SIZE;
2172 iPTDst++;
2173 } while ( iPTDst < ELEMENTS(pPTDst->a)
2174 && GCPhys < pRam->GCPhys);
2175 }
2176 else
2177 {
2178 Log(("Invalid pages at %VGp (2)\n", GCPhys));
2179 for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2180 pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2181 }
2182 } /* while more PTEs */
2183 } /* 4KB / 4MB */
2184 }
2185 else
2186 AssertRelease(!PdeDst.n.u1Present);
2187
2188 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2189# ifdef IN_GC
2190 if (VBOX_FAILURE(rc))
2191 STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2192# endif
2193 return rc;
2194
2195#elif PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT
2196
2197 int rc = VINF_SUCCESS;
2198
2199 /*
2200 * Validate input a little bit.
2201 */
2202# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2203 PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2204# else
2205 PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2206# endif
2207 const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2208 PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2209 SHWPDE PdeDst = *pPdeDst;
2210
2211 Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2212 Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2213
2214 GSTPDE PdeSrc;
2215 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2216 PdeSrc.n.u1Present = 1;
2217 PdeSrc.n.u1Write = 1;
2218 PdeSrc.n.u1Accessed = 1;
2219 PdeSrc.n.u1User = 1;
2220
2221 /*
2222 * Allocate & map the page table.
2223 */
2224 PSHWPT pPTDst;
2225 PPGMPOOLPAGE pShwPage;
2226 RTGCPHYS GCPhys;
2227
2228 /* Virtual address = physical address */
2229 GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2230 rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2231
2232 if ( rc == VINF_SUCCESS
2233 || rc == VINF_PGM_CACHED_PAGE)
2234 pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2235 else
2236 AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2237
2238 PdeDst.u &= X86_PDE_AVL_MASK;
2239 PdeDst.u |= pShwPage->Core.Key;
2240 PdeDst.n.u1Present = 1;
2241 *pPdeDst = PdeDst;
2242
2243 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2244 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2245 return rc;
2246
2247#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2248
2249 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2250 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2251 return VERR_INTERNAL_ERROR;
2252#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2253}
2254
2255
2256
2257/**
2258 * Prefetch a page/set of pages.
2259 *
2260 * Typically used to sync commonly used pages before entering raw mode
2261 * after a CR3 reload.
2262 *
2263 * @returns VBox status code.
2264 * @param pVM VM handle.
2265 * @param GCPtrPage Page to invalidate.
2266 */
2267PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2268{
2269#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2270
2271# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2272# error "Invalid shadow mode for 32-bit guest mode!"
2273# endif
2274
2275 /*
2276 * Check that all Guest levels thru the PDE are present, getting the
2277 * PD and PDE in the processes.
2278 */
2279 int rc = VINF_SUCCESS;
2280# if PGM_WITH_PAGING(PGM_GST_TYPE)
2281# if PGM_GST_TYPE == PGM_TYPE_32BIT
2282 const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2283 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2284# else /* PAE */
2285 unsigned iPDSrc
2286 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2287# endif
2288# else
2289 PGSTPD pPDSrc = NULL;
2290 const unsigned iPDSrc = 0;
2291# endif
2292
2293# if PGM_WITH_PAGING(PGM_GST_TYPE)
2294 const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2295# else
2296 GSTPDE PdeSrc;
2297 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2298 PdeSrc.n.u1Present = 1;
2299 PdeSrc.n.u1Write = 1;
2300 PdeSrc.n.u1Accessed = 1;
2301 PdeSrc.n.u1User = 1;
2302# endif
2303
2304# ifdef PGM_SYNC_ACCESSED_BIT
2305 if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2306# else
2307 if (PdeSrc.n.u1Present)
2308# endif
2309 {
2310# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2311 const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2312# else
2313 const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2314# endif
2315 if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2316 {
2317 if (!PdeDst.n.u1Present)
2318 /** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2319 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2320 else
2321 {
2322 /** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2323 * R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2324 * makes no sense to prefetch more than one page.
2325 */
2326 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2327 if (VBOX_SUCCESS(rc))
2328 rc = VINF_SUCCESS;
2329 }
2330 }
2331 }
2332 return rc;
2333
2334#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2335
2336 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2337 return VERR_INTERNAL_ERROR;
2338#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2339}
2340
2341
2342
2343
2344/**
2345 * Syncs a page during a PGMVerifyAccess() call.
2346 *
2347 * @returns VBox status code (informational included).
2348 * @param GCPtrPage The address of the page to sync.
2349 * @param fPage The effective guest page flags.
2350 * @param uErr The trap error code.
2351 */
2352PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2353{
2354 LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2355
2356#if (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT || PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2357
2358# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2359# error "Invalid shadow mode for 32-bit guest mode!"
2360# endif
2361
2362#ifndef IN_RING0
2363 if (!(fPage & X86_PTE_US))
2364 {
2365 /*
2366 * Mark this page as safe.
2367 */
2368 /** @todo not correct for pages that contain both code and data!! */
2369 Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2370 CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2371 }
2372#endif
2373 /*
2374 * Get guest PD and index.
2375 */
2376
2377# if PGM_WITH_PAGING(PGM_GST_TYPE)
2378# if PGM_GST_TYPE == PGM_TYPE_32BIT
2379 const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2380 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2381# else /* PAE */
2382 unsigned iPDSrc;
2383 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2384# endif
2385# else
2386 PGSTPD pPDSrc = NULL;
2387 const unsigned iPDSrc = 0;
2388# endif
2389 int rc = VINF_SUCCESS;
2390
2391 /*
2392 * First check if the shadow pd is present.
2393 */
2394# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2395 PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2396# else
2397 PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2398# endif
2399 if (!pPdeDst->n.u1Present)
2400 {
2401 rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2402 AssertRC(rc);
2403 if (rc != VINF_SUCCESS)
2404 return rc;
2405 }
2406
2407# if PGM_WITH_PAGING(PGM_GST_TYPE)
2408 /* Check for dirty bit fault */
2409 rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2410 if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2411 Log(("PGMVerifyAccess: success (dirty)\n"));
2412 else
2413 {
2414 GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2415#else
2416 {
2417 GSTPDE PdeSrc;
2418 PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2419 PdeSrc.n.u1Present = 1;
2420 PdeSrc.n.u1Write = 1;
2421 PdeSrc.n.u1Accessed = 1;
2422 PdeSrc.n.u1User = 1;
2423
2424#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2425 Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2426 if (uErr & X86_TRAP_PF_US)
2427 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2428 else /* supervisor */
2429 STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2430
2431 rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2432 if (VBOX_SUCCESS(rc))
2433 {
2434 /* Page was successfully synced */
2435 Log2(("PGMVerifyAccess: success (sync)\n"));
2436 rc = VINF_SUCCESS;
2437 }
2438 else
2439 {
2440 Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2441 return VINF_EM_RAW_GUEST_TRAP;
2442 }
2443 }
2444 return rc;
2445
2446#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2447
2448 AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2449 return VERR_INTERNAL_ERROR;
2450#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2451}
2452
2453
2454#if PGM_GST_TYPE == PGM_TYPE_32BIT
2455# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2456/**
2457 * Figures out which kind of shadow page this guest PDE warrants.
2458 *
2459 * @returns Shadow page kind.
2460 * @param pPdeSrc The guest PDE in question.
2461 * @param cr4 The current guest cr4 value.
2462 */
2463DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2464{
2465 if (!pPdeSrc->n.u1Size || !(cr4 & X86_CR4_PSE))
2466 return BTH_PGMPOOLKIND_PT_FOR_PT;
2467 //switch (pPdeSrc->u & (X86_PDE4M_RW | X86_PDE4M_US /*| X86_PDE4M_PAE_NX*/))
2468 //{
2469 // case 0:
2470 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2471 // case X86_PDE4M_RW:
2472 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2473 // case X86_PDE4M_US:
2474 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2475 // case X86_PDE4M_RW | X86_PDE4M_US:
2476 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2477# if 0
2478 // case X86_PDE4M_PAE_NX:
2479 // return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2480 // case X86_PDE4M_RW | X86_PDE4M_PAE_NX:
2481 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2482 // case X86_PDE4M_US | X86_PDE4M_PAE_NX:
2483 // return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2484 // case X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_PAE_NX:
2485 // return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2486# endif
2487 return BTH_PGMPOOLKIND_PT_FOR_BIG;
2488 //}
2489}
2490# endif
2491#endif
2492
2493#undef MY_STAM_COUNTER_INC
2494#define MY_STAM_COUNTER_INC(a) do { } while (0)
2495
2496
2497/**
2498 * Syncs the paging hierarchy starting at CR3.
2499 *
2500 * @returns VBox status code, no specials.
2501 * @param pVM The virtual machine.
2502 * @param cr0 Guest context CR0 register
2503 * @param cr3 Guest context CR3 register
2504 * @param cr4 Guest context CR4 register
2505 * @param fGlobal Including global page directories or not
2506 */
2507PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2508{
2509#if PGM_GST_TYPE == PGM_TYPE_32BIT
2510# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2511 if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2512 fGlobal = true; /* Change this CR3 reload to be a global one. */
2513# endif
2514#endif
2515
2516 /*
2517 * Update page access handlers.
2518 * The virtual are always flushed, while the physical are only on demand.
2519 * WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2520 * have to look into that later because it will have a bad influence on the performance.
2521 * @note SvL: There's no need for that. Just invalidate the virtual range(s).
2522 * bird: Yes, but that won't work for aliases.
2523 */
2524 /** @todo this MUST go away. See #1557. */
2525 STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2526 PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2527 STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2528
2529#ifdef PGMPOOL_WITH_MONITORING
2530 /*
2531 * When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2532 * Occationally we will have to clear all the shadow page tables because we wanted
2533 * to monitor a page which was mapped by too many shadowed page tables. This operation
2534 * sometimes refered to as a 'lightweight flush'.
2535 */
2536 if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2537 pgmPoolMonitorModifiedClearAll(pVM);
2538 else
2539 {
2540# ifdef IN_RING3
2541 pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2542 pgmPoolClearAll(pVM);
2543# else
2544 LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2545 return VINF_PGM_SYNC_CR3;
2546# endif
2547 }
2548#endif
2549
2550 Assert(fGlobal || (cr4 & X86_CR4_PGE));
2551 MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2552
2553#if PGM_GST_TYPE == PGM_TYPE_32BIT
2554# if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE
2555 /*
2556 * Get page directory addresses.
2557 */
2558# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2559 PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2560# else
2561 PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2562# endif
2563
2564# if PGM_GST_TYPE == PGM_TYPE_32BIT
2565 PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2566# else /* PAE */
2567 PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, 0);
2568# endif
2569
2570 Assert(pPDSrc);
2571#ifndef IN_GC
2572 Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2573#endif
2574
2575 /*
2576 * Iterate the page directory.
2577 */
2578 PPGMMAPPING pMapping;
2579 unsigned iPdNoMapping;
2580 const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2581 PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2582
2583 /* Only check mappings if they are supposed to be put into the shadow page table. */
2584 if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2585 {
2586 pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2587 iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2588 }
2589 else
2590 {
2591 pMapping = 0;
2592 iPdNoMapping = ~0U;
2593 }
2594
2595 for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2596 {
2597# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2598 Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2599# else
2600 Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2601# endif
2602 register GSTPDE PdeSrc = pPDSrc->a[iPD];
2603 if ( PdeSrc.n.u1Present
2604 && (PdeSrc.n.u1User || fRawR0Enabled))
2605 {
2606# if PGM_GST_TYPE == PGM_TYPE_32BIT
2607 /*
2608 * Check for conflicts with GC mappings.
2609 */
2610 if (iPD == iPdNoMapping)
2611 {
2612 if (pVM->pgm.s.fMappingsFixed)
2613 {
2614 /* It's fixed, just skip the mapping. */
2615 const unsigned cPTs = pMapping->cPTs;
2616 iPD += cPTs - 1;
2617 pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2618 pMapping = pMapping->CTXALLSUFF(pNext);
2619 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2620 continue;
2621 }
2622
2623# ifdef IN_RING3
2624 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2625 if (VBOX_FAILURE(rc))
2626 return rc;
2627
2628 /*
2629 * Update iPdNoMapping and pMapping.
2630 */
2631 pMapping = pVM->pgm.s.pMappingsR3;
2632 while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2633 pMapping = pMapping->pNextR3;
2634 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2635# else
2636 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2637 return VINF_PGM_SYNC_CR3;
2638# endif
2639 }
2640# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2641 /* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2642 Assert(iPD != iPdNoMapping);
2643# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2644 /*
2645 * Sync page directory entry.
2646 *
2647 * The current approach is to allocated the page table but to set
2648 * the entry to not-present and postpone the page table synching till
2649 * it's actually used.
2650 */
2651# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2652 const unsigned iPdShw = iPD; NOREF(iPdShw);
2653# else
2654 for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2655# endif
2656 {
2657 SHWPDE PdeDst = *pPDEDst;
2658 if (PdeDst.n.u1Present)
2659 {
2660 PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2661 RTGCPHYS GCPhys;
2662 if ( !PdeSrc.b.u1Size
2663 || !(cr4 & X86_CR4_PSE))
2664 {
2665 GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2666# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2667 GCPhys |= i * (PAGE_SIZE / 2);
2668# endif
2669 }
2670 else
2671 {
2672 GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2673# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2674 GCPhys |= i * X86_PAGE_2M_SIZE;
2675# endif
2676 }
2677
2678 if ( pShwPage->GCPhys == GCPhys
2679 && pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2680 && ( pShwPage->fCached
2681 || ( !fGlobal
2682 && ( false
2683# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2684 || ( (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
2685 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE)) /* global 2/4MB page. */
2686 || ( !pShwPage->fSeenNonGlobal
2687 && (cr4 & X86_CR4_PGE))
2688# endif
2689 )
2690 )
2691 )
2692 && ( (PdeSrc.u & (X86_PDE_US | X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US | X86_PDE_RW))
2693 || ( (cr4 & X86_CR4_PSE)
2694 && ((PdeSrc.u & (X86_PDE_US | X86_PDE4M_PS | X86_PDE4M_D)) | PGM_PDFLAGS_TRACK_DIRTY)
2695 == ((PdeDst.u & (X86_PDE_US | X86_PDE_RW | PGM_PDFLAGS_TRACK_DIRTY)) | X86_PDE4M_PS))
2696 )
2697 )
2698 {
2699# ifdef VBOX_WITH_STATISTICS
2700 if ( !fGlobal
2701 && (PdeSrc.u & (X86_PDE4M_PS | X86_PDE4M_G)) == (X86_PDE4M_PS | X86_PDE4M_G)
2702 && (cr4 & (X86_CR4_PGE | X86_CR4_PSE)) == (X86_CR4_PGE | X86_CR4_PSE))
2703 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2704 else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2705 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2706 else
2707 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2708# endif /* VBOX_WITH_STATISTICS */
2709/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2710 * The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2711//# ifdef PGMPOOL_WITH_CACHE
2712// pgmPoolCacheUsed(pPool, pShwPage);
2713//# endif
2714 }
2715 else
2716 {
2717 pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2718 pPDEDst->u = 0;
2719 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2720 }
2721 }
2722 else
2723 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2724 pPDEDst++;
2725 }
2726 }
2727 else if (iPD != iPdNoMapping)
2728 {
2729 /*
2730 * Check if there is any page directory to mark not present here.
2731 */
2732# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2733 const unsigned iPdShw = iPD; NOREF(iPdShw);
2734# else
2735 for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2736# endif
2737 {
2738 if (pPDEDst->n.u1Present)
2739 {
2740 pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2741 pPDEDst->u = 0;
2742 MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2743 }
2744 pPDEDst++;
2745 }
2746 }
2747 else
2748 {
2749# if PGM_GST_TYPE == PGM_TYPE_32BIT
2750 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2751 const unsigned cPTs = pMapping->cPTs;
2752 if (pVM->pgm.s.fMappingsFixed)
2753 {
2754 /* It's fixed, just skip the mapping. */
2755 pMapping = pMapping->CTXALLSUFF(pNext);
2756 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2757 }
2758 else
2759 {
2760 /*
2761 * Check for conflicts for subsequent pagetables
2762 * and advance to the next mapping.
2763 */
2764 iPdNoMapping = ~0U;
2765 unsigned iPT = cPTs;
2766 while (iPT-- > 1)
2767 {
2768 if ( pPDSrc->a[iPD + iPT].n.u1Present
2769 && (pPDSrc->a[iPD + iPT].n.u1User || fRawR0Enabled))
2770 {
2771# ifdef IN_RING3
2772 int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2773 if (VBOX_FAILURE(rc))
2774 return rc;
2775
2776 /*
2777 * Update iPdNoMapping and pMapping.
2778 */
2779 pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2780 while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2781 pMapping = pMapping->CTXALLSUFF(pNext);
2782 iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2783 break;
2784# else
2785 LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2786 return VINF_PGM_SYNC_CR3;
2787# endif
2788 }
2789 }
2790 if (iPdNoMapping == ~0U && pMapping)
2791 {
2792 pMapping = pMapping->CTXALLSUFF(pNext);
2793 if (pMapping)
2794 iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2795 }
2796# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2797 /* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2798 AssertFailed();
2799# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
2800 }
2801
2802 /* advance. */
2803 iPD += cPTs - 1;
2804 pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2805 }
2806
2807 } /* for iPD */
2808# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
2809# error "Guest 32-bit mode and shadow AMD64 mode doesn't add up!"
2810# endif
2811
2812 return VINF_SUCCESS;
2813
2814#elif PGM_GST_TYPE == PGM_TYPE_PAE
2815# if PGM_SHW_TYPE == PGM_TYPE_PAE
2816//# error not implemented
2817 return VERR_INTERNAL_ERROR;
2818
2819# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2820# error "Guest PAE mode, but not the shadow mode ; 32bit - maybe, but amd64 no."
2821# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2822
2823#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2824# if PGM_SHW_TYPE == PGM_TYPE_AMD64
2825//# error not implemented
2826 return VERR_INTERNAL_ERROR;
2827
2828# else /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2829# error "Guest AMD64 mode, but not the shadow mode - that can't be right!"
2830# endif /* PGM_SHW_TYPE != PGM_TYPE_AMD64 */
2831
2832#else /* guest real and protected mode */
2833
2834 return VINF_SUCCESS;
2835#endif
2836}
2837
2838
2839
2840
2841#ifdef VBOX_STRICT
2842#ifdef IN_GC
2843# undef AssertMsgFailed
2844# define AssertMsgFailed Log
2845#endif
2846#ifdef IN_RING3
2847# include <VBox/dbgf.h>
2848
2849/**
2850 * Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2851 *
2852 * @returns VBox status code (VINF_SUCCESS).
2853 * @param pVM The VM handle.
2854 * @param cr3 The root of the hierarchy.
2855 * @param crr The cr4, only PAE and PSE is currently used.
2856 * @param fLongMode Set if long mode, false if not long mode.
2857 * @param cMaxDepth Number of levels to dump.
2858 * @param pHlp Pointer to the output functions.
2859 */
2860__BEGIN_DECLS
2861PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2862__END_DECLS
2863
2864#endif
2865
2866/**
2867 * Checks that the shadow page table is in sync with the guest one.
2868 *
2869 * @returns The number of errors.
2870 * @param pVM The virtual machine.
2871 * @param cr3 Guest context CR3 register
2872 * @param cr4 Guest context CR4 register
2873 * @param GCPtr Where to start. Defaults to 0.
2874 * @param cb How much to check. Defaults to everything.
2875 */
2876PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2877{
2878 unsigned cErrors = 0;
2879
2880#if PGM_GST_TYPE == PGM_TYPE_32BIT
2881
2882# if PGM_SHW_TYPE != PGM_TYPE_32BIT && PGM_SHW_TYPE != PGM_TYPE_PAE
2883# error "Invalid shadow mode for 32-bit guest paging."
2884# endif
2885
2886 PPGM pPGM = &pVM->pgm.s;
2887 RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2888 RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2889 RTHCPHYS HCPhys; /* general usage. */
2890 int rc;
2891
2892 /*
2893 * Check that the Guest CR3 and all it's mappings are correct.
2894 */
2895 AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2896 ("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2897 false);
2898 rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2899 AssertRCReturn(rc, 1);
2900 HCPhys = NIL_RTHCPHYS;
2901 rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2902 AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2903# ifdef IN_RING3
2904 RTGCPHYS GCPhys;
2905 rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2906 AssertRCReturn(rc, 1);
2907 AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2908# endif
2909 const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2910
2911 /*
2912 * Get and check the Shadow CR3.
2913 */
2914# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2915 const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2916 unsigned cPDEs = ELEMENTS(pPDDst->a);
2917# else
2918 const X86PDPAE *pPDDst = pPGM->CTXMID(ap,PaePDs[0]); /* use it as a 2048 entry PD */
2919 unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2920# endif
2921 if (cb != ~(RTGCUINTPTR)0)
2922 cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2923
2924/** @todo call the other two PGMAssert*() functions. */
2925
2926 /*
2927 * Iterate the shadow page directory.
2928 */
2929 GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2930 unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2931 cPDEs += iPDDst;
2932 for (;
2933 iPDDst < cPDEs;
2934 iPDDst++, GCPtr += _4G / cPDEs)
2935 {
2936 const SHWPDE PdeDst = pPDDst->a[iPDDst];
2937 if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2938 {
2939 Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2940 if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2941 {
2942 AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2943 cErrors++;
2944 continue;
2945 }
2946 }
2947 else if ( (PdeDst.u & X86_PDE_P)
2948 || ((PdeDst.u & (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P | PGM_PDFLAGS_TRACK_DIRTY))
2949 )
2950 {
2951 HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2952 PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2953 if (!pPoolPage)
2954 {
2955 AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2956 HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2957 cErrors++;
2958 continue;
2959 }
2960 const SHWPT *pPTDst = (const SHWPT *)PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
2961
2962 if (PdeDst.u & (X86_PDE4M_PWT | X86_PDE4M_PCD))
2963 {
2964 AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2965 GCPtr, (uint64_t)PdeDst.u));
2966 cErrors++;
2967 }
2968
2969 if (PdeDst.u & (X86_PDE4M_G | X86_PDE4M_D))
2970 {
2971 AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2972 GCPtr, (uint64_t)PdeDst.u));
2973 cErrors++;
2974 }
2975
2976 const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2977 if (!PdeSrc.n.u1Present)
2978 {
2979 AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2980 GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2981 cErrors++;
2982 continue;
2983 }
2984
2985 if ( !PdeSrc.b.u1Size
2986 || !(cr4 & X86_CR4_PSE))
2987 {
2988 GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
2989# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2990 GCPhysGst |= (iPDDst & 1) * (PAGE_SIZE / 2);
2991# endif
2992 }
2993 else
2994 {
2995 if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
2996 {
2997 AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
2998 GCPtr, (uint64_t)PdeSrc.u));
2999 cErrors++;
3000 continue;
3001 }
3002 GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3003# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3004 GCPhysGst |= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3005# endif
3006 }
3007
3008 if ( pPoolPage->enmKind
3009 != (!PdeSrc.b.u1Size || !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3010 {
3011 AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3012 pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3013 cErrors++;
3014 }
3015
3016 PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3017 if (!pPhysPage)
3018 {
3019 AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3020 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3021 cErrors++;
3022 continue;
3023 }
3024
3025 if (GCPhysGst != pPoolPage->GCPhys)
3026 {
3027 AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3028 GCPhysGst, pPoolPage->GCPhys, GCPtr));
3029 cErrors++;
3030 continue;
3031 }
3032
3033 if ( !PdeSrc.b.u1Size
3034 || !(cr4 & X86_CR4_PSE))
3035 {
3036 /*
3037 * Page Table.
3038 */
3039 const GSTPT *pPTSrc;
3040 rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3041 if (VBOX_FAILURE(rc))
3042 {
3043 AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3044 GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3045 cErrors++;
3046 continue;
3047 }
3048 if ( (PdeSrc.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/))
3049 != (PdeDst.u & (X86_PDE_P | X86_PDE_US | X86_PDE_RW/* | X86_PDE_A*/)))
3050 {
3051 /// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3052 // (This problem will go away when/if we shadow multiple CR3s.)
3053 AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3054 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3055 cErrors++;
3056 continue;
3057 }
3058 if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3059 {
3060 AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3061 GCPtr, (uint64_t)PdeDst.u));
3062 cErrors++;
3063 continue;
3064 }
3065
3066 /* iterate the page table. */
3067# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3068 const unsigned offPTSrc = 0;
3069# else
3070 const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3071# endif
3072 for (unsigned iPT = 0, off = 0;
3073 iPT < ELEMENTS(pPTDst->a);
3074 iPT++, off += PAGE_SIZE)
3075 {
3076 const SHWPTE PteDst = pPTDst->a[iPT];
3077
3078 /* skip not-present entries. */
3079 if (!(PteDst.u & (X86_PTE_P | PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3080 continue;
3081 Assert(PteDst.n.u1Present);
3082
3083 const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3084 if (!PteSrc.n.u1Present)
3085 {
3086#ifdef IN_RING3
3087 PGMAssertHandlerAndFlagsInSync(pVM);
3088 PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3089#endif
3090 AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3091 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3092 (PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3093 cErrors++;
3094 continue;
3095 }
3096
3097 uint64_t fIgnoreFlags = GST_PTE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_G | X86_PTE_D | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3098# if 1 /** @todo sync accessed bit properly... */
3099 fIgnoreFlags |= X86_PTE_A;
3100# endif
3101
3102 /* match the physical addresses */
3103 HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3104 GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3105
3106# ifdef IN_RING3
3107 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3108 if (VBOX_FAILURE(rc))
3109 {
3110 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3111 {
3112 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3113 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3114 cErrors++;
3115 continue;
3116 }
3117 }
3118 else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3119 {
3120 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3121 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3122 cErrors++;
3123 continue;
3124 }
3125# endif
3126
3127 pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3128 if (!pPhysPage)
3129 {
3130# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3131 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3132 {
3133 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3134 GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3135 cErrors++;
3136 continue;
3137 }
3138# endif
3139 if (PteDst.n.u1Write)
3140 {
3141 AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3142 GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3143 cErrors++;
3144 }
3145 fIgnoreFlags |= X86_PTE_RW;
3146 }
3147 else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3148 {
3149 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3150 GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3151 cErrors++;
3152 continue;
3153 }
3154
3155 /* flags */
3156 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3157 {
3158 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3159 {
3160 if (PteDst.n.u1Write)
3161 {
3162 AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3163 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3164 cErrors++;
3165 continue;
3166 }
3167 fIgnoreFlags |= X86_PTE_RW;
3168 }
3169 else
3170 {
3171 if (PteDst.n.u1Present)
3172 {
3173 AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3174 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3175 cErrors++;
3176 continue;
3177 }
3178 fIgnoreFlags |= X86_PTE_P;
3179 }
3180 }
3181 else
3182 {
3183 if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3184 {
3185 if (PteDst.n.u1Write)
3186 {
3187 AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3188 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3189 cErrors++;
3190 continue;
3191 }
3192 if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3193 {
3194 AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3195 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3196 cErrors++;
3197 continue;
3198 }
3199 if (PteDst.n.u1Dirty)
3200 {
3201 AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3202 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3203 cErrors++;
3204 }
3205# if 0 /** @todo sync access bit properly... */
3206 if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3207 {
3208 AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3209 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3210 cErrors++;
3211 }
3212 fIgnoreFlags |= X86_PTE_RW;
3213# else
3214 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3215# endif
3216 }
3217 else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3218 {
3219 /* access bit emulation (not implemented). */
3220 if (PteSrc.n.u1Accessed || PteDst.n.u1Present)
3221 {
3222 AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3223 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3224 cErrors++;
3225 continue;
3226 }
3227 if (!PteDst.n.u1Accessed)
3228 {
3229 AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3230 GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3231 cErrors++;
3232 }
3233 fIgnoreFlags |= X86_PTE_P;
3234 }
3235# ifdef DEBUG_sandervl
3236 fIgnoreFlags |= X86_PTE_D | X86_PTE_A;
3237# endif
3238 }
3239
3240 if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3241 && (PteSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3242 )
3243 {
3244 AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3245 GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3246 fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3247 cErrors++;
3248 continue;
3249 }
3250 } /* foreach PTE */
3251 }
3252 else
3253 {
3254 /*
3255 * Big Page.
3256 */
3257 uint64_t fIgnoreFlags = X86_PDE_AVL_MASK | X86_PDE_PAE_PG_MASK | X86_PDE4M_G | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_PWT | X86_PDE4M_PCD;
3258 if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3259 {
3260 if (PdeDst.n.u1Write)
3261 {
3262 AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3263 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3264 cErrors++;
3265 continue;
3266 }
3267 if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3268 {
3269 AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3270 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3271 cErrors++;
3272 continue;
3273 }
3274# if 0 /** @todo sync access bit properly... */
3275 if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3276 {
3277 AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3278 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3279 cErrors++;
3280 }
3281 fIgnoreFlags |= X86_PTE_RW;
3282# else
3283 fIgnoreFlags |= X86_PTE_RW | X86_PTE_A;
3284# endif
3285 }
3286 else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3287 {
3288 /* access bit emulation (not implemented). */
3289 if (PdeSrc.b.u1Accessed || PdeDst.n.u1Present)
3290 {
3291 AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3292 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3293 cErrors++;
3294 continue;
3295 }
3296 if (!PdeDst.n.u1Accessed)
3297 {
3298 AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3299 GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3300 cErrors++;
3301 }
3302 fIgnoreFlags |= X86_PTE_P;
3303 }
3304
3305 if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3306 {
3307 AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3308 GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3309 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3310 cErrors++;
3311 }
3312
3313 /* iterate the page table. */
3314 for (unsigned iPT = 0, off = 0;
3315 iPT < ELEMENTS(pPTDst->a);
3316 iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3317 {
3318 const SHWPTE PteDst = pPTDst->a[iPT];
3319
3320 if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3321 {
3322 AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3323 GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3324 cErrors++;
3325 }
3326
3327 /* skip not-present entries. */
3328 if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3329 continue;
3330
3331 fIgnoreFlags = X86_PTE_PAE_PG_MASK | X86_PTE_AVL_MASK | X86_PTE_PWT | X86_PTE_PCD | X86_PTE_PAT;
3332
3333 /* match the physical addresses */
3334 HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3335
3336# ifdef IN_RING3
3337 rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3338 if (VBOX_FAILURE(rc))
3339 {
3340 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3341 {
3342 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3343 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3344 cErrors++;
3345 }
3346 }
3347 else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3348 {
3349 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3350 GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3351 cErrors++;
3352 continue;
3353 }
3354# endif
3355
3356 pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3357 if (!pPhysPage)
3358 {
3359# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3360 if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3361 {
3362 AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3363 GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3364 cErrors++;
3365 continue;
3366 }
3367# endif
3368 if (PteDst.n.u1Write)
3369 {
3370 AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3371 GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3372 cErrors++;
3373 }
3374 fIgnoreFlags |= X86_PTE_RW;
3375 }
3376 else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3377 {
3378 AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3379 GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3380 cErrors++;
3381 continue;
3382 }
3383
3384 /* flags */
3385 if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3386 {
3387 if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3388 {
3389 if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3390 {
3391 if (PteDst.n.u1Write)
3392 {
3393 AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3394 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3395 cErrors++;
3396 continue;
3397 }
3398 fIgnoreFlags |= X86_PTE_RW;
3399 }
3400 }
3401 else
3402 {
3403 if (PteDst.n.u1Present)
3404 {
3405 AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3406 GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3407 cErrors++;
3408 continue;
3409 }
3410 fIgnoreFlags |= X86_PTE_P;
3411 }
3412 }
3413
3414 if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3415 && (PdeSrc.u & ~(fIgnoreFlags | X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3416 )
3417 {
3418 AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3419 GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3420 fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3421 cErrors++;
3422 continue;
3423 }
3424 } /* foreach PTE */
3425 }
3426 }
3427 /* not present */
3428
3429 } /* forearch PDE */
3430
3431# ifdef DEBUG
3432 if (cErrors)
3433 LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3434# endif
3435
3436#elif PGM_GST_TYPE == PGM_TYPE_PAE
3437//# error not implemented
3438
3439
3440#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3441//# error not implemented
3442
3443/*#else: guest real and protected mode */
3444#endif
3445 return cErrors;
3446}
3447#endif /* VBOX_STRICT */
3448
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