PGMAllBth.h@ 7715

Last change on this file since 7715 was 7715, checked in by vboxsync, 17 years ago
Renamed PDPTR to PDPT. Added preliminary code for executing code with X86_CR0_WP cleared (disabled).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 150.2 KB

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1	/* $Id: PGMAllBth.h 7715 2008-04-03 09:03:01Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
42	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
43	#error "Invalid combination; PAE guest implies PAE shadow"
44	#endif
45
46	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
47	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
48	#error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
53	#error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
57	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
58	#error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
59	#endif
60
61	/**
62	* #PF Handler for raw-mode guest execution.
63	*
64	* @returns VBox status code (appropriate for trap handling and GC return).
65	* @param pVM VM Handle.
66	* @param uErr The trap error code.
67	* @param pRegFrame Trap register frame.
68	* @param pvFault The fault address.
69	*/
70	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
71	{
72	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
73
74	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
75	/*
76	* Hide the instruction fetch trap indicator for now.
77	*/
78	/** @todo NXE will change this and we must fix NXE in the switcher too! */
79	if (uErr & X86_TRAP_PF_ID)
80	{
81	uErr &= ~X86_TRAP_PF_ID;
82	TRPMSetErrorCode(pVM, uErr);
83	}
84	# endif
85
86	/*
87	* Get PDs.
88	*/
89	int rc;
90	# if PGM_WITH_PAGING(PGM_GST_TYPE)
91	# if PGM_GST_TYPE == PGM_TYPE_32BIT
92	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
93	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
94	# else /* PAE */
95	unsigned iPDSrc;
96	PGSTPD pPDSrc = pgmGstGetPaePDPt(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
97	# endif
98	# else
99	PGSTPD pPDSrc = NULL;
100	const unsigned iPDSrc = 0;
101	# endif
102
103	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
104	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
105	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
106	# else /* PAE */
107	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
108	# endif
109
110	# if PGM_WITH_PAGING(PGM_GST_TYPE)
111	# ifdef PGM_SYNC_DIRTY_BIT
112	/*
113	* If we successfully correct the write protection fault due to dirty bit
114	* tracking, or this page fault is a genuine one, then return immediately.
115	*/
116	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
117	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
118	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
119	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
120	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
121	{
122	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
123	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
124	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
125	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
126	}
127	# endif
128
129	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
130	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
131
132	/*
133	* A common case is the not-present error caused by lazy page table syncing.
134	*
135	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
136	* so we can safely assume that the shadow PT is present when calling SyncPage later.
137	*
138	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
139	* of mapping conflict and defer to SyncCR3 in R3.
140	* (Again, we do NOT support access handlers for non-present guest pages.)
141	*
142	*/
143	# if PGM_WITH_PAGING(PGM_GST_TYPE)
144	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
145	# else
146	GSTPDE PdeSrc;
147	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
148	PdeSrc.n.u1Present = 1;
149	PdeSrc.n.u1Write = 1;
150	PdeSrc.n.u1Accessed = 1;
151	PdeSrc.n.u1User = 1;
152	# endif
153	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
154	&& !pPDDst->a[iPDDst].n.u1Present
155	&& PdeSrc.n.u1Present
156	)
157
158	{
159	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
160	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
161	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
162	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
163	if (VBOX_SUCCESS(rc))
164	{
165	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
166	return rc;
167	}
168	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
169	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
170	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
171	return VINF_PGM_SYNC_CR3;
172	}
173
174	# if PGM_WITH_PAGING(PGM_GST_TYPE)
175	/*
176	* Check if this address is within any of our mappings.
177	*
178	* This is very fast and it's gonna save us a bit of effort below and prevent
179	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
180	* (BTW, it's impossible to have physical access handlers in a mapping.)
181	*/
182	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
183	{
184	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
185	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
186	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
187	{
188	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
189	break;
190	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
191	{
192	/*
193	* The first thing we check is if we've got an undetected conflict.
194	*/
195	if (!pVM->pgm.s.fMappingsFixed)
196	{
197	unsigned iPT = pMapping->cPTs;
198	while (iPT-- > 0)
199	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
200	{
201	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
202	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
203	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
204	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
205	return VINF_PGM_SYNC_CR3;
206	}
207	}
208
209	/*
210	* Check if the fault address is in a virtual page access handler range.
211	*/
212	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
213	if ( pCur
214	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
215	&& uErr & X86_TRAP_PF_RW)
216	{
217	# ifdef IN_GC
218	STAM_PROFILE_START(&pCur->Stat, h);
219	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
220	STAM_PROFILE_STOP(&pCur->Stat, h);
221	# else
222	AssertFailed();
223	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
224	# endif
225	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
226	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
227	return rc;
228	}
229
230	/*
231	* Pretend we're not here and let the guest handle the trap.
232	*/
233	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
234	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
235	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
236	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
237	return VINF_EM_RAW_GUEST_TRAP;
238	}
239	}
240	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
241	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
242	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
243
244	/*
245	* Check if this fault address is flagged for special treatment,
246	* which means we'll have to figure out the physical address and
247	* check flags associated with it.
248	*
249	* ASSUME that we can limit any special access handling to pages
250	* in page tables which the guest believes to be present.
251	*/
252	if (PdeSrc.n.u1Present)
253	{
254	RTGCPHYS GCPhys = NIL_RTGCPHYS;
255
256	# if PGM_WITH_PAGING(PGM_GST_TYPE)
257	uint32_t cr4 = CPUMGetGuestCR4(pVM);
258	if ( PdeSrc.b.u1Size
259	&& (cr4 & X86_CR4_PSE))
260	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
261	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
262	else
263	{
264	PX86PT pPTSrc;
265	# ifdef IN_GC
266	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & GST_PDE_PG_MASK, (void **)&pPTSrc);
267	# else
268	pPTSrc = (PX86PT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & GST_PDE_PG_MASK, sizeof(*pPTSrc));
269	if (pPTSrc == 0)
270	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
271	# endif
272	if (VBOX_SUCCESS(rc))
273	{
274	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & GST_PT_MASK;
275	if (pPTSrc->a[iPTESrc].n.u1Present)
276	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
277	}
278	}
279	# else
280	/* No paging so the fault address is the physical address */
281	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
282	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
283
284	/*
285	* If we have a GC address we'll check if it has any flags set.
286	*/
287	if (GCPhys != NIL_RTGCPHYS)
288	{
289	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
290
291	PPGMPAGE pPage;
292	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
293	if (VBOX_SUCCESS(rc))
294	{
295	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
296	{
297	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
298	{
299	/*
300	* Physical page access handler.
301	*/
302	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
303	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
304	if (pCur)
305	{
306	# ifdef PGM_SYNC_N_PAGES
307	/*
308	* If the region is write protected and we got a page not present fault, then sync
309	* the pages. If the fault was caused by a read, then restart the instruction.
310	* In case of write access continue to the GC write handler.
311	*
312	* ASSUMES that there is only one handler per page or that they have similar write properties.
313	*/
314	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
315	&& !(uErr & X86_TRAP_PF_P))
316	{
317	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
318	if ( VBOX_FAILURE(rc)
319	\|\| !(uErr & X86_TRAP_PF_RW)
320	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
321	{
322	AssertRC(rc);
323	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
324	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
325	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
326	return rc;
327	}
328	}
329	# endif
330
331	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
332	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
333	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
334
335	#if defined(IN_GC) \|\| defined(IN_RING0)
336	if (CTXALLSUFF(pCur->pfnHandler))
337	{
338	STAM_PROFILE_START(&pCur->Stat, h);
339	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
340	STAM_PROFILE_STOP(&pCur->Stat, h);
341	}
342	else
343	#endif
344	rc = VINF_EM_RAW_EMULATE_INSTR;
345	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
346	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
347	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
348	return rc;
349	}
350	}
351	# if PGM_WITH_PAGING(PGM_GST_TYPE)
352	else
353	{
354	# ifdef PGM_SYNC_N_PAGES
355	/*
356	* If the region is write protected and we got a page not present fault, then sync
357	* the pages. If the fault was caused by a read, then restart the instruction.
358	* In case of write access continue to the GC write handler.
359	*/
360	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
361	&& !(uErr & X86_TRAP_PF_P))
362	{
363	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
364	if ( VBOX_FAILURE(rc)
365	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
366	\|\| !(uErr & X86_TRAP_PF_RW))
367	{
368	AssertRC(rc);
369	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
370	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
371	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
372	return rc;
373	}
374	}
375	# endif
376	/*
377	* Ok, it's an virtual page access handler.
378	*
379	* Since it's faster to search by address, we'll do that first
380	* and then retry by GCPhys if that fails.
381	*/
382	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
383	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
384	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
385	*/
386	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
387	if (pCur)
388	{
389	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
390	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
391	\|\| !(uErr & X86_TRAP_PF_P)
392	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
393	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
394
395	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
396	&& ( uErr & X86_TRAP_PF_RW
397	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
398	{
399	# ifdef IN_GC
400	STAM_PROFILE_START(&pCur->Stat, h);
401	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
402	STAM_PROFILE_STOP(&pCur->Stat, h);
403	# else
404	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
405	# endif
406	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
407	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
408	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
409	return rc;
410	}
411	/* Unhandled part of a monitored page */
412	}
413	else
414	{
415	/* Check by physical address. */
416	PPGMVIRTHANDLER pCur;
417	unsigned iPage;
418	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
419	&pCur, &iPage);
420	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
421	if ( pCur
422	&& ( uErr & X86_TRAP_PF_RW
423	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
424	{
425	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
426	# ifdef IN_GC
427	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
428	Assert(off < pCur->cb);
429	STAM_PROFILE_START(&pCur->Stat, h);
430	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
431	STAM_PROFILE_STOP(&pCur->Stat, h);
432	# else
433	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
434	# endif
435	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
436	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
437	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
438	return rc;
439	}
440	}
441	}
442	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
443
444	/*
445	* There is a handled area of the page, but this fault doesn't belong to it.
446	* We must emulate the instruction.
447	*
448	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
449	* we first check if this was a page-not-present fault for a page with only
450	* write access handlers. Restart the instruction if it wasn't a write access.
451	*/
452	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
453
454	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
455	&& !(uErr & X86_TRAP_PF_P))
456	{
457	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
458	if ( VBOX_FAILURE(rc)
459	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
460	\|\| !(uErr & X86_TRAP_PF_RW))
461	{
462	AssertRC(rc);
463	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
464	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
465	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
466	return rc;
467	}
468	}
469
470	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
471	* It's writing to an unhandled part of the LDT page several million times.
472	*/
473	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
474	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
475	rc, pPage->HCPhys,
476	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
477	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
478	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
479	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
480	return rc;
481	} /* if any kind of handler */
482
483	# if PGM_WITH_PAGING(PGM_GST_TYPE)
484	if (uErr & X86_TRAP_PF_P)
485	{
486	/*
487	* The page isn't marked, but it might still be monitored by a virtual page access handler.
488	* (ASSUMES no temporary disabling of virtual handlers.)
489	*/
490	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
491	* we should correct both the shadow page table and physical memory flags, and not only check for
492	* accesses within the handler region but for access to pages with virtual handlers. */
493	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
494	if (pCur)
495	{
496	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
497	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
498	\|\| !(uErr & X86_TRAP_PF_P)
499	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
500	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
501
502	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
503	&& ( uErr & X86_TRAP_PF_RW
504	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
505	{
506	# ifdef IN_GC
507	STAM_PROFILE_START(&pCur->Stat, h);
508	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
509	STAM_PROFILE_STOP(&pCur->Stat, h);
510	# else
511	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
512	# endif
513	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
514	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
515	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
516	return rc;
517	}
518	}
519	}
520	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
521	}
522	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
523
524	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
525	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
526	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
527	&& (uErr & X86_TRAP_PF_RW))
528	{
529	uint64_t fPageGst;
530	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
531	if ( VBOX_SUCCESS(rc)
532	&& !(fPageGst & X86_PTE_RW))
533	{
534	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
535	if (VBOX_SUCCESS(rc))
536	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
537	else
538	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
539	return rc;
540	}
541	}
542
543	# ifdef PGM_OUT_OF_SYNC_IN_GC
544	/*
545	* We are here only if page is present in Guest page tables and trap is not handled
546	* by our handlers.
547	* Check it for page out-of-sync situation.
548	*/
549	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
550
551	if (!(uErr & X86_TRAP_PF_P))
552	{
553	/*
554	* Page is not present in our page tables.
555	* Try to sync it!
556	* BTW, fPageShw is invalid in this branch!
557	*/
558	if (uErr & X86_TRAP_PF_US)
559	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
560	else /* supervisor */
561	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
562
563	# if defined(LOG_ENABLED) && !defined(IN_RING0)
564	RTGCPHYS GCPhys;
565	uint64_t fPageGst;
566	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
567	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
568	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
569	# endif /* LOG_ENABLED */
570
571	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
572	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
573	{
574	uint64_t fPageGst;
575	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
576	if ( VBOX_SUCCESS(rc)
577	&& !(fPageGst & X86_PTE_US))
578	{
579	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
580	if ( pvFault == (RTGCPTR)pRegFrame->eip
581	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
582	# ifdef CSAM_DETECT_NEW_CODE_PAGES
583	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
584	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
585	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
586	)
587	{
588	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
589	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
590	if (rc != VINF_SUCCESS)
591	{
592	/*
593	* CSAM needs to perform a job in ring 3.
594	*
595	* Sync the page before going to the host context; otherwise we'll end up in a loop if
596	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
597	*/
598	LogFlow(("CSAM ring 3 job\n"));
599	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
600	AssertRC(rc2);
601
602	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
603	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
604	return rc;
605	}
606	}
607	# ifdef CSAM_DETECT_NEW_CODE_PAGES
608	else
609	if ( uErr == X86_TRAP_PF_RW
610	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
611	&& pRegFrame->ecx < 0x10000
612	)
613	{
614	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
615	* to detect loading of new code pages.
616	*/
617
618	/*
619	* Decode the instruction.
620	*/
621	RTGCPTR PC;
622	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
623	if (rc == VINF_SUCCESS)
624	{
625	DISCPUSTATE Cpu;
626	uint32_t cbOp;
627	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
628
629	/* For now we'll restrict this to rep movsw/d instructions */
630	if ( rc == VINF_SUCCESS
631	&& Cpu.pCurInstr->opcode == OP_MOVSWD
632	&& (Cpu.prefix & PREFIX_REP))
633	{
634	CSAMMarkPossibleCodePage(pVM, pvFault);
635	}
636	}
637	}
638	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
639
640	/*
641	* Mark this page as safe.
642	*/
643	/** @todo not correct for pages that contain both code and data!! */
644	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
645	CSAMMarkPage(pVM, pvFault, true);
646	}
647	}
648	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
649	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
650	if (VBOX_SUCCESS(rc))
651	{
652	/* The page was successfully synced, return to the guest. */
653	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
654	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
655	return VINF_SUCCESS;
656	}
657	}
658	else
659	{
660	/*
661	* A side effect of not flushing global PDEs are out of sync pages due
662	* to physical monitored regions, that are no longer valid.
663	* Assume for now it only applies to the read/write flag
664	*/
665	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
666	{
667	if (uErr & X86_TRAP_PF_US)
668	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
669	else /* supervisor */
670	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
671
672
673	/*
674	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
675	*/
676	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
677	if (VBOX_SUCCESS(rc))
678	{
679	/*
680	* Page was successfully synced, return to guest.
681	*/
682	# ifdef VBOX_STRICT
683	RTGCPHYS GCPhys;
684	uint64_t fPageGst;
685	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
686	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
687	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
688
689	uint64_t fPageShw;
690	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
691	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
692	# endif /* VBOX_STRICT */
693	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
694	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
695	return VINF_SUCCESS;
696	}
697	}
698
699	# if PGM_WITH_PAGING(PGM_GST_TYPE)
700	# ifdef VBOX_STRICT
701	/*
702	* Check for VMM page flags vs. Guest page flags consistency.
703	* Currently only for debug purposes.
704	*/
705	if (VBOX_SUCCESS(rc))
706	{
707	/* Get guest page flags. */
708	uint64_t fPageGst;
709	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
710	if (VBOX_SUCCESS(rc))
711	{
712	uint64_t fPageShw;
713	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
714
715	/*
716	* Compare page flags.
717	* Note: we have AVL, A, D bits desynched.
718	*/
719	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
720	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
721	}
722	else
723	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
724	}
725	else
726	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
727	# endif /* VBOX_STRICT */
728	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
729	}
730	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
731	# endif /* PGM_OUT_OF_SYNC_IN_GC */
732	}
733	else
734	{
735	/*
736	* Page not present in Guest OS or invalid page table address.
737	* This is potential virtual page access handler food.
738	*
739	* For the present we'll say that our access handlers don't
740	* work for this case - we've already discarded the page table
741	* not present case which is identical to this.
742	*
743	* When we perchance find we need this, we will probably have AVL
744	* trees (offset based) to operate on and we can measure their speed
745	* agains mapping a page table and probably rearrange this handling
746	* a bit. (Like, searching virtual ranges before checking the
747	* physical address.)
748	*/
749	}
750	}
751
752
753	# if PGM_WITH_PAGING(PGM_GST_TYPE)
754	/*
755	* Conclusion, this is a guest trap.
756	*/
757	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
758	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
759	return VINF_EM_RAW_GUEST_TRAP;
760	# else
761	/* present, but not a monitored page; perhaps the guest is probing physical memory */
762	return VINF_EM_RAW_EMULATE_INSTR;
763	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
764
765
766	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
767
768	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
769	return VERR_INTERNAL_ERROR;
770	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
771	}
772
773
774	/**
775	* Emulation of the invlpg instruction.
776	*
777	*
778	* @returns VBox status code.
779	*
780	* @param pVM VM handle.
781	* @param GCPtrPage Page to invalidate.
782	*
783	* @remark ASSUMES that the guest is updating before invalidating. This order
784	* isn't required by the CPU, so this is speculative and could cause
785	* trouble.
786	*
787	* @todo Flush page or page directory only if necessary!
788	* @todo Add a #define for simply invalidating the page.
789	*/
790	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
791	{
792	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
793	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
794
795	LogFlow(("InvalidatePage %x\n", GCPtrPage));
796	/*
797	* Get the shadow PD entry and skip out if this PD isn't present.
798	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
799	*/
800	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
801	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
802	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
803	# else
804	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
805	# endif
806	const SHWPDE PdeDst = *pPdeDst;
807	if (!PdeDst.n.u1Present)
808	{
809	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
810	return VINF_SUCCESS;
811	}
812
813	/*
814	* Get the guest PD entry and calc big page.
815	*/
816	# if PGM_GST_TYPE == PGM_TYPE_32BIT
817	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
818	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
819	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
820	# else /* PAE */
821	unsigned iPDSrc;
822	PX86PDPAE pPDSrc = pgmGstGetPaePDPt(&pVM->pgm.s, GCPtrPage, &iPDSrc);
823	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
824	# endif
825
826	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
827	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
828
829	# ifdef IN_RING3
830	/*
831	* If a CR3 Sync is pending we may ignore the invalidate page operation
832	* depending on the kind of sync and if it's a global page or not.
833	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
834	*/
835	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
836	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
837	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
838	&& fIsBigPage
839	&& PdeSrc.b.u1Global
840	&& (cr4 & X86_CR4_PGE)
841	)
842	)
843	# else
844	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
845	# endif
846	{
847	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
848	return VINF_SUCCESS;
849	}
850	# endif /* IN_RING3 */
851
852
853	/*
854	* Deal with the Guest PDE.
855	*/
856	int rc = VINF_SUCCESS;
857	if (PdeSrc.n.u1Present)
858	{
859	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
860	{
861	/*
862	* Conflict - Let SyncPT deal with it to avoid duplicate code.
863	*/
864	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
865	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
866	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
867	}
868	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
869	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
870	{
871	/*
872	* Mark not present so we can resync the PDE when it's used.
873	*/
874	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
875	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
876	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
877	pPdeDst->u = 0;
878	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
879	PGM_INVL_GUEST_TLBS();
880	}
881	# ifdef PGM_SYNC_ACCESSED_BIT
882	else if (!PdeSrc.n.u1Accessed)
883	{
884	/*
885	* Mark not present so we can set the accessed bit.
886	*/
887	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
888	pPdeDst->u = 0;
889	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
890	PGM_INVL_GUEST_TLBS();
891	}
892	# endif
893	else if (!fIsBigPage)
894	{
895	/*
896	* 4KB - page.
897	*/
898	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
899	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
900	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
901	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
902	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
903	# endif
904	if (pShwPage->GCPhys == GCPhys)
905	{
906	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
907	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
908	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
909	if (pPT->a[iPTEDst].n.u1Present)
910	{
911	# ifdef PGMPOOL_WITH_USER_TRACKING
912	/* This is very unlikely with caching/monitoring enabled. */
913	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
914	# endif
915	pPT->a[iPTEDst].u = 0;
916	}
917	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
918	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
919	if (VBOX_SUCCESS(rc))
920	rc = VINF_SUCCESS;
921	# endif
922	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
923	PGM_INVL_PG(GCPtrPage);
924	}
925	else
926	{
927	/*
928	* The page table address changed.
929	*/
930	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
931	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
932	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
933	pPdeDst->u = 0;
934	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
935	PGM_INVL_GUEST_TLBS();
936	}
937	}
938	else
939	{
940	/*
941	* 4MB - page.
942	*/
943	/* Before freeing the page, check if anything really changed. */
944	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
945	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
946	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
947	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
948	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
949	# endif
950	if ( pShwPage->GCPhys == GCPhys
951	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
952	{
953	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
954	/** @todo PAT */
955	# ifdef PGM_SYNC_DIRTY_BIT
956	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
957	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
958	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
959	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
960	# else
961	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
962	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
963	# endif
964	{
965	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
966	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
967	return VINF_SUCCESS;
968	}
969	}
970
971	/*
972	* Ok, the page table is present and it's been changed in the guest.
973	* If we're in host context, we'll just mark it as not present taking the lazy approach.
974	* We could do this for some flushes in GC too, but we need an algorithm for
975	* deciding which 4MB pages containing code likely to be executed very soon.
976	*/
977	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
978	pPdeDst->u = 0;
979	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
980	PGM_INVL_BIG_PG(GCPtrPage);
981	}
982	}
983	else
984	{
985	/*
986	* Page directory is not present, mark shadow PDE not present.
987	*/
988	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
989	{
990	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
991	pPdeDst->u = 0;
992	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
993	PGM_INVL_PG(GCPtrPage);
994	}
995	else
996	{
997	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
998	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
999	}
1000	}
1001
1002	return rc;
1003
1004	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1005	//# error not implemented
1006	return VERR_INTERNAL_ERROR;
1007
1008	#else /* guest real and protected mode */
1009	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1010	return VINF_SUCCESS;
1011	#endif
1012	}
1013
1014
1015	#ifdef PGMPOOL_WITH_USER_TRACKING
1016	/**
1017	* Update the tracking of shadowed pages.
1018	*
1019	* @param pVM The VM handle.
1020	* @param pShwPage The shadow page.
1021	* @param HCPhys The physical page we is being dereferenced.
1022	*/
1023	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1024	{
1025	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1026	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1027	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1028
1029	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1030	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1031	* 2. write protect all shadowed pages. I.e. implement caching.
1032	*/
1033	/*
1034	* Find the guest address.
1035	*/
1036	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1037	pRam;
1038	pRam = CTXALLSUFF(pRam->pNext))
1039	{
1040	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1041	while (iPage-- > 0)
1042	{
1043	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1044	{
1045	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1046	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1047	pShwPage->cPresent--;
1048	pPool->cPresent--;
1049	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1050	return;
1051	}
1052	}
1053	}
1054
1055	for (;;)
1056	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1057	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1058	pShwPage->cPresent--;
1059	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1060	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1061	}
1062
1063
1064	/**
1065	* Update the tracking of shadowed pages.
1066	*
1067	* @param pVM The VM handle.
1068	* @param pShwPage The shadow page.
1069	* @param u16 The top 16-bit of the pPage->HCPhys.
1070	* @param pPage Pointer to the guest page. this will be modified.
1071	* @param iPTDst The index into the shadow table.
1072	*/
1073	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1074	{
1075	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1076	/*
1077	* We're making certain assumptions about the placement of cRef and idx.
1078	*/
1079	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1080	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1081
1082	/*
1083	* Just deal with the simple first time here.
1084	*/
1085	if (!u16)
1086	{
1087	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1088	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1089	}
1090	else
1091	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1092
1093	/* write back, trying to be clever... */
1094	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1095	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1096	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1097	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1098
1099	/* update statistics. */
1100	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1101	pShwPage->cPresent++;
1102	if (pShwPage->iFirstPresent > iPTDst)
1103	pShwPage->iFirstPresent = iPTDst;
1104	}
1105	#endif /* PGMPOOL_WITH_USER_TRACKING */
1106
1107
1108	/**
1109	* Creates a 4K shadow page for a guest page.
1110	*
1111	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1112	* physical address. The PdeSrc argument only the flags are used. No page structured
1113	* will be mapped in this function.
1114	*
1115	* @param pVM VM handle.
1116	* @param pPteDst Destination page table entry.
1117	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1118	* Can safely assume that only the flags are being used.
1119	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1120	* @param pShwPage Pointer to the shadow page.
1121	* @param iPTDst The index into the shadow table.
1122	*
1123	* @remark Not used for 2/4MB pages!
1124	*/
1125	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1126	{
1127	if (PteSrc.n.u1Present)
1128	{
1129	/*
1130	* Find the ram range.
1131	*/
1132	PPGMPAGE pPage;
1133	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1134	if (VBOX_SUCCESS(rc))
1135	{
1136	/** @todo investiage PWT, PCD and PAT. */
1137	/*
1138	* Make page table entry.
1139	*/
1140	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1141	SHWPTE PteDst;
1142	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1143	{
1144	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1145	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1146	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1147	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1148	else
1149	{
1150	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1151	PteDst.u = 0;
1152	}
1153	/** @todo count these two kinds. */
1154	}
1155	else
1156	{
1157	#ifdef PGM_SYNC_DIRTY_BIT
1158	# ifdef PGM_SYNC_ACCESSED_BIT
1159	/*
1160	* If the page or page directory entry is not marked accessed,
1161	* we mark the page not present.
1162	*/
1163	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1164	{
1165	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1166	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1167	PteDst.u = 0;
1168	}
1169	else
1170	# endif
1171	/*
1172	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1173	* when the page is modified.
1174	*/
1175	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1176	{
1177	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1178	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1179	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1180	\| PGM_PTFLAGS_TRACK_DIRTY;
1181	}
1182	else
1183	{
1184	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1185	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1186	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1187	}
1188	#endif
1189	}
1190
1191	#ifdef PGMPOOL_WITH_USER_TRACKING
1192	/*
1193	* Keep user track up to date.
1194	*/
1195	if (PteDst.n.u1Present)
1196	{
1197	if (!pPteDst->n.u1Present)
1198	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1199	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1200	{
1201	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1202	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1203	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1204	}
1205	}
1206	else if (pPteDst->n.u1Present)
1207	{
1208	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1209	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1210	}
1211	#endif /* PGMPOOL_WITH_USER_TRACKING */
1212
1213	/*
1214	* Update statistics and commit the entry.
1215	*/
1216	if (!PteSrc.n.u1Global)
1217	pShwPage->fSeenNonGlobal = true;
1218	*pPteDst = PteDst;
1219	}
1220	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1221	/** @todo count these. */
1222	}
1223	else
1224	{
1225	/*
1226	* Page not-present.
1227	*/
1228	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1229	#ifdef PGMPOOL_WITH_USER_TRACKING
1230	/* Keep user track up to date. */
1231	if (pPteDst->n.u1Present)
1232	{
1233	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1234	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1235	}
1236	#endif /* PGMPOOL_WITH_USER_TRACKING */
1237	pPteDst->u = 0;
1238	/** @todo count these. */
1239	}
1240	}
1241
1242
1243	/**
1244	* Syncs a guest OS page.
1245	*
1246	* There are no conflicts at this point, neither is there any need for
1247	* page table allocations.
1248	*
1249	* @returns VBox status code.
1250	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1251	* @param pVM VM handle.
1252	* @param PdeSrc Page directory entry of the guest.
1253	* @param GCPtrPage Guest context page address.
1254	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1255	* @param uErr Fault error (X86_TRAP_PF_*).
1256	*/
1257	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1258	{
1259	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1260
1261	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1262	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1263
1264	/*
1265	* Assert preconditions.
1266	*/
1267	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1268	Assert(PdeSrc.n.u1Present);
1269	Assert(cPages);
1270
1271	/*
1272	* Get the shadow PDE, find the shadow page table in the pool.
1273	*/
1274	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1275	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1276	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1277	# else /* PAE */
1278	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1279	# endif
1280	Assert(PdeDst.n.u1Present);
1281	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1282
1283	/*
1284	* Check that the page is present and that the shadow PDE isn't out of sync.
1285	*/
1286	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1287	RTGCPHYS GCPhys;
1288	if (!fBigPage)
1289	{
1290	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1291	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1292	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1293	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1294	# endif
1295	}
1296	else
1297	{
1298	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1299	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1300	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1301	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1302	# endif
1303	}
1304	if ( pShwPage->GCPhys == GCPhys
1305	&& PdeSrc.n.u1Present
1306	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1307	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1308	# if PGM_GST_TYPE == PGM_TYPE_PAE
1309	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1310	# endif
1311	)
1312	{
1313	# ifdef PGM_SYNC_ACCESSED_BIT
1314	/*
1315	* Check that the PDE is marked accessed already.
1316	* Since we set the accessed bit before getting here on a #PF, this
1317	* check is only meant for dealing with non-#PF'ing paths.
1318	*/
1319	if (PdeSrc.n.u1Accessed)
1320	# endif
1321	{
1322	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1323	if (!fBigPage)
1324	{
1325	/*
1326	* 4KB Page - Map the guest page table.
1327	*/
1328	PGSTPT pPTSrc;
1329	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1330	if (VBOX_SUCCESS(rc))
1331	{
1332	# ifdef PGM_SYNC_N_PAGES
1333	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1334	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1335	{
1336	/*
1337	* This code path is currently only taken when the caller is PGMTrap0eHandler
1338	* for non-present pages!
1339	*
1340	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1341	* deal with locality.
1342	*/
1343	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1344	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1345	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1346	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1347	# else
1348	const unsigned offPTSrc = 0;
1349	# endif
1350	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1351	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1352	iPTDst = 0;
1353	else
1354	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1355	for (; iPTDst < iPTDstEnd; iPTDst++)
1356	{
1357	if (!pPTDst->a[iPTDst].n.u1Present)
1358	{
1359	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1360	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1361	NOREF(GCPtrCurPage);
1362	#ifndef IN_RING0
1363	/*
1364	* Assuming kernel code will be marked as supervisor - and not as user level
1365	* and executed using a conforming code selector - And marked as readonly.
1366	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1367	*/
1368	PPGMPAGE pPage;
1369	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1370	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1371	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1372	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1373	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1374	)
1375	#endif /* else: CSAM not active */
1376	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1377	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1378	GCPtrCurPage, PteSrc.n.u1Present,
1379	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1380	PteSrc.n.u1User & PdeSrc.n.u1User,
1381	(uint64_t)PteSrc.u,
1382	(uint64_t)pPTDst->a[iPTDst].u,
1383	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1384	}
1385	}
1386	}
1387	else
1388	# endif /* PGM_SYNC_N_PAGES */
1389	{
1390	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1391	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1392	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1393	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1394	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1395	GCPtrPage, PteSrc.n.u1Present,
1396	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1397	PteSrc.n.u1User & PdeSrc.n.u1User,
1398	(uint64_t)PteSrc.u,
1399	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1400	}
1401	}
1402	else /* MMIO or invalid page: emulated in #PF handler. */
1403	{
1404	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1405	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1406	}
1407	}
1408	else
1409	{
1410	/*
1411	* 4/2MB page - lazy syncing shadow 4K pages.
1412	* (There are many causes of getting here, it's no longer only CSAM.)
1413	*/
1414	/* Calculate the GC physical address of this 4KB shadow page. */
1415	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1416	/* Find ram range. */
1417	PPGMPAGE pPage;
1418	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1419	if (VBOX_SUCCESS(rc))
1420	{
1421	/*
1422	* Make shadow PTE entry.
1423	*/
1424	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1425	SHWPTE PteDst;
1426	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1427	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1428	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1429	{
1430	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1431	PteDst.n.u1Write = 0;
1432	else
1433	PteDst.u = 0;
1434	}
1435	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1436	# ifdef PGMPOOL_WITH_USER_TRACKING
1437	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1438	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1439	# endif
1440	pPTDst->a[iPTDst] = PteDst;
1441
1442
1443	# ifdef PGM_SYNC_DIRTY_BIT
1444	/*
1445	* If the page is not flagged as dirty and is writable, then make it read-only
1446	* at PD level, so we can set the dirty bit when the page is modified.
1447	*
1448	* ASSUMES that page access handlers are implemented on page table entry level.
1449	* Thus we will first catch the dirty access and set PDE.D and restart. If
1450	* there is an access handler, we'll trap again and let it work on the problem.
1451	*/
1452	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1453	* As for invlpg, it simply frees the whole shadow PT.
1454	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1455	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1456	{
1457	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1458	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1459	PdeDst.n.u1Write = 0;
1460	}
1461	else
1462	{
1463	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1464	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1465	}
1466	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1467	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1468	# else /* PAE */
1469	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1470	# endif
1471	# endif /* PGM_SYNC_DIRTY_BIT */
1472	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1473	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1474	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1475	}
1476	else
1477	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1478	}
1479	return VINF_SUCCESS;
1480	}
1481	# ifdef PGM_SYNC_ACCESSED_BIT
1482	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1483	#endif
1484	}
1485	else
1486	{
1487	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1488	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1489	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1490	}
1491
1492	/*
1493	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1494	* Yea, I'm lazy.
1495	*/
1496	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1497	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1498	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1499	# else /* PAE */
1500	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1501	# endif
1502	PGM_INVL_GUEST_TLBS();
1503	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1504
1505	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1506
1507	# ifdef PGM_SYNC_N_PAGES
1508	/*
1509	* Get the shadow PDE, find the shadow page table in the pool.
1510	*/
1511	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1512	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1513	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1514	# else /* PAE */
1515	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1516	# endif
1517	Assert(PdeDst.n.u1Present);
1518	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1519	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1520
1521	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1522	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1523	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1524	# else
1525	const unsigned offPTSrc = 0;
1526	# endif
1527
1528	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1529	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1530	{
1531	/*
1532	* This code path is currently only taken when the caller is PGMTrap0eHandler
1533	* for non-present pages!
1534	*
1535	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1536	* deal with locality.
1537	*/
1538	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1539	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1540	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1541	iPTDst = 0;
1542	else
1543	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1544	for (; iPTDst < iPTDstEnd; iPTDst++)
1545	{
1546	if (!pPTDst->a[iPTDst].n.u1Present)
1547	{
1548	GSTPTE PteSrc;
1549
1550	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1551
1552	/* Fake the page table entry */
1553	PteSrc.u = GCPtrCurPage;
1554	PteSrc.n.u1Present = 1;
1555	PteSrc.n.u1Dirty = 1;
1556	PteSrc.n.u1Accessed = 1;
1557	PteSrc.n.u1Write = 1;
1558	PteSrc.n.u1User = 1;
1559
1560	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1561
1562	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1563	GCPtrCurPage, PteSrc.n.u1Present,
1564	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1565	PteSrc.n.u1User & PdeSrc.n.u1User,
1566	(uint64_t)PteSrc.u,
1567	(uint64_t)pPTDst->a[iPTDst].u,
1568	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1569	}
1570	}
1571	}
1572	else
1573	# endif /* PGM_SYNC_N_PAGES */
1574	{
1575	GSTPTE PteSrc;
1576	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1577	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1578
1579	/* Fake the page table entry */
1580	PteSrc.u = GCPtrCurPage;
1581	PteSrc.n.u1Present = 1;
1582	PteSrc.n.u1Dirty = 1;
1583	PteSrc.n.u1Accessed = 1;
1584	PteSrc.n.u1Write = 1;
1585	PteSrc.n.u1User = 1;
1586	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1587
1588	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1589	GCPtrPage, PteSrc.n.u1Present,
1590	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1591	PteSrc.n.u1User & PdeSrc.n.u1User,
1592	(uint64_t)PteSrc.u,
1593	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1594	}
1595	return VINF_SUCCESS;
1596
1597	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1598	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1599	return VERR_INTERNAL_ERROR;
1600	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1601	}
1602
1603
1604
1605	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1606
1607	# ifdef PGM_SYNC_DIRTY_BIT
1608
1609	/**
1610	* Investigate page fault and handle write protection page faults caused by
1611	* dirty bit tracking.
1612	*
1613	* @returns VBox status code.
1614	* @param pVM VM handle.
1615	* @param uErr Page fault error code.
1616	* @param pPdeDst Shadow page directory entry.
1617	* @param pPdeSrc Guest page directory entry.
1618	* @param GCPtrPage Guest context page address.
1619	*/
1620	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1621	{
1622	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1623	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1624	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1625
1626	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1627	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1628
1629	/*
1630	* Real page fault?
1631	*/
1632	if ( (uErr & X86_TRAP_PF_RSVD)
1633	\|\| !pPdeSrc->n.u1Present
1634	# if PGM_WITH_NX(PGM_GST_TYPE)
1635	\|\| ((uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1636	# endif
1637	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1638	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1639	{
1640	# ifdef IN_GC
1641	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1642	# endif
1643	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1644	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1645
1646	if (pPdeSrc->n.u1Present)
1647	{
1648	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1649	* See the 2nd case below as well.
1650	*/
1651	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1652	{
1653	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1654	}
1655	else
1656	{
1657	/*
1658	* Map the guest page table.
1659	*/
1660	PGSTPT pPTSrc;
1661	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1662	if (VBOX_SUCCESS(rc))
1663	{
1664	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1665	const GSTPTE PteSrc = *pPteSrc;
1666	if (pPteSrc->n.u1Present)
1667	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1668	}
1669	AssertRC(rc);
1670	}
1671	}
1672	return VINF_EM_RAW_GUEST_TRAP;
1673	}
1674
1675	/*
1676	* First check the easy case where the page directory has been marked read-only to track
1677	* the dirty bit of an emulated BIG page
1678	*/
1679	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1680	{
1681	/* Mark guest page directory as accessed */
1682	pPdeSrc->b.u1Accessed = 1;
1683
1684	/*
1685	* Only write protection page faults are relevant here.
1686	*/
1687	if (fWriteFault)
1688	{
1689	/* Mark guest page directory as dirty (BIG page only). */
1690	pPdeSrc->b.u1Dirty = 1;
1691
1692	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1693	{
1694	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1695
1696	Assert(pPdeSrc->b.u1Write);
1697
1698	pPdeDst->n.u1Write = 1;
1699	pPdeDst->n.u1Accessed = 1;
1700	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1701	PGM_INVL_BIG_PG(GCPtrPage);
1702	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1703	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1704	}
1705	}
1706	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1707	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1708	}
1709	/* else: 4KB page table */
1710
1711	/*
1712	* Map the guest page table.
1713	*/
1714	PGSTPT pPTSrc;
1715	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1716	if (VBOX_SUCCESS(rc))
1717	{
1718	/*
1719	* Real page fault?
1720	*/
1721	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1722	const GSTPTE PteSrc = *pPteSrc;
1723	if ( !PteSrc.n.u1Present
1724	# if PGM_WITH_NX(PGM_GST_TYPE)
1725	\|\| ((uErr & X86_TRAP_PF_ID) && !PteSrc.n.u1NoExecute)
1726	# endif
1727	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1728	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1729	)
1730	{
1731	# ifdef IN_GC
1732	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1733	# endif
1734	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1735	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1736
1737	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1738	* See the 2nd case above as well.
1739	*/
1740	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1741	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1742
1743	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1744	return VINF_EM_RAW_GUEST_TRAP;
1745	}
1746	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1747
1748	/*
1749	* Set the accessed bits in the page directory and the page table.
1750	*/
1751	pPdeSrc->n.u1Accessed = 1;
1752	pPteSrc->n.u1Accessed = 1;
1753
1754	/*
1755	* Only write protection page faults are relevant here.
1756	*/
1757	if (fWriteFault)
1758	{
1759	/* Write access, so mark guest entry as dirty. */
1760	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1761	if (!pPteSrc->n.u1Dirty)
1762	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1763	else
1764	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1765	# endif
1766	pPteSrc->n.u1Dirty = 1;
1767
1768	if (pPdeDst->n.u1Present)
1769	{
1770	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1771	* Our individual shadow handlers will provide more information and force a fatal exit.
1772	*/
1773	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1774	{
1775	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1776	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1777	return VINF_SUCCESS;
1778	}
1779
1780	/*
1781	* Map shadow page table.
1782	*/
1783	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1784	if (pShwPage)
1785	{
1786	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1787	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1788	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1789	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1790	{
1791	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1792	# ifdef VBOX_STRICT
1793	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1794	if (pPage)
1795	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1796	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1797	# endif
1798	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1799
1800	Assert(pPteSrc->n.u1Write);
1801
1802	pPteDst->n.u1Write = 1;
1803	pPteDst->n.u1Dirty = 1;
1804	pPteDst->n.u1Accessed = 1;
1805	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1806	PGM_INVL_PG(GCPtrPage);
1807
1808	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1809	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1810	}
1811	}
1812	else
1813	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1814	}
1815	}
1816	/** @todo Optimize accessed bit emulation? */
1817	# ifdef VBOX_STRICT
1818	/*
1819	* Sanity check.
1820	*/
1821	else if ( !pPteSrc->n.u1Dirty
1822	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1823	&& pPdeDst->n.u1Present)
1824	{
1825	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1826	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1827	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1828	if ( pPteDst->n.u1Present
1829	&& pPteDst->n.u1Write)
1830	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1831	}
1832	# endif /* VBOX_STRICT */
1833	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1834	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1835	}
1836	AssertRC(rc);
1837	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1838	return rc;
1839	}
1840
1841	# endif
1842
1843	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1844
1845
1846	/**
1847	* Sync a shadow page table.
1848	*
1849	* The shadow page table is not present. This includes the case where
1850	* there is a conflict with a mapping.
1851	*
1852	* @returns VBox status code.
1853	* @param pVM VM handle.
1854	* @param iPD Page directory index.
1855	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1856	* Assume this is a temporary mapping.
1857	* @param GCPtrPage GC Pointer of the page that caused the fault
1858	*/
1859	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1860	{
1861	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1862	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1863	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1864
1865	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1866	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1867
1868	/*
1869	* Validate input a little bit.
1870	*/
1871	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1872	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1873	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1874	# else
1875	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1876	# endif
1877	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1878	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1879	SHWPDE PdeDst = *pPdeDst;
1880
1881	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1882	/*
1883	* Check for conflicts.
1884	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1885	* HC: Simply resolve the conflict.
1886	*/
1887	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1888	{
1889	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1890	# ifndef IN_RING3
1891	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1892	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1893	return VERR_ADDRESS_CONFLICT;
1894	# else
1895	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1896	Assert(pMapping);
1897	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1898	if (VBOX_FAILURE(rc))
1899	{
1900	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1901	return rc;
1902	}
1903	PdeDst = *pPdeDst;
1904	# endif
1905	}
1906	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1907	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1908	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1909	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1910	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1911
1912	/*
1913	* Sync page directory entry.
1914	*/
1915	int rc = VINF_SUCCESS;
1916	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1917	if (PdeSrc.n.u1Present)
1918	{
1919	/*
1920	* Allocate & map the page table.
1921	*/
1922	PSHWPT pPTDst;
1923	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1924	PPGMPOOLPAGE pShwPage;
1925	RTGCPHYS GCPhys;
1926	if (fPageTable)
1927	{
1928	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1929	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1930	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1931	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1932	# endif
1933	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1934	}
1935	else
1936	{
1937	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1938	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1939	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1940	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1941	# endif
1942	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1943	}
1944	if (rc == VINF_SUCCESS)
1945	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1946	else if (rc == VINF_PGM_CACHED_PAGE)
1947	{
1948	/*
1949	* The PT was cached, just hook it up.
1950	*/
1951	if (fPageTable)
1952	PdeDst.u = pShwPage->Core.Key
1953	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1954	else
1955	{
1956	PdeDst.u = pShwPage->Core.Key
1957	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
1958	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
1959	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1960	{
1961	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1962	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1963	PdeDst.b.u1Write = 0;
1964	}
1965	# endif
1966	}
1967	*pPdeDst = PdeDst;
1968	return VINF_SUCCESS;
1969	}
1970	else if (rc == VERR_PGM_POOL_FLUSHED)
1971	return VINF_PGM_SYNC_CR3;
1972	else
1973	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
1974	PdeDst.u &= X86_PDE_AVL_MASK;
1975	PdeDst.u \|= pShwPage->Core.Key;
1976
1977	# ifdef PGM_SYNC_DIRTY_BIT
1978	/*
1979	* Page directory has been accessed (this is a fault situation, remember).
1980	*/
1981	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
1982	# endif
1983	if (fPageTable)
1984	{
1985	/*
1986	* Page table - 4KB.
1987	*
1988	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
1989	*/
1990	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
1991	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
1992	PGSTPT pPTSrc;
1993	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1994	if (VBOX_SUCCESS(rc))
1995	{
1996	/*
1997	* Start by syncing the page directory entry so CSAM's TLB trick works.
1998	*/
1999	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2000	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2001	*pPdeDst = PdeDst;
2002
2003	/*
2004	* Directory/page user or supervisor privilege: (same goes for read/write)
2005	*
2006	* Directory Page Combined
2007	* U/S U/S U/S
2008	* 0 0 0
2009	* 0 1 0
2010	* 1 0 0
2011	* 1 1 1
2012	*
2013	* Simple AND operation. Table listed for completeness.
2014	*
2015	*/
2016	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2017	# ifdef PGM_SYNC_N_PAGES
2018	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2019	unsigned iPTDst = iPTBase;
2020	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2021	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2022	iPTDst = 0;
2023	else
2024	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2025	# else /* !PGM_SYNC_N_PAGES */
2026	unsigned iPTDst = 0;
2027	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2028	# endif /* !PGM_SYNC_N_PAGES */
2029	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2030	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2031	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2032	# else
2033	const unsigned offPTSrc = 0;
2034	# endif
2035	for (; iPTDst < iPTDstEnd; iPTDst++)
2036	{
2037	const unsigned iPTSrc = iPTDst + offPTSrc;
2038	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2039
2040	if (PteSrc.n.u1Present) /* we've already cleared it above */
2041	{
2042	# ifndef IN_RING0
2043	/*
2044	* Assuming kernel code will be marked as supervisor - and not as user level
2045	* and executed using a conforming code selector - And marked as readonly.
2046	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2047	*/
2048	PPGMPAGE pPage;
2049	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2050	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2051	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2052	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2053	)
2054	# endif
2055	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2056	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2057	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2058	PteSrc.n.u1Present,
2059	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2060	PteSrc.n.u1User & PdeSrc.n.u1User,
2061	(uint64_t)PteSrc.u,
2062	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2063	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2064	}
2065	} /* for PTEs */
2066	}
2067	}
2068	else
2069	{
2070	/*
2071	* Big page - 2/4MB.
2072	*
2073	* We'll walk the ram range list in parallel and optimize lookups.
2074	* We will only sync on shadow page table at a time.
2075	*/
2076	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2077
2078	/**
2079	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2080	*/
2081
2082	/*
2083	* Start by syncing the page directory entry.
2084	*/
2085	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2086	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2087
2088	# ifdef PGM_SYNC_DIRTY_BIT
2089	/*
2090	* If the page is not flagged as dirty and is writable, then make it read-only
2091	* at PD level, so we can set the dirty bit when the page is modified.
2092	*
2093	* ASSUMES that page access handlers are implemented on page table entry level.
2094	* Thus we will first catch the dirty access and set PDE.D and restart. If
2095	* there is an access handler, we'll trap again and let it work on the problem.
2096	*/
2097	/** @todo move the above stuff to a section in the PGM documentation. */
2098	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2099	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2100	{
2101	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2102	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2103	PdeDst.b.u1Write = 0;
2104	}
2105	# endif /* PGM_SYNC_DIRTY_BIT */
2106	*pPdeDst = PdeDst;
2107
2108	/*
2109	* Fill the shadow page table.
2110	*/
2111	/* Get address and flags from the source PDE. */
2112	SHWPTE PteDstBase;
2113	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2114
2115	/* Loop thru the entries in the shadow PT. */
2116	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2117	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2118	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2119	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2120	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2121	unsigned iPTDst = 0;
2122	while (iPTDst < ELEMENTS(pPTDst->a))
2123	{
2124	/* Advance ram range list. */
2125	while (pRam && GCPhys > pRam->GCPhysLast)
2126	pRam = CTXALLSUFF(pRam->pNext);
2127	if (pRam && GCPhys >= pRam->GCPhys)
2128	{
2129	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2130	do
2131	{
2132	/* Make shadow PTE. */
2133	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2134	SHWPTE PteDst;
2135
2136	/* Make sure the RAM has already been allocated. */
2137	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2138	{
2139	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2140	{
2141	# ifdef IN_RING3
2142	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2143	# else
2144	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2145	# endif
2146	if (rc != VINF_SUCCESS)
2147	return rc;
2148	}
2149	}
2150
2151	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2152	{
2153	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2154	{
2155	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2156	PteDst.n.u1Write = 0;
2157	}
2158	else
2159	PteDst.u = 0;
2160	}
2161	# ifndef IN_RING0
2162	/*
2163	* Assuming kernel code will be marked as supervisor and not as user level and executed
2164	* using a conforming code selector. Don't check for readonly, as that implies the whole
2165	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2166	*/
2167	else if ( !PdeSrc.n.u1User
2168	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2169	PteDst.u = 0;
2170	# endif
2171	else
2172	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2173	# ifdef PGMPOOL_WITH_USER_TRACKING
2174	if (PteDst.n.u1Present)
2175	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2176	# endif
2177	/* commit it */
2178	pPTDst->a[iPTDst] = PteDst;
2179	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2180	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2181	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2182
2183	/* advance */
2184	GCPhys += PAGE_SIZE;
2185	iHCPage++;
2186	iPTDst++;
2187	} while ( iPTDst < ELEMENTS(pPTDst->a)
2188	&& GCPhys <= pRam->GCPhysLast);
2189	}
2190	else if (pRam)
2191	{
2192	Log(("Invalid pages at %VGp\n", GCPhys));
2193	do
2194	{
2195	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2196	GCPhys += PAGE_SIZE;
2197	iPTDst++;
2198	} while ( iPTDst < ELEMENTS(pPTDst->a)
2199	&& GCPhys < pRam->GCPhys);
2200	}
2201	else
2202	{
2203	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2204	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2205	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2206	}
2207	} /* while more PTEs */
2208	} /* 4KB / 4MB */
2209	}
2210	else
2211	AssertRelease(!PdeDst.n.u1Present);
2212
2213	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2214	# ifdef IN_GC
2215	if (VBOX_FAILURE(rc))
2216	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2217	# endif
2218	return rc;
2219
2220	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2221
2222	int rc = VINF_SUCCESS;
2223
2224	/*
2225	* Validate input a little bit.
2226	*/
2227	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2228	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2229	# else
2230	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2231	# endif
2232	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2233	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2234	SHWPDE PdeDst = *pPdeDst;
2235
2236	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2237	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2238
2239	GSTPDE PdeSrc;
2240	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2241	PdeSrc.n.u1Present = 1;
2242	PdeSrc.n.u1Write = 1;
2243	PdeSrc.n.u1Accessed = 1;
2244	PdeSrc.n.u1User = 1;
2245
2246	/*
2247	* Allocate & map the page table.
2248	*/
2249	PSHWPT pPTDst;
2250	PPGMPOOLPAGE pShwPage;
2251	RTGCPHYS GCPhys;
2252
2253	/* Virtual address = physical address */
2254	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2255	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2256
2257	if ( rc == VINF_SUCCESS
2258	\|\| rc == VINF_PGM_CACHED_PAGE)
2259	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2260	else
2261	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2262
2263	PdeDst.u &= X86_PDE_AVL_MASK;
2264	PdeDst.u \|= pShwPage->Core.Key;
2265	PdeDst.n.u1Present = 1;
2266	*pPdeDst = PdeDst;
2267
2268	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2269	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2270	return rc;
2271
2272	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2273	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2274	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2275	return VERR_INTERNAL_ERROR;
2276	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2277	}
2278
2279
2280
2281	/**
2282	* Prefetch a page/set of pages.
2283	*
2284	* Typically used to sync commonly used pages before entering raw mode
2285	* after a CR3 reload.
2286	*
2287	* @returns VBox status code.
2288	* @param pVM VM handle.
2289	* @param GCPtrPage Page to invalidate.
2290	*/
2291	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2292	{
2293	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2294	/*
2295	* Check that all Guest levels thru the PDE are present, getting the
2296	* PD and PDE in the processes.
2297	*/
2298	int rc = VINF_SUCCESS;
2299	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2300	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2301	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2302	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2303	# else /* PAE */
2304	unsigned iPDSrc;
2305	PGSTPD pPDSrc = pgmGstGetPaePDPt(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2306	# endif
2307	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2308	# else
2309	PGSTPD pPDSrc = NULL;
2310	const unsigned iPDSrc = 0;
2311	GSTPDE PdeSrc;
2312
2313	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2314	PdeSrc.n.u1Present = 1;
2315	PdeSrc.n.u1Write = 1;
2316	PdeSrc.n.u1Accessed = 1;
2317	PdeSrc.n.u1User = 1;
2318	# endif
2319
2320	# ifdef PGM_SYNC_ACCESSED_BIT
2321	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2322	# else
2323	if (PdeSrc.n.u1Present)
2324	# endif
2325	{
2326	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2327	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2328	# else
2329	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2330	# endif
2331	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2332	{
2333	if (!PdeDst.n.u1Present)
2334	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2335	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2336	else
2337	{
2338	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2339	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2340	* makes no sense to prefetch more than one page.
2341	*/
2342	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2343	if (VBOX_SUCCESS(rc))
2344	rc = VINF_SUCCESS;
2345	}
2346	}
2347	}
2348	return rc;
2349
2350	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2351
2352	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2353	return VERR_INTERNAL_ERROR;
2354	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2355	}
2356
2357
2358
2359
2360	/**
2361	* Syncs a page during a PGMVerifyAccess() call.
2362	*
2363	* @returns VBox status code (informational included).
2364	* @param GCPtrPage The address of the page to sync.
2365	* @param fPage The effective guest page flags.
2366	* @param uErr The trap error code.
2367	*/
2368	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2369	{
2370	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2371
2372	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2373
2374	# ifndef IN_RING0
2375	if (!(fPage & X86_PTE_US))
2376	{
2377	/*
2378	* Mark this page as safe.
2379	*/
2380	/** @todo not correct for pages that contain both code and data!! */
2381	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2382	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2383	}
2384	# endif
2385	/*
2386	* Get guest PD and index.
2387	*/
2388
2389	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2390	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2391	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2392	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2393	# else /* PAE */
2394	unsigned iPDSrc;
2395	PGSTPD pPDSrc = pgmGstGetPaePDPt(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2396	# endif
2397	# else
2398	PGSTPD pPDSrc = NULL;
2399	const unsigned iPDSrc = 0;
2400	# endif
2401	int rc = VINF_SUCCESS;
2402
2403	/*
2404	* First check if the shadow pd is present.
2405	*/
2406	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2407	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2408	# else
2409	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2410	# endif
2411	if (!pPdeDst->n.u1Present)
2412	{
2413	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2414	AssertRC(rc);
2415	if (rc != VINF_SUCCESS)
2416	return rc;
2417	}
2418
2419	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2420	/* Check for dirty bit fault */
2421	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2422	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2423	Log(("PGMVerifyAccess: success (dirty)\n"));
2424	else
2425	{
2426	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2427	#else
2428	{
2429	GSTPDE PdeSrc;
2430	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2431	PdeSrc.n.u1Present = 1;
2432	PdeSrc.n.u1Write = 1;
2433	PdeSrc.n.u1Accessed = 1;
2434	PdeSrc.n.u1User = 1;
2435
2436	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2437	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2438	if (uErr & X86_TRAP_PF_US)
2439	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2440	else /* supervisor */
2441	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2442
2443	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2444	if (VBOX_SUCCESS(rc))
2445	{
2446	/* Page was successfully synced */
2447	Log2(("PGMVerifyAccess: success (sync)\n"));
2448	rc = VINF_SUCCESS;
2449	}
2450	else
2451	{
2452	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2453	return VINF_EM_RAW_GUEST_TRAP;
2454	}
2455	}
2456	return rc;
2457
2458	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2459
2460	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2461	return VERR_INTERNAL_ERROR;
2462	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2463	}
2464
2465
2466	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2467	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2468	/**
2469	* Figures out which kind of shadow page this guest PDE warrants.
2470	*
2471	* @returns Shadow page kind.
2472	* @param pPdeSrc The guest PDE in question.
2473	* @param cr4 The current guest cr4 value.
2474	*/
2475	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2476	{
2477	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2478	return BTH_PGMPOOLKIND_PT_FOR_PT;
2479	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2480	//{
2481	// case 0:
2482	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2483	// case X86_PDE4M_RW:
2484	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2485	// case X86_PDE4M_US:
2486	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2487	// case X86_PDE4M_RW \| X86_PDE4M_US:
2488	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2489	# if 0
2490	// case X86_PDE4M_PAE_NX:
2491	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2492	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2493	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2494	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2495	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2496	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2497	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2498	# endif
2499	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2500	//}
2501	}
2502	# endif
2503	#endif
2504
2505	#undef MY_STAM_COUNTER_INC
2506	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2507
2508
2509	/**
2510	* Syncs the paging hierarchy starting at CR3.
2511	*
2512	* @returns VBox status code, no specials.
2513	* @param pVM The virtual machine.
2514	* @param cr0 Guest context CR0 register
2515	* @param cr3 Guest context CR3 register
2516	* @param cr4 Guest context CR4 register
2517	* @param fGlobal Including global page directories or not
2518	*/
2519	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2520	{
2521	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2522	fGlobal = true; /* Change this CR3 reload to be a global one. */
2523
2524	/*
2525	* Update page access handlers.
2526	* The virtual are always flushed, while the physical are only on demand.
2527	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2528	* have to look into that later because it will have a bad influence on the performance.
2529	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2530	* bird: Yes, but that won't work for aliases.
2531	*/
2532	/** @todo this MUST go away. See #1557. */
2533	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2534	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2535	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2536
2537	#ifdef PGMPOOL_WITH_MONITORING
2538	/*
2539	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2540	* Occationally we will have to clear all the shadow page tables because we wanted
2541	* to monitor a page which was mapped by too many shadowed page tables. This operation
2542	* sometimes refered to as a 'lightweight flush'.
2543	*/
2544	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2545	pgmPoolMonitorModifiedClearAll(pVM);
2546	else
2547	{
2548	# ifdef IN_RING3
2549	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2550	pgmPoolClearAll(pVM);
2551	# else
2552	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2553	return VINF_PGM_SYNC_CR3;
2554	# endif
2555	}
2556	#endif
2557
2558	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2559	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2560
2561	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2562	/*
2563	* Get page directory addresses.
2564	*/
2565	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2566	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2567	# else
2568	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2569	# endif
2570
2571	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2572	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2573	Assert(pPDSrc);
2574	# ifndef IN_GC
2575	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2576	# endif
2577	# endif
2578
2579	/*
2580	* Iterate the page directory.
2581	*/
2582	PPGMMAPPING pMapping;
2583	unsigned iPdNoMapping;
2584	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2585	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2586
2587	/* Only check mappings if they are supposed to be put into the shadow page table. */
2588	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2589	{
2590	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2591	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2592	}
2593	else
2594	{
2595	pMapping = 0;
2596	iPdNoMapping = ~0U;
2597	}
2598	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2599	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2600	{
2601	unsigned iPDSrc;
2602	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2603	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_PAE_ENTRIES];
2604	# else
2605	AssertFailed(); /* @todo */
2606	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2607	# endif
2608	PX86PDEPAE pPDEDst = &pPDPAE->a[0];
2609	PGSTPD pPDSrc = pgmGstGetPaePDPt(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2610
2611	if (pPDSrc == NULL)
2612	{
2613	/* PDPT not present */
2614	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 0;
2615	continue;
2616	}
2617	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2618	{
2619	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2620	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2621	{
2622	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2623	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2624	# else
2625	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2626	# endif
2627	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2628	if ( PdeSrc.n.u1Present
2629	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2630	{
2631	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2632	/*
2633	* Check for conflicts with GC mappings.
2634	*/
2635	if (iPD == iPdNoMapping)
2636	{
2637	if (pVM->pgm.s.fMappingsFixed)
2638	{
2639	/* It's fixed, just skip the mapping. */
2640	const unsigned cPTs = pMapping->cPTs;
2641	iPD += cPTs - 1;
2642	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2643	pMapping = pMapping->CTXALLSUFF(pNext);
2644	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2645	continue;
2646	}
2647	# ifdef IN_RING3
2648	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2649	if (VBOX_FAILURE(rc))
2650	return rc;
2651
2652	/*
2653	* Update iPdNoMapping and pMapping.
2654	*/
2655	pMapping = pVM->pgm.s.pMappingsR3;
2656	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2657	pMapping = pMapping->pNextR3;
2658	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2659	# else
2660	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2661	return VINF_PGM_SYNC_CR3;
2662	# endif
2663	}
2664	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2665	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2666	Assert(iPD != iPdNoMapping);
2667	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2668	/*
2669	* Sync page directory entry.
2670	*
2671	* The current approach is to allocated the page table but to set
2672	* the entry to not-present and postpone the page table synching till
2673	* it's actually used.
2674	*/
2675	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2676	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2677	# else
2678	const unsigned iPdShw = iPD; NOREF(iPdShw);
2679	# endif
2680	{
2681	SHWPDE PdeDst = *pPDEDst;
2682	if (PdeDst.n.u1Present)
2683	{
2684	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2685	RTGCPHYS GCPhys;
2686	if ( !PdeSrc.b.u1Size
2687	\|\| !(cr4 & X86_CR4_PSE))
2688	{
2689	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2690	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2691	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2692	GCPhys \|= i * (PAGE_SIZE / 2);
2693	# endif
2694	}
2695	else
2696	{
2697	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2698	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2699	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2700	GCPhys \|= i * X86_PAGE_2M_SIZE;
2701	# endif
2702	}
2703
2704	if ( pShwPage->GCPhys == GCPhys
2705	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2706	&& ( pShwPage->fCached
2707	\|\| ( !fGlobal
2708	&& ( false
2709	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2710	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2711	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2712	\|\| ( !pShwPage->fSeenNonGlobal
2713	&& (cr4 & X86_CR4_PGE))
2714	# endif
2715	)
2716	)
2717	)
2718	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2719	\|\| ( (cr4 & X86_CR4_PSE)
2720	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2721	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2722	)
2723	)
2724	{
2725	# ifdef VBOX_WITH_STATISTICS
2726	if ( !fGlobal
2727	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2728	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2729	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2730	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2731	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2732	else
2733	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2734	# endif /* VBOX_WITH_STATISTICS */
2735	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2736	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2737	//# ifdef PGMPOOL_WITH_CACHE
2738	// pgmPoolCacheUsed(pPool, pShwPage);
2739	//# endif
2740	}
2741	else
2742	{
2743	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2744	pPDEDst->u = 0;
2745	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2746	}
2747	}
2748	else
2749	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2750	pPDEDst++;
2751	}
2752	}
2753	else if (iPD != iPdNoMapping)
2754	{
2755	/*
2756	* Check if there is any page directory to mark not present here.
2757	*/
2758	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2759	const unsigned iPdShw = iPD; NOREF(iPdShw);
2760	# else
2761	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2762	# endif
2763	{
2764	if (pPDEDst->n.u1Present)
2765	{
2766	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2767	pPDEDst->u = 0;
2768	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2769	}
2770	pPDEDst++;
2771	}
2772	}
2773	else
2774	{
2775	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2776	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2777	const unsigned cPTs = pMapping->cPTs;
2778	if (pVM->pgm.s.fMappingsFixed)
2779	{
2780	/* It's fixed, just skip the mapping. */
2781	pMapping = pMapping->CTXALLSUFF(pNext);
2782	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2783	}
2784	else
2785	{
2786	/*
2787	* Check for conflicts for subsequent pagetables
2788	* and advance to the next mapping.
2789	*/
2790	iPdNoMapping = ~0U;
2791	unsigned iPT = cPTs;
2792	while (iPT-- > 1)
2793	{
2794	if ( pPDSrc->a[iPD + iPT].n.u1Present
2795	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2796	{
2797	# ifdef IN_RING3
2798	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2799	if (VBOX_FAILURE(rc))
2800	return rc;
2801
2802	/*
2803	* Update iPdNoMapping and pMapping.
2804	*/
2805	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2806	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2807	pMapping = pMapping->CTXALLSUFF(pNext);
2808	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2809	break;
2810	# else
2811	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2812	return VINF_PGM_SYNC_CR3;
2813	# endif
2814	}
2815	}
2816	if (iPdNoMapping == ~0U && pMapping)
2817	{
2818	pMapping = pMapping->CTXALLSUFF(pNext);
2819	if (pMapping)
2820	iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2821	}
2822	}
2823
2824	/* advance. */
2825	iPD += cPTs - 1;
2826	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2827	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2828	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2829	AssertFailed();
2830	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2831	}
2832
2833	} /* for iPD */
2834	} /* for each PDPTE (PAE) */
2835
2836	return VINF_SUCCESS;
2837
2838	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2839	//# error not implemented
2840	return VERR_INTERNAL_ERROR;
2841	#else /* guest real and protected mode */
2842	return VINF_SUCCESS;
2843	#endif
2844	}
2845
2846
2847
2848
2849	#ifdef VBOX_STRICT
2850	#ifdef IN_GC
2851	# undef AssertMsgFailed
2852	# define AssertMsgFailed Log
2853	#endif
2854	#ifdef IN_RING3
2855	# include <VBox/dbgf.h>
2856
2857	/**
2858	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2859	*
2860	* @returns VBox status code (VINF_SUCCESS).
2861	* @param pVM The VM handle.
2862	* @param cr3 The root of the hierarchy.
2863	* @param crr The cr4, only PAE and PSE is currently used.
2864	* @param fLongMode Set if long mode, false if not long mode.
2865	* @param cMaxDepth Number of levels to dump.
2866	* @param pHlp Pointer to the output functions.
2867	*/
2868	__BEGIN_DECLS
2869	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2870	__END_DECLS
2871
2872	#endif
2873
2874	/**
2875	* Checks that the shadow page table is in sync with the guest one.
2876	*
2877	* @returns The number of errors.
2878	* @param pVM The virtual machine.
2879	* @param cr3 Guest context CR3 register
2880	* @param cr4 Guest context CR4 register
2881	* @param GCPtr Where to start. Defaults to 0.
2882	* @param cb How much to check. Defaults to everything.
2883	*/
2884	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2885	{
2886	unsigned cErrors = 0;
2887
2888	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2889	PPGM pPGM = &pVM->pgm.s;
2890	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2891	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2892	RTHCPHYS HCPhys; /* general usage. */
2893	int rc;
2894
2895	/*
2896	* Check that the Guest CR3 and all it's mappings are correct.
2897	*/
2898	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2899	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2900	false);
2901	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2902	AssertRCReturn(rc, 1);
2903	HCPhys = NIL_RTHCPHYS;
2904	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2905	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2906	# ifdef IN_RING3
2907	RTGCPHYS GCPhys;
2908	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2909	AssertRCReturn(rc, 1);
2910	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2911	# endif
2912	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2913
2914	/*
2915	* Get and check the Shadow CR3.
2916	*/
2917	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2918	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2919	unsigned cPDEs = ELEMENTS(pPDDst->a);
2920	# else
2921	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2922	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2923	# endif
2924	if (cb != ~(RTGCUINTPTR)0)
2925	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2926
2927	/** @todo call the other two PGMAssert() functions. /
2928
2929	/*
2930	* Iterate the shadow page directory.
2931	*/
2932	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2933	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2934	cPDEs += iPDDst;
2935	for (;
2936	iPDDst < cPDEs;
2937	iPDDst++, GCPtr += _4G / cPDEs)
2938	{
2939	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2940	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2941	{
2942	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2943	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
2944	{
2945	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
2946	cErrors++;
2947	continue;
2948	}
2949	}
2950	else if ( (PdeDst.u & X86_PDE_P)
2951	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
2952	)
2953	{
2954	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
2955	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
2956	if (!pPoolPage)
2957	{
2958	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
2959	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
2960	cErrors++;
2961	continue;
2962	}
2963	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
2964
2965	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
2966	{
2967	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
2968	GCPtr, (uint64_t)PdeDst.u));
2969	cErrors++;
2970	}
2971
2972	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
2973	{
2974	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
2975	GCPtr, (uint64_t)PdeDst.u));
2976	cErrors++;
2977	}
2978
2979	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
2980	if (!PdeSrc.n.u1Present)
2981	{
2982	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
2983	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
2984	cErrors++;
2985	continue;
2986	}
2987
2988	if ( !PdeSrc.b.u1Size
2989	\|\| !(cr4 & X86_CR4_PSE))
2990	{
2991	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
2992	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2993	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2994	# endif
2995	}
2996	else
2997	{
2998	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
2999	{
3000	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3001	GCPtr, (uint64_t)PdeSrc.u));
3002	cErrors++;
3003	continue;
3004	}
3005	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3006	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3007	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3008	# endif
3009	}
3010
3011	if ( pPoolPage->enmKind
3012	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3013	{
3014	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3015	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3016	cErrors++;
3017	}
3018
3019	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3020	if (!pPhysPage)
3021	{
3022	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3023	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3024	cErrors++;
3025	continue;
3026	}
3027
3028	if (GCPhysGst != pPoolPage->GCPhys)
3029	{
3030	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3031	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3032	cErrors++;
3033	continue;
3034	}
3035
3036	if ( !PdeSrc.b.u1Size
3037	\|\| !(cr4 & X86_CR4_PSE))
3038	{
3039	/*
3040	* Page Table.
3041	*/
3042	const GSTPT *pPTSrc;
3043	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3044	if (VBOX_FAILURE(rc))
3045	{
3046	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3047	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3048	cErrors++;
3049	continue;
3050	}
3051	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3052	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3053	{
3054	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3055	// (This problem will go away when/if we shadow multiple CR3s.)
3056	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3057	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3058	cErrors++;
3059	continue;
3060	}
3061	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3062	{
3063	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3064	GCPtr, (uint64_t)PdeDst.u));
3065	cErrors++;
3066	continue;
3067	}
3068
3069	/* iterate the page table. */
3070	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3071	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3072	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3073	# else
3074	const unsigned offPTSrc = 0;
3075	# endif
3076	for (unsigned iPT = 0, off = 0;
3077	iPT < ELEMENTS(pPTDst->a);
3078	iPT++, off += PAGE_SIZE)
3079	{
3080	const SHWPTE PteDst = pPTDst->a[iPT];
3081
3082	/* skip not-present entries. */
3083	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3084	continue;
3085	Assert(PteDst.n.u1Present);
3086
3087	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3088	if (!PteSrc.n.u1Present)
3089	{
3090	#ifdef IN_RING3
3091	PGMAssertHandlerAndFlagsInSync(pVM);
3092	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3093	#endif
3094	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3095	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3096	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3097	cErrors++;
3098	continue;
3099	}
3100
3101	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3102	# if 1 /** @todo sync accessed bit properly... */
3103	fIgnoreFlags \|= X86_PTE_A;
3104	# endif
3105
3106	/* match the physical addresses */
3107	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3108	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3109
3110	# ifdef IN_RING3
3111	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3112	if (VBOX_FAILURE(rc))
3113	{
3114	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3115	{
3116	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3117	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3118	cErrors++;
3119	continue;
3120	}
3121	}
3122	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3123	{
3124	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3125	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3126	cErrors++;
3127	continue;
3128	}
3129	# endif
3130
3131	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3132	if (!pPhysPage)
3133	{
3134	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3135	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3136	{
3137	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3138	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3139	cErrors++;
3140	continue;
3141	}
3142	# endif
3143	if (PteDst.n.u1Write)
3144	{
3145	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3146	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3147	cErrors++;
3148	}
3149	fIgnoreFlags \|= X86_PTE_RW;
3150	}
3151	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3152	{
3153	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3154	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3155	cErrors++;
3156	continue;
3157	}
3158
3159	/* flags */
3160	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3161	{
3162	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3163	{
3164	if (PteDst.n.u1Write)
3165	{
3166	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3167	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3168	cErrors++;
3169	continue;
3170	}
3171	fIgnoreFlags \|= X86_PTE_RW;
3172	}
3173	else
3174	{
3175	if (PteDst.n.u1Present)
3176	{
3177	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3178	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3179	cErrors++;
3180	continue;
3181	}
3182	fIgnoreFlags \|= X86_PTE_P;
3183	}
3184	}
3185	else
3186	{
3187	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3188	{
3189	if (PteDst.n.u1Write)
3190	{
3191	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3192	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3193	cErrors++;
3194	continue;
3195	}
3196	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3197	{
3198	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3199	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3200	cErrors++;
3201	continue;
3202	}
3203	if (PteDst.n.u1Dirty)
3204	{
3205	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3206	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3207	cErrors++;
3208	}
3209	# if 0 /** @todo sync access bit properly... */
3210	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3211	{
3212	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3213	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3214	cErrors++;
3215	}
3216	fIgnoreFlags \|= X86_PTE_RW;
3217	# else
3218	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3219	# endif
3220	}
3221	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3222	{
3223	/* access bit emulation (not implemented). */
3224	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3225	{
3226	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3227	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3228	cErrors++;
3229	continue;
3230	}
3231	if (!PteDst.n.u1Accessed)
3232	{
3233	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3234	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3235	cErrors++;
3236	}
3237	fIgnoreFlags \|= X86_PTE_P;
3238	}
3239	# ifdef DEBUG_sandervl
3240	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3241	# endif
3242	}
3243
3244	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3245	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3246	)
3247	{
3248	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3249	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3250	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3251	cErrors++;
3252	continue;
3253	}
3254	} /* foreach PTE */
3255	}
3256	else
3257	{
3258	/*
3259	* Big Page.
3260	*/
3261	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3262	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3263	{
3264	if (PdeDst.n.u1Write)
3265	{
3266	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3267	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3268	cErrors++;
3269	continue;
3270	}
3271	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3272	{
3273	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3274	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3275	cErrors++;
3276	continue;
3277	}
3278	# if 0 /** @todo sync access bit properly... */
3279	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3280	{
3281	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3282	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3283	cErrors++;
3284	}
3285	fIgnoreFlags \|= X86_PTE_RW;
3286	# else
3287	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3288	# endif
3289	}
3290	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3291	{
3292	/* access bit emulation (not implemented). */
3293	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3294	{
3295	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3296	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3297	cErrors++;
3298	continue;
3299	}
3300	if (!PdeDst.n.u1Accessed)
3301	{
3302	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3303	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3304	cErrors++;
3305	}
3306	fIgnoreFlags \|= X86_PTE_P;
3307	}
3308
3309	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3310	{
3311	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3312	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3313	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3314	cErrors++;
3315	}
3316
3317	/* iterate the page table. */
3318	for (unsigned iPT = 0, off = 0;
3319	iPT < ELEMENTS(pPTDst->a);
3320	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3321	{
3322	const SHWPTE PteDst = pPTDst->a[iPT];
3323
3324	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3325	{
3326	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3327	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3328	cErrors++;
3329	}
3330
3331	/* skip not-present entries. */
3332	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3333	continue;
3334
3335	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3336
3337	/* match the physical addresses */
3338	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3339
3340	# ifdef IN_RING3
3341	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3342	if (VBOX_FAILURE(rc))
3343	{
3344	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3345	{
3346	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3347	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3348	cErrors++;
3349	}
3350	}
3351	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3352	{
3353	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3354	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3355	cErrors++;
3356	continue;
3357	}
3358	# endif
3359
3360	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3361	if (!pPhysPage)
3362	{
3363	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3364	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3365	{
3366	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3367	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3368	cErrors++;
3369	continue;
3370	}
3371	# endif
3372	if (PteDst.n.u1Write)
3373	{
3374	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3375	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3376	cErrors++;
3377	}
3378	fIgnoreFlags \|= X86_PTE_RW;
3379	}
3380	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3381	{
3382	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3383	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3384	cErrors++;
3385	continue;
3386	}
3387
3388	/* flags */
3389	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3390	{
3391	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3392	{
3393	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3394	{
3395	if (PteDst.n.u1Write)
3396	{
3397	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3398	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3399	cErrors++;
3400	continue;
3401	}
3402	fIgnoreFlags \|= X86_PTE_RW;
3403	}
3404	}
3405	else
3406	{
3407	if (PteDst.n.u1Present)
3408	{
3409	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3410	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3411	cErrors++;
3412	continue;
3413	}
3414	fIgnoreFlags \|= X86_PTE_P;
3415	}
3416	}
3417
3418	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3419	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3420	)
3421	{
3422	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3423	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3424	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3425	cErrors++;
3426	continue;
3427	}
3428	} /* foreach PTE */
3429	}
3430	}
3431	/* not present */
3432
3433	} /* forearch PDE */
3434
3435	# ifdef DEBUG
3436	if (cErrors)
3437	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3438	# endif
3439
3440	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3441	//# error not implemented
3442
3443
3444	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3445	//# error not implemented
3446
3447	/#else: guest real and protected mode /
3448	#endif
3449	return cErrors;
3450	}
3451	#endif /* VBOX_STRICT */
3452

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7715

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