PGMAllBth.h@ 7730

Last change on this file since 7730 was 7730, checked in by vboxsync, 17 years ago
Added CPUMSet/GetGuestEFER. Corrected NX bit handling.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 152.4 KB

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1	/* $Id: PGMAllBth.h 7730 2008-04-03 16:30:35Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
42	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
43	#error "Invalid combination; PAE guest implies PAE shadow"
44	#endif
45
46	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
47	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
48	#error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
53	#error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
57	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
58	#error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
59	#endif
60
61	/**
62	* #PF Handler for raw-mode guest execution.
63	*
64	* @returns VBox status code (appropriate for trap handling and GC return).
65	* @param pVM VM Handle.
66	* @param uErr The trap error code.
67	* @param pRegFrame Trap register frame.
68	* @param pvFault The fault address.
69	*/
70	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
71	{
72	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
73
74	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
75	/*
76	* Hide the instruction fetch trap indicator for now.
77	*/
78	/** @todo NXE will change this and we must fix NXE in the switcher too! */
79	if (uErr & X86_TRAP_PF_ID)
80	{
81	uErr &= ~X86_TRAP_PF_ID;
82	TRPMSetErrorCode(pVM, uErr);
83	}
84	# endif
85
86	/*
87	* Get PDs.
88	*/
89	int rc;
90	# if PGM_WITH_PAGING(PGM_GST_TYPE)
91	# if PGM_GST_TYPE == PGM_TYPE_32BIT
92	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
93	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
94	# else /* PAE */
95	unsigned iPDSrc;
96	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
97	# endif
98	# else
99	PGSTPD pPDSrc = NULL;
100	const unsigned iPDSrc = 0;
101	# endif
102
103	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
104	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
105	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
106	# else /* PAE */
107	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
108	# endif
109
110	# if PGM_WITH_PAGING(PGM_GST_TYPE)
111	# ifdef PGM_SYNC_DIRTY_BIT
112	/*
113	* If we successfully correct the write protection fault due to dirty bit
114	* tracking, or this page fault is a genuine one, then return immediately.
115	*/
116	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
117	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
118	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
119	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
120	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
121	{
122	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
123	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
124	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
125	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
126	}
127	# endif
128
129	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
130	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
131
132	/*
133	* A common case is the not-present error caused by lazy page table syncing.
134	*
135	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
136	* so we can safely assume that the shadow PT is present when calling SyncPage later.
137	*
138	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
139	* of mapping conflict and defer to SyncCR3 in R3.
140	* (Again, we do NOT support access handlers for non-present guest pages.)
141	*
142	*/
143	# if PGM_WITH_PAGING(PGM_GST_TYPE)
144	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
145	# else
146	GSTPDE PdeSrc;
147	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
148	PdeSrc.n.u1Present = 1;
149	PdeSrc.n.u1Write = 1;
150	PdeSrc.n.u1Accessed = 1;
151	PdeSrc.n.u1User = 1;
152	# endif
153	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
154	&& !pPDDst->a[iPDDst].n.u1Present
155	&& PdeSrc.n.u1Present
156	)
157
158	{
159	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
160	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
161	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
162	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
163	if (VBOX_SUCCESS(rc))
164	{
165	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
166	return rc;
167	}
168	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
169	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
170	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
171	return VINF_PGM_SYNC_CR3;
172	}
173
174	# if PGM_WITH_PAGING(PGM_GST_TYPE)
175	/*
176	* Check if this address is within any of our mappings.
177	*
178	* This is very fast and it's gonna save us a bit of effort below and prevent
179	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
180	* (BTW, it's impossible to have physical access handlers in a mapping.)
181	*/
182	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
183	{
184	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
185	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
186	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
187	{
188	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
189	break;
190	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
191	{
192	/*
193	* The first thing we check is if we've got an undetected conflict.
194	*/
195	if (!pVM->pgm.s.fMappingsFixed)
196	{
197	unsigned iPT = pMapping->cPTs;
198	while (iPT-- > 0)
199	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
200	{
201	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
202	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
203	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
204	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
205	return VINF_PGM_SYNC_CR3;
206	}
207	}
208
209	/*
210	* Check if the fault address is in a virtual page access handler range.
211	*/
212	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
213	if ( pCur
214	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
215	&& uErr & X86_TRAP_PF_RW)
216	{
217	# ifdef IN_GC
218	STAM_PROFILE_START(&pCur->Stat, h);
219	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
220	STAM_PROFILE_STOP(&pCur->Stat, h);
221	# else
222	AssertFailed();
223	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
224	# endif
225	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
226	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
227	return rc;
228	}
229
230	/*
231	* Pretend we're not here and let the guest handle the trap.
232	*/
233	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
234	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
235	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
236	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
237	return VINF_EM_RAW_GUEST_TRAP;
238	}
239	}
240	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
241	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
242	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
243
244	/*
245	* Check if this fault address is flagged for special treatment,
246	* which means we'll have to figure out the physical address and
247	* check flags associated with it.
248	*
249	* ASSUME that we can limit any special access handling to pages
250	* in page tables which the guest believes to be present.
251	*/
252	if (PdeSrc.n.u1Present)
253	{
254	RTGCPHYS GCPhys = NIL_RTGCPHYS;
255
256	# if PGM_WITH_PAGING(PGM_GST_TYPE)
257	uint32_t cr4 = CPUMGetGuestCR4(pVM);
258	if ( PdeSrc.b.u1Size
259	&& (cr4 & X86_CR4_PSE))
260	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
261	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
262	else
263	{
264	PX86PT pPTSrc;
265	# ifdef IN_GC
266	rc = PGMGCDynMapGCPage(pVM, PdeSrc.u & GST_PDE_PG_MASK, (void **)&pPTSrc);
267	# else
268	pPTSrc = (PX86PT)MMPhysGCPhys2HCVirt(pVM, PdeSrc.u & GST_PDE_PG_MASK, sizeof(*pPTSrc));
269	if (pPTSrc == 0)
270	rc = VERR_PGM_INVALID_GC_PHYSICAL_ADDRESS;
271	# endif
272	if (VBOX_SUCCESS(rc))
273	{
274	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> PAGE_SHIFT) & GST_PT_MASK;
275	if (pPTSrc->a[iPTESrc].n.u1Present)
276	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
277	}
278	}
279	# else
280	/* No paging so the fault address is the physical address */
281	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
282	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
283
284	/*
285	* If we have a GC address we'll check if it has any flags set.
286	*/
287	if (GCPhys != NIL_RTGCPHYS)
288	{
289	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
290
291	PPGMPAGE pPage;
292	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
293	if (VBOX_SUCCESS(rc))
294	{
295	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
296	{
297	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
298	{
299	/*
300	* Physical page access handler.
301	*/
302	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
303	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
304	if (pCur)
305	{
306	# ifdef PGM_SYNC_N_PAGES
307	/*
308	* If the region is write protected and we got a page not present fault, then sync
309	* the pages. If the fault was caused by a read, then restart the instruction.
310	* In case of write access continue to the GC write handler.
311	*
312	* ASSUMES that there is only one handler per page or that they have similar write properties.
313	*/
314	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
315	&& !(uErr & X86_TRAP_PF_P))
316	{
317	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
318	if ( VBOX_FAILURE(rc)
319	\|\| !(uErr & X86_TRAP_PF_RW)
320	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
321	{
322	AssertRC(rc);
323	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
324	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
325	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
326	return rc;
327	}
328	}
329	# endif
330
331	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
332	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
333	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
334
335	#if defined(IN_GC) \|\| defined(IN_RING0)
336	if (CTXALLSUFF(pCur->pfnHandler))
337	{
338	STAM_PROFILE_START(&pCur->Stat, h);
339	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
340	STAM_PROFILE_STOP(&pCur->Stat, h);
341	}
342	else
343	#endif
344	rc = VINF_EM_RAW_EMULATE_INSTR;
345	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
346	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
347	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
348	return rc;
349	}
350	}
351	# if PGM_WITH_PAGING(PGM_GST_TYPE)
352	else
353	{
354	# ifdef PGM_SYNC_N_PAGES
355	/*
356	* If the region is write protected and we got a page not present fault, then sync
357	* the pages. If the fault was caused by a read, then restart the instruction.
358	* In case of write access continue to the GC write handler.
359	*/
360	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
361	&& !(uErr & X86_TRAP_PF_P))
362	{
363	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
364	if ( VBOX_FAILURE(rc)
365	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
366	\|\| !(uErr & X86_TRAP_PF_RW))
367	{
368	AssertRC(rc);
369	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
370	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
371	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
372	return rc;
373	}
374	}
375	# endif
376	/*
377	* Ok, it's an virtual page access handler.
378	*
379	* Since it's faster to search by address, we'll do that first
380	* and then retry by GCPhys if that fails.
381	*/
382	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
383	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
384	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
385	*/
386	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
387	if (pCur)
388	{
389	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
390	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
391	\|\| !(uErr & X86_TRAP_PF_P)
392	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
393	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
394
395	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
396	&& ( uErr & X86_TRAP_PF_RW
397	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
398	{
399	# ifdef IN_GC
400	STAM_PROFILE_START(&pCur->Stat, h);
401	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
402	STAM_PROFILE_STOP(&pCur->Stat, h);
403	# else
404	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
405	# endif
406	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
407	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
408	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
409	return rc;
410	}
411	/* Unhandled part of a monitored page */
412	}
413	else
414	{
415	/* Check by physical address. */
416	PPGMVIRTHANDLER pCur;
417	unsigned iPage;
418	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
419	&pCur, &iPage);
420	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
421	if ( pCur
422	&& ( uErr & X86_TRAP_PF_RW
423	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
424	{
425	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
426	# ifdef IN_GC
427	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
428	Assert(off < pCur->cb);
429	STAM_PROFILE_START(&pCur->Stat, h);
430	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
431	STAM_PROFILE_STOP(&pCur->Stat, h);
432	# else
433	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
434	# endif
435	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
436	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
437	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
438	return rc;
439	}
440	}
441	}
442	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
443
444	/*
445	* There is a handled area of the page, but this fault doesn't belong to it.
446	* We must emulate the instruction.
447	*
448	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
449	* we first check if this was a page-not-present fault for a page with only
450	* write access handlers. Restart the instruction if it wasn't a write access.
451	*/
452	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
453
454	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
455	&& !(uErr & X86_TRAP_PF_P))
456	{
457	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
458	if ( VBOX_FAILURE(rc)
459	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
460	\|\| !(uErr & X86_TRAP_PF_RW))
461	{
462	AssertRC(rc);
463	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
464	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
465	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
466	return rc;
467	}
468	}
469
470	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
471	* It's writing to an unhandled part of the LDT page several million times.
472	*/
473	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
474	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
475	rc, pPage->HCPhys,
476	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
477	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
478	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
479	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
480	return rc;
481	} /* if any kind of handler */
482
483	# if PGM_WITH_PAGING(PGM_GST_TYPE)
484	if (uErr & X86_TRAP_PF_P)
485	{
486	/*
487	* The page isn't marked, but it might still be monitored by a virtual page access handler.
488	* (ASSUMES no temporary disabling of virtual handlers.)
489	*/
490	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
491	* we should correct both the shadow page table and physical memory flags, and not only check for
492	* accesses within the handler region but for access to pages with virtual handlers. */
493	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
494	if (pCur)
495	{
496	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
497	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
498	\|\| !(uErr & X86_TRAP_PF_P)
499	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
500	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
501
502	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
503	&& ( uErr & X86_TRAP_PF_RW
504	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
505	{
506	# ifdef IN_GC
507	STAM_PROFILE_START(&pCur->Stat, h);
508	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
509	STAM_PROFILE_STOP(&pCur->Stat, h);
510	# else
511	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
512	# endif
513	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
514	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
515	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
516	return rc;
517	}
518	}
519	}
520	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
521	}
522	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
523
524	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
525	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
526	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
527	&& (uErr & X86_TRAP_PF_RW))
528	{
529	uint64_t fPageGst;
530	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
531	if ( VBOX_SUCCESS(rc)
532	&& !(fPageGst & X86_PTE_RW))
533	{
534	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
535	if (VBOX_SUCCESS(rc))
536	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
537	else
538	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
539	return rc;
540	}
541	else
542	AssertFailed(); /* This shouldn't happen; the above check is paranoid. */
543	}
544
545	# ifdef PGM_OUT_OF_SYNC_IN_GC
546	/*
547	* We are here only if page is present in Guest page tables and trap is not handled
548	* by our handlers.
549	* Check it for page out-of-sync situation.
550	*/
551	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
552
553	if (!(uErr & X86_TRAP_PF_P))
554	{
555	/*
556	* Page is not present in our page tables.
557	* Try to sync it!
558	* BTW, fPageShw is invalid in this branch!
559	*/
560	if (uErr & X86_TRAP_PF_US)
561	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
562	else /* supervisor */
563	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
564
565	# if defined(LOG_ENABLED) && !defined(IN_RING0)
566	RTGCPHYS GCPhys;
567	uint64_t fPageGst;
568	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
569	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
570	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
571	# endif /* LOG_ENABLED */
572
573	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
574	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
575	{
576	uint64_t fPageGst;
577	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
578	if ( VBOX_SUCCESS(rc)
579	&& !(fPageGst & X86_PTE_US))
580	{
581	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
582	if ( pvFault == (RTGCPTR)pRegFrame->eip
583	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
584	# ifdef CSAM_DETECT_NEW_CODE_PAGES
585	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
586	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
587	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
588	)
589	{
590	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
591	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
592	if (rc != VINF_SUCCESS)
593	{
594	/*
595	* CSAM needs to perform a job in ring 3.
596	*
597	* Sync the page before going to the host context; otherwise we'll end up in a loop if
598	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
599	*/
600	LogFlow(("CSAM ring 3 job\n"));
601	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
602	AssertRC(rc2);
603
604	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
605	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
606	return rc;
607	}
608	}
609	# ifdef CSAM_DETECT_NEW_CODE_PAGES
610	else
611	if ( uErr == X86_TRAP_PF_RW
612	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
613	&& pRegFrame->ecx < 0x10000
614	)
615	{
616	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
617	* to detect loading of new code pages.
618	*/
619
620	/*
621	* Decode the instruction.
622	*/
623	RTGCPTR PC;
624	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
625	if (rc == VINF_SUCCESS)
626	{
627	DISCPUSTATE Cpu;
628	uint32_t cbOp;
629	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
630
631	/* For now we'll restrict this to rep movsw/d instructions */
632	if ( rc == VINF_SUCCESS
633	&& Cpu.pCurInstr->opcode == OP_MOVSWD
634	&& (Cpu.prefix & PREFIX_REP))
635	{
636	CSAMMarkPossibleCodePage(pVM, pvFault);
637	}
638	}
639	}
640	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
641
642	/*
643	* Mark this page as safe.
644	*/
645	/** @todo not correct for pages that contain both code and data!! */
646	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
647	CSAMMarkPage(pVM, pvFault, true);
648	}
649	}
650	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
651	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
652	if (VBOX_SUCCESS(rc))
653	{
654	/* The page was successfully synced, return to the guest. */
655	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
656	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
657	return VINF_SUCCESS;
658	}
659	}
660	else
661	{
662	/*
663	* A side effect of not flushing global PDEs are out of sync pages due
664	* to physical monitored regions, that are no longer valid.
665	* Assume for now it only applies to the read/write flag
666	*/
667	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
668	{
669	if (uErr & X86_TRAP_PF_US)
670	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
671	else /* supervisor */
672	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
673
674
675	/*
676	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
677	*/
678	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
679	if (VBOX_SUCCESS(rc))
680	{
681	/*
682	* Page was successfully synced, return to guest.
683	*/
684	# ifdef VBOX_STRICT
685	RTGCPHYS GCPhys;
686	uint64_t fPageGst;
687	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
688	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
689	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
690
691	uint64_t fPageShw;
692	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
693	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
694	# endif /* VBOX_STRICT */
695	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
696	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
697	return VINF_SUCCESS;
698	}
699	}
700
701	# if PGM_WITH_PAGING(PGM_GST_TYPE)
702	# ifdef VBOX_STRICT
703	/*
704	* Check for VMM page flags vs. Guest page flags consistency.
705	* Currently only for debug purposes.
706	*/
707	if (VBOX_SUCCESS(rc))
708	{
709	/* Get guest page flags. */
710	uint64_t fPageGst;
711	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
712	if (VBOX_SUCCESS(rc))
713	{
714	uint64_t fPageShw;
715	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
716
717	/*
718	* Compare page flags.
719	* Note: we have AVL, A, D bits desynched.
720	*/
721	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
722	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
723	}
724	else
725	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
726	}
727	else
728	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
729	# endif /* VBOX_STRICT */
730	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
731	}
732	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
733	# endif /* PGM_OUT_OF_SYNC_IN_GC */
734	}
735	else
736	{
737	/*
738	* Page not present in Guest OS or invalid page table address.
739	* This is potential virtual page access handler food.
740	*
741	* For the present we'll say that our access handlers don't
742	* work for this case - we've already discarded the page table
743	* not present case which is identical to this.
744	*
745	* When we perchance find we need this, we will probably have AVL
746	* trees (offset based) to operate on and we can measure their speed
747	* agains mapping a page table and probably rearrange this handling
748	* a bit. (Like, searching virtual ranges before checking the
749	* physical address.)
750	*/
751	}
752	}
753
754
755	# if PGM_WITH_PAGING(PGM_GST_TYPE)
756	/*
757	* Conclusion, this is a guest trap.
758	*/
759	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
760	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
761	return VINF_EM_RAW_GUEST_TRAP;
762	# else
763	/* present, but not a monitored page; perhaps the guest is probing physical memory */
764	return VINF_EM_RAW_EMULATE_INSTR;
765	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
766
767
768	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
769
770	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
771	return VERR_INTERNAL_ERROR;
772	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
773	}
774
775
776	/**
777	* Emulation of the invlpg instruction.
778	*
779	*
780	* @returns VBox status code.
781	*
782	* @param pVM VM handle.
783	* @param GCPtrPage Page to invalidate.
784	*
785	* @remark ASSUMES that the guest is updating before invalidating. This order
786	* isn't required by the CPU, so this is speculative and could cause
787	* trouble.
788	*
789	* @todo Flush page or page directory only if necessary!
790	* @todo Add a #define for simply invalidating the page.
791	*/
792	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
793	{
794	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
795	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
796
797	LogFlow(("InvalidatePage %x\n", GCPtrPage));
798	/*
799	* Get the shadow PD entry and skip out if this PD isn't present.
800	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
801	*/
802	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
803	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
804	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
805	# else
806	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
807	# endif
808	const SHWPDE PdeDst = *pPdeDst;
809	if (!PdeDst.n.u1Present)
810	{
811	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
812	return VINF_SUCCESS;
813	}
814
815	/*
816	* Get the guest PD entry and calc big page.
817	*/
818	# if PGM_GST_TYPE == PGM_TYPE_32BIT
819	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
820	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
821	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
822	# else /* PAE */
823	unsigned iPDSrc;
824	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
825	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
826	# endif
827
828	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
829	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
830
831	# ifdef IN_RING3
832	/*
833	* If a CR3 Sync is pending we may ignore the invalidate page operation
834	* depending on the kind of sync and if it's a global page or not.
835	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
836	*/
837	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
838	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
839	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
840	&& fIsBigPage
841	&& PdeSrc.b.u1Global
842	&& (cr4 & X86_CR4_PGE)
843	)
844	)
845	# else
846	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
847	# endif
848	{
849	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
850	return VINF_SUCCESS;
851	}
852	# endif /* IN_RING3 */
853
854
855	/*
856	* Deal with the Guest PDE.
857	*/
858	int rc = VINF_SUCCESS;
859	if (PdeSrc.n.u1Present)
860	{
861	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
862	{
863	/*
864	* Conflict - Let SyncPT deal with it to avoid duplicate code.
865	*/
866	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
867	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
868	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
869	}
870	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
871	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
872	{
873	/*
874	* Mark not present so we can resync the PDE when it's used.
875	*/
876	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
877	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
878	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
879	pPdeDst->u = 0;
880	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
881	PGM_INVL_GUEST_TLBS();
882	}
883	# ifdef PGM_SYNC_ACCESSED_BIT
884	else if (!PdeSrc.n.u1Accessed)
885	{
886	/*
887	* Mark not present so we can set the accessed bit.
888	*/
889	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
890	pPdeDst->u = 0;
891	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
892	PGM_INVL_GUEST_TLBS();
893	}
894	# endif
895	else if (!fIsBigPage)
896	{
897	/*
898	* 4KB - page.
899	*/
900	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
901	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
902	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
903	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
904	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
905	# endif
906	if (pShwPage->GCPhys == GCPhys)
907	{
908	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
909	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
910	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
911	if (pPT->a[iPTEDst].n.u1Present)
912	{
913	# ifdef PGMPOOL_WITH_USER_TRACKING
914	/* This is very unlikely with caching/monitoring enabled. */
915	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
916	# endif
917	pPT->a[iPTEDst].u = 0;
918	}
919	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
920	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
921	if (VBOX_SUCCESS(rc))
922	rc = VINF_SUCCESS;
923	# endif
924	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
925	PGM_INVL_PG(GCPtrPage);
926	}
927	else
928	{
929	/*
930	* The page table address changed.
931	*/
932	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
933	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
934	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
935	pPdeDst->u = 0;
936	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
937	PGM_INVL_GUEST_TLBS();
938	}
939	}
940	else
941	{
942	/*
943	* 4MB - page.
944	*/
945	/* Before freeing the page, check if anything really changed. */
946	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
947	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
948	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
949	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
950	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
951	# endif
952	if ( pShwPage->GCPhys == GCPhys
953	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
954	{
955	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
956	/** @todo PAT */
957	# ifdef PGM_SYNC_DIRTY_BIT
958	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
959	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
960	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
961	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
962	# else
963	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
964	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
965	# endif
966	{
967	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
968	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
969	return VINF_SUCCESS;
970	}
971	}
972
973	/*
974	* Ok, the page table is present and it's been changed in the guest.
975	* If we're in host context, we'll just mark it as not present taking the lazy approach.
976	* We could do this for some flushes in GC too, but we need an algorithm for
977	* deciding which 4MB pages containing code likely to be executed very soon.
978	*/
979	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
980	pPdeDst->u = 0;
981	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
982	PGM_INVL_BIG_PG(GCPtrPage);
983	}
984	}
985	else
986	{
987	/*
988	* Page directory is not present, mark shadow PDE not present.
989	*/
990	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
991	{
992	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
993	pPdeDst->u = 0;
994	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
995	PGM_INVL_PG(GCPtrPage);
996	}
997	else
998	{
999	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1000	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1001	}
1002	}
1003
1004	return rc;
1005
1006	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1007	//# error not implemented
1008	return VERR_INTERNAL_ERROR;
1009
1010	#else /* guest real and protected mode */
1011	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1012	return VINF_SUCCESS;
1013	#endif
1014	}
1015
1016
1017	#ifdef PGMPOOL_WITH_USER_TRACKING
1018	/**
1019	* Update the tracking of shadowed pages.
1020	*
1021	* @param pVM The VM handle.
1022	* @param pShwPage The shadow page.
1023	* @param HCPhys The physical page we is being dereferenced.
1024	*/
1025	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1026	{
1027	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1028	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1029	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1030
1031	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1032	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1033	* 2. write protect all shadowed pages. I.e. implement caching.
1034	*/
1035	/*
1036	* Find the guest address.
1037	*/
1038	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1039	pRam;
1040	pRam = CTXALLSUFF(pRam->pNext))
1041	{
1042	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1043	while (iPage-- > 0)
1044	{
1045	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1046	{
1047	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1048	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1049	pShwPage->cPresent--;
1050	pPool->cPresent--;
1051	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1052	return;
1053	}
1054	}
1055	}
1056
1057	for (;;)
1058	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1059	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1060	pShwPage->cPresent--;
1061	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1062	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1063	}
1064
1065
1066	/**
1067	* Update the tracking of shadowed pages.
1068	*
1069	* @param pVM The VM handle.
1070	* @param pShwPage The shadow page.
1071	* @param u16 The top 16-bit of the pPage->HCPhys.
1072	* @param pPage Pointer to the guest page. this will be modified.
1073	* @param iPTDst The index into the shadow table.
1074	*/
1075	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1076	{
1077	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1078	/*
1079	* We're making certain assumptions about the placement of cRef and idx.
1080	*/
1081	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1082	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1083
1084	/*
1085	* Just deal with the simple first time here.
1086	*/
1087	if (!u16)
1088	{
1089	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1090	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1091	}
1092	else
1093	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1094
1095	/* write back, trying to be clever... */
1096	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1097	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1098	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1099	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1100
1101	/* update statistics. */
1102	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1103	pShwPage->cPresent++;
1104	if (pShwPage->iFirstPresent > iPTDst)
1105	pShwPage->iFirstPresent = iPTDst;
1106	}
1107	#endif /* PGMPOOL_WITH_USER_TRACKING */
1108
1109
1110	/**
1111	* Creates a 4K shadow page for a guest page.
1112	*
1113	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1114	* physical address. The PdeSrc argument only the flags are used. No page structured
1115	* will be mapped in this function.
1116	*
1117	* @param pVM VM handle.
1118	* @param pPteDst Destination page table entry.
1119	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1120	* Can safely assume that only the flags are being used.
1121	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1122	* @param pShwPage Pointer to the shadow page.
1123	* @param iPTDst The index into the shadow table.
1124	*
1125	* @remark Not used for 2/4MB pages!
1126	*/
1127	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1128	{
1129	if (PteSrc.n.u1Present)
1130	{
1131	/*
1132	* Find the ram range.
1133	*/
1134	PPGMPAGE pPage;
1135	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1136	if (VBOX_SUCCESS(rc))
1137	{
1138	/** @todo investiage PWT, PCD and PAT. */
1139	/*
1140	* Make page table entry.
1141	*/
1142	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1143	SHWPTE PteDst;
1144	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1145	{
1146	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1147	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1148	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1149	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1150	else
1151	{
1152	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1153	PteDst.u = 0;
1154	}
1155	/** @todo count these two kinds. */
1156	}
1157	else
1158	{
1159	#ifdef PGM_SYNC_DIRTY_BIT
1160	# ifdef PGM_SYNC_ACCESSED_BIT
1161	/*
1162	* If the page or page directory entry is not marked accessed,
1163	* we mark the page not present.
1164	*/
1165	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1166	{
1167	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1168	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1169	PteDst.u = 0;
1170	}
1171	else
1172	# endif
1173	/*
1174	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1175	* when the page is modified.
1176	*/
1177	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1178	{
1179	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1180	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1181	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1182	\| PGM_PTFLAGS_TRACK_DIRTY;
1183	}
1184	else
1185	{
1186	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1187	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1188	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1189	}
1190	#endif
1191	}
1192
1193	#ifdef PGMPOOL_WITH_USER_TRACKING
1194	/*
1195	* Keep user track up to date.
1196	*/
1197	if (PteDst.n.u1Present)
1198	{
1199	if (!pPteDst->n.u1Present)
1200	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1201	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1202	{
1203	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1204	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1205	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1206	}
1207	}
1208	else if (pPteDst->n.u1Present)
1209	{
1210	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1211	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1212	}
1213	#endif /* PGMPOOL_WITH_USER_TRACKING */
1214
1215	/*
1216	* Update statistics and commit the entry.
1217	*/
1218	if (!PteSrc.n.u1Global)
1219	pShwPage->fSeenNonGlobal = true;
1220	*pPteDst = PteDst;
1221	}
1222	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1223	/** @todo count these. */
1224	}
1225	else
1226	{
1227	/*
1228	* Page not-present.
1229	*/
1230	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1231	#ifdef PGMPOOL_WITH_USER_TRACKING
1232	/* Keep user track up to date. */
1233	if (pPteDst->n.u1Present)
1234	{
1235	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1236	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1237	}
1238	#endif /* PGMPOOL_WITH_USER_TRACKING */
1239	pPteDst->u = 0;
1240	/** @todo count these. */
1241	}
1242	}
1243
1244
1245	/**
1246	* Syncs a guest OS page.
1247	*
1248	* There are no conflicts at this point, neither is there any need for
1249	* page table allocations.
1250	*
1251	* @returns VBox status code.
1252	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1253	* @param pVM VM handle.
1254	* @param PdeSrc Page directory entry of the guest.
1255	* @param GCPtrPage Guest context page address.
1256	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1257	* @param uErr Fault error (X86_TRAP_PF_*).
1258	*/
1259	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1260	{
1261	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1262
1263	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1264	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1265
1266	/*
1267	* Assert preconditions.
1268	*/
1269	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1270	Assert(PdeSrc.n.u1Present);
1271	Assert(cPages);
1272
1273	/*
1274	* Get the shadow PDE, find the shadow page table in the pool.
1275	*/
1276	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1277	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1278	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1279	# else /* PAE */
1280	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1281	# endif
1282	Assert(PdeDst.n.u1Present);
1283	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1284
1285	/*
1286	* Check that the page is present and that the shadow PDE isn't out of sync.
1287	*/
1288	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1289	RTGCPHYS GCPhys;
1290	if (!fBigPage)
1291	{
1292	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1293	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1294	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1295	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1296	# endif
1297	}
1298	else
1299	{
1300	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1301	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1302	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1303	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1304	# endif
1305	}
1306	if ( pShwPage->GCPhys == GCPhys
1307	&& PdeSrc.n.u1Present
1308	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1309	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1310	# if PGM_GST_TYPE == PGM_TYPE_PAE
1311	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1312	# endif
1313	)
1314	{
1315	# ifdef PGM_SYNC_ACCESSED_BIT
1316	/*
1317	* Check that the PDE is marked accessed already.
1318	* Since we set the accessed bit before getting here on a #PF, this
1319	* check is only meant for dealing with non-#PF'ing paths.
1320	*/
1321	if (PdeSrc.n.u1Accessed)
1322	# endif
1323	{
1324	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1325	if (!fBigPage)
1326	{
1327	/*
1328	* 4KB Page - Map the guest page table.
1329	*/
1330	PGSTPT pPTSrc;
1331	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1332	if (VBOX_SUCCESS(rc))
1333	{
1334	# ifdef PGM_SYNC_N_PAGES
1335	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1336	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1337	{
1338	/*
1339	* This code path is currently only taken when the caller is PGMTrap0eHandler
1340	* for non-present pages!
1341	*
1342	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1343	* deal with locality.
1344	*/
1345	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1346	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1347	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1348	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1349	# else
1350	const unsigned offPTSrc = 0;
1351	# endif
1352	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1353	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1354	iPTDst = 0;
1355	else
1356	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1357	for (; iPTDst < iPTDstEnd; iPTDst++)
1358	{
1359	if (!pPTDst->a[iPTDst].n.u1Present)
1360	{
1361	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1362	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1363	NOREF(GCPtrCurPage);
1364	#ifndef IN_RING0
1365	/*
1366	* Assuming kernel code will be marked as supervisor - and not as user level
1367	* and executed using a conforming code selector - And marked as readonly.
1368	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1369	*/
1370	PPGMPAGE pPage;
1371	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1372	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1373	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1374	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1375	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1376	)
1377	#endif /* else: CSAM not active */
1378	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1379	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1380	GCPtrCurPage, PteSrc.n.u1Present,
1381	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1382	PteSrc.n.u1User & PdeSrc.n.u1User,
1383	(uint64_t)PteSrc.u,
1384	(uint64_t)pPTDst->a[iPTDst].u,
1385	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1386	}
1387	}
1388	}
1389	else
1390	# endif /* PGM_SYNC_N_PAGES */
1391	{
1392	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1393	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1394	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1395	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1396	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1397	GCPtrPage, PteSrc.n.u1Present,
1398	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1399	PteSrc.n.u1User & PdeSrc.n.u1User,
1400	(uint64_t)PteSrc.u,
1401	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1402	}
1403	}
1404	else /* MMIO or invalid page: emulated in #PF handler. */
1405	{
1406	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1407	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1408	}
1409	}
1410	else
1411	{
1412	/*
1413	* 4/2MB page - lazy syncing shadow 4K pages.
1414	* (There are many causes of getting here, it's no longer only CSAM.)
1415	*/
1416	/* Calculate the GC physical address of this 4KB shadow page. */
1417	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1418	/* Find ram range. */
1419	PPGMPAGE pPage;
1420	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1421	if (VBOX_SUCCESS(rc))
1422	{
1423	/*
1424	* Make shadow PTE entry.
1425	*/
1426	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1427	SHWPTE PteDst;
1428	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1429	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1430	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1431	{
1432	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1433	PteDst.n.u1Write = 0;
1434	else
1435	PteDst.u = 0;
1436	}
1437	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1438	# ifdef PGMPOOL_WITH_USER_TRACKING
1439	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1440	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1441	# endif
1442	pPTDst->a[iPTDst] = PteDst;
1443
1444
1445	# ifdef PGM_SYNC_DIRTY_BIT
1446	/*
1447	* If the page is not flagged as dirty and is writable, then make it read-only
1448	* at PD level, so we can set the dirty bit when the page is modified.
1449	*
1450	* ASSUMES that page access handlers are implemented on page table entry level.
1451	* Thus we will first catch the dirty access and set PDE.D and restart. If
1452	* there is an access handler, we'll trap again and let it work on the problem.
1453	*/
1454	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1455	* As for invlpg, it simply frees the whole shadow PT.
1456	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1457	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1458	{
1459	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1460	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1461	PdeDst.n.u1Write = 0;
1462	}
1463	else
1464	{
1465	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1466	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1467	}
1468	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1469	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1470	# else /* PAE */
1471	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1472	# endif
1473	# endif /* PGM_SYNC_DIRTY_BIT */
1474	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1475	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1476	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1477	}
1478	else
1479	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1480	}
1481	return VINF_SUCCESS;
1482	}
1483	# ifdef PGM_SYNC_ACCESSED_BIT
1484	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1485	#endif
1486	}
1487	else
1488	{
1489	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1490	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1491	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1492	}
1493
1494	/*
1495	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1496	* Yea, I'm lazy.
1497	*/
1498	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1499	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1500	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1501	# else /* PAE */
1502	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1503	# endif
1504	PGM_INVL_GUEST_TLBS();
1505	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1506
1507	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1508
1509	# ifdef PGM_SYNC_N_PAGES
1510	/*
1511	* Get the shadow PDE, find the shadow page table in the pool.
1512	*/
1513	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1514	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1515	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1516	# else /* PAE */
1517	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1518	# endif
1519	Assert(PdeDst.n.u1Present);
1520	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1521	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1522
1523	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1524	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1525	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1526	# else
1527	const unsigned offPTSrc = 0;
1528	# endif
1529
1530	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1531	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1532	{
1533	/*
1534	* This code path is currently only taken when the caller is PGMTrap0eHandler
1535	* for non-present pages!
1536	*
1537	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1538	* deal with locality.
1539	*/
1540	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1541	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1542	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1543	iPTDst = 0;
1544	else
1545	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1546	for (; iPTDst < iPTDstEnd; iPTDst++)
1547	{
1548	if (!pPTDst->a[iPTDst].n.u1Present)
1549	{
1550	GSTPTE PteSrc;
1551
1552	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1553
1554	/* Fake the page table entry */
1555	PteSrc.u = GCPtrCurPage;
1556	PteSrc.n.u1Present = 1;
1557	PteSrc.n.u1Dirty = 1;
1558	PteSrc.n.u1Accessed = 1;
1559	PteSrc.n.u1Write = 1;
1560	PteSrc.n.u1User = 1;
1561
1562	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1563
1564	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1565	GCPtrCurPage, PteSrc.n.u1Present,
1566	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1567	PteSrc.n.u1User & PdeSrc.n.u1User,
1568	(uint64_t)PteSrc.u,
1569	(uint64_t)pPTDst->a[iPTDst].u,
1570	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1571	}
1572	}
1573	}
1574	else
1575	# endif /* PGM_SYNC_N_PAGES */
1576	{
1577	GSTPTE PteSrc;
1578	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1579	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1580
1581	/* Fake the page table entry */
1582	PteSrc.u = GCPtrCurPage;
1583	PteSrc.n.u1Present = 1;
1584	PteSrc.n.u1Dirty = 1;
1585	PteSrc.n.u1Accessed = 1;
1586	PteSrc.n.u1Write = 1;
1587	PteSrc.n.u1User = 1;
1588	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1589
1590	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1591	GCPtrPage, PteSrc.n.u1Present,
1592	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1593	PteSrc.n.u1User & PdeSrc.n.u1User,
1594	(uint64_t)PteSrc.u,
1595	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1596	}
1597	return VINF_SUCCESS;
1598
1599	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1600	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1601	return VERR_INTERNAL_ERROR;
1602	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1603	}
1604
1605
1606
1607	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1608
1609	# ifdef PGM_SYNC_DIRTY_BIT
1610
1611	/**
1612	* Investigate page fault and handle write protection page faults caused by
1613	* dirty bit tracking.
1614	*
1615	* @returns VBox status code.
1616	* @param pVM VM handle.
1617	* @param uErr Page fault error code.
1618	* @param pPdeDst Shadow page directory entry.
1619	* @param pPdeSrc Guest page directory entry.
1620	* @param GCPtrPage Guest context page address.
1621	*/
1622	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1623	{
1624	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1625	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1626	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1627	# if PGM_WITH_NX(PGM_GST_TYPE)
1628	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1629	# endif
1630
1631	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1632	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1633
1634	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1635	AssertFailed();
1636	# elif PGM_GST_TYPE == PGM_TYPE_PAE
1637	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1638
1639	/*
1640	* Real page fault?
1641	*/
1642	if ( (uErr & X86_TRAP_PF_RSVD)
1643	\|\| !pPdpeSrc->n.u1Present
1644	# if PGM_WITH_NX(PGM_GST_TYPE)
1645	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->n.u1NoExecute)
1646	# endif
1647	\|\| (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1648	\|\| (fUserLevelFault && !pPdpeSrc->n.u1User) )
1649	{
1650	# ifdef IN_GC
1651	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1652	# endif
1653	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1654	LogFlow(("CheckPageFault: real page fault at %VGv (0)\n", GCPtrPage));
1655
1656	if ( pPdpeSrc->n.u1Present
1657	&& pPdeSrc->n.u1Present)
1658	{
1659	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1660	* See the 2nd case below as well.
1661	*/
1662	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1663	{
1664	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1665	}
1666	else
1667	{
1668	/*
1669	* Map the guest page table.
1670	*/
1671	PGSTPT pPTSrc;
1672	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1673	if (VBOX_SUCCESS(rc))
1674	{
1675	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1676	const GSTPTE PteSrc = *pPteSrc;
1677	if (pPteSrc->n.u1Present)
1678	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1679	}
1680	AssertRC(rc);
1681	}
1682	}
1683	return VINF_EM_RAW_GUEST_TRAP;
1684	}
1685	# endif
1686
1687	/*
1688	* Real page fault?
1689	*/
1690	if ( (uErr & X86_TRAP_PF_RSVD)
1691	\|\| !pPdeSrc->n.u1Present
1692	# if PGM_WITH_NX(PGM_GST_TYPE)
1693	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1694	# endif
1695	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1696	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1697	{
1698	# ifdef IN_GC
1699	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1700	# endif
1701	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1702	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1703
1704	if (pPdeSrc->n.u1Present)
1705	{
1706	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1707	* See the 2nd case below as well.
1708	*/
1709	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1710	{
1711	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1712	}
1713	else
1714	{
1715	/*
1716	* Map the guest page table.
1717	*/
1718	PGSTPT pPTSrc;
1719	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1720	if (VBOX_SUCCESS(rc))
1721	{
1722	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1723	const GSTPTE PteSrc = *pPteSrc;
1724	if (pPteSrc->n.u1Present)
1725	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1726	}
1727	AssertRC(rc);
1728	}
1729	}
1730	return VINF_EM_RAW_GUEST_TRAP;
1731	}
1732
1733	/*
1734	* First check the easy case where the page directory has been marked read-only to track
1735	* the dirty bit of an emulated BIG page
1736	*/
1737	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1738	{
1739	/* Mark guest page directory as accessed */
1740	pPdeSrc->b.u1Accessed = 1;
1741
1742	/*
1743	* Only write protection page faults are relevant here.
1744	*/
1745	if (fWriteFault)
1746	{
1747	/* Mark guest page directory as dirty (BIG page only). */
1748	pPdeSrc->b.u1Dirty = 1;
1749
1750	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1751	{
1752	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1753
1754	Assert(pPdeSrc->b.u1Write);
1755
1756	pPdeDst->n.u1Write = 1;
1757	pPdeDst->n.u1Accessed = 1;
1758	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1759	PGM_INVL_BIG_PG(GCPtrPage);
1760	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1761	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1762	}
1763	}
1764	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1765	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1766	}
1767	/* else: 4KB page table */
1768
1769	/*
1770	* Map the guest page table.
1771	*/
1772	PGSTPT pPTSrc;
1773	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1774	if (VBOX_SUCCESS(rc))
1775	{
1776	/*
1777	* Real page fault?
1778	*/
1779	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> PAGE_SHIFT) & GST_PT_MASK];
1780	const GSTPTE PteSrc = *pPteSrc;
1781	if ( !PteSrc.n.u1Present
1782	# if PGM_WITH_NX(PGM_GST_TYPE)
1783	\|\| ((uErr & X86_TRAP_PF_ID) && !PteSrc.n.u1NoExecute)
1784	# endif
1785	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1786	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1787	)
1788	{
1789	# ifdef IN_GC
1790	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1791	# endif
1792	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1793	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1794
1795	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1796	* See the 2nd case above as well.
1797	*/
1798	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1799	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1800
1801	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1802	return VINF_EM_RAW_GUEST_TRAP;
1803	}
1804	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1805
1806	/*
1807	* Set the accessed bits in the page directory and the page table.
1808	*/
1809	pPdeSrc->n.u1Accessed = 1;
1810	pPteSrc->n.u1Accessed = 1;
1811
1812	/*
1813	* Only write protection page faults are relevant here.
1814	*/
1815	if (fWriteFault)
1816	{
1817	/* Write access, so mark guest entry as dirty. */
1818	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1819	if (!pPteSrc->n.u1Dirty)
1820	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1821	else
1822	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1823	# endif
1824	pPteSrc->n.u1Dirty = 1;
1825
1826	if (pPdeDst->n.u1Present)
1827	{
1828	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1829	* Our individual shadow handlers will provide more information and force a fatal exit.
1830	*/
1831	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1832	{
1833	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1834	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1835	return VINF_SUCCESS;
1836	}
1837
1838	/*
1839	* Map shadow page table.
1840	*/
1841	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1842	if (pShwPage)
1843	{
1844	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1845	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1846	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1847	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1848	{
1849	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1850	# ifdef VBOX_STRICT
1851	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1852	if (pPage)
1853	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1854	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1855	# endif
1856	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1857
1858	Assert(pPteSrc->n.u1Write);
1859
1860	pPteDst->n.u1Write = 1;
1861	pPteDst->n.u1Dirty = 1;
1862	pPteDst->n.u1Accessed = 1;
1863	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1864	PGM_INVL_PG(GCPtrPage);
1865
1866	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1867	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1868	}
1869	}
1870	else
1871	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1872	}
1873	}
1874	/** @todo Optimize accessed bit emulation? */
1875	# ifdef VBOX_STRICT
1876	/*
1877	* Sanity check.
1878	*/
1879	else if ( !pPteSrc->n.u1Dirty
1880	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1881	&& pPdeDst->n.u1Present)
1882	{
1883	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1884	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1885	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1886	if ( pPteDst->n.u1Present
1887	&& pPteDst->n.u1Write)
1888	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1889	}
1890	# endif /* VBOX_STRICT */
1891	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1892	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1893	}
1894	AssertRC(rc);
1895	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1896	return rc;
1897	}
1898
1899	# endif
1900
1901	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1902
1903
1904	/**
1905	* Sync a shadow page table.
1906	*
1907	* The shadow page table is not present. This includes the case where
1908	* there is a conflict with a mapping.
1909	*
1910	* @returns VBox status code.
1911	* @param pVM VM handle.
1912	* @param iPD Page directory index.
1913	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1914	* Assume this is a temporary mapping.
1915	* @param GCPtrPage GC Pointer of the page that caused the fault
1916	*/
1917	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1918	{
1919	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1920	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1921	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1922
1923	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1924	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1925
1926	/*
1927	* Validate input a little bit.
1928	*/
1929	Assert(iPDSrc == (GCPtrPage >> GST_PD_SHIFT));
1930	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1931	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1932	# else
1933	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1934	# endif
1935	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1936	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1937	SHWPDE PdeDst = *pPdeDst;
1938
1939	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1940	/*
1941	* Check for conflicts.
1942	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1943	* HC: Simply resolve the conflict.
1944	*/
1945	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1946	{
1947	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1948	# ifndef IN_RING3
1949	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1950	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1951	return VERR_ADDRESS_CONFLICT;
1952	# else
1953	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1954	Assert(pMapping);
1955	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1956	if (VBOX_FAILURE(rc))
1957	{
1958	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1959	return rc;
1960	}
1961	PdeDst = *pPdeDst;
1962	# endif
1963	}
1964	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1965	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1966	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1967	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1968	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1969
1970	/*
1971	* Sync page directory entry.
1972	*/
1973	int rc = VINF_SUCCESS;
1974	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1975	if (PdeSrc.n.u1Present)
1976	{
1977	/*
1978	* Allocate & map the page table.
1979	*/
1980	PSHWPT pPTDst;
1981	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1982	PPGMPOOLPAGE pShwPage;
1983	RTGCPHYS GCPhys;
1984	if (fPageTable)
1985	{
1986	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1987	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1988	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1989	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1990	# endif
1991	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1992	}
1993	else
1994	{
1995	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1996	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1997	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1998	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1999	# endif
2000	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2001	}
2002	if (rc == VINF_SUCCESS)
2003	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2004	else if (rc == VINF_PGM_CACHED_PAGE)
2005	{
2006	/*
2007	* The PT was cached, just hook it up.
2008	*/
2009	if (fPageTable)
2010	PdeDst.u = pShwPage->Core.Key
2011	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2012	else
2013	{
2014	PdeDst.u = pShwPage->Core.Key
2015	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2016	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
2017	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2018	{
2019	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2020	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2021	PdeDst.b.u1Write = 0;
2022	}
2023	# endif
2024	}
2025	*pPdeDst = PdeDst;
2026	return VINF_SUCCESS;
2027	}
2028	else if (rc == VERR_PGM_POOL_FLUSHED)
2029	return VINF_PGM_SYNC_CR3;
2030	else
2031	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2032	PdeDst.u &= X86_PDE_AVL_MASK;
2033	PdeDst.u \|= pShwPage->Core.Key;
2034
2035	# ifdef PGM_SYNC_DIRTY_BIT
2036	/*
2037	* Page directory has been accessed (this is a fault situation, remember).
2038	*/
2039	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2040	# endif
2041	if (fPageTable)
2042	{
2043	/*
2044	* Page table - 4KB.
2045	*
2046	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2047	*/
2048	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2049	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2050	PGSTPT pPTSrc;
2051	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2052	if (VBOX_SUCCESS(rc))
2053	{
2054	/*
2055	* Start by syncing the page directory entry so CSAM's TLB trick works.
2056	*/
2057	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2058	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2059	*pPdeDst = PdeDst;
2060
2061	/*
2062	* Directory/page user or supervisor privilege: (same goes for read/write)
2063	*
2064	* Directory Page Combined
2065	* U/S U/S U/S
2066	* 0 0 0
2067	* 0 1 0
2068	* 1 0 0
2069	* 1 1 1
2070	*
2071	* Simple AND operation. Table listed for completeness.
2072	*
2073	*/
2074	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2075	# ifdef PGM_SYNC_N_PAGES
2076	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2077	unsigned iPTDst = iPTBase;
2078	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2079	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2080	iPTDst = 0;
2081	else
2082	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2083	# else /* !PGM_SYNC_N_PAGES */
2084	unsigned iPTDst = 0;
2085	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2086	# endif /* !PGM_SYNC_N_PAGES */
2087	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2088	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2089	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2090	# else
2091	const unsigned offPTSrc = 0;
2092	# endif
2093	for (; iPTDst < iPTDstEnd; iPTDst++)
2094	{
2095	const unsigned iPTSrc = iPTDst + offPTSrc;
2096	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2097
2098	if (PteSrc.n.u1Present) /* we've already cleared it above */
2099	{
2100	# ifndef IN_RING0
2101	/*
2102	* Assuming kernel code will be marked as supervisor - and not as user level
2103	* and executed using a conforming code selector - And marked as readonly.
2104	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2105	*/
2106	PPGMPAGE pPage;
2107	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2108	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2109	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2110	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2111	)
2112	# endif
2113	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2114	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2115	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2116	PteSrc.n.u1Present,
2117	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2118	PteSrc.n.u1User & PdeSrc.n.u1User,
2119	(uint64_t)PteSrc.u,
2120	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2121	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2122	}
2123	} /* for PTEs */
2124	}
2125	}
2126	else
2127	{
2128	/*
2129	* Big page - 2/4MB.
2130	*
2131	* We'll walk the ram range list in parallel and optimize lookups.
2132	* We will only sync on shadow page table at a time.
2133	*/
2134	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2135
2136	/**
2137	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2138	*/
2139
2140	/*
2141	* Start by syncing the page directory entry.
2142	*/
2143	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2144	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2145
2146	# ifdef PGM_SYNC_DIRTY_BIT
2147	/*
2148	* If the page is not flagged as dirty and is writable, then make it read-only
2149	* at PD level, so we can set the dirty bit when the page is modified.
2150	*
2151	* ASSUMES that page access handlers are implemented on page table entry level.
2152	* Thus we will first catch the dirty access and set PDE.D and restart. If
2153	* there is an access handler, we'll trap again and let it work on the problem.
2154	*/
2155	/** @todo move the above stuff to a section in the PGM documentation. */
2156	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2157	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2158	{
2159	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2160	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2161	PdeDst.b.u1Write = 0;
2162	}
2163	# endif /* PGM_SYNC_DIRTY_BIT */
2164	*pPdeDst = PdeDst;
2165
2166	/*
2167	* Fill the shadow page table.
2168	*/
2169	/* Get address and flags from the source PDE. */
2170	SHWPTE PteDstBase;
2171	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2172
2173	/* Loop thru the entries in the shadow PT. */
2174	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2175	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2176	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2177	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2178	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2179	unsigned iPTDst = 0;
2180	while (iPTDst < ELEMENTS(pPTDst->a))
2181	{
2182	/* Advance ram range list. */
2183	while (pRam && GCPhys > pRam->GCPhysLast)
2184	pRam = CTXALLSUFF(pRam->pNext);
2185	if (pRam && GCPhys >= pRam->GCPhys)
2186	{
2187	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2188	do
2189	{
2190	/* Make shadow PTE. */
2191	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2192	SHWPTE PteDst;
2193
2194	/* Make sure the RAM has already been allocated. */
2195	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2196	{
2197	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2198	{
2199	# ifdef IN_RING3
2200	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2201	# else
2202	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2203	# endif
2204	if (rc != VINF_SUCCESS)
2205	return rc;
2206	}
2207	}
2208
2209	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2210	{
2211	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2212	{
2213	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2214	PteDst.n.u1Write = 0;
2215	}
2216	else
2217	PteDst.u = 0;
2218	}
2219	# ifndef IN_RING0
2220	/*
2221	* Assuming kernel code will be marked as supervisor and not as user level and executed
2222	* using a conforming code selector. Don't check for readonly, as that implies the whole
2223	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2224	*/
2225	else if ( !PdeSrc.n.u1User
2226	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2227	PteDst.u = 0;
2228	# endif
2229	else
2230	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2231	# ifdef PGMPOOL_WITH_USER_TRACKING
2232	if (PteDst.n.u1Present)
2233	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2234	# endif
2235	/* commit it */
2236	pPTDst->a[iPTDst] = PteDst;
2237	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2238	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2239	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2240
2241	/* advance */
2242	GCPhys += PAGE_SIZE;
2243	iHCPage++;
2244	iPTDst++;
2245	} while ( iPTDst < ELEMENTS(pPTDst->a)
2246	&& GCPhys <= pRam->GCPhysLast);
2247	}
2248	else if (pRam)
2249	{
2250	Log(("Invalid pages at %VGp\n", GCPhys));
2251	do
2252	{
2253	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2254	GCPhys += PAGE_SIZE;
2255	iPTDst++;
2256	} while ( iPTDst < ELEMENTS(pPTDst->a)
2257	&& GCPhys < pRam->GCPhys);
2258	}
2259	else
2260	{
2261	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2262	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2263	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2264	}
2265	} /* while more PTEs */
2266	} /* 4KB / 4MB */
2267	}
2268	else
2269	AssertRelease(!PdeDst.n.u1Present);
2270
2271	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2272	# ifdef IN_GC
2273	if (VBOX_FAILURE(rc))
2274	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2275	# endif
2276	return rc;
2277
2278	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2279
2280	int rc = VINF_SUCCESS;
2281
2282	/*
2283	* Validate input a little bit.
2284	*/
2285	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2286	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2287	# else
2288	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2289	# endif
2290	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2291	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2292	SHWPDE PdeDst = *pPdeDst;
2293
2294	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2295	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2296
2297	GSTPDE PdeSrc;
2298	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2299	PdeSrc.n.u1Present = 1;
2300	PdeSrc.n.u1Write = 1;
2301	PdeSrc.n.u1Accessed = 1;
2302	PdeSrc.n.u1User = 1;
2303
2304	/*
2305	* Allocate & map the page table.
2306	*/
2307	PSHWPT pPTDst;
2308	PPGMPOOLPAGE pShwPage;
2309	RTGCPHYS GCPhys;
2310
2311	/* Virtual address = physical address */
2312	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2313	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2314
2315	if ( rc == VINF_SUCCESS
2316	\|\| rc == VINF_PGM_CACHED_PAGE)
2317	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2318	else
2319	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2320
2321	PdeDst.u &= X86_PDE_AVL_MASK;
2322	PdeDst.u \|= pShwPage->Core.Key;
2323	PdeDst.n.u1Present = 1;
2324	*pPdeDst = PdeDst;
2325
2326	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2327	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2328	return rc;
2329
2330	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2331	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2332	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2333	return VERR_INTERNAL_ERROR;
2334	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2335	}
2336
2337
2338
2339	/**
2340	* Prefetch a page/set of pages.
2341	*
2342	* Typically used to sync commonly used pages before entering raw mode
2343	* after a CR3 reload.
2344	*
2345	* @returns VBox status code.
2346	* @param pVM VM handle.
2347	* @param GCPtrPage Page to invalidate.
2348	*/
2349	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2350	{
2351	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2352	/*
2353	* Check that all Guest levels thru the PDE are present, getting the
2354	* PD and PDE in the processes.
2355	*/
2356	int rc = VINF_SUCCESS;
2357	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2358	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2359	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2360	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2361	# else /* PAE */
2362	unsigned iPDSrc;
2363	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2364	# endif
2365	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2366	# else
2367	PGSTPD pPDSrc = NULL;
2368	const unsigned iPDSrc = 0;
2369	GSTPDE PdeSrc;
2370
2371	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2372	PdeSrc.n.u1Present = 1;
2373	PdeSrc.n.u1Write = 1;
2374	PdeSrc.n.u1Accessed = 1;
2375	PdeSrc.n.u1User = 1;
2376	# endif
2377
2378	# ifdef PGM_SYNC_ACCESSED_BIT
2379	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2380	# else
2381	if (PdeSrc.n.u1Present)
2382	# endif
2383	{
2384	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2385	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2386	# else
2387	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2388	# endif
2389	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2390	{
2391	if (!PdeDst.n.u1Present)
2392	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2393	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2394	else
2395	{
2396	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2397	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2398	* makes no sense to prefetch more than one page.
2399	*/
2400	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2401	if (VBOX_SUCCESS(rc))
2402	rc = VINF_SUCCESS;
2403	}
2404	}
2405	}
2406	return rc;
2407
2408	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2409
2410	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2411	return VERR_INTERNAL_ERROR;
2412	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2413	}
2414
2415
2416
2417
2418	/**
2419	* Syncs a page during a PGMVerifyAccess() call.
2420	*
2421	* @returns VBox status code (informational included).
2422	* @param GCPtrPage The address of the page to sync.
2423	* @param fPage The effective guest page flags.
2424	* @param uErr The trap error code.
2425	*/
2426	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2427	{
2428	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2429
2430	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2431
2432	# ifndef IN_RING0
2433	if (!(fPage & X86_PTE_US))
2434	{
2435	/*
2436	* Mark this page as safe.
2437	*/
2438	/** @todo not correct for pages that contain both code and data!! */
2439	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2440	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2441	}
2442	# endif
2443	/*
2444	* Get guest PD and index.
2445	*/
2446
2447	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2448	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2449	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2450	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2451	# else /* PAE */
2452	unsigned iPDSrc;
2453	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2454	# endif
2455	# else
2456	PGSTPD pPDSrc = NULL;
2457	const unsigned iPDSrc = 0;
2458	# endif
2459	int rc = VINF_SUCCESS;
2460
2461	/*
2462	* First check if the shadow pd is present.
2463	*/
2464	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2465	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2466	# else
2467	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2468	# endif
2469	if (!pPdeDst->n.u1Present)
2470	{
2471	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2472	AssertRC(rc);
2473	if (rc != VINF_SUCCESS)
2474	return rc;
2475	}
2476
2477	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2478	/* Check for dirty bit fault */
2479	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2480	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2481	Log(("PGMVerifyAccess: success (dirty)\n"));
2482	else
2483	{
2484	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2485	#else
2486	{
2487	GSTPDE PdeSrc;
2488	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2489	PdeSrc.n.u1Present = 1;
2490	PdeSrc.n.u1Write = 1;
2491	PdeSrc.n.u1Accessed = 1;
2492	PdeSrc.n.u1User = 1;
2493
2494	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2495	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2496	if (uErr & X86_TRAP_PF_US)
2497	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2498	else /* supervisor */
2499	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2500
2501	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2502	if (VBOX_SUCCESS(rc))
2503	{
2504	/* Page was successfully synced */
2505	Log2(("PGMVerifyAccess: success (sync)\n"));
2506	rc = VINF_SUCCESS;
2507	}
2508	else
2509	{
2510	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2511	return VINF_EM_RAW_GUEST_TRAP;
2512	}
2513	}
2514	return rc;
2515
2516	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2517
2518	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2519	return VERR_INTERNAL_ERROR;
2520	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2521	}
2522
2523
2524	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2525	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2526	/**
2527	* Figures out which kind of shadow page this guest PDE warrants.
2528	*
2529	* @returns Shadow page kind.
2530	* @param pPdeSrc The guest PDE in question.
2531	* @param cr4 The current guest cr4 value.
2532	*/
2533	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2534	{
2535	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2536	return BTH_PGMPOOLKIND_PT_FOR_PT;
2537	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2538	//{
2539	// case 0:
2540	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2541	// case X86_PDE4M_RW:
2542	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2543	// case X86_PDE4M_US:
2544	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2545	// case X86_PDE4M_RW \| X86_PDE4M_US:
2546	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2547	# if 0
2548	// case X86_PDE4M_PAE_NX:
2549	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2550	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2551	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2552	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2553	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2554	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2555	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2556	# endif
2557	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2558	//}
2559	}
2560	# endif
2561	#endif
2562
2563	#undef MY_STAM_COUNTER_INC
2564	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2565
2566
2567	/**
2568	* Syncs the paging hierarchy starting at CR3.
2569	*
2570	* @returns VBox status code, no specials.
2571	* @param pVM The virtual machine.
2572	* @param cr0 Guest context CR0 register
2573	* @param cr3 Guest context CR3 register
2574	* @param cr4 Guest context CR4 register
2575	* @param fGlobal Including global page directories or not
2576	*/
2577	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2578	{
2579	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2580	fGlobal = true; /* Change this CR3 reload to be a global one. */
2581
2582	/*
2583	* Update page access handlers.
2584	* The virtual are always flushed, while the physical are only on demand.
2585	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2586	* have to look into that later because it will have a bad influence on the performance.
2587	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2588	* bird: Yes, but that won't work for aliases.
2589	*/
2590	/** @todo this MUST go away. See #1557. */
2591	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2592	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2593	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2594
2595	#ifdef PGMPOOL_WITH_MONITORING
2596	/*
2597	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2598	* Occationally we will have to clear all the shadow page tables because we wanted
2599	* to monitor a page which was mapped by too many shadowed page tables. This operation
2600	* sometimes refered to as a 'lightweight flush'.
2601	*/
2602	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2603	pgmPoolMonitorModifiedClearAll(pVM);
2604	else
2605	{
2606	# ifdef IN_RING3
2607	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2608	pgmPoolClearAll(pVM);
2609	# else
2610	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2611	return VINF_PGM_SYNC_CR3;
2612	# endif
2613	}
2614	#endif
2615
2616	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2617	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2618
2619	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2620	/*
2621	* Get page directory addresses.
2622	*/
2623	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2624	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2625	# else
2626	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2627	# endif
2628
2629	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2630	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2631	Assert(pPDSrc);
2632	# ifndef IN_GC
2633	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2634	# endif
2635	# endif
2636
2637	/*
2638	* Iterate the page directory.
2639	*/
2640	PPGMMAPPING pMapping;
2641	unsigned iPdNoMapping;
2642	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2643	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2644
2645	/* Only check mappings if they are supposed to be put into the shadow page table. */
2646	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2647	{
2648	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2649	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2650	}
2651	else
2652	{
2653	pMapping = 0;
2654	iPdNoMapping = ~0U;
2655	}
2656	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2657	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2658	{
2659	unsigned iPDSrc;
2660	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2661	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_PAE_ENTRIES];
2662	# else
2663	AssertFailed(); /* @todo */
2664	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2665	# endif
2666	PX86PDEPAE pPDEDst = &pPDPAE->a[0];
2667	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2668
2669	if (pPDSrc == NULL)
2670	{
2671	/* PDPT not present */
2672	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 0;
2673	continue;
2674	}
2675	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2676	{
2677	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2678	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2679	{
2680	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2681	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2682	# else
2683	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2684	# endif
2685	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2686	if ( PdeSrc.n.u1Present
2687	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2688	{
2689	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2690	/*
2691	* Check for conflicts with GC mappings.
2692	*/
2693	if (iPD == iPdNoMapping)
2694	{
2695	if (pVM->pgm.s.fMappingsFixed)
2696	{
2697	/* It's fixed, just skip the mapping. */
2698	const unsigned cPTs = pMapping->cPTs;
2699	iPD += cPTs - 1;
2700	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2701	pMapping = pMapping->CTXALLSUFF(pNext);
2702	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2703	continue;
2704	}
2705	# ifdef IN_RING3
2706	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2707	if (VBOX_FAILURE(rc))
2708	return rc;
2709
2710	/*
2711	* Update iPdNoMapping and pMapping.
2712	*/
2713	pMapping = pVM->pgm.s.pMappingsR3;
2714	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2715	pMapping = pMapping->pNextR3;
2716	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2717	# else
2718	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2719	return VINF_PGM_SYNC_CR3;
2720	# endif
2721	}
2722	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2723	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2724	Assert(iPD != iPdNoMapping);
2725	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2726	/*
2727	* Sync page directory entry.
2728	*
2729	* The current approach is to allocated the page table but to set
2730	* the entry to not-present and postpone the page table synching till
2731	* it's actually used.
2732	*/
2733	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2734	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2735	# else
2736	const unsigned iPdShw = iPD; NOREF(iPdShw);
2737	# endif
2738	{
2739	SHWPDE PdeDst = *pPDEDst;
2740	if (PdeDst.n.u1Present)
2741	{
2742	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2743	RTGCPHYS GCPhys;
2744	if ( !PdeSrc.b.u1Size
2745	\|\| !(cr4 & X86_CR4_PSE))
2746	{
2747	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2748	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2749	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2750	GCPhys \|= i * (PAGE_SIZE / 2);
2751	# endif
2752	}
2753	else
2754	{
2755	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2756	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2757	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2758	GCPhys \|= i * X86_PAGE_2M_SIZE;
2759	# endif
2760	}
2761
2762	if ( pShwPage->GCPhys == GCPhys
2763	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2764	&& ( pShwPage->fCached
2765	\|\| ( !fGlobal
2766	&& ( false
2767	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2768	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2769	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2770	\|\| ( !pShwPage->fSeenNonGlobal
2771	&& (cr4 & X86_CR4_PGE))
2772	# endif
2773	)
2774	)
2775	)
2776	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2777	\|\| ( (cr4 & X86_CR4_PSE)
2778	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2779	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2780	)
2781	)
2782	{
2783	# ifdef VBOX_WITH_STATISTICS
2784	if ( !fGlobal
2785	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2786	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2787	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2788	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2789	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2790	else
2791	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2792	# endif /* VBOX_WITH_STATISTICS */
2793	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2794	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2795	//# ifdef PGMPOOL_WITH_CACHE
2796	// pgmPoolCacheUsed(pPool, pShwPage);
2797	//# endif
2798	}
2799	else
2800	{
2801	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2802	pPDEDst->u = 0;
2803	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2804	}
2805	}
2806	else
2807	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2808	pPDEDst++;
2809	}
2810	}
2811	else if (iPD != iPdNoMapping)
2812	{
2813	/*
2814	* Check if there is any page directory to mark not present here.
2815	*/
2816	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2817	const unsigned iPdShw = iPD; NOREF(iPdShw);
2818	# else
2819	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2820	# endif
2821	{
2822	if (pPDEDst->n.u1Present)
2823	{
2824	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2825	pPDEDst->u = 0;
2826	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2827	}
2828	pPDEDst++;
2829	}
2830	}
2831	else
2832	{
2833	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2834	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2835	const unsigned cPTs = pMapping->cPTs;
2836	if (pVM->pgm.s.fMappingsFixed)
2837	{
2838	/* It's fixed, just skip the mapping. */
2839	pMapping = pMapping->CTXALLSUFF(pNext);
2840	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2841	}
2842	else
2843	{
2844	/*
2845	* Check for conflicts for subsequent pagetables
2846	* and advance to the next mapping.
2847	*/
2848	iPdNoMapping = ~0U;
2849	unsigned iPT = cPTs;
2850	while (iPT-- > 1)
2851	{
2852	if ( pPDSrc->a[iPD + iPT].n.u1Present
2853	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2854	{
2855	# ifdef IN_RING3
2856	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2857	if (VBOX_FAILURE(rc))
2858	return rc;
2859
2860	/*
2861	* Update iPdNoMapping and pMapping.
2862	*/
2863	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2864	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2865	pMapping = pMapping->CTXALLSUFF(pNext);
2866	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2867	break;
2868	# else
2869	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2870	return VINF_PGM_SYNC_CR3;
2871	# endif
2872	}
2873	}
2874	if (iPdNoMapping == ~0U && pMapping)
2875	{
2876	pMapping = pMapping->CTXALLSUFF(pNext);
2877	if (pMapping)
2878	iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2879	}
2880	}
2881
2882	/* advance. */
2883	iPD += cPTs - 1;
2884	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2885	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2886	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2887	AssertFailed();
2888	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2889	}
2890
2891	} /* for iPD */
2892	} /* for each PDPTE (PAE) */
2893
2894	return VINF_SUCCESS;
2895
2896	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2897	//# error not implemented
2898	return VERR_INTERNAL_ERROR;
2899	#else /* guest real and protected mode */
2900	return VINF_SUCCESS;
2901	#endif
2902	}
2903
2904
2905
2906
2907	#ifdef VBOX_STRICT
2908	#ifdef IN_GC
2909	# undef AssertMsgFailed
2910	# define AssertMsgFailed Log
2911	#endif
2912	#ifdef IN_RING3
2913	# include <VBox/dbgf.h>
2914
2915	/**
2916	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2917	*
2918	* @returns VBox status code (VINF_SUCCESS).
2919	* @param pVM The VM handle.
2920	* @param cr3 The root of the hierarchy.
2921	* @param crr The cr4, only PAE and PSE is currently used.
2922	* @param fLongMode Set if long mode, false if not long mode.
2923	* @param cMaxDepth Number of levels to dump.
2924	* @param pHlp Pointer to the output functions.
2925	*/
2926	__BEGIN_DECLS
2927	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2928	__END_DECLS
2929
2930	#endif
2931
2932	/**
2933	* Checks that the shadow page table is in sync with the guest one.
2934	*
2935	* @returns The number of errors.
2936	* @param pVM The virtual machine.
2937	* @param cr3 Guest context CR3 register
2938	* @param cr4 Guest context CR4 register
2939	* @param GCPtr Where to start. Defaults to 0.
2940	* @param cb How much to check. Defaults to everything.
2941	*/
2942	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2943	{
2944	unsigned cErrors = 0;
2945
2946	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2947	PPGM pPGM = &pVM->pgm.s;
2948	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2949	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2950	RTHCPHYS HCPhys; /* general usage. */
2951	int rc;
2952
2953	/*
2954	* Check that the Guest CR3 and all it's mappings are correct.
2955	*/
2956	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2957	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2958	false);
2959	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2960	AssertRCReturn(rc, 1);
2961	HCPhys = NIL_RTHCPHYS;
2962	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2963	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2964	# ifdef IN_RING3
2965	RTGCPHYS GCPhys;
2966	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2967	AssertRCReturn(rc, 1);
2968	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2969	# endif
2970	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2971
2972	/*
2973	* Get and check the Shadow CR3.
2974	*/
2975	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2976	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2977	unsigned cPDEs = ELEMENTS(pPDDst->a);
2978	# else
2979	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2980	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2981	# endif
2982	if (cb != ~(RTGCUINTPTR)0)
2983	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2984
2985	/** @todo call the other two PGMAssert() functions. /
2986
2987	/*
2988	* Iterate the shadow page directory.
2989	*/
2990	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2991	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2992	cPDEs += iPDDst;
2993	for (;
2994	iPDDst < cPDEs;
2995	iPDDst++, GCPtr += _4G / cPDEs)
2996	{
2997	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2998	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2999	{
3000	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3001	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3002	{
3003	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3004	cErrors++;
3005	continue;
3006	}
3007	}
3008	else if ( (PdeDst.u & X86_PDE_P)
3009	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3010	)
3011	{
3012	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3013	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3014	if (!pPoolPage)
3015	{
3016	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3017	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3018	cErrors++;
3019	continue;
3020	}
3021	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3022
3023	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3024	{
3025	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3026	GCPtr, (uint64_t)PdeDst.u));
3027	cErrors++;
3028	}
3029
3030	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3031	{
3032	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3033	GCPtr, (uint64_t)PdeDst.u));
3034	cErrors++;
3035	}
3036
3037	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
3038	if (!PdeSrc.n.u1Present)
3039	{
3040	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3041	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3042	cErrors++;
3043	continue;
3044	}
3045
3046	if ( !PdeSrc.b.u1Size
3047	\|\| !(cr4 & X86_CR4_PSE))
3048	{
3049	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3050	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3051	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3052	# endif
3053	}
3054	else
3055	{
3056	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3057	{
3058	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3059	GCPtr, (uint64_t)PdeSrc.u));
3060	cErrors++;
3061	continue;
3062	}
3063	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3064	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3065	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3066	# endif
3067	}
3068
3069	if ( pPoolPage->enmKind
3070	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3071	{
3072	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3073	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3074	cErrors++;
3075	}
3076
3077	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3078	if (!pPhysPage)
3079	{
3080	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3081	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3082	cErrors++;
3083	continue;
3084	}
3085
3086	if (GCPhysGst != pPoolPage->GCPhys)
3087	{
3088	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3089	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3090	cErrors++;
3091	continue;
3092	}
3093
3094	if ( !PdeSrc.b.u1Size
3095	\|\| !(cr4 & X86_CR4_PSE))
3096	{
3097	/*
3098	* Page Table.
3099	*/
3100	const GSTPT *pPTSrc;
3101	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3102	if (VBOX_FAILURE(rc))
3103	{
3104	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3105	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3106	cErrors++;
3107	continue;
3108	}
3109	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3110	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3111	{
3112	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3113	// (This problem will go away when/if we shadow multiple CR3s.)
3114	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3115	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3116	cErrors++;
3117	continue;
3118	}
3119	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3120	{
3121	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3122	GCPtr, (uint64_t)PdeDst.u));
3123	cErrors++;
3124	continue;
3125	}
3126
3127	/* iterate the page table. */
3128	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3129	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3130	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3131	# else
3132	const unsigned offPTSrc = 0;
3133	# endif
3134	for (unsigned iPT = 0, off = 0;
3135	iPT < ELEMENTS(pPTDst->a);
3136	iPT++, off += PAGE_SIZE)
3137	{
3138	const SHWPTE PteDst = pPTDst->a[iPT];
3139
3140	/* skip not-present entries. */
3141	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3142	continue;
3143	Assert(PteDst.n.u1Present);
3144
3145	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3146	if (!PteSrc.n.u1Present)
3147	{
3148	#ifdef IN_RING3
3149	PGMAssertHandlerAndFlagsInSync(pVM);
3150	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3151	#endif
3152	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3153	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3154	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3155	cErrors++;
3156	continue;
3157	}
3158
3159	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3160	# if 1 /** @todo sync accessed bit properly... */
3161	fIgnoreFlags \|= X86_PTE_A;
3162	# endif
3163
3164	/* match the physical addresses */
3165	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3166	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3167
3168	# ifdef IN_RING3
3169	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3170	if (VBOX_FAILURE(rc))
3171	{
3172	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3173	{
3174	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3175	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3176	cErrors++;
3177	continue;
3178	}
3179	}
3180	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3181	{
3182	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3183	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3184	cErrors++;
3185	continue;
3186	}
3187	# endif
3188
3189	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3190	if (!pPhysPage)
3191	{
3192	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3193	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3194	{
3195	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3196	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3197	cErrors++;
3198	continue;
3199	}
3200	# endif
3201	if (PteDst.n.u1Write)
3202	{
3203	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3204	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3205	cErrors++;
3206	}
3207	fIgnoreFlags \|= X86_PTE_RW;
3208	}
3209	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3210	{
3211	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3212	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3213	cErrors++;
3214	continue;
3215	}
3216
3217	/* flags */
3218	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3219	{
3220	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3221	{
3222	if (PteDst.n.u1Write)
3223	{
3224	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3225	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3226	cErrors++;
3227	continue;
3228	}
3229	fIgnoreFlags \|= X86_PTE_RW;
3230	}
3231	else
3232	{
3233	if (PteDst.n.u1Present)
3234	{
3235	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3236	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3237	cErrors++;
3238	continue;
3239	}
3240	fIgnoreFlags \|= X86_PTE_P;
3241	}
3242	}
3243	else
3244	{
3245	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3246	{
3247	if (PteDst.n.u1Write)
3248	{
3249	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3250	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3251	cErrors++;
3252	continue;
3253	}
3254	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3255	{
3256	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3257	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3258	cErrors++;
3259	continue;
3260	}
3261	if (PteDst.n.u1Dirty)
3262	{
3263	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3264	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3265	cErrors++;
3266	}
3267	# if 0 /** @todo sync access bit properly... */
3268	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3269	{
3270	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3271	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3272	cErrors++;
3273	}
3274	fIgnoreFlags \|= X86_PTE_RW;
3275	# else
3276	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3277	# endif
3278	}
3279	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3280	{
3281	/* access bit emulation (not implemented). */
3282	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3283	{
3284	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3285	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3286	cErrors++;
3287	continue;
3288	}
3289	if (!PteDst.n.u1Accessed)
3290	{
3291	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3292	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3293	cErrors++;
3294	}
3295	fIgnoreFlags \|= X86_PTE_P;
3296	}
3297	# ifdef DEBUG_sandervl
3298	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3299	# endif
3300	}
3301
3302	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3303	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3304	)
3305	{
3306	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3307	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3308	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3309	cErrors++;
3310	continue;
3311	}
3312	} /* foreach PTE */
3313	}
3314	else
3315	{
3316	/*
3317	* Big Page.
3318	*/
3319	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3320	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3321	{
3322	if (PdeDst.n.u1Write)
3323	{
3324	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3325	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3326	cErrors++;
3327	continue;
3328	}
3329	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3330	{
3331	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3332	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3333	cErrors++;
3334	continue;
3335	}
3336	# if 0 /** @todo sync access bit properly... */
3337	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3338	{
3339	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3340	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3341	cErrors++;
3342	}
3343	fIgnoreFlags \|= X86_PTE_RW;
3344	# else
3345	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3346	# endif
3347	}
3348	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3349	{
3350	/* access bit emulation (not implemented). */
3351	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3352	{
3353	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3354	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3355	cErrors++;
3356	continue;
3357	}
3358	if (!PdeDst.n.u1Accessed)
3359	{
3360	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3361	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3362	cErrors++;
3363	}
3364	fIgnoreFlags \|= X86_PTE_P;
3365	}
3366
3367	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3368	{
3369	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3370	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3371	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3372	cErrors++;
3373	}
3374
3375	/* iterate the page table. */
3376	for (unsigned iPT = 0, off = 0;
3377	iPT < ELEMENTS(pPTDst->a);
3378	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3379	{
3380	const SHWPTE PteDst = pPTDst->a[iPT];
3381
3382	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3383	{
3384	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3385	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3386	cErrors++;
3387	}
3388
3389	/* skip not-present entries. */
3390	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3391	continue;
3392
3393	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3394
3395	/* match the physical addresses */
3396	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3397
3398	# ifdef IN_RING3
3399	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3400	if (VBOX_FAILURE(rc))
3401	{
3402	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3403	{
3404	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3405	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3406	cErrors++;
3407	}
3408	}
3409	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3410	{
3411	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3412	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3413	cErrors++;
3414	continue;
3415	}
3416	# endif
3417
3418	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3419	if (!pPhysPage)
3420	{
3421	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3422	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3423	{
3424	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3425	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3426	cErrors++;
3427	continue;
3428	}
3429	# endif
3430	if (PteDst.n.u1Write)
3431	{
3432	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3433	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3434	cErrors++;
3435	}
3436	fIgnoreFlags \|= X86_PTE_RW;
3437	}
3438	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3439	{
3440	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3441	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3442	cErrors++;
3443	continue;
3444	}
3445
3446	/* flags */
3447	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3448	{
3449	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3450	{
3451	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3452	{
3453	if (PteDst.n.u1Write)
3454	{
3455	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3456	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3457	cErrors++;
3458	continue;
3459	}
3460	fIgnoreFlags \|= X86_PTE_RW;
3461	}
3462	}
3463	else
3464	{
3465	if (PteDst.n.u1Present)
3466	{
3467	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3468	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3469	cErrors++;
3470	continue;
3471	}
3472	fIgnoreFlags \|= X86_PTE_P;
3473	}
3474	}
3475
3476	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3477	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3478	)
3479	{
3480	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3481	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3482	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3483	cErrors++;
3484	continue;
3485	}
3486	} /* foreach PTE */
3487	}
3488	}
3489	/* not present */
3490
3491	} /* forearch PDE */
3492
3493	# ifdef DEBUG
3494	if (cErrors)
3495	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3496	# endif
3497
3498	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3499	//# error not implemented
3500
3501
3502	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3503	//# error not implemented
3504
3505	/#else: guest real and protected mode /
3506	#endif
3507	return cErrors;
3508	}
3509	#endif /* VBOX_STRICT */
3510

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7730

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