PGMAllBth.h@ 7804

Last change on this file since 7804 was 7804, checked in by vboxsync, 17 years ago
NXE correction
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File size: 152.9 KB

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1	/* $Id: PGMAllBth.h 7804 2008-04-08 13:34:26Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
42	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
43	#error "Invalid combination; PAE guest implies PAE shadow"
44	#endif
45
46	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
47	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
48	#error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
53	#error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
57	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
58	#error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
59	#endif
60
61	/**
62	* #PF Handler for raw-mode guest execution.
63	*
64	* @returns VBox status code (appropriate for trap handling and GC return).
65	* @param pVM VM Handle.
66	* @param uErr The trap error code.
67	* @param pRegFrame Trap register frame.
68	* @param pvFault The fault address.
69	*/
70	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
71	{
72	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
73
74	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
75	/*
76	* Hide the instruction fetch trap indicator for now.
77	*/
78	/** @todo NXE will change this and we must fix NXE in the switcher too! */
79	if (uErr & X86_TRAP_PF_ID)
80	{
81	uErr &= ~X86_TRAP_PF_ID;
82	TRPMSetErrorCode(pVM, uErr);
83	}
84	# endif
85
86	/*
87	* Get PDs.
88	*/
89	int rc;
90	# if PGM_WITH_PAGING(PGM_GST_TYPE)
91	# if PGM_GST_TYPE == PGM_TYPE_32BIT
92	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
93	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
94	# else /* PAE */
95	unsigned iPDSrc;
96	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
97	# endif
98	# else
99	PGSTPD pPDSrc = NULL;
100	const unsigned iPDSrc = 0;
101	# endif
102
103	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
104	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
105	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
106	# else /* PAE */
107	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
108	# endif
109
110	# if PGM_WITH_PAGING(PGM_GST_TYPE)
111	# ifdef PGM_SYNC_DIRTY_BIT
112	/*
113	* If we successfully correct the write protection fault due to dirty bit
114	* tracking, or this page fault is a genuine one, then return immediately.
115	*/
116	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
117	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
118	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
119	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
120	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
121	{
122	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
123	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
124	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
125	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
126	}
127	# endif
128
129	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
130	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
131
132	/*
133	* A common case is the not-present error caused by lazy page table syncing.
134	*
135	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
136	* so we can safely assume that the shadow PT is present when calling SyncPage later.
137	*
138	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
139	* of mapping conflict and defer to SyncCR3 in R3.
140	* (Again, we do NOT support access handlers for non-present guest pages.)
141	*
142	*/
143	# if PGM_WITH_PAGING(PGM_GST_TYPE)
144	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
145	# else
146	GSTPDE PdeSrc;
147	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
148	PdeSrc.n.u1Present = 1;
149	PdeSrc.n.u1Write = 1;
150	PdeSrc.n.u1Accessed = 1;
151	PdeSrc.n.u1User = 1;
152	# endif
153	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
154	&& !pPDDst->a[iPDDst].n.u1Present
155	&& PdeSrc.n.u1Present
156	)
157
158	{
159	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
160	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
161	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
162	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
163	if (VBOX_SUCCESS(rc))
164	{
165	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
166	return rc;
167	}
168	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
169	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
170	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
171	return VINF_PGM_SYNC_CR3;
172	}
173
174	# if PGM_WITH_PAGING(PGM_GST_TYPE)
175	/*
176	* Check if this address is within any of our mappings.
177	*
178	* This is very fast and it's gonna save us a bit of effort below and prevent
179	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
180	* (BTW, it's impossible to have physical access handlers in a mapping.)
181	*/
182	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
183	{
184	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
185	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
186	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
187	{
188	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
189	break;
190	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
191	{
192	/*
193	* The first thing we check is if we've got an undetected conflict.
194	*/
195	if (!pVM->pgm.s.fMappingsFixed)
196	{
197	unsigned iPT = pMapping->cPTs;
198	while (iPT-- > 0)
199	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
200	{
201	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
202	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
203	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
204	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
205	return VINF_PGM_SYNC_CR3;
206	}
207	}
208
209	/*
210	* Check if the fault address is in a virtual page access handler range.
211	*/
212	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
213	if ( pCur
214	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
215	&& uErr & X86_TRAP_PF_RW)
216	{
217	# ifdef IN_GC
218	STAM_PROFILE_START(&pCur->Stat, h);
219	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
220	STAM_PROFILE_STOP(&pCur->Stat, h);
221	# else
222	AssertFailed();
223	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
224	# endif
225	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
226	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
227	return rc;
228	}
229
230	/*
231	* Pretend we're not here and let the guest handle the trap.
232	*/
233	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
234	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
235	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
236	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
237	return VINF_EM_RAW_GUEST_TRAP;
238	}
239	}
240	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
241	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
242	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
243
244	/*
245	* Check if this fault address is flagged for special treatment,
246	* which means we'll have to figure out the physical address and
247	* check flags associated with it.
248	*
249	* ASSUME that we can limit any special access handling to pages
250	* in page tables which the guest believes to be present.
251	*/
252	if (PdeSrc.n.u1Present)
253	{
254	RTGCPHYS GCPhys = NIL_RTGCPHYS;
255
256	# if PGM_WITH_PAGING(PGM_GST_TYPE)
257	uint32_t cr4 = CPUMGetGuestCR4(pVM);
258	if ( PdeSrc.b.u1Size
259	&& (cr4 & X86_CR4_PSE))
260	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
261	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
262	else
263	{
264	PGSTPT pPTSrc;
265	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
266	if (VBOX_SUCCESS(rc))
267	{
268	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
269	if (pPTSrc->a[iPTESrc].n.u1Present)
270	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
271	}
272	}
273	# else
274	/* No paging so the fault address is the physical address */
275	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
276	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
277
278	/*
279	* If we have a GC address we'll check if it has any flags set.
280	*/
281	if (GCPhys != NIL_RTGCPHYS)
282	{
283	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
284
285	PPGMPAGE pPage;
286	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
287	if (VBOX_SUCCESS(rc))
288	{
289	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
290	{
291	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
292	{
293	/*
294	* Physical page access handler.
295	*/
296	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
297	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
298	if (pCur)
299	{
300	# ifdef PGM_SYNC_N_PAGES
301	/*
302	* If the region is write protected and we got a page not present fault, then sync
303	* the pages. If the fault was caused by a read, then restart the instruction.
304	* In case of write access continue to the GC write handler.
305	*
306	* ASSUMES that there is only one handler per page or that they have similar write properties.
307	*/
308	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
309	&& !(uErr & X86_TRAP_PF_P))
310	{
311	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
312	if ( VBOX_FAILURE(rc)
313	\|\| !(uErr & X86_TRAP_PF_RW)
314	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
315	{
316	AssertRC(rc);
317	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
318	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
319	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
320	return rc;
321	}
322	}
323	# endif
324
325	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
326	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
327	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
328
329	#if defined(IN_GC) \|\| defined(IN_RING0)
330	if (CTXALLSUFF(pCur->pfnHandler))
331	{
332	STAM_PROFILE_START(&pCur->Stat, h);
333	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
334	STAM_PROFILE_STOP(&pCur->Stat, h);
335	}
336	else
337	#endif
338	rc = VINF_EM_RAW_EMULATE_INSTR;
339	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
340	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
341	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
342	return rc;
343	}
344	}
345	# if PGM_WITH_PAGING(PGM_GST_TYPE)
346	else
347	{
348	# ifdef PGM_SYNC_N_PAGES
349	/*
350	* If the region is write protected and we got a page not present fault, then sync
351	* the pages. If the fault was caused by a read, then restart the instruction.
352	* In case of write access continue to the GC write handler.
353	*/
354	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
355	&& !(uErr & X86_TRAP_PF_P))
356	{
357	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
358	if ( VBOX_FAILURE(rc)
359	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
360	\|\| !(uErr & X86_TRAP_PF_RW))
361	{
362	AssertRC(rc);
363	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
364	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
365	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
366	return rc;
367	}
368	}
369	# endif
370	/*
371	* Ok, it's an virtual page access handler.
372	*
373	* Since it's faster to search by address, we'll do that first
374	* and then retry by GCPhys if that fails.
375	*/
376	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
377	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
378	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
379	*/
380	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
381	if (pCur)
382	{
383	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
384	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
385	\|\| !(uErr & X86_TRAP_PF_P)
386	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
387	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
388
389	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
390	&& ( uErr & X86_TRAP_PF_RW
391	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
392	{
393	# ifdef IN_GC
394	STAM_PROFILE_START(&pCur->Stat, h);
395	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
396	STAM_PROFILE_STOP(&pCur->Stat, h);
397	# else
398	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
399	# endif
400	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
401	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
402	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
403	return rc;
404	}
405	/* Unhandled part of a monitored page */
406	}
407	else
408	{
409	/* Check by physical address. */
410	PPGMVIRTHANDLER pCur;
411	unsigned iPage;
412	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
413	&pCur, &iPage);
414	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
415	if ( pCur
416	&& ( uErr & X86_TRAP_PF_RW
417	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
418	{
419	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
420	# ifdef IN_GC
421	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
422	Assert(off < pCur->cb);
423	STAM_PROFILE_START(&pCur->Stat, h);
424	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
425	STAM_PROFILE_STOP(&pCur->Stat, h);
426	# else
427	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
428	# endif
429	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
430	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
431	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
432	return rc;
433	}
434	}
435	}
436	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
437
438	/*
439	* There is a handled area of the page, but this fault doesn't belong to it.
440	* We must emulate the instruction.
441	*
442	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
443	* we first check if this was a page-not-present fault for a page with only
444	* write access handlers. Restart the instruction if it wasn't a write access.
445	*/
446	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
447
448	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
449	&& !(uErr & X86_TRAP_PF_P))
450	{
451	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
452	if ( VBOX_FAILURE(rc)
453	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
454	\|\| !(uErr & X86_TRAP_PF_RW))
455	{
456	AssertRC(rc);
457	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
458	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
459	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
460	return rc;
461	}
462	}
463
464	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
465	* It's writing to an unhandled part of the LDT page several million times.
466	*/
467	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
468	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
469	rc, pPage->HCPhys,
470	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
471	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
472	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
473	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
474	return rc;
475	} /* if any kind of handler */
476
477	# if PGM_WITH_PAGING(PGM_GST_TYPE)
478	if (uErr & X86_TRAP_PF_P)
479	{
480	/*
481	* The page isn't marked, but it might still be monitored by a virtual page access handler.
482	* (ASSUMES no temporary disabling of virtual handlers.)
483	*/
484	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
485	* we should correct both the shadow page table and physical memory flags, and not only check for
486	* accesses within the handler region but for access to pages with virtual handlers. */
487	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
488	if (pCur)
489	{
490	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
491	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
492	\|\| !(uErr & X86_TRAP_PF_P)
493	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
494	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
495
496	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
497	&& ( uErr & X86_TRAP_PF_RW
498	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
499	{
500	# ifdef IN_GC
501	STAM_PROFILE_START(&pCur->Stat, h);
502	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
503	STAM_PROFILE_STOP(&pCur->Stat, h);
504	# else
505	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
506	# endif
507	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
508	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
509	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
510	return rc;
511	}
512	}
513	}
514	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
515	}
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
517
518	# ifdef PGM_OUT_OF_SYNC_IN_GC
519	/*
520	* We are here only if page is present in Guest page tables and trap is not handled
521	* by our handlers.
522	* Check it for page out-of-sync situation.
523	*/
524	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
525
526	if (!(uErr & X86_TRAP_PF_P))
527	{
528	/*
529	* Page is not present in our page tables.
530	* Try to sync it!
531	* BTW, fPageShw is invalid in this branch!
532	*/
533	if (uErr & X86_TRAP_PF_US)
534	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
535	else /* supervisor */
536	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
537
538	# if defined(LOG_ENABLED) && !defined(IN_RING0)
539	RTGCPHYS GCPhys;
540	uint64_t fPageGst;
541	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
542	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
543	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
544	# endif /* LOG_ENABLED */
545
546	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
547	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
548	{
549	uint64_t fPageGst;
550	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
551	if ( VBOX_SUCCESS(rc)
552	&& !(fPageGst & X86_PTE_US))
553	{
554	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
555	if ( pvFault == (RTGCPTR)pRegFrame->eip
556	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
557	# ifdef CSAM_DETECT_NEW_CODE_PAGES
558	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
559	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
560	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
561	)
562	{
563	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
564	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
565	if (rc != VINF_SUCCESS)
566	{
567	/*
568	* CSAM needs to perform a job in ring 3.
569	*
570	* Sync the page before going to the host context; otherwise we'll end up in a loop if
571	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
572	*/
573	LogFlow(("CSAM ring 3 job\n"));
574	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
575	AssertRC(rc2);
576
577	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
578	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
579	return rc;
580	}
581	}
582	# ifdef CSAM_DETECT_NEW_CODE_PAGES
583	else
584	if ( uErr == X86_TRAP_PF_RW
585	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
586	&& pRegFrame->ecx < 0x10000
587	)
588	{
589	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
590	* to detect loading of new code pages.
591	*/
592
593	/*
594	* Decode the instruction.
595	*/
596	RTGCPTR PC;
597	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
598	if (rc == VINF_SUCCESS)
599	{
600	DISCPUSTATE Cpu;
601	uint32_t cbOp;
602	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
603
604	/* For now we'll restrict this to rep movsw/d instructions */
605	if ( rc == VINF_SUCCESS
606	&& Cpu.pCurInstr->opcode == OP_MOVSWD
607	&& (Cpu.prefix & PREFIX_REP))
608	{
609	CSAMMarkPossibleCodePage(pVM, pvFault);
610	}
611	}
612	}
613	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
614
615	/*
616	* Mark this page as safe.
617	*/
618	/** @todo not correct for pages that contain both code and data!! */
619	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
620	CSAMMarkPage(pVM, pvFault, true);
621	}
622	}
623	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
624	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
625	if (VBOX_SUCCESS(rc))
626	{
627	/* The page was successfully synced, return to the guest. */
628	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
629	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
630	return VINF_SUCCESS;
631	}
632	}
633	else
634	{
635	/*
636	* A side effect of not flushing global PDEs are out of sync pages due
637	* to physical monitored regions, that are no longer valid.
638	* Assume for now it only applies to the read/write flag
639	*/
640	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
641	{
642	if (uErr & X86_TRAP_PF_US)
643	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
644	else /* supervisor */
645	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
646
647
648	/*
649	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
650	*/
651	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
652	if (VBOX_SUCCESS(rc))
653	{
654	/*
655	* Page was successfully synced, return to guest.
656	*/
657	# ifdef VBOX_STRICT
658	RTGCPHYS GCPhys;
659	uint64_t fPageGst;
660	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
661	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
662	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
663
664	uint64_t fPageShw;
665	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
666	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
667	# endif /* VBOX_STRICT */
668	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
669	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
670	return VINF_SUCCESS;
671	}
672
673	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
674	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
675	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
676	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
677	{
678	uint64_t fPageGst;
679	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
680	if ( VBOX_SUCCESS(rc)
681	&& !(fPageGst & X86_PTE_RW))
682	{
683	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
684	if (VBOX_SUCCESS(rc))
685	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
686	else
687	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
688	return rc;
689	}
690	else
691	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
692	}
693
694	}
695
696	# if PGM_WITH_PAGING(PGM_GST_TYPE)
697	# ifdef VBOX_STRICT
698	/*
699	* Check for VMM page flags vs. Guest page flags consistency.
700	* Currently only for debug purposes.
701	*/
702	if (VBOX_SUCCESS(rc))
703	{
704	/* Get guest page flags. */
705	uint64_t fPageGst;
706	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
707	if (VBOX_SUCCESS(rc))
708	{
709	uint64_t fPageShw;
710	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
711
712	/*
713	* Compare page flags.
714	* Note: we have AVL, A, D bits desynched.
715	*/
716	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
717	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
718	}
719	else
720	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
721	}
722	else
723	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
724	# endif /* VBOX_STRICT */
725	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
726	}
727	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
728	# endif /* PGM_OUT_OF_SYNC_IN_GC */
729	}
730	else
731	{
732	/*
733	* Page not present in Guest OS or invalid page table address.
734	* This is potential virtual page access handler food.
735	*
736	* For the present we'll say that our access handlers don't
737	* work for this case - we've already discarded the page table
738	* not present case which is identical to this.
739	*
740	* When we perchance find we need this, we will probably have AVL
741	* trees (offset based) to operate on and we can measure their speed
742	* agains mapping a page table and probably rearrange this handling
743	* a bit. (Like, searching virtual ranges before checking the
744	* physical address.)
745	*/
746	}
747	}
748
749
750	# if PGM_WITH_PAGING(PGM_GST_TYPE)
751	/*
752	* Conclusion, this is a guest trap.
753	*/
754	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
755	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
756	return VINF_EM_RAW_GUEST_TRAP;
757	# else
758	/* present, but not a monitored page; perhaps the guest is probing physical memory */
759	return VINF_EM_RAW_EMULATE_INSTR;
760	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
761
762
763	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
764
765	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
766	return VERR_INTERNAL_ERROR;
767	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
768	}
769
770
771	/**
772	* Emulation of the invlpg instruction.
773	*
774	*
775	* @returns VBox status code.
776	*
777	* @param pVM VM handle.
778	* @param GCPtrPage Page to invalidate.
779	*
780	* @remark ASSUMES that the guest is updating before invalidating. This order
781	* isn't required by the CPU, so this is speculative and could cause
782	* trouble.
783	*
784	* @todo Flush page or page directory only if necessary!
785	* @todo Add a #define for simply invalidating the page.
786	*/
787	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
788	{
789	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
790	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
791
792	LogFlow(("InvalidatePage %x\n", GCPtrPage));
793	/*
794	* Get the shadow PD entry and skip out if this PD isn't present.
795	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
796	*/
797	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
798	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
799	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
800	# else
801	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
802	# endif
803	const SHWPDE PdeDst = *pPdeDst;
804	if (!PdeDst.n.u1Present)
805	{
806	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
807	return VINF_SUCCESS;
808	}
809
810	/*
811	* Get the guest PD entry and calc big page.
812	*/
813	# if PGM_GST_TYPE == PGM_TYPE_32BIT
814	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
815	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
816	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
817	# else /* PAE */
818	unsigned iPDSrc;
819	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
820	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
821	# endif
822
823	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
824	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
825
826	# ifdef IN_RING3
827	/*
828	* If a CR3 Sync is pending we may ignore the invalidate page operation
829	* depending on the kind of sync and if it's a global page or not.
830	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
831	*/
832	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
833	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
834	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
835	&& fIsBigPage
836	&& PdeSrc.b.u1Global
837	&& (cr4 & X86_CR4_PGE)
838	)
839	)
840	# else
841	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
842	# endif
843	{
844	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
845	return VINF_SUCCESS;
846	}
847	# endif /* IN_RING3 */
848
849
850	/*
851	* Deal with the Guest PDE.
852	*/
853	int rc = VINF_SUCCESS;
854	if (PdeSrc.n.u1Present)
855	{
856	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
857	{
858	/*
859	* Conflict - Let SyncPT deal with it to avoid duplicate code.
860	*/
861	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
862	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
863	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
864	}
865	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
866	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
867	{
868	/*
869	* Mark not present so we can resync the PDE when it's used.
870	*/
871	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
872	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
873	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
874	pPdeDst->u = 0;
875	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
876	PGM_INVL_GUEST_TLBS();
877	}
878	# ifdef PGM_SYNC_ACCESSED_BIT
879	else if (!PdeSrc.n.u1Accessed)
880	{
881	/*
882	* Mark not present so we can set the accessed bit.
883	*/
884	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
885	pPdeDst->u = 0;
886	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
887	PGM_INVL_GUEST_TLBS();
888	}
889	# endif
890	else if (!fIsBigPage)
891	{
892	/*
893	* 4KB - page.
894	*/
895	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
896	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
897	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
898	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
899	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
900	# endif
901	if (pShwPage->GCPhys == GCPhys)
902	{
903	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
904	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
905	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
906	if (pPT->a[iPTEDst].n.u1Present)
907	{
908	# ifdef PGMPOOL_WITH_USER_TRACKING
909	/* This is very unlikely with caching/monitoring enabled. */
910	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
911	# endif
912	pPT->a[iPTEDst].u = 0;
913	}
914	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
915	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
916	if (VBOX_SUCCESS(rc))
917	rc = VINF_SUCCESS;
918	# endif
919	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
920	PGM_INVL_PG(GCPtrPage);
921	}
922	else
923	{
924	/*
925	* The page table address changed.
926	*/
927	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
928	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
929	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
930	pPdeDst->u = 0;
931	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
932	PGM_INVL_GUEST_TLBS();
933	}
934	}
935	else
936	{
937	/*
938	* 4MB - page.
939	*/
940	/* Before freeing the page, check if anything really changed. */
941	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
942	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
943	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
944	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
945	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
946	# endif
947	if ( pShwPage->GCPhys == GCPhys
948	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
949	{
950	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
951	/** @todo PAT */
952	# ifdef PGM_SYNC_DIRTY_BIT
953	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
954	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
955	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
956	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
957	# else
958	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
959	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
960	# endif
961	{
962	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
963	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
964	return VINF_SUCCESS;
965	}
966	}
967
968	/*
969	* Ok, the page table is present and it's been changed in the guest.
970	* If we're in host context, we'll just mark it as not present taking the lazy approach.
971	* We could do this for some flushes in GC too, but we need an algorithm for
972	* deciding which 4MB pages containing code likely to be executed very soon.
973	*/
974	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
975	pPdeDst->u = 0;
976	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
977	PGM_INVL_BIG_PG(GCPtrPage);
978	}
979	}
980	else
981	{
982	/*
983	* Page directory is not present, mark shadow PDE not present.
984	*/
985	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
986	{
987	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
988	pPdeDst->u = 0;
989	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
990	PGM_INVL_PG(GCPtrPage);
991	}
992	else
993	{
994	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
995	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
996	}
997	}
998
999	return rc;
1000
1001	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1002	//# error not implemented
1003	return VERR_INTERNAL_ERROR;
1004
1005	#else /* guest real and protected mode */
1006	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1007	return VINF_SUCCESS;
1008	#endif
1009	}
1010
1011
1012	#ifdef PGMPOOL_WITH_USER_TRACKING
1013	/**
1014	* Update the tracking of shadowed pages.
1015	*
1016	* @param pVM The VM handle.
1017	* @param pShwPage The shadow page.
1018	* @param HCPhys The physical page we is being dereferenced.
1019	*/
1020	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1021	{
1022	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1023	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1024	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1025
1026	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1027	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1028	* 2. write protect all shadowed pages. I.e. implement caching.
1029	*/
1030	/*
1031	* Find the guest address.
1032	*/
1033	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1034	pRam;
1035	pRam = CTXALLSUFF(pRam->pNext))
1036	{
1037	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1038	while (iPage-- > 0)
1039	{
1040	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1041	{
1042	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1043	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1044	pShwPage->cPresent--;
1045	pPool->cPresent--;
1046	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1047	return;
1048	}
1049	}
1050	}
1051
1052	for (;;)
1053	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1054	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1055	pShwPage->cPresent--;
1056	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1057	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1058	}
1059
1060
1061	/**
1062	* Update the tracking of shadowed pages.
1063	*
1064	* @param pVM The VM handle.
1065	* @param pShwPage The shadow page.
1066	* @param u16 The top 16-bit of the pPage->HCPhys.
1067	* @param pPage Pointer to the guest page. this will be modified.
1068	* @param iPTDst The index into the shadow table.
1069	*/
1070	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1071	{
1072	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1073	/*
1074	* We're making certain assumptions about the placement of cRef and idx.
1075	*/
1076	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1077	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1078
1079	/*
1080	* Just deal with the simple first time here.
1081	*/
1082	if (!u16)
1083	{
1084	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1085	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1086	}
1087	else
1088	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1089
1090	/* write back, trying to be clever... */
1091	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1092	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1093	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1094	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1095
1096	/* update statistics. */
1097	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1098	pShwPage->cPresent++;
1099	if (pShwPage->iFirstPresent > iPTDst)
1100	pShwPage->iFirstPresent = iPTDst;
1101	}
1102	#endif /* PGMPOOL_WITH_USER_TRACKING */
1103
1104
1105	/**
1106	* Creates a 4K shadow page for a guest page.
1107	*
1108	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1109	* physical address. The PdeSrc argument only the flags are used. No page structured
1110	* will be mapped in this function.
1111	*
1112	* @param pVM VM handle.
1113	* @param pPteDst Destination page table entry.
1114	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1115	* Can safely assume that only the flags are being used.
1116	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1117	* @param pShwPage Pointer to the shadow page.
1118	* @param iPTDst The index into the shadow table.
1119	*
1120	* @remark Not used for 2/4MB pages!
1121	*/
1122	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1123	{
1124	if (PteSrc.n.u1Present)
1125	{
1126	/*
1127	* Find the ram range.
1128	*/
1129	PPGMPAGE pPage;
1130	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1131	if (VBOX_SUCCESS(rc))
1132	{
1133	/** @todo investiage PWT, PCD and PAT. */
1134	/*
1135	* Make page table entry.
1136	*/
1137	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1138	SHWPTE PteDst;
1139	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1140	{
1141	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1142	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1143	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1144	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1145	else
1146	{
1147	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1148	PteDst.u = 0;
1149	}
1150	/** @todo count these two kinds. */
1151	}
1152	else
1153	{
1154	#ifdef PGM_SYNC_DIRTY_BIT
1155	# ifdef PGM_SYNC_ACCESSED_BIT
1156	/*
1157	* If the page or page directory entry is not marked accessed,
1158	* we mark the page not present.
1159	*/
1160	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1161	{
1162	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1163	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1164	PteDst.u = 0;
1165	}
1166	else
1167	# endif
1168	/*
1169	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1170	* when the page is modified.
1171	*/
1172	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1173	{
1174	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1175	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1176	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1177	\| PGM_PTFLAGS_TRACK_DIRTY;
1178	}
1179	else
1180	{
1181	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1182	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1183	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1184	}
1185	#endif
1186	}
1187
1188	#ifdef PGMPOOL_WITH_USER_TRACKING
1189	/*
1190	* Keep user track up to date.
1191	*/
1192	if (PteDst.n.u1Present)
1193	{
1194	if (!pPteDst->n.u1Present)
1195	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1196	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1197	{
1198	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1199	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1200	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1201	}
1202	}
1203	else if (pPteDst->n.u1Present)
1204	{
1205	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1206	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1207	}
1208	#endif /* PGMPOOL_WITH_USER_TRACKING */
1209
1210	/*
1211	* Update statistics and commit the entry.
1212	*/
1213	if (!PteSrc.n.u1Global)
1214	pShwPage->fSeenNonGlobal = true;
1215	*pPteDst = PteDst;
1216	}
1217	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1218	/** @todo count these. */
1219	}
1220	else
1221	{
1222	/*
1223	* Page not-present.
1224	*/
1225	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1226	#ifdef PGMPOOL_WITH_USER_TRACKING
1227	/* Keep user track up to date. */
1228	if (pPteDst->n.u1Present)
1229	{
1230	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1231	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1232	}
1233	#endif /* PGMPOOL_WITH_USER_TRACKING */
1234	pPteDst->u = 0;
1235	/** @todo count these. */
1236	}
1237	}
1238
1239
1240	/**
1241	* Syncs a guest OS page.
1242	*
1243	* There are no conflicts at this point, neither is there any need for
1244	* page table allocations.
1245	*
1246	* @returns VBox status code.
1247	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1248	* @param pVM VM handle.
1249	* @param PdeSrc Page directory entry of the guest.
1250	* @param GCPtrPage Guest context page address.
1251	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1252	* @param uErr Fault error (X86_TRAP_PF_*).
1253	*/
1254	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1255	{
1256	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1257
1258	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1259	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1260
1261	/*
1262	* Assert preconditions.
1263	*/
1264	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1265	Assert(PdeSrc.n.u1Present);
1266	Assert(cPages);
1267
1268	/*
1269	* Get the shadow PDE, find the shadow page table in the pool.
1270	*/
1271	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1272	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1273	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1274	# else /* PAE */
1275	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1276	# endif
1277	Assert(PdeDst.n.u1Present);
1278	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1279
1280	/*
1281	* Check that the page is present and that the shadow PDE isn't out of sync.
1282	*/
1283	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1284	RTGCPHYS GCPhys;
1285	if (!fBigPage)
1286	{
1287	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1288	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1289	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1290	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1291	# endif
1292	}
1293	else
1294	{
1295	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1296	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1297	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1298	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1299	# endif
1300	}
1301	if ( pShwPage->GCPhys == GCPhys
1302	&& PdeSrc.n.u1Present
1303	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1304	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1305	# if PGM_GST_TYPE == PGM_TYPE_PAE
1306	&& (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1307	# endif
1308	)
1309	{
1310	# ifdef PGM_SYNC_ACCESSED_BIT
1311	/*
1312	* Check that the PDE is marked accessed already.
1313	* Since we set the accessed bit before getting here on a #PF, this
1314	* check is only meant for dealing with non-#PF'ing paths.
1315	*/
1316	if (PdeSrc.n.u1Accessed)
1317	# endif
1318	{
1319	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1320	if (!fBigPage)
1321	{
1322	/*
1323	* 4KB Page - Map the guest page table.
1324	*/
1325	PGSTPT pPTSrc;
1326	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1327	if (VBOX_SUCCESS(rc))
1328	{
1329	# ifdef PGM_SYNC_N_PAGES
1330	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1331	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1332	{
1333	/*
1334	* This code path is currently only taken when the caller is PGMTrap0eHandler
1335	* for non-present pages!
1336	*
1337	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1338	* deal with locality.
1339	*/
1340	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1341	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1342	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1343	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1344	# else
1345	const unsigned offPTSrc = 0;
1346	# endif
1347	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1348	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1349	iPTDst = 0;
1350	else
1351	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1352	for (; iPTDst < iPTDstEnd; iPTDst++)
1353	{
1354	if (!pPTDst->a[iPTDst].n.u1Present)
1355	{
1356	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1357	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1358	NOREF(GCPtrCurPage);
1359	#ifndef IN_RING0
1360	/*
1361	* Assuming kernel code will be marked as supervisor - and not as user level
1362	* and executed using a conforming code selector - And marked as readonly.
1363	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1364	*/
1365	PPGMPAGE pPage;
1366	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1367	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1368	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1369	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1370	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1371	)
1372	#endif /* else: CSAM not active */
1373	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1374	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1375	GCPtrCurPage, PteSrc.n.u1Present,
1376	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1377	PteSrc.n.u1User & PdeSrc.n.u1User,
1378	(uint64_t)PteSrc.u,
1379	(uint64_t)pPTDst->a[iPTDst].u,
1380	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1381	}
1382	}
1383	}
1384	else
1385	# endif /* PGM_SYNC_N_PAGES */
1386	{
1387	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1388	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1389	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1390	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1391	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1392	GCPtrPage, PteSrc.n.u1Present,
1393	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1394	PteSrc.n.u1User & PdeSrc.n.u1User,
1395	(uint64_t)PteSrc.u,
1396	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1397	}
1398	}
1399	else /* MMIO or invalid page: emulated in #PF handler. */
1400	{
1401	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1402	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1403	}
1404	}
1405	else
1406	{
1407	/*
1408	* 4/2MB page - lazy syncing shadow 4K pages.
1409	* (There are many causes of getting here, it's no longer only CSAM.)
1410	*/
1411	/* Calculate the GC physical address of this 4KB shadow page. */
1412	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1413	/* Find ram range. */
1414	PPGMPAGE pPage;
1415	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1416	if (VBOX_SUCCESS(rc))
1417	{
1418	/*
1419	* Make shadow PTE entry.
1420	*/
1421	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1422	SHWPTE PteDst;
1423	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1424	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1425	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1426	{
1427	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1428	PteDst.n.u1Write = 0;
1429	else
1430	PteDst.u = 0;
1431	}
1432	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1433	# ifdef PGMPOOL_WITH_USER_TRACKING
1434	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1435	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1436	# endif
1437	pPTDst->a[iPTDst] = PteDst;
1438
1439
1440	# ifdef PGM_SYNC_DIRTY_BIT
1441	/*
1442	* If the page is not flagged as dirty and is writable, then make it read-only
1443	* at PD level, so we can set the dirty bit when the page is modified.
1444	*
1445	* ASSUMES that page access handlers are implemented on page table entry level.
1446	* Thus we will first catch the dirty access and set PDE.D and restart. If
1447	* there is an access handler, we'll trap again and let it work on the problem.
1448	*/
1449	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1450	* As for invlpg, it simply frees the whole shadow PT.
1451	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1452	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1453	{
1454	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1455	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1456	PdeDst.n.u1Write = 0;
1457	}
1458	else
1459	{
1460	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1461	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1462	}
1463	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1464	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1465	# else /* PAE */
1466	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1467	# endif
1468	# endif /* PGM_SYNC_DIRTY_BIT */
1469	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1470	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1471	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1472	}
1473	else
1474	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1475	}
1476	return VINF_SUCCESS;
1477	}
1478	# ifdef PGM_SYNC_ACCESSED_BIT
1479	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1480	#endif
1481	}
1482	else
1483	{
1484	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1485	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1486	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1487	}
1488
1489	/*
1490	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1491	* Yea, I'm lazy.
1492	*/
1493	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1494	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1495	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1496	# else /* PAE */
1497	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1498	# endif
1499	PGM_INVL_GUEST_TLBS();
1500	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1501
1502	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1503
1504	# ifdef PGM_SYNC_N_PAGES
1505	/*
1506	* Get the shadow PDE, find the shadow page table in the pool.
1507	*/
1508	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1509	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1510	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1511	# else /* PAE */
1512	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1513	# endif
1514	Assert(PdeDst.n.u1Present);
1515	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1516	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1517
1518	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1519	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1520	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1521	# else
1522	const unsigned offPTSrc = 0;
1523	# endif
1524
1525	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1526	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1527	{
1528	/*
1529	* This code path is currently only taken when the caller is PGMTrap0eHandler
1530	* for non-present pages!
1531	*
1532	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1533	* deal with locality.
1534	*/
1535	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1536	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1537	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1538	iPTDst = 0;
1539	else
1540	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1541	for (; iPTDst < iPTDstEnd; iPTDst++)
1542	{
1543	if (!pPTDst->a[iPTDst].n.u1Present)
1544	{
1545	GSTPTE PteSrc;
1546
1547	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1548
1549	/* Fake the page table entry */
1550	PteSrc.u = GCPtrCurPage;
1551	PteSrc.n.u1Present = 1;
1552	PteSrc.n.u1Dirty = 1;
1553	PteSrc.n.u1Accessed = 1;
1554	PteSrc.n.u1Write = 1;
1555	PteSrc.n.u1User = 1;
1556
1557	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1558
1559	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1560	GCPtrCurPage, PteSrc.n.u1Present,
1561	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1562	PteSrc.n.u1User & PdeSrc.n.u1User,
1563	(uint64_t)PteSrc.u,
1564	(uint64_t)pPTDst->a[iPTDst].u,
1565	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1566	}
1567	}
1568	}
1569	else
1570	# endif /* PGM_SYNC_N_PAGES */
1571	{
1572	GSTPTE PteSrc;
1573	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1574	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1575
1576	/* Fake the page table entry */
1577	PteSrc.u = GCPtrCurPage;
1578	PteSrc.n.u1Present = 1;
1579	PteSrc.n.u1Dirty = 1;
1580	PteSrc.n.u1Accessed = 1;
1581	PteSrc.n.u1Write = 1;
1582	PteSrc.n.u1User = 1;
1583	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1584
1585	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1586	GCPtrPage, PteSrc.n.u1Present,
1587	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1588	PteSrc.n.u1User & PdeSrc.n.u1User,
1589	(uint64_t)PteSrc.u,
1590	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1591	}
1592	return VINF_SUCCESS;
1593
1594	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1595	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1596	return VERR_INTERNAL_ERROR;
1597	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1598	}
1599
1600
1601
1602	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1603
1604	# ifdef PGM_SYNC_DIRTY_BIT
1605
1606	/**
1607	* Investigate page fault and handle write protection page faults caused by
1608	* dirty bit tracking.
1609	*
1610	* @returns VBox status code.
1611	* @param pVM VM handle.
1612	* @param uErr Page fault error code.
1613	* @param pPdeDst Shadow page directory entry.
1614	* @param pPdeSrc Guest page directory entry.
1615	* @param GCPtrPage Guest context page address.
1616	*/
1617	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1618	{
1619	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1620	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1621	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1622	# if PGM_WITH_NX(PGM_GST_TYPE)
1623	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1624	# endif
1625
1626	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1627	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1628
1629	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1630	AssertFailed();
1631	# elif PGM_GST_TYPE == PGM_TYPE_PAE
1632	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1633
1634	/*
1635	* Real page fault?
1636	*/
1637	if ( (uErr & X86_TRAP_PF_RSVD)
1638	\|\| !pPdpeSrc->n.u1Present
1639	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1640	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->n.u1NoExecute)
1641	\|\| (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1642	\|\| (fUserLevelFault && !pPdpeSrc->n.u1User)
1643	# endif
1644	)
1645	{
1646	# ifdef IN_GC
1647	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1648	# endif
1649	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1650	LogFlow(("CheckPageFault: real page fault at %VGv (0)\n", GCPtrPage));
1651
1652	if ( pPdpeSrc->n.u1Present
1653	&& pPdeSrc->n.u1Present)
1654	{
1655	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1656	* See the 2nd case below as well.
1657	*/
1658	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1659	{
1660	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1661	}
1662	else
1663	{
1664	/*
1665	* Map the guest page table.
1666	*/
1667	PGSTPT pPTSrc;
1668	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1669	if (VBOX_SUCCESS(rc))
1670	{
1671	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1672	const GSTPTE PteSrc = *pPteSrc;
1673	if (pPteSrc->n.u1Present)
1674	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1675	}
1676	AssertRC(rc);
1677	}
1678	}
1679	return VINF_EM_RAW_GUEST_TRAP;
1680	}
1681	# endif
1682
1683	/*
1684	* Real page fault?
1685	*/
1686	if ( (uErr & X86_TRAP_PF_RSVD)
1687	\|\| !pPdeSrc->n.u1Present
1688	# if PGM_WITH_NX(PGM_GST_TYPE)
1689	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1690	# endif
1691	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1692	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1693	{
1694	# ifdef IN_GC
1695	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1696	# endif
1697	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1698	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1699
1700	if (pPdeSrc->n.u1Present)
1701	{
1702	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1703	* See the 2nd case below as well.
1704	*/
1705	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1706	{
1707	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1708	}
1709	else
1710	{
1711	/*
1712	* Map the guest page table.
1713	*/
1714	PGSTPT pPTSrc;
1715	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1716	if (VBOX_SUCCESS(rc))
1717	{
1718	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1719	const GSTPTE PteSrc = *pPteSrc;
1720	if (pPteSrc->n.u1Present)
1721	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1722	}
1723	AssertRC(rc);
1724	}
1725	}
1726	return VINF_EM_RAW_GUEST_TRAP;
1727	}
1728
1729	/*
1730	* First check the easy case where the page directory has been marked read-only to track
1731	* the dirty bit of an emulated BIG page
1732	*/
1733	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1734	{
1735	/* Mark guest page directory as accessed */
1736	pPdeSrc->b.u1Accessed = 1;
1737
1738	/*
1739	* Only write protection page faults are relevant here.
1740	*/
1741	if (fWriteFault)
1742	{
1743	/* Mark guest page directory as dirty (BIG page only). */
1744	pPdeSrc->b.u1Dirty = 1;
1745
1746	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1747	{
1748	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1749
1750	Assert(pPdeSrc->b.u1Write);
1751
1752	pPdeDst->n.u1Write = 1;
1753	pPdeDst->n.u1Accessed = 1;
1754	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1755	PGM_INVL_BIG_PG(GCPtrPage);
1756	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1757	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1758	}
1759	}
1760	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1761	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1762	}
1763	/* else: 4KB page table */
1764
1765	/*
1766	* Map the guest page table.
1767	*/
1768	PGSTPT pPTSrc;
1769	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1770	if (VBOX_SUCCESS(rc))
1771	{
1772	/*
1773	* Real page fault?
1774	*/
1775	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1776	const GSTPTE PteSrc = *pPteSrc;
1777	if ( !PteSrc.n.u1Present
1778	# if PGM_WITH_NX(PGM_GST_TYPE)
1779	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
1780	# endif
1781	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1782	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1783	)
1784	{
1785	# ifdef IN_GC
1786	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1787	# endif
1788	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1789	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1790
1791	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1792	* See the 2nd case above as well.
1793	*/
1794	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1795	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1796
1797	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1798	return VINF_EM_RAW_GUEST_TRAP;
1799	}
1800	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1801
1802	/*
1803	* Set the accessed bits in the page directory and the page table.
1804	*/
1805	pPdeSrc->n.u1Accessed = 1;
1806	pPteSrc->n.u1Accessed = 1;
1807
1808	/*
1809	* Only write protection page faults are relevant here.
1810	*/
1811	if (fWriteFault)
1812	{
1813	/* Write access, so mark guest entry as dirty. */
1814	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1815	if (!pPteSrc->n.u1Dirty)
1816	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1817	else
1818	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1819	# endif
1820	pPteSrc->n.u1Dirty = 1;
1821
1822	if (pPdeDst->n.u1Present)
1823	{
1824	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1825	* Our individual shadow handlers will provide more information and force a fatal exit.
1826	*/
1827	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1828	{
1829	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1830	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1831	return VINF_SUCCESS;
1832	}
1833
1834	/*
1835	* Map shadow page table.
1836	*/
1837	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1838	if (pShwPage)
1839	{
1840	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1841	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1842	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1843	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1844	{
1845	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1846	# ifdef VBOX_STRICT
1847	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1848	if (pPage)
1849	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1850	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1851	# endif
1852	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1853
1854	Assert(pPteSrc->n.u1Write);
1855
1856	pPteDst->n.u1Write = 1;
1857	pPteDst->n.u1Dirty = 1;
1858	pPteDst->n.u1Accessed = 1;
1859	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1860	PGM_INVL_PG(GCPtrPage);
1861
1862	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1863	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1864	}
1865	}
1866	else
1867	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1868	}
1869	}
1870	/** @todo Optimize accessed bit emulation? */
1871	# ifdef VBOX_STRICT
1872	/*
1873	* Sanity check.
1874	*/
1875	else if ( !pPteSrc->n.u1Dirty
1876	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1877	&& pPdeDst->n.u1Present)
1878	{
1879	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1880	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1881	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1882	if ( pPteDst->n.u1Present
1883	&& pPteDst->n.u1Write)
1884	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1885	}
1886	# endif /* VBOX_STRICT */
1887	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1888	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1889	}
1890	AssertRC(rc);
1891	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1892	return rc;
1893	}
1894
1895	# endif
1896
1897	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1898
1899
1900	/**
1901	* Sync a shadow page table.
1902	*
1903	* The shadow page table is not present. This includes the case where
1904	* there is a conflict with a mapping.
1905	*
1906	* @returns VBox status code.
1907	* @param pVM VM handle.
1908	* @param iPD Page directory index.
1909	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1910	* Assume this is a temporary mapping.
1911	* @param GCPtrPage GC Pointer of the page that caused the fault
1912	*/
1913	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1914	{
1915	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1916	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1917	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1918
1919	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1920	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1921
1922	/*
1923	* Validate input a little bit.
1924	*/
1925	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
1926	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1927	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1928	# else
1929	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1930	# endif
1931	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1932	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1933	SHWPDE PdeDst = *pPdeDst;
1934
1935	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1936	/*
1937	* Check for conflicts.
1938	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1939	* HC: Simply resolve the conflict.
1940	*/
1941	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1942	{
1943	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1944	# ifndef IN_RING3
1945	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1946	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1947	return VERR_ADDRESS_CONFLICT;
1948	# else
1949	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1950	Assert(pMapping);
1951	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1952	if (VBOX_FAILURE(rc))
1953	{
1954	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1955	return rc;
1956	}
1957	PdeDst = *pPdeDst;
1958	# endif
1959	}
1960	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1961	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1962	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1963	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1964	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1965
1966	/*
1967	* Sync page directory entry.
1968	*/
1969	int rc = VINF_SUCCESS;
1970	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1971	if (PdeSrc.n.u1Present)
1972	{
1973	/*
1974	* Allocate & map the page table.
1975	*/
1976	PSHWPT pPTDst;
1977	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1978	PPGMPOOLPAGE pShwPage;
1979	RTGCPHYS GCPhys;
1980	if (fPageTable)
1981	{
1982	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1983	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1984	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1985	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1986	# endif
1987	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1988	}
1989	else
1990	{
1991	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1992	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1993	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1994	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1995	# endif
1996	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1997	}
1998	if (rc == VINF_SUCCESS)
1999	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2000	else if (rc == VINF_PGM_CACHED_PAGE)
2001	{
2002	/*
2003	* The PT was cached, just hook it up.
2004	*/
2005	if (fPageTable)
2006	PdeDst.u = pShwPage->Core.Key
2007	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2008	else
2009	{
2010	PdeDst.u = pShwPage->Core.Key
2011	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2012	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
2013	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2014	{
2015	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2016	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2017	PdeDst.b.u1Write = 0;
2018	}
2019	# endif
2020	}
2021	*pPdeDst = PdeDst;
2022	return VINF_SUCCESS;
2023	}
2024	else if (rc == VERR_PGM_POOL_FLUSHED)
2025	return VINF_PGM_SYNC_CR3;
2026	else
2027	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2028	PdeDst.u &= X86_PDE_AVL_MASK;
2029	PdeDst.u \|= pShwPage->Core.Key;
2030
2031	# ifdef PGM_SYNC_DIRTY_BIT
2032	/*
2033	* Page directory has been accessed (this is a fault situation, remember).
2034	*/
2035	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2036	# endif
2037	if (fPageTable)
2038	{
2039	/*
2040	* Page table - 4KB.
2041	*
2042	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2043	*/
2044	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2045	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2046	PGSTPT pPTSrc;
2047	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2048	if (VBOX_SUCCESS(rc))
2049	{
2050	/*
2051	* Start by syncing the page directory entry so CSAM's TLB trick works.
2052	*/
2053	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2054	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2055	*pPdeDst = PdeDst;
2056
2057	/*
2058	* Directory/page user or supervisor privilege: (same goes for read/write)
2059	*
2060	* Directory Page Combined
2061	* U/S U/S U/S
2062	* 0 0 0
2063	* 0 1 0
2064	* 1 0 0
2065	* 1 1 1
2066	*
2067	* Simple AND operation. Table listed for completeness.
2068	*
2069	*/
2070	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2071	# ifdef PGM_SYNC_N_PAGES
2072	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2073	unsigned iPTDst = iPTBase;
2074	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2075	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2076	iPTDst = 0;
2077	else
2078	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2079	# else /* !PGM_SYNC_N_PAGES */
2080	unsigned iPTDst = 0;
2081	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2082	# endif /* !PGM_SYNC_N_PAGES */
2083	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2084	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2085	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2086	# else
2087	const unsigned offPTSrc = 0;
2088	# endif
2089	for (; iPTDst < iPTDstEnd; iPTDst++)
2090	{
2091	const unsigned iPTSrc = iPTDst + offPTSrc;
2092	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2093
2094	if (PteSrc.n.u1Present) /* we've already cleared it above */
2095	{
2096	# ifndef IN_RING0
2097	/*
2098	* Assuming kernel code will be marked as supervisor - and not as user level
2099	* and executed using a conforming code selector - And marked as readonly.
2100	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2101	*/
2102	PPGMPAGE pPage;
2103	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2104	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2105	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2106	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2107	)
2108	# endif
2109	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2110	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2111	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2112	PteSrc.n.u1Present,
2113	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2114	PteSrc.n.u1User & PdeSrc.n.u1User,
2115	(uint64_t)PteSrc.u,
2116	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2117	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2118	}
2119	} /* for PTEs */
2120	}
2121	}
2122	else
2123	{
2124	/*
2125	* Big page - 2/4MB.
2126	*
2127	* We'll walk the ram range list in parallel and optimize lookups.
2128	* We will only sync on shadow page table at a time.
2129	*/
2130	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2131
2132	/**
2133	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2134	*/
2135
2136	/*
2137	* Start by syncing the page directory entry.
2138	*/
2139	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2140	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2141
2142	# ifdef PGM_SYNC_DIRTY_BIT
2143	/*
2144	* If the page is not flagged as dirty and is writable, then make it read-only
2145	* at PD level, so we can set the dirty bit when the page is modified.
2146	*
2147	* ASSUMES that page access handlers are implemented on page table entry level.
2148	* Thus we will first catch the dirty access and set PDE.D and restart. If
2149	* there is an access handler, we'll trap again and let it work on the problem.
2150	*/
2151	/** @todo move the above stuff to a section in the PGM documentation. */
2152	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2153	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2154	{
2155	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2156	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2157	PdeDst.b.u1Write = 0;
2158	}
2159	# endif /* PGM_SYNC_DIRTY_BIT */
2160	*pPdeDst = PdeDst;
2161
2162	/*
2163	* Fill the shadow page table.
2164	*/
2165	/* Get address and flags from the source PDE. */
2166	SHWPTE PteDstBase;
2167	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2168
2169	/* Loop thru the entries in the shadow PT. */
2170	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2171	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2172	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2173	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2174	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2175	unsigned iPTDst = 0;
2176	while (iPTDst < ELEMENTS(pPTDst->a))
2177	{
2178	/* Advance ram range list. */
2179	while (pRam && GCPhys > pRam->GCPhysLast)
2180	pRam = CTXALLSUFF(pRam->pNext);
2181	if (pRam && GCPhys >= pRam->GCPhys)
2182	{
2183	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2184	do
2185	{
2186	/* Make shadow PTE. */
2187	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2188	SHWPTE PteDst;
2189
2190	/* Make sure the RAM has already been allocated. */
2191	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2192	{
2193	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2194	{
2195	# ifdef IN_RING3
2196	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2197	# else
2198	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2199	# endif
2200	if (rc != VINF_SUCCESS)
2201	return rc;
2202	}
2203	}
2204
2205	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2206	{
2207	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2208	{
2209	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2210	PteDst.n.u1Write = 0;
2211	}
2212	else
2213	PteDst.u = 0;
2214	}
2215	# ifndef IN_RING0
2216	/*
2217	* Assuming kernel code will be marked as supervisor and not as user level and executed
2218	* using a conforming code selector. Don't check for readonly, as that implies the whole
2219	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2220	*/
2221	else if ( !PdeSrc.n.u1User
2222	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2223	PteDst.u = 0;
2224	# endif
2225	else
2226	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2227	# ifdef PGMPOOL_WITH_USER_TRACKING
2228	if (PteDst.n.u1Present)
2229	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2230	# endif
2231	/* commit it */
2232	pPTDst->a[iPTDst] = PteDst;
2233	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2234	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2235	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2236
2237	/* advance */
2238	GCPhys += PAGE_SIZE;
2239	iHCPage++;
2240	iPTDst++;
2241	} while ( iPTDst < ELEMENTS(pPTDst->a)
2242	&& GCPhys <= pRam->GCPhysLast);
2243	}
2244	else if (pRam)
2245	{
2246	Log(("Invalid pages at %VGp\n", GCPhys));
2247	do
2248	{
2249	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2250	GCPhys += PAGE_SIZE;
2251	iPTDst++;
2252	} while ( iPTDst < ELEMENTS(pPTDst->a)
2253	&& GCPhys < pRam->GCPhys);
2254	}
2255	else
2256	{
2257	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2258	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2259	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2260	}
2261	} /* while more PTEs */
2262	} /* 4KB / 4MB */
2263	}
2264	else
2265	AssertRelease(!PdeDst.n.u1Present);
2266
2267	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2268	# ifdef IN_GC
2269	if (VBOX_FAILURE(rc))
2270	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2271	# endif
2272	return rc;
2273
2274	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2275
2276	int rc = VINF_SUCCESS;
2277
2278	/*
2279	* Validate input a little bit.
2280	*/
2281	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2282	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2283	# else
2284	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2285	# endif
2286	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2287	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2288	SHWPDE PdeDst = *pPdeDst;
2289
2290	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2291	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2292
2293	GSTPDE PdeSrc;
2294	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2295	PdeSrc.n.u1Present = 1;
2296	PdeSrc.n.u1Write = 1;
2297	PdeSrc.n.u1Accessed = 1;
2298	PdeSrc.n.u1User = 1;
2299
2300	/*
2301	* Allocate & map the page table.
2302	*/
2303	PSHWPT pPTDst;
2304	PPGMPOOLPAGE pShwPage;
2305	RTGCPHYS GCPhys;
2306
2307	/* Virtual address = physical address */
2308	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2309	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2310
2311	if ( rc == VINF_SUCCESS
2312	\|\| rc == VINF_PGM_CACHED_PAGE)
2313	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2314	else
2315	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2316
2317	PdeDst.u &= X86_PDE_AVL_MASK;
2318	PdeDst.u \|= pShwPage->Core.Key;
2319	PdeDst.n.u1Present = 1;
2320	*pPdeDst = PdeDst;
2321
2322	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2323	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2324	return rc;
2325
2326	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2327	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2328	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2329	return VERR_INTERNAL_ERROR;
2330	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2331	}
2332
2333
2334
2335	/**
2336	* Prefetch a page/set of pages.
2337	*
2338	* Typically used to sync commonly used pages before entering raw mode
2339	* after a CR3 reload.
2340	*
2341	* @returns VBox status code.
2342	* @param pVM VM handle.
2343	* @param GCPtrPage Page to invalidate.
2344	*/
2345	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2346	{
2347	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2348	/*
2349	* Check that all Guest levels thru the PDE are present, getting the
2350	* PD and PDE in the processes.
2351	*/
2352	int rc = VINF_SUCCESS;
2353	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2354	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2355	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2356	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2357	# else /* PAE */
2358	unsigned iPDSrc;
2359	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2360	# endif
2361	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2362	# else
2363	PGSTPD pPDSrc = NULL;
2364	const unsigned iPDSrc = 0;
2365	GSTPDE PdeSrc;
2366
2367	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2368	PdeSrc.n.u1Present = 1;
2369	PdeSrc.n.u1Write = 1;
2370	PdeSrc.n.u1Accessed = 1;
2371	PdeSrc.n.u1User = 1;
2372	# endif
2373
2374	# ifdef PGM_SYNC_ACCESSED_BIT
2375	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2376	# else
2377	if (PdeSrc.n.u1Present)
2378	# endif
2379	{
2380	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2381	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2382	# else
2383	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2384	# endif
2385	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2386	{
2387	if (!PdeDst.n.u1Present)
2388	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2389	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2390	else
2391	{
2392	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2393	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2394	* makes no sense to prefetch more than one page.
2395	*/
2396	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2397	if (VBOX_SUCCESS(rc))
2398	rc = VINF_SUCCESS;
2399	}
2400	}
2401	}
2402	return rc;
2403
2404	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2405
2406	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2407	return VERR_INTERNAL_ERROR;
2408	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2409	}
2410
2411
2412
2413
2414	/**
2415	* Syncs a page during a PGMVerifyAccess() call.
2416	*
2417	* @returns VBox status code (informational included).
2418	* @param GCPtrPage The address of the page to sync.
2419	* @param fPage The effective guest page flags.
2420	* @param uErr The trap error code.
2421	*/
2422	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2423	{
2424	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2425
2426	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2427
2428	# ifndef IN_RING0
2429	if (!(fPage & X86_PTE_US))
2430	{
2431	/*
2432	* Mark this page as safe.
2433	*/
2434	/** @todo not correct for pages that contain both code and data!! */
2435	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2436	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2437	}
2438	# endif
2439	/*
2440	* Get guest PD and index.
2441	*/
2442
2443	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2444	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2445	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2446	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2447	# else /* PAE */
2448	unsigned iPDSrc;
2449	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2450	# endif
2451	# else
2452	PGSTPD pPDSrc = NULL;
2453	const unsigned iPDSrc = 0;
2454	# endif
2455	int rc = VINF_SUCCESS;
2456
2457	/*
2458	* First check if the shadow pd is present.
2459	*/
2460	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2461	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2462	# else
2463	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2464	# endif
2465	if (!pPdeDst->n.u1Present)
2466	{
2467	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2468	AssertRC(rc);
2469	if (rc != VINF_SUCCESS)
2470	return rc;
2471	}
2472
2473	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2474	/* Check for dirty bit fault */
2475	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2476	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2477	Log(("PGMVerifyAccess: success (dirty)\n"));
2478	else
2479	{
2480	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2481	#else
2482	{
2483	GSTPDE PdeSrc;
2484	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2485	PdeSrc.n.u1Present = 1;
2486	PdeSrc.n.u1Write = 1;
2487	PdeSrc.n.u1Accessed = 1;
2488	PdeSrc.n.u1User = 1;
2489
2490	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2491	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2492	if (uErr & X86_TRAP_PF_US)
2493	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2494	else /* supervisor */
2495	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2496
2497	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2498	if (VBOX_SUCCESS(rc))
2499	{
2500	/* Page was successfully synced */
2501	Log2(("PGMVerifyAccess: success (sync)\n"));
2502	rc = VINF_SUCCESS;
2503	}
2504	else
2505	{
2506	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2507	return VINF_EM_RAW_GUEST_TRAP;
2508	}
2509	}
2510	return rc;
2511
2512	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2513
2514	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2515	return VERR_INTERNAL_ERROR;
2516	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2517	}
2518
2519
2520	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2521	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2522	/**
2523	* Figures out which kind of shadow page this guest PDE warrants.
2524	*
2525	* @returns Shadow page kind.
2526	* @param pPdeSrc The guest PDE in question.
2527	* @param cr4 The current guest cr4 value.
2528	*/
2529	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2530	{
2531	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2532	return BTH_PGMPOOLKIND_PT_FOR_PT;
2533	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2534	//{
2535	// case 0:
2536	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2537	// case X86_PDE4M_RW:
2538	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2539	// case X86_PDE4M_US:
2540	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2541	// case X86_PDE4M_RW \| X86_PDE4M_US:
2542	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2543	# if 0
2544	// case X86_PDE4M_PAE_NX:
2545	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2546	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2547	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2548	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2549	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2550	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2551	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2552	# endif
2553	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2554	//}
2555	}
2556	# endif
2557	#endif
2558
2559	#undef MY_STAM_COUNTER_INC
2560	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2561
2562
2563	/**
2564	* Syncs the paging hierarchy starting at CR3.
2565	*
2566	* @returns VBox status code, no specials.
2567	* @param pVM The virtual machine.
2568	* @param cr0 Guest context CR0 register
2569	* @param cr3 Guest context CR3 register
2570	* @param cr4 Guest context CR4 register
2571	* @param fGlobal Including global page directories or not
2572	*/
2573	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2574	{
2575	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2576	fGlobal = true; /* Change this CR3 reload to be a global one. */
2577
2578	/*
2579	* Update page access handlers.
2580	* The virtual are always flushed, while the physical are only on demand.
2581	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2582	* have to look into that later because it will have a bad influence on the performance.
2583	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2584	* bird: Yes, but that won't work for aliases.
2585	*/
2586	/** @todo this MUST go away. See #1557. */
2587	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2588	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2589	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2590
2591	#ifdef PGMPOOL_WITH_MONITORING
2592	/*
2593	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2594	* Occationally we will have to clear all the shadow page tables because we wanted
2595	* to monitor a page which was mapped by too many shadowed page tables. This operation
2596	* sometimes refered to as a 'lightweight flush'.
2597	*/
2598	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2599	pgmPoolMonitorModifiedClearAll(pVM);
2600	else
2601	{
2602	# ifdef IN_RING3
2603	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2604	pgmPoolClearAll(pVM);
2605	# else
2606	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2607	return VINF_PGM_SYNC_CR3;
2608	# endif
2609	}
2610	#endif
2611
2612	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2613	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2614
2615	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2616	/*
2617	* Get page directory addresses.
2618	*/
2619	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2620	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2621	# else
2622	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2623	# endif
2624
2625	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2626	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2627	Assert(pPDSrc);
2628	# ifndef IN_GC
2629	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2630	# endif
2631	# endif
2632
2633	/*
2634	* Iterate the page directory.
2635	*/
2636	PPGMMAPPING pMapping;
2637	unsigned iPdNoMapping;
2638	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2639	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2640
2641	/* Only check mappings if they are supposed to be put into the shadow page table. */
2642	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2643	{
2644	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2645	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2646	}
2647	else
2648	{
2649	pMapping = 0;
2650	iPdNoMapping = ~0U;
2651	}
2652	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2653	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2654	{
2655	unsigned iPDSrc;
2656	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2657	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2658	# else
2659	AssertFailed(); /* @todo */
2660	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2661	# endif
2662	PX86PDEPAE pPDEDst = &pPDPAE->a[iPDPTE * X86_PG_PAE_ENTRIES];
2663	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2664
2665	if (pPDSrc == NULL)
2666	{
2667	/* PDPT not present */
2668	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 0;
2669	continue;
2670	}
2671	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2672	{
2673	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2674	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2675	{
2676	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2677	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2678	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2679	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2680	# endif
2681	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2682	if ( PdeSrc.n.u1Present
2683	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2684	{
2685	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2686	/*
2687	* Check for conflicts with GC mappings.
2688	*/
2689	if (iPD == iPdNoMapping)
2690	{
2691	if (pVM->pgm.s.fMappingsFixed)
2692	{
2693	/* It's fixed, just skip the mapping. */
2694	const unsigned cPTs = pMapping->cPTs;
2695	iPD += cPTs - 1;
2696	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2697	pMapping = pMapping->CTXALLSUFF(pNext);
2698	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2699	continue;
2700	}
2701	# ifdef IN_RING3
2702	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2703	if (VBOX_FAILURE(rc))
2704	return rc;
2705
2706	/*
2707	* Update iPdNoMapping and pMapping.
2708	*/
2709	pMapping = pVM->pgm.s.pMappingsR3;
2710	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2711	pMapping = pMapping->pNextR3;
2712	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2713	# else
2714	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2715	return VINF_PGM_SYNC_CR3;
2716	# endif
2717	}
2718	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2719	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2720	Assert(iPD != iPdNoMapping);
2721	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2722	/*
2723	* Sync page directory entry.
2724	*
2725	* The current approach is to allocated the page table but to set
2726	* the entry to not-present and postpone the page table synching till
2727	* it's actually used.
2728	*/
2729	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2730	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2731	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2732	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2733	# else
2734	const unsigned iPdShw = iPD; NOREF(iPdShw);
2735	# endif
2736	{
2737	SHWPDE PdeDst = *pPDEDst;
2738	if (PdeDst.n.u1Present)
2739	{
2740	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2741	RTGCPHYS GCPhys;
2742	if ( !PdeSrc.b.u1Size
2743	\|\| !(cr4 & X86_CR4_PSE))
2744	{
2745	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2746	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2747	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2748	GCPhys \|= i * (PAGE_SIZE / 2);
2749	# endif
2750	}
2751	else
2752	{
2753	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2754	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2755	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2756	GCPhys \|= i * X86_PAGE_2M_SIZE;
2757	# endif
2758	}
2759
2760	if ( pShwPage->GCPhys == GCPhys
2761	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2762	&& ( pShwPage->fCached
2763	\|\| ( !fGlobal
2764	&& ( false
2765	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2766	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2767	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2768	\|\| ( !pShwPage->fSeenNonGlobal
2769	&& (cr4 & X86_CR4_PGE))
2770	# endif
2771	)
2772	)
2773	)
2774	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2775	\|\| ( (cr4 & X86_CR4_PSE)
2776	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2777	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2778	)
2779	)
2780	{
2781	# ifdef VBOX_WITH_STATISTICS
2782	if ( !fGlobal
2783	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2784	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2785	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2786	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2787	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2788	else
2789	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2790	# endif /* VBOX_WITH_STATISTICS */
2791	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2792	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2793	//# ifdef PGMPOOL_WITH_CACHE
2794	// pgmPoolCacheUsed(pPool, pShwPage);
2795	//# endif
2796	}
2797	else
2798	{
2799	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2800	pPDEDst->u = 0;
2801	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2802	}
2803	}
2804	else
2805	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2806	pPDEDst++;
2807	}
2808	}
2809	else if (iPD != iPdNoMapping)
2810	{
2811	/*
2812	* Check if there is any page directory to mark not present here.
2813	*/
2814	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2815	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2816	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2817	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2818	# else
2819	const unsigned iPdShw = iPD; NOREF(iPdShw);
2820	# endif
2821	{
2822	if (pPDEDst->n.u1Present)
2823	{
2824	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2825	pPDEDst->u = 0;
2826	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2827	}
2828	pPDEDst++;
2829	}
2830	}
2831	else
2832	{
2833	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2834	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2835	const unsigned cPTs = pMapping->cPTs;
2836	if (pVM->pgm.s.fMappingsFixed)
2837	{
2838	/* It's fixed, just skip the mapping. */
2839	pMapping = pMapping->CTXALLSUFF(pNext);
2840	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2841	}
2842	else
2843	{
2844	/*
2845	* Check for conflicts for subsequent pagetables
2846	* and advance to the next mapping.
2847	*/
2848	iPdNoMapping = ~0U;
2849	unsigned iPT = cPTs;
2850	while (iPT-- > 1)
2851	{
2852	if ( pPDSrc->a[iPD + iPT].n.u1Present
2853	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2854	{
2855	# ifdef IN_RING3
2856	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2857	if (VBOX_FAILURE(rc))
2858	return rc;
2859
2860	/*
2861	* Update iPdNoMapping and pMapping.
2862	*/
2863	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2864	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2865	pMapping = pMapping->CTXALLSUFF(pNext);
2866	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2867	break;
2868	# else
2869	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2870	return VINF_PGM_SYNC_CR3;
2871	# endif
2872	}
2873	}
2874	if (iPdNoMapping == ~0U && pMapping)
2875	{
2876	pMapping = pMapping->CTXALLSUFF(pNext);
2877	if (pMapping)
2878	iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2879	}
2880	}
2881
2882	/* advance. */
2883	iPD += cPTs - 1;
2884	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2885	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2886	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2887	AssertFailed();
2888	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2889	}
2890
2891	} /* for iPD */
2892	} /* for each PDPTE (PAE) */
2893
2894	return VINF_SUCCESS;
2895
2896	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2897	//# error not implemented
2898	return VERR_INTERNAL_ERROR;
2899	#else /* guest real and protected mode */
2900	return VINF_SUCCESS;
2901	#endif
2902	}
2903
2904
2905
2906
2907	#ifdef VBOX_STRICT
2908	#ifdef IN_GC
2909	# undef AssertMsgFailed
2910	# define AssertMsgFailed Log
2911	#endif
2912	#ifdef IN_RING3
2913	# include <VBox/dbgf.h>
2914
2915	/**
2916	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2917	*
2918	* @returns VBox status code (VINF_SUCCESS).
2919	* @param pVM The VM handle.
2920	* @param cr3 The root of the hierarchy.
2921	* @param crr The cr4, only PAE and PSE is currently used.
2922	* @param fLongMode Set if long mode, false if not long mode.
2923	* @param cMaxDepth Number of levels to dump.
2924	* @param pHlp Pointer to the output functions.
2925	*/
2926	__BEGIN_DECLS
2927	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2928	__END_DECLS
2929
2930	#endif
2931
2932	/**
2933	* Checks that the shadow page table is in sync with the guest one.
2934	*
2935	* @returns The number of errors.
2936	* @param pVM The virtual machine.
2937	* @param cr3 Guest context CR3 register
2938	* @param cr4 Guest context CR4 register
2939	* @param GCPtr Where to start. Defaults to 0.
2940	* @param cb How much to check. Defaults to everything.
2941	*/
2942	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2943	{
2944	unsigned cErrors = 0;
2945
2946	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2947	PPGM pPGM = &pVM->pgm.s;
2948	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2949	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2950	RTHCPHYS HCPhys; /* general usage. */
2951	int rc;
2952
2953	/*
2954	* Check that the Guest CR3 and all it's mappings are correct.
2955	*/
2956	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2957	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2958	false);
2959	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2960	AssertRCReturn(rc, 1);
2961	HCPhys = NIL_RTHCPHYS;
2962	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2963	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2964	# ifdef IN_RING3
2965	RTGCPHYS GCPhys;
2966	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2967	AssertRCReturn(rc, 1);
2968	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2969	# endif
2970	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2971
2972	/*
2973	* Get and check the Shadow CR3.
2974	*/
2975	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2976	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2977	unsigned cPDEs = ELEMENTS(pPDDst->a);
2978	# else
2979	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2980	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2981	# endif
2982	if (cb != ~(RTGCUINTPTR)0)
2983	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2984
2985	/** @todo call the other two PGMAssert() functions. /
2986
2987	/*
2988	* Iterate the shadow page directory.
2989	*/
2990	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2991	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2992	cPDEs += iPDDst;
2993	for (;
2994	iPDDst < cPDEs;
2995	iPDDst++, GCPtr += _4G / cPDEs)
2996	{
2997	const SHWPDE PdeDst = pPDDst->a[iPDDst];
2998	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2999	{
3000	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3001	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3002	{
3003	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3004	cErrors++;
3005	continue;
3006	}
3007	}
3008	else if ( (PdeDst.u & X86_PDE_P)
3009	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3010	)
3011	{
3012	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3013	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3014	if (!pPoolPage)
3015	{
3016	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3017	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3018	cErrors++;
3019	continue;
3020	}
3021	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3022
3023	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3024	{
3025	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3026	GCPtr, (uint64_t)PdeDst.u));
3027	cErrors++;
3028	}
3029
3030	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3031	{
3032	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3033	GCPtr, (uint64_t)PdeDst.u));
3034	cErrors++;
3035	}
3036
3037	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
3038	if (!PdeSrc.n.u1Present)
3039	{
3040	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3041	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3042	cErrors++;
3043	continue;
3044	}
3045
3046	if ( !PdeSrc.b.u1Size
3047	\|\| !(cr4 & X86_CR4_PSE))
3048	{
3049	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3050	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3051	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3052	# endif
3053	}
3054	else
3055	{
3056	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3057	{
3058	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3059	GCPtr, (uint64_t)PdeSrc.u));
3060	cErrors++;
3061	continue;
3062	}
3063	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3064	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3065	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3066	# endif
3067	}
3068
3069	if ( pPoolPage->enmKind
3070	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3071	{
3072	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3073	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3074	cErrors++;
3075	}
3076
3077	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3078	if (!pPhysPage)
3079	{
3080	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3081	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3082	cErrors++;
3083	continue;
3084	}
3085
3086	if (GCPhysGst != pPoolPage->GCPhys)
3087	{
3088	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3089	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3090	cErrors++;
3091	continue;
3092	}
3093
3094	if ( !PdeSrc.b.u1Size
3095	\|\| !(cr4 & X86_CR4_PSE))
3096	{
3097	/*
3098	* Page Table.
3099	*/
3100	const GSTPT *pPTSrc;
3101	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3102	if (VBOX_FAILURE(rc))
3103	{
3104	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3105	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3106	cErrors++;
3107	continue;
3108	}
3109	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3110	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3111	{
3112	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3113	// (This problem will go away when/if we shadow multiple CR3s.)
3114	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3115	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3116	cErrors++;
3117	continue;
3118	}
3119	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3120	{
3121	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3122	GCPtr, (uint64_t)PdeDst.u));
3123	cErrors++;
3124	continue;
3125	}
3126
3127	/* iterate the page table. */
3128	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3129	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3130	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3131	# else
3132	const unsigned offPTSrc = 0;
3133	# endif
3134	for (unsigned iPT = 0, off = 0;
3135	iPT < ELEMENTS(pPTDst->a);
3136	iPT++, off += PAGE_SIZE)
3137	{
3138	const SHWPTE PteDst = pPTDst->a[iPT];
3139
3140	/* skip not-present entries. */
3141	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3142	continue;
3143	Assert(PteDst.n.u1Present);
3144
3145	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3146	if (!PteSrc.n.u1Present)
3147	{
3148	#ifdef IN_RING3
3149	PGMAssertHandlerAndFlagsInSync(pVM);
3150	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3151	#endif
3152	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3153	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3154	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3155	cErrors++;
3156	continue;
3157	}
3158
3159	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3160	# if 1 /** @todo sync accessed bit properly... */
3161	fIgnoreFlags \|= X86_PTE_A;
3162	# endif
3163
3164	/* match the physical addresses */
3165	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3166	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3167
3168	# ifdef IN_RING3
3169	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3170	if (VBOX_FAILURE(rc))
3171	{
3172	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3173	{
3174	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3175	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3176	cErrors++;
3177	continue;
3178	}
3179	}
3180	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3181	{
3182	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3183	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3184	cErrors++;
3185	continue;
3186	}
3187	# endif
3188
3189	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3190	if (!pPhysPage)
3191	{
3192	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3193	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3194	{
3195	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3196	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3197	cErrors++;
3198	continue;
3199	}
3200	# endif
3201	if (PteDst.n.u1Write)
3202	{
3203	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3204	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3205	cErrors++;
3206	}
3207	fIgnoreFlags \|= X86_PTE_RW;
3208	}
3209	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3210	{
3211	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3212	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3213	cErrors++;
3214	continue;
3215	}
3216
3217	/* flags */
3218	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3219	{
3220	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3221	{
3222	if (PteDst.n.u1Write)
3223	{
3224	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3225	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3226	cErrors++;
3227	continue;
3228	}
3229	fIgnoreFlags \|= X86_PTE_RW;
3230	}
3231	else
3232	{
3233	if (PteDst.n.u1Present)
3234	{
3235	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3236	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3237	cErrors++;
3238	continue;
3239	}
3240	fIgnoreFlags \|= X86_PTE_P;
3241	}
3242	}
3243	else
3244	{
3245	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3246	{
3247	if (PteDst.n.u1Write)
3248	{
3249	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3250	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3251	cErrors++;
3252	continue;
3253	}
3254	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3255	{
3256	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3257	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3258	cErrors++;
3259	continue;
3260	}
3261	if (PteDst.n.u1Dirty)
3262	{
3263	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3264	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3265	cErrors++;
3266	}
3267	# if 0 /** @todo sync access bit properly... */
3268	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3269	{
3270	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3271	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3272	cErrors++;
3273	}
3274	fIgnoreFlags \|= X86_PTE_RW;
3275	# else
3276	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3277	# endif
3278	}
3279	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3280	{
3281	/* access bit emulation (not implemented). */
3282	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3283	{
3284	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3285	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3286	cErrors++;
3287	continue;
3288	}
3289	if (!PteDst.n.u1Accessed)
3290	{
3291	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3292	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3293	cErrors++;
3294	}
3295	fIgnoreFlags \|= X86_PTE_P;
3296	}
3297	# ifdef DEBUG_sandervl
3298	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3299	# endif
3300	}
3301
3302	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3303	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3304	)
3305	{
3306	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3307	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3308	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3309	cErrors++;
3310	continue;
3311	}
3312	} /* foreach PTE */
3313	}
3314	else
3315	{
3316	/*
3317	* Big Page.
3318	*/
3319	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3320	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3321	{
3322	if (PdeDst.n.u1Write)
3323	{
3324	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3325	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3326	cErrors++;
3327	continue;
3328	}
3329	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3330	{
3331	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3332	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3333	cErrors++;
3334	continue;
3335	}
3336	# if 0 /** @todo sync access bit properly... */
3337	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3338	{
3339	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3340	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3341	cErrors++;
3342	}
3343	fIgnoreFlags \|= X86_PTE_RW;
3344	# else
3345	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3346	# endif
3347	}
3348	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3349	{
3350	/* access bit emulation (not implemented). */
3351	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3352	{
3353	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3354	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3355	cErrors++;
3356	continue;
3357	}
3358	if (!PdeDst.n.u1Accessed)
3359	{
3360	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3361	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3362	cErrors++;
3363	}
3364	fIgnoreFlags \|= X86_PTE_P;
3365	}
3366
3367	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3368	{
3369	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3370	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3371	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3372	cErrors++;
3373	}
3374
3375	/* iterate the page table. */
3376	for (unsigned iPT = 0, off = 0;
3377	iPT < ELEMENTS(pPTDst->a);
3378	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3379	{
3380	const SHWPTE PteDst = pPTDst->a[iPT];
3381
3382	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3383	{
3384	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3385	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3386	cErrors++;
3387	}
3388
3389	/* skip not-present entries. */
3390	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3391	continue;
3392
3393	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3394
3395	/* match the physical addresses */
3396	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3397
3398	# ifdef IN_RING3
3399	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3400	if (VBOX_FAILURE(rc))
3401	{
3402	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3403	{
3404	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3405	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3406	cErrors++;
3407	}
3408	}
3409	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3410	{
3411	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3412	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3413	cErrors++;
3414	continue;
3415	}
3416	# endif
3417
3418	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3419	if (!pPhysPage)
3420	{
3421	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3422	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3423	{
3424	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3425	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3426	cErrors++;
3427	continue;
3428	}
3429	# endif
3430	if (PteDst.n.u1Write)
3431	{
3432	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3433	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3434	cErrors++;
3435	}
3436	fIgnoreFlags \|= X86_PTE_RW;
3437	}
3438	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3439	{
3440	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3441	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3442	cErrors++;
3443	continue;
3444	}
3445
3446	/* flags */
3447	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3448	{
3449	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3450	{
3451	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3452	{
3453	if (PteDst.n.u1Write)
3454	{
3455	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3456	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3457	cErrors++;
3458	continue;
3459	}
3460	fIgnoreFlags \|= X86_PTE_RW;
3461	}
3462	}
3463	else
3464	{
3465	if (PteDst.n.u1Present)
3466	{
3467	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3468	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3469	cErrors++;
3470	continue;
3471	}
3472	fIgnoreFlags \|= X86_PTE_P;
3473	}
3474	}
3475
3476	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3477	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3478	)
3479	{
3480	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3481	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3482	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3483	cErrors++;
3484	continue;
3485	}
3486	} /* foreach PTE */
3487	}
3488	}
3489	/* not present */
3490
3491	} /* forearch PDE */
3492
3493	# ifdef DEBUG
3494	if (cErrors)
3495	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3496	# endif
3497
3498	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3499	//# error not implemented
3500
3501
3502	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3503	//# error not implemented
3504
3505	/#else: guest real and protected mode /
3506	#endif
3507	return cErrors;
3508	}
3509	#endif /* VBOX_STRICT */
3510

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7804

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