PGMAllBth.h@ 7819

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1	/* $Id: PGMAllBth.h 7819 2008-04-09 08:00:14Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
42	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
43	#error "Invalid combination; PAE guest implies PAE shadow"
44	#endif
45
46	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
47	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
48	#error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
53	#error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
57	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
58	#error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
59	#endif
60
61	/**
62	* #PF Handler for raw-mode guest execution.
63	*
64	* @returns VBox status code (appropriate for trap handling and GC return).
65	* @param pVM VM Handle.
66	* @param uErr The trap error code.
67	* @param pRegFrame Trap register frame.
68	* @param pvFault The fault address.
69	*/
70	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
71	{
72	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
73
74	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
75	/*
76	* Hide the instruction fetch trap indicator for now.
77	*/
78	/** @todo NXE will change this and we must fix NXE in the switcher too! */
79	if (uErr & X86_TRAP_PF_ID)
80	{
81	uErr &= ~X86_TRAP_PF_ID;
82	TRPMSetErrorCode(pVM, uErr);
83	}
84	# endif
85
86	/*
87	* Get PDs.
88	*/
89	int rc;
90	# if PGM_WITH_PAGING(PGM_GST_TYPE)
91	# if PGM_GST_TYPE == PGM_TYPE_32BIT
92	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
93	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
94	# else /* PAE */
95	unsigned iPDSrc;
96	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
97	# endif
98	# else
99	PGSTPD pPDSrc = NULL;
100	const unsigned iPDSrc = 0;
101	# endif
102
103	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
104	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
105	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
106	# else /* PAE */
107	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
108	# endif
109
110	# if PGM_WITH_PAGING(PGM_GST_TYPE)
111	# ifdef PGM_SYNC_DIRTY_BIT
112	/*
113	* If we successfully correct the write protection fault due to dirty bit
114	* tracking, or this page fault is a genuine one, then return immediately.
115	*/
116	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
117	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
118	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
119	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
120	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
121	{
122	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
123	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
124	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
125	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
126	}
127	# endif
128
129	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
130	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
131
132	/*
133	* A common case is the not-present error caused by lazy page table syncing.
134	*
135	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
136	* so we can safely assume that the shadow PT is present when calling SyncPage later.
137	*
138	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
139	* of mapping conflict and defer to SyncCR3 in R3.
140	* (Again, we do NOT support access handlers for non-present guest pages.)
141	*
142	*/
143	# if PGM_WITH_PAGING(PGM_GST_TYPE)
144	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
145	# else
146	GSTPDE PdeSrc;
147	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
148	PdeSrc.n.u1Present = 1;
149	PdeSrc.n.u1Write = 1;
150	PdeSrc.n.u1Accessed = 1;
151	PdeSrc.n.u1User = 1;
152	# endif
153	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
154	&& !pPDDst->a[iPDDst].n.u1Present
155	&& PdeSrc.n.u1Present
156	)
157
158	{
159	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
160	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
161	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
162	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
163	if (VBOX_SUCCESS(rc))
164	{
165	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
166	return rc;
167	}
168	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
169	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
170	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
171	return VINF_PGM_SYNC_CR3;
172	}
173
174	# if PGM_WITH_PAGING(PGM_GST_TYPE)
175	/*
176	* Check if this address is within any of our mappings.
177	*
178	* This is very fast and it's gonna save us a bit of effort below and prevent
179	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
180	* (BTW, it's impossible to have physical access handlers in a mapping.)
181	*/
182	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
183	{
184	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
185	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
186	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
187	{
188	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
189	break;
190	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
191	{
192	/*
193	* The first thing we check is if we've got an undetected conflict.
194	*/
195	if (!pVM->pgm.s.fMappingsFixed)
196	{
197	unsigned iPT = pMapping->cPTs;
198	while (iPT-- > 0)
199	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
200	{
201	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
202	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
203	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
204	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
205	return VINF_PGM_SYNC_CR3;
206	}
207	}
208
209	/*
210	* Check if the fault address is in a virtual page access handler range.
211	*/
212	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
213	if ( pCur
214	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
215	&& uErr & X86_TRAP_PF_RW)
216	{
217	# ifdef IN_GC
218	STAM_PROFILE_START(&pCur->Stat, h);
219	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
220	STAM_PROFILE_STOP(&pCur->Stat, h);
221	# else
222	AssertFailed();
223	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
224	# endif
225	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
226	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
227	return rc;
228	}
229
230	/*
231	* Pretend we're not here and let the guest handle the trap.
232	*/
233	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
234	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
235	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
236	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
237	return VINF_EM_RAW_GUEST_TRAP;
238	}
239	}
240	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
241	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
242	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
243
244	/*
245	* Check if this fault address is flagged for special treatment,
246	* which means we'll have to figure out the physical address and
247	* check flags associated with it.
248	*
249	* ASSUME that we can limit any special access handling to pages
250	* in page tables which the guest believes to be present.
251	*/
252	if (PdeSrc.n.u1Present)
253	{
254	RTGCPHYS GCPhys = NIL_RTGCPHYS;
255
256	# if PGM_WITH_PAGING(PGM_GST_TYPE)
257	uint32_t cr4 = CPUMGetGuestCR4(pVM);
258	if ( PdeSrc.b.u1Size
259	&& (cr4 & X86_CR4_PSE))
260	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
261	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
262	else
263	{
264	PGSTPT pPTSrc;
265	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
266	if (VBOX_SUCCESS(rc))
267	{
268	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
269	if (pPTSrc->a[iPTESrc].n.u1Present)
270	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
271	}
272	}
273	# else
274	/* No paging so the fault address is the physical address */
275	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
276	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
277
278	/*
279	* If we have a GC address we'll check if it has any flags set.
280	*/
281	if (GCPhys != NIL_RTGCPHYS)
282	{
283	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
284
285	PPGMPAGE pPage;
286	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
287	if (VBOX_SUCCESS(rc))
288	{
289	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
290	{
291	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
292	{
293	/*
294	* Physical page access handler.
295	*/
296	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
297	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
298	if (pCur)
299	{
300	# ifdef PGM_SYNC_N_PAGES
301	/*
302	* If the region is write protected and we got a page not present fault, then sync
303	* the pages. If the fault was caused by a read, then restart the instruction.
304	* In case of write access continue to the GC write handler.
305	*
306	* ASSUMES that there is only one handler per page or that they have similar write properties.
307	*/
308	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
309	&& !(uErr & X86_TRAP_PF_P))
310	{
311	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
312	if ( VBOX_FAILURE(rc)
313	\|\| !(uErr & X86_TRAP_PF_RW)
314	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
315	{
316	AssertRC(rc);
317	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
318	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
319	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
320	return rc;
321	}
322	}
323	# endif
324
325	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
326	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
327	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
328
329	#if defined(IN_GC) \|\| defined(IN_RING0)
330	if (CTXALLSUFF(pCur->pfnHandler))
331	{
332	STAM_PROFILE_START(&pCur->Stat, h);
333	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
334	STAM_PROFILE_STOP(&pCur->Stat, h);
335	}
336	else
337	#endif
338	rc = VINF_EM_RAW_EMULATE_INSTR;
339	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
340	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
341	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
342	return rc;
343	}
344	}
345	# if PGM_WITH_PAGING(PGM_GST_TYPE)
346	else
347	{
348	# ifdef PGM_SYNC_N_PAGES
349	/*
350	* If the region is write protected and we got a page not present fault, then sync
351	* the pages. If the fault was caused by a read, then restart the instruction.
352	* In case of write access continue to the GC write handler.
353	*/
354	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
355	&& !(uErr & X86_TRAP_PF_P))
356	{
357	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
358	if ( VBOX_FAILURE(rc)
359	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
360	\|\| !(uErr & X86_TRAP_PF_RW))
361	{
362	AssertRC(rc);
363	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
364	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
365	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
366	return rc;
367	}
368	}
369	# endif
370	/*
371	* Ok, it's an virtual page access handler.
372	*
373	* Since it's faster to search by address, we'll do that first
374	* and then retry by GCPhys if that fails.
375	*/
376	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
377	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
378	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
379	*/
380	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
381	if (pCur)
382	{
383	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
384	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
385	\|\| !(uErr & X86_TRAP_PF_P)
386	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
387	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
388
389	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
390	&& ( uErr & X86_TRAP_PF_RW
391	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
392	{
393	# ifdef IN_GC
394	STAM_PROFILE_START(&pCur->Stat, h);
395	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
396	STAM_PROFILE_STOP(&pCur->Stat, h);
397	# else
398	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
399	# endif
400	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
401	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
402	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
403	return rc;
404	}
405	/* Unhandled part of a monitored page */
406	}
407	else
408	{
409	/* Check by physical address. */
410	PPGMVIRTHANDLER pCur;
411	unsigned iPage;
412	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
413	&pCur, &iPage);
414	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
415	if ( pCur
416	&& ( uErr & X86_TRAP_PF_RW
417	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
418	{
419	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
420	# ifdef IN_GC
421	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
422	Assert(off < pCur->cb);
423	STAM_PROFILE_START(&pCur->Stat, h);
424	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
425	STAM_PROFILE_STOP(&pCur->Stat, h);
426	# else
427	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
428	# endif
429	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
430	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
431	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
432	return rc;
433	}
434	}
435	}
436	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
437
438	/*
439	* There is a handled area of the page, but this fault doesn't belong to it.
440	* We must emulate the instruction.
441	*
442	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
443	* we first check if this was a page-not-present fault for a page with only
444	* write access handlers. Restart the instruction if it wasn't a write access.
445	*/
446	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
447
448	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
449	&& !(uErr & X86_TRAP_PF_P))
450	{
451	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
452	if ( VBOX_FAILURE(rc)
453	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
454	\|\| !(uErr & X86_TRAP_PF_RW))
455	{
456	AssertRC(rc);
457	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
458	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
459	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
460	return rc;
461	}
462	}
463
464	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
465	* It's writing to an unhandled part of the LDT page several million times.
466	*/
467	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
468	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
469	rc, pPage->HCPhys,
470	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
471	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
472	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
473	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
474	return rc;
475	} /* if any kind of handler */
476
477	# if PGM_WITH_PAGING(PGM_GST_TYPE)
478	if (uErr & X86_TRAP_PF_P)
479	{
480	/*
481	* The page isn't marked, but it might still be monitored by a virtual page access handler.
482	* (ASSUMES no temporary disabling of virtual handlers.)
483	*/
484	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
485	* we should correct both the shadow page table and physical memory flags, and not only check for
486	* accesses within the handler region but for access to pages with virtual handlers. */
487	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
488	if (pCur)
489	{
490	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
491	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
492	\|\| !(uErr & X86_TRAP_PF_P)
493	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
494	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
495
496	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
497	&& ( uErr & X86_TRAP_PF_RW
498	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
499	{
500	# ifdef IN_GC
501	STAM_PROFILE_START(&pCur->Stat, h);
502	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
503	STAM_PROFILE_STOP(&pCur->Stat, h);
504	# else
505	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
506	# endif
507	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
508	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
509	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
510	return rc;
511	}
512	}
513	}
514	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
515	}
516	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
517
518	# ifdef PGM_OUT_OF_SYNC_IN_GC
519	/*
520	* We are here only if page is present in Guest page tables and trap is not handled
521	* by our handlers.
522	* Check it for page out-of-sync situation.
523	*/
524	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
525
526	if (!(uErr & X86_TRAP_PF_P))
527	{
528	/*
529	* Page is not present in our page tables.
530	* Try to sync it!
531	* BTW, fPageShw is invalid in this branch!
532	*/
533	if (uErr & X86_TRAP_PF_US)
534	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
535	else /* supervisor */
536	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
537
538	# if defined(LOG_ENABLED) && !defined(IN_RING0)
539	RTGCPHYS GCPhys;
540	uint64_t fPageGst;
541	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
542	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
543	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
544	# endif /* LOG_ENABLED */
545
546	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
547	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
548	{
549	uint64_t fPageGst;
550	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
551	if ( VBOX_SUCCESS(rc)
552	&& !(fPageGst & X86_PTE_US))
553	{
554	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
555	if ( pvFault == (RTGCPTR)pRegFrame->eip
556	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
557	# ifdef CSAM_DETECT_NEW_CODE_PAGES
558	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
559	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
560	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
561	)
562	{
563	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
564	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
565	if (rc != VINF_SUCCESS)
566	{
567	/*
568	* CSAM needs to perform a job in ring 3.
569	*
570	* Sync the page before going to the host context; otherwise we'll end up in a loop if
571	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
572	*/
573	LogFlow(("CSAM ring 3 job\n"));
574	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
575	AssertRC(rc2);
576
577	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
578	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
579	return rc;
580	}
581	}
582	# ifdef CSAM_DETECT_NEW_CODE_PAGES
583	else
584	if ( uErr == X86_TRAP_PF_RW
585	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
586	&& pRegFrame->ecx < 0x10000
587	)
588	{
589	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
590	* to detect loading of new code pages.
591	*/
592
593	/*
594	* Decode the instruction.
595	*/
596	RTGCPTR PC;
597	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
598	if (rc == VINF_SUCCESS)
599	{
600	DISCPUSTATE Cpu;
601	uint32_t cbOp;
602	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
603
604	/* For now we'll restrict this to rep movsw/d instructions */
605	if ( rc == VINF_SUCCESS
606	&& Cpu.pCurInstr->opcode == OP_MOVSWD
607	&& (Cpu.prefix & PREFIX_REP))
608	{
609	CSAMMarkPossibleCodePage(pVM, pvFault);
610	}
611	}
612	}
613	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
614
615	/*
616	* Mark this page as safe.
617	*/
618	/** @todo not correct for pages that contain both code and data!! */
619	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
620	CSAMMarkPage(pVM, pvFault, true);
621	}
622	}
623	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
624	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
625	if (VBOX_SUCCESS(rc))
626	{
627	/* The page was successfully synced, return to the guest. */
628	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
629	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
630	return VINF_SUCCESS;
631	}
632	}
633	else
634	{
635	/*
636	* A side effect of not flushing global PDEs are out of sync pages due
637	* to physical monitored regions, that are no longer valid.
638	* Assume for now it only applies to the read/write flag
639	*/
640	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
641	{
642	if (uErr & X86_TRAP_PF_US)
643	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
644	else /* supervisor */
645	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
646
647
648	/*
649	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
650	*/
651	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
652	if (VBOX_SUCCESS(rc))
653	{
654	/*
655	* Page was successfully synced, return to guest.
656	*/
657	# ifdef VBOX_STRICT
658	RTGCPHYS GCPhys;
659	uint64_t fPageGst;
660	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
661	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
662	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
663
664	uint64_t fPageShw;
665	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
666	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
667	# endif /* VBOX_STRICT */
668	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
669	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
670	return VINF_SUCCESS;
671	}
672
673	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
674	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
675	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
676	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
677	{
678	uint64_t fPageGst;
679	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
680	if ( VBOX_SUCCESS(rc)
681	&& !(fPageGst & X86_PTE_RW))
682	{
683	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
684	if (VBOX_SUCCESS(rc))
685	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
686	else
687	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
688	return rc;
689	}
690	else
691	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
692	}
693
694	}
695
696	# if PGM_WITH_PAGING(PGM_GST_TYPE)
697	# ifdef VBOX_STRICT
698	/*
699	* Check for VMM page flags vs. Guest page flags consistency.
700	* Currently only for debug purposes.
701	*/
702	if (VBOX_SUCCESS(rc))
703	{
704	/* Get guest page flags. */
705	uint64_t fPageGst;
706	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
707	if (VBOX_SUCCESS(rc))
708	{
709	uint64_t fPageShw;
710	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
711
712	/*
713	* Compare page flags.
714	* Note: we have AVL, A, D bits desynched.
715	*/
716	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
717	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
718	}
719	else
720	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
721	}
722	else
723	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
724	# endif /* VBOX_STRICT */
725	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
726	}
727	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
728	# endif /* PGM_OUT_OF_SYNC_IN_GC */
729	}
730	else
731	{
732	/*
733	* Page not present in Guest OS or invalid page table address.
734	* This is potential virtual page access handler food.
735	*
736	* For the present we'll say that our access handlers don't
737	* work for this case - we've already discarded the page table
738	* not present case which is identical to this.
739	*
740	* When we perchance find we need this, we will probably have AVL
741	* trees (offset based) to operate on and we can measure their speed
742	* agains mapping a page table and probably rearrange this handling
743	* a bit. (Like, searching virtual ranges before checking the
744	* physical address.)
745	*/
746	}
747	}
748
749
750	# if PGM_WITH_PAGING(PGM_GST_TYPE)
751	/*
752	* Conclusion, this is a guest trap.
753	*/
754	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
755	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
756	return VINF_EM_RAW_GUEST_TRAP;
757	# else
758	/* present, but not a monitored page; perhaps the guest is probing physical memory */
759	return VINF_EM_RAW_EMULATE_INSTR;
760	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
761
762
763	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
764
765	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
766	return VERR_INTERNAL_ERROR;
767	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
768	}
769
770
771	/**
772	* Emulation of the invlpg instruction.
773	*
774	*
775	* @returns VBox status code.
776	*
777	* @param pVM VM handle.
778	* @param GCPtrPage Page to invalidate.
779	*
780	* @remark ASSUMES that the guest is updating before invalidating. This order
781	* isn't required by the CPU, so this is speculative and could cause
782	* trouble.
783	*
784	* @todo Flush page or page directory only if necessary!
785	* @todo Add a #define for simply invalidating the page.
786	*/
787	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
788	{
789	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
790	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
791
792	LogFlow(("InvalidatePage %x\n", GCPtrPage));
793	/*
794	* Get the shadow PD entry and skip out if this PD isn't present.
795	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
796	*/
797	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
798	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
799	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
800	# else
801	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
802	# endif
803	const SHWPDE PdeDst = *pPdeDst;
804	if (!PdeDst.n.u1Present)
805	{
806	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
807	return VINF_SUCCESS;
808	}
809
810	/*
811	* Get the guest PD entry and calc big page.
812	*/
813	# if PGM_GST_TYPE == PGM_TYPE_32BIT
814	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
815	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
816	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
817	# else /* PAE */
818	unsigned iPDSrc;
819	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
820	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
821	# endif
822
823	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
824	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
825
826	# ifdef IN_RING3
827	/*
828	* If a CR3 Sync is pending we may ignore the invalidate page operation
829	* depending on the kind of sync and if it's a global page or not.
830	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
831	*/
832	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
833	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
834	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
835	&& fIsBigPage
836	&& PdeSrc.b.u1Global
837	&& (cr4 & X86_CR4_PGE)
838	)
839	)
840	# else
841	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
842	# endif
843	{
844	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
845	return VINF_SUCCESS;
846	}
847	# endif /* IN_RING3 */
848
849
850	/*
851	* Deal with the Guest PDE.
852	*/
853	int rc = VINF_SUCCESS;
854	if (PdeSrc.n.u1Present)
855	{
856	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
857	{
858	/*
859	* Conflict - Let SyncPT deal with it to avoid duplicate code.
860	*/
861	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
862	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
863	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
864	}
865	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
866	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
867	{
868	/*
869	* Mark not present so we can resync the PDE when it's used.
870	*/
871	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
872	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
873	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
874	pPdeDst->u = 0;
875	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
876	PGM_INVL_GUEST_TLBS();
877	}
878	# ifdef PGM_SYNC_ACCESSED_BIT
879	else if (!PdeSrc.n.u1Accessed)
880	{
881	/*
882	* Mark not present so we can set the accessed bit.
883	*/
884	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
885	pPdeDst->u = 0;
886	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
887	PGM_INVL_GUEST_TLBS();
888	}
889	# endif
890	else if (!fIsBigPage)
891	{
892	/*
893	* 4KB - page.
894	*/
895	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
896	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
897	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
898	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
899	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
900	# endif
901	if (pShwPage->GCPhys == GCPhys)
902	{
903	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
904	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
905	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
906	if (pPT->a[iPTEDst].n.u1Present)
907	{
908	# ifdef PGMPOOL_WITH_USER_TRACKING
909	/* This is very unlikely with caching/monitoring enabled. */
910	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
911	# endif
912	pPT->a[iPTEDst].u = 0;
913	}
914	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
915	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
916	if (VBOX_SUCCESS(rc))
917	rc = VINF_SUCCESS;
918	# endif
919	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
920	PGM_INVL_PG(GCPtrPage);
921	}
922	else
923	{
924	/*
925	* The page table address changed.
926	*/
927	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
928	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
929	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
930	pPdeDst->u = 0;
931	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
932	PGM_INVL_GUEST_TLBS();
933	}
934	}
935	else
936	{
937	/*
938	* 4MB - page.
939	*/
940	/* Before freeing the page, check if anything really changed. */
941	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
942	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
943	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
944	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
945	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
946	# endif
947	if ( pShwPage->GCPhys == GCPhys
948	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
949	{
950	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
951	/** @todo PAT */
952	# ifdef PGM_SYNC_DIRTY_BIT
953	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
954	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
955	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
956	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
957	# else
958	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
959	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
960	# endif
961	{
962	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
963	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
964	return VINF_SUCCESS;
965	}
966	}
967
968	/*
969	* Ok, the page table is present and it's been changed in the guest.
970	* If we're in host context, we'll just mark it as not present taking the lazy approach.
971	* We could do this for some flushes in GC too, but we need an algorithm for
972	* deciding which 4MB pages containing code likely to be executed very soon.
973	*/
974	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
975	pPdeDst->u = 0;
976	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
977	PGM_INVL_BIG_PG(GCPtrPage);
978	}
979	}
980	else
981	{
982	/*
983	* Page directory is not present, mark shadow PDE not present.
984	*/
985	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
986	{
987	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
988	pPdeDst->u = 0;
989	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
990	PGM_INVL_PG(GCPtrPage);
991	}
992	else
993	{
994	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
995	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
996	}
997	}
998
999	return rc;
1000
1001	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1002	//# error not implemented
1003	return VERR_INTERNAL_ERROR;
1004
1005	#else /* guest real and protected mode */
1006	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1007	return VINF_SUCCESS;
1008	#endif
1009	}
1010
1011
1012	#ifdef PGMPOOL_WITH_USER_TRACKING
1013	/**
1014	* Update the tracking of shadowed pages.
1015	*
1016	* @param pVM The VM handle.
1017	* @param pShwPage The shadow page.
1018	* @param HCPhys The physical page we is being dereferenced.
1019	*/
1020	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1021	{
1022	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1023	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1024	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1025
1026	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1027	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1028	* 2. write protect all shadowed pages. I.e. implement caching.
1029	*/
1030	/*
1031	* Find the guest address.
1032	*/
1033	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1034	pRam;
1035	pRam = CTXALLSUFF(pRam->pNext))
1036	{
1037	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1038	while (iPage-- > 0)
1039	{
1040	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1041	{
1042	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1043	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1044	pShwPage->cPresent--;
1045	pPool->cPresent--;
1046	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1047	return;
1048	}
1049	}
1050	}
1051
1052	for (;;)
1053	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1054	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1055	pShwPage->cPresent--;
1056	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1057	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1058	}
1059
1060
1061	/**
1062	* Update the tracking of shadowed pages.
1063	*
1064	* @param pVM The VM handle.
1065	* @param pShwPage The shadow page.
1066	* @param u16 The top 16-bit of the pPage->HCPhys.
1067	* @param pPage Pointer to the guest page. this will be modified.
1068	* @param iPTDst The index into the shadow table.
1069	*/
1070	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1071	{
1072	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1073	/*
1074	* We're making certain assumptions about the placement of cRef and idx.
1075	*/
1076	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1077	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1078
1079	/*
1080	* Just deal with the simple first time here.
1081	*/
1082	if (!u16)
1083	{
1084	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1085	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1086	}
1087	else
1088	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1089
1090	/* write back, trying to be clever... */
1091	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1092	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1093	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1094	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1095
1096	/* update statistics. */
1097	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1098	pShwPage->cPresent++;
1099	if (pShwPage->iFirstPresent > iPTDst)
1100	pShwPage->iFirstPresent = iPTDst;
1101	}
1102	#endif /* PGMPOOL_WITH_USER_TRACKING */
1103
1104
1105	/**
1106	* Creates a 4K shadow page for a guest page.
1107	*
1108	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1109	* physical address. The PdeSrc argument only the flags are used. No page structured
1110	* will be mapped in this function.
1111	*
1112	* @param pVM VM handle.
1113	* @param pPteDst Destination page table entry.
1114	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1115	* Can safely assume that only the flags are being used.
1116	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1117	* @param pShwPage Pointer to the shadow page.
1118	* @param iPTDst The index into the shadow table.
1119	*
1120	* @remark Not used for 2/4MB pages!
1121	*/
1122	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1123	{
1124	if (PteSrc.n.u1Present)
1125	{
1126	/*
1127	* Find the ram range.
1128	*/
1129	PPGMPAGE pPage;
1130	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1131	if (VBOX_SUCCESS(rc))
1132	{
1133	/** @todo investiage PWT, PCD and PAT. */
1134	/*
1135	* Make page table entry.
1136	*/
1137	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1138	SHWPTE PteDst;
1139	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1140	{
1141	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1142	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1143	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1144	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1145	else
1146	{
1147	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1148	PteDst.u = 0;
1149	}
1150	/** @todo count these two kinds. */
1151	}
1152	else
1153	{
1154	#ifdef PGM_SYNC_DIRTY_BIT
1155	# ifdef PGM_SYNC_ACCESSED_BIT
1156	/*
1157	* If the page or page directory entry is not marked accessed,
1158	* we mark the page not present.
1159	*/
1160	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1161	{
1162	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1163	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1164	PteDst.u = 0;
1165	}
1166	else
1167	# endif
1168	/*
1169	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1170	* when the page is modified.
1171	*/
1172	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1173	{
1174	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1175	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1176	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1177	\| PGM_PTFLAGS_TRACK_DIRTY;
1178	}
1179	else
1180	{
1181	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1182	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1183	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1184	}
1185	#endif
1186	}
1187
1188	#ifdef PGMPOOL_WITH_USER_TRACKING
1189	/*
1190	* Keep user track up to date.
1191	*/
1192	if (PteDst.n.u1Present)
1193	{
1194	if (!pPteDst->n.u1Present)
1195	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1196	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1197	{
1198	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1199	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1200	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1201	}
1202	}
1203	else if (pPteDst->n.u1Present)
1204	{
1205	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1206	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1207	}
1208	#endif /* PGMPOOL_WITH_USER_TRACKING */
1209
1210	/*
1211	* Update statistics and commit the entry.
1212	*/
1213	if (!PteSrc.n.u1Global)
1214	pShwPage->fSeenNonGlobal = true;
1215	*pPteDst = PteDst;
1216	}
1217	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1218	/** @todo count these. */
1219	}
1220	else
1221	{
1222	/*
1223	* Page not-present.
1224	*/
1225	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1226	#ifdef PGMPOOL_WITH_USER_TRACKING
1227	/* Keep user track up to date. */
1228	if (pPteDst->n.u1Present)
1229	{
1230	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1231	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1232	}
1233	#endif /* PGMPOOL_WITH_USER_TRACKING */
1234	pPteDst->u = 0;
1235	/** @todo count these. */
1236	}
1237	}
1238
1239
1240	/**
1241	* Syncs a guest OS page.
1242	*
1243	* There are no conflicts at this point, neither is there any need for
1244	* page table allocations.
1245	*
1246	* @returns VBox status code.
1247	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1248	* @param pVM VM handle.
1249	* @param PdeSrc Page directory entry of the guest.
1250	* @param GCPtrPage Guest context page address.
1251	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1252	* @param uErr Fault error (X86_TRAP_PF_*).
1253	*/
1254	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1255	{
1256	# if PGM_WITH_NX(PGM_GST_TYPE)
1257	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1258	# endif
1259	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1260
1261	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1262	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1263
1264	/*
1265	* Assert preconditions.
1266	*/
1267	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1268	Assert(PdeSrc.n.u1Present);
1269	Assert(cPages);
1270
1271	/*
1272	* Get the shadow PDE, find the shadow page table in the pool.
1273	*/
1274	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1275	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1276	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1277	# else /* PAE */
1278	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1279	# endif
1280	Assert(PdeDst.n.u1Present);
1281	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1282
1283	/*
1284	* Check that the page is present and that the shadow PDE isn't out of sync.
1285	*/
1286	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1287	RTGCPHYS GCPhys;
1288	if (!fBigPage)
1289	{
1290	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1291	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1292	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1293	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1294	# endif
1295	}
1296	else
1297	{
1298	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1299	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1300	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1301	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1302	# endif
1303	}
1304	if ( pShwPage->GCPhys == GCPhys
1305	&& PdeSrc.n.u1Present
1306	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1307	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1308	# if PGM_WITH_NX(PGM_GST_TYPE)
1309	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1310	# endif
1311	)
1312	{
1313	# ifdef PGM_SYNC_ACCESSED_BIT
1314	/*
1315	* Check that the PDE is marked accessed already.
1316	* Since we set the accessed bit before getting here on a #PF, this
1317	* check is only meant for dealing with non-#PF'ing paths.
1318	*/
1319	if (PdeSrc.n.u1Accessed)
1320	# endif
1321	{
1322	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1323	if (!fBigPage)
1324	{
1325	/*
1326	* 4KB Page - Map the guest page table.
1327	*/
1328	PGSTPT pPTSrc;
1329	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1330	if (VBOX_SUCCESS(rc))
1331	{
1332	# ifdef PGM_SYNC_N_PAGES
1333	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1334	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1335	{
1336	/*
1337	* This code path is currently only taken when the caller is PGMTrap0eHandler
1338	* for non-present pages!
1339	*
1340	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1341	* deal with locality.
1342	*/
1343	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1344	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1345	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1346	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1347	# else
1348	const unsigned offPTSrc = 0;
1349	# endif
1350	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1351	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1352	iPTDst = 0;
1353	else
1354	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1355	for (; iPTDst < iPTDstEnd; iPTDst++)
1356	{
1357	if (!pPTDst->a[iPTDst].n.u1Present)
1358	{
1359	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1360	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1361	NOREF(GCPtrCurPage);
1362	#ifndef IN_RING0
1363	/*
1364	* Assuming kernel code will be marked as supervisor - and not as user level
1365	* and executed using a conforming code selector - And marked as readonly.
1366	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1367	*/
1368	PPGMPAGE pPage;
1369	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1370	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1371	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1372	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1373	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1374	)
1375	#endif /* else: CSAM not active */
1376	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1377	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1378	GCPtrCurPage, PteSrc.n.u1Present,
1379	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1380	PteSrc.n.u1User & PdeSrc.n.u1User,
1381	(uint64_t)PteSrc.u,
1382	(uint64_t)pPTDst->a[iPTDst].u,
1383	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1384	}
1385	}
1386	}
1387	else
1388	# endif /* PGM_SYNC_N_PAGES */
1389	{
1390	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1391	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1392	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1393	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1394	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1395	GCPtrPage, PteSrc.n.u1Present,
1396	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1397	PteSrc.n.u1User & PdeSrc.n.u1User,
1398	(uint64_t)PteSrc.u,
1399	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1400	}
1401	}
1402	else /* MMIO or invalid page: emulated in #PF handler. */
1403	{
1404	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1405	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1406	}
1407	}
1408	else
1409	{
1410	/*
1411	* 4/2MB page - lazy syncing shadow 4K pages.
1412	* (There are many causes of getting here, it's no longer only CSAM.)
1413	*/
1414	/* Calculate the GC physical address of this 4KB shadow page. */
1415	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1416	/* Find ram range. */
1417	PPGMPAGE pPage;
1418	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1419	if (VBOX_SUCCESS(rc))
1420	{
1421	/*
1422	* Make shadow PTE entry.
1423	*/
1424	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1425	SHWPTE PteDst;
1426	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1427	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1428	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1429	{
1430	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1431	PteDst.n.u1Write = 0;
1432	else
1433	PteDst.u = 0;
1434	}
1435	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1436	# ifdef PGMPOOL_WITH_USER_TRACKING
1437	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1438	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1439	# endif
1440	pPTDst->a[iPTDst] = PteDst;
1441
1442
1443	# ifdef PGM_SYNC_DIRTY_BIT
1444	/*
1445	* If the page is not flagged as dirty and is writable, then make it read-only
1446	* at PD level, so we can set the dirty bit when the page is modified.
1447	*
1448	* ASSUMES that page access handlers are implemented on page table entry level.
1449	* Thus we will first catch the dirty access and set PDE.D and restart. If
1450	* there is an access handler, we'll trap again and let it work on the problem.
1451	*/
1452	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1453	* As for invlpg, it simply frees the whole shadow PT.
1454	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1455	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1456	{
1457	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1458	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1459	PdeDst.n.u1Write = 0;
1460	}
1461	else
1462	{
1463	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1464	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1465	}
1466	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1467	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1468	# else /* PAE */
1469	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1470	# endif
1471	# endif /* PGM_SYNC_DIRTY_BIT */
1472	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1473	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1474	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1475	}
1476	else
1477	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1478	}
1479	return VINF_SUCCESS;
1480	}
1481	# ifdef PGM_SYNC_ACCESSED_BIT
1482	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1483	#endif
1484	}
1485	else
1486	{
1487	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1488	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1489	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1490	}
1491
1492	/*
1493	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1494	* Yea, I'm lazy.
1495	*/
1496	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1497	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1498	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1499	# else /* PAE */
1500	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1501	# endif
1502	PGM_INVL_GUEST_TLBS();
1503	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1504
1505	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1506
1507	# ifdef PGM_SYNC_N_PAGES
1508	/*
1509	* Get the shadow PDE, find the shadow page table in the pool.
1510	*/
1511	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1512	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1513	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1514	# else /* PAE */
1515	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1516	# endif
1517	Assert(PdeDst.n.u1Present);
1518	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1519	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1520
1521	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1522	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1523	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1524	# else
1525	const unsigned offPTSrc = 0;
1526	# endif
1527
1528	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1529	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1530	{
1531	/*
1532	* This code path is currently only taken when the caller is PGMTrap0eHandler
1533	* for non-present pages!
1534	*
1535	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1536	* deal with locality.
1537	*/
1538	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1539	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1540	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1541	iPTDst = 0;
1542	else
1543	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1544	for (; iPTDst < iPTDstEnd; iPTDst++)
1545	{
1546	if (!pPTDst->a[iPTDst].n.u1Present)
1547	{
1548	GSTPTE PteSrc;
1549
1550	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1551
1552	/* Fake the page table entry */
1553	PteSrc.u = GCPtrCurPage;
1554	PteSrc.n.u1Present = 1;
1555	PteSrc.n.u1Dirty = 1;
1556	PteSrc.n.u1Accessed = 1;
1557	PteSrc.n.u1Write = 1;
1558	PteSrc.n.u1User = 1;
1559
1560	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1561
1562	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1563	GCPtrCurPage, PteSrc.n.u1Present,
1564	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1565	PteSrc.n.u1User & PdeSrc.n.u1User,
1566	(uint64_t)PteSrc.u,
1567	(uint64_t)pPTDst->a[iPTDst].u,
1568	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1569	}
1570	}
1571	}
1572	else
1573	# endif /* PGM_SYNC_N_PAGES */
1574	{
1575	GSTPTE PteSrc;
1576	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1577	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1578
1579	/* Fake the page table entry */
1580	PteSrc.u = GCPtrCurPage;
1581	PteSrc.n.u1Present = 1;
1582	PteSrc.n.u1Dirty = 1;
1583	PteSrc.n.u1Accessed = 1;
1584	PteSrc.n.u1Write = 1;
1585	PteSrc.n.u1User = 1;
1586	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1587
1588	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1589	GCPtrPage, PteSrc.n.u1Present,
1590	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1591	PteSrc.n.u1User & PdeSrc.n.u1User,
1592	(uint64_t)PteSrc.u,
1593	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1594	}
1595	return VINF_SUCCESS;
1596
1597	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1598	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1599	return VERR_INTERNAL_ERROR;
1600	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1601	}
1602
1603
1604
1605	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1606
1607	# ifdef PGM_SYNC_DIRTY_BIT
1608
1609	/**
1610	* Investigate page fault and handle write protection page faults caused by
1611	* dirty bit tracking.
1612	*
1613	* @returns VBox status code.
1614	* @param pVM VM handle.
1615	* @param uErr Page fault error code.
1616	* @param pPdeDst Shadow page directory entry.
1617	* @param pPdeSrc Guest page directory entry.
1618	* @param GCPtrPage Guest context page address.
1619	*/
1620	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1621	{
1622	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1623	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1624	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1625	# if PGM_WITH_NX(PGM_GST_TYPE)
1626	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1627	# endif
1628
1629	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1630	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1631
1632	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1633	AssertFailed();
1634	# elif PGM_GST_TYPE == PGM_TYPE_PAE
1635	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1636
1637	/*
1638	* Real page fault?
1639	*/
1640	if ( (uErr & X86_TRAP_PF_RSVD)
1641	\|\| !pPdpeSrc->n.u1Present
1642	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1643	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->n.u1NoExecute)
1644	\|\| (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1645	\|\| (fUserLevelFault && !pPdpeSrc->n.u1User)
1646	# endif
1647	)
1648	{
1649	# ifdef IN_GC
1650	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1651	# endif
1652	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1653	LogFlow(("CheckPageFault: real page fault at %VGv (0)\n", GCPtrPage));
1654
1655	if ( pPdpeSrc->n.u1Present
1656	&& pPdeSrc->n.u1Present)
1657	{
1658	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1659	* See the 2nd case below as well.
1660	*/
1661	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1662	{
1663	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1664	}
1665	else
1666	{
1667	/*
1668	* Map the guest page table.
1669	*/
1670	PGSTPT pPTSrc;
1671	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1672	if (VBOX_SUCCESS(rc))
1673	{
1674	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1675	const GSTPTE PteSrc = *pPteSrc;
1676	if (pPteSrc->n.u1Present)
1677	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1678	}
1679	AssertRC(rc);
1680	}
1681	}
1682	return VINF_EM_RAW_GUEST_TRAP;
1683	}
1684	# endif
1685
1686	/*
1687	* Real page fault?
1688	*/
1689	if ( (uErr & X86_TRAP_PF_RSVD)
1690	\|\| !pPdeSrc->n.u1Present
1691	# if PGM_WITH_NX(PGM_GST_TYPE)
1692	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1693	# endif
1694	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1695	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1696	{
1697	# ifdef IN_GC
1698	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1699	# endif
1700	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1701	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1702
1703	if (pPdeSrc->n.u1Present)
1704	{
1705	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1706	* See the 2nd case below as well.
1707	*/
1708	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1709	{
1710	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1711	}
1712	else
1713	{
1714	/*
1715	* Map the guest page table.
1716	*/
1717	PGSTPT pPTSrc;
1718	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1719	if (VBOX_SUCCESS(rc))
1720	{
1721	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1722	const GSTPTE PteSrc = *pPteSrc;
1723	if (pPteSrc->n.u1Present)
1724	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1725	}
1726	AssertRC(rc);
1727	}
1728	}
1729	return VINF_EM_RAW_GUEST_TRAP;
1730	}
1731
1732	/*
1733	* First check the easy case where the page directory has been marked read-only to track
1734	* the dirty bit of an emulated BIG page
1735	*/
1736	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1737	{
1738	/* Mark guest page directory as accessed */
1739	pPdeSrc->b.u1Accessed = 1;
1740
1741	/*
1742	* Only write protection page faults are relevant here.
1743	*/
1744	if (fWriteFault)
1745	{
1746	/* Mark guest page directory as dirty (BIG page only). */
1747	pPdeSrc->b.u1Dirty = 1;
1748
1749	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1750	{
1751	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1752
1753	Assert(pPdeSrc->b.u1Write);
1754
1755	pPdeDst->n.u1Write = 1;
1756	pPdeDst->n.u1Accessed = 1;
1757	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1758	PGM_INVL_BIG_PG(GCPtrPage);
1759	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1760	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1761	}
1762	}
1763	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1764	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1765	}
1766	/* else: 4KB page table */
1767
1768	/*
1769	* Map the guest page table.
1770	*/
1771	PGSTPT pPTSrc;
1772	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1773	if (VBOX_SUCCESS(rc))
1774	{
1775	/*
1776	* Real page fault?
1777	*/
1778	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1779	const GSTPTE PteSrc = *pPteSrc;
1780	if ( !PteSrc.n.u1Present
1781	# if PGM_WITH_NX(PGM_GST_TYPE)
1782	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
1783	# endif
1784	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1785	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1786	)
1787	{
1788	# ifdef IN_GC
1789	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1790	# endif
1791	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1792	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1793
1794	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1795	* See the 2nd case above as well.
1796	*/
1797	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1798	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1799
1800	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1801	return VINF_EM_RAW_GUEST_TRAP;
1802	}
1803	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1804
1805	/*
1806	* Set the accessed bits in the page directory and the page table.
1807	*/
1808	pPdeSrc->n.u1Accessed = 1;
1809	pPteSrc->n.u1Accessed = 1;
1810
1811	/*
1812	* Only write protection page faults are relevant here.
1813	*/
1814	if (fWriteFault)
1815	{
1816	/* Write access, so mark guest entry as dirty. */
1817	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1818	if (!pPteSrc->n.u1Dirty)
1819	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1820	else
1821	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1822	# endif
1823	pPteSrc->n.u1Dirty = 1;
1824
1825	if (pPdeDst->n.u1Present)
1826	{
1827	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1828	* Our individual shadow handlers will provide more information and force a fatal exit.
1829	*/
1830	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1831	{
1832	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1833	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1834	return VINF_SUCCESS;
1835	}
1836
1837	/*
1838	* Map shadow page table.
1839	*/
1840	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1841	if (pShwPage)
1842	{
1843	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1844	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1845	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1846	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1847	{
1848	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1849	# ifdef VBOX_STRICT
1850	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1851	if (pPage)
1852	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1853	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1854	# endif
1855	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1856
1857	Assert(pPteSrc->n.u1Write);
1858
1859	pPteDst->n.u1Write = 1;
1860	pPteDst->n.u1Dirty = 1;
1861	pPteDst->n.u1Accessed = 1;
1862	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1863	PGM_INVL_PG(GCPtrPage);
1864
1865	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1866	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1867	}
1868	}
1869	else
1870	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1871	}
1872	}
1873	/** @todo Optimize accessed bit emulation? */
1874	# ifdef VBOX_STRICT
1875	/*
1876	* Sanity check.
1877	*/
1878	else if ( !pPteSrc->n.u1Dirty
1879	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1880	&& pPdeDst->n.u1Present)
1881	{
1882	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1883	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1884	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1885	if ( pPteDst->n.u1Present
1886	&& pPteDst->n.u1Write)
1887	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1888	}
1889	# endif /* VBOX_STRICT */
1890	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1891	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1892	}
1893	AssertRC(rc);
1894	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1895	return rc;
1896	}
1897
1898	# endif
1899
1900	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1901
1902
1903	/**
1904	* Sync a shadow page table.
1905	*
1906	* The shadow page table is not present. This includes the case where
1907	* there is a conflict with a mapping.
1908	*
1909	* @returns VBox status code.
1910	* @param pVM VM handle.
1911	* @param iPD Page directory index.
1912	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1913	* Assume this is a temporary mapping.
1914	* @param GCPtrPage GC Pointer of the page that caused the fault
1915	*/
1916	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1917	{
1918	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1919	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1920	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1921
1922	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1923	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1924
1925	/*
1926	* Validate input a little bit.
1927	*/
1928	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
1929	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1930	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1931	# else
1932	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1933	# endif
1934	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1935	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1936	SHWPDE PdeDst = *pPdeDst;
1937
1938	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1939	/*
1940	* Check for conflicts.
1941	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1942	* HC: Simply resolve the conflict.
1943	*/
1944	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1945	{
1946	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1947	# ifndef IN_RING3
1948	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1949	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1950	return VERR_ADDRESS_CONFLICT;
1951	# else
1952	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1953	Assert(pMapping);
1954	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1955	if (VBOX_FAILURE(rc))
1956	{
1957	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1958	return rc;
1959	}
1960	PdeDst = *pPdeDst;
1961	# endif
1962	}
1963	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1964	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1965	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1966	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1967	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1968
1969	/*
1970	* Sync page directory entry.
1971	*/
1972	int rc = VINF_SUCCESS;
1973	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1974	if (PdeSrc.n.u1Present)
1975	{
1976	/*
1977	* Allocate & map the page table.
1978	*/
1979	PSHWPT pPTDst;
1980	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1981	PPGMPOOLPAGE pShwPage;
1982	RTGCPHYS GCPhys;
1983	if (fPageTable)
1984	{
1985	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1986	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1987	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1988	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
1989	# endif
1990	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
1991	}
1992	else
1993	{
1994	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1995	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1996	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1997	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1998	# endif
1999	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2000	}
2001	if (rc == VINF_SUCCESS)
2002	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2003	else if (rc == VINF_PGM_CACHED_PAGE)
2004	{
2005	/*
2006	* The PT was cached, just hook it up.
2007	*/
2008	if (fPageTable)
2009	PdeDst.u = pShwPage->Core.Key
2010	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2011	else
2012	{
2013	PdeDst.u = pShwPage->Core.Key
2014	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2015	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
2016	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2017	{
2018	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2019	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2020	PdeDst.b.u1Write = 0;
2021	}
2022	# endif
2023	}
2024	*pPdeDst = PdeDst;
2025	return VINF_SUCCESS;
2026	}
2027	else if (rc == VERR_PGM_POOL_FLUSHED)
2028	return VINF_PGM_SYNC_CR3;
2029	else
2030	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2031	PdeDst.u &= X86_PDE_AVL_MASK;
2032	PdeDst.u \|= pShwPage->Core.Key;
2033
2034	# ifdef PGM_SYNC_DIRTY_BIT
2035	/*
2036	* Page directory has been accessed (this is a fault situation, remember).
2037	*/
2038	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2039	# endif
2040	if (fPageTable)
2041	{
2042	/*
2043	* Page table - 4KB.
2044	*
2045	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2046	*/
2047	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2048	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2049	PGSTPT pPTSrc;
2050	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2051	if (VBOX_SUCCESS(rc))
2052	{
2053	/*
2054	* Start by syncing the page directory entry so CSAM's TLB trick works.
2055	*/
2056	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2057	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2058	*pPdeDst = PdeDst;
2059
2060	/*
2061	* Directory/page user or supervisor privilege: (same goes for read/write)
2062	*
2063	* Directory Page Combined
2064	* U/S U/S U/S
2065	* 0 0 0
2066	* 0 1 0
2067	* 1 0 0
2068	* 1 1 1
2069	*
2070	* Simple AND operation. Table listed for completeness.
2071	*
2072	*/
2073	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2074	# ifdef PGM_SYNC_N_PAGES
2075	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2076	unsigned iPTDst = iPTBase;
2077	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2078	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2079	iPTDst = 0;
2080	else
2081	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2082	# else /* !PGM_SYNC_N_PAGES */
2083	unsigned iPTDst = 0;
2084	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2085	# endif /* !PGM_SYNC_N_PAGES */
2086	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2087	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2088	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2089	# else
2090	const unsigned offPTSrc = 0;
2091	# endif
2092	for (; iPTDst < iPTDstEnd; iPTDst++)
2093	{
2094	const unsigned iPTSrc = iPTDst + offPTSrc;
2095	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2096
2097	if (PteSrc.n.u1Present) /* we've already cleared it above */
2098	{
2099	# ifndef IN_RING0
2100	/*
2101	* Assuming kernel code will be marked as supervisor - and not as user level
2102	* and executed using a conforming code selector - And marked as readonly.
2103	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2104	*/
2105	PPGMPAGE pPage;
2106	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2107	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2108	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2109	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2110	)
2111	# endif
2112	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2113	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2114	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2115	PteSrc.n.u1Present,
2116	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2117	PteSrc.n.u1User & PdeSrc.n.u1User,
2118	(uint64_t)PteSrc.u,
2119	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2120	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2121	}
2122	} /* for PTEs */
2123	}
2124	}
2125	else
2126	{
2127	/*
2128	* Big page - 2/4MB.
2129	*
2130	* We'll walk the ram range list in parallel and optimize lookups.
2131	* We will only sync on shadow page table at a time.
2132	*/
2133	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2134
2135	/**
2136	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2137	*/
2138
2139	/*
2140	* Start by syncing the page directory entry.
2141	*/
2142	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2143	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2144
2145	# ifdef PGM_SYNC_DIRTY_BIT
2146	/*
2147	* If the page is not flagged as dirty and is writable, then make it read-only
2148	* at PD level, so we can set the dirty bit when the page is modified.
2149	*
2150	* ASSUMES that page access handlers are implemented on page table entry level.
2151	* Thus we will first catch the dirty access and set PDE.D and restart. If
2152	* there is an access handler, we'll trap again and let it work on the problem.
2153	*/
2154	/** @todo move the above stuff to a section in the PGM documentation. */
2155	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2156	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2157	{
2158	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2159	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2160	PdeDst.b.u1Write = 0;
2161	}
2162	# endif /* PGM_SYNC_DIRTY_BIT */
2163	*pPdeDst = PdeDst;
2164
2165	/*
2166	* Fill the shadow page table.
2167	*/
2168	/* Get address and flags from the source PDE. */
2169	SHWPTE PteDstBase;
2170	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2171
2172	/* Loop thru the entries in the shadow PT. */
2173	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2174	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2175	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2176	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2177	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2178	unsigned iPTDst = 0;
2179	while (iPTDst < ELEMENTS(pPTDst->a))
2180	{
2181	/* Advance ram range list. */
2182	while (pRam && GCPhys > pRam->GCPhysLast)
2183	pRam = CTXALLSUFF(pRam->pNext);
2184	if (pRam && GCPhys >= pRam->GCPhys)
2185	{
2186	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2187	do
2188	{
2189	/* Make shadow PTE. */
2190	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2191	SHWPTE PteDst;
2192
2193	/* Make sure the RAM has already been allocated. */
2194	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2195	{
2196	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2197	{
2198	# ifdef IN_RING3
2199	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2200	# else
2201	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2202	# endif
2203	if (rc != VINF_SUCCESS)
2204	return rc;
2205	}
2206	}
2207
2208	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2209	{
2210	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2211	{
2212	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2213	PteDst.n.u1Write = 0;
2214	}
2215	else
2216	PteDst.u = 0;
2217	}
2218	# ifndef IN_RING0
2219	/*
2220	* Assuming kernel code will be marked as supervisor and not as user level and executed
2221	* using a conforming code selector. Don't check for readonly, as that implies the whole
2222	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2223	*/
2224	else if ( !PdeSrc.n.u1User
2225	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2226	PteDst.u = 0;
2227	# endif
2228	else
2229	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2230	# ifdef PGMPOOL_WITH_USER_TRACKING
2231	if (PteDst.n.u1Present)
2232	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2233	# endif
2234	/* commit it */
2235	pPTDst->a[iPTDst] = PteDst;
2236	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2237	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2238	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2239
2240	/* advance */
2241	GCPhys += PAGE_SIZE;
2242	iHCPage++;
2243	iPTDst++;
2244	} while ( iPTDst < ELEMENTS(pPTDst->a)
2245	&& GCPhys <= pRam->GCPhysLast);
2246	}
2247	else if (pRam)
2248	{
2249	Log(("Invalid pages at %VGp\n", GCPhys));
2250	do
2251	{
2252	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2253	GCPhys += PAGE_SIZE;
2254	iPTDst++;
2255	} while ( iPTDst < ELEMENTS(pPTDst->a)
2256	&& GCPhys < pRam->GCPhys);
2257	}
2258	else
2259	{
2260	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2261	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2262	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2263	}
2264	} /* while more PTEs */
2265	} /* 4KB / 4MB */
2266	}
2267	else
2268	AssertRelease(!PdeDst.n.u1Present);
2269
2270	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2271	# ifdef IN_GC
2272	if (VBOX_FAILURE(rc))
2273	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2274	# endif
2275	return rc;
2276
2277	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2278
2279	int rc = VINF_SUCCESS;
2280
2281	/*
2282	* Validate input a little bit.
2283	*/
2284	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2285	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2286	# else
2287	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2288	# endif
2289	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2290	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2291	SHWPDE PdeDst = *pPdeDst;
2292
2293	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2294	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2295
2296	GSTPDE PdeSrc;
2297	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2298	PdeSrc.n.u1Present = 1;
2299	PdeSrc.n.u1Write = 1;
2300	PdeSrc.n.u1Accessed = 1;
2301	PdeSrc.n.u1User = 1;
2302
2303	/*
2304	* Allocate & map the page table.
2305	*/
2306	PSHWPT pPTDst;
2307	PPGMPOOLPAGE pShwPage;
2308	RTGCPHYS GCPhys;
2309
2310	/* Virtual address = physical address */
2311	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2312	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2313
2314	if ( rc == VINF_SUCCESS
2315	\|\| rc == VINF_PGM_CACHED_PAGE)
2316	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2317	else
2318	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2319
2320	PdeDst.u &= X86_PDE_AVL_MASK;
2321	PdeDst.u \|= pShwPage->Core.Key;
2322	PdeDst.n.u1Present = 1;
2323	*pPdeDst = PdeDst;
2324
2325	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2326	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2327	return rc;
2328
2329	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2330	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2331	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2332	return VERR_INTERNAL_ERROR;
2333	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2334	}
2335
2336
2337
2338	/**
2339	* Prefetch a page/set of pages.
2340	*
2341	* Typically used to sync commonly used pages before entering raw mode
2342	* after a CR3 reload.
2343	*
2344	* @returns VBox status code.
2345	* @param pVM VM handle.
2346	* @param GCPtrPage Page to invalidate.
2347	*/
2348	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2349	{
2350	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2351	/*
2352	* Check that all Guest levels thru the PDE are present, getting the
2353	* PD and PDE in the processes.
2354	*/
2355	int rc = VINF_SUCCESS;
2356	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2357	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2358	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2359	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2360	# else /* PAE */
2361	unsigned iPDSrc;
2362	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2363	if (!pPDSrc)
2364	return VINF_SUCCESS; /* not present */
2365	# endif
2366	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2367	# else
2368	PGSTPD pPDSrc = NULL;
2369	const unsigned iPDSrc = 0;
2370	GSTPDE PdeSrc;
2371
2372	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2373	PdeSrc.n.u1Present = 1;
2374	PdeSrc.n.u1Write = 1;
2375	PdeSrc.n.u1Accessed = 1;
2376	PdeSrc.n.u1User = 1;
2377	# endif
2378
2379	# ifdef PGM_SYNC_ACCESSED_BIT
2380	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2381	# else
2382	if (PdeSrc.n.u1Present)
2383	# endif
2384	{
2385	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2386	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2387	# else
2388	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2389	# endif
2390	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2391	{
2392	if (!PdeDst.n.u1Present)
2393	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2394	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2395	else
2396	{
2397	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2398	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2399	* makes no sense to prefetch more than one page.
2400	*/
2401	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2402	if (VBOX_SUCCESS(rc))
2403	rc = VINF_SUCCESS;
2404	}
2405	}
2406	}
2407	return rc;
2408
2409	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2410
2411	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2412	return VERR_INTERNAL_ERROR;
2413	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2414	}
2415
2416
2417
2418
2419	/**
2420	* Syncs a page during a PGMVerifyAccess() call.
2421	*
2422	* @returns VBox status code (informational included).
2423	* @param GCPtrPage The address of the page to sync.
2424	* @param fPage The effective guest page flags.
2425	* @param uErr The trap error code.
2426	*/
2427	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2428	{
2429	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2430
2431	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2432
2433	# ifndef IN_RING0
2434	if (!(fPage & X86_PTE_US))
2435	{
2436	/*
2437	* Mark this page as safe.
2438	*/
2439	/** @todo not correct for pages that contain both code and data!! */
2440	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2441	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2442	}
2443	# endif
2444	/*
2445	* Get guest PD and index.
2446	*/
2447
2448	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2449	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2450	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2451	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2452	# else /* PAE */
2453	unsigned iPDSrc;
2454	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2455	# endif
2456	# else
2457	PGSTPD pPDSrc = NULL;
2458	const unsigned iPDSrc = 0;
2459	# endif
2460	int rc = VINF_SUCCESS;
2461
2462	/*
2463	* First check if the shadow pd is present.
2464	*/
2465	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2466	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2467	# else
2468	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2469	# endif
2470	if (!pPdeDst->n.u1Present)
2471	{
2472	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2473	AssertRC(rc);
2474	if (rc != VINF_SUCCESS)
2475	return rc;
2476	}
2477
2478	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2479	/* Check for dirty bit fault */
2480	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2481	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2482	Log(("PGMVerifyAccess: success (dirty)\n"));
2483	else
2484	{
2485	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2486	#else
2487	{
2488	GSTPDE PdeSrc;
2489	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2490	PdeSrc.n.u1Present = 1;
2491	PdeSrc.n.u1Write = 1;
2492	PdeSrc.n.u1Accessed = 1;
2493	PdeSrc.n.u1User = 1;
2494
2495	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2496	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2497	if (uErr & X86_TRAP_PF_US)
2498	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2499	else /* supervisor */
2500	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2501
2502	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2503	if (VBOX_SUCCESS(rc))
2504	{
2505	/* Page was successfully synced */
2506	Log2(("PGMVerifyAccess: success (sync)\n"));
2507	rc = VINF_SUCCESS;
2508	}
2509	else
2510	{
2511	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2512	return VINF_EM_RAW_GUEST_TRAP;
2513	}
2514	}
2515	return rc;
2516
2517	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2518
2519	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2520	return VERR_INTERNAL_ERROR;
2521	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2522	}
2523
2524
2525	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2526	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2527	/**
2528	* Figures out which kind of shadow page this guest PDE warrants.
2529	*
2530	* @returns Shadow page kind.
2531	* @param pPdeSrc The guest PDE in question.
2532	* @param cr4 The current guest cr4 value.
2533	*/
2534	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2535	{
2536	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2537	return BTH_PGMPOOLKIND_PT_FOR_PT;
2538	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2539	//{
2540	// case 0:
2541	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2542	// case X86_PDE4M_RW:
2543	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2544	// case X86_PDE4M_US:
2545	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2546	// case X86_PDE4M_RW \| X86_PDE4M_US:
2547	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2548	# if 0
2549	// case X86_PDE4M_PAE_NX:
2550	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2551	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2552	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2553	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2554	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2555	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2556	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2557	# endif
2558	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2559	//}
2560	}
2561	# endif
2562	#endif
2563
2564	#undef MY_STAM_COUNTER_INC
2565	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2566
2567
2568	/**
2569	* Syncs the paging hierarchy starting at CR3.
2570	*
2571	* @returns VBox status code, no specials.
2572	* @param pVM The virtual machine.
2573	* @param cr0 Guest context CR0 register
2574	* @param cr3 Guest context CR3 register
2575	* @param cr4 Guest context CR4 register
2576	* @param fGlobal Including global page directories or not
2577	*/
2578	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint32_t cr0, uint32_t cr3, uint32_t cr4, bool fGlobal)
2579	{
2580	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2581	fGlobal = true; /* Change this CR3 reload to be a global one. */
2582
2583	/*
2584	* Update page access handlers.
2585	* The virtual are always flushed, while the physical are only on demand.
2586	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2587	* have to look into that later because it will have a bad influence on the performance.
2588	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2589	* bird: Yes, but that won't work for aliases.
2590	*/
2591	/** @todo this MUST go away. See #1557. */
2592	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2593	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2594	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2595
2596	#ifdef PGMPOOL_WITH_MONITORING
2597	/*
2598	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2599	* Occationally we will have to clear all the shadow page tables because we wanted
2600	* to monitor a page which was mapped by too many shadowed page tables. This operation
2601	* sometimes refered to as a 'lightweight flush'.
2602	*/
2603	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2604	pgmPoolMonitorModifiedClearAll(pVM);
2605	else
2606	{
2607	# ifdef IN_RING3
2608	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2609	pgmPoolClearAll(pVM);
2610	# else
2611	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2612	return VINF_PGM_SYNC_CR3;
2613	# endif
2614	}
2615	#endif
2616
2617	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2618	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2619
2620	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2621	/*
2622	* Get page directory addresses.
2623	*/
2624	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2625	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2626	# else
2627	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2628	# endif
2629
2630	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2631	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2632	Assert(pPDSrc);
2633	# ifndef IN_GC
2634	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2635	# endif
2636	# endif
2637
2638	/*
2639	* Iterate the page directory.
2640	*/
2641	PPGMMAPPING pMapping;
2642	unsigned iPdNoMapping;
2643	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2644	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2645
2646	/* Only check mappings if they are supposed to be put into the shadow page table. */
2647	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2648	{
2649	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2650	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2651	}
2652	else
2653	{
2654	pMapping = 0;
2655	iPdNoMapping = ~0U;
2656	}
2657	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2658	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2659	{
2660	unsigned iPDSrc;
2661	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2662	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2663	# else
2664	AssertFailed(); /* @todo */
2665	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2666	# endif
2667	PX86PDEPAE pPDEDst = &pPDPAE->a[iPDPTE * X86_PG_PAE_ENTRIES];
2668	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2669
2670	if (pPDSrc == NULL)
2671	{
2672	/* PDPT not present */
2673	/** @todo expensive */
2674	ASMMemZero32(pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE], PAGE_SIZE);
2675	continue;
2676	}
2677	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2678	{
2679	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2680	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2681	{
2682	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2683	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2684	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2685	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2686	# endif
2687	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2688	if ( PdeSrc.n.u1Present
2689	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2690	{
2691	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2692	/*
2693	* Check for conflicts with GC mappings.
2694	*/
2695	if (iPD == iPdNoMapping)
2696	{
2697	if (pVM->pgm.s.fMappingsFixed)
2698	{
2699	/* It's fixed, just skip the mapping. */
2700	const unsigned cPTs = pMapping->cPTs;
2701	iPD += cPTs - 1;
2702	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2703	pMapping = pMapping->CTXALLSUFF(pNext);
2704	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2705	continue;
2706	}
2707	# ifdef IN_RING3
2708	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2709	if (VBOX_FAILURE(rc))
2710	return rc;
2711
2712	/*
2713	* Update iPdNoMapping and pMapping.
2714	*/
2715	pMapping = pVM->pgm.s.pMappingsR3;
2716	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2717	pMapping = pMapping->pNextR3;
2718	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2719	# else
2720	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2721	return VINF_PGM_SYNC_CR3;
2722	# endif
2723	}
2724	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2725	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2726	Assert(iPD != iPdNoMapping);
2727	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2728	/*
2729	* Sync page directory entry.
2730	*
2731	* The current approach is to allocated the page table but to set
2732	* the entry to not-present and postpone the page table synching till
2733	* it's actually used.
2734	*/
2735	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2736	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2737	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2738	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2739	# else
2740	const unsigned iPdShw = iPD; NOREF(iPdShw);
2741	# endif
2742	{
2743	SHWPDE PdeDst = *pPDEDst;
2744	if (PdeDst.n.u1Present)
2745	{
2746	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2747	RTGCPHYS GCPhys;
2748	if ( !PdeSrc.b.u1Size
2749	\|\| !(cr4 & X86_CR4_PSE))
2750	{
2751	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2752	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2753	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2754	GCPhys \|= i * (PAGE_SIZE / 2);
2755	# endif
2756	}
2757	else
2758	{
2759	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2760	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2761	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2762	GCPhys \|= i * X86_PAGE_2M_SIZE;
2763	# endif
2764	}
2765
2766	if ( pShwPage->GCPhys == GCPhys
2767	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2768	&& ( pShwPage->fCached
2769	\|\| ( !fGlobal
2770	&& ( false
2771	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2772	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2773	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2774	\|\| ( !pShwPage->fSeenNonGlobal
2775	&& (cr4 & X86_CR4_PGE))
2776	# endif
2777	)
2778	)
2779	)
2780	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2781	\|\| ( (cr4 & X86_CR4_PSE)
2782	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2783	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2784	)
2785	)
2786	{
2787	# ifdef VBOX_WITH_STATISTICS
2788	if ( !fGlobal
2789	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2790	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2791	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2792	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2793	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2794	else
2795	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2796	# endif /* VBOX_WITH_STATISTICS */
2797	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2798	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2799	//# ifdef PGMPOOL_WITH_CACHE
2800	// pgmPoolCacheUsed(pPool, pShwPage);
2801	//# endif
2802	}
2803	else
2804	{
2805	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2806	pPDEDst->u = 0;
2807	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2808	}
2809	}
2810	else
2811	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2812	pPDEDst++;
2813	}
2814	}
2815	else if (iPD != iPdNoMapping)
2816	{
2817	/*
2818	* Check if there is any page directory to mark not present here.
2819	*/
2820	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2821	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2822	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2823	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2824	# else
2825	const unsigned iPdShw = iPD; NOREF(iPdShw);
2826	# endif
2827	{
2828	if (pPDEDst->n.u1Present)
2829	{
2830	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2831	pPDEDst->u = 0;
2832	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2833	}
2834	pPDEDst++;
2835	}
2836	}
2837	else
2838	{
2839	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2840	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2841	const unsigned cPTs = pMapping->cPTs;
2842	if (pVM->pgm.s.fMappingsFixed)
2843	{
2844	/* It's fixed, just skip the mapping. */
2845	pMapping = pMapping->CTXALLSUFF(pNext);
2846	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2847	}
2848	else
2849	{
2850	/*
2851	* Check for conflicts for subsequent pagetables
2852	* and advance to the next mapping.
2853	*/
2854	iPdNoMapping = ~0U;
2855	unsigned iPT = cPTs;
2856	while (iPT-- > 1)
2857	{
2858	if ( pPDSrc->a[iPD + iPT].n.u1Present
2859	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2860	{
2861	# ifdef IN_RING3
2862	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2863	if (VBOX_FAILURE(rc))
2864	return rc;
2865
2866	/*
2867	* Update iPdNoMapping and pMapping.
2868	*/
2869	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2870	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2871	pMapping = pMapping->CTXALLSUFF(pNext);
2872	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2873	break;
2874	# else
2875	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2876	return VINF_PGM_SYNC_CR3;
2877	# endif
2878	}
2879	}
2880	if (iPdNoMapping == ~0U && pMapping)
2881	{
2882	pMapping = pMapping->CTXALLSUFF(pNext);
2883	if (pMapping)
2884	iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2885	}
2886	}
2887
2888	/* advance. */
2889	iPD += cPTs - 1;
2890	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2891	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2892	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2893	AssertFailed();
2894	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2895	}
2896
2897	} /* for iPD */
2898	} /* for each PDPTE (PAE) */
2899
2900	return VINF_SUCCESS;
2901
2902	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2903	//# error not implemented
2904	return VERR_INTERNAL_ERROR;
2905	#else /* guest real and protected mode */
2906	return VINF_SUCCESS;
2907	#endif
2908	}
2909
2910
2911
2912
2913	#ifdef VBOX_STRICT
2914	#ifdef IN_GC
2915	# undef AssertMsgFailed
2916	# define AssertMsgFailed Log
2917	#endif
2918	#ifdef IN_RING3
2919	# include <VBox/dbgf.h>
2920
2921	/**
2922	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2923	*
2924	* @returns VBox status code (VINF_SUCCESS).
2925	* @param pVM The VM handle.
2926	* @param cr3 The root of the hierarchy.
2927	* @param crr The cr4, only PAE and PSE is currently used.
2928	* @param fLongMode Set if long mode, false if not long mode.
2929	* @param cMaxDepth Number of levels to dump.
2930	* @param pHlp Pointer to the output functions.
2931	*/
2932	__BEGIN_DECLS
2933	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2934	__END_DECLS
2935
2936	#endif
2937
2938	/**
2939	* Checks that the shadow page table is in sync with the guest one.
2940	*
2941	* @returns The number of errors.
2942	* @param pVM The virtual machine.
2943	* @param cr3 Guest context CR3 register
2944	* @param cr4 Guest context CR4 register
2945	* @param GCPtr Where to start. Defaults to 0.
2946	* @param cb How much to check. Defaults to everything.
2947	*/
2948	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2949	{
2950	unsigned cErrors = 0;
2951
2952	#if PGM_GST_TYPE == PGM_TYPE_32BIT
2953	PPGM pPGM = &pVM->pgm.s;
2954	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2955	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2956	RTHCPHYS HCPhys; /* general usage. */
2957	int rc;
2958
2959	/*
2960	* Check that the Guest CR3 and all it's mappings are correct.
2961	*/
2962	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
2963	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
2964	false);
2965	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
2966	AssertRCReturn(rc, 1);
2967	HCPhys = NIL_RTHCPHYS;
2968	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
2969	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
2970	# ifdef IN_RING3
2971	RTGCPHYS GCPhys;
2972	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
2973	AssertRCReturn(rc, 1);
2974	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
2975	# endif
2976	const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
2977
2978	/*
2979	* Get and check the Shadow CR3.
2980	*/
2981	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2982	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
2983	unsigned cPDEs = ELEMENTS(pPDDst->a);
2984	# else
2985	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
2986	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
2987	# endif
2988	if (cb != ~(RTGCUINTPTR)0)
2989	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
2990
2991	/** @todo call the other two PGMAssert() functions. /
2992
2993	/*
2994	* Iterate the shadow page directory.
2995	*/
2996	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
2997	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
2998	cPDEs += iPDDst;
2999	for (;
3000	iPDDst < cPDEs;
3001	iPDDst++, GCPtr += _4G / cPDEs)
3002	{
3003	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3004	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3005	{
3006	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3007	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3008	{
3009	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3010	cErrors++;
3011	continue;
3012	}
3013	}
3014	else if ( (PdeDst.u & X86_PDE_P)
3015	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3016	)
3017	{
3018	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3019	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3020	if (!pPoolPage)
3021	{
3022	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3023	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3024	cErrors++;
3025	continue;
3026	}
3027	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3028
3029	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3030	{
3031	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3032	GCPtr, (uint64_t)PdeDst.u));
3033	cErrors++;
3034	}
3035
3036	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3037	{
3038	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3039	GCPtr, (uint64_t)PdeDst.u));
3040	cErrors++;
3041	}
3042
3043	const X86PDE PdeSrc = pPDSrc->a[iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)];
3044	if (!PdeSrc.n.u1Present)
3045	{
3046	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3047	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3048	cErrors++;
3049	continue;
3050	}
3051
3052	if ( !PdeSrc.b.u1Size
3053	\|\| !(cr4 & X86_CR4_PSE))
3054	{
3055	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3056	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3057	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3058	# endif
3059	}
3060	else
3061	{
3062	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3063	{
3064	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3065	GCPtr, (uint64_t)PdeSrc.u));
3066	cErrors++;
3067	continue;
3068	}
3069	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3070	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3071	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3072	# endif
3073	}
3074
3075	if ( pPoolPage->enmKind
3076	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3077	{
3078	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3079	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3080	cErrors++;
3081	}
3082
3083	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3084	if (!pPhysPage)
3085	{
3086	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3087	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3088	cErrors++;
3089	continue;
3090	}
3091
3092	if (GCPhysGst != pPoolPage->GCPhys)
3093	{
3094	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3095	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3096	cErrors++;
3097	continue;
3098	}
3099
3100	if ( !PdeSrc.b.u1Size
3101	\|\| !(cr4 & X86_CR4_PSE))
3102	{
3103	/*
3104	* Page Table.
3105	*/
3106	const GSTPT *pPTSrc;
3107	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3108	if (VBOX_FAILURE(rc))
3109	{
3110	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3111	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3112	cErrors++;
3113	continue;
3114	}
3115	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3116	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3117	{
3118	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3119	// (This problem will go away when/if we shadow multiple CR3s.)
3120	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3121	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3122	cErrors++;
3123	continue;
3124	}
3125	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3126	{
3127	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3128	GCPtr, (uint64_t)PdeDst.u));
3129	cErrors++;
3130	continue;
3131	}
3132
3133	/* iterate the page table. */
3134	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3135	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3136	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3137	# else
3138	const unsigned offPTSrc = 0;
3139	# endif
3140	for (unsigned iPT = 0, off = 0;
3141	iPT < ELEMENTS(pPTDst->a);
3142	iPT++, off += PAGE_SIZE)
3143	{
3144	const SHWPTE PteDst = pPTDst->a[iPT];
3145
3146	/* skip not-present entries. */
3147	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3148	continue;
3149	Assert(PteDst.n.u1Present);
3150
3151	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3152	if (!PteSrc.n.u1Present)
3153	{
3154	#ifdef IN_RING3
3155	PGMAssertHandlerAndFlagsInSync(pVM);
3156	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3157	#endif
3158	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3159	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3160	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3161	cErrors++;
3162	continue;
3163	}
3164
3165	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3166	# if 1 /** @todo sync accessed bit properly... */
3167	fIgnoreFlags \|= X86_PTE_A;
3168	# endif
3169
3170	/* match the physical addresses */
3171	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3172	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3173
3174	# ifdef IN_RING3
3175	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3176	if (VBOX_FAILURE(rc))
3177	{
3178	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3179	{
3180	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3181	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3182	cErrors++;
3183	continue;
3184	}
3185	}
3186	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3187	{
3188	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3189	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3190	cErrors++;
3191	continue;
3192	}
3193	# endif
3194
3195	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3196	if (!pPhysPage)
3197	{
3198	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3199	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3200	{
3201	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3202	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3203	cErrors++;
3204	continue;
3205	}
3206	# endif
3207	if (PteDst.n.u1Write)
3208	{
3209	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3210	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3211	cErrors++;
3212	}
3213	fIgnoreFlags \|= X86_PTE_RW;
3214	}
3215	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3216	{
3217	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3218	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3219	cErrors++;
3220	continue;
3221	}
3222
3223	/* flags */
3224	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3225	{
3226	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3227	{
3228	if (PteDst.n.u1Write)
3229	{
3230	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3231	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3232	cErrors++;
3233	continue;
3234	}
3235	fIgnoreFlags \|= X86_PTE_RW;
3236	}
3237	else
3238	{
3239	if (PteDst.n.u1Present)
3240	{
3241	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3242	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3243	cErrors++;
3244	continue;
3245	}
3246	fIgnoreFlags \|= X86_PTE_P;
3247	}
3248	}
3249	else
3250	{
3251	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3252	{
3253	if (PteDst.n.u1Write)
3254	{
3255	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3256	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3257	cErrors++;
3258	continue;
3259	}
3260	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3261	{
3262	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3263	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3264	cErrors++;
3265	continue;
3266	}
3267	if (PteDst.n.u1Dirty)
3268	{
3269	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3270	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3271	cErrors++;
3272	}
3273	# if 0 /** @todo sync access bit properly... */
3274	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3275	{
3276	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3277	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3278	cErrors++;
3279	}
3280	fIgnoreFlags \|= X86_PTE_RW;
3281	# else
3282	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3283	# endif
3284	}
3285	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3286	{
3287	/* access bit emulation (not implemented). */
3288	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3289	{
3290	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3291	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3292	cErrors++;
3293	continue;
3294	}
3295	if (!PteDst.n.u1Accessed)
3296	{
3297	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3298	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3299	cErrors++;
3300	}
3301	fIgnoreFlags \|= X86_PTE_P;
3302	}
3303	# ifdef DEBUG_sandervl
3304	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3305	# endif
3306	}
3307
3308	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3309	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3310	)
3311	{
3312	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3313	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3314	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3315	cErrors++;
3316	continue;
3317	}
3318	} /* foreach PTE */
3319	}
3320	else
3321	{
3322	/*
3323	* Big Page.
3324	*/
3325	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3326	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3327	{
3328	if (PdeDst.n.u1Write)
3329	{
3330	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3331	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3332	cErrors++;
3333	continue;
3334	}
3335	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3336	{
3337	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3338	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3339	cErrors++;
3340	continue;
3341	}
3342	# if 0 /** @todo sync access bit properly... */
3343	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3344	{
3345	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3346	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3347	cErrors++;
3348	}
3349	fIgnoreFlags \|= X86_PTE_RW;
3350	# else
3351	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3352	# endif
3353	}
3354	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3355	{
3356	/* access bit emulation (not implemented). */
3357	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3358	{
3359	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3360	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3361	cErrors++;
3362	continue;
3363	}
3364	if (!PdeDst.n.u1Accessed)
3365	{
3366	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3367	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3368	cErrors++;
3369	}
3370	fIgnoreFlags \|= X86_PTE_P;
3371	}
3372
3373	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3374	{
3375	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3376	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3377	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3378	cErrors++;
3379	}
3380
3381	/* iterate the page table. */
3382	for (unsigned iPT = 0, off = 0;
3383	iPT < ELEMENTS(pPTDst->a);
3384	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3385	{
3386	const SHWPTE PteDst = pPTDst->a[iPT];
3387
3388	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3389	{
3390	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3391	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3392	cErrors++;
3393	}
3394
3395	/* skip not-present entries. */
3396	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3397	continue;
3398
3399	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3400
3401	/* match the physical addresses */
3402	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3403
3404	# ifdef IN_RING3
3405	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3406	if (VBOX_FAILURE(rc))
3407	{
3408	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3409	{
3410	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3411	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3412	cErrors++;
3413	}
3414	}
3415	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3416	{
3417	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3418	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3419	cErrors++;
3420	continue;
3421	}
3422	# endif
3423
3424	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3425	if (!pPhysPage)
3426	{
3427	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3428	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3429	{
3430	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3431	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3432	cErrors++;
3433	continue;
3434	}
3435	# endif
3436	if (PteDst.n.u1Write)
3437	{
3438	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3439	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3440	cErrors++;
3441	}
3442	fIgnoreFlags \|= X86_PTE_RW;
3443	}
3444	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3445	{
3446	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3447	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3448	cErrors++;
3449	continue;
3450	}
3451
3452	/* flags */
3453	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3454	{
3455	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3456	{
3457	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3458	{
3459	if (PteDst.n.u1Write)
3460	{
3461	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3462	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3463	cErrors++;
3464	continue;
3465	}
3466	fIgnoreFlags \|= X86_PTE_RW;
3467	}
3468	}
3469	else
3470	{
3471	if (PteDst.n.u1Present)
3472	{
3473	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3474	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3475	cErrors++;
3476	continue;
3477	}
3478	fIgnoreFlags \|= X86_PTE_P;
3479	}
3480	}
3481
3482	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3483	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3484	)
3485	{
3486	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3487	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3488	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3489	cErrors++;
3490	continue;
3491	}
3492	} /* foreach PTE */
3493	}
3494	}
3495	/* not present */
3496
3497	} /* forearch PDE */
3498
3499	# ifdef DEBUG
3500	if (cErrors)
3501	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3502	# endif
3503
3504	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3505	//# error not implemented
3506
3507
3508	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3509	//# error not implemented
3510
3511	/#else: guest real and protected mode /
3512	#endif
3513	return cErrors;
3514	}
3515	#endif /* VBOX_STRICT */
3516

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7819

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