PGMAllBth.h@ 7904

Last change on this file since 7904 was 7904, checked in by vboxsync, 17 years ago
Additional checks for pgmGstGetPaePDPtr return value
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File size: 156.0 KB

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1	/* $Id: PGMAllBth.h 7904 2008-04-11 09:39:47Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
42	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
43	#error "Invalid combination; PAE guest implies PAE shadow"
44	#endif
45
46	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
47	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
48	#error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
53	#error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
57	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
58	#error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
59	#endif
60
61	/**
62	* #PF Handler for raw-mode guest execution.
63	*
64	* @returns VBox status code (appropriate for trap handling and GC return).
65	* @param pVM VM Handle.
66	* @param uErr The trap error code.
67	* @param pRegFrame Trap register frame.
68	* @param pvFault The fault address.
69	*/
70	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
71	{
72	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
73
74	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
75	/*
76	* Hide the instruction fetch trap indicator for now.
77	*/
78	/** @todo NXE will change this and we must fix NXE in the switcher too! */
79	if (uErr & X86_TRAP_PF_ID)
80	{
81	uErr &= ~X86_TRAP_PF_ID;
82	TRPMSetErrorCode(pVM, uErr);
83	}
84	# endif
85
86	/*
87	* Get PDs.
88	*/
89	int rc;
90	# if PGM_WITH_PAGING(PGM_GST_TYPE)
91	# if PGM_GST_TYPE == PGM_TYPE_32BIT
92	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
93	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
94	# else /* PAE */
95	unsigned iPDSrc;
96	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
97
98	/* Quick check for a valid guest trap. */
99	if (!pPDSrc)
100	{
101	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
102	TRPMSetErrorCode(pVM, uErr);
103	return VINF_EM_RAW_GUEST_TRAP;
104	}
105	# endif
106	# else
107	PGSTPD pPDSrc = NULL;
108	const unsigned iPDSrc = 0;
109	# endif
110
111	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
112	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
113	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
114	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
115	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
116
117	# if PGM_GST_TYPE == PGM_TYPE_PAE
118	/* Did we mark the PDPT as not present in SyncCR3? */
119	unsigned iPDPTE = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
120	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
121	{
122	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 1;
123	}
124	# endif
125	# else
126	AssertFailed();
127	# endif
128
129	# if PGM_WITH_PAGING(PGM_GST_TYPE)
130	# ifdef PGM_SYNC_DIRTY_BIT
131	/*
132	* If we successfully correct the write protection fault due to dirty bit
133	* tracking, or this page fault is a genuine one, then return immediately.
134	*/
135	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
136	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
137	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
138	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
139	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
140	{
141	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
142	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
143	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
144	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
145	}
146	# endif
147
148	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
149	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
150
151	/*
152	* A common case is the not-present error caused by lazy page table syncing.
153	*
154	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
155	* so we can safely assume that the shadow PT is present when calling SyncPage later.
156	*
157	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
158	* of mapping conflict and defer to SyncCR3 in R3.
159	* (Again, we do NOT support access handlers for non-present guest pages.)
160	*
161	*/
162	# if PGM_WITH_PAGING(PGM_GST_TYPE)
163	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
164	# else
165	GSTPDE PdeSrc;
166	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
167	PdeSrc.n.u1Present = 1;
168	PdeSrc.n.u1Write = 1;
169	PdeSrc.n.u1Accessed = 1;
170	PdeSrc.n.u1User = 1;
171	# endif
172	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
173	&& !pPDDst->a[iPDDst].n.u1Present
174	&& PdeSrc.n.u1Present
175	)
176
177	{
178	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
179	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
180	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
181	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
182	if (VBOX_SUCCESS(rc))
183	{
184	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
185	return rc;
186	}
187	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
188	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
189	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
190	return VINF_PGM_SYNC_CR3;
191	}
192
193	# if PGM_WITH_PAGING(PGM_GST_TYPE)
194	/*
195	* Check if this address is within any of our mappings.
196	*
197	* This is very fast and it's gonna save us a bit of effort below and prevent
198	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
199	* (BTW, it's impossible to have physical access handlers in a mapping.)
200	*/
201	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
202	{
203	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
204	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
205	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
206	{
207	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
208	break;
209	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
210	{
211	/*
212	* The first thing we check is if we've got an undetected conflict.
213	*/
214	if (!pVM->pgm.s.fMappingsFixed)
215	{
216	unsigned iPT = pMapping->cPTs;
217	while (iPT-- > 0)
218	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
219	{
220	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
221	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
222	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
223	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
224	return VINF_PGM_SYNC_CR3;
225	}
226	}
227
228	/*
229	* Check if the fault address is in a virtual page access handler range.
230	*/
231	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
232	if ( pCur
233	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
234	&& uErr & X86_TRAP_PF_RW)
235	{
236	# ifdef IN_GC
237	STAM_PROFILE_START(&pCur->Stat, h);
238	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
239	STAM_PROFILE_STOP(&pCur->Stat, h);
240	# else
241	AssertFailed();
242	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
243	# endif
244	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
245	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
246	return rc;
247	}
248
249	/*
250	* Pretend we're not here and let the guest handle the trap.
251	*/
252	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
253	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
254	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
255	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
256	return VINF_EM_RAW_GUEST_TRAP;
257	}
258	}
259	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
260	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
261	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
262
263	/*
264	* Check if this fault address is flagged for special treatment,
265	* which means we'll have to figure out the physical address and
266	* check flags associated with it.
267	*
268	* ASSUME that we can limit any special access handling to pages
269	* in page tables which the guest believes to be present.
270	*/
271	if (PdeSrc.n.u1Present)
272	{
273	RTGCPHYS GCPhys = NIL_RTGCPHYS;
274
275	# if PGM_WITH_PAGING(PGM_GST_TYPE)
276	uint32_t cr4 = CPUMGetGuestCR4(pVM);
277	if ( PdeSrc.b.u1Size
278	&& (cr4 & X86_CR4_PSE))
279	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
280	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
281	else
282	{
283	PGSTPT pPTSrc;
284	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
285	if (VBOX_SUCCESS(rc))
286	{
287	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
288	if (pPTSrc->a[iPTESrc].n.u1Present)
289	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
290	}
291	}
292	# else
293	/* No paging so the fault address is the physical address */
294	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
295	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
296
297	/*
298	* If we have a GC address we'll check if it has any flags set.
299	*/
300	if (GCPhys != NIL_RTGCPHYS)
301	{
302	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
303
304	PPGMPAGE pPage;
305	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
306	if (VBOX_SUCCESS(rc))
307	{
308	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
309	{
310	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
311	{
312	/*
313	* Physical page access handler.
314	*/
315	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
316	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
317	if (pCur)
318	{
319	# ifdef PGM_SYNC_N_PAGES
320	/*
321	* If the region is write protected and we got a page not present fault, then sync
322	* the pages. If the fault was caused by a read, then restart the instruction.
323	* In case of write access continue to the GC write handler.
324	*
325	* ASSUMES that there is only one handler per page or that they have similar write properties.
326	*/
327	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
328	&& !(uErr & X86_TRAP_PF_P))
329	{
330	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
331	if ( VBOX_FAILURE(rc)
332	\|\| !(uErr & X86_TRAP_PF_RW)
333	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
334	{
335	AssertRC(rc);
336	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
337	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
338	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
339	return rc;
340	}
341	}
342	# endif
343
344	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
345	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
346	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
347
348	#if defined(IN_GC) \|\| defined(IN_RING0)
349	if (CTXALLSUFF(pCur->pfnHandler))
350	{
351	STAM_PROFILE_START(&pCur->Stat, h);
352	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
353	STAM_PROFILE_STOP(&pCur->Stat, h);
354	}
355	else
356	#endif
357	rc = VINF_EM_RAW_EMULATE_INSTR;
358	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
359	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
360	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
361	return rc;
362	}
363	}
364	# if PGM_WITH_PAGING(PGM_GST_TYPE)
365	else
366	{
367	# ifdef PGM_SYNC_N_PAGES
368	/*
369	* If the region is write protected and we got a page not present fault, then sync
370	* the pages. If the fault was caused by a read, then restart the instruction.
371	* In case of write access continue to the GC write handler.
372	*/
373	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
374	&& !(uErr & X86_TRAP_PF_P))
375	{
376	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
377	if ( VBOX_FAILURE(rc)
378	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
379	\|\| !(uErr & X86_TRAP_PF_RW))
380	{
381	AssertRC(rc);
382	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
383	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
384	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
385	return rc;
386	}
387	}
388	# endif
389	/*
390	* Ok, it's an virtual page access handler.
391	*
392	* Since it's faster to search by address, we'll do that first
393	* and then retry by GCPhys if that fails.
394	*/
395	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
396	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
397	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
398	*/
399	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
400	if (pCur)
401	{
402	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
403	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
404	\|\| !(uErr & X86_TRAP_PF_P)
405	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
406	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
407
408	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
409	&& ( uErr & X86_TRAP_PF_RW
410	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
411	{
412	# ifdef IN_GC
413	STAM_PROFILE_START(&pCur->Stat, h);
414	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
415	STAM_PROFILE_STOP(&pCur->Stat, h);
416	# else
417	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
418	# endif
419	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
420	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
421	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
422	return rc;
423	}
424	/* Unhandled part of a monitored page */
425	}
426	else
427	{
428	/* Check by physical address. */
429	PPGMVIRTHANDLER pCur;
430	unsigned iPage;
431	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
432	&pCur, &iPage);
433	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
434	if ( pCur
435	&& ( uErr & X86_TRAP_PF_RW
436	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
437	{
438	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
439	# ifdef IN_GC
440	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
441	Assert(off < pCur->cb);
442	STAM_PROFILE_START(&pCur->Stat, h);
443	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
444	STAM_PROFILE_STOP(&pCur->Stat, h);
445	# else
446	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
447	# endif
448	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
449	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
450	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
451	return rc;
452	}
453	}
454	}
455	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
456
457	/*
458	* There is a handled area of the page, but this fault doesn't belong to it.
459	* We must emulate the instruction.
460	*
461	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
462	* we first check if this was a page-not-present fault for a page with only
463	* write access handlers. Restart the instruction if it wasn't a write access.
464	*/
465	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
466
467	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
468	&& !(uErr & X86_TRAP_PF_P))
469	{
470	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
471	if ( VBOX_FAILURE(rc)
472	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
473	\|\| !(uErr & X86_TRAP_PF_RW))
474	{
475	AssertRC(rc);
476	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
477	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
478	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
479	return rc;
480	}
481	}
482
483	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
484	* It's writing to an unhandled part of the LDT page several million times.
485	*/
486	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
487	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
488	rc, pPage->HCPhys,
489	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
490	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
491	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
492	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
493	return rc;
494	} /* if any kind of handler */
495
496	# if PGM_WITH_PAGING(PGM_GST_TYPE)
497	if (uErr & X86_TRAP_PF_P)
498	{
499	/*
500	* The page isn't marked, but it might still be monitored by a virtual page access handler.
501	* (ASSUMES no temporary disabling of virtual handlers.)
502	*/
503	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
504	* we should correct both the shadow page table and physical memory flags, and not only check for
505	* accesses within the handler region but for access to pages with virtual handlers. */
506	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
507	if (pCur)
508	{
509	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
510	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
511	\|\| !(uErr & X86_TRAP_PF_P)
512	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
513	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
514
515	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
516	&& ( uErr & X86_TRAP_PF_RW
517	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
518	{
519	# ifdef IN_GC
520	STAM_PROFILE_START(&pCur->Stat, h);
521	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
522	STAM_PROFILE_STOP(&pCur->Stat, h);
523	# else
524	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
525	# endif
526	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
527	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
528	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
529	return rc;
530	}
531	}
532	}
533	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
534	}
535	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
536
537	# ifdef PGM_OUT_OF_SYNC_IN_GC
538	/*
539	* We are here only if page is present in Guest page tables and trap is not handled
540	* by our handlers.
541	* Check it for page out-of-sync situation.
542	*/
543	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
544
545	if (!(uErr & X86_TRAP_PF_P))
546	{
547	/*
548	* Page is not present in our page tables.
549	* Try to sync it!
550	* BTW, fPageShw is invalid in this branch!
551	*/
552	if (uErr & X86_TRAP_PF_US)
553	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
554	else /* supervisor */
555	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
556
557	# if defined(LOG_ENABLED) && !defined(IN_RING0)
558	RTGCPHYS GCPhys;
559	uint64_t fPageGst;
560	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
561	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
562	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
563	# endif /* LOG_ENABLED */
564
565	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
566	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
567	{
568	uint64_t fPageGst;
569	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
570	if ( VBOX_SUCCESS(rc)
571	&& !(fPageGst & X86_PTE_US))
572	{
573	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
574	if ( pvFault == (RTGCPTR)pRegFrame->eip
575	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
576	# ifdef CSAM_DETECT_NEW_CODE_PAGES
577	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
578	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
579	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
580	)
581	{
582	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
583	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
584	if (rc != VINF_SUCCESS)
585	{
586	/*
587	* CSAM needs to perform a job in ring 3.
588	*
589	* Sync the page before going to the host context; otherwise we'll end up in a loop if
590	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
591	*/
592	LogFlow(("CSAM ring 3 job\n"));
593	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
594	AssertRC(rc2);
595
596	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
597	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
598	return rc;
599	}
600	}
601	# ifdef CSAM_DETECT_NEW_CODE_PAGES
602	else
603	if ( uErr == X86_TRAP_PF_RW
604	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
605	&& pRegFrame->ecx < 0x10000
606	)
607	{
608	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
609	* to detect loading of new code pages.
610	*/
611
612	/*
613	* Decode the instruction.
614	*/
615	RTGCPTR PC;
616	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
617	if (rc == VINF_SUCCESS)
618	{
619	DISCPUSTATE Cpu;
620	uint32_t cbOp;
621	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
622
623	/* For now we'll restrict this to rep movsw/d instructions */
624	if ( rc == VINF_SUCCESS
625	&& Cpu.pCurInstr->opcode == OP_MOVSWD
626	&& (Cpu.prefix & PREFIX_REP))
627	{
628	CSAMMarkPossibleCodePage(pVM, pvFault);
629	}
630	}
631	}
632	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
633
634	/*
635	* Mark this page as safe.
636	*/
637	/** @todo not correct for pages that contain both code and data!! */
638	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
639	CSAMMarkPage(pVM, pvFault, true);
640	}
641	}
642	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
643	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
644	if (VBOX_SUCCESS(rc))
645	{
646	/* The page was successfully synced, return to the guest. */
647	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
648	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
649	return VINF_SUCCESS;
650	}
651	}
652	else
653	{
654	/*
655	* A side effect of not flushing global PDEs are out of sync pages due
656	* to physical monitored regions, that are no longer valid.
657	* Assume for now it only applies to the read/write flag
658	*/
659	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
660	{
661	if (uErr & X86_TRAP_PF_US)
662	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
663	else /* supervisor */
664	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
665
666
667	/*
668	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
669	*/
670	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
671	if (VBOX_SUCCESS(rc))
672	{
673	/*
674	* Page was successfully synced, return to guest.
675	*/
676	# ifdef VBOX_STRICT
677	RTGCPHYS GCPhys;
678	uint64_t fPageGst;
679	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
680	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
681	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
682
683	uint64_t fPageShw;
684	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
685	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
686	# endif /* VBOX_STRICT */
687	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
688	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
689	return VINF_SUCCESS;
690	}
691
692	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
693	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
694	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
695	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
696	{
697	uint64_t fPageGst;
698	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
699	if ( VBOX_SUCCESS(rc)
700	&& !(fPageGst & X86_PTE_RW))
701	{
702	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
703	if (VBOX_SUCCESS(rc))
704	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
705	else
706	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
707	return rc;
708	}
709	else
710	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
711	}
712
713	}
714
715	# if PGM_WITH_PAGING(PGM_GST_TYPE)
716	# ifdef VBOX_STRICT
717	/*
718	* Check for VMM page flags vs. Guest page flags consistency.
719	* Currently only for debug purposes.
720	*/
721	if (VBOX_SUCCESS(rc))
722	{
723	/* Get guest page flags. */
724	uint64_t fPageGst;
725	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
726	if (VBOX_SUCCESS(rc))
727	{
728	uint64_t fPageShw;
729	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
730
731	/*
732	* Compare page flags.
733	* Note: we have AVL, A, D bits desynched.
734	*/
735	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
736	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
737	}
738	else
739	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
740	}
741	else
742	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
743	# endif /* VBOX_STRICT */
744	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
745	}
746	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
747	# endif /* PGM_OUT_OF_SYNC_IN_GC */
748	}
749	else
750	{
751	/*
752	* Page not present in Guest OS or invalid page table address.
753	* This is potential virtual page access handler food.
754	*
755	* For the present we'll say that our access handlers don't
756	* work for this case - we've already discarded the page table
757	* not present case which is identical to this.
758	*
759	* When we perchance find we need this, we will probably have AVL
760	* trees (offset based) to operate on and we can measure their speed
761	* agains mapping a page table and probably rearrange this handling
762	* a bit. (Like, searching virtual ranges before checking the
763	* physical address.)
764	*/
765	}
766	}
767
768
769	# if PGM_WITH_PAGING(PGM_GST_TYPE)
770	/*
771	* Conclusion, this is a guest trap.
772	*/
773	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
774	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
775	return VINF_EM_RAW_GUEST_TRAP;
776	# else
777	/* present, but not a monitored page; perhaps the guest is probing physical memory */
778	return VINF_EM_RAW_EMULATE_INSTR;
779	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
780
781
782	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
783
784	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
785	return VERR_INTERNAL_ERROR;
786	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
787	}
788
789
790	/**
791	* Emulation of the invlpg instruction.
792	*
793	*
794	* @returns VBox status code.
795	*
796	* @param pVM VM handle.
797	* @param GCPtrPage Page to invalidate.
798	*
799	* @remark ASSUMES that the guest is updating before invalidating. This order
800	* isn't required by the CPU, so this is speculative and could cause
801	* trouble.
802	*
803	* @todo Flush page or page directory only if necessary!
804	* @todo Add a #define for simply invalidating the page.
805	*/
806	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
807	{
808	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
809	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
810
811	LogFlow(("InvalidatePage %x\n", GCPtrPage));
812	/*
813	* Get the shadow PD entry and skip out if this PD isn't present.
814	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
815	*/
816	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
817	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
818	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
819	# else
820	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
821	# endif
822	const SHWPDE PdeDst = *pPdeDst;
823	if (!PdeDst.n.u1Present)
824	{
825	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
826	return VINF_SUCCESS;
827	}
828
829	/*
830	* Get the guest PD entry and calc big page.
831	*/
832	# if PGM_GST_TYPE == PGM_TYPE_32BIT
833	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
834	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
835	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
836	# else /* PAE */
837	unsigned iPDSrc;
838	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
839	GSTPDE PdeSrc;
840
841	if (pPDSrc)
842	PdeSrc = pPDSrc->a[iPDSrc];
843	else
844	PdeSrc.u = 0;
845	# endif
846
847	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
848	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
849
850	# ifdef IN_RING3
851	/*
852	* If a CR3 Sync is pending we may ignore the invalidate page operation
853	* depending on the kind of sync and if it's a global page or not.
854	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
855	*/
856	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
857	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
858	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
859	&& fIsBigPage
860	&& PdeSrc.b.u1Global
861	&& (cr4 & X86_CR4_PGE)
862	)
863	)
864	# else
865	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
866	# endif
867	{
868	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
869	return VINF_SUCCESS;
870	}
871	# endif /* IN_RING3 */
872
873
874	/*
875	* Deal with the Guest PDE.
876	*/
877	int rc = VINF_SUCCESS;
878	if (PdeSrc.n.u1Present)
879	{
880	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
881	{
882	/*
883	* Conflict - Let SyncPT deal with it to avoid duplicate code.
884	*/
885	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
886	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
887	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
888	}
889	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
890	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
891	{
892	/*
893	* Mark not present so we can resync the PDE when it's used.
894	*/
895	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
896	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
897	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
898	pPdeDst->u = 0;
899	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
900	PGM_INVL_GUEST_TLBS();
901	}
902	# ifdef PGM_SYNC_ACCESSED_BIT
903	else if (!PdeSrc.n.u1Accessed)
904	{
905	/*
906	* Mark not present so we can set the accessed bit.
907	*/
908	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
909	pPdeDst->u = 0;
910	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
911	PGM_INVL_GUEST_TLBS();
912	}
913	# endif
914	else if (!fIsBigPage)
915	{
916	/*
917	* 4KB - page.
918	*/
919	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
920	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
921	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
922	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
923	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
924	# endif
925	if (pShwPage->GCPhys == GCPhys)
926	{
927	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
928	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
929	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
930	if (pPT->a[iPTEDst].n.u1Present)
931	{
932	# ifdef PGMPOOL_WITH_USER_TRACKING
933	/* This is very unlikely with caching/monitoring enabled. */
934	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
935	# endif
936	pPT->a[iPTEDst].u = 0;
937	}
938	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
939	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
940	if (VBOX_SUCCESS(rc))
941	rc = VINF_SUCCESS;
942	# endif
943	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
944	PGM_INVL_PG(GCPtrPage);
945	}
946	else
947	{
948	/*
949	* The page table address changed.
950	*/
951	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
952	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
953	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
954	pPdeDst->u = 0;
955	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
956	PGM_INVL_GUEST_TLBS();
957	}
958	}
959	else
960	{
961	/*
962	* 4MB - page.
963	*/
964	/* Before freeing the page, check if anything really changed. */
965	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
966	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
967	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
968	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
969	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
970	# endif
971	if ( pShwPage->GCPhys == GCPhys
972	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
973	{
974	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
975	/** @todo PAT */
976	# ifdef PGM_SYNC_DIRTY_BIT
977	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
978	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
979	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
980	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
981	# else
982	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
983	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
984	# endif
985	{
986	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
987	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
988	return VINF_SUCCESS;
989	}
990	}
991
992	/*
993	* Ok, the page table is present and it's been changed in the guest.
994	* If we're in host context, we'll just mark it as not present taking the lazy approach.
995	* We could do this for some flushes in GC too, but we need an algorithm for
996	* deciding which 4MB pages containing code likely to be executed very soon.
997	*/
998	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
999	pPdeDst->u = 0;
1000	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1001	PGM_INVL_BIG_PG(GCPtrPage);
1002	}
1003	}
1004	else
1005	{
1006	/*
1007	* Page directory is not present, mark shadow PDE not present.
1008	*/
1009	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1010	{
1011	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1012	pPdeDst->u = 0;
1013	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1014	PGM_INVL_PG(GCPtrPage);
1015	}
1016	else
1017	{
1018	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1019	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1020	}
1021	}
1022
1023	return rc;
1024
1025	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1026	//# error not implemented
1027	return VERR_INTERNAL_ERROR;
1028
1029	#else /* guest real and protected mode */
1030	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1031	return VINF_SUCCESS;
1032	#endif
1033	}
1034
1035
1036	#ifdef PGMPOOL_WITH_USER_TRACKING
1037	/**
1038	* Update the tracking of shadowed pages.
1039	*
1040	* @param pVM The VM handle.
1041	* @param pShwPage The shadow page.
1042	* @param HCPhys The physical page we is being dereferenced.
1043	*/
1044	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1045	{
1046	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1047	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1048	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1049
1050	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1051	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1052	* 2. write protect all shadowed pages. I.e. implement caching.
1053	*/
1054	/*
1055	* Find the guest address.
1056	*/
1057	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1058	pRam;
1059	pRam = CTXALLSUFF(pRam->pNext))
1060	{
1061	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1062	while (iPage-- > 0)
1063	{
1064	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1065	{
1066	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1067	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1068	pShwPage->cPresent--;
1069	pPool->cPresent--;
1070	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1071	return;
1072	}
1073	}
1074	}
1075
1076	for (;;)
1077	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1078	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1079	pShwPage->cPresent--;
1080	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1081	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1082	}
1083
1084
1085	/**
1086	* Update the tracking of shadowed pages.
1087	*
1088	* @param pVM The VM handle.
1089	* @param pShwPage The shadow page.
1090	* @param u16 The top 16-bit of the pPage->HCPhys.
1091	* @param pPage Pointer to the guest page. this will be modified.
1092	* @param iPTDst The index into the shadow table.
1093	*/
1094	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1095	{
1096	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1097	/*
1098	* We're making certain assumptions about the placement of cRef and idx.
1099	*/
1100	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1101	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1102
1103	/*
1104	* Just deal with the simple first time here.
1105	*/
1106	if (!u16)
1107	{
1108	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1109	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1110	}
1111	else
1112	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1113
1114	/* write back, trying to be clever... */
1115	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1116	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1117	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1118	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1119
1120	/* update statistics. */
1121	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1122	pShwPage->cPresent++;
1123	if (pShwPage->iFirstPresent > iPTDst)
1124	pShwPage->iFirstPresent = iPTDst;
1125	}
1126	#endif /* PGMPOOL_WITH_USER_TRACKING */
1127
1128
1129	/**
1130	* Creates a 4K shadow page for a guest page.
1131	*
1132	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1133	* physical address. The PdeSrc argument only the flags are used. No page structured
1134	* will be mapped in this function.
1135	*
1136	* @param pVM VM handle.
1137	* @param pPteDst Destination page table entry.
1138	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1139	* Can safely assume that only the flags are being used.
1140	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1141	* @param pShwPage Pointer to the shadow page.
1142	* @param iPTDst The index into the shadow table.
1143	*
1144	* @remark Not used for 2/4MB pages!
1145	*/
1146	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1147	{
1148	if (PteSrc.n.u1Present)
1149	{
1150	/*
1151	* Find the ram range.
1152	*/
1153	PPGMPAGE pPage;
1154	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1155	if (VBOX_SUCCESS(rc))
1156	{
1157	/** @todo investiage PWT, PCD and PAT. */
1158	/*
1159	* Make page table entry.
1160	*/
1161	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1162	SHWPTE PteDst;
1163	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1164	{
1165	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1166	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1167	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1168	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1169	else
1170	{
1171	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1172	PteDst.u = 0;
1173	}
1174	/** @todo count these two kinds. */
1175	}
1176	else
1177	{
1178	#ifdef PGM_SYNC_DIRTY_BIT
1179	# ifdef PGM_SYNC_ACCESSED_BIT
1180	/*
1181	* If the page or page directory entry is not marked accessed,
1182	* we mark the page not present.
1183	*/
1184	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1185	{
1186	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1187	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1188	PteDst.u = 0;
1189	}
1190	else
1191	# endif
1192	/*
1193	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1194	* when the page is modified.
1195	*/
1196	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1197	{
1198	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1199	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1200	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1201	\| PGM_PTFLAGS_TRACK_DIRTY;
1202	}
1203	else
1204	{
1205	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1206	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1207	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1208	}
1209	#endif
1210	}
1211
1212	#ifdef PGMPOOL_WITH_USER_TRACKING
1213	/*
1214	* Keep user track up to date.
1215	*/
1216	if (PteDst.n.u1Present)
1217	{
1218	if (!pPteDst->n.u1Present)
1219	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1220	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1221	{
1222	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1223	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1224	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1225	}
1226	}
1227	else if (pPteDst->n.u1Present)
1228	{
1229	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1230	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1231	}
1232	#endif /* PGMPOOL_WITH_USER_TRACKING */
1233
1234	/*
1235	* Update statistics and commit the entry.
1236	*/
1237	if (!PteSrc.n.u1Global)
1238	pShwPage->fSeenNonGlobal = true;
1239	*pPteDst = PteDst;
1240	}
1241	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1242	/** @todo count these. */
1243	}
1244	else
1245	{
1246	/*
1247	* Page not-present.
1248	*/
1249	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1250	#ifdef PGMPOOL_WITH_USER_TRACKING
1251	/* Keep user track up to date. */
1252	if (pPteDst->n.u1Present)
1253	{
1254	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1255	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1256	}
1257	#endif /* PGMPOOL_WITH_USER_TRACKING */
1258	pPteDst->u = 0;
1259	/** @todo count these. */
1260	}
1261	}
1262
1263
1264	/**
1265	* Syncs a guest OS page.
1266	*
1267	* There are no conflicts at this point, neither is there any need for
1268	* page table allocations.
1269	*
1270	* @returns VBox status code.
1271	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1272	* @param pVM VM handle.
1273	* @param PdeSrc Page directory entry of the guest.
1274	* @param GCPtrPage Guest context page address.
1275	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1276	* @param uErr Fault error (X86_TRAP_PF_*).
1277	*/
1278	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1279	{
1280	# if PGM_WITH_NX(PGM_GST_TYPE)
1281	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1282	# endif
1283	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1284
1285	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1286	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1287
1288	/*
1289	* Assert preconditions.
1290	*/
1291	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
1292	Assert(PdeSrc.n.u1Present);
1293	Assert(cPages);
1294
1295	/*
1296	* Get the shadow PDE, find the shadow page table in the pool.
1297	*/
1298	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1299	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1300	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1301	# else /* PAE */
1302	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1303	# endif
1304	Assert(PdeDst.n.u1Present);
1305	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1306
1307	/*
1308	* Check that the page is present and that the shadow PDE isn't out of sync.
1309	*/
1310	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1311	RTGCPHYS GCPhys;
1312	if (!fBigPage)
1313	{
1314	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1315	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1316	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1317	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1318	# endif
1319	}
1320	else
1321	{
1322	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1323	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1324	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1325	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1326	# endif
1327	}
1328	if ( pShwPage->GCPhys == GCPhys
1329	&& PdeSrc.n.u1Present
1330	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1331	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1332	# if PGM_WITH_NX(PGM_GST_TYPE)
1333	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1334	# endif
1335	)
1336	{
1337	# ifdef PGM_SYNC_ACCESSED_BIT
1338	/*
1339	* Check that the PDE is marked accessed already.
1340	* Since we set the accessed bit before getting here on a #PF, this
1341	* check is only meant for dealing with non-#PF'ing paths.
1342	*/
1343	if (PdeSrc.n.u1Accessed)
1344	# endif
1345	{
1346	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1347	if (!fBigPage)
1348	{
1349	/*
1350	* 4KB Page - Map the guest page table.
1351	*/
1352	PGSTPT pPTSrc;
1353	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1354	if (VBOX_SUCCESS(rc))
1355	{
1356	# ifdef PGM_SYNC_N_PAGES
1357	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1358	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1359	{
1360	/*
1361	* This code path is currently only taken when the caller is PGMTrap0eHandler
1362	* for non-present pages!
1363	*
1364	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1365	* deal with locality.
1366	*/
1367	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1368	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1369	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1370	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1371	# else
1372	const unsigned offPTSrc = 0;
1373	# endif
1374	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1375	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1376	iPTDst = 0;
1377	else
1378	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1379	for (; iPTDst < iPTDstEnd; iPTDst++)
1380	{
1381	if (!pPTDst->a[iPTDst].n.u1Present)
1382	{
1383	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1384	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1385	NOREF(GCPtrCurPage);
1386	#ifndef IN_RING0
1387	/*
1388	* Assuming kernel code will be marked as supervisor - and not as user level
1389	* and executed using a conforming code selector - And marked as readonly.
1390	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1391	*/
1392	PPGMPAGE pPage;
1393	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1394	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1395	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1396	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1397	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1398	)
1399	#endif /* else: CSAM not active */
1400	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1401	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1402	GCPtrCurPage, PteSrc.n.u1Present,
1403	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1404	PteSrc.n.u1User & PdeSrc.n.u1User,
1405	(uint64_t)PteSrc.u,
1406	(uint64_t)pPTDst->a[iPTDst].u,
1407	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1408	}
1409	}
1410	}
1411	else
1412	# endif /* PGM_SYNC_N_PAGES */
1413	{
1414	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1415	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1416	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1417	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1418	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1419	GCPtrPage, PteSrc.n.u1Present,
1420	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1421	PteSrc.n.u1User & PdeSrc.n.u1User,
1422	(uint64_t)PteSrc.u,
1423	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1424	}
1425	}
1426	else /* MMIO or invalid page: emulated in #PF handler. */
1427	{
1428	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1429	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1430	}
1431	}
1432	else
1433	{
1434	/*
1435	* 4/2MB page - lazy syncing shadow 4K pages.
1436	* (There are many causes of getting here, it's no longer only CSAM.)
1437	*/
1438	/* Calculate the GC physical address of this 4KB shadow page. */
1439	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1440	/* Find ram range. */
1441	PPGMPAGE pPage;
1442	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1443	if (VBOX_SUCCESS(rc))
1444	{
1445	/*
1446	* Make shadow PTE entry.
1447	*/
1448	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1449	SHWPTE PteDst;
1450	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1451	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1452	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1453	{
1454	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1455	PteDst.n.u1Write = 0;
1456	else
1457	PteDst.u = 0;
1458	}
1459	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1460	# ifdef PGMPOOL_WITH_USER_TRACKING
1461	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1462	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1463	# endif
1464	pPTDst->a[iPTDst] = PteDst;
1465
1466
1467	# ifdef PGM_SYNC_DIRTY_BIT
1468	/*
1469	* If the page is not flagged as dirty and is writable, then make it read-only
1470	* at PD level, so we can set the dirty bit when the page is modified.
1471	*
1472	* ASSUMES that page access handlers are implemented on page table entry level.
1473	* Thus we will first catch the dirty access and set PDE.D and restart. If
1474	* there is an access handler, we'll trap again and let it work on the problem.
1475	*/
1476	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1477	* As for invlpg, it simply frees the whole shadow PT.
1478	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1479	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1480	{
1481	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1482	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1483	PdeDst.n.u1Write = 0;
1484	}
1485	else
1486	{
1487	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1488	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1489	}
1490	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1491	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1492	# else /* PAE */
1493	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1494	# endif
1495	# endif /* PGM_SYNC_DIRTY_BIT */
1496	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1497	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1498	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1499	}
1500	else
1501	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1502	}
1503	return VINF_SUCCESS;
1504	}
1505	# ifdef PGM_SYNC_ACCESSED_BIT
1506	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1507	#endif
1508	}
1509	else
1510	{
1511	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1512	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1513	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1514	}
1515
1516	/*
1517	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1518	* Yea, I'm lazy.
1519	*/
1520	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1521	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1522	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1523	# else /* PAE */
1524	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1525	# endif
1526	PGM_INVL_GUEST_TLBS();
1527	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1528
1529	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1530
1531	# ifdef PGM_SYNC_N_PAGES
1532	/*
1533	* Get the shadow PDE, find the shadow page table in the pool.
1534	*/
1535	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1536	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1537	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1538	# else /* PAE */
1539	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1540	# endif
1541	Assert(PdeDst.n.u1Present);
1542	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1543	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1544
1545	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1546	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1547	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1548	# else
1549	const unsigned offPTSrc = 0;
1550	# endif
1551
1552	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1553	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1554	{
1555	/*
1556	* This code path is currently only taken when the caller is PGMTrap0eHandler
1557	* for non-present pages!
1558	*
1559	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1560	* deal with locality.
1561	*/
1562	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1563	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1564	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1565	iPTDst = 0;
1566	else
1567	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1568	for (; iPTDst < iPTDstEnd; iPTDst++)
1569	{
1570	if (!pPTDst->a[iPTDst].n.u1Present)
1571	{
1572	GSTPTE PteSrc;
1573
1574	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1575
1576	/* Fake the page table entry */
1577	PteSrc.u = GCPtrCurPage;
1578	PteSrc.n.u1Present = 1;
1579	PteSrc.n.u1Dirty = 1;
1580	PteSrc.n.u1Accessed = 1;
1581	PteSrc.n.u1Write = 1;
1582	PteSrc.n.u1User = 1;
1583
1584	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1585
1586	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1587	GCPtrCurPage, PteSrc.n.u1Present,
1588	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1589	PteSrc.n.u1User & PdeSrc.n.u1User,
1590	(uint64_t)PteSrc.u,
1591	(uint64_t)pPTDst->a[iPTDst].u,
1592	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1593	}
1594	}
1595	}
1596	else
1597	# endif /* PGM_SYNC_N_PAGES */
1598	{
1599	GSTPTE PteSrc;
1600	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1601	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1602
1603	/* Fake the page table entry */
1604	PteSrc.u = GCPtrCurPage;
1605	PteSrc.n.u1Present = 1;
1606	PteSrc.n.u1Dirty = 1;
1607	PteSrc.n.u1Accessed = 1;
1608	PteSrc.n.u1Write = 1;
1609	PteSrc.n.u1User = 1;
1610	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1611
1612	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1613	GCPtrPage, PteSrc.n.u1Present,
1614	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1615	PteSrc.n.u1User & PdeSrc.n.u1User,
1616	(uint64_t)PteSrc.u,
1617	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1618	}
1619	return VINF_SUCCESS;
1620
1621	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1622	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1623	return VERR_INTERNAL_ERROR;
1624	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1625	}
1626
1627
1628
1629	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1630
1631	# ifdef PGM_SYNC_DIRTY_BIT
1632
1633	/**
1634	* Investigate page fault and handle write protection page faults caused by
1635	* dirty bit tracking.
1636	*
1637	* @returns VBox status code.
1638	* @param pVM VM handle.
1639	* @param uErr Page fault error code.
1640	* @param pPdeDst Shadow page directory entry.
1641	* @param pPdeSrc Guest page directory entry.
1642	* @param GCPtrPage Guest context page address.
1643	*/
1644	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1645	{
1646	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1647	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1648	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1649	# if PGM_WITH_NX(PGM_GST_TYPE)
1650	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1651	# endif
1652
1653	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1654	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1655
1656	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1657	AssertFailed();
1658	# elif PGM_GST_TYPE == PGM_TYPE_PAE
1659	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1660
1661	/*
1662	* Real page fault?
1663	*/
1664	if ( (uErr & X86_TRAP_PF_RSVD)
1665	\|\| !pPdpeSrc->n.u1Present
1666	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1667	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->n.u1NoExecute)
1668	\|\| (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1669	\|\| (fUserLevelFault && !pPdpeSrc->n.u1User)
1670	# endif
1671	)
1672	{
1673	# ifdef IN_GC
1674	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1675	# endif
1676	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1677	LogFlow(("CheckPageFault: real page fault at %VGv (0)\n", GCPtrPage));
1678
1679	if ( pPdpeSrc->n.u1Present
1680	&& pPdeSrc->n.u1Present)
1681	{
1682	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1683	* See the 2nd case below as well.
1684	*/
1685	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1686	{
1687	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1688	}
1689	else
1690	{
1691	/*
1692	* Map the guest page table.
1693	*/
1694	PGSTPT pPTSrc;
1695	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1696	if (VBOX_SUCCESS(rc))
1697	{
1698	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1699	const GSTPTE PteSrc = *pPteSrc;
1700	if (pPteSrc->n.u1Present)
1701	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1702	}
1703	AssertRC(rc);
1704	}
1705	}
1706	return VINF_EM_RAW_GUEST_TRAP;
1707	}
1708	# endif
1709
1710	/*
1711	* Real page fault?
1712	*/
1713	if ( (uErr & X86_TRAP_PF_RSVD)
1714	\|\| !pPdeSrc->n.u1Present
1715	# if PGM_WITH_NX(PGM_GST_TYPE)
1716	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1717	# endif
1718	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1719	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1720	{
1721	# ifdef IN_GC
1722	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1723	# endif
1724	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1725	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1726
1727	if (pPdeSrc->n.u1Present)
1728	{
1729	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1730	* See the 2nd case below as well.
1731	*/
1732	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1733	{
1734	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1735	}
1736	else
1737	{
1738	/*
1739	* Map the guest page table.
1740	*/
1741	PGSTPT pPTSrc;
1742	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1743	if (VBOX_SUCCESS(rc))
1744	{
1745	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1746	const GSTPTE PteSrc = *pPteSrc;
1747	if (pPteSrc->n.u1Present)
1748	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1749	}
1750	AssertRC(rc);
1751	}
1752	}
1753	return VINF_EM_RAW_GUEST_TRAP;
1754	}
1755
1756	/*
1757	* First check the easy case where the page directory has been marked read-only to track
1758	* the dirty bit of an emulated BIG page
1759	*/
1760	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1761	{
1762	/* Mark guest page directory as accessed */
1763	pPdeSrc->b.u1Accessed = 1;
1764
1765	/*
1766	* Only write protection page faults are relevant here.
1767	*/
1768	if (fWriteFault)
1769	{
1770	/* Mark guest page directory as dirty (BIG page only). */
1771	pPdeSrc->b.u1Dirty = 1;
1772
1773	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1774	{
1775	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1776
1777	Assert(pPdeSrc->b.u1Write);
1778
1779	pPdeDst->n.u1Write = 1;
1780	pPdeDst->n.u1Accessed = 1;
1781	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1782	PGM_INVL_BIG_PG(GCPtrPage);
1783	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1784	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1785	}
1786	}
1787	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1788	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1789	}
1790	/* else: 4KB page table */
1791
1792	/*
1793	* Map the guest page table.
1794	*/
1795	PGSTPT pPTSrc;
1796	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1797	if (VBOX_SUCCESS(rc))
1798	{
1799	/*
1800	* Real page fault?
1801	*/
1802	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1803	const GSTPTE PteSrc = *pPteSrc;
1804	if ( !PteSrc.n.u1Present
1805	# if PGM_WITH_NX(PGM_GST_TYPE)
1806	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
1807	# endif
1808	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1809	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1810	)
1811	{
1812	# ifdef IN_GC
1813	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1814	# endif
1815	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1816	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1817
1818	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1819	* See the 2nd case above as well.
1820	*/
1821	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1822	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1823
1824	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1825	return VINF_EM_RAW_GUEST_TRAP;
1826	}
1827	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1828
1829	/*
1830	* Set the accessed bits in the page directory and the page table.
1831	*/
1832	pPdeSrc->n.u1Accessed = 1;
1833	pPteSrc->n.u1Accessed = 1;
1834
1835	/*
1836	* Only write protection page faults are relevant here.
1837	*/
1838	if (fWriteFault)
1839	{
1840	/* Write access, so mark guest entry as dirty. */
1841	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1842	if (!pPteSrc->n.u1Dirty)
1843	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1844	else
1845	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1846	# endif
1847	pPteSrc->n.u1Dirty = 1;
1848
1849	if (pPdeDst->n.u1Present)
1850	{
1851	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1852	* Our individual shadow handlers will provide more information and force a fatal exit.
1853	*/
1854	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1855	{
1856	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1857	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1858	return VINF_SUCCESS;
1859	}
1860
1861	/*
1862	* Map shadow page table.
1863	*/
1864	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1865	if (pShwPage)
1866	{
1867	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1868	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1869	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1870	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1871	{
1872	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1873	# ifdef VBOX_STRICT
1874	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1875	if (pPage)
1876	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1877	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1878	# endif
1879	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1880
1881	Assert(pPteSrc->n.u1Write);
1882
1883	pPteDst->n.u1Write = 1;
1884	pPteDst->n.u1Dirty = 1;
1885	pPteDst->n.u1Accessed = 1;
1886	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1887	PGM_INVL_PG(GCPtrPage);
1888
1889	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1890	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1891	}
1892	}
1893	else
1894	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1895	}
1896	}
1897	/** @todo Optimize accessed bit emulation? */
1898	# ifdef VBOX_STRICT
1899	/*
1900	* Sanity check.
1901	*/
1902	else if ( !pPteSrc->n.u1Dirty
1903	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1904	&& pPdeDst->n.u1Present)
1905	{
1906	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1907	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1908	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1909	if ( pPteDst->n.u1Present
1910	&& pPteDst->n.u1Write)
1911	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1912	}
1913	# endif /* VBOX_STRICT */
1914	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1915	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1916	}
1917	AssertRC(rc);
1918	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1919	return rc;
1920	}
1921
1922	# endif
1923
1924	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1925
1926
1927	/**
1928	* Sync a shadow page table.
1929	*
1930	* The shadow page table is not present. This includes the case where
1931	* there is a conflict with a mapping.
1932	*
1933	* @returns VBox status code.
1934	* @param pVM VM handle.
1935	* @param iPD Page directory index.
1936	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1937	* Assume this is a temporary mapping.
1938	* @param GCPtrPage GC Pointer of the page that caused the fault
1939	*/
1940	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1941	{
1942	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1943	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1944	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1945
1946	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1947	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1948
1949	/*
1950	* Validate input a little bit.
1951	*/
1952	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
1953	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1954	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1955	# else
1956	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1957	# endif
1958	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1959	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1960	SHWPDE PdeDst = *pPdeDst;
1961
1962	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1963	/*
1964	* Check for conflicts.
1965	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1966	* HC: Simply resolve the conflict.
1967	*/
1968	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1969	{
1970	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1971	# ifndef IN_RING3
1972	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1973	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1974	return VERR_ADDRESS_CONFLICT;
1975	# else
1976	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1977	Assert(pMapping);
1978	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPDSrc);
1979	if (VBOX_FAILURE(rc))
1980	{
1981	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1982	return rc;
1983	}
1984	PdeDst = *pPdeDst;
1985	# endif
1986	}
1987	# else /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1988	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
1989	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1990	# endif /* PGM_GST_TYPE == PGM_TYPE_32BIT */
1991	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1992
1993	/*
1994	* Sync page directory entry.
1995	*/
1996	int rc = VINF_SUCCESS;
1997	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
1998	if (PdeSrc.n.u1Present)
1999	{
2000	/*
2001	* Allocate & map the page table.
2002	*/
2003	PSHWPT pPTDst;
2004	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2005	PPGMPOOLPAGE pShwPage;
2006	RTGCPHYS GCPhys;
2007	if (fPageTable)
2008	{
2009	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2010	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2011	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2012	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2013	# endif
2014	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2015	}
2016	else
2017	{
2018	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2019	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2020	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2021	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2022	# endif
2023	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2024	}
2025	if (rc == VINF_SUCCESS)
2026	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2027	else if (rc == VINF_PGM_CACHED_PAGE)
2028	{
2029	/*
2030	* The PT was cached, just hook it up.
2031	*/
2032	if (fPageTable)
2033	PdeDst.u = pShwPage->Core.Key
2034	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2035	else
2036	{
2037	PdeDst.u = pShwPage->Core.Key
2038	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2039	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
2040	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2041	{
2042	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2043	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2044	PdeDst.b.u1Write = 0;
2045	}
2046	# endif
2047	}
2048	*pPdeDst = PdeDst;
2049	return VINF_SUCCESS;
2050	}
2051	else if (rc == VERR_PGM_POOL_FLUSHED)
2052	return VINF_PGM_SYNC_CR3;
2053	else
2054	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2055	PdeDst.u &= X86_PDE_AVL_MASK;
2056	PdeDst.u \|= pShwPage->Core.Key;
2057
2058	# ifdef PGM_SYNC_DIRTY_BIT
2059	/*
2060	* Page directory has been accessed (this is a fault situation, remember).
2061	*/
2062	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2063	# endif
2064	if (fPageTable)
2065	{
2066	/*
2067	* Page table - 4KB.
2068	*
2069	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2070	*/
2071	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2072	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2073	PGSTPT pPTSrc;
2074	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2075	if (VBOX_SUCCESS(rc))
2076	{
2077	/*
2078	* Start by syncing the page directory entry so CSAM's TLB trick works.
2079	*/
2080	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2081	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2082	*pPdeDst = PdeDst;
2083
2084	/*
2085	* Directory/page user or supervisor privilege: (same goes for read/write)
2086	*
2087	* Directory Page Combined
2088	* U/S U/S U/S
2089	* 0 0 0
2090	* 0 1 0
2091	* 1 0 0
2092	* 1 1 1
2093	*
2094	* Simple AND operation. Table listed for completeness.
2095	*
2096	*/
2097	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2098	# ifdef PGM_SYNC_N_PAGES
2099	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2100	unsigned iPTDst = iPTBase;
2101	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2102	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2103	iPTDst = 0;
2104	else
2105	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2106	# else /* !PGM_SYNC_N_PAGES */
2107	unsigned iPTDst = 0;
2108	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2109	# endif /* !PGM_SYNC_N_PAGES */
2110	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2111	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2112	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2113	# else
2114	const unsigned offPTSrc = 0;
2115	# endif
2116	for (; iPTDst < iPTDstEnd; iPTDst++)
2117	{
2118	const unsigned iPTSrc = iPTDst + offPTSrc;
2119	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2120
2121	if (PteSrc.n.u1Present) /* we've already cleared it above */
2122	{
2123	# ifndef IN_RING0
2124	/*
2125	* Assuming kernel code will be marked as supervisor - and not as user level
2126	* and executed using a conforming code selector - And marked as readonly.
2127	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2128	*/
2129	PPGMPAGE pPage;
2130	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2131	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2132	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2133	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2134	)
2135	# endif
2136	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2137	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2138	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2139	PteSrc.n.u1Present,
2140	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2141	PteSrc.n.u1User & PdeSrc.n.u1User,
2142	(uint64_t)PteSrc.u,
2143	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2144	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2145	}
2146	} /* for PTEs */
2147	}
2148	}
2149	else
2150	{
2151	/*
2152	* Big page - 2/4MB.
2153	*
2154	* We'll walk the ram range list in parallel and optimize lookups.
2155	* We will only sync on shadow page table at a time.
2156	*/
2157	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2158
2159	/**
2160	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2161	*/
2162
2163	/*
2164	* Start by syncing the page directory entry.
2165	*/
2166	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2167	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2168
2169	# ifdef PGM_SYNC_DIRTY_BIT
2170	/*
2171	* If the page is not flagged as dirty and is writable, then make it read-only
2172	* at PD level, so we can set the dirty bit when the page is modified.
2173	*
2174	* ASSUMES that page access handlers are implemented on page table entry level.
2175	* Thus we will first catch the dirty access and set PDE.D and restart. If
2176	* there is an access handler, we'll trap again and let it work on the problem.
2177	*/
2178	/** @todo move the above stuff to a section in the PGM documentation. */
2179	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2180	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2181	{
2182	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2183	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2184	PdeDst.b.u1Write = 0;
2185	}
2186	# endif /* PGM_SYNC_DIRTY_BIT */
2187	*pPdeDst = PdeDst;
2188
2189	/*
2190	* Fill the shadow page table.
2191	*/
2192	/* Get address and flags from the source PDE. */
2193	SHWPTE PteDstBase;
2194	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2195
2196	/* Loop thru the entries in the shadow PT. */
2197	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2198	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2199	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2200	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2201	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2202	unsigned iPTDst = 0;
2203	while (iPTDst < ELEMENTS(pPTDst->a))
2204	{
2205	/* Advance ram range list. */
2206	while (pRam && GCPhys > pRam->GCPhysLast)
2207	pRam = CTXALLSUFF(pRam->pNext);
2208	if (pRam && GCPhys >= pRam->GCPhys)
2209	{
2210	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2211	do
2212	{
2213	/* Make shadow PTE. */
2214	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2215	SHWPTE PteDst;
2216
2217	/* Make sure the RAM has already been allocated. */
2218	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2219	{
2220	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2221	{
2222	# ifdef IN_RING3
2223	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2224	# else
2225	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2226	# endif
2227	if (rc != VINF_SUCCESS)
2228	return rc;
2229	}
2230	}
2231
2232	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2233	{
2234	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2235	{
2236	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2237	PteDst.n.u1Write = 0;
2238	}
2239	else
2240	PteDst.u = 0;
2241	}
2242	# ifndef IN_RING0
2243	/*
2244	* Assuming kernel code will be marked as supervisor and not as user level and executed
2245	* using a conforming code selector. Don't check for readonly, as that implies the whole
2246	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2247	*/
2248	else if ( !PdeSrc.n.u1User
2249	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2250	PteDst.u = 0;
2251	# endif
2252	else
2253	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2254	# ifdef PGMPOOL_WITH_USER_TRACKING
2255	if (PteDst.n.u1Present)
2256	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2257	# endif
2258	/* commit it */
2259	pPTDst->a[iPTDst] = PteDst;
2260	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2261	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2262	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2263
2264	/* advance */
2265	GCPhys += PAGE_SIZE;
2266	iHCPage++;
2267	iPTDst++;
2268	} while ( iPTDst < ELEMENTS(pPTDst->a)
2269	&& GCPhys <= pRam->GCPhysLast);
2270	}
2271	else if (pRam)
2272	{
2273	Log(("Invalid pages at %VGp\n", GCPhys));
2274	do
2275	{
2276	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2277	GCPhys += PAGE_SIZE;
2278	iPTDst++;
2279	} while ( iPTDst < ELEMENTS(pPTDst->a)
2280	&& GCPhys < pRam->GCPhys);
2281	}
2282	else
2283	{
2284	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2285	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2286	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2287	}
2288	} /* while more PTEs */
2289	} /* 4KB / 4MB */
2290	}
2291	else
2292	AssertRelease(!PdeDst.n.u1Present);
2293
2294	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2295	# ifdef IN_GC
2296	if (VBOX_FAILURE(rc))
2297	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2298	# endif
2299	return rc;
2300
2301	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2302
2303	int rc = VINF_SUCCESS;
2304
2305	/*
2306	* Validate input a little bit.
2307	*/
2308	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2309	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2310	# else
2311	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2312	# endif
2313	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2314	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2315	SHWPDE PdeDst = *pPdeDst;
2316
2317	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2318	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2319
2320	GSTPDE PdeSrc;
2321	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2322	PdeSrc.n.u1Present = 1;
2323	PdeSrc.n.u1Write = 1;
2324	PdeSrc.n.u1Accessed = 1;
2325	PdeSrc.n.u1User = 1;
2326
2327	/*
2328	* Allocate & map the page table.
2329	*/
2330	PSHWPT pPTDst;
2331	PPGMPOOLPAGE pShwPage;
2332	RTGCPHYS GCPhys;
2333
2334	/* Virtual address = physical address */
2335	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2336	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2337
2338	if ( rc == VINF_SUCCESS
2339	\|\| rc == VINF_PGM_CACHED_PAGE)
2340	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2341	else
2342	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2343
2344	PdeDst.u &= X86_PDE_AVL_MASK;
2345	PdeDst.u \|= pShwPage->Core.Key;
2346	PdeDst.n.u1Present = 1;
2347	*pPdeDst = PdeDst;
2348
2349	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2350	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2351	return rc;
2352
2353	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2354	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2355	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2356	return VERR_INTERNAL_ERROR;
2357	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2358	}
2359
2360
2361
2362	/**
2363	* Prefetch a page/set of pages.
2364	*
2365	* Typically used to sync commonly used pages before entering raw mode
2366	* after a CR3 reload.
2367	*
2368	* @returns VBox status code.
2369	* @param pVM VM handle.
2370	* @param GCPtrPage Page to invalidate.
2371	*/
2372	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2373	{
2374	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2375	/*
2376	* Check that all Guest levels thru the PDE are present, getting the
2377	* PD and PDE in the processes.
2378	*/
2379	int rc = VINF_SUCCESS;
2380	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2381	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2382	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2383	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2384	# else /* PAE */
2385	unsigned iPDSrc;
2386	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2387	if (!pPDSrc)
2388	return VINF_SUCCESS; /* not present */
2389	# endif
2390	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2391	# else
2392	PGSTPD pPDSrc = NULL;
2393	const unsigned iPDSrc = 0;
2394	GSTPDE PdeSrc;
2395
2396	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2397	PdeSrc.n.u1Present = 1;
2398	PdeSrc.n.u1Write = 1;
2399	PdeSrc.n.u1Accessed = 1;
2400	PdeSrc.n.u1User = 1;
2401	# endif
2402
2403	# ifdef PGM_SYNC_ACCESSED_BIT
2404	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2405	# else
2406	if (PdeSrc.n.u1Present)
2407	# endif
2408	{
2409	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2410	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2411	# else
2412	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2413	# endif
2414	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2415	{
2416	if (!PdeDst.n.u1Present)
2417	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2418	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2419	else
2420	{
2421	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2422	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2423	* makes no sense to prefetch more than one page.
2424	*/
2425	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2426	if (VBOX_SUCCESS(rc))
2427	rc = VINF_SUCCESS;
2428	}
2429	}
2430	}
2431	return rc;
2432
2433	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2434
2435	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2436	return VERR_INTERNAL_ERROR;
2437	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2438	}
2439
2440
2441
2442
2443	/**
2444	* Syncs a page during a PGMVerifyAccess() call.
2445	*
2446	* @returns VBox status code (informational included).
2447	* @param GCPtrPage The address of the page to sync.
2448	* @param fPage The effective guest page flags.
2449	* @param uErr The trap error code.
2450	*/
2451	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2452	{
2453	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2454
2455	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2456
2457	# ifndef IN_RING0
2458	if (!(fPage & X86_PTE_US))
2459	{
2460	/*
2461	* Mark this page as safe.
2462	*/
2463	/** @todo not correct for pages that contain both code and data!! */
2464	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2465	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2466	}
2467	# endif
2468	/*
2469	* Get guest PD and index.
2470	*/
2471
2472	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2473	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2474	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2475	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2476	# else /* PAE */
2477	unsigned iPDSrc;
2478	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2479
2480	if (pPDSrc)
2481	{
2482	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2483	return VINF_EM_RAW_GUEST_TRAP;
2484	}
2485	# endif
2486	# else
2487	PGSTPD pPDSrc = NULL;
2488	const unsigned iPDSrc = 0;
2489	# endif
2490	int rc = VINF_SUCCESS;
2491
2492	/*
2493	* First check if the shadow pd is present.
2494	*/
2495	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2496	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2497	# else
2498	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2499	# endif
2500	if (!pPdeDst->n.u1Present)
2501	{
2502	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2503	AssertRC(rc);
2504	if (rc != VINF_SUCCESS)
2505	return rc;
2506	}
2507
2508	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2509	/* Check for dirty bit fault */
2510	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2511	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2512	Log(("PGMVerifyAccess: success (dirty)\n"));
2513	else
2514	{
2515	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2516	#else
2517	{
2518	GSTPDE PdeSrc;
2519	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2520	PdeSrc.n.u1Present = 1;
2521	PdeSrc.n.u1Write = 1;
2522	PdeSrc.n.u1Accessed = 1;
2523	PdeSrc.n.u1User = 1;
2524
2525	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2526	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2527	if (uErr & X86_TRAP_PF_US)
2528	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2529	else /* supervisor */
2530	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2531
2532	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2533	if (VBOX_SUCCESS(rc))
2534	{
2535	/* Page was successfully synced */
2536	Log2(("PGMVerifyAccess: success (sync)\n"));
2537	rc = VINF_SUCCESS;
2538	}
2539	else
2540	{
2541	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2542	return VINF_EM_RAW_GUEST_TRAP;
2543	}
2544	}
2545	return rc;
2546
2547	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2548
2549	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2550	return VERR_INTERNAL_ERROR;
2551	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2552	}
2553
2554
2555	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2556	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2557	/**
2558	* Figures out which kind of shadow page this guest PDE warrants.
2559	*
2560	* @returns Shadow page kind.
2561	* @param pPdeSrc The guest PDE in question.
2562	* @param cr4 The current guest cr4 value.
2563	*/
2564	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2565	{
2566	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2567	return BTH_PGMPOOLKIND_PT_FOR_PT;
2568	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2569	//{
2570	// case 0:
2571	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2572	// case X86_PDE4M_RW:
2573	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2574	// case X86_PDE4M_US:
2575	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2576	// case X86_PDE4M_RW \| X86_PDE4M_US:
2577	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2578	# if 0
2579	// case X86_PDE4M_PAE_NX:
2580	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2581	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2582	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2583	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2584	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2585	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2586	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2587	# endif
2588	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2589	//}
2590	}
2591	# endif
2592	#endif
2593
2594	#undef MY_STAM_COUNTER_INC
2595	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2596
2597
2598	/**
2599	* Syncs the paging hierarchy starting at CR3.
2600	*
2601	* @returns VBox status code, no specials.
2602	* @param pVM The virtual machine.
2603	* @param cr0 Guest context CR0 register
2604	* @param cr3 Guest context CR3 register
2605	* @param cr4 Guest context CR4 register
2606	* @param fGlobal Including global page directories or not
2607	*/
2608	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2609	{
2610	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2611	fGlobal = true; /* Change this CR3 reload to be a global one. */
2612
2613	/*
2614	* Update page access handlers.
2615	* The virtual are always flushed, while the physical are only on demand.
2616	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2617	* have to look into that later because it will have a bad influence on the performance.
2618	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2619	* bird: Yes, but that won't work for aliases.
2620	*/
2621	/** @todo this MUST go away. See #1557. */
2622	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2623	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2624	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2625
2626	#ifdef PGMPOOL_WITH_MONITORING
2627	/*
2628	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2629	* Occationally we will have to clear all the shadow page tables because we wanted
2630	* to monitor a page which was mapped by too many shadowed page tables. This operation
2631	* sometimes refered to as a 'lightweight flush'.
2632	*/
2633	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2634	pgmPoolMonitorModifiedClearAll(pVM);
2635	else
2636	{
2637	# ifdef IN_RING3
2638	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2639	pgmPoolClearAll(pVM);
2640	# else
2641	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2642	return VINF_PGM_SYNC_CR3;
2643	# endif
2644	}
2645	#endif
2646
2647	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2648	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2649
2650	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2651	/*
2652	* Get page directory addresses.
2653	*/
2654	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2655	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2656	# else
2657	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2658	# endif
2659
2660	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2661	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2662	Assert(pPDSrc);
2663	# ifndef IN_GC
2664	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2665	# endif
2666	# endif
2667
2668	/*
2669	* Iterate the page directory.
2670	*/
2671	PPGMMAPPING pMapping;
2672	unsigned iPdNoMapping;
2673	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2674	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2675
2676	/* Only check mappings if they are supposed to be put into the shadow page table. */
2677	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2678	{
2679	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2680	iPdNoMapping = (pMapping) ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U; /** PAE todo */
2681	}
2682	else
2683	{
2684	pMapping = 0;
2685	iPdNoMapping = ~0U;
2686	}
2687	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2688	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2689	{
2690	unsigned iPDSrc;
2691	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2692	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2693	# else
2694	AssertFailed(); /* @todo */
2695	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2696	# endif
2697	PX86PDEPAE pPDEDst = &pPDPAE->a[iPDPTE * X86_PG_PAE_ENTRIES];
2698	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2699
2700	if (pPDSrc == NULL)
2701	{
2702	/* PDPT not present */
2703	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
2704	{
2705	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2706	{
2707	if (pPDEDst[iPD].n.u1Present)
2708	{
2709	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPDPTE * X86_PG_PAE_ENTRIES + iPD);
2710	pPDEDst[iPD].u = 0;
2711	}
2712	}
2713	}
2714	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 0;
2715	continue;
2716	}
2717	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2718	{
2719	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2720	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2721	{
2722	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2723	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2724	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2725	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2726	# endif
2727	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2728	if ( PdeSrc.n.u1Present
2729	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2730	{
2731	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2732	/*
2733	* Check for conflicts with GC mappings.
2734	*/
2735	if (iPD == iPdNoMapping)
2736	{
2737	if (pVM->pgm.s.fMappingsFixed)
2738	{
2739	/* It's fixed, just skip the mapping. */
2740	const unsigned cPTs = pMapping->cPTs;
2741	iPD += cPTs - 1;
2742	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2743	pMapping = pMapping->CTXALLSUFF(pNext);
2744	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2745	continue;
2746	}
2747	# ifdef IN_RING3
2748	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2749	if (VBOX_FAILURE(rc))
2750	return rc;
2751
2752	/*
2753	* Update iPdNoMapping and pMapping.
2754	*/
2755	pMapping = pVM->pgm.s.pMappingsR3;
2756	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2757	pMapping = pMapping->pNextR3;
2758	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2759	# else
2760	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2761	return VINF_PGM_SYNC_CR3;
2762	# endif
2763	}
2764	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2765	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2766	Assert(iPD != iPdNoMapping);
2767	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2768	/*
2769	* Sync page directory entry.
2770	*
2771	* The current approach is to allocated the page table but to set
2772	* the entry to not-present and postpone the page table synching till
2773	* it's actually used.
2774	*/
2775	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2776	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2777	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2778	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2779	# else
2780	const unsigned iPdShw = iPD; NOREF(iPdShw);
2781	# endif
2782	{
2783	SHWPDE PdeDst = *pPDEDst;
2784	if (PdeDst.n.u1Present)
2785	{
2786	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2787	RTGCPHYS GCPhys;
2788	if ( !PdeSrc.b.u1Size
2789	\|\| !(cr4 & X86_CR4_PSE))
2790	{
2791	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2792	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2793	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2794	GCPhys \|= i * (PAGE_SIZE / 2);
2795	# endif
2796	}
2797	else
2798	{
2799	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2800	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2801	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2802	GCPhys \|= i * X86_PAGE_2M_SIZE;
2803	# endif
2804	}
2805
2806	if ( pShwPage->GCPhys == GCPhys
2807	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2808	&& ( pShwPage->fCached
2809	\|\| ( !fGlobal
2810	&& ( false
2811	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2812	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2813	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2814	\|\| ( !pShwPage->fSeenNonGlobal
2815	&& (cr4 & X86_CR4_PGE))
2816	# endif
2817	)
2818	)
2819	)
2820	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2821	\|\| ( (cr4 & X86_CR4_PSE)
2822	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2823	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2824	)
2825	)
2826	{
2827	# ifdef VBOX_WITH_STATISTICS
2828	if ( !fGlobal
2829	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2830	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2831	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2832	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2833	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2834	else
2835	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2836	# endif /* VBOX_WITH_STATISTICS */
2837	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2838	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2839	//# ifdef PGMPOOL_WITH_CACHE
2840	// pgmPoolCacheUsed(pPool, pShwPage);
2841	//# endif
2842	}
2843	else
2844	{
2845	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2846	pPDEDst->u = 0;
2847	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2848	}
2849	}
2850	else
2851	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2852	pPDEDst++;
2853	}
2854	}
2855	else if (iPD != iPdNoMapping)
2856	{
2857	/*
2858	* Check if there is any page directory to mark not present here.
2859	*/
2860	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2861	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2862	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2863	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2864	# else
2865	const unsigned iPdShw = iPD; NOREF(iPdShw);
2866	# endif
2867	{
2868	if (pPDEDst->n.u1Present)
2869	{
2870	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2871	pPDEDst->u = 0;
2872	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2873	}
2874	pPDEDst++;
2875	}
2876	}
2877	else
2878	{
2879	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2880	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2881	const unsigned cPTs = pMapping->cPTs;
2882	if (pVM->pgm.s.fMappingsFixed)
2883	{
2884	/* It's fixed, just skip the mapping. */
2885	pMapping = pMapping->CTXALLSUFF(pNext);
2886	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2887	}
2888	else
2889	{
2890	/*
2891	* Check for conflicts for subsequent pagetables
2892	* and advance to the next mapping.
2893	*/
2894	iPdNoMapping = ~0U;
2895	unsigned iPT = cPTs;
2896	while (iPT-- > 1)
2897	{
2898	if ( pPDSrc->a[iPD + iPT].n.u1Present
2899	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2900	{
2901	# ifdef IN_RING3
2902	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD);
2903	if (VBOX_FAILURE(rc))
2904	return rc;
2905
2906	/*
2907	* Update iPdNoMapping and pMapping.
2908	*/
2909	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2910	while (pMapping && pMapping->GCPtr < (iPD << X86_PD_SHIFT))
2911	pMapping = pMapping->CTXALLSUFF(pNext);
2912	iPdNoMapping = pMapping ? pMapping->GCPtr >> X86_PD_SHIFT : ~0U;
2913	break;
2914	# else
2915	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2916	return VINF_PGM_SYNC_CR3;
2917	# endif
2918	}
2919	}
2920	if (iPdNoMapping == ~0U && pMapping)
2921	{
2922	pMapping = pMapping->CTXALLSUFF(pNext);
2923	if (pMapping)
2924	iPdNoMapping = pMapping->GCPtr >> X86_PD_SHIFT;
2925	}
2926	}
2927
2928	/* advance. */
2929	iPD += cPTs - 1;
2930	pPDEDst += cPTs + (PGM_SHW_TYPE != PGM_TYPE_32BIT) * cPTs;
2931	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2932	/* PAE and AMD64 modes are hardware accelerated only, so there are no mappings. */
2933	AssertFailed();
2934	# endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2935	}
2936
2937	} /* for iPD */
2938	} /* for each PDPTE (PAE) */
2939
2940	return VINF_SUCCESS;
2941
2942	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2943	//# error not implemented
2944	return VERR_INTERNAL_ERROR;
2945	#else /* guest real and protected mode */
2946	return VINF_SUCCESS;
2947	#endif
2948	}
2949
2950
2951
2952
2953	#ifdef VBOX_STRICT
2954	#ifdef IN_GC
2955	# undef AssertMsgFailed
2956	# define AssertMsgFailed Log
2957	#endif
2958	#ifdef IN_RING3
2959	# include <VBox/dbgf.h>
2960
2961	/**
2962	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2963	*
2964	* @returns VBox status code (VINF_SUCCESS).
2965	* @param pVM The VM handle.
2966	* @param cr3 The root of the hierarchy.
2967	* @param crr The cr4, only PAE and PSE is currently used.
2968	* @param fLongMode Set if long mode, false if not long mode.
2969	* @param cMaxDepth Number of levels to dump.
2970	* @param pHlp Pointer to the output functions.
2971	*/
2972	__BEGIN_DECLS
2973	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
2974	__END_DECLS
2975
2976	#endif
2977
2978	/**
2979	* Checks that the shadow page table is in sync with the guest one.
2980	*
2981	* @returns The number of errors.
2982	* @param pVM The virtual machine.
2983	* @param cr3 Guest context CR3 register
2984	* @param cr4 Guest context CR4 register
2985	* @param GCPtr Where to start. Defaults to 0.
2986	* @param cb How much to check. Defaults to everything.
2987	*/
2988	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
2989	{
2990	unsigned cErrors = 0;
2991
2992	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
2993	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
2994
2995	PPGM pPGM = &pVM->pgm.s;
2996	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
2997	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
2998	# ifndef IN_RING0
2999	RTHCPHYS HCPhys; /* general usage. */
3000	# endif
3001	int rc;
3002
3003	/*
3004	* Check that the Guest CR3 and all its mappings are correct.
3005	*/
3006	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3007	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3008	false);
3009	# ifndef IN_RING0
3010	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3011	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
3012	# else
3013	rc = PGMShwGetPage(pVM, pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3014	# endif
3015	AssertRCReturn(rc, 1);
3016	HCPhys = NIL_RTHCPHYS;
3017	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3018	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3019	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3020	RTGCPHYS GCPhys;
3021	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3022	AssertRCReturn(rc, 1);
3023	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3024	# endif
3025	#endif /* !IN_RING0 */
3026
3027	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3028	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3029	# endif
3030
3031	/*
3032	* Get and check the Shadow CR3.
3033	*/
3034	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3035	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3036	unsigned cPDEs = ELEMENTS(pPDDst->a);
3037	# else
3038	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
3039	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
3040	# endif
3041	if (cb != ~(RTGCUINTPTR)0)
3042	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3043
3044	/** @todo call the other two PGMAssert() functions. /
3045
3046	# if PGM_GST_TYPE == PGM_TYPE_PAE
3047	/*
3048	* Check the 4 PDPTs too.
3049	*/
3050	for (unsigned i = 0; i < 4; i++)
3051	{
3052	RTHCPTR HCPtr;
3053	RTHCPHYS HCPhys;
3054	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
3055	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
3056	if (VBOX_SUCCESS(rc2))
3057	{
3058	AssertMsg( pVM->pgm.s.apGstPaePDsHC[i] == (R3R0PTRTYPE(PX86PDPAE))HCPtr
3059	&& pVM->pgm.s.aGCPhysGstPaePDs[i] == GCPhys,
3060	("idx %d apGstPaePDsHC %VHv vs %VHv aGCPhysGstPaePDs %VGp vs %VGp\n",
3061	i, pVM->pgm.s.apGstPaePDsHC[i], HCPtr, pVM->pgm.s.aGCPhysGstPaePDs[i], GCPhys));
3062	}
3063	}
3064	# endif
3065
3066	/*
3067	* Iterate the shadow page directory.
3068	*/
3069	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3070	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
3071	cPDEs += iPDDst;
3072	for (;
3073	iPDDst < cPDEs;
3074	iPDDst++, GCPtr += _4G / cPDEs)
3075	{
3076	# if PGM_GST_TYPE == PGM_TYPE_PAE
3077	uint32_t iPDSrc;
3078	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pPGM, (RTGCUINTPTR)GCPtr, &iPDSrc);
3079	if (!pPDSrc)
3080	{
3081	AssertMsg(!pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].n.u1Present, ("Guest PDTPR not present, shadow PDPTR %VX64\n", pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].u));
3082	continue;
3083	}
3084	#endif
3085
3086	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3087	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3088	{
3089	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3090	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3091	{
3092	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3093	cErrors++;
3094	continue;
3095	}
3096	}
3097	else if ( (PdeDst.u & X86_PDE_P)
3098	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3099	)
3100	{
3101	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3102	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3103	if (!pPoolPage)
3104	{
3105	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3106	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3107	cErrors++;
3108	continue;
3109	}
3110	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3111
3112	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3113	{
3114	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3115	GCPtr, (uint64_t)PdeDst.u));
3116	cErrors++;
3117	}
3118
3119	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3120	{
3121	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3122	GCPtr, (uint64_t)PdeDst.u));
3123	cErrors++;
3124	}
3125
3126	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3127	if (!PdeSrc.n.u1Present)
3128	{
3129	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3130	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3131	cErrors++;
3132	continue;
3133	}
3134
3135	if ( !PdeSrc.b.u1Size
3136	\|\| !(cr4 & X86_CR4_PSE))
3137	{
3138	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3139	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3140	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3141	# endif
3142	}
3143	else
3144	{
3145	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3146	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3147	{
3148	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3149	GCPtr, (uint64_t)PdeSrc.u));
3150	cErrors++;
3151	continue;
3152	}
3153	# endif
3154	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3155	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3156	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3157	# endif
3158	}
3159
3160	if ( pPoolPage->enmKind
3161	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3162	{
3163	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3164	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3165	cErrors++;
3166	}
3167
3168	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3169	if (!pPhysPage)
3170	{
3171	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3172	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3173	cErrors++;
3174	continue;
3175	}
3176
3177	if (GCPhysGst != pPoolPage->GCPhys)
3178	{
3179	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3180	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3181	cErrors++;
3182	continue;
3183	}
3184
3185	if ( !PdeSrc.b.u1Size
3186	\|\| !(cr4 & X86_CR4_PSE))
3187	{
3188	/*
3189	* Page Table.
3190	*/
3191	const GSTPT *pPTSrc;
3192	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3193	if (VBOX_FAILURE(rc))
3194	{
3195	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3196	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3197	cErrors++;
3198	continue;
3199	}
3200	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3201	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3202	{
3203	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3204	// (This problem will go away when/if we shadow multiple CR3s.)
3205	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3206	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3207	cErrors++;
3208	continue;
3209	}
3210	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3211	{
3212	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3213	GCPtr, (uint64_t)PdeDst.u));
3214	cErrors++;
3215	continue;
3216	}
3217
3218	/* iterate the page table. */
3219	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3220	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3221	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3222	# else
3223	const unsigned offPTSrc = 0;
3224	# endif
3225	for (unsigned iPT = 0, off = 0;
3226	iPT < ELEMENTS(pPTDst->a);
3227	iPT++, off += PAGE_SIZE)
3228	{
3229	const SHWPTE PteDst = pPTDst->a[iPT];
3230
3231	/* skip not-present entries. */
3232	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3233	continue;
3234	Assert(PteDst.n.u1Present);
3235
3236	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3237	if (!PteSrc.n.u1Present)
3238	{
3239	#ifdef IN_RING3
3240	PGMAssertHandlerAndFlagsInSync(pVM);
3241	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3242	#endif
3243	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3244	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3245	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3246	cErrors++;
3247	continue;
3248	}
3249
3250	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3251	# if 1 /** @todo sync accessed bit properly... */
3252	fIgnoreFlags \|= X86_PTE_A;
3253	# endif
3254
3255	/* match the physical addresses */
3256	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3257	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3258
3259	# ifdef IN_RING3
3260	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3261	if (VBOX_FAILURE(rc))
3262	{
3263	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3264	{
3265	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3266	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3267	cErrors++;
3268	continue;
3269	}
3270	}
3271	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3272	{
3273	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3274	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3275	cErrors++;
3276	continue;
3277	}
3278	# endif
3279
3280	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3281	if (!pPhysPage)
3282	{
3283	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3284	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3285	{
3286	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3287	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3288	cErrors++;
3289	continue;
3290	}
3291	# endif
3292	if (PteDst.n.u1Write)
3293	{
3294	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3295	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3296	cErrors++;
3297	}
3298	fIgnoreFlags \|= X86_PTE_RW;
3299	}
3300	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3301	{
3302	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3303	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3304	cErrors++;
3305	continue;
3306	}
3307
3308	/* flags */
3309	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3310	{
3311	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3312	{
3313	if (PteDst.n.u1Write)
3314	{
3315	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3316	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3317	cErrors++;
3318	continue;
3319	}
3320	fIgnoreFlags \|= X86_PTE_RW;
3321	}
3322	else
3323	{
3324	if (PteDst.n.u1Present)
3325	{
3326	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3327	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3328	cErrors++;
3329	continue;
3330	}
3331	fIgnoreFlags \|= X86_PTE_P;
3332	}
3333	}
3334	else
3335	{
3336	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3337	{
3338	if (PteDst.n.u1Write)
3339	{
3340	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3341	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3342	cErrors++;
3343	continue;
3344	}
3345	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3346	{
3347	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3348	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3349	cErrors++;
3350	continue;
3351	}
3352	if (PteDst.n.u1Dirty)
3353	{
3354	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3355	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3356	cErrors++;
3357	}
3358	# if 0 /** @todo sync access bit properly... */
3359	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3360	{
3361	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3362	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3363	cErrors++;
3364	}
3365	fIgnoreFlags \|= X86_PTE_RW;
3366	# else
3367	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3368	# endif
3369	}
3370	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3371	{
3372	/* access bit emulation (not implemented). */
3373	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3374	{
3375	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3376	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3377	cErrors++;
3378	continue;
3379	}
3380	if (!PteDst.n.u1Accessed)
3381	{
3382	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3383	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3384	cErrors++;
3385	}
3386	fIgnoreFlags \|= X86_PTE_P;
3387	}
3388	# ifdef DEBUG_sandervl
3389	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3390	# endif
3391	}
3392
3393	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3394	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3395	)
3396	{
3397	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3398	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3399	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3400	cErrors++;
3401	continue;
3402	}
3403	} /* foreach PTE */
3404	}
3405	else
3406	{
3407	/*
3408	* Big Page.
3409	*/
3410	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3411	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3412	{
3413	if (PdeDst.n.u1Write)
3414	{
3415	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3416	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3417	cErrors++;
3418	continue;
3419	}
3420	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3421	{
3422	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3423	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3424	cErrors++;
3425	continue;
3426	}
3427	# if 0 /** @todo sync access bit properly... */
3428	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3429	{
3430	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3431	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3432	cErrors++;
3433	}
3434	fIgnoreFlags \|= X86_PTE_RW;
3435	# else
3436	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3437	# endif
3438	}
3439	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3440	{
3441	/* access bit emulation (not implemented). */
3442	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3443	{
3444	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3445	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3446	cErrors++;
3447	continue;
3448	}
3449	if (!PdeDst.n.u1Accessed)
3450	{
3451	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3452	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3453	cErrors++;
3454	}
3455	fIgnoreFlags \|= X86_PTE_P;
3456	}
3457
3458	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3459	{
3460	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3461	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3462	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3463	cErrors++;
3464	}
3465
3466	/* iterate the page table. */
3467	for (unsigned iPT = 0, off = 0;
3468	iPT < ELEMENTS(pPTDst->a);
3469	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3470	{
3471	const SHWPTE PteDst = pPTDst->a[iPT];
3472
3473	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3474	{
3475	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3476	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3477	cErrors++;
3478	}
3479
3480	/* skip not-present entries. */
3481	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3482	continue;
3483
3484	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3485
3486	/* match the physical addresses */
3487	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3488
3489	# ifdef IN_RING3
3490	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3491	if (VBOX_FAILURE(rc))
3492	{
3493	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3494	{
3495	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3496	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3497	cErrors++;
3498	}
3499	}
3500	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3501	{
3502	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3503	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3504	cErrors++;
3505	continue;
3506	}
3507	# endif
3508
3509	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3510	if (!pPhysPage)
3511	{
3512	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3513	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3514	{
3515	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3516	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3517	cErrors++;
3518	continue;
3519	}
3520	# endif
3521	if (PteDst.n.u1Write)
3522	{
3523	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3524	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3525	cErrors++;
3526	}
3527	fIgnoreFlags \|= X86_PTE_RW;
3528	}
3529	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3530	{
3531	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3532	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3533	cErrors++;
3534	continue;
3535	}
3536
3537	/* flags */
3538	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3539	{
3540	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3541	{
3542	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3543	{
3544	if (PteDst.n.u1Write)
3545	{
3546	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3547	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3548	cErrors++;
3549	continue;
3550	}
3551	fIgnoreFlags \|= X86_PTE_RW;
3552	}
3553	}
3554	else
3555	{
3556	if (PteDst.n.u1Present)
3557	{
3558	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3559	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3560	cErrors++;
3561	continue;
3562	}
3563	fIgnoreFlags \|= X86_PTE_P;
3564	}
3565	}
3566
3567	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3568	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3569	)
3570	{
3571	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3572	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3573	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3574	cErrors++;
3575	continue;
3576	}
3577	} /* foreach PTE */
3578	}
3579	}
3580	/* not present */
3581
3582	} /* forearch PDE */
3583
3584	# ifdef DEBUG
3585	if (cErrors)
3586	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3587	# endif
3588
3589	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3590	//# error not implemented
3591
3592
3593	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3594	//# error not implemented
3595
3596	/#else: guest real and protected mode /
3597	#endif
3598	return cErrors;
3599	}
3600	#endif /* VBOX_STRICT */
3601

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 7904

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