PGMAllBth.h@ 8030

Last change on this file since 8030 was 8030, checked in by vboxsync, 17 years ago
Another fix for PAE mappings
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File size: 157.3 KB

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1	/* $Id: PGMAllBth.h 8030 2008-04-16 11:43:17Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 innotek GmbH
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*/
19
20	/*******************************************************************************
21	* Internal Functions *
22	*******************************************************************************/
23	__BEGIN_DECLS
24	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
25	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
26	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
27	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
28	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
29	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
30	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
31	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
32	#ifdef VBOX_STRICT
33	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
34	#endif
35	#ifdef PGMPOOL_WITH_USER_TRACKING
36	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
37	#endif
38	__END_DECLS
39
40
41	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
42	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
43	#error "Invalid combination; PAE guest implies PAE shadow"
44	#endif
45
46	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
47	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
48	#error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
49	#endif
50
51	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
52	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
53	#error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
54	#endif
55
56	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
57	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
58	#error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
59	#endif
60
61	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
62	#define PGM_WITHOUT_MAPPINGS
63	#endif
64
65	/**
66	* #PF Handler for raw-mode guest execution.
67	*
68	* @returns VBox status code (appropriate for trap handling and GC return).
69	* @param pVM VM Handle.
70	* @param uErr The trap error code.
71	* @param pRegFrame Trap register frame.
72	* @param pvFault The fault address.
73	*/
74	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
75	{
76	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
77
78	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
79	/*
80	* Hide the instruction fetch trap indicator for now.
81	*/
82	/** @todo NXE will change this and we must fix NXE in the switcher too! */
83	if (uErr & X86_TRAP_PF_ID)
84	{
85	uErr &= ~X86_TRAP_PF_ID;
86	TRPMSetErrorCode(pVM, uErr);
87	}
88	# endif
89
90	/*
91	* Get PDs.
92	*/
93	int rc;
94	# if PGM_WITH_PAGING(PGM_GST_TYPE)
95	# if PGM_GST_TYPE == PGM_TYPE_32BIT
96	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
97	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
98	# else /* PAE */
99	unsigned iPDSrc;
100	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
101
102	/* Quick check for a valid guest trap. */
103	if (!pPDSrc)
104	{
105	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
106	TRPMSetErrorCode(pVM, uErr);
107	return VINF_EM_RAW_GUEST_TRAP;
108	}
109	# endif
110	# else
111	PGSTPD pPDSrc = NULL;
112	const unsigned iPDSrc = 0;
113	# endif
114
115	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
116	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
117	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
118	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
119	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries. */
120
121	# if PGM_GST_TYPE == PGM_TYPE_PAE
122	/* Did we mark the PDPT as not present in SyncCR3? */
123	unsigned iPDPTE = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
124	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
125	{
126	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 1;
127	}
128	# endif
129	# else
130	AssertFailed();
131	# endif
132
133	# if PGM_WITH_PAGING(PGM_GST_TYPE)
134	# ifdef PGM_SYNC_DIRTY_BIT
135	/*
136	* If we successfully correct the write protection fault due to dirty bit
137	* tracking, or this page fault is a genuine one, then return immediately.
138	*/
139	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
140	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
141	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
142	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
143	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
144	{
145	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
146	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
147	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
148	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
149	}
150	# endif
151
152	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
153	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
154
155	/*
156	* A common case is the not-present error caused by lazy page table syncing.
157	*
158	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
159	* so we can safely assume that the shadow PT is present when calling SyncPage later.
160	*
161	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
162	* of mapping conflict and defer to SyncCR3 in R3.
163	* (Again, we do NOT support access handlers for non-present guest pages.)
164	*
165	*/
166	# if PGM_WITH_PAGING(PGM_GST_TYPE)
167	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
168	# else
169	GSTPDE PdeSrc;
170	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
171	PdeSrc.n.u1Present = 1;
172	PdeSrc.n.u1Write = 1;
173	PdeSrc.n.u1Accessed = 1;
174	PdeSrc.n.u1User = 1;
175	# endif
176	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
177	&& !pPDDst->a[iPDDst].n.u1Present
178	&& PdeSrc.n.u1Present
179	)
180
181	{
182	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
183	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
184	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
185	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
186	if (VBOX_SUCCESS(rc))
187	{
188	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
189	return rc;
190	}
191	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
192	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
193	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
194	return VINF_PGM_SYNC_CR3;
195	}
196
197	# if PGM_WITH_PAGING(PGM_GST_TYPE)
198	/*
199	* Check if this address is within any of our mappings.
200	*
201	* This is very fast and it's gonna save us a bit of effort below and prevent
202	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
203	* (BTW, it's impossible to have physical access handlers in a mapping.)
204	*/
205	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
206	{
207	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
208	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
209	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
210	{
211	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
212	break;
213	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
214	{
215	/*
216	* The first thing we check is if we've got an undetected conflict.
217	*/
218	if (!pVM->pgm.s.fMappingsFixed)
219	{
220	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
221	while (iPT-- > 0)
222	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
223	{
224	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
225	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
226	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
227	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
228	return VINF_PGM_SYNC_CR3;
229	}
230	}
231
232	/*
233	* Check if the fault address is in a virtual page access handler range.
234	*/
235	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
236	if ( pCur
237	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
238	&& uErr & X86_TRAP_PF_RW)
239	{
240	# ifdef IN_GC
241	STAM_PROFILE_START(&pCur->Stat, h);
242	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
243	STAM_PROFILE_STOP(&pCur->Stat, h);
244	# else
245	AssertFailed();
246	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
247	# endif
248	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
249	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
250	return rc;
251	}
252
253	/*
254	* Pretend we're not here and let the guest handle the trap.
255	*/
256	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
257	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
258	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
259	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
260	return VINF_EM_RAW_GUEST_TRAP;
261	}
262	}
263	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
264	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
265	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
266
267	/*
268	* Check if this fault address is flagged for special treatment,
269	* which means we'll have to figure out the physical address and
270	* check flags associated with it.
271	*
272	* ASSUME that we can limit any special access handling to pages
273	* in page tables which the guest believes to be present.
274	*/
275	if (PdeSrc.n.u1Present)
276	{
277	RTGCPHYS GCPhys = NIL_RTGCPHYS;
278
279	# if PGM_WITH_PAGING(PGM_GST_TYPE)
280	uint32_t cr4 = CPUMGetGuestCR4(pVM);
281	if ( PdeSrc.b.u1Size
282	&& (cr4 & X86_CR4_PSE))
283	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
284	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
285	else
286	{
287	PGSTPT pPTSrc;
288	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
289	if (VBOX_SUCCESS(rc))
290	{
291	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
292	if (pPTSrc->a[iPTESrc].n.u1Present)
293	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
294	}
295	}
296	# else
297	/* No paging so the fault address is the physical address */
298	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
299	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
300
301	/*
302	* If we have a GC address we'll check if it has any flags set.
303	*/
304	if (GCPhys != NIL_RTGCPHYS)
305	{
306	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
307
308	PPGMPAGE pPage;
309	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
310	if (VBOX_SUCCESS(rc))
311	{
312	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
313	{
314	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
315	{
316	/*
317	* Physical page access handler.
318	*/
319	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
320	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
321	if (pCur)
322	{
323	# ifdef PGM_SYNC_N_PAGES
324	/*
325	* If the region is write protected and we got a page not present fault, then sync
326	* the pages. If the fault was caused by a read, then restart the instruction.
327	* In case of write access continue to the GC write handler.
328	*
329	* ASSUMES that there is only one handler per page or that they have similar write properties.
330	*/
331	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
332	&& !(uErr & X86_TRAP_PF_P))
333	{
334	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
335	if ( VBOX_FAILURE(rc)
336	\|\| !(uErr & X86_TRAP_PF_RW)
337	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
338	{
339	AssertRC(rc);
340	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
341	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
342	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
343	return rc;
344	}
345	}
346	# endif
347
348	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
349	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
350	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
351
352	#if defined(IN_GC) \|\| defined(IN_RING0)
353	if (CTXALLSUFF(pCur->pfnHandler))
354	{
355	STAM_PROFILE_START(&pCur->Stat, h);
356	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
357	STAM_PROFILE_STOP(&pCur->Stat, h);
358	}
359	else
360	#endif
361	rc = VINF_EM_RAW_EMULATE_INSTR;
362	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
363	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
364	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
365	return rc;
366	}
367	}
368	# if PGM_WITH_PAGING(PGM_GST_TYPE)
369	else
370	{
371	# ifdef PGM_SYNC_N_PAGES
372	/*
373	* If the region is write protected and we got a page not present fault, then sync
374	* the pages. If the fault was caused by a read, then restart the instruction.
375	* In case of write access continue to the GC write handler.
376	*/
377	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
378	&& !(uErr & X86_TRAP_PF_P))
379	{
380	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
381	if ( VBOX_FAILURE(rc)
382	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
383	\|\| !(uErr & X86_TRAP_PF_RW))
384	{
385	AssertRC(rc);
386	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
387	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
388	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
389	return rc;
390	}
391	}
392	# endif
393	/*
394	* Ok, it's an virtual page access handler.
395	*
396	* Since it's faster to search by address, we'll do that first
397	* and then retry by GCPhys if that fails.
398	*/
399	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
400	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
401	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
402	*/
403	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
404	if (pCur)
405	{
406	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
407	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
408	\|\| !(uErr & X86_TRAP_PF_P)
409	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
410	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
411
412	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
413	&& ( uErr & X86_TRAP_PF_RW
414	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
415	{
416	# ifdef IN_GC
417	STAM_PROFILE_START(&pCur->Stat, h);
418	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
419	STAM_PROFILE_STOP(&pCur->Stat, h);
420	# else
421	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
422	# endif
423	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
424	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
425	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
426	return rc;
427	}
428	/* Unhandled part of a monitored page */
429	}
430	else
431	{
432	/* Check by physical address. */
433	PPGMVIRTHANDLER pCur;
434	unsigned iPage;
435	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
436	&pCur, &iPage);
437	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
438	if ( pCur
439	&& ( uErr & X86_TRAP_PF_RW
440	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
441	{
442	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
443	# ifdef IN_GC
444	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
445	Assert(off < pCur->cb);
446	STAM_PROFILE_START(&pCur->Stat, h);
447	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
448	STAM_PROFILE_STOP(&pCur->Stat, h);
449	# else
450	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
451	# endif
452	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
453	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
454	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
455	return rc;
456	}
457	}
458	}
459	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
460
461	/*
462	* There is a handled area of the page, but this fault doesn't belong to it.
463	* We must emulate the instruction.
464	*
465	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
466	* we first check if this was a page-not-present fault for a page with only
467	* write access handlers. Restart the instruction if it wasn't a write access.
468	*/
469	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
470
471	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
472	&& !(uErr & X86_TRAP_PF_P))
473	{
474	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
475	if ( VBOX_FAILURE(rc)
476	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
477	\|\| !(uErr & X86_TRAP_PF_RW))
478	{
479	AssertRC(rc);
480	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
481	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
482	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
483	return rc;
484	}
485	}
486
487	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
488	* It's writing to an unhandled part of the LDT page several million times.
489	*/
490	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
491	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
492	rc, pPage->HCPhys,
493	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
494	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
495	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
496	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
497	return rc;
498	} /* if any kind of handler */
499
500	# if PGM_WITH_PAGING(PGM_GST_TYPE)
501	if (uErr & X86_TRAP_PF_P)
502	{
503	/*
504	* The page isn't marked, but it might still be monitored by a virtual page access handler.
505	* (ASSUMES no temporary disabling of virtual handlers.)
506	*/
507	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
508	* we should correct both the shadow page table and physical memory flags, and not only check for
509	* accesses within the handler region but for access to pages with virtual handlers. */
510	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
511	if (pCur)
512	{
513	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
514	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
515	\|\| !(uErr & X86_TRAP_PF_P)
516	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
517	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
518
519	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
520	&& ( uErr & X86_TRAP_PF_RW
521	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
522	{
523	# ifdef IN_GC
524	STAM_PROFILE_START(&pCur->Stat, h);
525	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
526	STAM_PROFILE_STOP(&pCur->Stat, h);
527	# else
528	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
529	# endif
530	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
531	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
532	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
533	return rc;
534	}
535	}
536	}
537	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
538	}
539	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
540
541	# ifdef PGM_OUT_OF_SYNC_IN_GC
542	/*
543	* We are here only if page is present in Guest page tables and trap is not handled
544	* by our handlers.
545	* Check it for page out-of-sync situation.
546	*/
547	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
548
549	if (!(uErr & X86_TRAP_PF_P))
550	{
551	/*
552	* Page is not present in our page tables.
553	* Try to sync it!
554	* BTW, fPageShw is invalid in this branch!
555	*/
556	if (uErr & X86_TRAP_PF_US)
557	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
558	else /* supervisor */
559	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
560
561	# if defined(LOG_ENABLED) && !defined(IN_RING0)
562	RTGCPHYS GCPhys;
563	uint64_t fPageGst;
564	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
565	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
566	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
567	# endif /* LOG_ENABLED */
568
569	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
570	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
571	{
572	uint64_t fPageGst;
573	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
574	if ( VBOX_SUCCESS(rc)
575	&& !(fPageGst & X86_PTE_US))
576	{
577	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
578	if ( pvFault == (RTGCPTR)pRegFrame->eip
579	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
580	# ifdef CSAM_DETECT_NEW_CODE_PAGES
581	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
582	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
583	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
584	)
585	{
586	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
587	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
588	if (rc != VINF_SUCCESS)
589	{
590	/*
591	* CSAM needs to perform a job in ring 3.
592	*
593	* Sync the page before going to the host context; otherwise we'll end up in a loop if
594	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
595	*/
596	LogFlow(("CSAM ring 3 job\n"));
597	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
598	AssertRC(rc2);
599
600	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
601	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
602	return rc;
603	}
604	}
605	# ifdef CSAM_DETECT_NEW_CODE_PAGES
606	else
607	if ( uErr == X86_TRAP_PF_RW
608	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
609	&& pRegFrame->ecx < 0x10000
610	)
611	{
612	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
613	* to detect loading of new code pages.
614	*/
615
616	/*
617	* Decode the instruction.
618	*/
619	RTGCPTR PC;
620	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
621	if (rc == VINF_SUCCESS)
622	{
623	DISCPUSTATE Cpu;
624	uint32_t cbOp;
625	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
626
627	/* For now we'll restrict this to rep movsw/d instructions */
628	if ( rc == VINF_SUCCESS
629	&& Cpu.pCurInstr->opcode == OP_MOVSWD
630	&& (Cpu.prefix & PREFIX_REP))
631	{
632	CSAMMarkPossibleCodePage(pVM, pvFault);
633	}
634	}
635	}
636	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
637
638	/*
639	* Mark this page as safe.
640	*/
641	/** @todo not correct for pages that contain both code and data!! */
642	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
643	CSAMMarkPage(pVM, pvFault, true);
644	}
645	}
646	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
647	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
648	if (VBOX_SUCCESS(rc))
649	{
650	/* The page was successfully synced, return to the guest. */
651	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
652	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
653	return VINF_SUCCESS;
654	}
655	}
656	else
657	{
658	/*
659	* A side effect of not flushing global PDEs are out of sync pages due
660	* to physical monitored regions, that are no longer valid.
661	* Assume for now it only applies to the read/write flag
662	*/
663	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
664	{
665	if (uErr & X86_TRAP_PF_US)
666	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
667	else /* supervisor */
668	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
669
670
671	/*
672	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
673	*/
674	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
675	if (VBOX_SUCCESS(rc))
676	{
677	/*
678	* Page was successfully synced, return to guest.
679	*/
680	# ifdef VBOX_STRICT
681	RTGCPHYS GCPhys;
682	uint64_t fPageGst;
683	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
684	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
685	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
686
687	uint64_t fPageShw;
688	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
689	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
690	# endif /* VBOX_STRICT */
691	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
692	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
693	return VINF_SUCCESS;
694	}
695
696	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
697	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
698	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
699	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
700	{
701	uint64_t fPageGst;
702	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
703	if ( VBOX_SUCCESS(rc)
704	&& !(fPageGst & X86_PTE_RW))
705	{
706	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
707	if (VBOX_SUCCESS(rc))
708	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
709	else
710	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
711	return rc;
712	}
713	else
714	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
715	}
716
717	}
718
719	# if PGM_WITH_PAGING(PGM_GST_TYPE)
720	# ifdef VBOX_STRICT
721	/*
722	* Check for VMM page flags vs. Guest page flags consistency.
723	* Currently only for debug purposes.
724	*/
725	if (VBOX_SUCCESS(rc))
726	{
727	/* Get guest page flags. */
728	uint64_t fPageGst;
729	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
730	if (VBOX_SUCCESS(rc))
731	{
732	uint64_t fPageShw;
733	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
734
735	/*
736	* Compare page flags.
737	* Note: we have AVL, A, D bits desynched.
738	*/
739	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
740	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
741	}
742	else
743	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
744	}
745	else
746	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
747	# endif /* VBOX_STRICT */
748	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
749	}
750	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
751	# endif /* PGM_OUT_OF_SYNC_IN_GC */
752	}
753	else
754	{
755	/*
756	* Page not present in Guest OS or invalid page table address.
757	* This is potential virtual page access handler food.
758	*
759	* For the present we'll say that our access handlers don't
760	* work for this case - we've already discarded the page table
761	* not present case which is identical to this.
762	*
763	* When we perchance find we need this, we will probably have AVL
764	* trees (offset based) to operate on and we can measure their speed
765	* agains mapping a page table and probably rearrange this handling
766	* a bit. (Like, searching virtual ranges before checking the
767	* physical address.)
768	*/
769	}
770	}
771
772
773	# if PGM_WITH_PAGING(PGM_GST_TYPE)
774	/*
775	* Conclusion, this is a guest trap.
776	*/
777	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
778	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
779	return VINF_EM_RAW_GUEST_TRAP;
780	# else
781	/* present, but not a monitored page; perhaps the guest is probing physical memory */
782	return VINF_EM_RAW_EMULATE_INSTR;
783	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
784
785
786	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
787
788	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
789	return VERR_INTERNAL_ERROR;
790	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
791	}
792
793
794	/**
795	* Emulation of the invlpg instruction.
796	*
797	*
798	* @returns VBox status code.
799	*
800	* @param pVM VM handle.
801	* @param GCPtrPage Page to invalidate.
802	*
803	* @remark ASSUMES that the guest is updating before invalidating. This order
804	* isn't required by the CPU, so this is speculative and could cause
805	* trouble.
806	*
807	* @todo Flush page or page directory only if necessary!
808	* @todo Add a #define for simply invalidating the page.
809	*/
810	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
811	{
812	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
813	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
814
815	LogFlow(("InvalidatePage %x\n", GCPtrPage));
816	/*
817	* Get the shadow PD entry and skip out if this PD isn't present.
818	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
819	*/
820	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
821	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
822	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
823	# else
824	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
825	# endif
826	const SHWPDE PdeDst = *pPdeDst;
827	if (!PdeDst.n.u1Present)
828	{
829	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
830	return VINF_SUCCESS;
831	}
832
833	/*
834	* Get the guest PD entry and calc big page.
835	*/
836	# if PGM_GST_TYPE == PGM_TYPE_32BIT
837	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
838	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
839	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
840	# else /* PAE */
841	unsigned iPDSrc;
842	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
843	GSTPDE PdeSrc;
844
845	if (pPDSrc)
846	PdeSrc = pPDSrc->a[iPDSrc];
847	else
848	PdeSrc.u = 0;
849	# endif
850
851	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
852	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
853
854	# ifdef IN_RING3
855	/*
856	* If a CR3 Sync is pending we may ignore the invalidate page operation
857	* depending on the kind of sync and if it's a global page or not.
858	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
859	*/
860	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
861	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
862	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
863	&& fIsBigPage
864	&& PdeSrc.b.u1Global
865	&& (cr4 & X86_CR4_PGE)
866	)
867	)
868	# else
869	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
870	# endif
871	{
872	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
873	return VINF_SUCCESS;
874	}
875	# endif /* IN_RING3 */
876
877
878	/*
879	* Deal with the Guest PDE.
880	*/
881	int rc = VINF_SUCCESS;
882	if (PdeSrc.n.u1Present)
883	{
884	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
885	{
886	/*
887	* Conflict - Let SyncPT deal with it to avoid duplicate code.
888	*/
889	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
890	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
891	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
892	}
893	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
894	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
895	{
896	/*
897	* Mark not present so we can resync the PDE when it's used.
898	*/
899	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
900	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
901	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
902	pPdeDst->u = 0;
903	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
904	PGM_INVL_GUEST_TLBS();
905	}
906	# ifdef PGM_SYNC_ACCESSED_BIT
907	else if (!PdeSrc.n.u1Accessed)
908	{
909	/*
910	* Mark not present so we can set the accessed bit.
911	*/
912	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
913	pPdeDst->u = 0;
914	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
915	PGM_INVL_GUEST_TLBS();
916	}
917	# endif
918	else if (!fIsBigPage)
919	{
920	/*
921	* 4KB - page.
922	*/
923	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
924	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
925	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
926	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
927	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
928	# endif
929	if (pShwPage->GCPhys == GCPhys)
930	{
931	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
932	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
933	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
934	if (pPT->a[iPTEDst].n.u1Present)
935	{
936	# ifdef PGMPOOL_WITH_USER_TRACKING
937	/* This is very unlikely with caching/monitoring enabled. */
938	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
939	# endif
940	pPT->a[iPTEDst].u = 0;
941	}
942	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
943	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
944	if (VBOX_SUCCESS(rc))
945	rc = VINF_SUCCESS;
946	# endif
947	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
948	PGM_INVL_PG(GCPtrPage);
949	}
950	else
951	{
952	/*
953	* The page table address changed.
954	*/
955	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
956	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
957	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
958	pPdeDst->u = 0;
959	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
960	PGM_INVL_GUEST_TLBS();
961	}
962	}
963	else
964	{
965	/*
966	* 4MB - page.
967	*/
968	/* Before freeing the page, check if anything really changed. */
969	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
970	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
971	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
972	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
973	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
974	# endif
975	if ( pShwPage->GCPhys == GCPhys
976	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
977	{
978	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
979	/** @todo PAT */
980	# ifdef PGM_SYNC_DIRTY_BIT
981	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
982	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
983	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
984	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
985	# else
986	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
987	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
988	# endif
989	{
990	LogFlow(("Skipping flush for big page containing %VGv (PD=%X)-> nothing has changed!\n", GCPtrPage, iPDSrc));
991	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
992	return VINF_SUCCESS;
993	}
994	}
995
996	/*
997	* Ok, the page table is present and it's been changed in the guest.
998	* If we're in host context, we'll just mark it as not present taking the lazy approach.
999	* We could do this for some flushes in GC too, but we need an algorithm for
1000	* deciding which 4MB pages containing code likely to be executed very soon.
1001	*/
1002	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1003	pPdeDst->u = 0;
1004	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1005	PGM_INVL_BIG_PG(GCPtrPage);
1006	}
1007	}
1008	else
1009	{
1010	/*
1011	* Page directory is not present, mark shadow PDE not present.
1012	*/
1013	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1014	{
1015	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1016	pPdeDst->u = 0;
1017	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1018	PGM_INVL_PG(GCPtrPage);
1019	}
1020	else
1021	{
1022	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1023	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1024	}
1025	}
1026
1027	return rc;
1028
1029	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1030	//# error not implemented
1031	return VERR_INTERNAL_ERROR;
1032
1033	#else /* guest real and protected mode */
1034	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1035	return VINF_SUCCESS;
1036	#endif
1037	}
1038
1039
1040	#ifdef PGMPOOL_WITH_USER_TRACKING
1041	/**
1042	* Update the tracking of shadowed pages.
1043	*
1044	* @param pVM The VM handle.
1045	* @param pShwPage The shadow page.
1046	* @param HCPhys The physical page we is being dereferenced.
1047	*/
1048	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1049	{
1050	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1051	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1052	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1053
1054	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1055	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1056	* 2. write protect all shadowed pages. I.e. implement caching.
1057	*/
1058	/*
1059	* Find the guest address.
1060	*/
1061	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1062	pRam;
1063	pRam = CTXALLSUFF(pRam->pNext))
1064	{
1065	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1066	while (iPage-- > 0)
1067	{
1068	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1069	{
1070	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1071	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1072	pShwPage->cPresent--;
1073	pPool->cPresent--;
1074	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1075	return;
1076	}
1077	}
1078	}
1079
1080	for (;;)
1081	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1082	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1083	pShwPage->cPresent--;
1084	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1085	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1086	}
1087
1088
1089	/**
1090	* Update the tracking of shadowed pages.
1091	*
1092	* @param pVM The VM handle.
1093	* @param pShwPage The shadow page.
1094	* @param u16 The top 16-bit of the pPage->HCPhys.
1095	* @param pPage Pointer to the guest page. this will be modified.
1096	* @param iPTDst The index into the shadow table.
1097	*/
1098	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1099	{
1100	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1101	/*
1102	* We're making certain assumptions about the placement of cRef and idx.
1103	*/
1104	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1105	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1106
1107	/*
1108	* Just deal with the simple first time here.
1109	*/
1110	if (!u16)
1111	{
1112	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1113	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1114	}
1115	else
1116	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1117
1118	/* write back, trying to be clever... */
1119	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1120	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1121	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1122	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1123
1124	/* update statistics. */
1125	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1126	pShwPage->cPresent++;
1127	if (pShwPage->iFirstPresent > iPTDst)
1128	pShwPage->iFirstPresent = iPTDst;
1129	}
1130	#endif /* PGMPOOL_WITH_USER_TRACKING */
1131
1132
1133	/**
1134	* Creates a 4K shadow page for a guest page.
1135	*
1136	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1137	* physical address. The PdeSrc argument only the flags are used. No page structured
1138	* will be mapped in this function.
1139	*
1140	* @param pVM VM handle.
1141	* @param pPteDst Destination page table entry.
1142	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1143	* Can safely assume that only the flags are being used.
1144	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1145	* @param pShwPage Pointer to the shadow page.
1146	* @param iPTDst The index into the shadow table.
1147	*
1148	* @remark Not used for 2/4MB pages!
1149	*/
1150	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1151	{
1152	if (PteSrc.n.u1Present)
1153	{
1154	/*
1155	* Find the ram range.
1156	*/
1157	PPGMPAGE pPage;
1158	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1159	if (VBOX_SUCCESS(rc))
1160	{
1161	/** @todo investiage PWT, PCD and PAT. */
1162	/*
1163	* Make page table entry.
1164	*/
1165	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1166	SHWPTE PteDst;
1167	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1168	{
1169	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1170	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1171	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1172	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1173	else
1174	{
1175	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1176	PteDst.u = 0;
1177	}
1178	/** @todo count these two kinds. */
1179	}
1180	else
1181	{
1182	#ifdef PGM_SYNC_DIRTY_BIT
1183	# ifdef PGM_SYNC_ACCESSED_BIT
1184	/*
1185	* If the page or page directory entry is not marked accessed,
1186	* we mark the page not present.
1187	*/
1188	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1189	{
1190	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1191	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1192	PteDst.u = 0;
1193	}
1194	else
1195	# endif
1196	/*
1197	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1198	* when the page is modified.
1199	*/
1200	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1201	{
1202	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1203	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1204	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1205	\| PGM_PTFLAGS_TRACK_DIRTY;
1206	}
1207	else
1208	{
1209	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1210	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1211	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1212	}
1213	#endif
1214	}
1215
1216	#ifdef PGMPOOL_WITH_USER_TRACKING
1217	/*
1218	* Keep user track up to date.
1219	*/
1220	if (PteDst.n.u1Present)
1221	{
1222	if (!pPteDst->n.u1Present)
1223	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1224	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1225	{
1226	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1227	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1228	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1229	}
1230	}
1231	else if (pPteDst->n.u1Present)
1232	{
1233	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1234	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1235	}
1236	#endif /* PGMPOOL_WITH_USER_TRACKING */
1237
1238	/*
1239	* Update statistics and commit the entry.
1240	*/
1241	if (!PteSrc.n.u1Global)
1242	pShwPage->fSeenNonGlobal = true;
1243	*pPteDst = PteDst;
1244	}
1245	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1246	/** @todo count these. */
1247	}
1248	else
1249	{
1250	/*
1251	* Page not-present.
1252	*/
1253	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1254	#ifdef PGMPOOL_WITH_USER_TRACKING
1255	/* Keep user track up to date. */
1256	if (pPteDst->n.u1Present)
1257	{
1258	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1259	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1260	}
1261	#endif /* PGMPOOL_WITH_USER_TRACKING */
1262	pPteDst->u = 0;
1263	/** @todo count these. */
1264	}
1265	}
1266
1267
1268	/**
1269	* Syncs a guest OS page.
1270	*
1271	* There are no conflicts at this point, neither is there any need for
1272	* page table allocations.
1273	*
1274	* @returns VBox status code.
1275	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1276	* @param pVM VM handle.
1277	* @param PdeSrc Page directory entry of the guest.
1278	* @param GCPtrPage Guest context page address.
1279	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1280	* @param uErr Fault error (X86_TRAP_PF_*).
1281	*/
1282	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1283	{
1284	# if PGM_WITH_NX(PGM_GST_TYPE)
1285	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1286	# endif
1287	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1288
1289	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1290	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1291
1292	/*
1293	* Assert preconditions.
1294	*/
1295	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1296	Assert(PdeSrc.n.u1Present);
1297	Assert(cPages);
1298
1299	/*
1300	* Get the shadow PDE, find the shadow page table in the pool.
1301	*/
1302	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1303	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1304	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1305	# else /* PAE */
1306	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1307	# endif
1308	Assert(PdeDst.n.u1Present);
1309	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1310
1311	/*
1312	* Check that the page is present and that the shadow PDE isn't out of sync.
1313	*/
1314	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1315	RTGCPHYS GCPhys;
1316	if (!fBigPage)
1317	{
1318	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1319	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1320	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1321	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1322	# endif
1323	}
1324	else
1325	{
1326	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1327	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1328	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1329	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1330	# endif
1331	}
1332	if ( pShwPage->GCPhys == GCPhys
1333	&& PdeSrc.n.u1Present
1334	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1335	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1336	# if PGM_WITH_NX(PGM_GST_TYPE)
1337	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1338	# endif
1339	)
1340	{
1341	# ifdef PGM_SYNC_ACCESSED_BIT
1342	/*
1343	* Check that the PDE is marked accessed already.
1344	* Since we set the accessed bit before getting here on a #PF, this
1345	* check is only meant for dealing with non-#PF'ing paths.
1346	*/
1347	if (PdeSrc.n.u1Accessed)
1348	# endif
1349	{
1350	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1351	if (!fBigPage)
1352	{
1353	/*
1354	* 4KB Page - Map the guest page table.
1355	*/
1356	PGSTPT pPTSrc;
1357	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1358	if (VBOX_SUCCESS(rc))
1359	{
1360	# ifdef PGM_SYNC_N_PAGES
1361	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1362	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1363	{
1364	/*
1365	* This code path is currently only taken when the caller is PGMTrap0eHandler
1366	* for non-present pages!
1367	*
1368	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1369	* deal with locality.
1370	*/
1371	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1372	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1373	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1374	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1375	# else
1376	const unsigned offPTSrc = 0;
1377	# endif
1378	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1379	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1380	iPTDst = 0;
1381	else
1382	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1383	for (; iPTDst < iPTDstEnd; iPTDst++)
1384	{
1385	if (!pPTDst->a[iPTDst].n.u1Present)
1386	{
1387	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1388	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1389	NOREF(GCPtrCurPage);
1390	#ifndef IN_RING0
1391	/*
1392	* Assuming kernel code will be marked as supervisor - and not as user level
1393	* and executed using a conforming code selector - And marked as readonly.
1394	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1395	*/
1396	PPGMPAGE pPage;
1397	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1398	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1399	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1400	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1401	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1402	)
1403	#endif /* else: CSAM not active */
1404	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1405	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1406	GCPtrCurPage, PteSrc.n.u1Present,
1407	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1408	PteSrc.n.u1User & PdeSrc.n.u1User,
1409	(uint64_t)PteSrc.u,
1410	(uint64_t)pPTDst->a[iPTDst].u,
1411	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1412	}
1413	}
1414	}
1415	else
1416	# endif /* PGM_SYNC_N_PAGES */
1417	{
1418	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1419	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1420	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1421	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1422	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1423	GCPtrPage, PteSrc.n.u1Present,
1424	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1425	PteSrc.n.u1User & PdeSrc.n.u1User,
1426	(uint64_t)PteSrc.u,
1427	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1428	}
1429	}
1430	else /* MMIO or invalid page: emulated in #PF handler. */
1431	{
1432	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1433	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1434	}
1435	}
1436	else
1437	{
1438	/*
1439	* 4/2MB page - lazy syncing shadow 4K pages.
1440	* (There are many causes of getting here, it's no longer only CSAM.)
1441	*/
1442	/* Calculate the GC physical address of this 4KB shadow page. */
1443	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1444	/* Find ram range. */
1445	PPGMPAGE pPage;
1446	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1447	if (VBOX_SUCCESS(rc))
1448	{
1449	/*
1450	* Make shadow PTE entry.
1451	*/
1452	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1453	SHWPTE PteDst;
1454	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1455	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1456	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1457	{
1458	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1459	PteDst.n.u1Write = 0;
1460	else
1461	PteDst.u = 0;
1462	}
1463	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1464	# ifdef PGMPOOL_WITH_USER_TRACKING
1465	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1466	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1467	# endif
1468	pPTDst->a[iPTDst] = PteDst;
1469
1470
1471	# ifdef PGM_SYNC_DIRTY_BIT
1472	/*
1473	* If the page is not flagged as dirty and is writable, then make it read-only
1474	* at PD level, so we can set the dirty bit when the page is modified.
1475	*
1476	* ASSUMES that page access handlers are implemented on page table entry level.
1477	* Thus we will first catch the dirty access and set PDE.D and restart. If
1478	* there is an access handler, we'll trap again and let it work on the problem.
1479	*/
1480	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1481	* As for invlpg, it simply frees the whole shadow PT.
1482	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1483	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1484	{
1485	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1486	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1487	PdeDst.n.u1Write = 0;
1488	}
1489	else
1490	{
1491	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1492	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1493	}
1494	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1495	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1496	# else /* PAE */
1497	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1498	# endif
1499	# endif /* PGM_SYNC_DIRTY_BIT */
1500	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1501	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1502	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1503	}
1504	else
1505	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1506	}
1507	return VINF_SUCCESS;
1508	}
1509	# ifdef PGM_SYNC_ACCESSED_BIT
1510	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1511	#endif
1512	}
1513	else
1514	{
1515	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1516	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1517	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1518	}
1519
1520	/*
1521	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1522	* Yea, I'm lazy.
1523	*/
1524	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1525	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1526	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1527	# else /* PAE */
1528	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1529	# endif
1530	PGM_INVL_GUEST_TLBS();
1531	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1532
1533	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1534
1535	# ifdef PGM_SYNC_N_PAGES
1536	/*
1537	* Get the shadow PDE, find the shadow page table in the pool.
1538	*/
1539	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1540	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1541	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1542	# else /* PAE */
1543	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1544	# endif
1545	Assert(PdeDst.n.u1Present);
1546	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1547	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1548
1549	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1550	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1551	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1552	# else
1553	const unsigned offPTSrc = 0;
1554	# endif
1555
1556	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1557	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1558	{
1559	/*
1560	* This code path is currently only taken when the caller is PGMTrap0eHandler
1561	* for non-present pages!
1562	*
1563	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1564	* deal with locality.
1565	*/
1566	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1567	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1568	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1569	iPTDst = 0;
1570	else
1571	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1572	for (; iPTDst < iPTDstEnd; iPTDst++)
1573	{
1574	if (!pPTDst->a[iPTDst].n.u1Present)
1575	{
1576	GSTPTE PteSrc;
1577
1578	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1579
1580	/* Fake the page table entry */
1581	PteSrc.u = GCPtrCurPage;
1582	PteSrc.n.u1Present = 1;
1583	PteSrc.n.u1Dirty = 1;
1584	PteSrc.n.u1Accessed = 1;
1585	PteSrc.n.u1Write = 1;
1586	PteSrc.n.u1User = 1;
1587
1588	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1589
1590	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1591	GCPtrCurPage, PteSrc.n.u1Present,
1592	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1593	PteSrc.n.u1User & PdeSrc.n.u1User,
1594	(uint64_t)PteSrc.u,
1595	(uint64_t)pPTDst->a[iPTDst].u,
1596	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1597	}
1598	}
1599	}
1600	else
1601	# endif /* PGM_SYNC_N_PAGES */
1602	{
1603	GSTPTE PteSrc;
1604	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1605	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1606
1607	/* Fake the page table entry */
1608	PteSrc.u = GCPtrCurPage;
1609	PteSrc.n.u1Present = 1;
1610	PteSrc.n.u1Dirty = 1;
1611	PteSrc.n.u1Accessed = 1;
1612	PteSrc.n.u1Write = 1;
1613	PteSrc.n.u1User = 1;
1614	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1615
1616	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1617	GCPtrPage, PteSrc.n.u1Present,
1618	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1619	PteSrc.n.u1User & PdeSrc.n.u1User,
1620	(uint64_t)PteSrc.u,
1621	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1622	}
1623	return VINF_SUCCESS;
1624
1625	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1626	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1627	return VERR_INTERNAL_ERROR;
1628	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1629	}
1630
1631
1632
1633	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1634
1635	# ifdef PGM_SYNC_DIRTY_BIT
1636
1637	/**
1638	* Investigate page fault and handle write protection page faults caused by
1639	* dirty bit tracking.
1640	*
1641	* @returns VBox status code.
1642	* @param pVM VM handle.
1643	* @param uErr Page fault error code.
1644	* @param pPdeDst Shadow page directory entry.
1645	* @param pPdeSrc Guest page directory entry.
1646	* @param GCPtrPage Guest context page address.
1647	*/
1648	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1649	{
1650	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1651	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1652	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1653	# if PGM_WITH_NX(PGM_GST_TYPE)
1654	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1655	# endif
1656
1657	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1658	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1659
1660	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1661	AssertFailed();
1662	# elif PGM_GST_TYPE == PGM_TYPE_PAE
1663	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1664
1665	/*
1666	* Real page fault?
1667	*/
1668	if ( (uErr & X86_TRAP_PF_RSVD)
1669	\|\| !pPdpeSrc->n.u1Present
1670	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1671	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->n.u1NoExecute)
1672	\|\| (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1673	\|\| (fUserLevelFault && !pPdpeSrc->n.u1User)
1674	# endif
1675	)
1676	{
1677	# ifdef IN_GC
1678	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1679	# endif
1680	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1681	LogFlow(("CheckPageFault: real page fault at %VGv (0)\n", GCPtrPage));
1682
1683	if ( pPdpeSrc->n.u1Present
1684	&& pPdeSrc->n.u1Present)
1685	{
1686	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1687	* See the 2nd case below as well.
1688	*/
1689	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1690	{
1691	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1692	}
1693	else
1694	{
1695	/*
1696	* Map the guest page table.
1697	*/
1698	PGSTPT pPTSrc;
1699	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1700	if (VBOX_SUCCESS(rc))
1701	{
1702	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1703	const GSTPTE PteSrc = *pPteSrc;
1704	if (pPteSrc->n.u1Present)
1705	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1706	}
1707	AssertRC(rc);
1708	}
1709	}
1710	return VINF_EM_RAW_GUEST_TRAP;
1711	}
1712	# endif
1713
1714	/*
1715	* Real page fault?
1716	*/
1717	if ( (uErr & X86_TRAP_PF_RSVD)
1718	\|\| !pPdeSrc->n.u1Present
1719	# if PGM_WITH_NX(PGM_GST_TYPE)
1720	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1721	# endif
1722	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1723	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1724	{
1725	# ifdef IN_GC
1726	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1727	# endif
1728	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1729	LogFlow(("CheckPageFault: real page fault at %VGv (1)\n", GCPtrPage));
1730
1731	if (pPdeSrc->n.u1Present)
1732	{
1733	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1734	* See the 2nd case below as well.
1735	*/
1736	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1737	{
1738	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1739	}
1740	else
1741	{
1742	/*
1743	* Map the guest page table.
1744	*/
1745	PGSTPT pPTSrc;
1746	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1747	if (VBOX_SUCCESS(rc))
1748	{
1749	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1750	const GSTPTE PteSrc = *pPteSrc;
1751	if (pPteSrc->n.u1Present)
1752	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1753	}
1754	AssertRC(rc);
1755	}
1756	}
1757	return VINF_EM_RAW_GUEST_TRAP;
1758	}
1759
1760	/*
1761	* First check the easy case where the page directory has been marked read-only to track
1762	* the dirty bit of an emulated BIG page
1763	*/
1764	if (pPdeSrc->b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE))
1765	{
1766	/* Mark guest page directory as accessed */
1767	pPdeSrc->b.u1Accessed = 1;
1768
1769	/*
1770	* Only write protection page faults are relevant here.
1771	*/
1772	if (fWriteFault)
1773	{
1774	/* Mark guest page directory as dirty (BIG page only). */
1775	pPdeSrc->b.u1Dirty = 1;
1776
1777	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1778	{
1779	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1780
1781	Assert(pPdeSrc->b.u1Write);
1782
1783	pPdeDst->n.u1Write = 1;
1784	pPdeDst->n.u1Accessed = 1;
1785	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1786	PGM_INVL_BIG_PG(GCPtrPage);
1787	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1788	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1789	}
1790	}
1791	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1792	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1793	}
1794	/* else: 4KB page table */
1795
1796	/*
1797	* Map the guest page table.
1798	*/
1799	PGSTPT pPTSrc;
1800	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1801	if (VBOX_SUCCESS(rc))
1802	{
1803	/*
1804	* Real page fault?
1805	*/
1806	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1807	const GSTPTE PteSrc = *pPteSrc;
1808	if ( !PteSrc.n.u1Present
1809	# if PGM_WITH_NX(PGM_GST_TYPE)
1810	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
1811	# endif
1812	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1813	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1814	)
1815	{
1816	# ifdef IN_GC
1817	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1818	# endif
1819	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1820	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1821
1822	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1823	* See the 2nd case above as well.
1824	*/
1825	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1826	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1827
1828	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1829	return VINF_EM_RAW_GUEST_TRAP;
1830	}
1831	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1832
1833	/*
1834	* Set the accessed bits in the page directory and the page table.
1835	*/
1836	pPdeSrc->n.u1Accessed = 1;
1837	pPteSrc->n.u1Accessed = 1;
1838
1839	/*
1840	* Only write protection page faults are relevant here.
1841	*/
1842	if (fWriteFault)
1843	{
1844	/* Write access, so mark guest entry as dirty. */
1845	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1846	if (!pPteSrc->n.u1Dirty)
1847	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1848	else
1849	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1850	# endif
1851	pPteSrc->n.u1Dirty = 1;
1852
1853	if (pPdeDst->n.u1Present)
1854	{
1855	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1856	* Our individual shadow handlers will provide more information and force a fatal exit.
1857	*/
1858	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1859	{
1860	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1861	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1862	return VINF_SUCCESS;
1863	}
1864
1865	/*
1866	* Map shadow page table.
1867	*/
1868	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1869	if (pShwPage)
1870	{
1871	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1872	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1873	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1874	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1875	{
1876	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1877	# ifdef VBOX_STRICT
1878	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1879	if (pPage)
1880	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1881	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1882	# endif
1883	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1884
1885	Assert(pPteSrc->n.u1Write);
1886
1887	pPteDst->n.u1Write = 1;
1888	pPteDst->n.u1Dirty = 1;
1889	pPteDst->n.u1Accessed = 1;
1890	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1891	PGM_INVL_PG(GCPtrPage);
1892
1893	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1894	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1895	}
1896	}
1897	else
1898	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1899	}
1900	}
1901	/** @todo Optimize accessed bit emulation? */
1902	# ifdef VBOX_STRICT
1903	/*
1904	* Sanity check.
1905	*/
1906	else if ( !pPteSrc->n.u1Dirty
1907	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1908	&& pPdeDst->n.u1Present)
1909	{
1910	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1911	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1912	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1913	if ( pPteDst->n.u1Present
1914	&& pPteDst->n.u1Write)
1915	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1916	}
1917	# endif /* VBOX_STRICT */
1918	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1919	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1920	}
1921	AssertRC(rc);
1922	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1923	return rc;
1924	}
1925
1926	# endif
1927
1928	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1929
1930
1931	/**
1932	* Sync a shadow page table.
1933	*
1934	* The shadow page table is not present. This includes the case where
1935	* there is a conflict with a mapping.
1936	*
1937	* @returns VBox status code.
1938	* @param pVM VM handle.
1939	* @param iPD Page directory index.
1940	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1941	* Assume this is a temporary mapping.
1942	* @param GCPtrPage GC Pointer of the page that caused the fault
1943	*/
1944	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1945	{
1946	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1947	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1948	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1949
1950	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1951	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1952
1953	/*
1954	* Validate input a little bit.
1955	*/
1956	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
1957	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1958	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
1959	# else
1960	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
1961	# endif
1962	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1963	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
1964	SHWPDE PdeDst = *pPdeDst;
1965
1966	# ifndef PGM_WITHOUT_MAPPINGS
1967	/*
1968	* Check for conflicts.
1969	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
1970	* HC: Simply resolve the conflict.
1971	*/
1972	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
1973	{
1974	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1975	# ifndef IN_RING3
1976	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
1977	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1978	return VERR_ADDRESS_CONFLICT;
1979	# else
1980	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
1981	Assert(pMapping);
1982	# if PGM_GST_TYPE == PGM_TYPE_32BIT
1983	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
1984	# elif PGM_GST_TYPE == PGM_TYPE_PAE
1985	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
1986	# endif
1987	if (VBOX_FAILURE(rc))
1988	{
1989	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1990	return rc;
1991	}
1992	PdeDst = *pPdeDst;
1993	# endif
1994	}
1995	# else /* PGM_WITHOUT_MAPPINGS */
1996	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
1997	# endif /* !PGM_WITHOUT_MAPPINGS */
1998	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
1999
2000	/*
2001	* Sync page directory entry.
2002	*/
2003	int rc = VINF_SUCCESS;
2004	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2005	if (PdeSrc.n.u1Present)
2006	{
2007	/*
2008	* Allocate & map the page table.
2009	*/
2010	PSHWPT pPTDst;
2011	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2012	PPGMPOOLPAGE pShwPage;
2013	RTGCPHYS GCPhys;
2014	if (fPageTable)
2015	{
2016	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2017	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2018	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2019	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2020	# endif
2021	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2022	}
2023	else
2024	{
2025	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2026	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2027	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2028	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2029	# endif
2030	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2031	}
2032	if (rc == VINF_SUCCESS)
2033	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2034	else if (rc == VINF_PGM_CACHED_PAGE)
2035	{
2036	/*
2037	* The PT was cached, just hook it up.
2038	*/
2039	if (fPageTable)
2040	PdeDst.u = pShwPage->Core.Key
2041	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2042	else
2043	{
2044	PdeDst.u = pShwPage->Core.Key
2045	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2046	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
2047	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2048	{
2049	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2050	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2051	PdeDst.b.u1Write = 0;
2052	}
2053	# endif
2054	}
2055	*pPdeDst = PdeDst;
2056	return VINF_SUCCESS;
2057	}
2058	else if (rc == VERR_PGM_POOL_FLUSHED)
2059	return VINF_PGM_SYNC_CR3;
2060	else
2061	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2062	PdeDst.u &= X86_PDE_AVL_MASK;
2063	PdeDst.u \|= pShwPage->Core.Key;
2064
2065	# ifdef PGM_SYNC_DIRTY_BIT
2066	/*
2067	* Page directory has been accessed (this is a fault situation, remember).
2068	*/
2069	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2070	# endif
2071	if (fPageTable)
2072	{
2073	/*
2074	* Page table - 4KB.
2075	*
2076	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2077	*/
2078	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2079	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2080	PGSTPT pPTSrc;
2081	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2082	if (VBOX_SUCCESS(rc))
2083	{
2084	/*
2085	* Start by syncing the page directory entry so CSAM's TLB trick works.
2086	*/
2087	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2088	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2089	*pPdeDst = PdeDst;
2090
2091	/*
2092	* Directory/page user or supervisor privilege: (same goes for read/write)
2093	*
2094	* Directory Page Combined
2095	* U/S U/S U/S
2096	* 0 0 0
2097	* 0 1 0
2098	* 1 0 0
2099	* 1 1 1
2100	*
2101	* Simple AND operation. Table listed for completeness.
2102	*
2103	*/
2104	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2105	# ifdef PGM_SYNC_N_PAGES
2106	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2107	unsigned iPTDst = iPTBase;
2108	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2109	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2110	iPTDst = 0;
2111	else
2112	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2113	# else /* !PGM_SYNC_N_PAGES */
2114	unsigned iPTDst = 0;
2115	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2116	# endif /* !PGM_SYNC_N_PAGES */
2117	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2118	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2119	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2120	# else
2121	const unsigned offPTSrc = 0;
2122	# endif
2123	for (; iPTDst < iPTDstEnd; iPTDst++)
2124	{
2125	const unsigned iPTSrc = iPTDst + offPTSrc;
2126	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2127
2128	if (PteSrc.n.u1Present) /* we've already cleared it above */
2129	{
2130	# ifndef IN_RING0
2131	/*
2132	* Assuming kernel code will be marked as supervisor - and not as user level
2133	* and executed using a conforming code selector - And marked as readonly.
2134	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2135	*/
2136	PPGMPAGE pPage;
2137	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2138	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2139	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2140	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2141	)
2142	# endif
2143	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2144	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2145	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2146	PteSrc.n.u1Present,
2147	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2148	PteSrc.n.u1User & PdeSrc.n.u1User,
2149	(uint64_t)PteSrc.u,
2150	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2151	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2152	}
2153	} /* for PTEs */
2154	}
2155	}
2156	else
2157	{
2158	/*
2159	* Big page - 2/4MB.
2160	*
2161	* We'll walk the ram range list in parallel and optimize lookups.
2162	* We will only sync on shadow page table at a time.
2163	*/
2164	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2165
2166	/**
2167	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2168	*/
2169
2170	/*
2171	* Start by syncing the page directory entry.
2172	*/
2173	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2174	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2175
2176	# ifdef PGM_SYNC_DIRTY_BIT
2177	/*
2178	* If the page is not flagged as dirty and is writable, then make it read-only
2179	* at PD level, so we can set the dirty bit when the page is modified.
2180	*
2181	* ASSUMES that page access handlers are implemented on page table entry level.
2182	* Thus we will first catch the dirty access and set PDE.D and restart. If
2183	* there is an access handler, we'll trap again and let it work on the problem.
2184	*/
2185	/** @todo move the above stuff to a section in the PGM documentation. */
2186	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2187	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2188	{
2189	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2190	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2191	PdeDst.b.u1Write = 0;
2192	}
2193	# endif /* PGM_SYNC_DIRTY_BIT */
2194	*pPdeDst = PdeDst;
2195
2196	/*
2197	* Fill the shadow page table.
2198	*/
2199	/* Get address and flags from the source PDE. */
2200	SHWPTE PteDstBase;
2201	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2202
2203	/* Loop thru the entries in the shadow PT. */
2204	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2205	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2206	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2207	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2208	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2209	unsigned iPTDst = 0;
2210	while (iPTDst < ELEMENTS(pPTDst->a))
2211	{
2212	/* Advance ram range list. */
2213	while (pRam && GCPhys > pRam->GCPhysLast)
2214	pRam = CTXALLSUFF(pRam->pNext);
2215	if (pRam && GCPhys >= pRam->GCPhys)
2216	{
2217	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2218	do
2219	{
2220	/* Make shadow PTE. */
2221	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2222	SHWPTE PteDst;
2223
2224	/* Make sure the RAM has already been allocated. */
2225	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2226	{
2227	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2228	{
2229	# ifdef IN_RING3
2230	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2231	# else
2232	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2233	# endif
2234	if (rc != VINF_SUCCESS)
2235	return rc;
2236	}
2237	}
2238
2239	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2240	{
2241	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2242	{
2243	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2244	PteDst.n.u1Write = 0;
2245	}
2246	else
2247	PteDst.u = 0;
2248	}
2249	# ifndef IN_RING0
2250	/*
2251	* Assuming kernel code will be marked as supervisor and not as user level and executed
2252	* using a conforming code selector. Don't check for readonly, as that implies the whole
2253	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2254	*/
2255	else if ( !PdeSrc.n.u1User
2256	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2257	PteDst.u = 0;
2258	# endif
2259	else
2260	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2261	# ifdef PGMPOOL_WITH_USER_TRACKING
2262	if (PteDst.n.u1Present)
2263	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2264	# endif
2265	/* commit it */
2266	pPTDst->a[iPTDst] = PteDst;
2267	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2268	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2269	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2270
2271	/* advance */
2272	GCPhys += PAGE_SIZE;
2273	iHCPage++;
2274	iPTDst++;
2275	} while ( iPTDst < ELEMENTS(pPTDst->a)
2276	&& GCPhys <= pRam->GCPhysLast);
2277	}
2278	else if (pRam)
2279	{
2280	Log(("Invalid pages at %VGp\n", GCPhys));
2281	do
2282	{
2283	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2284	GCPhys += PAGE_SIZE;
2285	iPTDst++;
2286	} while ( iPTDst < ELEMENTS(pPTDst->a)
2287	&& GCPhys < pRam->GCPhys);
2288	}
2289	else
2290	{
2291	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2292	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2293	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2294	}
2295	} /* while more PTEs */
2296	} /* 4KB / 4MB */
2297	}
2298	else
2299	AssertRelease(!PdeDst.n.u1Present);
2300
2301	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2302	# ifdef IN_GC
2303	if (VBOX_FAILURE(rc))
2304	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2305	# endif
2306	return rc;
2307
2308	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2309
2310	int rc = VINF_SUCCESS;
2311
2312	/*
2313	* Validate input a little bit.
2314	*/
2315	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2316	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2317	# else
2318	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2319	# endif
2320	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2321	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2322	SHWPDE PdeDst = *pPdeDst;
2323
2324	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2325	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2326
2327	GSTPDE PdeSrc;
2328	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2329	PdeSrc.n.u1Present = 1;
2330	PdeSrc.n.u1Write = 1;
2331	PdeSrc.n.u1Accessed = 1;
2332	PdeSrc.n.u1User = 1;
2333
2334	/*
2335	* Allocate & map the page table.
2336	*/
2337	PSHWPT pPTDst;
2338	PPGMPOOLPAGE pShwPage;
2339	RTGCPHYS GCPhys;
2340
2341	/* Virtual address = physical address */
2342	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2343	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2344
2345	if ( rc == VINF_SUCCESS
2346	\|\| rc == VINF_PGM_CACHED_PAGE)
2347	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2348	else
2349	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2350
2351	PdeDst.u &= X86_PDE_AVL_MASK;
2352	PdeDst.u \|= pShwPage->Core.Key;
2353	PdeDst.n.u1Present = 1;
2354	*pPdeDst = PdeDst;
2355
2356	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2357	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2358	return rc;
2359
2360	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2361	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2362	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2363	return VERR_INTERNAL_ERROR;
2364	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2365	}
2366
2367
2368
2369	/**
2370	* Prefetch a page/set of pages.
2371	*
2372	* Typically used to sync commonly used pages before entering raw mode
2373	* after a CR3 reload.
2374	*
2375	* @returns VBox status code.
2376	* @param pVM VM handle.
2377	* @param GCPtrPage Page to invalidate.
2378	*/
2379	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2380	{
2381	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2382	/*
2383	* Check that all Guest levels thru the PDE are present, getting the
2384	* PD and PDE in the processes.
2385	*/
2386	int rc = VINF_SUCCESS;
2387	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2388	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2389	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2390	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2391	# else /* PAE */
2392	unsigned iPDSrc;
2393	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2394	if (!pPDSrc)
2395	return VINF_SUCCESS; /* not present */
2396	# endif
2397	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2398	# else
2399	PGSTPD pPDSrc = NULL;
2400	const unsigned iPDSrc = 0;
2401	GSTPDE PdeSrc;
2402
2403	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2404	PdeSrc.n.u1Present = 1;
2405	PdeSrc.n.u1Write = 1;
2406	PdeSrc.n.u1Accessed = 1;
2407	PdeSrc.n.u1User = 1;
2408	# endif
2409
2410	# ifdef PGM_SYNC_ACCESSED_BIT
2411	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2412	# else
2413	if (PdeSrc.n.u1Present)
2414	# endif
2415	{
2416	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2417	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2418	# else
2419	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2420	# endif
2421	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2422	{
2423	if (!PdeDst.n.u1Present)
2424	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2425	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2426	else
2427	{
2428	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2429	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2430	* makes no sense to prefetch more than one page.
2431	*/
2432	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2433	if (VBOX_SUCCESS(rc))
2434	rc = VINF_SUCCESS;
2435	}
2436	}
2437	}
2438	return rc;
2439
2440	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2441
2442	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2443	return VERR_INTERNAL_ERROR;
2444	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2445	}
2446
2447
2448
2449
2450	/**
2451	* Syncs a page during a PGMVerifyAccess() call.
2452	*
2453	* @returns VBox status code (informational included).
2454	* @param GCPtrPage The address of the page to sync.
2455	* @param fPage The effective guest page flags.
2456	* @param uErr The trap error code.
2457	*/
2458	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2459	{
2460	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2461
2462	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2463
2464	# ifndef IN_RING0
2465	if (!(fPage & X86_PTE_US))
2466	{
2467	/*
2468	* Mark this page as safe.
2469	*/
2470	/** @todo not correct for pages that contain both code and data!! */
2471	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2472	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2473	}
2474	# endif
2475	/*
2476	* Get guest PD and index.
2477	*/
2478
2479	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2480	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2481	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2482	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2483	# else /* PAE */
2484	unsigned iPDSrc;
2485	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2486
2487	if (pPDSrc)
2488	{
2489	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2490	return VINF_EM_RAW_GUEST_TRAP;
2491	}
2492	# endif
2493	# else
2494	PGSTPD pPDSrc = NULL;
2495	const unsigned iPDSrc = 0;
2496	# endif
2497	int rc = VINF_SUCCESS;
2498
2499	/*
2500	* First check if the shadow pd is present.
2501	*/
2502	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2503	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2504	# else
2505	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2506	# endif
2507	if (!pPdeDst->n.u1Present)
2508	{
2509	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2510	AssertRC(rc);
2511	if (rc != VINF_SUCCESS)
2512	return rc;
2513	}
2514
2515	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2516	/* Check for dirty bit fault */
2517	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2518	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2519	Log(("PGMVerifyAccess: success (dirty)\n"));
2520	else
2521	{
2522	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2523	#else
2524	{
2525	GSTPDE PdeSrc;
2526	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2527	PdeSrc.n.u1Present = 1;
2528	PdeSrc.n.u1Write = 1;
2529	PdeSrc.n.u1Accessed = 1;
2530	PdeSrc.n.u1User = 1;
2531
2532	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2533	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2534	if (uErr & X86_TRAP_PF_US)
2535	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2536	else /* supervisor */
2537	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2538
2539	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2540	if (VBOX_SUCCESS(rc))
2541	{
2542	/* Page was successfully synced */
2543	Log2(("PGMVerifyAccess: success (sync)\n"));
2544	rc = VINF_SUCCESS;
2545	}
2546	else
2547	{
2548	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2549	return VINF_EM_RAW_GUEST_TRAP;
2550	}
2551	}
2552	return rc;
2553
2554	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2555
2556	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2557	return VERR_INTERNAL_ERROR;
2558	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2559	}
2560
2561
2562	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2563	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2564	/**
2565	* Figures out which kind of shadow page this guest PDE warrants.
2566	*
2567	* @returns Shadow page kind.
2568	* @param pPdeSrc The guest PDE in question.
2569	* @param cr4 The current guest cr4 value.
2570	*/
2571	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2572	{
2573	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2574	return BTH_PGMPOOLKIND_PT_FOR_PT;
2575	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2576	//{
2577	// case 0:
2578	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2579	// case X86_PDE4M_RW:
2580	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2581	// case X86_PDE4M_US:
2582	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2583	// case X86_PDE4M_RW \| X86_PDE4M_US:
2584	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2585	# if 0
2586	// case X86_PDE4M_PAE_NX:
2587	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2588	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2589	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2590	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2591	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2592	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2593	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2594	# endif
2595	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2596	//}
2597	}
2598	# endif
2599	#endif
2600
2601	#undef MY_STAM_COUNTER_INC
2602	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2603
2604
2605	/**
2606	* Syncs the paging hierarchy starting at CR3.
2607	*
2608	* @returns VBox status code, no specials.
2609	* @param pVM The virtual machine.
2610	* @param cr0 Guest context CR0 register
2611	* @param cr3 Guest context CR3 register
2612	* @param cr4 Guest context CR4 register
2613	* @param fGlobal Including global page directories or not
2614	*/
2615	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2616	{
2617	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2618	fGlobal = true; /* Change this CR3 reload to be a global one. */
2619
2620	/*
2621	* Update page access handlers.
2622	* The virtual are always flushed, while the physical are only on demand.
2623	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2624	* have to look into that later because it will have a bad influence on the performance.
2625	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2626	* bird: Yes, but that won't work for aliases.
2627	*/
2628	/** @todo this MUST go away. See #1557. */
2629	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2630	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2631	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2632
2633	#ifdef IN_RING3
2634	_asm int 3;
2635	#endif
2636
2637	#ifdef PGMPOOL_WITH_MONITORING
2638	/*
2639	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2640	* Occationally we will have to clear all the shadow page tables because we wanted
2641	* to monitor a page which was mapped by too many shadowed page tables. This operation
2642	* sometimes refered to as a 'lightweight flush'.
2643	*/
2644	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2645	pgmPoolMonitorModifiedClearAll(pVM);
2646	else
2647	{
2648	# ifdef IN_RING3
2649	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2650	pgmPoolClearAll(pVM);
2651	# else
2652	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2653	return VINF_PGM_SYNC_CR3;
2654	# endif
2655	}
2656	#endif
2657
2658	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2659	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2660
2661	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2662	/*
2663	* Get page directory addresses.
2664	*/
2665	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2666	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2667	# else
2668	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2669	# endif
2670
2671	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2672	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2673	Assert(pPDSrc);
2674	# ifndef IN_GC
2675	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2676	# endif
2677	# endif
2678
2679	/*
2680	* Iterate the page directory.
2681	*/
2682	PPGMMAPPING pMapping;
2683	unsigned iPdNoMapping;
2684	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2685	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2686
2687	/* Only check mappings if they are supposed to be put into the shadow page table. */
2688	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2689	{
2690	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2691	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
2692	}
2693	else
2694	{
2695	pMapping = 0;
2696	iPdNoMapping = ~0U;
2697	}
2698	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2699	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2700	{
2701	unsigned iPDSrc;
2702	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2703	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2704	# else
2705	AssertFailed(); /* @todo */
2706	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2707	# endif
2708	PX86PDEPAE pPDEDst = &pPDPAE->a[iPDPTE * X86_PG_PAE_ENTRIES];
2709	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2710
2711	if (pPDSrc == NULL)
2712	{
2713	/* PDPT not present */
2714	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
2715	{
2716	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2717	{
2718	if (pPDEDst[iPD].n.u1Present)
2719	{
2720	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPDPTE * X86_PG_PAE_ENTRIES + iPD);
2721	pPDEDst[iPD].u = 0;
2722	}
2723	}
2724	}
2725	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 0;
2726	continue;
2727	}
2728	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2729	{
2730	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2731	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2732	{
2733	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2734	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2735	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2736	Assert(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst);
2737	# endif
2738	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2739	if ( PdeSrc.n.u1Present
2740	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2741	{
2742	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \
2743	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
2744	&& !defined(PGM_WITHOUT_MAPPINGS)
2745
2746	/*
2747	* Check for conflicts with GC mappings.
2748	*/
2749	# if PGM_GST_TYPE == PGM_TYPE_PAE
2750	if (iPD + iPDPTE * X86_PG_PAE_ENTRIES == iPdNoMapping)
2751	# else
2752	if (iPD == iPdNoMapping)
2753	# endif
2754	{
2755	if (pVM->pgm.s.fMappingsFixed)
2756	{
2757	/* It's fixed, just skip the mapping. */
2758	const unsigned cPTs = pMapping->cb >> SHW_PD_SHIFT;
2759	iPD += cPTs - 1;
2760	pPDEDst += cPTs + cPTs;
2761	pMapping = pMapping->CTXALLSUFF(pNext);
2762	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2763	continue;
2764	}
2765	# ifdef IN_RING3
2766	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2767	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
2768	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2769	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPDPTE << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
2770	# endif
2771	if (VBOX_FAILURE(rc))
2772	return rc;
2773
2774	/*
2775	* Update iPdNoMapping and pMapping.
2776	*/
2777	pMapping = pVM->pgm.s.pMappingsR3;
2778	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
2779	pMapping = pMapping->pNextR3;
2780	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2781	# else
2782	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2783	return VINF_PGM_SYNC_CR3;
2784	# endif
2785	}
2786	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE && PGM_WITHOUT_MAPPINGS */
2787	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2788	# endif /* (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && !PGM_WITHOUT_MAPPINGS */
2789	/*
2790	* Sync page directory entry.
2791	*
2792	* The current approach is to allocated the page table but to set
2793	* the entry to not-present and postpone the page table synching till
2794	* it's actually used.
2795	*/
2796	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2797	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2798	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2799	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2800	# else
2801	const unsigned iPdShw = iPD; NOREF(iPdShw);
2802	# endif
2803	{
2804	SHWPDE PdeDst = *pPDEDst;
2805	if (PdeDst.n.u1Present)
2806	{
2807	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2808	RTGCPHYS GCPhys;
2809	if ( !PdeSrc.b.u1Size
2810	\|\| !(cr4 & X86_CR4_PSE))
2811	{
2812	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2813	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2814	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2815	GCPhys \|= i * (PAGE_SIZE / 2);
2816	# endif
2817	}
2818	else
2819	{
2820	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2821	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2822	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2823	GCPhys \|= i * X86_PAGE_2M_SIZE;
2824	# endif
2825	}
2826
2827	if ( pShwPage->GCPhys == GCPhys
2828	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2829	&& ( pShwPage->fCached
2830	\|\| ( !fGlobal
2831	&& ( false
2832	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2833	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2834	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2835	\|\| ( !pShwPage->fSeenNonGlobal
2836	&& (cr4 & X86_CR4_PGE))
2837	# endif
2838	)
2839	)
2840	)
2841	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2842	\|\| ( (cr4 & X86_CR4_PSE)
2843	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2844	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2845	)
2846	)
2847	{
2848	# ifdef VBOX_WITH_STATISTICS
2849	if ( !fGlobal
2850	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2851	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2852	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2853	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2854	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2855	else
2856	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2857	# endif /* VBOX_WITH_STATISTICS */
2858	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2859	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2860	//# ifdef PGMPOOL_WITH_CACHE
2861	// pgmPoolCacheUsed(pPool, pShwPage);
2862	//# endif
2863	}
2864	else
2865	{
2866	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2867	pPDEDst->u = 0;
2868	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2869	}
2870	}
2871	else
2872	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2873	pPDEDst++;
2874	}
2875	}
2876	# if PGM_GST_TYPE == PGM_TYPE_PAE
2877	else if (iPD + iPDPTE * X86_PG_PAE_ENTRIES != iPdNoMapping)
2878	# else
2879	else if (iPD != iPdNoMapping)
2880	# endif
2881	{
2882	/*
2883	* Check if there is any page directory to mark not present here.
2884	*/
2885	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2886	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2887	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2888	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2889	# else
2890	const unsigned iPdShw = iPD; NOREF(iPdShw);
2891	# endif
2892	{
2893	if (pPDEDst->n.u1Present)
2894	{
2895	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2896	pPDEDst->u = 0;
2897	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2898	}
2899	pPDEDst++;
2900	}
2901	}
2902	else
2903	{
2904	# if (PGM_GST_TYPE == PGM_TYPE_32BIT \
2905	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
2906	&& !defined(PGM_WITHOUT_MAPPINGS)
2907
2908	const unsigned cPTs = pMapping->cb >> SHW_PD_SHIFT; /* needed below to skip the mapping */
2909
2910	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2911	if (pVM->pgm.s.fMappingsFixed)
2912	{
2913	/* It's fixed, just skip the mapping. */
2914	pMapping = pMapping->CTXALLSUFF(pNext);
2915	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2916	}
2917	else
2918	{
2919	/*
2920	* Check for conflicts for subsequent pagetables
2921	* and advance to the next mapping.
2922	*/
2923	iPdNoMapping = ~0U;
2924	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
2925	while (iPT-- > 1)
2926	{
2927	if ( pPDSrc->a[iPD + iPT].n.u1Present
2928	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2929	{
2930	# ifdef IN_RING3
2931	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2932	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
2933	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2934	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPDPTE << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
2935	# endif
2936	if (VBOX_FAILURE(rc))
2937	return rc;
2938
2939	/*
2940	* Update iPdNoMapping and pMapping.
2941	*/
2942	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2943	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
2944	pMapping = pMapping->CTXALLSUFF(pNext);
2945	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2946	break;
2947	# else
2948	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2949	return VINF_PGM_SYNC_CR3;
2950	# endif
2951	}
2952	}
2953	if (iPdNoMapping == ~0U && pMapping)
2954	{
2955	pMapping = pMapping->CTXALLSUFF(pNext);
2956	if (pMapping)
2957	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
2958	}
2959	}
2960
2961	/* advance. */
2962	iPD += cPTs - 1;
2963	pPDEDst += cPTs;
2964	# else /* PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE && PGM_WITHOUT_MAPPINGS */
2965	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2966	# endif /* (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && !PGM_WITHOUT_MAPPINGS */
2967	}
2968
2969	} /* for iPD */
2970	} /* for each PDPTE (PAE) */
2971
2972	return VINF_SUCCESS;
2973
2974	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
2975	//# error not implemented
2976	return VERR_INTERNAL_ERROR;
2977	#else /* guest real and protected mode */
2978	return VINF_SUCCESS;
2979	#endif
2980	}
2981
2982
2983
2984
2985	#ifdef VBOX_STRICT
2986	#ifdef IN_GC
2987	# undef AssertMsgFailed
2988	# define AssertMsgFailed Log
2989	#endif
2990	#ifdef IN_RING3
2991	# include <VBox/dbgf.h>
2992
2993	/**
2994	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
2995	*
2996	* @returns VBox status code (VINF_SUCCESS).
2997	* @param pVM The VM handle.
2998	* @param cr3 The root of the hierarchy.
2999	* @param crr The cr4, only PAE and PSE is currently used.
3000	* @param fLongMode Set if long mode, false if not long mode.
3001	* @param cMaxDepth Number of levels to dump.
3002	* @param pHlp Pointer to the output functions.
3003	*/
3004	__BEGIN_DECLS
3005	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3006	__END_DECLS
3007
3008	#endif
3009
3010	/**
3011	* Checks that the shadow page table is in sync with the guest one.
3012	*
3013	* @returns The number of errors.
3014	* @param pVM The virtual machine.
3015	* @param cr3 Guest context CR3 register
3016	* @param cr4 Guest context CR4 register
3017	* @param GCPtr Where to start. Defaults to 0.
3018	* @param cb How much to check. Defaults to everything.
3019	*/
3020	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3021	{
3022	unsigned cErrors = 0;
3023
3024	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3025	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
3026
3027	PPGM pPGM = &pVM->pgm.s;
3028	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3029	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3030	# ifndef IN_RING0
3031	RTHCPHYS HCPhys; /* general usage. */
3032	# endif
3033	int rc;
3034
3035	/*
3036	* Check that the Guest CR3 and all its mappings are correct.
3037	*/
3038	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3039	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3040	false);
3041	# ifndef IN_RING0
3042	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3043	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
3044	# else
3045	rc = PGMShwGetPage(pVM, pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3046	# endif
3047	AssertRCReturn(rc, 1);
3048	HCPhys = NIL_RTHCPHYS;
3049	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3050	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3051	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3052	RTGCPHYS GCPhys;
3053	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3054	AssertRCReturn(rc, 1);
3055	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3056	# endif
3057	#endif /* !IN_RING0 */
3058
3059	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3060	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3061	# endif
3062
3063	/*
3064	* Get and check the Shadow CR3.
3065	*/
3066	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3067	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3068	unsigned cPDEs = ELEMENTS(pPDDst->a);
3069	# else
3070	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
3071	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
3072	# endif
3073	if (cb != ~(RTGCUINTPTR)0)
3074	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3075
3076	/** @todo call the other two PGMAssert() functions. /
3077
3078	# if PGM_GST_TYPE == PGM_TYPE_PAE
3079	/*
3080	* Check the 4 PDPTs too.
3081	*/
3082	for (unsigned i = 0; i < 4; i++)
3083	{
3084	RTHCPTR HCPtr;
3085	RTHCPHYS HCPhys;
3086	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
3087	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
3088	if (VBOX_SUCCESS(rc2))
3089	{
3090	AssertMsg( pVM->pgm.s.apGstPaePDsHC[i] == (R3R0PTRTYPE(PX86PDPAE))HCPtr
3091	&& pVM->pgm.s.aGCPhysGstPaePDs[i] == GCPhys,
3092	("idx %d apGstPaePDsHC %VHv vs %VHv aGCPhysGstPaePDs %VGp vs %VGp\n",
3093	i, pVM->pgm.s.apGstPaePDsHC[i], HCPtr, pVM->pgm.s.aGCPhysGstPaePDs[i], GCPhys));
3094	}
3095	}
3096	# endif
3097
3098	/*
3099	* Iterate the shadow page directory.
3100	*/
3101	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3102	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
3103	cPDEs += iPDDst;
3104	for (;
3105	iPDDst < cPDEs;
3106	iPDDst++, GCPtr += _4G / cPDEs)
3107	{
3108	# if PGM_GST_TYPE == PGM_TYPE_PAE
3109	uint32_t iPDSrc;
3110	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pPGM, (RTGCUINTPTR)GCPtr, &iPDSrc);
3111	if (!pPDSrc)
3112	{
3113	AssertMsg(!pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].n.u1Present, ("Guest PDTPR not present, shadow PDPTR %VX64\n", pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].u));
3114	continue;
3115	}
3116	#endif
3117
3118	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3119	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3120	{
3121	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3122	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3123	{
3124	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3125	cErrors++;
3126	continue;
3127	}
3128	}
3129	else if ( (PdeDst.u & X86_PDE_P)
3130	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3131	)
3132	{
3133	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3134	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3135	if (!pPoolPage)
3136	{
3137	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3138	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3139	cErrors++;
3140	continue;
3141	}
3142	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3143
3144	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3145	{
3146	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3147	GCPtr, (uint64_t)PdeDst.u));
3148	cErrors++;
3149	}
3150
3151	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3152	{
3153	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3154	GCPtr, (uint64_t)PdeDst.u));
3155	cErrors++;
3156	}
3157
3158	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3159	if (!PdeSrc.n.u1Present)
3160	{
3161	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3162	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3163	cErrors++;
3164	continue;
3165	}
3166
3167	if ( !PdeSrc.b.u1Size
3168	\|\| !(cr4 & X86_CR4_PSE))
3169	{
3170	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3171	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3172	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3173	# endif
3174	}
3175	else
3176	{
3177	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3178	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3179	{
3180	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3181	GCPtr, (uint64_t)PdeSrc.u));
3182	cErrors++;
3183	continue;
3184	}
3185	# endif
3186	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3187	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3188	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3189	# endif
3190	}
3191
3192	if ( pPoolPage->enmKind
3193	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3194	{
3195	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3196	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3197	cErrors++;
3198	}
3199
3200	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3201	if (!pPhysPage)
3202	{
3203	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3204	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3205	cErrors++;
3206	continue;
3207	}
3208
3209	if (GCPhysGst != pPoolPage->GCPhys)
3210	{
3211	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3212	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3213	cErrors++;
3214	continue;
3215	}
3216
3217	if ( !PdeSrc.b.u1Size
3218	\|\| !(cr4 & X86_CR4_PSE))
3219	{
3220	/*
3221	* Page Table.
3222	*/
3223	const GSTPT *pPTSrc;
3224	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3225	if (VBOX_FAILURE(rc))
3226	{
3227	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3228	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3229	cErrors++;
3230	continue;
3231	}
3232	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3233	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3234	{
3235	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3236	// (This problem will go away when/if we shadow multiple CR3s.)
3237	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3238	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3239	cErrors++;
3240	continue;
3241	}
3242	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3243	{
3244	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3245	GCPtr, (uint64_t)PdeDst.u));
3246	cErrors++;
3247	continue;
3248	}
3249
3250	/* iterate the page table. */
3251	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3252	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3253	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3254	# else
3255	const unsigned offPTSrc = 0;
3256	# endif
3257	for (unsigned iPT = 0, off = 0;
3258	iPT < ELEMENTS(pPTDst->a);
3259	iPT++, off += PAGE_SIZE)
3260	{
3261	const SHWPTE PteDst = pPTDst->a[iPT];
3262
3263	/* skip not-present entries. */
3264	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3265	continue;
3266	Assert(PteDst.n.u1Present);
3267
3268	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3269	if (!PteSrc.n.u1Present)
3270	{
3271	#ifdef IN_RING3
3272	PGMAssertHandlerAndFlagsInSync(pVM);
3273	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3274	#endif
3275	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3276	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3277	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3278	cErrors++;
3279	continue;
3280	}
3281
3282	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3283	# if 1 /** @todo sync accessed bit properly... */
3284	fIgnoreFlags \|= X86_PTE_A;
3285	# endif
3286
3287	/* match the physical addresses */
3288	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3289	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3290
3291	# ifdef IN_RING3
3292	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3293	if (VBOX_FAILURE(rc))
3294	{
3295	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3296	{
3297	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3298	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3299	cErrors++;
3300	continue;
3301	}
3302	}
3303	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3304	{
3305	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3306	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3307	cErrors++;
3308	continue;
3309	}
3310	# endif
3311
3312	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3313	if (!pPhysPage)
3314	{
3315	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3316	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3317	{
3318	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3319	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3320	cErrors++;
3321	continue;
3322	}
3323	# endif
3324	if (PteDst.n.u1Write)
3325	{
3326	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3327	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3328	cErrors++;
3329	}
3330	fIgnoreFlags \|= X86_PTE_RW;
3331	}
3332	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3333	{
3334	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3335	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3336	cErrors++;
3337	continue;
3338	}
3339
3340	/* flags */
3341	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3342	{
3343	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3344	{
3345	if (PteDst.n.u1Write)
3346	{
3347	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3348	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3349	cErrors++;
3350	continue;
3351	}
3352	fIgnoreFlags \|= X86_PTE_RW;
3353	}
3354	else
3355	{
3356	if (PteDst.n.u1Present)
3357	{
3358	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3359	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3360	cErrors++;
3361	continue;
3362	}
3363	fIgnoreFlags \|= X86_PTE_P;
3364	}
3365	}
3366	else
3367	{
3368	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3369	{
3370	if (PteDst.n.u1Write)
3371	{
3372	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3373	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3374	cErrors++;
3375	continue;
3376	}
3377	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3378	{
3379	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3380	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3381	cErrors++;
3382	continue;
3383	}
3384	if (PteDst.n.u1Dirty)
3385	{
3386	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3387	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3388	cErrors++;
3389	}
3390	# if 0 /** @todo sync access bit properly... */
3391	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3392	{
3393	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3394	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3395	cErrors++;
3396	}
3397	fIgnoreFlags \|= X86_PTE_RW;
3398	# else
3399	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3400	# endif
3401	}
3402	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3403	{
3404	/* access bit emulation (not implemented). */
3405	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3406	{
3407	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3408	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3409	cErrors++;
3410	continue;
3411	}
3412	if (!PteDst.n.u1Accessed)
3413	{
3414	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3415	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3416	cErrors++;
3417	}
3418	fIgnoreFlags \|= X86_PTE_P;
3419	}
3420	# ifdef DEBUG_sandervl
3421	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3422	# endif
3423	}
3424
3425	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3426	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3427	)
3428	{
3429	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3430	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3431	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3432	cErrors++;
3433	continue;
3434	}
3435	} /* foreach PTE */
3436	}
3437	else
3438	{
3439	/*
3440	* Big Page.
3441	*/
3442	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3443	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3444	{
3445	if (PdeDst.n.u1Write)
3446	{
3447	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3448	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3449	cErrors++;
3450	continue;
3451	}
3452	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3453	{
3454	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3455	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3456	cErrors++;
3457	continue;
3458	}
3459	# if 0 /** @todo sync access bit properly... */
3460	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3461	{
3462	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3463	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3464	cErrors++;
3465	}
3466	fIgnoreFlags \|= X86_PTE_RW;
3467	# else
3468	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3469	# endif
3470	}
3471	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3472	{
3473	/* access bit emulation (not implemented). */
3474	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3475	{
3476	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3477	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3478	cErrors++;
3479	continue;
3480	}
3481	if (!PdeDst.n.u1Accessed)
3482	{
3483	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3484	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3485	cErrors++;
3486	}
3487	fIgnoreFlags \|= X86_PTE_P;
3488	}
3489
3490	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3491	{
3492	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3493	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3494	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3495	cErrors++;
3496	}
3497
3498	/* iterate the page table. */
3499	for (unsigned iPT = 0, off = 0;
3500	iPT < ELEMENTS(pPTDst->a);
3501	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3502	{
3503	const SHWPTE PteDst = pPTDst->a[iPT];
3504
3505	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3506	{
3507	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3508	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3509	cErrors++;
3510	}
3511
3512	/* skip not-present entries. */
3513	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3514	continue;
3515
3516	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3517
3518	/* match the physical addresses */
3519	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3520
3521	# ifdef IN_RING3
3522	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3523	if (VBOX_FAILURE(rc))
3524	{
3525	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3526	{
3527	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3528	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3529	cErrors++;
3530	}
3531	}
3532	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3533	{
3534	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3535	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3536	cErrors++;
3537	continue;
3538	}
3539	# endif
3540
3541	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3542	if (!pPhysPage)
3543	{
3544	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3545	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3546	{
3547	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3548	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3549	cErrors++;
3550	continue;
3551	}
3552	# endif
3553	if (PteDst.n.u1Write)
3554	{
3555	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3556	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3557	cErrors++;
3558	}
3559	fIgnoreFlags \|= X86_PTE_RW;
3560	}
3561	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3562	{
3563	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3564	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3565	cErrors++;
3566	continue;
3567	}
3568
3569	/* flags */
3570	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3571	{
3572	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3573	{
3574	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3575	{
3576	if (PteDst.n.u1Write)
3577	{
3578	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3579	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3580	cErrors++;
3581	continue;
3582	}
3583	fIgnoreFlags \|= X86_PTE_RW;
3584	}
3585	}
3586	else
3587	{
3588	if (PteDst.n.u1Present)
3589	{
3590	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3591	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3592	cErrors++;
3593	continue;
3594	}
3595	fIgnoreFlags \|= X86_PTE_P;
3596	}
3597	}
3598
3599	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3600	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3601	)
3602	{
3603	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3604	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3605	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3606	cErrors++;
3607	continue;
3608	}
3609	} /* foreach PTE */
3610	}
3611	}
3612	/* not present */
3613
3614	} /* forearch PDE */
3615
3616	# ifdef DEBUG
3617	if (cErrors)
3618	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3619	# endif
3620
3621	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3622	//# error not implemented
3623
3624
3625	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3626	//# error not implemented
3627
3628	/#else: guest real and protected mode /
3629	#endif
3630	return cErrors;
3631	}
3632	#endif /* VBOX_STRICT */
3633

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 8030

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