PGMAllBth.h@ 8533

Last change on this file since 8533 was 8533, checked in by vboxsync, 17 years ago
Start of 64 bits paging support
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File size: 159.1 KB

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1	/* $Id: PGMAllBth.h 8533 2008-05-02 16:04:51Z vboxsync $ */
2	/** @file
3	* VBox - Page Manager, Shadow+Guest Paging Template - All context code.
4	*
5	* This file is a big challenge!
6	*/
7
8	/*
9	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
10	*
11	* This file is part of VirtualBox Open Source Edition (OSE), as
12	* available from http://www.virtualbox.org. This file is free software;
13	* you can redistribute it and/or modify it under the terms of the GNU
14	* General Public License (GPL) as published by the Free Software
15	* Foundation, in version 2 as it comes in the "COPYING" file of the
16	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
17	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
18	*
19	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
20	* Clara, CA 95054 USA or visit http://www.sun.com if you need
21	* additional information or have any questions.
22	*/
23
24	/*******************************************************************************
25	* Internal Functions *
26	*******************************************************************************/
27	__BEGIN_DECLS
28	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault);
29	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage);
30	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr);
31	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage);
32	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPD, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage);
33	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR Addr, unsigned fPage, unsigned uErr);
34	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage);
35	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
36	#ifdef VBOX_STRICT
37	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr = 0, RTGCUINTPTR cb = ~(RTGCUINTPTR)0);
38	#endif
39	#ifdef PGMPOOL_WITH_USER_TRACKING
40	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys);
41	#endif
42	__END_DECLS
43
44
45	/* Filter out some illegal combinations of guest and shadow paging, so we can remove redundant checks inside functions. */
46	#if PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE
47	# error "Invalid combination; PAE guest implies PAE shadow"
48	#endif
49
50	#if (PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT) \
51	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
52	# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
53	#endif
54
55	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
56	&& !(PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE)
57	# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
58	#endif
59
60	#if (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64)
61	\|\| (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64)
62	# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
63	#endif
64
65	#ifdef IN_RING0 /* no mappings in VT-x and AMD-V mode */
66	# define PGM_WITHOUT_MAPPINGS
67	#endif
68
69	/**
70	* #PF Handler for raw-mode guest execution.
71	*
72	* @returns VBox status code (appropriate for trap handling and GC return).
73	* @param pVM VM Handle.
74	* @param uErr The trap error code.
75	* @param pRegFrame Trap register frame.
76	* @param pvFault The fault address.
77	*/
78	PGM_BTH_DECL(int, Trap0eHandler)(PVM pVM, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault)
79	{
80	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
81
82	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_PAE
83	/*
84	* Hide the instruction fetch trap indicator for now.
85	*/
86	/** @todo NXE will change this and we must fix NXE in the switcher too! */
87	if (uErr & X86_TRAP_PF_ID)
88	{
89	uErr &= ~X86_TRAP_PF_ID;
90	TRPMSetErrorCode(pVM, uErr);
91	}
92	# endif
93
94	/*
95	* Get PDs.
96	*/
97	int rc;
98	# if PGM_WITH_PAGING(PGM_GST_TYPE)
99	# if PGM_GST_TYPE == PGM_TYPE_32BIT
100	const unsigned iPDSrc = (RTGCUINTPTR)pvFault >> GST_PD_SHIFT;
101	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
102
103	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
104
105	# if PGM_GST_TYPE == PGM_TYPE_PAE
106	unsigned iPDSrc;
107	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, (RTGCUINTPTR)pvFault, &iPDSrc);
108
109	# elif PGM_GST_TYPE == PGM_TYPE_AMD64
110	unsigned iPDSrc;
111	PX86PML4E pPml4e;
112	X86PDPE Pdpe;
113	PGSTPD pPDSrc;
114
115	pPDSrc = pgmGstGetLongModePDPtr(&pVM->pgm.s, pvFault, &pPml4e, &Pdpe, &iPDSrc);
116	Assert(pPml4e);
117	# endif
118	/* Quick check for a valid guest trap. */
119	if (!pPDSrc)
120	{
121	LogFlow(("Trap0eHandler: guest PDPTR not present CR3=%VGp\n", (CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK)));
122	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eGuestTrap; });
123	TRPMSetErrorCode(pVM, uErr);
124	return VINF_EM_RAW_GUEST_TRAP;
125	}
126	# endif
127	# else
128	PGSTPD pPDSrc = NULL;
129	const unsigned iPDSrc = 0;
130	# endif
131
132	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
133	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
134	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
135	# elif PGM_SHW_TYPE == PGM_TYPE_PAE
136	const unsigned iPDDst = (RTGCUINTPTR)pvFault >> SHW_PD_SHIFT;
137	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]; /* We treat this as a PD with 2048 entries, so no need to and with SHW_PD_MASK to get iPDDst */
138
139	# if PGM_GST_TYPE == PGM_TYPE_PAE
140	/* Did we mark the PDPT as not present in SyncCR3? */
141	unsigned iPDPTE = ((RTGCUINTPTR)pvFault >> SHW_PDPT_SHIFT) & SHW_PDPT_MASK;
142	if (!pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
143	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 1;
144
145	# endif
146
147	# elif PGM_SHW_TYPE == PGM_TYPE_AMD64
148	const unsigned iPDDst = (((RTGCUINTPTR)pvFault >> SHW_PD_SHIFT) & SHW_PD_MASK);
149	PX86PDPAE pPDDst;
150
151	rc = PGMShwGetLongModePDPtr(pVM, (RTGCUINTPTR)pvFault, &pPDDst);
152	if (rc != VINF_SUCCESS)
153	{
154	AssertMsg(rc == VINF_PGM_SYNC_CR3, ("Unexpected rc=%Vrc\n", rc));
155	return rc;
156	}
157	Assert(pPDDst);
158	# endif
159
160	# if PGM_WITH_PAGING(PGM_GST_TYPE)
161	# ifdef PGM_SYNC_DIRTY_BIT
162	/*
163	* If we successfully correct the write protection fault due to dirty bit
164	* tracking, or this page fault is a genuine one, then return immediately.
165	*/
166	STAM_PROFILE_START(&pVM->pgm.s.StatCheckPageFault, e);
167	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, &pPDDst->a[iPDDst], &pPDSrc->a[iPDSrc], (RTGCUINTPTR)pvFault);
168	STAM_PROFILE_STOP(&pVM->pgm.s.StatCheckPageFault, e);
169	if ( rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT
170	\|\| rc == VINF_EM_RAW_GUEST_TRAP)
171	{
172	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution)
173	= rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? &pVM->pgm.s.StatTrap0eDirtyAndAccessedBits : &pVM->pgm.s.StatTrap0eGuestTrap; });
174	LogBird(("Trap0eHandler: returns %s\n", rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? "VINF_SUCCESS" : "VINF_EM_RAW_GUEST_TRAP"));
175	return rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT ? VINF_SUCCESS : rc;
176	}
177	# endif
178
179	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0ePD[iPDSrc]);
180	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
181
182	/*
183	* A common case is the not-present error caused by lazy page table syncing.
184	*
185	* It is IMPORTANT that we weed out any access to non-present shadow PDEs here
186	* so we can safely assume that the shadow PT is present when calling SyncPage later.
187	*
188	* On failure, we ASSUME that SyncPT is out of memory or detected some kind
189	* of mapping conflict and defer to SyncCR3 in R3.
190	* (Again, we do NOT support access handlers for non-present guest pages.)
191	*
192	*/
193	# if PGM_WITH_PAGING(PGM_GST_TYPE)
194	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
195	# else
196	GSTPDE PdeSrc;
197	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
198	PdeSrc.n.u1Present = 1;
199	PdeSrc.n.u1Write = 1;
200	PdeSrc.n.u1Accessed = 1;
201	PdeSrc.n.u1User = 1;
202	# endif
203	if ( !(uErr & X86_TRAP_PF_P) /* not set means page not present instead of page protection violation */
204	&& !pPDDst->a[iPDDst].n.u1Present
205	&& PdeSrc.n.u1Present
206	)
207
208	{
209	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eSyncPT; });
210	STAM_PROFILE_START(&pVM->pgm.s.StatLazySyncPT, f);
211	LogFlow(("=>SyncPT %04x = %08x\n", iPDSrc, PdeSrc.au32[0]));
212	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, (RTGCUINTPTR)pvFault);
213	if (VBOX_SUCCESS(rc))
214	{
215	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
216	return rc;
217	}
218	Log(("SyncPT: %d failed!! rc=%d\n", iPDSrc, rc));
219	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync, right? */
220	STAM_PROFILE_STOP(&pVM->pgm.s.StatLazySyncPT, f);
221	return VINF_PGM_SYNC_CR3;
222	}
223
224	# if PGM_WITH_PAGING(PGM_GST_TYPE)
225	/*
226	* Check if this address is within any of our mappings.
227	*
228	* This is very fast and it's gonna save us a bit of effort below and prevent
229	* us from screwing ourself with MMIO2 pages which have a GC Mapping (VRam).
230	* (BTW, it's impossible to have physical access handlers in a mapping.)
231	*/
232	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
233	{
234	STAM_PROFILE_START(&pVM->pgm.s.StatMapping, a);
235	PPGMMAPPING pMapping = CTXALLSUFF(pVM->pgm.s.pMappings);
236	for ( ; pMapping; pMapping = CTXALLSUFF(pMapping->pNext))
237	{
238	if ((RTGCUINTPTR)pvFault < (RTGCUINTPTR)pMapping->GCPtr)
239	break;
240	if ((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pMapping->GCPtr < pMapping->cb)
241	{
242	/*
243	* The first thing we check is if we've got an undetected conflict.
244	*/
245	if (!pVM->pgm.s.fMappingsFixed)
246	{
247	unsigned iPT = pMapping->cb >> GST_PD_SHIFT;
248	while (iPT-- > 0)
249	if (pPDSrc->a[iPDSrc + iPT].n.u1Present)
250	{
251	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eConflicts);
252	Log(("Trap0e: Detected Conflict %VGv-%VGv\n", pMapping->GCPtr, pMapping->GCPtrLast));
253	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3); /** @todo no need to do global sync,right? */
254	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
255	return VINF_PGM_SYNC_CR3;
256	}
257	}
258
259	/*
260	* Check if the fault address is in a virtual page access handler range.
261	*/
262	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->HyperVirtHandlers, pvFault);
263	if ( pCur
264	&& (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
265	&& uErr & X86_TRAP_PF_RW)
266	{
267	# ifdef IN_GC
268	STAM_PROFILE_START(&pCur->Stat, h);
269	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
270	STAM_PROFILE_STOP(&pCur->Stat, h);
271	# else
272	AssertFailed();
273	rc = VINF_EM_RAW_EMULATE_INSTR; /* can't happen with VMX */
274	# endif
275	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eMapHandler);
276	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
277	return rc;
278	}
279
280	/*
281	* Pretend we're not here and let the guest handle the trap.
282	*/
283	TRPMSetErrorCode(pVM, uErr & ~X86_TRAP_PF_P);
284	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eMap);
285	LogFlow(("PGM: Mapping access -> route trap to recompiler!\n"));
286	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
287	return VINF_EM_RAW_GUEST_TRAP;
288	}
289	}
290	STAM_PROFILE_STOP(&pVM->pgm.s.StatMapping, a);
291	} /* pgmAreMappingsEnabled(&pVM->pgm.s) */
292	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
293
294	/*
295	* Check if this fault address is flagged for special treatment,
296	* which means we'll have to figure out the physical address and
297	* check flags associated with it.
298	*
299	* ASSUME that we can limit any special access handling to pages
300	* in page tables which the guest believes to be present.
301	*/
302	if (PdeSrc.n.u1Present)
303	{
304	RTGCPHYS GCPhys = NIL_RTGCPHYS;
305
306	# if PGM_WITH_PAGING(PGM_GST_TYPE)
307	uint32_t cr4 = CPUMGetGuestCR4(pVM);
308	if ( PdeSrc.b.u1Size
309	&& (cr4 & X86_CR4_PSE))
310	GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK)
311	\| ((RTGCPHYS)pvFault & (GST_BIG_PAGE_OFFSET_MASK ^ PAGE_OFFSET_MASK));
312	else
313	{
314	PGSTPT pPTSrc;
315	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
316	if (VBOX_SUCCESS(rc))
317	{
318	unsigned iPTESrc = ((RTGCUINTPTR)pvFault >> GST_PT_SHIFT) & GST_PT_MASK;
319	if (pPTSrc->a[iPTESrc].n.u1Present)
320	GCPhys = pPTSrc->a[iPTESrc].u & GST_PTE_PG_MASK;
321	}
322	}
323	# else
324	/* No paging so the fault address is the physical address */
325	GCPhys = (RTGCPHYS)((RTGCUINTPTR)pvFault & ~PAGE_OFFSET_MASK);
326	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
327
328	/*
329	* If we have a GC address we'll check if it has any flags set.
330	*/
331	if (GCPhys != NIL_RTGCPHYS)
332	{
333	STAM_PROFILE_START(&pVM->pgm.s.StatHandlers, b);
334
335	PPGMPAGE pPage;
336	rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
337	if (VBOX_SUCCESS(rc))
338	{
339	if (PGM_PAGE_HAS_ANY_HANDLERS(pPage))
340	{
341	if (PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage))
342	{
343	/*
344	* Physical page access handler.
345	*/
346	const RTGCPHYS GCPhysFault = GCPhys \| ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK);
347	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)RTAvlroGCPhysRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->PhysHandlers, GCPhysFault);
348	if (pCur)
349	{
350	# ifdef PGM_SYNC_N_PAGES
351	/*
352	* If the region is write protected and we got a page not present fault, then sync
353	* the pages. If the fault was caused by a read, then restart the instruction.
354	* In case of write access continue to the GC write handler.
355	*
356	* ASSUMES that there is only one handler per page or that they have similar write properties.
357	*/
358	if ( pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
359	&& !(uErr & X86_TRAP_PF_P))
360	{
361	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
362	if ( VBOX_FAILURE(rc)
363	\|\| !(uErr & X86_TRAP_PF_RW)
364	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE)
365	{
366	AssertRC(rc);
367	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
368	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
369	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
370	return rc;
371	}
372	}
373	# endif
374
375	AssertMsg( pCur->enmType != PGMPHYSHANDLERTYPE_PHYSICAL_WRITE
376	\|\| (pCur->enmType == PGMPHYSHANDLERTYPE_PHYSICAL_WRITE && (uErr & X86_TRAP_PF_RW)),
377	("Unexpected trap for physical handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
378
379	#if defined(IN_GC) \|\| defined(IN_RING0)
380	if (CTXALLSUFF(pCur->pfnHandler))
381	{
382	STAM_PROFILE_START(&pCur->Stat, h);
383	rc = pCur->CTXALLSUFF(pfnHandler)(pVM, uErr, pRegFrame, pvFault, GCPhysFault, CTXALLSUFF(pCur->pvUser));
384	STAM_PROFILE_STOP(&pCur->Stat, h);
385	}
386	else
387	#endif
388	rc = VINF_EM_RAW_EMULATE_INSTR;
389	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersPhysical);
390	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
391	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndPhys; });
392	return rc;
393	}
394	}
395	# if PGM_WITH_PAGING(PGM_GST_TYPE)
396	else
397	{
398	# ifdef PGM_SYNC_N_PAGES
399	/*
400	* If the region is write protected and we got a page not present fault, then sync
401	* the pages. If the fault was caused by a read, then restart the instruction.
402	* In case of write access continue to the GC write handler.
403	*/
404	if ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) < PGM_PAGE_HNDL_PHYS_STATE_ALL
405	&& !(uErr & X86_TRAP_PF_P))
406	{
407	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
408	if ( VBOX_FAILURE(rc)
409	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
410	\|\| !(uErr & X86_TRAP_PF_RW))
411	{
412	AssertRC(rc);
413	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
414	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
415	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndVirt; });
416	return rc;
417	}
418	}
419	# endif
420	/*
421	* Ok, it's an virtual page access handler.
422	*
423	* Since it's faster to search by address, we'll do that first
424	* and then retry by GCPhys if that fails.
425	*/
426	/** @todo r=bird: perhaps we should consider looking up by physical address directly now? */
427	/** @note r=svl: true, but lookup on virtual address should remain as a fallback as phys & virt trees might be out of sync, because the
428	* page was changed without us noticing it (not-present -> present without invlpg or mov cr3, xxx)
429	*/
430	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
431	if (pCur)
432	{
433	AssertMsg(!((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
434	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
435	\|\| !(uErr & X86_TRAP_PF_P)
436	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
437	("Unexpected trap for virtual handler: %VGv (phys=%VGp) HCPhys=%HGp uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
438
439	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
440	&& ( uErr & X86_TRAP_PF_RW
441	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
442	{
443	# ifdef IN_GC
444	STAM_PROFILE_START(&pCur->Stat, h);
445	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
446	STAM_PROFILE_STOP(&pCur->Stat, h);
447	# else
448	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
449	# endif
450	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtual);
451	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
452	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
453	return rc;
454	}
455	/* Unhandled part of a monitored page */
456	}
457	else
458	{
459	/* Check by physical address. */
460	PPGMVIRTHANDLER pCur;
461	unsigned iPage;
462	rc = pgmHandlerVirtualFindByPhysAddr(pVM, GCPhys + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK),
463	&pCur, &iPage);
464	Assert(VBOX_SUCCESS(rc) \|\| !pCur);
465	if ( pCur
466	&& ( uErr & X86_TRAP_PF_RW
467	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
468	{
469	Assert((pCur->aPhysToVirt[iPage].Core.Key & X86_PTE_PAE_PG_MASK) == GCPhys);
470	# ifdef IN_GC
471	RTGCUINTPTR off = (iPage << PAGE_SHIFT) + ((RTGCUINTPTR)pvFault & PAGE_OFFSET_MASK) - ((RTGCUINTPTR)pCur->GCPtr & PAGE_OFFSET_MASK);
472	Assert(off < pCur->cb);
473	STAM_PROFILE_START(&pCur->Stat, h);
474	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, off);
475	STAM_PROFILE_STOP(&pCur->Stat, h);
476	# else
477	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
478	# endif
479	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualByPhys);
480	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
481	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
482	return rc;
483	}
484	}
485	}
486	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
487
488	/*
489	* There is a handled area of the page, but this fault doesn't belong to it.
490	* We must emulate the instruction.
491	*
492	* To avoid crashing (non-fatal) in the interpreter and go back to the recompiler
493	* we first check if this was a page-not-present fault for a page with only
494	* write access handlers. Restart the instruction if it wasn't a write access.
495	*/
496	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersUnhandled);
497
498	if ( !PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
499	&& !(uErr & X86_TRAP_PF_P))
500	{
501	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
502	if ( VBOX_FAILURE(rc)
503	\|\| rc == VINF_PGM_SYNCPAGE_MODIFIED_PDE
504	\|\| !(uErr & X86_TRAP_PF_RW))
505	{
506	AssertRC(rc);
507	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersOutOfSync);
508	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
509	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncHndPhys; });
510	return rc;
511	}
512	}
513
514	/** @todo This particular case can cause quite a lot of overhead. E.g. early stage of kernel booting in Ubuntu 6.06
515	* It's writing to an unhandled part of the LDT page several million times.
516	*/
517	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
518	LogFlow(("PGM: PGMInterpretInstruction -> rc=%d HCPhys=%RHp%s%s\n",
519	rc, pPage->HCPhys,
520	PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) ? " phys" : "",
521	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) ? " virt" : ""));
522	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
523	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndUnhandled; });
524	return rc;
525	} /* if any kind of handler */
526
527	# if PGM_WITH_PAGING(PGM_GST_TYPE)
528	if (uErr & X86_TRAP_PF_P)
529	{
530	/*
531	* The page isn't marked, but it might still be monitored by a virtual page access handler.
532	* (ASSUMES no temporary disabling of virtual handlers.)
533	*/
534	/** @todo r=bird: Since the purpose is to catch out of sync pages with virtual handler(s) here,
535	* we should correct both the shadow page table and physical memory flags, and not only check for
536	* accesses within the handler region but for access to pages with virtual handlers. */
537	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)RTAvlroGCPtrRangeGet(&CTXSUFF(pVM->pgm.s.pTrees)->VirtHandlers, pvFault);
538	if (pCur)
539	{
540	AssertMsg( !((RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb)
541	\|\| ( pCur->enmType != PGMVIRTHANDLERTYPE_WRITE
542	\|\| !(uErr & X86_TRAP_PF_P)
543	\|\| (pCur->enmType == PGMVIRTHANDLERTYPE_WRITE && (uErr & X86_TRAP_PF_RW))),
544	("Unexpected trap for virtual handler: %08X (phys=%08x) HCPhys=%X uErr=%X, enum=%d\n", pvFault, GCPhys, pPage->HCPhys, uErr, pCur->enmType));
545
546	if ( (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr < pCur->cb
547	&& ( uErr & X86_TRAP_PF_RW
548	\|\| pCur->enmType != PGMVIRTHANDLERTYPE_WRITE ) )
549	{
550	# ifdef IN_GC
551	STAM_PROFILE_START(&pCur->Stat, h);
552	rc = CTXSUFF(pCur->pfnHandler)(pVM, uErr, pRegFrame, pvFault, pCur->GCPtr, (RTGCUINTPTR)pvFault - (RTGCUINTPTR)pCur->GCPtr);
553	STAM_PROFILE_STOP(&pCur->Stat, h);
554	# else
555	rc = VINF_EM_RAW_EMULATE_INSTR; /** @todo for VMX */
556	# endif
557	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersVirtualUnmarked);
558	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
559	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eHndVirt; });
560	return rc;
561	}
562	}
563	}
564	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
565	}
566	else
567	{
568	/* When the guest accesses invalid physical memory (e.g. probing of RAM or accessing a remapped MMIO range), then we'll fall
569	* back to the recompiler to emulate the instruction.
570	*/
571	LogFlow(("pgmPhysGetPageEx %VGp failed with %Vrc\n", GCPhys, rc));
572	STAM_COUNTER_INC(&pVM->pgm.s.StatHandlersInvalid);
573	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
574	return VINF_EM_RAW_EMULATE_INSTR;
575	}
576
577	STAM_PROFILE_STOP(&pVM->pgm.s.StatHandlers, b);
578
579	# ifdef PGM_OUT_OF_SYNC_IN_GC
580	/*
581	* We are here only if page is present in Guest page tables and trap is not handled
582	* by our handlers.
583	* Check it for page out-of-sync situation.
584	*/
585	STAM_PROFILE_START(&pVM->pgm.s.StatOutOfSync, c);
586
587	if (!(uErr & X86_TRAP_PF_P))
588	{
589	/*
590	* Page is not present in our page tables.
591	* Try to sync it!
592	* BTW, fPageShw is invalid in this branch!
593	*/
594	if (uErr & X86_TRAP_PF_US)
595	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
596	else /* supervisor */
597	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
598
599	# if defined(LOG_ENABLED) && !defined(IN_RING0)
600	RTGCPHYS GCPhys;
601	uint64_t fPageGst;
602	PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
603	Log(("Page out of sync: %p eip=%08x PdeSrc.n.u1User=%d fPageGst=%08llx GCPhys=%VGp scan=%d\n",
604	pvFault, pRegFrame->eip, PdeSrc.n.u1User, fPageGst, GCPhys, CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)));
605	# endif /* LOG_ENABLED */
606
607	# if PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0)
608	if (CPUMGetGuestCPL(pVM, pRegFrame) == 0)
609	{
610	uint64_t fPageGst;
611	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
612	if ( VBOX_SUCCESS(rc)
613	&& !(fPageGst & X86_PTE_US))
614	{
615	/* Note: can't check for X86_TRAP_ID bit, because that requires execute disable support on the CPU */
616	if ( pvFault == (RTGCPTR)pRegFrame->eip
617	\|\| (RTGCUINTPTR)pvFault - pRegFrame->eip < 8 /* instruction crossing a page boundary */
618	# ifdef CSAM_DETECT_NEW_CODE_PAGES
619	\|\| ( !PATMIsPatchGCAddr(pVM, (RTGCPTR)pRegFrame->eip)
620	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)pRegFrame->eip)) /* any new code we encounter here */
621	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
622	)
623	{
624	LogFlow(("CSAMExecFault %VGv\n", pRegFrame->eip));
625	rc = CSAMExecFault(pVM, (RTGCPTR)pRegFrame->eip);
626	if (rc != VINF_SUCCESS)
627	{
628	/*
629	* CSAM needs to perform a job in ring 3.
630	*
631	* Sync the page before going to the host context; otherwise we'll end up in a loop if
632	* CSAM fails (e.g. instruction crosses a page boundary and the next page is not present)
633	*/
634	LogFlow(("CSAM ring 3 job\n"));
635	int rc2 = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
636	AssertRC(rc2);
637
638	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
639	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eCSAM; });
640	return rc;
641	}
642	}
643	# ifdef CSAM_DETECT_NEW_CODE_PAGES
644	else
645	if ( uErr == X86_TRAP_PF_RW
646	&& pRegFrame->ecx >= 0x100 /* early check for movswd count */
647	&& pRegFrame->ecx < 0x10000
648	)
649	{
650	/* In case of a write to a non-present supervisor shadow page, we'll take special precautions
651	* to detect loading of new code pages.
652	*/
653
654	/*
655	* Decode the instruction.
656	*/
657	RTGCPTR PC;
658	rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &PC);
659	if (rc == VINF_SUCCESS)
660	{
661	DISCPUSTATE Cpu;
662	uint32_t cbOp;
663	rc = EMInterpretDisasOneEx(pVM, (RTGCUINTPTR)PC, pRegFrame, &Cpu, &cbOp);
664
665	/* For now we'll restrict this to rep movsw/d instructions */
666	if ( rc == VINF_SUCCESS
667	&& Cpu.pCurInstr->opcode == OP_MOVSWD
668	&& (Cpu.prefix & PREFIX_REP))
669	{
670	CSAMMarkPossibleCodePage(pVM, pvFault);
671	}
672	}
673	}
674	# endif /* CSAM_DETECT_NEW_CODE_PAGES */
675
676	/*
677	* Mark this page as safe.
678	*/
679	/** @todo not correct for pages that contain both code and data!! */
680	Log2(("CSAMMarkPage %p; scanned=%d\n", pvFault, true));
681	CSAMMarkPage(pVM, pvFault, true);
682	}
683	}
684	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) && !defined(IN_RING0) */
685	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, PGM_SYNC_NR_PAGES, uErr);
686	if (VBOX_SUCCESS(rc))
687	{
688	/* The page was successfully synced, return to the guest. */
689	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
690	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSync; });
691	return VINF_SUCCESS;
692	}
693	}
694	else
695	{
696	/*
697	* A side effect of not flushing global PDEs are out of sync pages due
698	* to physical monitored regions, that are no longer valid.
699	* Assume for now it only applies to the read/write flag
700	*/
701	if (VBOX_SUCCESS(rc) && (uErr & X86_TRAP_PF_RW))
702	{
703	if (uErr & X86_TRAP_PF_US)
704	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
705	else /* supervisor */
706	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
707
708
709	/*
710	* Note: Do NOT use PGM_SYNC_NR_PAGES here. That only works if the page is not present, which is not true in this case.
711	*/
712	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)pvFault, 1, uErr);
713	if (VBOX_SUCCESS(rc))
714	{
715	/*
716	* Page was successfully synced, return to guest.
717	*/
718	# ifdef VBOX_STRICT
719	RTGCPHYS GCPhys;
720	uint64_t fPageGst;
721	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, &GCPhys);
722	Assert(VBOX_SUCCESS(rc) && fPageGst & X86_PTE_RW);
723	LogFlow(("Obsolete physical monitor page out of sync %VGv - phys %VGp flags=%08llx\n", pvFault, GCPhys, (uint64_t)fPageGst));
724
725	uint64_t fPageShw;
726	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
727	Assert(VBOX_SUCCESS(rc) && fPageShw & X86_PTE_RW);
728	# endif /* VBOX_STRICT */
729	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
730	STAM_STATS({ pVM->pgm.s.CTXSUFF(pStatTrap0eAttribution) = &pVM->pgm.s.StatTrap0eOutOfSyncObsHnd; });
731	return VINF_SUCCESS;
732	}
733
734	/* Check to see if we need to emulate the instruction as X86_CR0_WP has been cleared. */
735	if ( CPUMGetGuestCPL(pVM, pRegFrame) == 0
736	&& ((CPUMGetGuestCR0(pVM) & (X86_CR0_WP\|X86_CR0_PG)) == X86_CR0_PG)
737	&& (uErr & (X86_TRAP_PF_RW \| X86_TRAP_PF_P)) == (X86_TRAP_PF_RW \| X86_TRAP_PF_P))
738	{
739	uint64_t fPageGst;
740	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
741	if ( VBOX_SUCCESS(rc)
742	&& !(fPageGst & X86_PTE_RW))
743	{
744	rc = PGMInterpretInstruction(pVM, pRegFrame, pvFault);
745	if (VBOX_SUCCESS(rc))
746	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulGC);
747	else
748	STAM_COUNTER_INC(&pVM->pgm.s.StatTrap0eWPEmulR3);
749	return rc;
750	}
751	else
752	AssertMsgFailed(("Unexpected r/w page %x flag=%x\n", pvFault, (uint32_t)fPageGst));
753	}
754
755	}
756
757	# if PGM_WITH_PAGING(PGM_GST_TYPE)
758	# ifdef VBOX_STRICT
759	/*
760	* Check for VMM page flags vs. Guest page flags consistency.
761	* Currently only for debug purposes.
762	*/
763	if (VBOX_SUCCESS(rc))
764	{
765	/* Get guest page flags. */
766	uint64_t fPageGst;
767	rc = PGMGstGetPage(pVM, pvFault, &fPageGst, NULL);
768	if (VBOX_SUCCESS(rc))
769	{
770	uint64_t fPageShw;
771	rc = PGMShwGetPage(pVM, pvFault, &fPageShw, NULL);
772
773	/*
774	* Compare page flags.
775	* Note: we have AVL, A, D bits desynched.
776	*/
777	AssertMsg((fPageShw & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)) == (fPageGst & ~(X86_PTE_A \| X86_PTE_D \| X86_PTE_AVL_MASK)),
778	("Page flags mismatch! pvFault=%p GCPhys=%VGp fPageShw=%08llx fPageGst=%08llx\n", pvFault, GCPhys, fPageShw, fPageGst));
779	}
780	else
781	AssertMsgFailed(("PGMGstGetPage rc=%Vrc\n", rc));
782	}
783	else
784	AssertMsgFailed(("PGMGCGetPage rc=%Vrc\n", rc));
785	# endif /* VBOX_STRICT */
786	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
787	}
788	STAM_PROFILE_STOP(&pVM->pgm.s.StatOutOfSync, c);
789	# endif /* PGM_OUT_OF_SYNC_IN_GC */
790	}
791	else
792	{
793	/*
794	* Page not present in Guest OS or invalid page table address.
795	* This is potential virtual page access handler food.
796	*
797	* For the present we'll say that our access handlers don't
798	* work for this case - we've already discarded the page table
799	* not present case which is identical to this.
800	*
801	* When we perchance find we need this, we will probably have AVL
802	* trees (offset based) to operate on and we can measure their speed
803	* agains mapping a page table and probably rearrange this handling
804	* a bit. (Like, searching virtual ranges before checking the
805	* physical address.)
806	*/
807	}
808	}
809
810
811	# if PGM_WITH_PAGING(PGM_GST_TYPE)
812	/*
813	* Conclusion, this is a guest trap.
814	*/
815	LogFlow(("PGM: Unhandled #PF -> route trap to recompiler!\n"));
816	STAM_COUNTER_INC(&pVM->pgm.s.StatGCTrap0eUnhandled);
817	return VINF_EM_RAW_GUEST_TRAP;
818	# else
819	/* present, but not a monitored page; perhaps the guest is probing physical memory */
820	return VINF_EM_RAW_EMULATE_INSTR;
821	# endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
822
823
824	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
825
826	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
827	return VERR_INTERNAL_ERROR;
828	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
829	}
830
831
832	/**
833	* Emulation of the invlpg instruction.
834	*
835	*
836	* @returns VBox status code.
837	*
838	* @param pVM VM handle.
839	* @param GCPtrPage Page to invalidate.
840	*
841	* @remark ASSUMES that the guest is updating before invalidating. This order
842	* isn't required by the CPU, so this is speculative and could cause
843	* trouble.
844	*
845	* @todo Flush page or page directory only if necessary!
846	* @todo Add a #define for simply invalidating the page.
847	*/
848	PGM_BTH_DECL(int, InvalidatePage)(PVM pVM, RTGCUINTPTR GCPtrPage)
849	{
850	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
851	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
852
853	LogFlow(("InvalidatePage %x\n", GCPtrPage));
854	/*
855	* Get the shadow PD entry and skip out if this PD isn't present.
856	* (Guessing that it is frequent for a shadow PDE to not be present, do this first.)
857	*/
858	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
859	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
860	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
861	# else
862	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs[0])->a[iPDDst];
863	# endif
864	const SHWPDE PdeDst = *pPdeDst;
865	if (!PdeDst.n.u1Present)
866	{
867	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePageSkipped));
868	return VINF_SUCCESS;
869	}
870
871	/*
872	* Get the guest PD entry and calc big page.
873	*/
874	# if PGM_GST_TYPE == PGM_TYPE_32BIT
875	PX86PD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
876	const unsigned iPDSrc = GCPtrPage >> GST_PD_SHIFT;
877	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
878	# else /* PAE */
879	unsigned iPDSrc;
880	PX86PDPAE pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
881	GSTPDE PdeSrc;
882
883	if (pPDSrc)
884	PdeSrc = pPDSrc->a[iPDSrc];
885	else
886	PdeSrc.u = 0;
887	# endif
888
889	const uint32_t cr4 = CPUMGetGuestCR4(pVM);
890	const bool fIsBigPage = PdeSrc.b.u1Size && (cr4 & X86_CR4_PSE);
891
892	# ifdef IN_RING3
893	/*
894	* If a CR3 Sync is pending we may ignore the invalidate page operation
895	* depending on the kind of sync and if it's a global page or not.
896	* This doesn't make sense in GC/R0 so we'll skip it entirely there.
897	*/
898	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
899	if ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3)
900	\|\| ( VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL)
901	&& fIsBigPage
902	&& PdeSrc.b.u1Global
903	&& (cr4 & X86_CR4_PGE)
904	)
905	)
906	# else
907	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_SYNC_CR3 \| VM_FF_PGM_SYNC_CR3_NON_GLOBAL) )
908	# endif
909	{
910	STAM_COUNTER_INC(&pVM->pgm.s.StatHCInvalidatePageSkipped);
911	return VINF_SUCCESS;
912	}
913	# endif /* IN_RING3 */
914
915
916	/*
917	* Deal with the Guest PDE.
918	*/
919	int rc = VINF_SUCCESS;
920	if (PdeSrc.n.u1Present)
921	{
922	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
923	{
924	/*
925	* Conflict - Let SyncPT deal with it to avoid duplicate code.
926	*/
927	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
928	Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
929	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
930	}
931	else if ( PdeSrc.n.u1User != PdeDst.n.u1User
932	\|\| (!PdeSrc.n.u1Write && PdeDst.n.u1Write))
933	{
934	/*
935	* Mark not present so we can resync the PDE when it's used.
936	*/
937	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
938	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
939	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
940	pPdeDst->u = 0;
941	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
942	PGM_INVL_GUEST_TLBS();
943	}
944	# ifdef PGM_SYNC_ACCESSED_BIT
945	else if (!PdeSrc.n.u1Accessed)
946	{
947	/*
948	* Mark not present so we can set the accessed bit.
949	*/
950	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
951	pPdeDst->u = 0;
952	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
953	PGM_INVL_GUEST_TLBS();
954	}
955	# endif
956	else if (!fIsBigPage)
957	{
958	/*
959	* 4KB - page.
960	*/
961	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
962	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
963	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
964	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
965	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
966	# endif
967	if (pShwPage->GCPhys == GCPhys)
968	{
969	# if 0 /* likely cause of a major performance regression; must be SyncPageWorkerTrackDeref then */
970	const unsigned iPTEDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
971	PSHWPT pPT = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
972	if (pPT->a[iPTEDst].n.u1Present)
973	{
974	# ifdef PGMPOOL_WITH_USER_TRACKING
975	/* This is very unlikely with caching/monitoring enabled. */
976	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPT->a[iPTEDst].u & SHW_PTE_PG_MASK);
977	# endif
978	pPT->a[iPTEDst].u = 0;
979	}
980	# else /* Syncing it here isn't 100% safe and it's probably not worth spending time syncing it. */
981	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
982	if (VBOX_SUCCESS(rc))
983	rc = VINF_SUCCESS;
984	# endif
985	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4KBPages));
986	PGM_INVL_PG(GCPtrPage);
987	}
988	else
989	{
990	/*
991	* The page table address changed.
992	*/
993	LogFlow(("InvalidatePage: Out-of-sync at %VGp PdeSrc=%RX64 PdeDst=%RX64 ShwGCPhys=%VGp iPDDst=%#x\n",
994	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u, pShwPage->GCPhys, iPDDst));
995	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
996	pPdeDst->u = 0;
997	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
998	PGM_INVL_GUEST_TLBS();
999	}
1000	}
1001	else
1002	{
1003	/*
1004	* 2/4MB - page.
1005	*/
1006	/* Before freeing the page, check if anything really changed. */
1007	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1008	RTGCPHYS GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1009	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1010	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1011	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1012	# endif
1013	if ( pShwPage->GCPhys == GCPhys
1014	&& pShwPage->enmKind == BTH_PGMPOOLKIND_PT_FOR_BIG)
1015	{
1016	/* ASSUMES a the given bits are identical for 4M and normal PDEs */
1017	/** @todo PAT */
1018	# ifdef PGM_SYNC_DIRTY_BIT
1019	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1020	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1021	&& ( PdeSrc.b.u1Dirty /** @todo rainy day: What about read-only 4M pages? not very common, but still... */
1022	\|\| (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)))
1023	# else
1024	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD))
1025	== (PdeDst.u & (X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_PWT \| X86_PDE_PCD)))
1026	# endif
1027	{
1028	LogFlow(("Skipping flush for big page containing %VGv (PD=%X .u=%VX64)-> nothing has changed!\n", GCPtrPage, iPDSrc, PdeSrc.u));
1029	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPagesSkip));
1030	return VINF_SUCCESS;
1031	}
1032	}
1033
1034	/*
1035	* Ok, the page table is present and it's been changed in the guest.
1036	* If we're in host context, we'll just mark it as not present taking the lazy approach.
1037	* We could do this for some flushes in GC too, but we need an algorithm for
1038	* deciding which 4MB pages containing code likely to be executed very soon.
1039	*/
1040	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1041	pPdeDst->u = 0;
1042	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePage4MBPages));
1043	PGM_INVL_BIG_PG(GCPtrPage);
1044	}
1045	}
1046	else
1047	{
1048	/*
1049	* Page directory is not present, mark shadow PDE not present.
1050	*/
1051	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
1052	{
1053	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1054	pPdeDst->u = 0;
1055	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
1056	PGM_INVL_PG(GCPtrPage);
1057	}
1058	else
1059	{
1060	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
1061	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDMappings));
1062	}
1063	}
1064
1065	return rc;
1066
1067	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
1068	//# error not implemented
1069	return VERR_INTERNAL_ERROR;
1070
1071	#else /* guest real and protected mode */
1072	/* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
1073	return VINF_SUCCESS;
1074	#endif
1075	}
1076
1077
1078	#ifdef PGMPOOL_WITH_USER_TRACKING
1079	/**
1080	* Update the tracking of shadowed pages.
1081	*
1082	* @param pVM The VM handle.
1083	* @param pShwPage The shadow page.
1084	* @param HCPhys The physical page we is being dereferenced.
1085	*/
1086	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackDeref)(PVM pVM, PPGMPOOLPAGE pShwPage, RTHCPHYS HCPhys)
1087	{
1088	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1089	STAM_PROFILE_START(&pVM->pgm.s.StatTrackDeref, a);
1090	LogFlow(("SyncPageWorkerTrackDeref: Damn HCPhys=%VHp pShwPage->idx=%#x!!!\n", HCPhys, pShwPage->idx));
1091
1092	/** @todo If this turns out to be a bottle neck (very likely) two things can be done:
1093	* 1. have a medium sized HCPhys -> GCPhys TLB (hash?)
1094	* 2. write protect all shadowed pages. I.e. implement caching.
1095	*/
1096	/*
1097	* Find the guest address.
1098	*/
1099	for (PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
1100	pRam;
1101	pRam = CTXALLSUFF(pRam->pNext))
1102	{
1103	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1104	while (iPage-- > 0)
1105	{
1106	if (PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) == HCPhys)
1107	{
1108	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
1109	pgmTrackDerefGCPhys(pPool, pShwPage, &pRam->aPages[iPage]);
1110	pShwPage->cPresent--;
1111	pPool->cPresent--;
1112	STAM_PROFILE_STOP(&pVM->pgm.s.StatTrackDeref, a);
1113	return;
1114	}
1115	}
1116	}
1117
1118	for (;;)
1119	AssertReleaseMsgFailed(("HCPhys=%VHp wasn't found!\n", HCPhys));
1120	# else /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1121	pShwPage->cPresent--;
1122	pVM->pgm.s.CTXSUFF(pPool)->cPresent--;
1123	# endif /* !PGMPOOL_WITH_GCPHYS_TRACKING */
1124	}
1125
1126
1127	/**
1128	* Update the tracking of shadowed pages.
1129	*
1130	* @param pVM The VM handle.
1131	* @param pShwPage The shadow page.
1132	* @param u16 The top 16-bit of the pPage->HCPhys.
1133	* @param pPage Pointer to the guest page. this will be modified.
1134	* @param iPTDst The index into the shadow table.
1135	*/
1136	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorkerTrackAddref)(PVM pVM, PPGMPOOLPAGE pShwPage, uint16_t u16, PPGMPAGE pPage, const unsigned iPTDst)
1137	{
1138	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1139	/*
1140	* We're making certain assumptions about the placement of cRef and idx.
1141	*/
1142	Assert(MM_RAM_FLAGS_IDX_SHIFT == 48);
1143	Assert(MM_RAM_FLAGS_CREFS_SHIFT > MM_RAM_FLAGS_IDX_SHIFT);
1144
1145	/*
1146	* Just deal with the simple first time here.
1147	*/
1148	if (!u16)
1149	{
1150	STAM_COUNTER_INC(&pVM->pgm.s.StatTrackVirgin);
1151	u16 = (1 << (MM_RAM_FLAGS_CREFS_SHIFT - MM_RAM_FLAGS_IDX_SHIFT)) \| pShwPage->idx;
1152	}
1153	else
1154	u16 = pgmPoolTrackPhysExtAddref(pVM, u16, pShwPage->idx);
1155
1156	/* write back, trying to be clever... */
1157	Log2(("SyncPageWorkerTrackAddRef: u16=%#x pPage->HCPhys=%VHp->%VHp iPTDst=%#x\n",
1158	u16, pPage->HCPhys, (pPage->HCPhys & MM_RAM_FLAGS_NO_REFS_MASK) \| ((uint64_t)u16 << MM_RAM_FLAGS_CREFS_SHIFT), iPTDst));
1159	((uint16_t )&pPage->HCPhys + 3) = u16; /** @todo PAGE FLAGS */
1160	# endif /* PGMPOOL_WITH_GCPHYS_TRACKING */
1161
1162	/* update statistics. */
1163	pVM->pgm.s.CTXSUFF(pPool)->cPresent++;
1164	pShwPage->cPresent++;
1165	if (pShwPage->iFirstPresent > iPTDst)
1166	pShwPage->iFirstPresent = iPTDst;
1167	}
1168	#endif /* PGMPOOL_WITH_USER_TRACKING */
1169
1170
1171	/**
1172	* Creates a 4K shadow page for a guest page.
1173	*
1174	* For 4M pages the caller must convert the PDE4M to a PTE, this includes adjusting the
1175	* physical address. The PdeSrc argument only the flags are used. No page structured
1176	* will be mapped in this function.
1177	*
1178	* @param pVM VM handle.
1179	* @param pPteDst Destination page table entry.
1180	* @param PdeSrc Source page directory entry (i.e. Guest OS page directory entry).
1181	* Can safely assume that only the flags are being used.
1182	* @param PteSrc Source page table entry (i.e. Guest OS page table entry).
1183	* @param pShwPage Pointer to the shadow page.
1184	* @param iPTDst The index into the shadow table.
1185	*
1186	* @remark Not used for 2/4MB pages!
1187	*/
1188	DECLINLINE(void) PGM_BTH_NAME(SyncPageWorker)(PVM pVM, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc, PPGMPOOLPAGE pShwPage, unsigned iPTDst)
1189	{
1190	if (PteSrc.n.u1Present)
1191	{
1192	/*
1193	* Find the ram range.
1194	*/
1195	PPGMPAGE pPage;
1196	int rc = pgmPhysGetPageEx(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK, &pPage);
1197	if (VBOX_SUCCESS(rc))
1198	{
1199	/** @todo investiage PWT, PCD and PAT. */
1200	/*
1201	* Make page table entry.
1202	*/
1203	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo FLAGS */
1204	SHWPTE PteDst;
1205	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1206	{
1207	/** @todo r=bird: Are we actually handling dirty and access bits for pages with access handlers correctly? No. */
1208	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1209	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1210	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1211	else
1212	{
1213	LogFlow(("SyncPageWorker: monitored page (%VGp) -> mark not present\n", HCPhys));
1214	PteDst.u = 0;
1215	}
1216	/** @todo count these two kinds. */
1217	}
1218	else
1219	{
1220	#ifdef PGM_SYNC_DIRTY_BIT
1221	# ifdef PGM_SYNC_ACCESSED_BIT
1222	/*
1223	* If the page or page directory entry is not marked accessed,
1224	* we mark the page not present.
1225	*/
1226	if (!PteSrc.n.u1Accessed \|\| !PdeSrc.n.u1Accessed)
1227	{
1228	LogFlow(("SyncPageWorker: page and or page directory not accessed -> mark not present\n"));
1229	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,AccessedPage));
1230	PteDst.u = 0;
1231	}
1232	else
1233	# endif
1234	/*
1235	* If the page is not flagged as dirty and is writable, then make it read-only, so we can set the dirty bit
1236	* when the page is modified.
1237	*/
1238	if (!PteSrc.n.u1Dirty && (PdeSrc.n.u1Write & PteSrc.n.u1Write))
1239	{
1240	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPage));
1241	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT \| X86_PTE_RW))
1242	\| (HCPhys & X86_PTE_PAE_PG_MASK)
1243	\| PGM_PTFLAGS_TRACK_DIRTY;
1244	}
1245	else
1246	{
1247	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageSkipped));
1248	PteDst.u = (PteSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1249	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1250	}
1251	#endif
1252	}
1253
1254	#ifdef PGMPOOL_WITH_USER_TRACKING
1255	/*
1256	* Keep user track up to date.
1257	*/
1258	if (PteDst.n.u1Present)
1259	{
1260	if (!pPteDst->n.u1Present)
1261	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1262	else if ((pPteDst->u & SHW_PTE_PG_MASK) != (PteDst.u & SHW_PTE_PG_MASK))
1263	{
1264	Log2(("SyncPageWorker: deref! *pPteDst=%RX64 PteDst=%RX64\n", (uint64_t)pPteDst->u, (uint64_t)PteDst.u));
1265	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1266	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1267	}
1268	}
1269	else if (pPteDst->n.u1Present)
1270	{
1271	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1272	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1273	}
1274	#endif /* PGMPOOL_WITH_USER_TRACKING */
1275
1276	/*
1277	* Update statistics and commit the entry.
1278	*/
1279	if (!PteSrc.n.u1Global)
1280	pShwPage->fSeenNonGlobal = true;
1281	*pPteDst = PteDst;
1282	}
1283	/* else MMIO or invalid page, we must handle them manually in the #PF handler. */
1284	/** @todo count these. */
1285	}
1286	else
1287	{
1288	/*
1289	* Page not-present.
1290	*/
1291	LogFlow(("SyncPageWorker: page not present in Pte\n"));
1292	#ifdef PGMPOOL_WITH_USER_TRACKING
1293	/* Keep user track up to date. */
1294	if (pPteDst->n.u1Present)
1295	{
1296	Log2(("SyncPageWorker: deref! *pPteDst=%RX64\n", (uint64_t)pPteDst->u));
1297	PGM_BTH_NAME(SyncPageWorkerTrackDeref)(pVM, pShwPage, pPteDst->u & SHW_PTE_PG_MASK);
1298	}
1299	#endif /* PGMPOOL_WITH_USER_TRACKING */
1300	pPteDst->u = 0;
1301	/** @todo count these. */
1302	}
1303	}
1304
1305
1306	/**
1307	* Syncs a guest OS page.
1308	*
1309	* There are no conflicts at this point, neither is there any need for
1310	* page table allocations.
1311	*
1312	* @returns VBox status code.
1313	* @returns VINF_PGM_SYNCPAGE_MODIFIED_PDE if it modifies the PDE in any way.
1314	* @param pVM VM handle.
1315	* @param PdeSrc Page directory entry of the guest.
1316	* @param GCPtrPage Guest context page address.
1317	* @param cPages Number of pages to sync (PGM_SYNC_N_PAGES) (default=1).
1318	* @param uErr Fault error (X86_TRAP_PF_*).
1319	*/
1320	PGM_BTH_DECL(int, SyncPage)(PVM pVM, GSTPDE PdeSrc, RTGCUINTPTR GCPtrPage, unsigned cPages, unsigned uErr)
1321	{
1322	LogFlow(("SyncPage: GCPtrPage=%VGv cPages=%d uErr=%#x\n", GCPtrPage, cPages, uErr));
1323
1324	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1325	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1326
1327	# if PGM_WITH_NX(PGM_GST_TYPE)
1328	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1329	# endif
1330
1331	/*
1332	* Assert preconditions.
1333	*/
1334	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
1335	Assert(PdeSrc.n.u1Present);
1336	Assert(cPages);
1337
1338	/*
1339	* Get the shadow PDE, find the shadow page table in the pool.
1340	*/
1341	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1342	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1343	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1344	# else /* PAE */
1345	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1346	# endif
1347	Assert(PdeDst.n.u1Present);
1348	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1349
1350	/*
1351	* Check that the page is present and that the shadow PDE isn't out of sync.
1352	*/
1353	const bool fBigPage = PdeSrc.b.u1Size && (CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1354	RTGCPHYS GCPhys;
1355	if (!fBigPage)
1356	{
1357	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
1358	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1359	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1360	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE/2);
1361	# endif
1362	}
1363	else
1364	{
1365	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
1366	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1367	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
1368	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
1369	# endif
1370	}
1371	if ( pShwPage->GCPhys == GCPhys
1372	&& PdeSrc.n.u1Present
1373	&& (PdeSrc.n.u1User == PdeDst.n.u1User)
1374	&& (PdeSrc.n.u1Write == PdeDst.n.u1Write \|\| !PdeDst.n.u1Write)
1375	# if PGM_WITH_NX(PGM_GST_TYPE)
1376	&& (!fNoExecuteBitValid \|\| PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute)
1377	# endif
1378	)
1379	{
1380	# ifdef PGM_SYNC_ACCESSED_BIT
1381	/*
1382	* Check that the PDE is marked accessed already.
1383	* Since we set the accessed bit before getting here on a #PF, this
1384	* check is only meant for dealing with non-#PF'ing paths.
1385	*/
1386	if (PdeSrc.n.u1Accessed)
1387	# endif
1388	{
1389	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1390	if (!fBigPage)
1391	{
1392	/*
1393	* 4KB Page - Map the guest page table.
1394	*/
1395	PGSTPT pPTSrc;
1396	int rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
1397	if (VBOX_SUCCESS(rc))
1398	{
1399	# ifdef PGM_SYNC_N_PAGES
1400	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1401	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1402	{
1403	/*
1404	* This code path is currently only taken when the caller is PGMTrap0eHandler
1405	* for non-present pages!
1406	*
1407	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1408	* deal with locality.
1409	*/
1410	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1411	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
1412	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1413	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1414	# else
1415	const unsigned offPTSrc = 0;
1416	# endif
1417	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1418	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1419	iPTDst = 0;
1420	else
1421	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1422	for (; iPTDst < iPTDstEnd; iPTDst++)
1423	{
1424	if (!pPTDst->a[iPTDst].n.u1Present)
1425	{
1426	GSTPTE PteSrc = pPTSrc->a[offPTSrc + iPTDst];
1427	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1428	NOREF(GCPtrCurPage);
1429	#ifndef IN_RING0
1430	/*
1431	* Assuming kernel code will be marked as supervisor - and not as user level
1432	* and executed using a conforming code selector - And marked as readonly.
1433	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
1434	*/
1435	PPGMPAGE pPage;
1436	if ( ((PdeSrc.u & PteSrc.u) & (X86_PTE_RW \| X86_PTE_US))
1437	\|\| iPTDst == ((GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK) /* always sync GCPtrPage */
1438	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)GCPtrCurPage)
1439	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
1440	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1441	)
1442	#endif /* else: CSAM not active */
1443	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1444	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1445	GCPtrCurPage, PteSrc.n.u1Present,
1446	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1447	PteSrc.n.u1User & PdeSrc.n.u1User,
1448	(uint64_t)PteSrc.u,
1449	(uint64_t)pPTDst->a[iPTDst].u,
1450	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1451	}
1452	}
1453	}
1454	else
1455	# endif /* PGM_SYNC_N_PAGES */
1456	{
1457	const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
1458	GSTPTE PteSrc = pPTSrc->a[iPTSrc];
1459	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1460	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1461	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1462	GCPtrPage, PteSrc.n.u1Present,
1463	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1464	PteSrc.n.u1User & PdeSrc.n.u1User,
1465	(uint64_t)PteSrc.u,
1466	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1467	}
1468	}
1469	else /* MMIO or invalid page: emulated in #PF handler. */
1470	{
1471	LogFlow(("PGM_GCPHYS_2_PTR %VGp failed with %Vrc\n", GCPhys, rc));
1472	Assert(!pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK].n.u1Present);
1473	}
1474	}
1475	else
1476	{
1477	/*
1478	* 4/2MB page - lazy syncing shadow 4K pages.
1479	* (There are many causes of getting here, it's no longer only CSAM.)
1480	*/
1481	/* Calculate the GC physical address of this 4KB shadow page. */
1482	RTGCPHYS GCPhys = (PdeSrc.u & GST_PDE_BIG_PG_MASK) \| ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
1483	/* Find ram range. */
1484	PPGMPAGE pPage;
1485	int rc = pgmPhysGetPageEx(&pVM->pgm.s, GCPhys, &pPage);
1486	if (VBOX_SUCCESS(rc))
1487	{
1488	/*
1489	* Make shadow PTE entry.
1490	*/
1491	const RTHCPHYS HCPhys = pPage->HCPhys; /** @todo PAGE FLAGS */
1492	SHWPTE PteDst;
1493	PteDst.u = (PdeSrc.u & ~(X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT))
1494	\| (HCPhys & X86_PTE_PAE_PG_MASK);
1495	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
1496	{
1497	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
1498	PteDst.n.u1Write = 0;
1499	else
1500	PteDst.u = 0;
1501	}
1502	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1503	# ifdef PGMPOOL_WITH_USER_TRACKING
1504	if (PteDst.n.u1Present && !pPTDst->a[iPTDst].n.u1Present)
1505	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst);
1506	# endif
1507	pPTDst->a[iPTDst] = PteDst;
1508
1509
1510	# ifdef PGM_SYNC_DIRTY_BIT
1511	/*
1512	* If the page is not flagged as dirty and is writable, then make it read-only
1513	* at PD level, so we can set the dirty bit when the page is modified.
1514	*
1515	* ASSUMES that page access handlers are implemented on page table entry level.
1516	* Thus we will first catch the dirty access and set PDE.D and restart. If
1517	* there is an access handler, we'll trap again and let it work on the problem.
1518	*/
1519	/** @todo r=bird: figure out why we need this here, SyncPT should've taken care of this already.
1520	* As for invlpg, it simply frees the whole shadow PT.
1521	* ...It's possibly because the guest clears it and the guest doesn't really tell us... */
1522	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
1523	{
1524	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
1525	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
1526	PdeDst.n.u1Write = 0;
1527	}
1528	else
1529	{
1530	PdeDst.au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1531	PdeDst.n.u1Write = PdeSrc.n.u1Write;
1532	}
1533	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1534	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst] = PdeDst;
1535	# else /* PAE */
1536	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
1537	# endif
1538	# endif /* PGM_SYNC_DIRTY_BIT */
1539	Log2(("SyncPage: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} GCPhys=%VGp%s\n",
1540	GCPtrPage, PdeSrc.n.u1Present, PdeSrc.n.u1Write, PdeSrc.n.u1User, (uint64_t)PdeSrc.u, GCPhys,
1541	PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1542	}
1543	else
1544	LogFlow(("PGM_GCPHYS_2_PTR %VGp (big) failed with %Vrc\n", GCPhys, rc));
1545	}
1546	return VINF_SUCCESS;
1547	}
1548	# ifdef PGM_SYNC_ACCESSED_BIT
1549	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDNAs));
1550	#endif
1551	}
1552	else
1553	{
1554	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPagePDOutOfSync));
1555	Log2(("SyncPage: Out-Of-Sync PDE at %VGp PdeSrc=%RX64 PdeDst=%RX64\n",
1556	GCPtrPage, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
1557	}
1558
1559	/*
1560	* Mark the PDE not present. Restart the instruction and let #PF call SyncPT.
1561	* Yea, I'm lazy.
1562	*/
1563	pgmPoolFree(pVM, PdeDst.u & SHW_PDE_PG_MASK, SHW_POOL_ROOT_IDX, iPDDst);
1564	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1565	pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst].u = 0;
1566	# else /* PAE */
1567	pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst].u = 0;
1568	# endif
1569	PGM_INVL_GUEST_TLBS();
1570	return VINF_PGM_SYNCPAGE_MODIFIED_PDE;
1571
1572	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
1573
1574	# ifdef PGM_SYNC_N_PAGES
1575	/*
1576	* Get the shadow PDE, find the shadow page table in the pool.
1577	*/
1578	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
1579	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
1580	X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst];
1581	# else /* PAE */
1582	X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst];
1583	# endif
1584	Assert(PdeDst.n.u1Present);
1585	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, PdeDst.u & SHW_PDE_PG_MASK);
1586	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1587
1588	# if PGM_SHW_TYPE == PGM_TYPE_PAE
1589	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
1590	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
1591	# else
1592	const unsigned offPTSrc = 0;
1593	# endif
1594
1595	Assert(cPages == 1 \|\| !(uErr & X86_TRAP_PF_P));
1596	if (cPages > 1 && !(uErr & X86_TRAP_PF_P))
1597	{
1598	/*
1599	* This code path is currently only taken when the caller is PGMTrap0eHandler
1600	* for non-present pages!
1601	*
1602	* We're setting PGM_SYNC_NR_PAGES pages around the faulting page to sync it and
1603	* deal with locality.
1604	*/
1605	unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1606	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
1607	if (iPTDst < PGM_SYNC_NR_PAGES / 2)
1608	iPTDst = 0;
1609	else
1610	iPTDst -= PGM_SYNC_NR_PAGES / 2;
1611	for (; iPTDst < iPTDstEnd; iPTDst++)
1612	{
1613	if (!pPTDst->a[iPTDst].n.u1Present)
1614	{
1615	GSTPTE PteSrc;
1616
1617	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1618
1619	/* Fake the page table entry */
1620	PteSrc.u = GCPtrCurPage;
1621	PteSrc.n.u1Present = 1;
1622	PteSrc.n.u1Dirty = 1;
1623	PteSrc.n.u1Accessed = 1;
1624	PteSrc.n.u1Write = 1;
1625	PteSrc.n.u1User = 1;
1626
1627	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1628
1629	Log2(("SyncPage: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
1630	GCPtrCurPage, PteSrc.n.u1Present,
1631	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1632	PteSrc.n.u1User & PdeSrc.n.u1User,
1633	(uint64_t)PteSrc.u,
1634	(uint64_t)pPTDst->a[iPTDst].u,
1635	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1636	}
1637	}
1638	}
1639	else
1640	# endif /* PGM_SYNC_N_PAGES */
1641	{
1642	GSTPTE PteSrc;
1643	const unsigned iPTDst = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
1644	RTGCUINTPTR GCPtrCurPage = ((RTGCUINTPTR)GCPtrPage & ~(RTGCUINTPTR)(GST_PT_MASK << GST_PT_SHIFT)) \| ((offPTSrc + iPTDst) << PAGE_SHIFT);
1645
1646	/* Fake the page table entry */
1647	PteSrc.u = GCPtrCurPage;
1648	PteSrc.n.u1Present = 1;
1649	PteSrc.n.u1Dirty = 1;
1650	PteSrc.n.u1Accessed = 1;
1651	PteSrc.n.u1Write = 1;
1652	PteSrc.n.u1User = 1;
1653	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
1654
1655	Log2(("SyncPage: 4K %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s\n",
1656	GCPtrPage, PteSrc.n.u1Present,
1657	PteSrc.n.u1Write & PdeSrc.n.u1Write,
1658	PteSrc.n.u1User & PdeSrc.n.u1User,
1659	(uint64_t)PteSrc.u,
1660	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
1661	}
1662	return VINF_SUCCESS;
1663
1664	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1665	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
1666	return VERR_INTERNAL_ERROR;
1667	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
1668	}
1669
1670
1671
1672	#if PGM_WITH_PAGING(PGM_GST_TYPE)
1673
1674	/**
1675	* Investigate page fault and handle write protection page faults caused by
1676	* dirty bit tracking.
1677	*
1678	* @returns VBox status code.
1679	* @param pVM VM handle.
1680	* @param uErr Page fault error code.
1681	* @param pPdeDst Shadow page directory entry.
1682	* @param pPdeSrc Guest page directory entry.
1683	* @param GCPtrPage Guest context page address.
1684	*/
1685	PGM_BTH_DECL(int, CheckPageFault)(PVM pVM, uint32_t uErr, PSHWPDE pPdeDst, PGSTPDE pPdeSrc, RTGCUINTPTR GCPtrPage)
1686	{
1687	bool fWriteProtect = !!(CPUMGetGuestCR0(pVM) & X86_CR0_WP);
1688	bool fUserLevelFault = !!(uErr & X86_TRAP_PF_US);
1689	bool fWriteFault = !!(uErr & X86_TRAP_PF_RW);
1690	bool fBigPagesSupported = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1691	# if PGM_WITH_NX(PGM_GST_TYPE)
1692	bool fNoExecuteBitValid = !!(CPUMGetGuestEFER(pVM) & MSR_K6_EFER_NXE);
1693	# endif
1694	unsigned uPageFaultLevel;
1695
1696	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1697	LogFlow(("CheckPageFault: GCPtrPage=%VGv uErr=%#x PdeSrc=%08x\n", GCPtrPage, uErr, pPdeSrc->u));
1698
1699	# if PGM_GST_TYPE == PGM_TYPE_PAE \
1700	\|\| PGM_GST_TYPE == PGM_TYPE_AMD64
1701
1702	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1703	PX86PML4E pPml4eSrc;
1704	PX86PDPE pPdpeSrc;
1705
1706	pPdpeSrc = pgmGstGetLongModePDPTPtr(&pVM->pgm.s, GCPtrPage, &pPml4eSrc);
1707	Assert(pPml4eSrc);
1708
1709	/*
1710	* Real page fault? (PML4E level)
1711	*/
1712	if ( (uErr & X86_TRAP_PF_RSVD)
1713	\|\| !pPml4eSrc->n.u1Present
1714	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPml4eSrc->n.u1NoExecute)
1715	\|\| (fWriteFault && !pPml4eSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1716	\|\| (fUserLevelFault && !pPml4eSrc->n.u1User)
1717	)
1718	{
1719	uPageFaultLevel = 0;
1720	goto UpperLevelPageFault;
1721	}
1722	Assert(pPdpeSrc);
1723
1724	# else /* PAE */
1725	PX86PDPE pPdpeSrc = &pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtrPage >> GST_PDPT_SHIFT) & GST_PDPT_MASK];
1726	# endif
1727
1728	/*
1729	* Real page fault? (PDPE level)
1730	*/
1731	if ( (uErr & X86_TRAP_PF_RSVD)
1732	\|\| !pPdpeSrc->n.u1Present
1733	# if PGM_GST_TYPE == PGM_TYPE_AMD64 /* NX, r/w, u/s bits in the PDPE are long mode only */
1734	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdpeSrc->n.u1NoExecute)
1735	\|\| (fWriteFault && !pPdpeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1736	\|\| (fUserLevelFault && !pPdpeSrc->n.u1User)
1737	# endif
1738	)
1739	{
1740	uPageFaultLevel = 1;
1741	goto UpperLevelPageFault;
1742	}
1743	# endif
1744
1745	/*
1746	* Real page fault? (PDE level)
1747	*/
1748	if ( (uErr & X86_TRAP_PF_RSVD)
1749	\|\| !pPdeSrc->n.u1Present
1750	# if PGM_WITH_NX(PGM_GST_TYPE)
1751	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && pPdeSrc->n.u1NoExecute)
1752	# endif
1753	\|\| (fWriteFault && !pPdeSrc->n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1754	\|\| (fUserLevelFault && !pPdeSrc->n.u1User) )
1755	{
1756	uPageFaultLevel = 2;
1757	goto UpperLevelPageFault;
1758	}
1759
1760	/*
1761	* First check the easy case where the page directory has been marked read-only to track
1762	* the dirty bit of an emulated BIG page
1763	*/
1764	if (pPdeSrc->b.u1Size && fBigPagesSupported)
1765	{
1766	/* Mark guest page directory as accessed */
1767	pPdeSrc->b.u1Accessed = 1;
1768
1769	/*
1770	* Only write protection page faults are relevant here.
1771	*/
1772	if (fWriteFault)
1773	{
1774	/* Mark guest page directory as dirty (BIG page only). */
1775	pPdeSrc->b.u1Dirty = 1;
1776
1777	if (pPdeDst->n.u1Present && (pPdeDst->u & PGM_PDFLAGS_TRACK_DIRTY))
1778	{
1779	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1780
1781	Assert(pPdeSrc->b.u1Write);
1782
1783	pPdeDst->n.u1Write = 1;
1784	pPdeDst->n.u1Accessed = 1;
1785	pPdeDst->au32[0] &= ~PGM_PDFLAGS_TRACK_DIRTY;
1786	PGM_INVL_BIG_PG(GCPtrPage);
1787	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1788	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1789	}
1790	}
1791	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1792	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1793	}
1794	/* else: 4KB page table */
1795
1796	/*
1797	* Map the guest page table.
1798	*/
1799	PGSTPT pPTSrc;
1800	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1801	if (VBOX_SUCCESS(rc))
1802	{
1803	/*
1804	* Real page fault?
1805	*/
1806	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1807	const GSTPTE PteSrc = *pPteSrc;
1808	if ( !PteSrc.n.u1Present
1809	# if PGM_WITH_NX(PGM_GST_TYPE)
1810	\|\| (fNoExecuteBitValid && (uErr & X86_TRAP_PF_ID) && PteSrc.n.u1NoExecute)
1811	# endif
1812	\|\| (fWriteFault && !PteSrc.n.u1Write && (fUserLevelFault \|\| fWriteProtect))
1813	\|\| (fUserLevelFault && !PteSrc.n.u1User)
1814	)
1815	{
1816	# ifdef IN_GC
1817	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1818	# endif
1819	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1820	LogFlow(("CheckPageFault: real page fault at %VGv PteSrc.u=%08x (2)\n", GCPtrPage, PteSrc.u));
1821
1822	/* Check the present bit as the shadow tables can cause different error codes by being out of sync.
1823	* See the 2nd case above as well.
1824	*/
1825	if (pPdeSrc->n.u1Present && pPteSrc->n.u1Present)
1826	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1827
1828	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1829	return VINF_EM_RAW_GUEST_TRAP;
1830	}
1831	LogFlow(("CheckPageFault: page fault at %VGv PteSrc.u=%08x\n", GCPtrPage, PteSrc.u));
1832
1833	/*
1834	* Set the accessed bits in the page directory and the page table.
1835	*/
1836	pPdeSrc->n.u1Accessed = 1;
1837	pPteSrc->n.u1Accessed = 1;
1838
1839	/*
1840	* Only write protection page faults are relevant here.
1841	*/
1842	if (fWriteFault)
1843	{
1844	/* Write access, so mark guest entry as dirty. */
1845	# if defined(IN_GC) && defined(VBOX_WITH_STATISTICS)
1846	if (!pPteSrc->n.u1Dirty)
1847	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtiedPage);
1848	else
1849	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageAlreadyDirty);
1850	# endif
1851	pPteSrc->n.u1Dirty = 1;
1852
1853	if (pPdeDst->n.u1Present)
1854	{
1855	/* Bail out here as pgmPoolGetPageByHCPhys will return NULL and we'll crash below.
1856	* Our individual shadow handlers will provide more information and force a fatal exit.
1857	*/
1858	if (MMHyperIsInsideArea(pVM, (RTGCPTR)GCPtrPage))
1859	{
1860	LogRel(("CheckPageFault: write to hypervisor region %VGv\n", GCPtrPage));
1861	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1862	return VINF_SUCCESS;
1863	}
1864
1865	/*
1866	* Map shadow page table.
1867	*/
1868	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1869	if (pShwPage)
1870	{
1871	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1872	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1873	if ( pPteDst->n.u1Present /** @todo Optimize accessed bit emulation? */
1874	&& (pPteDst->u & PGM_PTFLAGS_TRACK_DIRTY))
1875	{
1876	LogFlow(("DIRTY page trap addr=%VGv\n", GCPtrPage));
1877	# ifdef VBOX_STRICT
1878	PPGMPAGE pPage = pgmPhysGetPage(&pVM->pgm.s, pPteSrc->u & GST_PTE_PG_MASK);
1879	if (pPage)
1880	AssertMsg(!PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage),
1881	("Unexpected dirty bit tracking on monitored page %VGv (phys %VGp)!!!!!!\n", GCPtrPage, pPteSrc->u & X86_PTE_PAE_PG_MASK));
1882	# endif
1883	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageTrap));
1884
1885	Assert(pPteSrc->n.u1Write);
1886
1887	pPteDst->n.u1Write = 1;
1888	pPteDst->n.u1Dirty = 1;
1889	pPteDst->n.u1Accessed = 1;
1890	pPteDst->au32[0] &= ~PGM_PTFLAGS_TRACK_DIRTY;
1891	PGM_INVL_PG(GCPtrPage);
1892
1893	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1894	return VINF_PGM_HANDLED_DIRTY_BIT_FAULT;
1895	}
1896	}
1897	else
1898	AssertMsgFailed(("pgmPoolGetPageByHCPhys %VGp failed!\n", pPdeDst->u & SHW_PDE_PG_MASK));
1899	}
1900	}
1901	/** @todo Optimize accessed bit emulation? */
1902	# ifdef VBOX_STRICT
1903	/*
1904	* Sanity check.
1905	*/
1906	else if ( !pPteSrc->n.u1Dirty
1907	&& (pPdeSrc->n.u1Write & pPteSrc->n.u1Write)
1908	&& pPdeDst->n.u1Present)
1909	{
1910	PPGMPOOLPAGE pShwPage = pgmPoolGetPageByHCPhys(pVM, pPdeDst->u & SHW_PDE_PG_MASK);
1911	PSHWPT pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
1912	PSHWPTE pPteDst = &pPTDst->a[(GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK];
1913	if ( pPteDst->n.u1Present
1914	&& pPteDst->n.u1Write)
1915	LogFlow(("Writable present page %VGv not marked for dirty bit tracking!!!\n", GCPtrPage));
1916	}
1917	# endif /* VBOX_STRICT */
1918	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1919	return VINF_PGM_NO_DIRTY_BIT_TRACKING;
1920	}
1921	AssertRC(rc);
1922	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,DirtyBitTracking), a);
1923	return rc;
1924
1925
1926	UpperLevelPageFault:
1927	/* Pagefault detected while checking the PML4E, PDPE or PDE.
1928	* Single exit handler to get rid of duplicate code paths.
1929	*/
1930	# ifdef IN_GC
1931	STAM_COUNTER_INC(&pVM->pgm.s.StatGCDirtyTrackRealPF);
1932	# endif
1933	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat, DirtyBitTracking), a);
1934	LogFlow(("CheckPageFault: real page fault at %VGv (%d)\n", GCPtrPage, uPageFaultLevel));
1935
1936	if (
1937	# if PGM_GST_TYPE == PGM_TYPE_AMD64
1938	pPml4eSrc->n.u1Present &&
1939	# endif
1940	# if PGM_GST_TYPE == PGM_TYPE_AMD64 \|\| PGM_GST_TYPE == PGM_TYPE_PAE
1941	pPdpeSrc->n.u1Present &&
1942	# endif
1943	pPdeSrc->n.u1Present)
1944	{
1945	/* Check the present bit as the shadow tables can cause different error codes by being out of sync. */
1946	if (pPdeSrc->b.u1Size && fBigPagesSupported)
1947	{
1948	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1949	}
1950	else
1951	{
1952	/*
1953	* Map the guest page table.
1954	*/
1955	PGSTPT pPTSrc;
1956	int rc = PGM_GCPHYS_2_PTR(pVM, pPdeSrc->u & GST_PDE_PG_MASK, &pPTSrc);
1957	if (VBOX_SUCCESS(rc))
1958	{
1959	PGSTPTE pPteSrc = &pPTSrc->a[(GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK];
1960	const GSTPTE PteSrc = *pPteSrc;
1961	if (pPteSrc->n.u1Present)
1962	TRPMSetErrorCode(pVM, uErr \| X86_TRAP_PF_P); /* page-level protection violation */
1963	}
1964	AssertRC(rc);
1965	}
1966	}
1967	return VINF_EM_RAW_GUEST_TRAP;
1968	}
1969
1970	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
1971
1972
1973	/**
1974	* Sync a shadow page table.
1975	*
1976	* The shadow page table is not present. This includes the case where
1977	* there is a conflict with a mapping.
1978	*
1979	* @returns VBox status code.
1980	* @param pVM VM handle.
1981	* @param iPD Page directory index.
1982	* @param pPDSrc Source page directory (i.e. Guest OS page directory).
1983	* Assume this is a temporary mapping.
1984	* @param GCPtrPage GC Pointer of the page that caused the fault
1985	*/
1986	PGM_BTH_DECL(int, SyncPT)(PVM pVM, unsigned iPDSrc, PGSTPD pPDSrc, RTGCUINTPTR GCPtrPage)
1987	{
1988	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
1989	STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPtPD[iPDSrc]);
1990	LogFlow(("SyncPT: GCPtrPage=%VGv\n", GCPtrPage));
1991
1992	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
1993	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
1994
1995	/*
1996	* Validate input a little bit.
1997	*/
1998	AssertMsg(iPDSrc == ((GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK), ("iPDSrc=%x GCPtrPage=%VGv\n", iPDSrc, GCPtrPage));
1999	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2000	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2001	# else
2002	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2003	# endif
2004	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2005	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2006	SHWPDE PdeDst = *pPdeDst;
2007
2008	# ifndef PGM_WITHOUT_MAPPINGS
2009	/*
2010	* Check for conflicts.
2011	* GC: In case of a conflict we'll go to Ring-3 and do a full SyncCR3.
2012	* HC: Simply resolve the conflict.
2013	*/
2014	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
2015	{
2016	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2017	# ifndef IN_RING3
2018	Log(("SyncPT: Conflict at %VGv\n", GCPtrPage));
2019	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2020	return VERR_ADDRESS_CONFLICT;
2021	# else
2022	PPGMMAPPING pMapping = pgmGetMapping(pVM, (RTGCPTR)GCPtrPage);
2023	Assert(pMapping);
2024	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2025	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2026	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2027	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, GCPtrPage & (GST_PD_MASK << GST_PD_SHIFT));
2028	# endif
2029	if (VBOX_FAILURE(rc))
2030	{
2031	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2032	return rc;
2033	}
2034	PdeDst = *pPdeDst;
2035	# endif
2036	}
2037	# else /* PGM_WITHOUT_MAPPINGS */
2038	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2039	# endif /* PGM_WITHOUT_MAPPINGS */
2040	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2041
2042	/*
2043	* Sync page directory entry.
2044	*/
2045	int rc = VINF_SUCCESS;
2046	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2047	if (PdeSrc.n.u1Present)
2048	{
2049	/*
2050	* Allocate & map the page table.
2051	*/
2052	PSHWPT pPTDst;
2053	const bool fPageTable = !PdeSrc.b.u1Size \|\| !(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2054	PPGMPOOLPAGE pShwPage;
2055	RTGCPHYS GCPhys;
2056	if (fPageTable)
2057	{
2058	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2059	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2060	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2061	GCPhys \|= (iPDDst & 1) * (PAGE_SIZE / 2);
2062	# endif
2063	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2064	}
2065	else
2066	{
2067	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2068	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2069	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2070	GCPhys \|= GCPtrPage & (1 << X86_PD_PAE_SHIFT);
2071	# endif
2072	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_BIG, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2073	}
2074	if (rc == VINF_SUCCESS)
2075	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2076	else if (rc == VINF_PGM_CACHED_PAGE)
2077	{
2078	/*
2079	* The PT was cached, just hook it up.
2080	*/
2081	if (fPageTable)
2082	PdeDst.u = pShwPage->Core.Key
2083	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2084	else
2085	{
2086	PdeDst.u = pShwPage->Core.Key
2087	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2088	# ifdef PGM_SYNC_DIRTY_BIT /* (see explanation and assumptions further down.) */
2089	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2090	{
2091	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2092	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2093	PdeDst.b.u1Write = 0;
2094	}
2095	# endif
2096	}
2097	*pPdeDst = PdeDst;
2098	return VINF_SUCCESS;
2099	}
2100	else if (rc == VERR_PGM_POOL_FLUSHED)
2101	return VINF_PGM_SYNC_CR3;
2102	else
2103	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2104	PdeDst.u &= X86_PDE_AVL_MASK;
2105	PdeDst.u \|= pShwPage->Core.Key;
2106
2107	# ifdef PGM_SYNC_DIRTY_BIT
2108	/*
2109	* Page directory has been accessed (this is a fault situation, remember).
2110	*/
2111	pPDSrc->a[iPDSrc].n.u1Accessed = 1;
2112	# endif
2113	if (fPageTable)
2114	{
2115	/*
2116	* Page table - 4KB.
2117	*
2118	* Sync all or just a few entries depending on PGM_SYNC_N_PAGES.
2119	*/
2120	Log2(("SyncPT: 4K %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx}\n",
2121	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u));
2122	PGSTPT pPTSrc;
2123	rc = PGM_GCPHYS_2_PTR(pVM, PdeSrc.u & GST_PDE_PG_MASK, &pPTSrc);
2124	if (VBOX_SUCCESS(rc))
2125	{
2126	/*
2127	* Start by syncing the page directory entry so CSAM's TLB trick works.
2128	*/
2129	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| X86_PDE_AVL_MASK))
2130	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2131	*pPdeDst = PdeDst;
2132
2133	/*
2134	* Directory/page user or supervisor privilege: (same goes for read/write)
2135	*
2136	* Directory Page Combined
2137	* U/S U/S U/S
2138	* 0 0 0
2139	* 0 1 0
2140	* 1 0 0
2141	* 1 1 1
2142	*
2143	* Simple AND operation. Table listed for completeness.
2144	*
2145	*/
2146	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4k));
2147	# ifdef PGM_SYNC_N_PAGES
2148	unsigned iPTBase = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
2149	unsigned iPTDst = iPTBase;
2150	const unsigned iPTDstEnd = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, ELEMENTS(pPTDst->a));
2151	if (iPTDst <= PGM_SYNC_NR_PAGES / 2)
2152	iPTDst = 0;
2153	else
2154	iPTDst -= PGM_SYNC_NR_PAGES / 2;
2155	# else /* !PGM_SYNC_N_PAGES */
2156	unsigned iPTDst = 0;
2157	const unsigned iPTDstEnd = ELEMENTS(pPTDst->a);
2158	# endif /* !PGM_SYNC_N_PAGES */
2159	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2160	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2161	const unsigned offPTSrc = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
2162	# else
2163	const unsigned offPTSrc = 0;
2164	# endif
2165	for (; iPTDst < iPTDstEnd; iPTDst++)
2166	{
2167	const unsigned iPTSrc = iPTDst + offPTSrc;
2168	const GSTPTE PteSrc = pPTSrc->a[iPTSrc];
2169
2170	if (PteSrc.n.u1Present) /* we've already cleared it above */
2171	{
2172	# ifndef IN_RING0
2173	/*
2174	* Assuming kernel code will be marked as supervisor - and not as user level
2175	* and executed using a conforming code selector - And marked as readonly.
2176	* Also assume that if we're monitoring a page, it's of no interest to CSAM.
2177	*/
2178	PPGMPAGE pPage;
2179	if ( ((PdeSrc.u & pPTSrc->a[iPTSrc].u) & (X86_PTE_RW \| X86_PTE_US))
2180	\|\| !CSAMDoesPageNeedScanning(pVM, (RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)))
2181	\|\| ( (pPage = pgmPhysGetPage(&pVM->pgm.s, PteSrc.u & GST_PTE_PG_MASK))
2182	&& PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2183	)
2184	# endif
2185	PGM_BTH_NAME(SyncPageWorker)(pVM, &pPTDst->a[iPTDst], PdeSrc, PteSrc, pShwPage, iPTDst);
2186	Log2(("SyncPT: 4K+ %VGv PteSrc:{P=%d RW=%d U=%d raw=%08llx}%s dst.raw=%08llx iPTSrc=%x PdeSrc.u=%x physpte=%VGp\n",
2187	(RTGCPTR)((iPDSrc << GST_PD_SHIFT) \| (iPTSrc << PAGE_SHIFT)),
2188	PteSrc.n.u1Present,
2189	PteSrc.n.u1Write & PdeSrc.n.u1Write,
2190	PteSrc.n.u1User & PdeSrc.n.u1User,
2191	(uint64_t)PteSrc.u,
2192	pPTDst->a[iPTDst].u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : "", pPTDst->a[iPTDst].u, iPTSrc, PdeSrc.au32[0],
2193	(PdeSrc.u & GST_PDE_PG_MASK) + iPTSrc*sizeof(PteSrc)));
2194	}
2195	} /* for PTEs */
2196	}
2197	}
2198	else
2199	{
2200	/*
2201	* Big page - 2/4MB.
2202	*
2203	* We'll walk the ram range list in parallel and optimize lookups.
2204	* We will only sync on shadow page table at a time.
2205	*/
2206	STAM_COUNTER_INC(CTXSUFF(&pVM->pgm.s.StatSynPT4M));
2207
2208	/**
2209	* @todo It might be more efficient to sync only a part of the 4MB page (similar to what we do for 4kb PDs).
2210	*/
2211
2212	/*
2213	* Start by syncing the page directory entry.
2214	*/
2215	PdeDst.u = (PdeDst.u & (SHW_PDE_PG_MASK \| (X86_PDE_AVL_MASK & ~PGM_PDFLAGS_TRACK_DIRTY)))
2216	\| (PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PDE_AVL_MASK \| X86_PDE_PCD \| X86_PDE_PWT \| X86_PDE_PS \| X86_PDE4M_G \| X86_PDE4M_D));
2217
2218	# ifdef PGM_SYNC_DIRTY_BIT
2219	/*
2220	* If the page is not flagged as dirty and is writable, then make it read-only
2221	* at PD level, so we can set the dirty bit when the page is modified.
2222	*
2223	* ASSUMES that page access handlers are implemented on page table entry level.
2224	* Thus we will first catch the dirty access and set PDE.D and restart. If
2225	* there is an access handler, we'll trap again and let it work on the problem.
2226	*/
2227	/** @todo move the above stuff to a section in the PGM documentation. */
2228	Assert(!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY));
2229	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
2230	{
2231	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,DirtyPageBig));
2232	PdeDst.u \|= PGM_PDFLAGS_TRACK_DIRTY;
2233	PdeDst.b.u1Write = 0;
2234	}
2235	# endif /* PGM_SYNC_DIRTY_BIT */
2236	*pPdeDst = PdeDst;
2237
2238	/*
2239	* Fill the shadow page table.
2240	*/
2241	/* Get address and flags from the source PDE. */
2242	SHWPTE PteDstBase;
2243	PteDstBase.u = PdeSrc.u & ~(GST_PDE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PAT \| X86_PTE_PCD \| X86_PTE_PWT);
2244
2245	/* Loop thru the entries in the shadow PT. */
2246	const RTGCUINTPTR GCPtr = (GCPtrPage >> SHW_PD_SHIFT) << SHW_PD_SHIFT; NOREF(GCPtr);
2247	Log2(("SyncPT: BIG %VGv PdeSrc:{P=%d RW=%d U=%d raw=%08llx} Shw=%VGv GCPhys=%VGp %s\n",
2248	GCPtrPage, PdeSrc.b.u1Present, PdeSrc.b.u1Write, PdeSrc.b.u1User, (uint64_t)PdeSrc.u, GCPtr,
2249	GCPhys, PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2250	PPGMRAMRANGE pRam = CTXALLSUFF(pVM->pgm.s.pRamRanges);
2251	unsigned iPTDst = 0;
2252	while (iPTDst < ELEMENTS(pPTDst->a))
2253	{
2254	/* Advance ram range list. */
2255	while (pRam && GCPhys > pRam->GCPhysLast)
2256	pRam = CTXALLSUFF(pRam->pNext);
2257	if (pRam && GCPhys >= pRam->GCPhys)
2258	{
2259	unsigned iHCPage = (GCPhys - pRam->GCPhys) >> PAGE_SHIFT;
2260	do
2261	{
2262	/* Make shadow PTE. */
2263	PPGMPAGE pPage = &pRam->aPages[iHCPage];
2264	SHWPTE PteDst;
2265
2266	/* Make sure the RAM has already been allocated. */
2267	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC) /** @todo PAGE FLAGS */
2268	{
2269	if (RT_UNLIKELY(!PGM_PAGE_GET_HCPHYS(pPage)))
2270	{
2271	# ifdef IN_RING3
2272	int rc = pgmr3PhysGrowRange(pVM, GCPhys);
2273	# else
2274	int rc = CTXALLMID(VMM, CallHost)(pVM, VMMCALLHOST_PGM_RAM_GROW_RANGE, GCPhys);
2275	# endif
2276	if (rc != VINF_SUCCESS)
2277	return rc;
2278	}
2279	}
2280
2281	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
2282	{
2283	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage))
2284	{
2285	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2286	PteDst.n.u1Write = 0;
2287	}
2288	else
2289	PteDst.u = 0;
2290	}
2291	# ifndef IN_RING0
2292	/*
2293	* Assuming kernel code will be marked as supervisor and not as user level and executed
2294	* using a conforming code selector. Don't check for readonly, as that implies the whole
2295	* 4MB can be code or readonly data. Linux enables write access for its large pages.
2296	*/
2297	else if ( !PdeSrc.n.u1User
2298	&& CSAMDoesPageNeedScanning(pVM, (RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT))))
2299	PteDst.u = 0;
2300	# endif
2301	else
2302	PteDst.u = PGM_PAGE_GET_HCPHYS(pPage) \| PteDstBase.u;
2303	# ifdef PGMPOOL_WITH_USER_TRACKING
2304	if (PteDst.n.u1Present)
2305	PGM_BTH_NAME(SyncPageWorkerTrackAddref)(pVM, pShwPage, pPage->HCPhys >> MM_RAM_FLAGS_IDX_SHIFT, pPage, iPTDst); /** @todo PAGE FLAGS */
2306	# endif
2307	/* commit it */
2308	pPTDst->a[iPTDst] = PteDst;
2309	Log4(("SyncPT: BIG %VGv PteDst:{P=%d RW=%d U=%d raw=%08llx}%s\n",
2310	(RTGCPTR)(GCPtr \| (iPTDst << SHW_PT_SHIFT)), PteDst.n.u1Present, PteDst.n.u1Write, PteDst.n.u1User, (uint64_t)PteDst.u,
2311	PteDst.u & PGM_PTFLAGS_TRACK_DIRTY ? " Track-Dirty" : ""));
2312
2313	/* advance */
2314	GCPhys += PAGE_SIZE;
2315	iHCPage++;
2316	iPTDst++;
2317	} while ( iPTDst < ELEMENTS(pPTDst->a)
2318	&& GCPhys <= pRam->GCPhysLast);
2319	}
2320	else if (pRam)
2321	{
2322	Log(("Invalid pages at %VGp\n", GCPhys));
2323	do
2324	{
2325	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2326	GCPhys += PAGE_SIZE;
2327	iPTDst++;
2328	} while ( iPTDst < ELEMENTS(pPTDst->a)
2329	&& GCPhys < pRam->GCPhys);
2330	}
2331	else
2332	{
2333	Log(("Invalid pages at %VGp (2)\n", GCPhys));
2334	for ( ; iPTDst < ELEMENTS(pPTDst->a); iPTDst++)
2335	pPTDst->a[iPTDst].u = 0; /* MMIO or invalid page, we must handle them manually. */
2336	}
2337	} /* while more PTEs */
2338	} /* 4KB / 4MB */
2339	}
2340	else
2341	AssertRelease(!PdeDst.n.u1Present);
2342
2343	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2344	# ifdef IN_GC
2345	if (VBOX_FAILURE(rc))
2346	STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncPTFailed));
2347	# endif
2348	return rc;
2349
2350	#elif PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT
2351
2352	int rc = VINF_SUCCESS;
2353
2354	/*
2355	* Validate input a little bit.
2356	*/
2357	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2358	PX86PD pPDDst = pVM->pgm.s.CTXMID(p,32BitPD);
2359	# else
2360	PX86PDPAE pPDDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2361	# endif
2362	const unsigned iPDDst = GCPtrPage >> SHW_PD_SHIFT;
2363	PSHWPDE pPdeDst = &pPDDst->a[iPDDst];
2364	SHWPDE PdeDst = *pPdeDst;
2365
2366	Assert(!(PdeDst.u & PGM_PDFLAGS_MAPPING));
2367	Assert(!PdeDst.n.u1Present); /* We're only supposed to call SyncPT on PDE!P and conflicts.*/
2368
2369	GSTPDE PdeSrc;
2370	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2371	PdeSrc.n.u1Present = 1;
2372	PdeSrc.n.u1Write = 1;
2373	PdeSrc.n.u1Accessed = 1;
2374	PdeSrc.n.u1User = 1;
2375
2376	/*
2377	* Allocate & map the page table.
2378	*/
2379	PSHWPT pPTDst;
2380	PPGMPOOLPAGE pShwPage;
2381	RTGCPHYS GCPhys;
2382
2383	/* Virtual address = physical address */
2384	GCPhys = GCPtrPage & X86_PAGE_4K_BASE_MASK_32;
2385	rc = pgmPoolAlloc(pVM, GCPhys, BTH_PGMPOOLKIND_PT_FOR_PT, SHW_POOL_ROOT_IDX, iPDDst, &pShwPage);
2386
2387	if ( rc == VINF_SUCCESS
2388	\|\| rc == VINF_PGM_CACHED_PAGE)
2389	pPTDst = (PSHWPT)PGMPOOL_PAGE_2_PTR(pVM, pShwPage);
2390	else
2391	AssertMsgFailedReturn(("rc=%Vrc\n", rc), VERR_INTERNAL_ERROR);
2392
2393	PdeDst.u &= X86_PDE_AVL_MASK;
2394	PdeDst.u \|= pShwPage->Core.Key;
2395	PdeDst.n.u1Present = 1;
2396	*pPdeDst = PdeDst;
2397
2398	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, (RTGCUINTPTR)GCPtrPage, PGM_SYNC_NR_PAGES, 0 /* page not present */);
2399	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2400	return rc;
2401
2402	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2403	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2404	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncPT), a);
2405	return VERR_INTERNAL_ERROR;
2406	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2407	}
2408
2409
2410
2411	/**
2412	* Prefetch a page/set of pages.
2413	*
2414	* Typically used to sync commonly used pages before entering raw mode
2415	* after a CR3 reload.
2416	*
2417	* @returns VBox status code.
2418	* @param pVM VM handle.
2419	* @param GCPtrPage Page to invalidate.
2420	*/
2421	PGM_BTH_DECL(int, PrefetchPage)(PVM pVM, RTGCUINTPTR GCPtrPage)
2422	{
2423	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2424	/*
2425	* Check that all Guest levels thru the PDE are present, getting the
2426	* PD and PDE in the processes.
2427	*/
2428	int rc = VINF_SUCCESS;
2429	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2430	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2431	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2432	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2433	# else /* PAE */
2434	unsigned iPDSrc;
2435	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2436	if (!pPDSrc)
2437	return VINF_SUCCESS; /* not present */
2438	# endif
2439	const GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2440	# else
2441	PGSTPD pPDSrc = NULL;
2442	const unsigned iPDSrc = 0;
2443	GSTPDE PdeSrc;
2444
2445	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2446	PdeSrc.n.u1Present = 1;
2447	PdeSrc.n.u1Write = 1;
2448	PdeSrc.n.u1Accessed = 1;
2449	PdeSrc.n.u1User = 1;
2450	# endif
2451
2452	# ifdef PGM_SYNC_ACCESSED_BIT
2453	if (PdeSrc.n.u1Present && PdeSrc.n.u1Accessed)
2454	# else
2455	if (PdeSrc.n.u1Present)
2456	# endif
2457	{
2458	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2459	const X86PDE PdeDst = pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2460	# else
2461	const X86PDEPAE PdeDst = pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2462	# endif
2463	if (!(PdeDst.u & PGM_PDFLAGS_MAPPING))
2464	{
2465	if (!PdeDst.n.u1Present)
2466	/** r=bird: This guy will set the A bit on the PDE, probably harmless. */
2467	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2468	else
2469	{
2470	/** @note We used to sync PGM_SYNC_NR_PAGES pages, which triggered assertions in CSAM, because
2471	* R/W attributes of nearby pages were reset. Not sure how that could happen. Anyway, it
2472	* makes no sense to prefetch more than one page.
2473	*/
2474	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2475	if (VBOX_SUCCESS(rc))
2476	rc = VINF_SUCCESS;
2477	}
2478	}
2479	}
2480	return rc;
2481
2482	#else /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2483
2484	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
2485	return VERR_INTERNAL_ERROR;
2486	#endif /* PGM_GST_TYPE == PGM_TYPE_AMD64 */
2487	}
2488
2489
2490
2491
2492	/**
2493	* Syncs a page during a PGMVerifyAccess() call.
2494	*
2495	* @returns VBox status code (informational included).
2496	* @param GCPtrPage The address of the page to sync.
2497	* @param fPage The effective guest page flags.
2498	* @param uErr The trap error code.
2499	*/
2500	PGM_BTH_DECL(int, VerifyAccessSyncPage)(PVM pVM, RTGCUINTPTR GCPtrPage, unsigned fPage, unsigned uErr)
2501	{
2502	LogFlow(("VerifyAccessSyncPage: GCPtrPage=%VGv fPage=%#x uErr=%#x\n", GCPtrPage, fPage, uErr));
2503
2504	#if (PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_REAL \|\| PGM_GST_TYPE == PGM_TYPE_PROT \|\| PGM_GST_TYPE == PGM_TYPE_PAE) && PGM_SHW_TYPE != PGM_TYPE_AMD64
2505
2506	# ifndef IN_RING0
2507	if (!(fPage & X86_PTE_US))
2508	{
2509	/*
2510	* Mark this page as safe.
2511	*/
2512	/** @todo not correct for pages that contain both code and data!! */
2513	Log(("CSAMMarkPage %VGv; scanned=%d\n", GCPtrPage, true));
2514	CSAMMarkPage(pVM, (RTGCPTR)GCPtrPage, true);
2515	}
2516	# endif
2517	/*
2518	* Get guest PD and index.
2519	*/
2520
2521	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2522	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2523	const unsigned iPDSrc = (RTGCUINTPTR)GCPtrPage >> GST_PD_SHIFT;
2524	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2525	# else /* PAE */
2526	unsigned iPDSrc;
2527	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, GCPtrPage, &iPDSrc);
2528
2529	if (pPDSrc)
2530	{
2531	Log(("PGMVerifyAccess: access violation for %VGv due to non-present PDPTR\n", GCPtrPage));
2532	return VINF_EM_RAW_GUEST_TRAP;
2533	}
2534	# endif
2535	# else
2536	PGSTPD pPDSrc = NULL;
2537	const unsigned iPDSrc = 0;
2538	# endif
2539	int rc = VINF_SUCCESS;
2540
2541	/*
2542	* First check if the shadow pd is present.
2543	*/
2544	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2545	PX86PDE pPdeDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[GCPtrPage >> SHW_PD_SHIFT];
2546	# else
2547	PX86PDEPAE pPdeDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[GCPtrPage >> SHW_PD_SHIFT];
2548	# endif
2549	if (!pPdeDst->n.u1Present)
2550	{
2551	rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
2552	AssertRC(rc);
2553	if (rc != VINF_SUCCESS)
2554	return rc;
2555	}
2556
2557	# if PGM_WITH_PAGING(PGM_GST_TYPE)
2558	/* Check for dirty bit fault */
2559	rc = PGM_BTH_NAME(CheckPageFault)(pVM, uErr, pPdeDst, &pPDSrc->a[iPDSrc], GCPtrPage);
2560	if (rc == VINF_PGM_HANDLED_DIRTY_BIT_FAULT)
2561	Log(("PGMVerifyAccess: success (dirty)\n"));
2562	else
2563	{
2564	GSTPDE PdeSrc = pPDSrc->a[iPDSrc];
2565	#else
2566	{
2567	GSTPDE PdeSrc;
2568	PdeSrc.au32[0] = 0; /* faked so we don't have to #ifdef everything */
2569	PdeSrc.n.u1Present = 1;
2570	PdeSrc.n.u1Write = 1;
2571	PdeSrc.n.u1Accessed = 1;
2572	PdeSrc.n.u1User = 1;
2573
2574	#endif /* PGM_WITH_PAGING(PGM_GST_TYPE) */
2575	Assert(rc != VINF_EM_RAW_GUEST_TRAP);
2576	if (uErr & X86_TRAP_PF_US)
2577	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncUser);
2578	else /* supervisor */
2579	STAM_COUNTER_INC(&pVM->pgm.s.StatGCPageOutOfSyncSupervisor);
2580
2581	rc = PGM_BTH_NAME(SyncPage)(pVM, PdeSrc, GCPtrPage, 1, 0);
2582	if (VBOX_SUCCESS(rc))
2583	{
2584	/* Page was successfully synced */
2585	Log2(("PGMVerifyAccess: success (sync)\n"));
2586	rc = VINF_SUCCESS;
2587	}
2588	else
2589	{
2590	Log(("PGMVerifyAccess: access violation for %VGv rc=%d\n", GCPtrPage, rc));
2591	return VINF_EM_RAW_GUEST_TRAP;
2592	}
2593	}
2594	return rc;
2595
2596	#else /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2597
2598	AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
2599	return VERR_INTERNAL_ERROR;
2600	#endif /* PGM_GST_TYPE != PGM_TYPE_32BIT */
2601	}
2602
2603
2604	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2605	# if PGM_SHW_TYPE == PGM_TYPE_32BIT \|\| PGM_SHW_TYPE == PGM_TYPE_PAE
2606	/**
2607	* Figures out which kind of shadow page this guest PDE warrants.
2608	*
2609	* @returns Shadow page kind.
2610	* @param pPdeSrc The guest PDE in question.
2611	* @param cr4 The current guest cr4 value.
2612	*/
2613	DECLINLINE(PGMPOOLKIND) PGM_BTH_NAME(CalcPageKind)(const GSTPDE *pPdeSrc, uint32_t cr4)
2614	{
2615	if (!pPdeSrc->n.u1Size \|\| !(cr4 & X86_CR4_PSE))
2616	return BTH_PGMPOOLKIND_PT_FOR_PT;
2617	//switch (pPdeSrc->u & (X86_PDE4M_RW \| X86_PDE4M_US /\| X86_PDE4M_PAE_NX/))
2618	//{
2619	// case 0:
2620	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RO;
2621	// case X86_PDE4M_RW:
2622	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW;
2623	// case X86_PDE4M_US:
2624	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US;
2625	// case X86_PDE4M_RW \| X86_PDE4M_US:
2626	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US;
2627	# if 0
2628	// case X86_PDE4M_PAE_NX:
2629	// return BTH_PGMPOOLKIND_PT_FOR_BIG_NX;
2630	// case X86_PDE4M_RW \| X86_PDE4M_PAE_NX:
2631	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_NX;
2632	// case X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2633	// return BTH_PGMPOOLKIND_PT_FOR_BIG_US_NX;
2634	// case X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_PAE_NX:
2635	// return BTH_PGMPOOLKIND_PT_FOR_BIG_RW_US_NX;
2636	# endif
2637	return BTH_PGMPOOLKIND_PT_FOR_BIG;
2638	//}
2639	}
2640	# endif
2641	#endif
2642
2643	#undef MY_STAM_COUNTER_INC
2644	#define MY_STAM_COUNTER_INC(a) do { } while (0)
2645
2646
2647	/**
2648	* Syncs the paging hierarchy starting at CR3.
2649	*
2650	* @returns VBox status code, no specials.
2651	* @param pVM The virtual machine.
2652	* @param cr0 Guest context CR0 register
2653	* @param cr3 Guest context CR3 register
2654	* @param cr4 Guest context CR4 register
2655	* @param fGlobal Including global page directories or not
2656	*/
2657	PGM_BTH_DECL(int, SyncCR3)(PVM pVM, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal)
2658	{
2659	if (VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3))
2660	fGlobal = true; /* Change this CR3 reload to be a global one. */
2661
2662	/*
2663	* Update page access handlers.
2664	* The virtual are always flushed, while the physical are only on demand.
2665	* WARNING: We are incorrectly not doing global flushing on Virtual Handler updates. We'll
2666	* have to look into that later because it will have a bad influence on the performance.
2667	* @note SvL: There's no need for that. Just invalidate the virtual range(s).
2668	* bird: Yes, but that won't work for aliases.
2669	*/
2670	/** @todo this MUST go away. See #1557. */
2671	STAM_PROFILE_START(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2672	PGM_GST_NAME(HandlerVirtualUpdate)(pVM, cr4);
2673	STAM_PROFILE_STOP(&pVM->pgm.s.CTXMID(Stat,SyncCR3Handlers), h);
2674
2675	#ifdef PGMPOOL_WITH_MONITORING
2676	/*
2677	* When monitoring shadowed pages, we reset the modification counters on CR3 sync.
2678	* Occationally we will have to clear all the shadow page tables because we wanted
2679	* to monitor a page which was mapped by too many shadowed page tables. This operation
2680	* sometimes refered to as a 'lightweight flush'.
2681	*/
2682	if (!(pVM->pgm.s.fSyncFlags & PGM_SYNC_CLEAR_PGM_POOL))
2683	pgmPoolMonitorModifiedClearAll(pVM);
2684	else
2685	{
2686	# ifdef IN_RING3
2687	pVM->pgm.s.fSyncFlags &= ~PGM_SYNC_CLEAR_PGM_POOL;
2688	pgmPoolClearAll(pVM);
2689	# else
2690	LogFlow(("SyncCR3: PGM_SYNC_CLEAR_PGM_POOL is set -> VINF_PGM_SYNC_CR3\n"));
2691	return VINF_PGM_SYNC_CR3;
2692	# endif
2693	}
2694	#endif
2695
2696	Assert(fGlobal \|\| (cr4 & X86_CR4_PGE));
2697	MY_STAM_COUNTER_INC(fGlobal ? &pVM->pgm.s.CTXMID(Stat,SyncCR3Global) : &pVM->pgm.s.CTXMID(Stat,SyncCR3NotGlobal));
2698
2699	#if PGM_GST_TYPE == PGM_TYPE_32BIT \|\| PGM_GST_TYPE == PGM_TYPE_PAE
2700	/*
2701	* Get page directory addresses.
2702	*/
2703	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2704	PX86PDE pPDEDst = &pVM->pgm.s.CTXMID(p,32BitPD)->a[0];
2705	# else /* PGM_SHW_TYPE == PGM_TYPE_PAE */
2706	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2707	PX86PDEPAE pPDEDst = &pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[0];
2708	# endif
2709	# endif
2710
2711	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2712	PGSTPD pPDSrc = CTXSUFF(pVM->pgm.s.pGuestPD);
2713	Assert(pPDSrc);
2714	# ifndef IN_GC
2715	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2716	# endif
2717	# endif
2718
2719	/*
2720	* Iterate the page directory.
2721	*/
2722	PPGMMAPPING pMapping;
2723	unsigned iPdNoMapping;
2724	const bool fRawR0Enabled = EMIsRawRing0Enabled(pVM);
2725	PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
2726
2727	/* Only check mappings if they are supposed to be put into the shadow page table. */
2728	if (pgmMapAreMappingsEnabled(&pVM->pgm.s))
2729	{
2730	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2731	iPdNoMapping = (pMapping) ? (pMapping->GCPtr >> GST_PD_SHIFT) : ~0U;
2732	}
2733	else
2734	{
2735	pMapping = 0;
2736	iPdNoMapping = ~0U;
2737	}
2738	# if PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2739	for (unsigned iPDPTE = 0; iPDPTE < GST_PDPE_ENTRIES; iPDPTE++)
2740	{
2741	unsigned iPDSrc;
2742	# if PGM_SHW_TYPE == PGM_TYPE_PAE
2743	PX86PDPAE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[0];
2744	# else
2745	AssertFailed(); /* @todo */
2746	PX86PDPE pPDPAE = pVM->pgm.s.CTXMID(ap,PaePDs)[iPDPTE * X86_PG_AMD64_ENTRIES];
2747	# endif
2748	PX86PDEPAE pPDEDst = &pPDPAE->a[iPDPTE * X86_PG_PAE_ENTRIES];
2749	PGSTPD pPDSrc = pgmGstGetPaePDPtr(&pVM->pgm.s, iPDPTE << X86_PDPT_SHIFT, &iPDSrc);
2750
2751	if (pPDSrc == NULL)
2752	{
2753	/* PDPT not present */
2754	if (pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present)
2755	{
2756	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2757	{
2758	if ( pPDEDst[iPD].n.u1Present
2759	&& !(pPDEDst[iPD].u & PGM_PDFLAGS_MAPPING))
2760	{
2761	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst[iPD].u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPDPTE * X86_PG_PAE_ENTRIES + iPD);
2762	pPDEDst[iPD].u = 0;
2763	}
2764	}
2765	}
2766	if (!(pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].u & PGM_PLXFLAGS_MAPPING))
2767	pVM->pgm.s.CTXMID(p,PaePDPT)->a[iPDPTE].n.u1Present = 0;
2768	continue;
2769	}
2770	# else /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2771	{
2772	# endif /* PGM_GST_TYPE != PGM_TYPE_PAE && PGM_GST_TYPE != PGM_TYPE_AMD64 */
2773	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2774	{
2775	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
2776	Assert(&pVM->pgm.s.CTXMID(p,32BitPD)->a[iPD] == pPDEDst);
2777	# elif PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2778	AssertMsg(&pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512] == pPDEDst, ("%p vs %p\n", &pVM->pgm.s.CTXMID(ap,PaePDs)[iPD * 2 / 512]->a[iPD * 2 % 512], pPDEDst));
2779	# endif
2780	register GSTPDE PdeSrc = pPDSrc->a[iPD];
2781	if ( PdeSrc.n.u1Present
2782	&& (PdeSrc.n.u1User \|\| fRawR0Enabled))
2783	{
2784	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2785	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
2786	&& !defined(PGM_WITHOUT_MAPPINGS)
2787
2788	/*
2789	* Check for conflicts with GC mappings.
2790	*/
2791	# if PGM_GST_TYPE == PGM_TYPE_PAE
2792	if (iPD + iPDPTE * X86_PG_PAE_ENTRIES == iPdNoMapping)
2793	# else
2794	if (iPD == iPdNoMapping)
2795	# endif
2796	{
2797	if (pVM->pgm.s.fMappingsFixed)
2798	{
2799	/* It's fixed, just skip the mapping. */
2800	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
2801	iPD += cPTs - 1;
2802	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
2803	pMapping = pMapping->CTXALLSUFF(pNext);
2804	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2805	continue;
2806	}
2807	# ifdef IN_RING3
2808	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2809	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
2810	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2811	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPDPTE << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
2812	# endif
2813	if (VBOX_FAILURE(rc))
2814	return rc;
2815
2816	/*
2817	* Update iPdNoMapping and pMapping.
2818	*/
2819	pMapping = pVM->pgm.s.pMappingsR3;
2820	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
2821	pMapping = pMapping->pNextR3;
2822	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2823	# else
2824	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2825	return VINF_PGM_SYNC_CR3;
2826	# endif
2827	}
2828	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
2829	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
2830	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
2831	/*
2832	* Sync page directory entry.
2833	*
2834	* The current approach is to allocated the page table but to set
2835	* the entry to not-present and postpone the page table synching till
2836	* it's actually used.
2837	*/
2838	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2839	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2840	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2841	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2842	# else
2843	const unsigned iPdShw = iPD; NOREF(iPdShw);
2844	# endif
2845	{
2846	SHWPDE PdeDst = *pPDEDst;
2847	if (PdeDst.n.u1Present)
2848	{
2849	PPGMPOOLPAGE pShwPage = pgmPoolGetPage(pPool, PdeDst.u & SHW_PDE_PG_MASK);
2850	RTGCPHYS GCPhys;
2851	if ( !PdeSrc.b.u1Size
2852	\|\| !(cr4 & X86_CR4_PSE))
2853	{
2854	GCPhys = PdeSrc.u & GST_PDE_PG_MASK;
2855	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2856	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
2857	GCPhys \|= i * (PAGE_SIZE / 2);
2858	# endif
2859	}
2860	else
2861	{
2862	GCPhys = PdeSrc.u & GST_PDE_BIG_PG_MASK;
2863	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2864	/* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
2865	GCPhys \|= i * X86_PAGE_2M_SIZE;
2866	# endif
2867	}
2868
2869	if ( pShwPage->GCPhys == GCPhys
2870	&& pShwPage->enmKind == PGM_BTH_NAME(CalcPageKind)(&PdeSrc, cr4)
2871	&& ( pShwPage->fCached
2872	\|\| ( !fGlobal
2873	&& ( false
2874	# ifdef PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
2875	\|\| ( (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2876	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE)) /* global 2/4MB page. */
2877	\|\| ( !pShwPage->fSeenNonGlobal
2878	&& (cr4 & X86_CR4_PGE))
2879	# endif
2880	)
2881	)
2882	)
2883	&& ( (PdeSrc.u & (X86_PDE_US \| X86_PDE_RW)) == (PdeDst.u & (X86_PDE_US \| X86_PDE_RW))
2884	\|\| ( (cr4 & X86_CR4_PSE)
2885	&& ((PdeSrc.u & (X86_PDE_US \| X86_PDE4M_PS \| X86_PDE4M_D)) \| PGM_PDFLAGS_TRACK_DIRTY)
2886	== ((PdeDst.u & (X86_PDE_US \| X86_PDE_RW \| PGM_PDFLAGS_TRACK_DIRTY)) \| X86_PDE4M_PS))
2887	)
2888	)
2889	{
2890	# ifdef VBOX_WITH_STATISTICS
2891	if ( !fGlobal
2892	&& (PdeSrc.u & (X86_PDE4M_PS \| X86_PDE4M_G)) == (X86_PDE4M_PS \| X86_PDE4M_G)
2893	&& (cr4 & (X86_CR4_PGE \| X86_CR4_PSE)) == (X86_CR4_PGE \| X86_CR4_PSE))
2894	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPD));
2895	else if (!fGlobal && !pShwPage->fSeenNonGlobal && (cr4 & X86_CR4_PGE))
2896	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstSkippedGlobalPT));
2897	else
2898	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstCacheHit));
2899	# endif /* VBOX_WITH_STATISTICS */
2900	/** @todo a replacement strategy isn't really needed unless we're using a very small pool < 512 pages.
2901	* The whole ageing stuff should be put in yet another set of #ifdefs. For now, let's just skip it. */
2902	//# ifdef PGMPOOL_WITH_CACHE
2903	// pgmPoolCacheUsed(pPool, pShwPage);
2904	//# endif
2905	}
2906	else
2907	{
2908	pgmPoolFreeByPage(pPool, pShwPage, SHW_POOL_ROOT_IDX, iPdShw);
2909	pPDEDst->u = 0;
2910	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreed));
2911	}
2912	}
2913	else
2914	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstNotPresent));
2915	pPDEDst++;
2916	}
2917	}
2918	# if PGM_GST_TYPE == PGM_TYPE_PAE
2919	else if (iPD + iPDPTE * X86_PG_PAE_ENTRIES != iPdNoMapping)
2920	# else
2921	else if (iPD != iPdNoMapping)
2922	# endif
2923	{
2924	/*
2925	* Check if there is any page directory to mark not present here.
2926	*/
2927	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
2928	for (unsigned i = 0, iPdShw = iPD * 2; i < 2; i++, iPdShw++) /* pray that the compiler unrolls this */
2929	# elif PGM_GST_TYPE == PGM_TYPE_PAE \|\| PGM_GST_TYPE == PGM_TYPE_AMD64
2930	const unsigned iPdShw = iPD + iPDPTE * X86_PG_PAE_ENTRIES; NOREF(iPdShw);
2931	# else
2932	const unsigned iPdShw = iPD; NOREF(iPdShw);
2933	# endif
2934	{
2935	if (pPDEDst->n.u1Present)
2936	{
2937	pgmPoolFreeByPage(pPool, pgmPoolGetPage(pPool, pPDEDst->u & SHW_PDE_PG_MASK), SHW_POOL_ROOT_IDX, iPdShw);
2938	pPDEDst->u = 0;
2939	MY_STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,SyncCR3DstFreedSrcNP));
2940	}
2941	pPDEDst++;
2942	}
2943	}
2944	else
2945	{
2946	# if ( PGM_GST_TYPE == PGM_TYPE_32BIT \
2947	\|\| PGM_GST_TYPE == PGM_TYPE_PAE) \
2948	&& !defined(PGM_WITHOUT_MAPPINGS)
2949
2950	const unsigned cPTs = pMapping->cb >> GST_PD_SHIFT;
2951
2952	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
2953	if (pVM->pgm.s.fMappingsFixed)
2954	{
2955	/* It's fixed, just skip the mapping. */
2956	pMapping = pMapping->CTXALLSUFF(pNext);
2957	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2958	}
2959	else
2960	{
2961	/*
2962	* Check for conflicts for subsequent pagetables
2963	* and advance to the next mapping.
2964	*/
2965	iPdNoMapping = ~0U;
2966	unsigned iPT = cPTs;
2967	while (iPT-- > 1)
2968	{
2969	if ( pPDSrc->a[iPD + iPT].n.u1Present
2970	&& (pPDSrc->a[iPD + iPT].n.u1User \|\| fRawR0Enabled))
2971	{
2972	# ifdef IN_RING3
2973	# if PGM_GST_TYPE == PGM_TYPE_32BIT
2974	int rc = pgmR3SyncPTResolveConflict(pVM, pMapping, pPDSrc, iPD << GST_PD_SHIFT);
2975	# elif PGM_GST_TYPE == PGM_TYPE_PAE
2976	int rc = pgmR3SyncPTResolveConflictPAE(pVM, pMapping, (iPDPTE << GST_PDPT_SHIFT) + (iPD << GST_PD_SHIFT));
2977	# endif
2978	if (VBOX_FAILURE(rc))
2979	return rc;
2980
2981	/*
2982	* Update iPdNoMapping and pMapping.
2983	*/
2984	pMapping = pVM->pgm.s.CTXALLSUFF(pMappings);
2985	while (pMapping && pMapping->GCPtr < (iPD << GST_PD_SHIFT))
2986	pMapping = pMapping->CTXALLSUFF(pNext);
2987	iPdNoMapping = pMapping ? pMapping->GCPtr >> GST_PD_SHIFT : ~0U;
2988	break;
2989	# else
2990	LogFlow(("SyncCR3: detected conflict -> VINF_PGM_SYNC_CR3\n"));
2991	return VINF_PGM_SYNC_CR3;
2992	# endif
2993	}
2994	}
2995	if (iPdNoMapping == ~0U && pMapping)
2996	{
2997	pMapping = pMapping->CTXALLSUFF(pNext);
2998	if (pMapping)
2999	iPdNoMapping = pMapping->GCPtr >> GST_PD_SHIFT;
3000	}
3001	}
3002
3003	/* advance. */
3004	iPD += cPTs - 1;
3005	pPDEDst += cPTs + (PGM_GST_TYPE != PGM_SHW_TYPE) * cPTs; /* Only applies to the pae shadow and 32 bits guest case */
3006	# if PGM_GST_TYPE != PGM_SHW_TYPE
3007	AssertCompile(PGM_GST_TYPE == PGM_TYPE_32BIT && PGM_SHW_TYPE == PGM_TYPE_PAE);
3008	# endif
3009	# else /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3010	Assert(!pgmMapAreMappingsEnabled(&pVM->pgm.s));
3011	# endif /* (PGM_GST_TYPE != PGM_TYPE_32BIT && PGM_GST_TYPE != PGM_TYPE_PAE) \|\| PGM_WITHOUT_MAPPINGS */
3012	}
3013
3014	} /* for iPD */
3015	} /* for each PDPTE (PAE) */
3016
3017	return VINF_SUCCESS;
3018
3019	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3020	//# error not implemented
3021	return VERR_INTERNAL_ERROR;
3022	#else /* guest real and protected mode */
3023	return VINF_SUCCESS;
3024	#endif
3025	}
3026
3027
3028
3029
3030	#ifdef VBOX_STRICT
3031	#ifdef IN_GC
3032	# undef AssertMsgFailed
3033	# define AssertMsgFailed Log
3034	#endif
3035	#ifdef IN_RING3
3036	# include <VBox/dbgf.h>
3037
3038	/**
3039	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3040	*
3041	* @returns VBox status code (VINF_SUCCESS).
3042	* @param pVM The VM handle.
3043	* @param cr3 The root of the hierarchy.
3044	* @param crr The cr4, only PAE and PSE is currently used.
3045	* @param fLongMode Set if long mode, false if not long mode.
3046	* @param cMaxDepth Number of levels to dump.
3047	* @param pHlp Pointer to the output functions.
3048	*/
3049	__BEGIN_DECLS
3050	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp);
3051	__END_DECLS
3052
3053	#endif
3054
3055	/**
3056	* Checks that the shadow page table is in sync with the guest one.
3057	*
3058	* @returns The number of errors.
3059	* @param pVM The virtual machine.
3060	* @param cr3 Guest context CR3 register
3061	* @param cr4 Guest context CR4 register
3062	* @param GCPtr Where to start. Defaults to 0.
3063	* @param cb How much to check. Defaults to everything.
3064	*/
3065	PGM_BTH_DECL(unsigned, AssertCR3)(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCUINTPTR GCPtr, RTGCUINTPTR cb)
3066	{
3067	unsigned cErrors = 0;
3068
3069	#if PGM_GST_TYPE == PGM_TYPE_32BIT \
3070	\|\| PGM_GST_TYPE == PGM_TYPE_PAE
3071
3072	PPGM pPGM = &pVM->pgm.s;
3073	RTGCPHYS GCPhysGst; /* page address derived from the guest page tables. */
3074	RTHCPHYS HCPhysShw; /* page address derived from the shadow page tables. */
3075	# ifndef IN_RING0
3076	RTHCPHYS HCPhys; /* general usage. */
3077	# endif
3078	int rc;
3079
3080	/*
3081	* Check that the Guest CR3 and all its mappings are correct.
3082	*/
3083	AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
3084	("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
3085	false);
3086	# ifndef IN_RING0
3087	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3088	rc = PGMShwGetPage(pVM, pPGM->pGuestPDGC, NULL, &HCPhysShw);
3089	# else
3090	rc = PGMShwGetPage(pVM, pPGM->pGstPaePDPTGC, NULL, &HCPhysShw);
3091	# endif
3092	AssertRCReturn(rc, 1);
3093	HCPhys = NIL_RTHCPHYS;
3094	rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
3095	AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
3096	# if PGM_GST_TYPE == PGM_TYPE_32BIT && defined(IN_RING3)
3097	RTGCPHYS GCPhys;
3098	rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
3099	AssertRCReturn(rc, 1);
3100	AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
3101	# endif
3102	#endif /* !IN_RING0 */
3103
3104	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3105	const GSTPD *pPDSrc = CTXSUFF(pPGM->pGuestPD);
3106	# endif
3107
3108	/*
3109	* Get and check the Shadow CR3.
3110	*/
3111	# if PGM_SHW_TYPE == PGM_TYPE_32BIT
3112	const X86PD *pPDDst = pPGM->CTXMID(p,32BitPD);
3113	unsigned cPDEs = ELEMENTS(pPDDst->a);
3114	# else
3115	const X86PDPAE pPDDst = pPGM->CTXMID(ap,PaePDs[0]); / use it as a 2048 entry PD */
3116	unsigned cPDEs = ELEMENTS(pPDDst->a) * ELEMENTS(pPGM->apHCPaePDs);
3117	# endif
3118	if (cb != ~(RTGCUINTPTR)0)
3119	cPDEs = RT_MIN(cb >> SHW_PD_SHIFT, 1);
3120
3121	/** @todo call the other two PGMAssert() functions. /
3122
3123	# if PGM_GST_TYPE == PGM_TYPE_PAE
3124	/*
3125	* Check the 4 PDPTs too.
3126	*/
3127	for (unsigned i = 0; i < 4; i++)
3128	{
3129	RTHCPTR HCPtr;
3130	RTHCPHYS HCPhys;
3131	RTGCPHYS GCPhys = pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[i].u & X86_PDPE_PG_MASK;
3132	int rc2 = pgmRamGCPhys2HCPtrAndHCPhysWithFlags(&pVM->pgm.s, GCPhys, &HCPtr, &HCPhys);
3133	if (VBOX_SUCCESS(rc2))
3134	{
3135	AssertMsg( pVM->pgm.s.apGstPaePDsHC[i] == (R3R0PTRTYPE(PX86PDPAE))HCPtr
3136	&& pVM->pgm.s.aGCPhysGstPaePDs[i] == GCPhys,
3137	("idx %d apGstPaePDsHC %VHv vs %VHv aGCPhysGstPaePDs %VGp vs %VGp\n",
3138	i, pVM->pgm.s.apGstPaePDsHC[i], HCPtr, pVM->pgm.s.aGCPhysGstPaePDs[i], GCPhys));
3139	}
3140	}
3141	# endif
3142
3143	/*
3144	* Iterate the shadow page directory.
3145	*/
3146	GCPtr = (GCPtr >> SHW_PD_SHIFT) << SHW_PD_SHIFT;
3147	unsigned iPDDst = GCPtr >> SHW_PD_SHIFT;
3148	cPDEs += iPDDst;
3149	for (;
3150	iPDDst < cPDEs;
3151	iPDDst++, GCPtr += _4G / cPDEs)
3152	{
3153	# if PGM_GST_TYPE == PGM_TYPE_PAE
3154	uint32_t iPDSrc;
3155	PGSTPD pPDSrc = pgmGstGetPaePDPtr(pPGM, (RTGCUINTPTR)GCPtr, &iPDSrc);
3156	if (!pPDSrc)
3157	{
3158	AssertMsg(!pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].n.u1Present, ("Guest PDTPR not present, shadow PDPTR %VX64\n", pVM->pgm.s.CTXSUFF(pGstPaePDPT)->a[(GCPtr >> GST_PDPT_SHIFT) & GST_PDPT_MASK].u));
3159	continue;
3160	}
3161	#endif
3162
3163	const SHWPDE PdeDst = pPDDst->a[iPDDst];
3164	if (PdeDst.u & PGM_PDFLAGS_MAPPING)
3165	{
3166	Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
3167	if ((PdeDst.u & X86_PDE_AVL_MASK) != PGM_PDFLAGS_MAPPING)
3168	{
3169	AssertMsgFailed(("Mapping shall only have PGM_PDFLAGS_MAPPING set! PdeDst.u=%#RX64\n", (uint64_t)PdeDst.u));
3170	cErrors++;
3171	continue;
3172	}
3173	}
3174	else if ( (PdeDst.u & X86_PDE_P)
3175	\|\| ((PdeDst.u & (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY)) == (X86_PDE_P \| PGM_PDFLAGS_TRACK_DIRTY))
3176	)
3177	{
3178	HCPhysShw = PdeDst.u & SHW_PDE_PG_MASK;
3179	PPGMPOOLPAGE pPoolPage = pgmPoolGetPageByHCPhys(pVM, HCPhysShw);
3180	if (!pPoolPage)
3181	{
3182	AssertMsgFailed(("Invalid page table address %VGp at %VGv! PdeDst=%#RX64\n",
3183	HCPhysShw, GCPtr, (uint64_t)PdeDst.u));
3184	cErrors++;
3185	continue;
3186	}
3187	const SHWPT pPTDst = (const SHWPT )PGMPOOL_PAGE_2_PTR(pVM, pPoolPage);
3188
3189	if (PdeDst.u & (X86_PDE4M_PWT \| X86_PDE4M_PCD))
3190	{
3191	AssertMsgFailed(("PDE flags PWT and/or PCD is set at %VGv! These flags are not virtualized! PdeDst=%#RX64\n",
3192	GCPtr, (uint64_t)PdeDst.u));
3193	cErrors++;
3194	}
3195
3196	if (PdeDst.u & (X86_PDE4M_G \| X86_PDE4M_D))
3197	{
3198	AssertMsgFailed(("4K PDE reserved flags at %VGv! PdeDst=%#RX64\n",
3199	GCPtr, (uint64_t)PdeDst.u));
3200	cErrors++;
3201	}
3202
3203	const GSTPDE PdeSrc = pPDSrc->a[(iPDDst >> (GST_PD_SHIFT - SHW_PD_SHIFT)) & GST_PD_MASK];
3204	if (!PdeSrc.n.u1Present)
3205	{
3206	AssertMsgFailed(("Guest PDE at %VGv is not present! PdeDst=%#RX64 PdeSrc=%#RX64\n",
3207	GCPtr, (uint64_t)PdeDst.u, (uint64_t)PdeSrc.u));
3208	cErrors++;
3209	continue;
3210	}
3211
3212	if ( !PdeSrc.b.u1Size
3213	\|\| !(cr4 & X86_CR4_PSE))
3214	{
3215	GCPhysGst = PdeSrc.u & GST_PDE_PG_MASK;
3216	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3217	GCPhysGst \|= (iPDDst & 1) * (PAGE_SIZE / 2);
3218	# endif
3219	}
3220	else
3221	{
3222	# if PGM_GST_TYPE == PGM_TYPE_32BIT
3223	if (PdeSrc.u & X86_PDE4M_PG_HIGH_MASK)
3224	{
3225	AssertMsgFailed(("Guest PDE at %VGv is using PSE36 or similar! PdeSrc=%#RX64\n",
3226	GCPtr, (uint64_t)PdeSrc.u));
3227	cErrors++;
3228	continue;
3229	}
3230	# endif
3231	GCPhysGst = PdeSrc.u & GST_PDE_BIG_PG_MASK;
3232	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3233	GCPhysGst \|= GCPtr & RT_BIT(X86_PAGE_2M_SHIFT);
3234	# endif
3235	}
3236
3237	if ( pPoolPage->enmKind
3238	!= (!PdeSrc.b.u1Size \|\| !(cr4 & X86_CR4_PSE) ? BTH_PGMPOOLKIND_PT_FOR_PT : BTH_PGMPOOLKIND_PT_FOR_BIG))
3239	{
3240	AssertMsgFailed(("Invalid shadow page table kind %d at %VGv! PdeSrc=%#RX64\n",
3241	pPoolPage->enmKind, GCPtr, (uint64_t)PdeSrc.u));
3242	cErrors++;
3243	}
3244
3245	PPGMPAGE pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3246	if (!pPhysPage)
3247	{
3248	AssertMsgFailed(("Cannot find guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3249	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3250	cErrors++;
3251	continue;
3252	}
3253
3254	if (GCPhysGst != pPoolPage->GCPhys)
3255	{
3256	AssertMsgFailed(("GCPhysGst=%VGp != pPage->GCPhys=%VGp at %VGv\n",
3257	GCPhysGst, pPoolPage->GCPhys, GCPtr));
3258	cErrors++;
3259	continue;
3260	}
3261
3262	if ( !PdeSrc.b.u1Size
3263	\|\| !(cr4 & X86_CR4_PSE))
3264	{
3265	/*
3266	* Page Table.
3267	*/
3268	const GSTPT *pPTSrc;
3269	rc = PGM_GCPHYS_2_PTR(pVM, GCPhysGst & ~(RTGCPHYS)(PAGE_SIZE - 1), &pPTSrc);
3270	if (VBOX_FAILURE(rc))
3271	{
3272	AssertMsgFailed(("Cannot map/convert guest physical address %VGp in the PDE at %VGv! PdeSrc=%#RX64\n",
3273	GCPhysGst, GCPtr, (uint64_t)PdeSrc.u));
3274	cErrors++;
3275	continue;
3276	}
3277	if ( (PdeSrc.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/))
3278	!= (PdeDst.u & (X86_PDE_P \| X86_PDE_US \| X86_PDE_RW/* \| X86_PDE_A*/)))
3279	{
3280	/// @todo We get here a lot on out-of-sync CR3 entries. The access handler should zap them to avoid false alarms here!
3281	// (This problem will go away when/if we shadow multiple CR3s.)
3282	AssertMsgFailed(("4K PDE flags mismatch at %VGv! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3283	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3284	cErrors++;
3285	continue;
3286	}
3287	if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3288	{
3289	AssertMsgFailed(("4K PDEs cannot have PGM_PDFLAGS_TRACK_DIRTY set! GCPtr=%VGv PdeDst=%#RX64\n",
3290	GCPtr, (uint64_t)PdeDst.u));
3291	cErrors++;
3292	continue;
3293	}
3294
3295	/* iterate the page table. */
3296	# if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
3297	/* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
3298	const unsigned offPTSrc = ((GCPtr >> SHW_PD_SHIFT) & 1) * 512;
3299	# else
3300	const unsigned offPTSrc = 0;
3301	# endif
3302	for (unsigned iPT = 0, off = 0;
3303	iPT < ELEMENTS(pPTDst->a);
3304	iPT++, off += PAGE_SIZE)
3305	{
3306	const SHWPTE PteDst = pPTDst->a[iPT];
3307
3308	/* skip not-present entries. */
3309	if (!(PteDst.u & (X86_PTE_P \| PGM_PTFLAGS_TRACK_DIRTY))) /** @todo deal with ALL handlers and CSAM !P pages! */
3310	continue;
3311	Assert(PteDst.n.u1Present);
3312
3313	const GSTPTE PteSrc = pPTSrc->a[iPT + offPTSrc];
3314	if (!PteSrc.n.u1Present)
3315	{
3316	#ifdef IN_RING3
3317	PGMAssertHandlerAndFlagsInSync(pVM);
3318	PGMR3DumpHierarchyGC(pVM, cr3, cr4, (PdeSrc.u & GST_PDE_PG_MASK));
3319	#endif
3320	AssertMsgFailed(("Out of sync (!P) PTE at %VGv! PteSrc=%#RX64 PteDst=%#RX64 pPTSrc=%VGv iPTSrc=%x PdeSrc=%x physpte=%VGp\n",
3321	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u, pPTSrc, iPT + offPTSrc, PdeSrc.au32[0],
3322	(PdeSrc.u & GST_PDE_PG_MASK) + (iPT + offPTSrc)*sizeof(PteSrc)));
3323	cErrors++;
3324	continue;
3325	}
3326
3327	uint64_t fIgnoreFlags = GST_PTE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_G \| X86_PTE_D \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3328	# if 1 /** @todo sync accessed bit properly... */
3329	fIgnoreFlags \|= X86_PTE_A;
3330	# endif
3331
3332	/* match the physical addresses */
3333	HCPhysShw = PteDst.u & SHW_PTE_PG_MASK;
3334	GCPhysGst = PteSrc.u & GST_PTE_PG_MASK;
3335
3336	# ifdef IN_RING3
3337	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3338	if (VBOX_FAILURE(rc))
3339	{
3340	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3341	{
3342	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3343	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3344	cErrors++;
3345	continue;
3346	}
3347	}
3348	else if (HCPhysShw != (HCPhys & SHW_PTE_PG_MASK))
3349	{
3350	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3351	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3352	cErrors++;
3353	continue;
3354	}
3355	# endif
3356
3357	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3358	if (!pPhysPage)
3359	{
3360	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3361	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3362	{
3363	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PteSrc=%#RX64 PteDst=%#RX64\n",
3364	GCPhysGst, GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3365	cErrors++;
3366	continue;
3367	}
3368	# endif
3369	if (PteDst.n.u1Write)
3370	{
3371	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3372	GCPtr + off, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3373	cErrors++;
3374	}
3375	fIgnoreFlags \|= X86_PTE_RW;
3376	}
3377	else if (HCPhysShw != (PGM_PAGE_GET_HCPHYS(pPhysPage) & SHW_PTE_PG_MASK))
3378	{
3379	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PteSrc=%#RX64 PteDst=%#RX64\n",
3380	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3381	cErrors++;
3382	continue;
3383	}
3384
3385	/* flags */
3386	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3387	{
3388	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3389	{
3390	if (PteDst.n.u1Write)
3391	{
3392	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PteSrc=%#RX64 PteDst=%#RX64\n",
3393	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3394	cErrors++;
3395	continue;
3396	}
3397	fIgnoreFlags \|= X86_PTE_RW;
3398	}
3399	else
3400	{
3401	if (PteDst.n.u1Present)
3402	{
3403	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VHp PteSrc=%#RX64 PteDst=%#RX64\n",
3404	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3405	cErrors++;
3406	continue;
3407	}
3408	fIgnoreFlags \|= X86_PTE_P;
3409	}
3410	}
3411	else
3412	{
3413	if (!PteSrc.n.u1Dirty && PteSrc.n.u1Write)
3414	{
3415	if (PteDst.n.u1Write)
3416	{
3417	AssertMsgFailed(("!DIRTY page at %VGv is writable! PteSrc=%#RX64 PteDst=%#RX64\n",
3418	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3419	cErrors++;
3420	continue;
3421	}
3422	if (!(PteDst.u & PGM_PTFLAGS_TRACK_DIRTY))
3423	{
3424	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3425	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3426	cErrors++;
3427	continue;
3428	}
3429	if (PteDst.n.u1Dirty)
3430	{
3431	AssertMsgFailed(("!DIRTY page at %VGv is marked DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3432	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3433	cErrors++;
3434	}
3435	# if 0 /** @todo sync access bit properly... */
3436	if (PteDst.n.u1Accessed != PteSrc.n.u1Accessed)
3437	{
3438	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3439	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3440	cErrors++;
3441	}
3442	fIgnoreFlags \|= X86_PTE_RW;
3443	# else
3444	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3445	# endif
3446	}
3447	else if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3448	{
3449	/* access bit emulation (not implemented). */
3450	if (PteSrc.n.u1Accessed \|\| PteDst.n.u1Present)
3451	{
3452	AssertMsgFailed(("PGM_PTFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PteSrc=%#RX64 PteDst=%#RX64\n",
3453	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3454	cErrors++;
3455	continue;
3456	}
3457	if (!PteDst.n.u1Accessed)
3458	{
3459	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PteSrc=%#RX64 PteDst=%#RX64\n",
3460	GCPtr + off, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3461	cErrors++;
3462	}
3463	fIgnoreFlags \|= X86_PTE_P;
3464	}
3465	# ifdef DEBUG_sandervl
3466	fIgnoreFlags \|= X86_PTE_D \| X86_PTE_A;
3467	# endif
3468	}
3469
3470	if ( (PteSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3471	&& (PteSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags)
3472	)
3473	{
3474	AssertMsgFailed(("Flags mismatch at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PteSrc=%#RX64 PteDst=%#RX64\n",
3475	GCPtr + off, (uint64_t)PteSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3476	fIgnoreFlags, (uint64_t)PteSrc.u, (uint64_t)PteDst.u));
3477	cErrors++;
3478	continue;
3479	}
3480	} /* foreach PTE */
3481	}
3482	else
3483	{
3484	/*
3485	* Big Page.
3486	*/
3487	uint64_t fIgnoreFlags = X86_PDE_AVL_MASK \| GST_PDE_PG_MASK \| X86_PDE4M_G \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_PWT \| X86_PDE4M_PCD;
3488	if (!PdeSrc.b.u1Dirty && PdeSrc.b.u1Write)
3489	{
3490	if (PdeDst.n.u1Write)
3491	{
3492	AssertMsgFailed(("!DIRTY page at %VGv is writable! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3493	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3494	cErrors++;
3495	continue;
3496	}
3497	if (!(PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY))
3498	{
3499	AssertMsgFailed(("!DIRTY page at %VGv is not marked TRACK_DIRTY! PteSrc=%#RX64 PteDst=%#RX64\n",
3500	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3501	cErrors++;
3502	continue;
3503	}
3504	# if 0 /** @todo sync access bit properly... */
3505	if (PdeDst.n.u1Accessed != PdeSrc.b.u1Accessed)
3506	{
3507	AssertMsgFailed(("!DIRTY page at %VGv is has mismatching accessed bit! PteSrc=%#RX64 PteDst=%#RX64\n",
3508	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3509	cErrors++;
3510	}
3511	fIgnoreFlags \|= X86_PTE_RW;
3512	# else
3513	fIgnoreFlags \|= X86_PTE_RW \| X86_PTE_A;
3514	# endif
3515	}
3516	else if (PdeDst.u & PGM_PDFLAGS_TRACK_DIRTY)
3517	{
3518	/* access bit emulation (not implemented). */
3519	if (PdeSrc.b.u1Accessed \|\| PdeDst.n.u1Present)
3520	{
3521	AssertMsgFailed(("PGM_PDFLAGS_TRACK_DIRTY set at %VGv but no accessed bit emulation! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3522	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3523	cErrors++;
3524	continue;
3525	}
3526	if (!PdeDst.n.u1Accessed)
3527	{
3528	AssertMsgFailed(("!ACCESSED page at %VGv is has the accessed bit set! PdeSrc=%#RX64 PdeDst=%#RX64\n",
3529	GCPtr, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3530	cErrors++;
3531	}
3532	fIgnoreFlags \|= X86_PTE_P;
3533	}
3534
3535	if ((PdeSrc.u & ~fIgnoreFlags) != (PdeDst.u & ~fIgnoreFlags))
3536	{
3537	AssertMsgFailed(("Flags mismatch (B) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PdeDst=%#RX64\n",
3538	GCPtr, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PdeDst.u & ~fIgnoreFlags,
3539	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PdeDst.u));
3540	cErrors++;
3541	}
3542
3543	/* iterate the page table. */
3544	for (unsigned iPT = 0, off = 0;
3545	iPT < ELEMENTS(pPTDst->a);
3546	iPT++, off += PAGE_SIZE, GCPhysGst += PAGE_SIZE)
3547	{
3548	const SHWPTE PteDst = pPTDst->a[iPT];
3549
3550	if (PteDst.u & PGM_PTFLAGS_TRACK_DIRTY)
3551	{
3552	AssertMsgFailed(("The PTE at %VGv emulating a 2/4M page is marked TRACK_DIRTY! PdeSrc=%#RX64 PteDst=%#RX64\n",
3553	GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3554	cErrors++;
3555	}
3556
3557	/* skip not-present entries. */
3558	if (!PteDst.n.u1Present) /** @todo deal with ALL handlers and CSAM !P pages! */
3559	continue;
3560
3561	fIgnoreFlags = X86_PTE_PAE_PG_MASK \| X86_PTE_AVL_MASK \| X86_PTE_PWT \| X86_PTE_PCD \| X86_PTE_PAT;
3562
3563	/* match the physical addresses */
3564	HCPhysShw = PteDst.u & X86_PTE_PAE_PG_MASK;
3565
3566	# ifdef IN_RING3
3567	rc = PGMPhysGCPhys2HCPhys(pVM, GCPhysGst, &HCPhys);
3568	if (VBOX_FAILURE(rc))
3569	{
3570	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3571	{
3572	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3573	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3574	cErrors++;
3575	}
3576	}
3577	else if (HCPhysShw != (HCPhys & X86_PTE_PAE_PG_MASK))
3578	{
3579	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3580	GCPtr + off, HCPhysShw, HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3581	cErrors++;
3582	continue;
3583	}
3584	# endif
3585
3586	pPhysPage = pgmPhysGetPage(pPGM, GCPhysGst);
3587	if (!pPhysPage)
3588	{
3589	# ifdef IN_RING3 /** @todo make MMR3PageDummyHCPhys an 'All' function! */
3590	if (HCPhysShw != MMR3PageDummyHCPhys(pVM))
3591	{
3592	AssertMsgFailed(("Cannot find guest physical address %VGp at %VGv! PdeSrc=%#RX64 PteDst=%#RX64\n",
3593	GCPhysGst, GCPtr + off, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3594	cErrors++;
3595	continue;
3596	}
3597	# endif
3598	if (PteDst.n.u1Write)
3599	{
3600	AssertMsgFailed(("Invalid guest page at %VGv is writable! GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3601	GCPtr + off, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3602	cErrors++;
3603	}
3604	fIgnoreFlags \|= X86_PTE_RW;
3605	}
3606	else if (HCPhysShw != (pPhysPage->HCPhys & X86_PTE_PAE_PG_MASK))
3607	{
3608	AssertMsgFailed(("Out of sync (phys) at %VGv! HCPhysShw=%VHp HCPhys=%VHp GCPhysGst=%VGp PdeSrc=%#RX64 PteDst=%#RX64\n",
3609	GCPtr + off, HCPhysShw, pPhysPage->HCPhys, GCPhysGst, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3610	cErrors++;
3611	continue;
3612	}
3613
3614	/* flags */
3615	if (PGM_PAGE_HAS_ACTIVE_HANDLERS(pPhysPage))
3616	{
3617	if (!PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPhysPage))
3618	{
3619	if (PGM_PAGE_GET_HNDL_PHYS_STATE(pPhysPage) != PGM_PAGE_HNDL_PHYS_STATE_DISABLED)
3620	{
3621	if (PteDst.n.u1Write)
3622	{
3623	AssertMsgFailed(("WRITE access flagged at %VGv but the page is writable! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3624	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3625	cErrors++;
3626	continue;
3627	}
3628	fIgnoreFlags \|= X86_PTE_RW;
3629	}
3630	}
3631	else
3632	{
3633	if (PteDst.n.u1Present)
3634	{
3635	AssertMsgFailed(("ALL access flagged at %VGv but the page is present! HCPhys=%VGv PdeSrc=%#RX64 PteDst=%#RX64\n",
3636	GCPtr + off, pPhysPage->HCPhys, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3637	cErrors++;
3638	continue;
3639	}
3640	fIgnoreFlags \|= X86_PTE_P;
3641	}
3642	}
3643
3644	if ( (PdeSrc.u & ~fIgnoreFlags) != (PteDst.u & ~fIgnoreFlags)
3645	&& (PdeSrc.u & ~(fIgnoreFlags \| X86_PTE_RW)) != (PteDst.u & ~fIgnoreFlags) /* lazy phys handler dereg. */
3646	)
3647	{
3648	AssertMsgFailed(("Flags mismatch (BT) at %VGv! %#RX64 != %#RX64 fIgnoreFlags=%#RX64 PdeSrc=%#RX64 PteDst=%#RX64\n",
3649	GCPtr + off, (uint64_t)PdeSrc.u & ~fIgnoreFlags, (uint64_t)PteDst.u & ~fIgnoreFlags,
3650	fIgnoreFlags, (uint64_t)PdeSrc.u, (uint64_t)PteDst.u));
3651	cErrors++;
3652	continue;
3653	}
3654	} /* foreach PTE */
3655	}
3656	}
3657	/* not present */
3658
3659	} /* forearch PDE */
3660
3661	# ifdef DEBUG
3662	if (cErrors)
3663	LogFlow(("AssertCR3: cErrors=%d\n", cErrors));
3664	# endif
3665
3666	#elif PGM_GST_TYPE == PGM_TYPE_PAE
3667	//# error not implemented
3668
3669
3670	#elif PGM_GST_TYPE == PGM_TYPE_AMD64
3671	//# error not implemented
3672
3673	/#else: guest real and protected mode /
3674	#endif
3675	return cErrors;
3676	}
3677	#endif /* VBOX_STRICT */
3678

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source: vbox/trunk/src/VBox/VMM/VMMAll/PGMAllBth.h@ 8533

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